mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
1176 lines
33 KiB
NASM
1176 lines
33 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 May 2010 Time:20:03:34
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no ini_VECT.c
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; In-file : ini_VECT.c
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; Asm-file : inter_asm\ini_VECT.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 0115H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, ini_VECT.c
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$DGS MOD_NAM, ini_VECT, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT10, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT1C, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT24, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT2A, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT34, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT4A, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT5A, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@VECT62, U, U, 00H, 078H, 00H, 00H
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$DGS GLV_SYM, _fn_intwdti, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 025H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intwdti, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 04BH, 00H, 01FH
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$DGS BEG_BLK, ??bb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intwdti, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intlvi, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 02FH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intlvi, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 052H, 00H, 029H
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$DGS BEG_BLK, ??bb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intlvi, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intp0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 039H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intp0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 059H, 00H, 033H
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$DGS BEG_BLK, ??bb00_fn_intp0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intp0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intp0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intp1, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 043H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intp1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 061H, 00H, 03DH
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$DGS BEG_BLK, ??bb00_fn_intp1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intp1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intp1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intp2, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 04DH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intp2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 068H, 00H, 047H
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$DGS BEG_BLK, ??bb00_fn_intp2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intp2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intp2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intp3, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intp3, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 06FH, 00H, 051H
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$DGS BEG_BLK, ??bb00_fn_intp3, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intp3, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intp3, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _intp21_RFTx, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 061H, 00H, 00H
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$DGS BEG_FUN, ??bf_intp21_RFTx, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 078H, 00H, 05BH
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$DGS BEG_BLK, ??bb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_intp21_RFTx, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intcmp0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intcmp0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 087H, 00H, 065H
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$DGS BEG_BLK, ??bb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intcmp0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intcmp1, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intcmp1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 08EH, 00H, 06FH
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$DGS BEG_BLK, ??bb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intcmp1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intdma0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intdma0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 095H, 00H, 079H
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$DGS BEG_BLK, ??bb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intdma0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intst0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 089H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intst0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 09FH, 00H, 083H
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$DGS BEG_BLK, ??bb00_fn_intst0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intst0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intst0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intsr0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intsr0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0A8H, 00H, 08DH
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$DGS BEG_BLK, ??bb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intsr0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intsre0, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 09DH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intsre0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0B1H, 00H, 097H
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$DGS BEG_BLK, ??bb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intsre0, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intst1, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0A7H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intst1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0B9H, 00H, 0A1H
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$DGS BEG_BLK, ??bb00_fn_intst1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intst1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intst1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intsr1, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0B1H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intsr1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0C3H, 00H, 0ABH
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$DGS BEG_BLK, ??bb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intsr1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intsre1, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0BBH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intsre1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0CAH, 00H, 0B5H
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$DGS BEG_BLK, ??bb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intsre1, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_inttm01, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0C5H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_inttm01, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0D4H, 00H, 0BFH
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$DGS BEG_BLK, ??bb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_inttm01, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_inttm02, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0CFH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_inttm02, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0DCH, 00H, 0C9H
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$DGS BEG_BLK, ??bb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_inttm02, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_inttm03, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0D9H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_inttm03, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0E3H, 00H, 0D3H
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$DGS BEG_BLK, ??bb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_inttm03, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intrtc, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0E3H, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intrtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0ECH, 00H, 0DDH
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$DGS BEG_BLK, ??bb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05H
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$DGS END_FUN, ??ef_fn_intrtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS GLV_SYM, _fn_intmd, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0EDH, 00H, 00H
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$DGS BEG_FUN, ??bf_fn_intmd, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0F6H, 00H, 0E7H
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$DGS BEG_BLK, ??bb00_fn_intmd, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_BEG, 03H, 00H, 00H
|
||
$DGS END_BLK, ??eb00_fn_intmd, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_END, 05H
|
||
$DGS END_FUN, ??ef_fn_intmd, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_END, 06H
|
||
$DGS GLV_SYM, _fn_inttm04, U, U, 0E001H, 026H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 0F7H, 00H, 00H
|
||
$DGS BEG_FUN, ??bf_fn_inttm04, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_BEG, 0FEH, 00H, 0F1H
|
||
$DGS BEG_BLK, ??bb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_BEG, 03H, 00H, 00H
|
||
$DGS END_BLK, ??eb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_END, 05H
|
||
$DGS END_FUN, ??ef_fn_inttm04, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_END, 06H
|
||
$DGS GLV_SYM, _fn_inttm05, U, U, 0E001H, 026H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 0101H, 00H, 00H
|
||
$DGS BEG_FUN, ??bf_fn_inttm05, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_BEG, 0106H, 00H, 0FBH
|
||
$DGS BEG_BLK, ??bb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_BEG, 03H, 00H, 00H
|
||
$DGS END_BLK, ??eb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_END, 05H
|
||
$DGS END_FUN, ??ef_fn_inttm05, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_END, 06H
|
||
$DGS GLV_SYM, _fn_inttm06, U, U, 0E001H, 026H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 010BH, 00H, 00H
|
||
$DGS BEG_FUN, ??bf_fn_inttm06, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_BEG, 010EH, 00H, 0105H
|
||
$DGS BEG_BLK, ??bb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_BEG, 03H, 00H, 00H
|
||
$DGS END_BLK, ??eb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_END, 05H
|
||
$DGS END_FUN, ??ef_fn_inttm06, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_END, 06H
|
||
$DGS GLV_SYM, _fn_inttm07, U, U, 0E001H, 026H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 0115H, 00H, 00H
|
||
$DGS BEG_FUN, ??bf_fn_inttm07, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_BEG, 0116H, 00H, 010FH
|
||
$DGS BEG_BLK, ??bb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_BEG, 03H, 00H, 00H
|
||
$DGS END_BLK, ??eb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H
|
||
$DGS AUX_END, 05H
|
||
$DGS END_FUN, ??ef_fn_inttm07, U, U, 00H, 065H, 01H, 00H
|
||
$DGS AUX_END, 06H
|
||
$DGS GLV_SYM, _@vect10, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect12, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect1c, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect24, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect2a, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect34, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect36, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect38, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect3a, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect4a, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect5a, U, U, 00H, 026H, 00H, 00H
|
||
$DGS GLV_SYM, _@vect62, U, U, 00H, 026H, 00H, 00H
|
||
|
||
EXTRN _intp4_extdc
|
||
EXTRN _intp5_shell
|
||
EXTRN _int_dma1
|
||
EXTRN _int_iic10
|
||
EXTRN _int_iic_twl
|
||
EXTRN _int_adc
|
||
EXTRN _int_rtc
|
||
EXTRN _int_rtc_int
|
||
EXTRN _int_kr
|
||
EXTRN _intp6_PM_irq
|
||
EXTRN _int_iic_ctr
|
||
EXTRN _intp23_ACC_ready
|
||
PUBLIC _fn_intwdti
|
||
PUBLIC _fn_intlvi
|
||
PUBLIC _fn_intp0
|
||
PUBLIC _fn_intp1
|
||
PUBLIC _fn_intp2
|
||
PUBLIC _fn_intp3
|
||
PUBLIC _intp21_RFTx
|
||
PUBLIC _fn_intcmp0
|
||
PUBLIC _fn_intcmp1
|
||
PUBLIC _fn_intdma0
|
||
PUBLIC _fn_intst0
|
||
PUBLIC _fn_intsr0
|
||
PUBLIC _fn_intsre0
|
||
PUBLIC _fn_intst1
|
||
PUBLIC _fn_intsr1
|
||
PUBLIC _fn_intsre1
|
||
PUBLIC _fn_inttm01
|
||
PUBLIC _fn_inttm02
|
||
PUBLIC _fn_inttm03
|
||
PUBLIC _fn_intrtc
|
||
PUBLIC _fn_intmd
|
||
PUBLIC _fn_inttm04
|
||
PUBLIC _fn_inttm05
|
||
PUBLIC _fn_inttm06
|
||
PUBLIC _fn_inttm07
|
||
PUBLIC _@vect10
|
||
PUBLIC _@vect12
|
||
PUBLIC _@vect1c
|
||
PUBLIC _@vect24
|
||
PUBLIC _@vect2a
|
||
PUBLIC _@vect34
|
||
PUBLIC _@vect36
|
||
PUBLIC _@vect38
|
||
PUBLIC _@vect3a
|
||
PUBLIC _@vect4a
|
||
PUBLIC _@vect5a
|
||
PUBLIC _@vect62
|
||
|
||
@@BITS BSEG
|
||
|
||
@@CNST CSEG MIRRORP
|
||
|
||
@@R_INIT CSEG UNIT64KP
|
||
|
||
@@INIT DSEG BASEP
|
||
|
||
@@DATA DSEG BASEP
|
||
|
||
@@R_INIS CSEG UNIT64KP
|
||
|
||
@@INIS DSEG SADDRP
|
||
|
||
@@DATS DSEG SADDRP
|
||
|
||
@@CNSTL CSEG PAGE64KP
|
||
|
||
@@RLINIT CSEG UNIT64KP
|
||
|
||
@@INITL DSEG UNIT64KP
|
||
|
||
@@DATAL DSEG UNIT64KP
|
||
|
||
@@CALT CSEG CALLT0
|
||
|
||
; line 1 : #pragma nop
|
||
; line 2 :
|
||
; line 3 :
|
||
; line 4 : #include "config.h"
|
||
; line 5 :
|
||
; line 6 : //#pragma interrupt INTWDTI fn_intwdti // <20><><EFBFBD>g<EFBFBD>p
|
||
; line 7 : //#pragma interrupt INTLVI fn_intlvi // <20><><EFBFBD>g<EFBFBD>p
|
||
; line 8 :
|
||
; line 9 : //#pragma interrupt INTP0 intp0_slp // SLP (CPU<50><55><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>v<EFBFBD><76>
|
||
; ) <20>|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O
|
||
; line 10 : //#pragma interrupt INTP1 fn_intp1 // (I2C)
|
||
; line 11 : //#pragma interrupt INTP2 fn_intp2 // (I2C)
|
||
; line 12 : //#pragma interrupt INTP3 fn_intp3 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 13 : #pragma interrupt INTP4 intp4_extdc // EXTDC, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>d<EFBFBD><64>off
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>̂݁B<DD81>ʏ<EFBFBD><CA8F>̓|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O
|
||
; line 14 : #pragma interrupt INTP5 intp5_shell // SHELL_CLOSE, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>d
|
||
; <20><>off<66><66><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>̂݁B<DD81>ʏ<EFBFBD><CA8F>̓|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O
|
||
; line 15 : #pragma interrupt INTP6 intp6_PM_irq // CODEC<45>o<EFBFBD>R<EFBFBD>ŋ<EFBFBD>PMIC<49>ւ<EFBFBD>
|
||
; <20>R<EFBFBD>}<7D><><EFBFBD>h<EFBFBD><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 16 :
|
||
; line 17 : //#ifdef _MCU_BSR_ // <20><><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82>̂<EFBFBD><CC82>̂<EFBFBD>
|
||
; <20>g<EFBFBD><67><EFBFBD>܂<EFBFBD><DC82><EFBFBD>
|
||
; line 18 : //#pragma interrupt INTP21 intp21_RFTx // <20>d<EFBFBD>g<EFBFBD><67><EFBFBD>M<EFBFBD>p<EFBFBD><70><EFBFBD>X
|
||
; line 19 : //#else
|
||
; line 20 : //#pragma interrupt INTP7 intp21_RFTx
|
||
; line 21 : //#endif
|
||
; line 22 :
|
||
; line 23 : #ifdef _MCU_BSR_
|
||
; line 24 : #pragma interrupt INTP23 intp23_ACC_ready // <20><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T
|
||
; <20>A<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 25 : #endif
|
||
; line 26 :
|
||
; line 27 : //#pragma interrupt INTCMP0 fn_intcmp0
|
||
; line 28 : //#pragma interrupt INTCMP1 fn_intcmp1
|
||
; line 29 : //#pragma interrupt INTDMA0 fn_intdma0
|
||
; line 30 : #pragma interrupt INTDMA1 int_dma1
|
||
; line 31 :
|
||
; line 32 : //#pragma interrupt INTST0 fn_intst0
|
||
; line 33 : /* #pragma interrupt INTCSI00 fn_intcsi00 */
|
||
; line 34 : //#pragma interrupt INTSR0 fn_intsr0
|
||
; line 35 : /* #pragma interrupt INTCSI01 fn_intcsi01 */
|
||
; line 36 : //#pragma interrupt INTSRE0 fn_intsre0
|
||
; line 37 :
|
||
; line 38 : //#pragma interrupt INTST1 fn_intst1
|
||
; line 39 : /* #pragma interrupt INTCSI10 fn_intcsi10 */
|
||
; line 40 : #pragma interrupt INTIIC10 int_iic10
|
||
; line 41 : //#pragma interrupt INTSR1 fn_intsr1
|
||
; line 42 : //#pragma interrupt INTSRE1 fn_intsre1
|
||
; line 43 :
|
||
; line 44 :
|
||
; line 45 : #ifdef _MCU_KE3_
|
||
; line 46 : #pragma interrupt INTIICA int_iic_ctr // CTR<54><52>
|
||
; line 47 : #else
|
||
; line 48 :
|
||
; line 49 : // TS<54>̓}<7D>U<EFBFBD>{<7B>Ńe<C583><65><EFBFBD>R<EFBFBD>AWM<57>͉<EFBFBD><CD89>H<EFBFBD>}<7D><><EFBFBD>e<EFBFBD><65><EFBFBD>R<EFBFBD>Ō<EFBFBD><C58C>Lj<EFBFBD><C788>v<EFBFBD>c
|
||
; line 50 : #pragma interrupt INTIICA0 int_iic_twl
|
||
; line 51 : #pragma interrupt INTIICA1 int_iic_ctr
|
||
; line 52 : #endif
|
||
; line 53 :
|
||
; line 54 : //#pragma interrupt INTTM00 fn_inttm00
|
||
; line 55 : //#pragma interrupt INTTM01 fn_inttm01
|
||
; line 56 : //#pragma interrupt INTTM02 fn_inttm02
|
||
; line 57 : //#pragma interrupt INTTM03 fn_inttm03
|
||
; line 58 :
|
||
; line 59 : #pragma interrupt INTAD int_adc
|
||
; line 60 : #pragma interrupt INTRTC int_rtc
|
||
; line 61 : #pragma interrupt INTRTCI int_rtc_int
|
||
; line 62 : #pragma interrupt INTKR int_kr
|
||
; line 63 : //#pragma interrupt INTMD fn_intmd
|
||
; line 64 :
|
||
; line 65 : //#pragma interrupt INTTM04 fn_inttm04
|
||
; line 66 : //#pragma interrupt INTTM05 fn_inttm05
|
||
; line 67 : //#pragma interrupt INTTM06 fn_inttm06
|
||
; line 68 : //#pragma interrupt INTTM07 fn_inttm07
|
||
; line 69 :
|
||
; line 70 :
|
||
; line 71 : /****************************************************/
|
||
; line 72 : /* <20><><EFBFBD>g<EFBFBD>p<EFBFBD><70><EFBFBD>̃_<CC83>~<7E>[<5B><EFBFBD><D690><EFBFBD><EFBFBD>` */
|
||
; line 73 : /****************************************************/
|
||
; line 74 : __interrupt void fn_intwdti( )
|
||
; line 75 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_fn_intwdti:
|
||
$DGL 1,27
|
||
??bf_fn_intwdti:
|
||
; line 76 : while( 1 )
|
||
?L0003:
|
||
; line 77 : {
|
||
??bb00_fn_intwdti:
|
||
; line 78 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intwdti:
|
||
; line 79 : }
|
||
$DGL 0,5
|
||
br $?L0003 ;[INF] 2, 3
|
||
; line 80 : }
|
||
$DGL 0,6
|
||
??ef_fn_intwdti:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intwdti:
|
||
; line 81 : __interrupt void fn_intlvi( )
|
||
; line 82 : {
|
||
_fn_intlvi:
|
||
$DGL 1,37
|
||
??bf_fn_intlvi:
|
||
; line 83 : while( 1 )
|
||
?L0007:
|
||
; line 84 : {
|
||
??bb00_fn_intlvi:
|
||
; line 85 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intlvi:
|
||
; line 86 : }
|
||
$DGL 0,5
|
||
br $?L0007 ;[INF] 2, 3
|
||
; line 87 : }
|
||
$DGL 0,6
|
||
??ef_fn_intlvi:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intlvi:
|
||
; line 88 :
|
||
; line 89 : __interrupt void fn_intp0(){
|
||
_fn_intp0:
|
||
$DGL 1,47
|
||
??bf_fn_intp0:
|
||
; line 90 : while( 1 )
|
||
?L0011:
|
||
; line 91 : {
|
||
??bb00_fn_intp0:
|
||
; line 92 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intp0:
|
||
; line 93 : }
|
||
$DGL 0,5
|
||
br $?L0011 ;[INF] 2, 3
|
||
; line 94 : }
|
||
$DGL 0,6
|
||
??ef_fn_intp0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intp0:
|
||
; line 95 :
|
||
; line 96 : __interrupt void fn_intp1( )
|
||
; line 97 : {
|
||
_fn_intp1:
|
||
$DGL 1,57
|
||
??bf_fn_intp1:
|
||
; line 98 : while( 1 )
|
||
?L0015:
|
||
; line 99 : {
|
||
??bb00_fn_intp1:
|
||
; line 100 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intp1:
|
||
; line 101 : }
|
||
$DGL 0,5
|
||
br $?L0015 ;[INF] 2, 3
|
||
; line 102 : } //
|
||
$DGL 0,6
|
||
??ef_fn_intp1:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intp1:
|
||
; line 103 : __interrupt void fn_intp2( )
|
||
; line 104 : {
|
||
_fn_intp2:
|
||
$DGL 1,67
|
||
??bf_fn_intp2:
|
||
; line 105 : while( 1 )
|
||
?L0019:
|
||
; line 106 : {
|
||
??bb00_fn_intp2:
|
||
; line 107 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intp2:
|
||
; line 108 : }
|
||
$DGL 0,5
|
||
br $?L0019 ;[INF] 2, 3
|
||
; line 109 : }
|
||
$DGL 0,6
|
||
??ef_fn_intp2:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intp2:
|
||
; line 110 : __interrupt void fn_intp3( )
|
||
; line 111 : {
|
||
_fn_intp3:
|
||
$DGL 1,77
|
||
??bf_fn_intp3:
|
||
; line 112 : while( 1 )
|
||
?L0023:
|
||
; line 113 : {
|
||
??bb00_fn_intp3:
|
||
; line 114 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intp3:
|
||
; line 115 : }
|
||
$DGL 0,5
|
||
br $?L0023 ;[INF] 2, 3
|
||
; line 116 : }
|
||
$DGL 0,6
|
||
??ef_fn_intp3:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intp3:
|
||
; line 117 :
|
||
; line 118 :
|
||
; line 119 : __interrupt void intp21_RFTx( )
|
||
; line 120 : {
|
||
_intp21_RFTx:
|
||
$DGL 1,87
|
||
??bf_intp21_RFTx:
|
||
; line 121 : while( 1 )
|
||
?L0027:
|
||
; line 122 : {
|
||
??bb00_intp21_RFTx:
|
||
; line 123 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_intp21_RFTx:
|
||
; line 124 : }
|
||
$DGL 0,5
|
||
br $?L0027 ;[INF] 2, 3
|
||
; line 125 : }
|
||
$DGL 0,6
|
||
??ef_intp21_RFTx:
|
||
reti ;[INF] 2, 6
|
||
??ee_intp21_RFTx:
|
||
; line 126 :
|
||
; line 127 :
|
||
; line 128 : //__interrupt void fn_intp4(){ while(1){} } // pm.c
|
||
; line 129 : //__interrupt void fn_intp5(){ while(1){} } // pm.c
|
||
; line 130 : //__interrupt void fn_intp6(){ while(1){} } // pm.c
|
||
; line 131 : //__interrupt void fn_intp7(){ while(1){} } // led.c
|
||
; line 132 : //__interrupt void fn_intp21(){ while(1){} } // led.c
|
||
; line 133 :
|
||
; line 134 : __interrupt void fn_intcmp0( )
|
||
; line 135 : {
|
||
_fn_intcmp0:
|
||
$DGL 1,97
|
||
??bf_fn_intcmp0:
|
||
; line 136 : while( 1 )
|
||
?L0031:
|
||
; line 137 : {
|
||
??bb00_fn_intcmp0:
|
||
; line 138 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intcmp0:
|
||
; line 139 : }
|
||
$DGL 0,5
|
||
br $?L0031 ;[INF] 2, 3
|
||
; line 140 : }
|
||
$DGL 0,6
|
||
??ef_fn_intcmp0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intcmp0:
|
||
; line 141 : __interrupt void fn_intcmp1( )
|
||
; line 142 : {
|
||
_fn_intcmp1:
|
||
$DGL 1,107
|
||
??bf_fn_intcmp1:
|
||
; line 143 : while( 1 )
|
||
?L0035:
|
||
; line 144 : {
|
||
??bb00_fn_intcmp1:
|
||
; line 145 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intcmp1:
|
||
; line 146 : }
|
||
$DGL 0,5
|
||
br $?L0035 ;[INF] 2, 3
|
||
; line 147 : }
|
||
$DGL 0,6
|
||
??ef_fn_intcmp1:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intcmp1:
|
||
; line 148 : __interrupt void fn_intdma0( )
|
||
; line 149 : {
|
||
_fn_intdma0:
|
||
$DGL 1,117
|
||
??bf_fn_intdma0:
|
||
; line 150 : while( 1 )
|
||
?L0039:
|
||
; line 151 : {
|
||
??bb00_fn_intdma0:
|
||
; line 152 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intdma0:
|
||
; line 153 : }
|
||
$DGL 0,5
|
||
br $?L0039 ;[INF] 2, 3
|
||
; line 154 : }
|
||
$DGL 0,6
|
||
??ef_fn_intdma0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intdma0:
|
||
; line 155 :
|
||
; line 156 : //__interrupt void fn_intdma1(){} // i2c_mcu.c<>ɂ<EFBFBD><C982><EFBFBD>
|
||
; line 157 :
|
||
; line 158 : __interrupt void fn_intst0( )
|
||
; line 159 : {
|
||
_fn_intst0:
|
||
$DGL 1,127
|
||
??bf_fn_intst0:
|
||
; line 160 : while( 1 )
|
||
?L0043:
|
||
; line 161 : {
|
||
??bb00_fn_intst0:
|
||
; line 162 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intst0:
|
||
; line 163 : }
|
||
$DGL 0,5
|
||
br $?L0043 ;[INF] 2, 3
|
||
; line 164 : }
|
||
$DGL 0,6
|
||
??ef_fn_intst0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intst0:
|
||
; line 165 :
|
||
; line 166 : /* __interrupt void fn_intcsi00(){} */
|
||
; line 167 : __interrupt void fn_intsr0( )
|
||
; line 168 : {
|
||
_fn_intsr0:
|
||
$DGL 1,137
|
||
??bf_fn_intsr0:
|
||
; line 169 : while( 1 )
|
||
?L0047:
|
||
; line 170 : {
|
||
??bb00_fn_intsr0:
|
||
; line 171 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intsr0:
|
||
; line 172 : }
|
||
$DGL 0,5
|
||
br $?L0047 ;[INF] 2, 3
|
||
; line 173 : }
|
||
$DGL 0,6
|
||
??ef_fn_intsr0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intsr0:
|
||
; line 174 :
|
||
; line 175 : /* __interrupt void fn_intcsi01(){} */
|
||
; line 176 : __interrupt void fn_intsre0( )
|
||
; line 177 : {
|
||
_fn_intsre0:
|
||
$DGL 1,147
|
||
??bf_fn_intsre0:
|
||
; line 178 : while( 1 )
|
||
?L0051:
|
||
; line 179 : {
|
||
??bb00_fn_intsre0:
|
||
; line 180 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intsre0:
|
||
; line 181 : }
|
||
$DGL 0,5
|
||
br $?L0051 ;[INF] 2, 3
|
||
; line 182 : }
|
||
$DGL 0,6
|
||
??ef_fn_intsre0:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intsre0:
|
||
; line 183 :
|
||
; line 184 : __interrupt void fn_intst1( )
|
||
; line 185 : {
|
||
_fn_intst1:
|
||
$DGL 1,157
|
||
??bf_fn_intst1:
|
||
; line 186 : while( 1 )
|
||
?L0055:
|
||
; line 187 : {
|
||
??bb00_fn_intst1:
|
||
; line 188 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intst1:
|
||
; line 189 : }
|
||
$DGL 0,5
|
||
br $?L0055 ;[INF] 2, 3
|
||
; line 190 : }
|
||
$DGL 0,6
|
||
??ef_fn_intst1:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intst1:
|
||
; line 191 :
|
||
; line 192 : /* __interrupt void fn_intcsi10(){} */
|
||
; line 193 : //__interrupt void fn_intiic10(){ while(1){} }
|
||
; line 194 : __interrupt void fn_intsr1( )
|
||
; line 195 : {
|
||
_fn_intsr1:
|
||
$DGL 1,167
|
||
??bf_fn_intsr1:
|
||
; line 196 : while( 1 )
|
||
?L0059:
|
||
; line 197 : {
|
||
??bb00_fn_intsr1:
|
||
; line 198 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intsr1:
|
||
; line 199 : }
|
||
$DGL 0,5
|
||
br $?L0059 ;[INF] 2, 3
|
||
; line 200 : }
|
||
$DGL 0,6
|
||
??ef_fn_intsr1:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intsr1:
|
||
; line 201 : __interrupt void fn_intsre1( )
|
||
; line 202 : {
|
||
_fn_intsre1:
|
||
$DGL 1,177
|
||
??bf_fn_intsre1:
|
||
; line 203 : while( 1 )
|
||
?L0063:
|
||
; line 204 : {
|
||
??bb00_fn_intsre1:
|
||
; line 205 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intsre1:
|
||
; line 206 : }
|
||
$DGL 0,5
|
||
br $?L0063 ;[INF] 2, 3
|
||
; line 207 : }
|
||
$DGL 0,6
|
||
??ef_fn_intsre1:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intsre1:
|
||
; line 208 :
|
||
; line 209 : //__interrupt void fn_intiica(){} // i2c.c<>ɂ<EFBFBD><C982><EFBFBD>
|
||
; line 210 : /* __interrupt void fn_inttm00(){} *//* sub.c<>ɂĒ<C982><C492>` */
|
||
; line 211 : __interrupt void fn_inttm01( )
|
||
; line 212 : {
|
||
_fn_inttm01:
|
||
$DGL 1,187
|
||
??bf_fn_inttm01:
|
||
; line 213 : while( 1 )
|
||
?L0067:
|
||
; line 214 : {
|
||
??bb00_fn_inttm01:
|
||
; line 215 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm01:
|
||
; line 216 : }
|
||
$DGL 0,5
|
||
br $?L0067 ;[INF] 2, 3
|
||
; line 217 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm01:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm01:
|
||
; line 218 :
|
||
; line 219 : __interrupt void fn_inttm02( )
|
||
; line 220 : {
|
||
_fn_inttm02:
|
||
$DGL 1,197
|
||
??bf_fn_inttm02:
|
||
; line 221 : while( 1 )
|
||
?L0071:
|
||
; line 222 : {
|
||
??bb00_fn_inttm02:
|
||
; line 223 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm02:
|
||
; line 224 : }
|
||
$DGL 0,5
|
||
br $?L0071 ;[INF] 2, 3
|
||
; line 225 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm02:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm02:
|
||
; line 226 : __interrupt void fn_inttm03( )
|
||
; line 227 : {
|
||
_fn_inttm03:
|
||
$DGL 1,207
|
||
??bf_fn_inttm03:
|
||
; line 228 : while( 1 )
|
||
?L0075:
|
||
; line 229 : {
|
||
??bb00_fn_inttm03:
|
||
; line 230 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm03:
|
||
; line 231 : }
|
||
$DGL 0,5
|
||
br $?L0075 ;[INF] 2, 3
|
||
; line 232 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm03:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm03:
|
||
; line 233 :
|
||
; line 234 : //__interrupt void fn_intad(){ while(1){} } // adc.c
|
||
; line 235 : __interrupt void fn_intrtc( )
|
||
; line 236 : {
|
||
_fn_intrtc:
|
||
$DGL 1,217
|
||
??bf_fn_intrtc:
|
||
; line 237 : while( 1 )
|
||
?L0079:
|
||
; line 238 : {
|
||
??bb00_fn_intrtc:
|
||
; line 239 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intrtc:
|
||
; line 240 : }
|
||
$DGL 0,5
|
||
br $?L0079 ;[INF] 2, 3
|
||
; line 241 : }
|
||
$DGL 0,6
|
||
??ef_fn_intrtc:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intrtc:
|
||
; line 242 :
|
||
; line 243 : //__interrupt void int_rtcint(){} // rtc.c<>ɂ<EFBFBD><C982><EFBFBD>
|
||
; line 244 : //__interrupt void fn_intkr(){} // main.c
|
||
; line 245 : __interrupt void fn_intmd( )
|
||
; line 246 : {
|
||
_fn_intmd:
|
||
$DGL 1,227
|
||
??bf_fn_intmd:
|
||
; line 247 : while( 1 )
|
||
?L0083:
|
||
; line 248 : {
|
||
??bb00_fn_intmd:
|
||
; line 249 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_intmd:
|
||
; line 250 : }
|
||
$DGL 0,5
|
||
br $?L0083 ;[INF] 2, 3
|
||
; line 251 : }
|
||
$DGL 0,6
|
||
??ef_fn_intmd:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_intmd:
|
||
; line 252 :
|
||
; line 253 : __interrupt void fn_inttm04( )
|
||
; line 254 : {
|
||
_fn_inttm04:
|
||
$DGL 1,237
|
||
??bf_fn_inttm04:
|
||
; line 255 : while( 1 )
|
||
?L0087:
|
||
; line 256 : {
|
||
??bb00_fn_inttm04:
|
||
; line 257 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm04:
|
||
; line 258 : }
|
||
$DGL 0,5
|
||
br $?L0087 ;[INF] 2, 3
|
||
; line 259 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm04:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm04:
|
||
; line 260 :
|
||
; line 261 : __interrupt void fn_inttm05( )
|
||
; line 262 : {
|
||
_fn_inttm05:
|
||
$DGL 1,247
|
||
??bf_fn_inttm05:
|
||
; line 263 : while( 1 )
|
||
?L0091:
|
||
; line 264 : {
|
||
??bb00_fn_inttm05:
|
||
; line 265 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm05:
|
||
; line 266 : }
|
||
$DGL 0,5
|
||
br $?L0091 ;[INF] 2, 3
|
||
; line 267 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm05:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm05:
|
||
; line 268 :
|
||
; line 269 : __interrupt void fn_inttm06( )
|
||
; line 270 : {
|
||
_fn_inttm06:
|
||
$DGL 1,257
|
||
??bf_fn_inttm06:
|
||
; line 271 : while( 1 )
|
||
?L0095:
|
||
; line 272 : {
|
||
??bb00_fn_inttm06:
|
||
; line 273 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm06:
|
||
; line 274 : }
|
||
$DGL 0,5
|
||
br $?L0095 ;[INF] 2, 3
|
||
; line 275 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm06:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm06:
|
||
; line 276 :
|
||
; line 277 : __interrupt void fn_inttm07( )
|
||
; line 278 : {
|
||
_fn_inttm07:
|
||
$DGL 1,267
|
||
??bf_fn_inttm07:
|
||
; line 279 : while( 1 )
|
||
?L0099:
|
||
; line 280 : {
|
||
??bb00_fn_inttm07:
|
||
; line 281 : NOP();
|
||
$DGL 0,4
|
||
nop ;[INF] 1, 1
|
||
??eb00_fn_inttm07:
|
||
; line 282 : }
|
||
$DGL 0,5
|
||
br $?L0099 ;[INF] 2, 3
|
||
; line 283 : }
|
||
$DGL 0,6
|
||
??ef_fn_inttm07:
|
||
reti ;[INF] 2, 6
|
||
??ee_fn_inttm07:
|
||
|
||
@@VECT10 CSEG AT 0010H
|
||
_@vect10:
|
||
DW _intp4_extdc
|
||
_@vect12:
|
||
DW _intp5_shell
|
||
|
||
@@VECT1C CSEG AT 001CH
|
||
_@vect1c:
|
||
DW _int_dma1
|
||
|
||
@@VECT24 CSEG AT 0024H
|
||
_@vect24:
|
||
DW _int_iic10
|
||
|
||
@@VECT2A CSEG AT 002AH
|
||
_@vect2a:
|
||
DW _int_iic_twl
|
||
|
||
@@VECT34 CSEG AT 0034H
|
||
_@vect34:
|
||
DW _int_adc
|
||
_@vect36:
|
||
DW _int_rtc
|
||
_@vect38:
|
||
DW _int_rtc_int
|
||
_@vect3a:
|
||
DW _int_kr
|
||
|
||
@@VECT4A CSEG AT 004AH
|
||
_@vect4a:
|
||
DW _intp6_PM_irq
|
||
|
||
@@VECT5A CSEG AT 005AH
|
||
_@vect5a:
|
||
DW _int_iic_ctr
|
||
|
||
@@VECT62 CSEG AT 0062H
|
||
_@vect62:
|
||
DW _intp23_ACC_ready
|
||
|
||
@@CODE CSEG BASE
|
||
|
||
@@CODEL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara_0.10\ini_VECT.c
|
||
;
|
||
; $FUNC fn_intwdti(75)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intlvi(82)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intp0(89)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intp1(97)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intp2(104)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intp3(111)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC intp21_RFTx(120)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intcmp0(135)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intcmp1(142)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intdma0(149)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intst0(159)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intsr0(168)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intsre0(177)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intst1(185)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intsr1(195)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intsre1(202)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm01(212)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm02(220)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm03(227)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intrtc(236)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_intmd(246)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm04(254)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm05(262)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm06(270)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC fn_inttm07(278)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|