mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
985 lines
32 KiB
NASM
985 lines
32 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no accero.c
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; In-file : accero.c
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; Asm-file : inter_asm\accero.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 0B7H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, accero.c
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$DGS MOD_NAM, accero, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 047H
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$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 041H, 01H
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$DGS LAB_SYM, bs_F0038, U, U, 00H, 06H, 00H, 00H
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$DGS LAB_SYM, es_F0038, U, U, 00H, 06H, 00H, 00H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 026H, 01H, 02H
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$DGS AUX_FUN, 041H, U, U, 067H, 00H, 00H
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$DGS BEG_FUN, ??bf_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 042H, 06H, 04FH
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$DGS BEG_BLK, ??bb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0EH, 00H, 053H
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$DGS END_BLK, ??eb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 014H
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$DGS BEG_BLK, ??bb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 016H, 00H, 055H
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$DGS BEG_BLK, ??bb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01CH, 00H, 057H
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$DGS BEG_BLK, ??bb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 020H, 00H, 05FH
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$DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H
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$DGS AUX_STR, 00H, 021H, 06H, 06H, 00H, 00H, 00H, 00H
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$DGS END_BLK, ??eb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 023H
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$DGS END_BLK, ??eb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 024H
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$DGS BEG_BLK, ??bb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 029H, 00H, 00H
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$DGS END_BLK, ??eb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02DH
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$DGS END_BLK, ??eb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02EH
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$DGS END_FUN, ??ef_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 030H
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$DGS GLV_SYM, _acc_read, U, U, 0AH, 026H, 01H, 02H
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$DGS AUX_FUN, 041H, U, U, 075H, 00H, 00H
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$DGS BEG_FUN, ??bf_acc_read, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 07BH, 00H, 06BH
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$DGS BEG_BLK, ??bb00_acc_read, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 06DH
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$DGS BEG_BLK, ??bb01_acc_read, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 07H, 00H, 00H
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$DGS END_BLK, ??eb01_acc_read, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 07H
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$DGS END_BLK, ??eb00_acc_read, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 08H
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$DGS END_FUN, ??ef_acc_read, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 0AH
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$DGS GLV_SYM, _acc_write, U, U, 0AH, 026H, 01H, 02H
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$DGS AUX_FUN, 041H, U, U, 083H, 00H, 00H
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$DGS BEG_FUN, ??bf_acc_write, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 08CH, 00H, 079H
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$DGS BEG_BLK, ??bb00_acc_write, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 05H, 00H, 07BH
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$DGS BEG_BLK, ??bb01_acc_write, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 00H
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$DGS END_BLK, ??eb01_acc_write, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 06H
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$DGS END_BLK, ??eb00_acc_write, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 07H
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$DGS END_FUN, ??ef_acc_write, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 09H
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$DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 026H, 01H, 02H
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$DGS AUX_FUN, 041H, U, U, 0A5H, 00H, 00H
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$DGS BEG_FUN, ??bf_acc_hosu_set, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 09EH, 0AH, 089H
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$DGS AUT_VAR, _str_send_buf, 06H, 0FFFFH, 0CH, 01H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H
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$DGS BEG_BLK, ??bb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 08DH
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$DGS END_BLK, ??eb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0CH
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$DGS BEG_BLK, ??bb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0CH, 00H, 091H
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$DGS END_BLK, ??eb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0EH
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$DGS BEG_BLK, ??bb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 028H, 00H, 095H
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$DGS END_BLK, ??eb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02FH
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$DGS BEG_BLK, ??bb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 031H, 00H, 099H
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$DGS END_BLK, ??eb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03AH
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$DGS BEG_BLK, ??bb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03FH, 00H, 09BH
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$DGS BEG_BLK, ??bb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 041H, 00H, 00H
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$DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H
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$DGS AUX_STR, 00H, 042H, 06H, 06H, 00H, 00H, 00H, 00H
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$DGS END_BLK, ??eb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 044H
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$DGS END_BLK, ??eb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 045H
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$DGS END_FUN, ??ef_acc_hosu_set, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 047H
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$DGS GLV_SYM, _intp23_ACC_ready, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0B7H, 00H, 00H
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$DGS BEG_FUN, ??bf_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0EDH, 016H, 0A9H
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$DGS BEG_BLK, ??bb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 04H, 00H, 0ABH
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$DGS BEG_BLK, ??bb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 0ADH
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$DGS BEG_BLK, ??bb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 08H, 00H, 00H
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$DGS END_BLK, ??eb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0AH
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$DGS END_BLK, ??eb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0BH
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$DGS END_BLK, ??eb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0CH
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$DGS END_FUN, ??ef_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 0DH
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$DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _pedometer, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
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EXTRN _iic_mcu_read
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EXTRN _vreg_ctr
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EXTRN _system_status
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EXTRN _set_irq
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EXTRN _pedometer
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EXTRN _iic_mcu_read_a_byte
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EXTRN _iic_mcu_write_a_byte
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EXTRN _iic_mcu_bus_status
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EXTRN _iic_mcu_write
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EXTRN _@SEGAX
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EXTRN _@SEGDE
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EXTRN _@RTARG0
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EXTRN _renge_task_immed_add
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PUBLIC _tsk_cbk_accero
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PUBLIC _acc_read
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PUBLIC _acc_write
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PUBLIC _acc_hosu_set
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PUBLIC _intp23_ACC_ready
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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||
DB 025H ; 37
|
||
DB 038H ; 56
|
||
DB 04DH ; 77
|
||
DB 05FH ; 95
|
||
DB 06EH ; 110
|
||
DB 077H ; 119
|
||
DB 07AH ; 122
|
||
DB 077H ; 119
|
||
DB 06EH ; 110
|
||
DB 05FH ; 95
|
||
DB 04DH ; 77
|
||
DB 038H ; 56
|
||
DB 025H ; 37
|
||
DB 012H ; 18
|
||
DB 04H ; 4
|
||
DB 0FAH ; 250
|
||
DB 0F3H ; 243
|
||
DB 0F0H ; 240
|
||
DB 0F0H ; 240
|
||
DB 0F3H ; 243
|
||
DB 0F7H ; 247
|
||
DB 0FBH ; 251
|
||
DB 0FEH ; 254
|
||
DB 00H ; 0
|
||
DB 02H ; 2
|
||
DB 03H ; 3
|
||
DB 03H ; 3
|
||
DB 02H ; 2
|
||
DB 02H ; 2
|
||
DB 01H ; 1
|
||
DB (1)
|
||
|
||
@@R_INIT CSEG UNIT64KP
|
||
|
||
@@INIT DSEG BASEP
|
||
|
||
@@DATA DSEG BASEP
|
||
|
||
@@R_INIS CSEG UNIT64KP
|
||
|
||
@@INIS DSEG SADDRP
|
||
|
||
@@DATS DSEG SADDRP
|
||
|
||
@@CNSTL CSEG PAGE64KP
|
||
|
||
@@RLINIT CSEG UNIT64KP
|
||
|
||
@@INITL DSEG UNIT64KP
|
||
|
||
@@DATAL DSEG UNIT64KP
|
||
|
||
@@CALT CSEG CALLT0
|
||
|
||
; Sub-Routines created by CC78K0R
|
||
|
||
ROM_CODE CSEG BASE
|
||
bs_F0038:
|
||
push ax ;[INF] 1, 1
|
||
movw ax,#06H ; 6 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#0A8H ; 168 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_read ;[INF] 3, 3
|
||
addw sp,#06H ; 6 ;[INF] 2, 1
|
||
ret ;[INF] 1, 6
|
||
es_F0038:
|
||
|
||
; *** Sub-Routine Information ***
|
||
;
|
||
; $SUB bs_F0038
|
||
; CODE SIZE= 16 bytes
|
||
|
||
; End of Sub-Routines
|
||
|
||
; line 1 : /* ========================================================
|
||
; line 2 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD>W
|
||
; line 3 : <20>E<EFBFBD>f<EFBFBD>[<5B>^<5E>X<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>Ńf<C583>[<5B>^<5E><><EFBFBD>z<EFBFBD><7A><EFBFBD>グ<EFBFBD>背<EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD>X<EFBFBD>V<EFBFBD>ACPU<50>Ɋ<EFBFBD><C98A>荞<EFBFBD><E88D9E>
|
||
; line 4 : <20>E<EFBFBD>t<EFBFBD><74><EFBFBD>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>Ε<EFBFBD><CE95><EFBFBD><EFBFBD>J<EFBFBD>E<EFBFBD><45><EFBFBD>g
|
||
; line 5 : <20>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD><54><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD>^<5E>X<EFBFBD>N<EFBFBD><4E><EFBFBD>o<EFBFBD>^<5E><><EFBFBD>ĉ<EFBFBD><C489><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD>iI2C<32>̋<EFBFBD><CC8B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20>Ȃǂ<C882><C782><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂Łj
|
||
; line 6 :
|
||
; line 7 : ======================================================== */
|
||
; line 8 : #pragma SFR
|
||
; line 9 : #pragma NOP
|
||
; line 10 : #pragma HALT
|
||
; line 11 : #pragma STOP
|
||
; line 12 : #pragma ROT
|
||
; line 13 : // rorb, rolb, rorw, rolw
|
||
; line 14 : #pragma MUL
|
||
; line 15 : #pragma BCD
|
||
; line 16 :
|
||
; line 17 : #include "incs.h"
|
||
; line 18 : #include <math.h>
|
||
; line 19 :
|
||
; line 20 : // ========================================================
|
||
; line 21 : // <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><>
|
||
; line 22 : #define ACC_REG_WHOAMI 0x0F
|
||
; line 23 : #define ACC_REG_CTRL1 0x20
|
||
; line 24 : #define ACC_REG_CTRL5 0x24
|
||
; line 25 : #define ACC_REG_X 0x28
|
||
; line 26 :
|
||
; line 27 : // <20>r<EFBFBD>b<EFBFBD>g<EFBFBD>ʒu
|
||
; line 28 : #define ACC_bP_PM0 5
|
||
; line 29 : #define ACC_bP_DR0 3
|
||
; line 30 :
|
||
; line 31 : // <20>r<EFBFBD>b<EFBFBD>g<EFBFBD>ݒ<EFBFBD><DD92>l
|
||
; line 32 : #define ACC_BITS_PM_PDN 0
|
||
; line 33 : #define ACC_BITS_PM_NORM 1
|
||
; line 34 : #define ACC_BITS_PM_LP0R5 2
|
||
; line 35 : #define ACC_BITS_PM_LP1 3
|
||
; line 36 : #define ACC_BITS_PM_LP2 4
|
||
; line 37 : #define ACC_BITS_PM_LP5 5
|
||
; line 38 : #define ACC_BITS_PM_LP10 6
|
||
; line 39 :
|
||
; line 40 : #define ACC_BITS_DR_50Hz 0
|
||
; line 41 : #define ACC_BITS_DR_100Hz 1
|
||
; line 42 : #define ACC_BITS_DR_400Hz 2
|
||
; line 43 : #define ACC_BITS_DR_1000Hz 3
|
||
; line 44 :
|
||
; line 45 : #define ACC_BITS_ALL_AXIS_ON 7
|
||
; line 46 :
|
||
; line 47 :
|
||
; line 48 : #define VREG_BITMASK_ACC_CONF_ACQ ( 1 << 0 )
|
||
; line 49 : #define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 )
|
||
; line 50 :
|
||
; line 51 :
|
||
; line 52 :
|
||
; line 53 :
|
||
; line 54 : // ========================================================
|
||
; line 55 : task_status tsk_soft_int( );
|
||
; line 56 :
|
||
; line 57 :
|
||
; line 58 :
|
||
; line 59 : /* ========================================================
|
||
; line 60 : <20>@<40>E<EFBFBD><45><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82>m<EFBFBD>F<EFBFBD><46><EFBFBD>ăf<C483>[<5B>^<5E><><EFBFBD>z<EFBFBD><7A><EFBFBD>グ<EFBFBD>A<EFBFBD><41><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>܂<EFBFBD>
|
||
; line 61 : <20>E<EFBFBD>{<7B><><EFBFBD>ł<EFBFBD><C582><EFBFBD><EFBFBD>R<CE83>[<5B><><EFBFBD>o<EFBFBD>b<EFBFBD>N<EFBFBD><EFBFBD><D690><EFBFBD><EFBFBD>o<EFBFBD>^<5E><><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD><CE82><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƂȂ<C682>
|
||
; <20>̂ł<CC82><C582><EFBFBD><EFBFBD>A
|
||
; line 62 : I2C<32><43><EFBFBD>g<EFBFBD>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>H<EFBFBD>Ƃ<EFBFBD><C682>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD>Ǝ<EFBFBD><C68E>ł͂<C582><CD82><EFBFBD><EFBFBD>܂łł<C582><C582>Ȃ<EFBFBD><C882>̂ł<CC82><C582>B
|
||
; line 63 : <20>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>v<EFBFBD>Ƃ<EFBFBD><C682>ł<EFBFBD><C582><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 64 : ======================================================== */
|
||
; line 65 : task_status_immed tsk_cbk_accero( )
|
||
; line 66 : { // <20>i<EFBFBD>^<5E><><EFBFBD>jisr<73><72><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
|
||
ROM_CODE CSEG BASE
|
||
_tsk_cbk_accero:
|
||
$DGL 1,75
|
||
push hl ;[INF] 1, 1
|
||
subw sp,#06H ;[INF] 2, 1
|
||
movw hl,sp ;[INF] 3, 1
|
||
??bf_tsk_cbk_accero:
|
||
; line 67 :
|
||
; line 68 : /*
|
||
; line 69 : if(( system_status.pwr_state == OFF ) || ( system_status.pwr
|
||
; _state == BT_CHARGE ) )
|
||
; line 70 : {
|
||
; line 71 : return ( ERR_SUCCESS );
|
||
; line 72 : }
|
||
; line 73 : else
|
||
; line 74 : {
|
||
; line 75 : */
|
||
; line 76 : // <20><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ւ̔<D682><CC94>f
|
||
; line 77 : if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6
|
||
; , &vreg_ctr[VREG_C_ACC_XL] )
|
||
; line 78 : != ERR_SUCCESS )
|
||
$DGL 0,13
|
||
movw de,#loww (_vreg_ctr+69) ;[INF] 3, 1
|
||
push de ;[INF] 1, 1
|
||
movw ax,#06H ; 6 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#0A8H ; 168 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_read ;[INF] 3, 3
|
||
addw sp,#06H ; 6 ;[INF] 2, 1
|
||
cmp0 c ;[INF] 1, 1
|
||
bz $?L0003 ;[INF] 2, 4
|
||
; line 79 : {
|
||
??bb00_tsk_cbk_accero:
|
||
; line 80 : // <20><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD><54><EFBFBD>ُ<EFBFBD><D98F>ɂȂ<C982><C882><EFBFBD><EFBFBD>̂Ŏ~<7E>߂<EFBFBD>
|
||
; line 81 : vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_
|
||
; HOSU | VREG_BITMASK_ACC_CONF_ACQ );
|
||
$DGL 0,16
|
||
movw de,#loww (_vreg_ctr+64) ;[INF] 3, 1
|
||
mov a,[de] ;[INF] 1, 1
|
||
and a,#0FCH ; 252 ;[INF] 2, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
; line 82 : // vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
|
||
; line 83 : acc_hosu_set();
|
||
$DGL 0,18
|
||
call !_acc_hosu_set ;[INF] 3, 3
|
||
; line 84 : return ( ERR_SUCCESS ); // <20>^<5E>X<EFBFBD>N<EFBFBD>̍폜<CC8D>͕K<CD95>v
|
||
$DGL 0,19
|
||
clrw bc ;[INF] 1, 1
|
||
br $?L0002 ;[INF] 2, 3
|
||
??eb00_tsk_cbk_accero:
|
||
; line 85 : }
|
||
?L0003:
|
||
; line 86 : else
|
||
; line 87 : {
|
||
??bb01_tsk_cbk_accero:
|
||
; line 88 : // <20><><EFBFBD>펞<EFBFBD>p<EFBFBD>X //
|
||
; line 89 : // <20><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>X<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
; line 90 : if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO
|
||
; NF_ACQ ) != 0 ) &&
|
||
$DGL 0,25
|
||
mov a,!_vreg_ctr+64 ;[INF] 3, 1
|
||
and a,#01H ; 1 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0007 ;[INF] 2, 4
|
||
; line 91 : ( system_status.pwr_state == ON )
|
||
$DGL 0,26
|
||
cmp !_system_status,#03H ; 3 ;[INF] 4, 1
|
||
bnz $?L0007 ;[INF] 2, 4
|
||
; line 92 : )
|
||
; line 93 : {
|
||
??bb02_tsk_cbk_accero:
|
||
; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY );
|
||
$DGL 0,29
|
||
movw ax,#010H ; 16 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
incw ax ;[INF] 1, 1
|
||
call !_set_irq ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
; line 95 : // <20>S<EFBFBD>~<7E>f<EFBFBD>[<5B>^<5E>̃J<CC83><4A><EFBFBD>ǂ<EFBFBD>
|
||
; line 96 : if( ACC_VALID == 1 )
|
||
$DGL 0,31
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0510H ; 1296 ;[INF] 3, 1
|
||
mov1 CY,[hl].5 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0007 ;[INF] 2, 4
|
||
; line 97 : {
|
||
??bb03_tsk_cbk_accero:
|
||
; line 98 : u8 temp[6];
|
||
; line 99 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80
|
||
; ), 6, temp );
|
||
$DGL 0,34
|
||
movw ax,hl ;[INF] 1, 1
|
||
call !bs_F0038 ;[INF] 3, 3
|
||
??eb03_tsk_cbk_accero:
|
||
; line 100 : }
|
||
?L0007:
|
||
??eb02_tsk_cbk_accero:
|
||
; line 101 : }
|
||
; line 102 : if(( system_status.pwr_state != OFF ) &&
|
||
; line 103 : ( system_status.pwr_state != BT_CHARGE ) &&
|
||
$DGL 0,38
|
||
cmp !_system_status,#01H ; 1 ;[INF] 4, 1
|
||
bz $?L0009 ;[INF] 2, 4
|
||
cmp !_system_status,#06H ; 6 ;[INF] 4, 1
|
||
bz $?L0009 ;[INF] 2, 4
|
||
; line 104 : ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO
|
||
; NF_HOSU ) != 0 )
|
||
$DGL 0,39
|
||
mov a,!_vreg_ctr+64 ;[INF] 3, 1
|
||
and a,#02H ; 2 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
skz ;[INF] 2, 1
|
||
; line 105 : )
|
||
; line 106 : {
|
||
??bb04_tsk_cbk_accero:
|
||
; line 107 : DBG_LED_WIFI_2_on;
|
||
; line 108 : pedometer(); // <20><><EFBFBD><EFBFBD><EFBFBD>v
|
||
$DGL 0,43
|
||
call !_pedometer ;[INF] 3, 3
|
||
; line 109 : DBG_LED_WIFI_2_off;
|
||
??eb04_tsk_cbk_accero:
|
||
; line 110 : }
|
||
?L0009:
|
||
??eb01_tsk_cbk_accero:
|
||
; line 111 : }
|
||
; line 112 : return ( ERR_SUCCESS );
|
||
$DGL 0,47
|
||
clrw bc ;[INF] 1, 1
|
||
; line 113 : }
|
||
?L0002:
|
||
$DGL 0,48
|
||
??ef_tsk_cbk_accero:
|
||
addw sp,#06H ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_tsk_cbk_accero:
|
||
; line 114 :
|
||
; line 115 :
|
||
; line 116 :
|
||
; line 117 :
|
||
; line 118 :
|
||
; line 119 : /*=======================================================
|
||
; line 120 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD><54><EFBFBD>߃A<DF83>N<EFBFBD>Z<EFBFBD>X<EFBFBD>@<40><><EFBFBD>[<5B>h
|
||
; line 121 : ========================================================*/
|
||
; line 122 : task_status_immed acc_read( )
|
||
; line 123 : {
|
||
_acc_read:
|
||
$DGL 1,103
|
||
??bf_acc_read:
|
||
; line 124 : vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_AC
|
||
; CEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
|
||
$DGL 0,2
|
||
mov x,!_vreg_ctr+65 ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_read_a_byte ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
mov a,c ;[INF] 1, 1
|
||
mov !_vreg_ctr+68,a ;[INF] 3, 1
|
||
; line 125 : // vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_
|
||
; ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
|
||
; line 126 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
|
||
$DGL 0,4
|
||
set1 !_vreg_ctr+17.3 ;[INF] 4, 2
|
||
; line 127 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
|
||
$DGL 0,5
|
||
mov a,!_vreg_ctr+25 ;[INF] 3, 1
|
||
and a,#08H ; 8 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
; line 128 : {
|
||
??bb00_acc_read:
|
||
; line 129 : IRQ0_ast;
|
||
$DGL 0,7
|
||
??bb01_acc_read:
|
||
clr1 P7.6 ;[INF] 3, 2
|
||
clr1 PM7.6 ;[INF] 3, 2
|
||
??eb01_acc_read:
|
||
??eb00_acc_read:
|
||
; line 130 : }
|
||
?L0013:
|
||
; line 131 : return ( ERR_SUCCESS );
|
||
$DGL 0,9
|
||
clrw bc ;[INF] 1, 1
|
||
; line 132 : }
|
||
$DGL 0,10
|
||
??ef_acc_read:
|
||
ret ;[INF] 1, 6
|
||
??ee_acc_read:
|
||
; line 133 :
|
||
; line 134 :
|
||
; line 135 :
|
||
; line 136 : /*=========================================================
|
||
; line 137 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD><54><EFBFBD>߃A<DF83>N<EFBFBD>Z<EFBFBD>X<EFBFBD>@<40><><EFBFBD>C<EFBFBD>g
|
||
; line 138 : ========================================================*/
|
||
; line 139 : task_status_immed acc_write( )
|
||
; line 140 : {
|
||
_acc_write:
|
||
$DGL 1,117
|
||
??bf_acc_write:
|
||
; line 141 : iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_A
|
||
; DRS], vreg_ctr[VREG_C_ACC_W_BUF] );
|
||
$DGL 0,2
|
||
mov x,!_vreg_ctr+68 ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,!_vreg_ctr+67 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_write_a_byte ;[INF] 3, 3
|
||
addw sp,#04H ; 4 ;[INF] 2, 1
|
||
; line 142 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
|
||
$DGL 0,3
|
||
set1 !_vreg_ctr+17.3 ;[INF] 4, 2
|
||
; line 143 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
|
||
$DGL 0,4
|
||
mov a,!_vreg_ctr+25 ;[INF] 3, 1
|
||
and a,#08H ; 8 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0017 ;[INF] 2, 4
|
||
; line 144 : {
|
||
??bb00_acc_write:
|
||
; line 145 : IRQ0_ast;
|
||
$DGL 0,6
|
||
??bb01_acc_write:
|
||
clr1 P7.6 ;[INF] 3, 2
|
||
clr1 PM7.6 ;[INF] 3, 2
|
||
??eb01_acc_write:
|
||
??eb00_acc_write:
|
||
; line 146 : }
|
||
?L0017:
|
||
; line 147 : return ( ERR_SUCCESS );
|
||
$DGL 0,8
|
||
clrw bc ;[INF] 1, 1
|
||
; line 148 : }
|
||
$DGL 0,9
|
||
??ef_acc_write:
|
||
ret ;[INF] 1, 6
|
||
??ee_acc_write:
|
||
; line 149 :
|
||
; line 150 :
|
||
; line 151 :
|
||
; line 152 : /*=========================================================
|
||
; line 153 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD>E<EFBFBD><45><EFBFBD>g<EFBFBD><67><EFBFBD>[<5B>h<EFBFBD>ɃZ<C983>b<EFBFBD>g
|
||
; line 154 : todo <20><><EFBFBD>̃<EFBFBD><CC83>[<5B>h<EFBFBD><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~<7E>߂<EFBFBD><DF82><EFBFBD><EFBFBD>A<EFBFBD><41><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 155 : <20><><EFBFBD>荞<EFBFBD>݃<EFBFBD><DD83>[<5B>`<60><><EFBFBD>ȂǂŃJ<C583>E<EFBFBD><45><EFBFBD>g<EFBFBD><67><EFBFBD>肪<EFBFBD>K<EFBFBD>v
|
||
; line 156 : ========================================================*/
|
||
; line 157 : task_status_immed acc_hosu_set( )
|
||
; line 158 : {
|
||
_acc_hosu_set:
|
||
$DGL 1,131
|
||
push hl ;[INF] 1, 1
|
||
subw sp,#0AH ;[INF] 2, 1
|
||
movw hl,sp ;[INF] 3, 1
|
||
??bf_acc_hosu_set:
|
||
; line 159 : u8 str_send_buf[4];
|
||
; line 160 :
|
||
; line 161 : iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI );
|
||
$DGL 0,4
|
||
movw ax,#0FH ; 15 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_read_a_byte ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
; line 162 : if( iic_mcu_bus_status == ERR_NOSLAVE )
|
||
$DGL 0,5
|
||
cmp !_iic_mcu_bus_status,#02H ; 2 ;[INF] 4, 1
|
||
bnz $?L0021 ;[INF] 2, 4
|
||
; line 163 : {
|
||
??bb00_acc_hosu_set:
|
||
; line 164 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
|
||
$DGL 0,7
|
||
set1 !_vreg_ctr+14.1 ;[INF] 4, 2
|
||
; line 165 : #ifdef _MCU_BSR_
|
||
; line 166 : // PMK23 = 1;
|
||
; line 167 : #endif
|
||
; line 168 : return ( ERR_SUCCESS ); // <20>Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>^<5E>X<EFBFBD>N<EFBFBD>͍폜<CD8D><ED8F9C><EFBFBD>Ȃ<EFBFBD>
|
||
; <20>Ă͂Ȃ<CD82><C882>Ȃ<EFBFBD>
|
||
$DGL 0,11
|
||
clrw bc ;[INF] 1, 1
|
||
br $?L0020 ;[INF] 2, 3
|
||
??eb00_acc_hosu_set:
|
||
; line 169 : }else{
|
||
?L0021:
|
||
??bb01_acc_hosu_set:
|
||
; line 170 : vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR;
|
||
$DGL 0,13
|
||
clr1 !_vreg_ctr+14.1 ;[INF] 4, 2
|
||
??eb01_acc_hosu_set:
|
||
; line 171 : }
|
||
; line 172 :
|
||
; line 173 :
|
||
; line 174 : str_send_buf[1] = 0x00; // ctrl2 HPF:normal, filterd, H
|
||
; PF for IRQ : dis/dis, HPF coeff:norm
|
||
$DGL 0,17
|
||
mov [hl+7],#00H ; str_send_buf,0 ;[INF] 3, 1
|
||
; line 175 : #ifdef _MODEL_WM0_
|
||
; line 176 : # ifdef _MODEL_WM0_TEG2_CTRC_
|
||
; line 177 : str_send_buf[2] = 0x02; // <20><><EFBFBD>H<EFBFBD><48><EFBFBD>ꕔ<EFBFBD>Ⴄ
|
||
; line 178 : # else
|
||
; line 179 :
|
||
; line 180 : str_send_buf[2] = 0x10; // 3 IRQ pol :Active HI, Dr
|
||
; ive:Pushpull,
|
||
; line 181 : /// IRQ2flg latch: auto cl
|
||
; ear after read, IRQ2 conf: IRQ( fall,shock,...)
|
||
; line 182 : /// 1 : auto cl
|
||
; ear after read, conf: data ready
|
||
; line 183 : # endif
|
||
; line 184 : #else
|
||
; line 185 : # ifdef _MODEL_CTR_JIKKI_
|
||
; line 186 : str_send_buf[2] = 0x10;
|
||
; line 187 : # else
|
||
; line 188 : str_send_buf[2] = 0x02; // 3 IRQ pol :Active HI, Dr
|
||
; ive:Pushpull,
|
||
$DGL 0,31
|
||
mov [hl+8],#02H ; str_send_buf,2 ;[INF] 3, 1
|
||
; line 189 : /// IRQ2flg latch: auto cl
|
||
; ear after read, IRQ2 conf: IRQ( fall,shock,...)
|
||
; line 190 : /// 1 : auto cl
|
||
; ear after read, conf: data ready
|
||
; line 191 : # endif
|
||
; line 192 : #endif
|
||
; line 193 : str_send_buf[3] = 0x80; // ctrl3 block update:enable, M
|
||
; SB first, scale: +-2G(default), selftest: dis
|
||
$DGL 0,36
|
||
mov [hl+9],#080H ; str_send_buf,128 ;[INF] 3, 1
|
||
; line 194 :
|
||
; line 195 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] &
|
||
; line 196 : ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_A
|
||
; CQ ) ) == 0 )
|
||
$DGL 0,39
|
||
mov a,!_vreg_ctr+64 ;[INF] 3, 1
|
||
and a,#03H ; 3 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0023 ;[INF] 2, 4
|
||
; line 197 : {
|
||
??bb02_acc_hosu_set:
|
||
; line 198 : #ifdef _MCU_BSR_
|
||
; line 199 : PMK23 = 1;
|
||
$DGL 0,42
|
||
set1 MK2H.7 ;[INF] 3, 2
|
||
; line 200 : #endif
|
||
; line 201 : // <20><><EFBFBD>S<EFBFBD><53><EFBFBD>~
|
||
; line 202 : str_send_buf[0] =
|
||
; line 203 : ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 |
|
||
; ACC_BITS_ALL_AXIS_ON );
|
||
$DGL 0,46
|
||
mov [hl+6],#07H ; str_send_buf,7 ;[INF] 3, 1
|
||
??eb02_acc_hosu_set:
|
||
; line 204 : }
|
||
$DGL 0,47
|
||
br $?L0024 ;[INF] 2, 3
|
||
?L0023:
|
||
; line 205 : else
|
||
; line 206 : {
|
||
??bb03_acc_hosu_set:
|
||
; line 207 : #ifdef _MCU_BSR_
|
||
; line 208 : PMK23 = 0;
|
||
$DGL 0,51
|
||
clr1 MK2H.7 ;[INF] 3, 2
|
||
; line 209 : #endif
|
||
; line 210 : // 100Hz <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
; line 211 : str_send_buf[0] =
|
||
; line 212 : ( ACC_BITS_PM_NORM << ACC_bP_PM0
|
||
; line 213 : | ACC_BITS_DR_100Hz << ACC_bP_DR0
|
||
; line 214 : | ACC_BITS_ALL_AXIS_ON );
|
||
$DGL 0,57
|
||
mov [hl+6],#02FH ; str_send_buf,47 ;[INF] 3, 1
|
||
??eb03_acc_hosu_set:
|
||
; line 215 : }
|
||
?L0024:
|
||
; line 216 : iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, s
|
||
; tr_send_buf );
|
||
$DGL 0,59
|
||
movw ax,hl ;[INF] 1, 1
|
||
addw ax,#06H ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
movw ax,#04H ; 4 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#0A0H ; 160 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#030H ; 48 ;[INF] 2, 1
|
||
call !_iic_mcu_write ;[INF] 3, 3
|
||
addw sp,#06H ; 6 ;[INF] 2, 1
|
||
; line 217 :
|
||
; line 218 : // <20>J<EFBFBD><4A><EFBFBD>ǂ<EFBFBD>
|
||
; line 219 : if( ACC_VALID == 1 )
|
||
$DGL 0,62
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0510H ; 1296 ;[INF] 3, 1
|
||
mov1 CY,[hl].5 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0027 ;[INF] 2, 4
|
||
; line 220 : {
|
||
??bb04_acc_hosu_set:
|
||
; line 221 : if( system_status.pwr_state == ON )
|
||
$DGL 0,64
|
||
cmp !_system_status,#03H ; 3 ;[INF] 4, 1
|
||
bnz $?L0027 ;[INF] 2, 4
|
||
; line 222 : {
|
||
??bb05_acc_hosu_set:
|
||
; line 223 : u8 temp[6];
|
||
; line 224 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6
|
||
; , temp );
|
||
$DGL 0,67
|
||
movw ax,hl ;[INF] 1, 1
|
||
call !bs_F0038 ;[INF] 3, 3
|
||
??eb05_acc_hosu_set:
|
||
; line 225 : }
|
||
?L0027:
|
||
??eb04_acc_hosu_set:
|
||
; line 226 : }
|
||
; line 227 : return ( ERR_SUCCESS );
|
||
$DGL 0,70
|
||
clrw bc ;[INF] 1, 1
|
||
; line 228 : }
|
||
?L0020:
|
||
$DGL 0,71
|
||
??ef_acc_hosu_set:
|
||
addw sp,#0AH ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_acc_hosu_set:
|
||
; line 229 :
|
||
; line 230 :
|
||
; line 231 :
|
||
; line 232 : /* ========================================================
|
||
; line 233 : <20><><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Z<EFBFBD><5A><EFBFBD>T<EFBFBD><54><EFBFBD>荞<EFBFBD><E88D9E>
|
||
; line 234 : I2C<32><43><EFBFBD>g<EFBFBD>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>̂ŁA<C581>ǂݏo<DD8F><6F><EFBFBD>^<5E>X<EFBFBD>N<EFBFBD>̓o<CC93>^<5E><><EFBFBD>s<EFBFBD><73><EFBFBD>̂<EFBFBD>
|
||
; line 235 : ======================================================== */
|
||
; line 236 : __interrupt void intp23_ACC_ready( )
|
||
; line 237 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_intp23_ACC_ready:
|
||
$DGL 1,165
|
||
push ax ;[INF] 1, 1
|
||
push bc ;[INF] 1, 1
|
||
push de ;[INF] 1, 1
|
||
push hl ;[INF] 1, 1
|
||
mov c,#0CH ;[INF] 2, 1
|
||
dec c ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
movw ax,_@SEGAX[c] ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
bnz $$-6 ;[INF] 2, 4
|
||
mov a,ES ;[INF] 2, 1
|
||
mov x,a ;[INF] 1, 1
|
||
mov a,CS ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
??bf_intp23_ACC_ready:
|
||
; line 238 : EI();
|
||
$DGL 0,2
|
||
ei ;[INF] 3, 4
|
||
; line 239 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 )
|
||
$DGL 0,3
|
||
mov a,!_vreg_ctr+64 ;[INF] 3, 1
|
||
and a,#03H ; 3 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0036 ;[INF] 2, 4
|
||
; line 240 : {
|
||
??bb00_intp23_ACC_ready:
|
||
; line 241 : if( ( system_status.pwr_state == ON ) || ( system_status
|
||
; .pwr_state == SLEEP ) )
|
||
$DGL 0,5
|
||
cmp !_system_status,#03H ; 3 ;[INF] 4, 1
|
||
bz $?L0035 ;[INF] 2, 4
|
||
cmp !_system_status,#05H ; 5 ;[INF] 4, 1
|
||
bnz $?L0036 ;[INF] 2, 4
|
||
?L0035:
|
||
; line 242 : {
|
||
??bb01_intp23_ACC_ready:
|
||
; line 243 : if( ACC_VALID )
|
||
$DGL 0,7
|
||
movw hl,#0510H ; 1296 ;[INF] 3, 1
|
||
mov1 CY,[hl].5 ;[INF] 2, 1
|
||
bnc $?L0036 ;[INF] 2, 4
|
||
; line 244 : {
|
||
??bb02_intp23_ACC_ready:
|
||
; line 245 : renge_task_immed_add( tsk_cbk_accero );
|
||
$DGL 0,9
|
||
movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1
|
||
call !_renge_task_immed_add ;[INF] 3, 3
|
||
??eb02_intp23_ACC_ready:
|
||
; line 246 : }
|
||
?L0036:
|
||
??eb01_intp23_ACC_ready:
|
||
; line 247 : }
|
||
??eb00_intp23_ACC_ready:
|
||
; line 248 : }
|
||
; line 249 : }
|
||
$DGL 0,13
|
||
??ef_intp23_ACC_ready:
|
||
pop ax ;[INF] 1, 1
|
||
mov CS,a ;[INF] 2, 1
|
||
mov a,x ;[INF] 1, 1
|
||
mov ES,a ;[INF] 2, 1
|
||
movw de,#_@SEGAX ;[INF] 3, 1
|
||
mov c,#06H ;[INF] 2, 1
|
||
pop ax ;[INF] 1, 1
|
||
movw [de],ax ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $$-5 ;[INF] 2, 4
|
||
pop hl ;[INF] 1, 1
|
||
pop de ;[INF] 1, 1
|
||
pop bc ;[INF] 1, 1
|
||
pop ax ;[INF] 1, 1
|
||
reti ;[INF] 2, 6
|
||
??ee_intp23_ACC_ready:
|
||
|
||
@@CODEL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c
|
||
;
|
||
; $FUNC tsk_cbk_accero(66)
|
||
; bc=(void)
|
||
; CODE SIZE= 104 bytes, CLOCK_SIZE= 103 clocks, STACK_SIZE= 22 bytes
|
||
;
|
||
; $CALL iic_mcu_read(78)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
|
||
;
|
||
; $CALL acc_hosu_set(83)
|
||
; bc=(void)
|
||
;
|
||
; $CALL set_irq(94)
|
||
; void=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL iic_mcu_read(99)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
|
||
;
|
||
; $CALL pedometer(108)
|
||
; void=(void)
|
||
;
|
||
; $FUNC acc_read(123)
|
||
; bc=(void)
|
||
; CODE SIZE= 35 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes
|
||
;
|
||
; $CALL iic_mcu_read_a_byte(124)
|
||
; bc=(int:ax, int:[sp+4])
|
||
;
|
||
; $FUNC acc_write(140)
|
||
; bc=(void)
|
||
; CODE SIZE= 36 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 8 bytes
|
||
;
|
||
; $CALL iic_mcu_write_a_byte(141)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
;
|
||
; $FUNC acc_hosu_set(158)
|
||
; bc=(void)
|
||
; CODE SIZE= 107 bytes, CLOCK_SIZE= 96 clocks, STACK_SIZE= 26 bytes
|
||
;
|
||
; $CALL iic_mcu_read_a_byte(161)
|
||
; bc=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL iic_mcu_write(216)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
|
||
;
|
||
; $CALL iic_mcu_read(224)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
|
||
;
|
||
; $FUNC intp23_ACC_ready(237)
|
||
; void=(void)
|
||
; CODE SIZE= 80 bytes, CLOCK_SIZE= 73 clocks, STACK_SIZE= 26 bytes
|
||
;
|
||
; $CALL renge_task_immed_add(245)
|
||
; bc=(pointer:ax)
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|