mirror of
https://github.com/rvtr/ctr_mcu.git
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dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
112 lines
2.9 KiB
NASM
112 lines
2.9 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no WDT.c
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; In-file : WDT.c
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; Asm-file : inter_asm\WDT.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, WDT.c
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$DGS MOD_NAM, WDT, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H
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$DGS BEG_FUN, ??bf_WDT_Restart, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0CH, 00H, 019H
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$DGS END_FUN, ??ef_WDT_Restart, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 03H
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PUBLIC _WDT_Restart
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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@@R_INIT CSEG UNIT64KP
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@@INIT DSEG BASEP
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@@DATA DSEG BASEP
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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LDR_CNSL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : #pragma sfr
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; line 2 :
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; line 3 :
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; line 4 : #include "incs_loader.h"
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; line 5 :
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; line 6 :
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; line 7 :
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; line 8 : //=========================================================
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; line 9 : // <20>E<EFBFBD>H<EFBFBD>b<EFBFBD>`<60>h<EFBFBD>b<EFBFBD>O<EFBFBD>^<5E>C<EFBFBD>}<7D>̃<EFBFBD><CC83>X<EFBFBD>^<5E>[<5B>g
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; line 10 : // 0xAC<41>̓}<7D>W<EFBFBD>b<EFBFBD>N
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; line 11 : void WDT_Restart( void )
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; line 12 : {
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LDR_CODE CSEG BASE
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_WDT_Restart:
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$DGL 1,19
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??bf_WDT_Restart:
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; line 13 : WDTE = WDT_RESTART_MAGIC;
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$DGL 0,2
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mov WDTE,#0ACH ; 172 ;[INF] 3, 1
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; line 14 : }
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$DGL 0,3
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??ef_WDT_Restart:
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ret ;[INF] 1, 6
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??ee_WDT_Restart:
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LDR_CODL CSEG
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@@BASE CSEG BASE
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END
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; *** Code Information ***
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;
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; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c
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;
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; $FUNC WDT_Restart(12)
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; void=(void)
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; CODE SIZE= 4 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
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; Target chip : uPD79F0104
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; Device file : E1.00b
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