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dc469bd4c6
ctr_mcu/branches/0.10(X3)/pm.prn
N2232 dc469bd4c6 0.10のX3対応版を登録 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
2010-06-23 07:16:15 +00:00

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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\pm.asm
Para-file:
In-file: inter_asm\pm.asm
Obj-file: pm.rel
Prn-file: pm.prn
Assemble list
ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
2 2
3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no pm.c
6 6 ; In-file : pm.c
7 7 ; Asm-file : inter_asm\pm.asm
8 8 ; Para-file :
9 9
10 10 $PROCESSOR(9F0104)
11 11 $DEBUG
12 12 $NODEBUGA
13 13 $KANJICODE SJIS
14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
15 15
16 16 $DGS FIL_NAM, .file, 0217H, 0FFFEH, 03FH, 067H, 01H, 00H
17 17 $DGS AUX_FIL, pm.c
18 18 $DGS MOD_NAM, pm, 00H, 0FFFEH, 00H, 077H, 00H, 00H
19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
36 36 $DGS AUX_TAG, 01H, 01EH
37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
45 45 $DGS AUX_EOS, 013H, 01H
46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
47 47 $DGS AUX_TAG, 01H, 025H
48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
52 52 $DGS AUX_EOS, 01EH, 01H
53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
54 54 $DGS AUX_TAG, 01H, 02FH
55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
62 62 $DGS AUX_EOS, 025H, 01H
63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
64 64 $DGS AUX_TAG, 04H, 041H
65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
70 70 $DGS AUX_BIT, 00H, 01H
71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
72 72 $DGS AUX_BIT, 00H, 01H
73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
74 74 $DGS AUX_BIT, 00H, 01H
75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
76 76 $DGS AUX_BIT, 00H, 01H
77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
80 80 $DGS AUX_EOS, 02FH, 04H
81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
82 82 $DGS AUX_TAG, 01H, 06DH
83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
86 86 $DGS AUX_EOS, 041H, 01H
87 87 $DGS LAB_SYM, bs_F0153, U, U, 00H, 06H, 00H, 00H
88 88 $DGS LAB_SYM, es_F0153, U, U, 00H, 06H, 00H, 00H
89 89 $DGS LAB_SYM, bs_F0154, U, U, 00H, 06H, 00H, 00H
90 90 $DGS LAB_SYM, es_F0154, U, U, 00H, 06H, 00H, 00H
91 91 $DGS LAB_SYM, bs_F0155, U, U, 00H, 06H, 00H, 00H
92 92 $DGS LAB_SYM, es_F0155, U, U, 00H, 06H, 00H, 00H
93 93 $DGS LAB_SYM, bs_F0151, U, U, 00H, 06H, 00H, 00H
94 94 $DGS LAB_SYM, es_F0151, U, U, 00H, 06H, 00H, 00H
95 95 $DGS LAB_SYM, bs_S0152, U, U, 00H, 06H, 00H, 00H
96 96 $DGS LAB_SYM, es_S0152, U, U, 00H, 06H, 00H, 00H
97 97 $DGS LAB_SYM, bs_F0149, U, U, 00H, 06H, 00H, 00H
98 98 $DGS LAB_SYM, es_F0149, U, U, 00H, 06H, 00H, 00H
99 99 $DGS LAB_SYM, bs_F0150, U, U, 00H, 06H, 00H, 00H
100 100 $DGS LAB_SYM, es_F0150, U, U, 00H, 06H, 00H, 00H
101 101 $DGS LAB_SYM, bs_F0146, U, U, 00H, 06H, 00H, 00H
102 102 $DGS LAB_SYM, es_F0146, U, U, 00H, 06H, 00H, 00H
103 103 $DGS LAB_SYM, bs_F0147, U, U, 00H, 06H, 00H, 00H
104 104 $DGS LAB_SYM, es_F0147, U, U, 00H, 06H, 00H, 00H
105 105 $DGS LAB_SYM, bs_F0148, U, U, 00H, 06H, 00H, 00H
106 106 $DGS LAB_SYM, es_F0148, U, U, 00H, 06H, 00H, 00H
107 107 $DGS LAB_SYM, bs_S0144, U, U, 00H, 06H, 00H, 00H
108 108 $DGS LAB_SYM, es_S0144, U, U, 00H, 06H, 00H, 00H
109 109 $DGS LAB_SYM, bs_F0145, U, U, 00H, 06H, 00H, 00H
110 110 $DGS LAB_SYM, es_F0145, U, U, 00H, 06H, 00H, 00H
111 111 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
112 112 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
113 113 $DGS STA_SYM, _BT_PARAM, U, U, 0500CH, 03H, 01H, 0FH
114 114 $DGS AUX_STR, 00H, 00H, 01C0H, 07H, 040H, 00H, 00H, 00H
115 115 $DGS STA_SYM, _BT_PANA_RCOMP, U, U, 0500CH, 03H, 00H, 00H
116 116 $DGS STA_SYM, _BT_PANA_TEMPCOUP, U, U, 05006H, 03H, 00H, 00H
117 117 $DGS STA_SYM, _BT_PANA_TEMPCODN, U, U, 05006H, 03H, 00H, 00H
118 118 $DGS GLV_SYM, _PM_init, U, U, 01H, 026H, 01H, 02H
119 119 $DGS AUX_FUN, 00H, U, U, 09AH, 00H, 00H
120 120 $DGS BEG_FUN, ??bf_PM_init, U, U, 00H, 065H, 01H, 00H
121 121 $DGS AUX_BEG, 02EH, 08H, 07CH
122 122 $DGS AUT_VAR, _temp, 07H, 0FFFFH, 0CH, 01H, 00H, 00H
123 123 $DGS AUT_VAR, _origParam, 03H, 0FFFFH, 0CH, 01H, 01H, 03H
124 124 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H
125 125 $DGS STR_STR, .7fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
126 126 $DGS AUX_TAG, 02H, 073H
127 127 $DGS MEB_STR, _lsb, 00H, 0FFFFH, 0CH, 08H, 00H, 00H
128 128 $DGS MEB_STR, _msb, 01H, 0FFFFH, 0CH, 08H, 00H, 00H
129 129 $DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H
130 130 $DGS AUX_EOS, 06DH, 02H
131 131 $DGS UNI_TAG, .6fake, 00H, 0FFFEH, 09H, 0CH, 01H, 00H
132 132 $DGS AUX_TAG, 02H, 07AH
133 133 $DGS MEB_UNI, __u16, 00H, 0FFFFH, 0DH, 0BH, 00H, 00H
134 134 $DGS MEB_UNI, _chars, 00H, 0FFFFH, 08H, 0BH, 01H, 00H
135 135 $DGS AUX_STR, 06DH, 00H, 02H, 00H, 00H, 00H, 00H, 00H
136 136 $DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H
137 137 $DGS AUX_EOS, 073H, 02H
138 138 $DGS AUT_VAR, _dat_16, 00H, 0FFFFH, 09H, 01H, 01H, 00H
139 139 $DGS AUX_STR, 073H, 00H, 02H, 00H, 00H, 00H, 00H, 00H
140 140 $DGS BEG_BLK, ??bb00_PM_init, U, U, 00H, 064H, 01H, 00H
141 141 $DGS AUX_BEG, 016H, 00H, 080H
142 142 $DGS END_BLK, ??eb00_PM_init, U, U, 00H, 064H, 01H, 00H
143 143 $DGS AUX_END, 019H
144 144 $DGS BEG_BLK, ??bb01_PM_init, U, U, 00H, 064H, 01H, 00H
145 145 $DGS AUX_BEG, 01BH, 00H, 082H
146 146 $DGS BEG_BLK, ??bb02_PM_init, U, U, 00H, 064H, 01H, 00H
147 147 $DGS AUX_BEG, 030H, 00H, 084H
148 148 $DGS BEG_BLK, ??bb03_PM_init, U, U, 00H, 064H, 01H, 00H
149 149 $DGS AUX_BEG, 030H, 00H, 08AH
150 150 $DGS END_BLK, ??eb03_PM_init, U, U, 00H, 064H, 01H, 00H
151 151 $DGS AUX_END, 030H
152 152 $DGS END_BLK, ??eb02_PM_init, U, U, 00H, 064H, 01H, 00H
153 153 $DGS AUX_END, 030H
154 154 $DGS BEG_BLK, ??bb04_PM_init, U, U, 00H, 064H, 01H, 00H
155 155 $DGS AUX_BEG, 033H, 00H, 08EH
156 156 $DGS END_BLK, ??eb04_PM_init, U, U, 00H, 064H, 01H, 00H
157 157 $DGS AUX_END, 040H
158 158 $DGS BEG_BLK, ??bb05_PM_init, U, U, 00H, 064H, 01H, 00H
159 159 $DGS AUX_BEG, 04FH, 00H, 092H
160 160 $DGS END_BLK, ??eb05_PM_init, U, U, 00H, 064H, 01H, 00H
161 161 $DGS AUX_END, 051H
162 162 $DGS BEG_BLK, ??bb06_PM_init, U, U, 00H, 064H, 01H, 00H
163 163 $DGS AUX_BEG, 051H, 00H, 00H
164 164 $DGS END_BLK, ??eb06_PM_init, U, U, 00H, 064H, 01H, 00H
165 165 $DGS AUX_END, 053H
166 166 $DGS END_BLK, ??eb01_PM_init, U, U, 00H, 064H, 01H, 00H
167 167 $DGS AUX_END, 05DH
168 168 $DGS END_FUN, ??ef_PM_init, U, U, 00H, 065H, 01H, 00H
169 169 $DGS AUX_END, 068H
170 170 $DGS GLV_SYM, _PM_bt_temp_update, U, U, 0AH, 026H, 01H, 02H
171 171 $DGS AUX_FUN, 041H, U, U, 0B8H, 00H, 00H
172 172 $DGS BEG_FUN, ??bf_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H
173 173 $DGS AUX_BEG, 0A3H, 02H, 0A2H
174 174 $DGS STA_SYM, _count, ?L0018, U, 0CH, 03H, 00H, 00H
175 175 $DGS STA_SYM, _rawdat_old, ?L0019, U, 0CH, 03H, 00H, 00H
176 176 $DGS STA_SYM, _temperature, ?L0020, U, 03H, 03H, 00H, 00H
177 177 $DGS AUT_VAR, _newrcomp, 00H, 0FFFFH, 0DH, 01H, 00H, 00H
178 178 $DGS BEG_BLK, ??bb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
179 179 $DGS AUX_BEG, 0EH, 00H, 0A6H
180 180 $DGS END_BLK, ??eb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
181 181 $DGS AUX_END, 013H
182 182 $DGS BEG_BLK, ??bb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
183 183 $DGS AUX_BEG, 017H, 00H, 0A8H
184 184 $DGS BEG_BLK, ??bb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
185 185 $DGS AUX_BEG, 01AH, 00H, 0ACH
186 186 $DGS END_BLK, ??eb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
187 187 $DGS AUX_END, 01CH
188 188 $DGS BEG_BLK, ??bb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
189 189 $DGS AUX_BEG, 01EH, 00H, 0B0H
190 190 $DGS END_BLK, ??eb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
191 191 $DGS AUX_END, 020H
192 192 $DGS BEG_BLK, ??bb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
193 193 $DGS AUX_BEG, 028H, 00H, 00H
194 194 $DGS END_BLK, ??eb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
195 195 $DGS AUX_END, 02AH
196 196 $DGS END_BLK, ??eb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H
197 197 $DGS AUX_END, 02BH
198 198 $DGS END_FUN, ??ef_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H
199 199 $DGS AUX_END, 02FH
200 200 $DGS GLV_SYM, _PM_LCD_on, U, U, 0CH, 026H, 01H, 02H
201 201 $DGS AUX_FUN, 00H, U, U, 0C3H, 00H, 00H
202 202 $DGS BEG_FUN, ??bf_PM_LCD_on, U, U, 00H, 065H, 01H, 00H
203 203 $DGS AUX_BEG, 0E3H, 02H, 0BDH
204 204 $DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
205 205 $DGS BEG_BLK, ??bb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H
206 206 $DGS AUX_BEG, 016H, 00H, 00H
207 207 $DGS END_BLK, ??eb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H
208 208 $DGS AUX_END, 01CH
209 209 $DGS END_FUN, ??ef_PM_LCD_on, U, U, 00H, 065H, 01H, 00H
210 210 $DGS AUX_END, 023H
211 211 $DGS GLV_SYM, _PM_LCD_off, U, U, 01H, 026H, 01H, 02H
212 212 $DGS AUX_FUN, 00H, U, U, 0DFH, 00H, 00H
213 213 $DGS BEG_FUN, ??bf_PM_LCD_off, U, U, 00H, 065H, 01H, 00H
214 214 $DGS AUX_BEG, 0109H, 02H, 0C7H
215 215 $DGS BEG_BLK, ??bb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
216 216 $DGS AUX_BEG, 0AH, 00H, 0CBH
217 217 $DGS REG_VAR, _tot, 06H, 0FFFFH, 010CH, 04H, 01H, 00H
218 218 $DGS AUX_STR, 00H, 0BH, 01H, 00H, 00H, 00H, 00H, 00H
219 219 $DGS BEG_BLK, ??bb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
220 220 $DGS AUX_BEG, 011H, 00H, 0CDH
221 221 $DGS BEG_BLK, ??bb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
222 222 $DGS AUX_BEG, 013H, 00H, 0D1H
223 223 $DGS END_BLK, ??eb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
224 224 $DGS AUX_END, 013H
225 225 $DGS BEG_BLK, ??bb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
226 226 $DGS AUX_BEG, 015H, 00H, 0D5H
227 227 $DGS END_BLK, ??eb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
228 228 $DGS AUX_END, 015H
229 229 $DGS BEG_BLK, ??bb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
230 230 $DGS AUX_BEG, 016H, 00H, 00H
231 231 $DGS END_BLK, ??eb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
232 232 $DGS AUX_END, 016H
233 233 $DGS END_BLK, ??eb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
234 234 $DGS AUX_END, 017H
235 235 $DGS END_BLK, ??eb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H
236 236 $DGS AUX_END, 019H
237 237 $DGS END_FUN, ??ef_PM_LCD_off, U, U, 00H, 065H, 01H, 00H
238 238 $DGS AUX_END, 028H
239 239 $DGS GLV_SYM, _PM_BL_set, U, U, 0CH, 026H, 01H, 02H
240 240 $DGS AUX_FUN, 00H, U, U, 0112H, 00H, 00H
241 241 $DGS BEG_FUN, ??bf_PM_BL_set, U, U, 00H, 065H, 01H, 00H
242 242 $DGS AUX_BEG, 013AH, 06H, 0E6H
243 243 $DGS FUN_ARG, _dat, 04H, 0FFFFH, 0CH, 09H, 00H, 00H
244 244 $DGS AUT_VAR, _blset, 03H, 0FFFFH, 0CH, 01H, 00H, 00H
245 245 $DGS AUT_VAR, _intset, 02H, 0FFFFH, 0CH, 01H, 00H, 00H
246 246 $DGS BEG_BLK, ??bb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H
247 247 $DGS AUX_BEG, 010H, 00H, 0EAH
248 248 $DGS END_BLK, ??eb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H
249 249 $DGS AUX_END, 013H
250 250 $DGS BEG_BLK, ??bb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H
251 251 $DGS AUX_BEG, 015H, 00H, 0EEH
252 252 $DGS END_BLK, ??eb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H
253 253 $DGS AUX_END, 018H
254 254 $DGS BEG_BLK, ??bb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H
255 255 $DGS AUX_BEG, 01CH, 00H, 0F2H
256 256 $DGS END_BLK, ??eb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H
257 257 $DGS AUX_END, 01FH
258 258 $DGS BEG_BLK, ??bb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H
259 259 $DGS AUX_BEG, 021H, 00H, 0F6H
260 260 $DGS END_BLK, ??eb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H
261 261 $DGS AUX_END, 024H
262 262 $DGS BEG_BLK, ??bb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H
263 263 $DGS AUX_BEG, 033H, 00H, 0FAH
264 264 $DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 01H, 00H
265 265 $DGS AUX_STR, 00H, 034H, 01H, 00H, 00H, 00H, 00H, 00H
266 266 $DGS BEG_BLK, ??bb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H
267 267 $DGS AUX_BEG, 037H, 00H, 0FCH
268 268 $DGS BEG_BLK, ??bb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H
269 269 $DGS AUX_BEG, 039H, 00H, 0100H
270 270 $DGS END_BLK, ??eb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H
271 271 $DGS AUX_END, 039H
272 272 $DGS BEG_BLK, ??bb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H
273 273 $DGS AUX_BEG, 03BH, 00H, 0104H
274 274 $DGS END_BLK, ??eb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H
275 275 $DGS AUX_END, 03BH
276 276 $DGS BEG_BLK, ??bb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H
277 277 $DGS AUX_BEG, 03CH, 00H, 010CH
278 278 $DGS END_BLK, ??eb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H
279 279 $DGS AUX_END, 03CH
280 280 $DGS END_BLK, ??eb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H
281 281 $DGS AUX_END, 03DH
282 282 $DGS END_BLK, ??eb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H
283 283 $DGS AUX_END, 03EH
284 284 $DGS BEG_BLK, ??bb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H
285 285 $DGS AUX_BEG, 043H, 00H, 00H
286 286 $DGS END_BLK, ??eb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H
287 287 $DGS AUX_END, 045H
288 288 $DGS END_FUN, ??ef_PM_BL_set, U, U, 00H, 065H, 01H, 00H
289 289 $DGS AUX_END, 049H
290 290 $DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 026H, 01H, 02H
291 291 $DGS AUX_FUN, 00H, U, U, 0119H, 00H, 00H
292 292 $DGS BEG_FUN, ??bf_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H
293 293 $DGS AUX_BEG, 018BH, 02H, 0119H
294 294 $DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
295 295 $DGS END_FUN, ??ef_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H
296 296 $DGS AUX_END, 07H
297 297 $DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 026H, 01H, 02H
298 298 $DGS AUX_FUN, 041H, U, U, 011FH, 00H, 00H
299 299 $DGS BEG_FUN, ??bf_tski_vcom_set, U, U, 00H, 065H, 01H, 00H
300 300 $DGS AUX_BEG, 01C2H, 00H, 011FH
301 301 $DGS END_FUN, ??ef_tski_vcom_set, U, U, 00H, 065H, 01H, 00H
302 302 $DGS AUX_END, 04H
303 303 $DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 026H, 01H, 02H
304 304 $DGS AUX_FUN, 00H, U, U, 0142H, 00H, 00H
305 305 $DGS BEG_FUN, ??bf_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H
306 306 $DGS AUX_BEG, 01D2H, 02H, 0124H
307 307 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
308 308 $DGS BEG_BLK, ??bb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
309 309 $DGS AUX_BEG, 07H, 00H, 0128H
310 310 $DGS END_BLK, ??eb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
311 311 $DGS AUX_END, 08H
312 312 $DGS BEG_BLK, ??bb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
313 313 $DGS AUX_BEG, 012H, 00H, 012CH
314 314 $DGS END_BLK, ??eb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
315 315 $DGS AUX_END, 014H
316 316 $DGS BEG_BLK, ??bb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
317 317 $DGS AUX_BEG, 018H, 00H, 0130H
318 318 $DGS END_BLK, ??eb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
319 319 $DGS AUX_END, 018H
320 320 $DGS BEG_BLK, ??bb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
321 321 $DGS AUX_BEG, 019H, 00H, 0134H
322 322 $DGS END_BLK, ??eb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
323 323 $DGS AUX_END, 019H
324 324 $DGS BEG_BLK, ??bb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
325 325 $DGS AUX_BEG, 030H, 00H, 0138H
326 326 $DGS END_BLK, ??eb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
327 327 $DGS AUX_END, 032H
328 328 $DGS BEG_BLK, ??bb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
329 329 $DGS AUX_BEG, 033H, 00H, 013CH
330 330 $DGS END_BLK, ??eb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
331 331 $DGS AUX_END, 033H
332 332 $DGS BEG_BLK, ??bb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
333 333 $DGS AUX_BEG, 035H, 00H, 00H
334 334 $DGS END_BLK, ??eb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H
335 335 $DGS AUX_END, 035H
336 336 $DGS END_FUN, ??ef_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H
337 337 $DGS AUX_END, 069H
338 338 $DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 026H, 01H, 02H
339 339 $DGS AUX_FUN, 00H, U, U, 0150H, 00H, 00H
340 340 $DGS BEG_FUN, ??bf_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H
341 341 $DGS AUX_BEG, 0247H, 00H, 0146H
342 342 $DGS BEG_BLK, ??bb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H
343 343 $DGS AUX_BEG, 07H, 00H, 014AH
344 344 $DGS END_BLK, ??eb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H
345 345 $DGS AUX_END, 07H
346 346 $DGS BEG_BLK, ??bb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H
347 347 $DGS AUX_BEG, 08H, 00H, 00H
348 348 $DGS END_BLK, ??eb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H
349 349 $DGS AUX_END, 08H
350 350 $DGS END_FUN, ??ef_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H
351 351 $DGS AUX_END, 020H
352 352 $DGS GLV_SYM, _tsk_batt, U, U, 01H, 026H, 01H, 02H
353 353 $DGS AUX_FUN, 00H, U, U, 01A1H, 00H, 00H
354 354 $DGS BEG_FUN, ??bf_tsk_batt, U, U, 00H, 065H, 01H, 00H
355 355 $DGS AUX_BEG, 027DH, 00H, 0157H
356 356 $DGS STA_SYM, _task_interval, ?L0077, U, 0CH, 03H, 00H, 00H
357 357 $DGS STA_SYM, _charge_hys, ?L0078, U, 0CH, 03H, 00H, 00H
358 358 $DGS STA_SYM, _pm_extdc_old, ?L0079, U, 034CH, 028H, 00H, 00H
359 359 $DGS BEG_BLK, ??bb00_tsk_batt, U, U, 00H, 064H, 01H, 00H
360 360 $DGS AUX_BEG, 07H, 00H, 015BH
361 361 $DGS END_BLK, ??eb00_tsk_batt, U, U, 00H, 064H, 01H, 00H
362 362 $DGS AUX_END, 09H
363 363 $DGS BEG_BLK, ??bb01_tsk_batt, U, U, 00H, 064H, 01H, 00H
364 364 $DGS AUX_BEG, 0BH, 00H, 015FH
365 365 $DGS END_BLK, ??eb01_tsk_batt, U, U, 00H, 064H, 01H, 00H
366 366 $DGS AUX_END, 0DH
367 367 $DGS BEG_BLK, ??bb02_tsk_batt, U, U, 00H, 064H, 01H, 00H
368 368 $DGS AUX_BEG, 012H, 00H, 0161H
369 369 $DGS BEG_BLK, ??bb03_tsk_batt, U, U, 00H, 064H, 01H, 00H
370 370 $DGS AUX_BEG, 015H, 00H, 0163H
371 371 $DGS BEG_BLK, ??bb04_tsk_batt, U, U, 00H, 064H, 01H, 00H
372 372 $DGS AUX_BEG, 016H, 00H, 0165H
373 373 $DGS BEG_BLK, ??bb05_tsk_batt, U, U, 00H, 064H, 01H, 00H
374 374 $DGS AUX_BEG, 016H, 00H, 0169H
375 375 $DGS END_BLK, ??eb05_tsk_batt, U, U, 00H, 064H, 01H, 00H
376 376 $DGS AUX_END, 016H
377 377 $DGS BEG_BLK, ??bb06_tsk_batt, U, U, 00H, 064H, 01H, 00H
378 378 $DGS AUX_BEG, 016H, 00H, 0171H
379 379 $DGS END_BLK, ??eb06_tsk_batt, U, U, 00H, 064H, 01H, 00H
380 380 $DGS AUX_END, 016H
381 381 $DGS END_BLK, ??eb04_tsk_batt, U, U, 00H, 064H, 01H, 00H
382 382 $DGS AUX_END, 016H
383 383 $DGS END_BLK, ??eb03_tsk_batt, U, U, 00H, 064H, 01H, 00H
384 384 $DGS AUX_END, 018H
385 385 $DGS BEG_BLK, ??bb07_tsk_batt, U, U, 00H, 064H, 01H, 00H
386 386 $DGS AUX_BEG, 01AH, 00H, 0173H
387 387 $DGS BEG_BLK, ??bb08_tsk_batt, U, U, 00H, 064H, 01H, 00H
388 388 $DGS AUX_BEG, 01BH, 00H, 0175H
389 389 $DGS BEG_BLK, ??bb09_tsk_batt, U, U, 00H, 064H, 01H, 00H
390 390 $DGS AUX_BEG, 01BH, 00H, 0179H
391 391 $DGS END_BLK, ??eb09_tsk_batt, U, U, 00H, 064H, 01H, 00H
392 392 $DGS AUX_END, 01BH
393 393 $DGS BEG_BLK, ??bb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H
394 394 $DGS AUX_BEG, 01BH, 00H, 0183H
395 395 $DGS END_BLK, ??eb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H
396 396 $DGS AUX_END, 01BH
397 397 $DGS END_BLK, ??eb08_tsk_batt, U, U, 00H, 064H, 01H, 00H
398 398 $DGS AUX_END, 01BH
399 399 $DGS END_BLK, ??eb07_tsk_batt, U, U, 00H, 064H, 01H, 00H
400 400 $DGS AUX_END, 01DH
401 401 $DGS END_BLK, ??eb02_tsk_batt, U, U, 00H, 064H, 01H, 00H
402 402 $DGS AUX_END, 01EH
403 403 $DGS BEG_BLK, ??bb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H
404 404 $DGS AUX_BEG, 024H, 00H, 0187H
405 405 $DGS END_BLK, ??eb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H
406 406 $DGS AUX_END, 026H
407 407 $DGS BEG_BLK, ??bb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H
408 408 $DGS AUX_BEG, 02AH, 00H, 018BH
409 409 $DGS END_BLK, ??eb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H
410 410 $DGS AUX_END, 02CH
411 411 $DGS BEG_BLK, ??bb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H
412 412 $DGS AUX_BEG, 034H, 00H, 018FH
413 413 $DGS END_BLK, ??eb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H
414 414 $DGS AUX_END, 037H
415 415 $DGS BEG_BLK, ??bb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H
416 416 $DGS AUX_BEG, 039H, 00H, 0193H
417 417 $DGS END_BLK, ??eb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H
418 418 $DGS AUX_END, 03CH
419 419 $DGS BEG_BLK, ??bb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H
420 420 $DGS AUX_BEG, 043H, 00H, 0195H
421 421 $DGS BEG_BLK, ??bb10_tsk_batt, U, U, 00H, 064H, 01H, 00H
422 422 $DGS AUX_BEG, 043H, 00H, 0199H
423 423 $DGS END_BLK, ??eb10_tsk_batt, U, U, 00H, 064H, 01H, 00H
424 424 $DGS AUX_END, 043H
425 425 $DGS BEG_BLK, ??bb11_tsk_batt, U, U, 00H, 064H, 01H, 00H
426 426 $DGS AUX_BEG, 043H, 00H, 00H
427 427 $DGS END_BLK, ??eb11_tsk_batt, U, U, 00H, 064H, 01H, 00H
428 428 $DGS AUX_END, 043H
429 429 $DGS END_BLK, ??eb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H
430 430 $DGS AUX_END, 043H
431 431 $DGS END_FUN, ??ef_tsk_batt, U, U, 00H, 065H, 01H, 00H
432 432 $DGS AUX_END, 04DH
433 433 $DGS GLV_SYM, _intp4_extdc, U, U, 0E001H, 026H, 01H, 02H
434 434 $DGS AUX_FUN, 00H, U, U, 01A7H, 00H, 00H
435 435 $DGS BEG_FUN, ??bf_intp4_extdc, U, U, 00H, 065H, 01H, 00H
436 436 $DGS AUX_BEG, 02D4H, 00H, 01A7H
437 437 $DGS END_FUN, ??ef_intp4_extdc, U, U, 00H, 065H, 01H, 00H
438 438 $DGS AUX_END, 03H
439 439 $DGS GLV_SYM, _intp5_shell, U, U, 0E001H, 026H, 01H, 02H
440 440 $DGS AUX_FUN, 00H, U, U, 01ADH, 00H, 00H
441 441 $DGS BEG_FUN, ??bf_intp5_shell, U, U, 00H, 065H, 01H, 00H
442 442 $DGS AUX_BEG, 02DFH, 00H, 01ADH
443 443 $DGS END_FUN, ??ef_intp5_shell, U, U, 00H, 065H, 01H, 00H
444 444 $DGS AUX_END, 03H
445 445 $DGS GLV_SYM, _intp6_PM_irq, U, U, 0E001H, 026H, 01H, 02H
446 446 $DGS AUX_FUN, 00H, U, U, 01B7H, 00H, 00H
447 447 $DGS BEG_FUN, ??bf_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H
448 448 $DGS AUX_BEG, 02E8H, 016H, 01B1H
449 449 $DGS BEG_BLK, ??bb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H
450 450 $DGS AUX_BEG, 03H, 00H, 00H
451 451 $DGS END_BLK, ??eb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H
452 452 $DGS AUX_END, 06H
453 453 $DGS END_FUN, ??ef_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H
454 454 $DGS AUX_END, 07H
455 455 $DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 026H, 01H, 02H
456 456 $DGS AUX_FUN, 041H, U, U, 01ECH, 00H, 00H
457 457 $DGS BEG_FUN, ??bf_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H
458 458 $DGS AUX_BEG, 02F8H, 02H, 01BEH
459 459 $DGS STA_SYM, _reg_shadow, ?L0112, U, 0CH, 03H, 00H, 00H
460 460 $DGS REG_VAR, _reg1_old, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
461 461 $DGS REG_VAR, _irq_work, 07H, 0FFFFH, 010CH, 04H, 00H, 00H
462 462 $DGS BEG_BLK, ??bb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
463 463 $DGS AUX_BEG, 09H, 00H, 01C2H
464 464 $DGS END_BLK, ??eb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
465 465 $DGS AUX_END, 0BH
466 466 $DGS BEG_BLK, ??bb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
467 467 $DGS AUX_BEG, 011H, 00H, 01C4H
468 468 $DGS BEG_BLK, ??bb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
469 469 $DGS AUX_BEG, 013H, 00H, 01C8H
470 470 $DGS END_BLK, ??eb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
471 471 $DGS AUX_END, 016H
472 472 $DGS BEG_BLK, ??bb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
473 473 $DGS AUX_BEG, 018H, 00H, 01CEH
474 474 $DGS END_BLK, ??eb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
475 475 $DGS AUX_END, 01BH
476 476 $DGS END_BLK, ??eb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
477 477 $DGS AUX_END, 01CH
478 478 $DGS BEG_BLK, ??bb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
479 479 $DGS AUX_BEG, 020H, 00H, 01D0H
480 480 $DGS BEG_BLK, ??bb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
481 481 $DGS AUX_BEG, 022H, 00H, 01D4H
482 482 $DGS END_BLK, ??eb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
483 483 $DGS AUX_END, 025H
484 484 $DGS BEG_BLK, ??bb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
485 485 $DGS AUX_BEG, 027H, 00H, 01DAH
486 486 $DGS END_BLK, ??eb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
487 487 $DGS AUX_END, 02AH
488 488 $DGS END_BLK, ??eb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
489 489 $DGS AUX_END, 02BH
490 490 $DGS BEG_BLK, ??bb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
491 491 $DGS AUX_BEG, 04BH, 00H, 01DEH
492 492 $DGS END_BLK, ??eb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
493 493 $DGS AUX_END, 04DH
494 494 $DGS BEG_BLK, ??bb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
495 495 $DGS AUX_BEG, 051H, 00H, 01E0H
496 496 $DGS BEG_BLK, ??bb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
497 497 $DGS AUX_BEG, 056H, 00H, 01E6H
498 498 $DGS END_BLK, ??eb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
499 499 $DGS AUX_END, 058H
500 500 $DGS END_BLK, ??eb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
501 501 $DGS AUX_END, 059H
502 502 $DGS BEG_BLK, ??bb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
503 503 $DGS AUX_BEG, 05EH, 00H, 00H
504 504 $DGS END_BLK, ??eb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H
505 505 $DGS AUX_END, 061H
506 506 $DGS END_FUN, ??ef_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H
507 507 $DGS AUX_END, 063H
508 508 $DGS STA_SYM, _PM_get_batt_left, U, U, 01H, 03H, 01H, 02H
509 509 $DGS AUX_FUN, 00H, U, U, 0200H, 00H, 00H
510 510 $DGS BEG_FUN, ??bf_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H
511 511 $DGS AUX_BEG, 0364H, 02H, 01F0H
512 512 $DGS BEG_BLK, ??bb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
513 513 $DGS AUX_BEG, 03H, 00H, 01F2H
514 514 $DGS BEG_BLK, ??bb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
515 515 $DGS AUX_BEG, 05H, 00H, 01FAH
516 516 $DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H
517 517 $DGS AUX_STR, 00H, 06H, 02H, 02H, 00H, 00H, 00H, 00H
518 518 $DGS END_BLK, ??eb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
519 519 $DGS AUX_END, 0DH
520 520 $DGS END_BLK, ??eb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
521 521 $DGS AUX_END, 010H
522 522 $DGS BEG_BLK, ??bb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
523 523 $DGS AUX_BEG, 012H, 00H, 00H
524 524 $DGS END_BLK, ??eb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H
525 525 $DGS AUX_END, 014H
526 526 $DGS END_FUN, ??ef_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H
527 527 $DGS AUX_END, 01AH
528 528 $DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 026H, 01H, 02H
529 529 $DGS AUX_FUN, 041H, U, U, 0206H, 00H, 00H
530 530 $DGS BEG_FUN, ??bf_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H
531 531 $DGS AUX_BEG, 0388H, 00H, 0206H
532 532 $DGS END_FUN, ??ef_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H
533 533 $DGS AUX_END, 04H
534 534 $DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 026H, 01H, 02H
535 535 $DGS AUX_FUN, 041H, U, U, 020CH, 00H, 00H
536 536 $DGS BEG_FUN, ??bf_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H
537 537 $DGS AUX_BEG, 038EH, 00H, 020CH
538 538 $DGS END_FUN, ??ef_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H
539 539 $DGS AUX_END, 04H
540 540 $DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 026H, 01H, 02H
541 541 $DGS AUX_FUN, 041H, U, U, 0217H, 00H, 00H
542 542 $DGS BEG_FUN, ??bf_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H
543 543 $DGS AUX_BEG, 0394H, 02H, 0211H
544 544 $DGS REG_VAR, _cmd_BL, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
545 545 $DGS BEG_BLK, ??bb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H
546 546 $DGS AUX_BEG, 05H, 00H, 00H
547 547 $DGS END_BLK, ??eb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H
548 548 $DGS AUX_END, 08H
549 549 $DGS END_FUN, ??ef_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H
550 550 $DGS AUX_END, 0DH
551 551 $DGS GLV_SYM, _raw_adc_temperature, U, U, 0CH, 026H, 00H, 00H
552 552 $DGS GLV_SYM, _rcomp, U, U, 0CH, 026H, 00H, 00H
553 553 $DGS GLV_SYM, _temp_co_up, U, U, 06H, 026H, 00H, 00H
554 554 $DGS GLV_SYM, _temp_co_dn, U, U, 06H, 026H, 00H, 00H
555 555 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H
556 556 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
557 557 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H
558 558 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
559 559 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H
560 560 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
561 561 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
562 562 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
563 563 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
564 564 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
565 565 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
566 566 $DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H
567 567 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
568 568 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
569 569 $DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H
570 570 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
571 571 $DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H
572 572 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
573 573 $DGS GLV_SYM, _iic_mcu_busy, U, U, 0134CH, 02H, 00H, 00H
574 574 $DGS GLV_SYM, _iic_mcu_wo_dma, U, U, 034CH, 02H, 00H, 00H
575 575 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H
576 576 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
577 577 $DGS GLV_SYM, @@lstof, U, U, 00H, 02H, 00H, 00H
578 578 $DGS GLV_SYM, _@RTARG4, U, U, 00H, 02H, 00H, 00H
579 579 $DGS GLV_SYM, @@fmul, U, U, 00H, 02H, 00H, 00H
580 580 $DGS GLV_SYM, @@fdiv, U, U, 00H, 02H, 00H, 00H
581 581 $DGS GLV_SYM, @@fsub, U, U, 00H, 02H, 00H, 00H
582 582 $DGS GLV_SYM, @@ftols, U, U, 00H, 02H, 00H, 00H
583 583 $DGS GLV_SYM, @@frev, U, U, 00H, 02H, 00H, 00H
584 584 $DGS GLV_SYM, _@RTARG3, U, U, 00H, 02H, 00H, 00H
585 585 $DGS GLV_SYM, @@ftolu, U, U, 00H, 02H, 00H, 00H
586 586 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
587 587 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
588 588 $DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H
589 589 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H
590 590 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H
591 591
592 592 EXTRN _iic_mcu_write
593 593 EXTRN _iic_mcu_write_a_byte
594 594 EXTRN _wait_ms
595 595 EXTRN _iic_mcu_read_a_byte
596 596 EXTRN _vreg_ctr
597 597 EXTRN _@RTARG0
598 598 EXTRN _@RTARG2
599 599 EXTRN _system_status
600 600 EXTRN _iic_mcu_read
601 601 EXTRN _get_adc
602 602 EXTRN _renge_task_immed_add
603 603 EXTRN @@lstof
604 604 EXTRN _@RTARG4
605 605 EXTRN @@fmul
606 606 EXTRN @@fdiv
607 607 EXTRN @@fsub
608 608 EXTRN @@ftols
609 609 EXTRN @@frev
610 610 EXTRN _@RTARG3
611 611 EXTRN @@ftolu
612 612 EXTRN _set_irq
613 613 EXTRN _@SEGAX
614 614 EXTRN _@SEGDE
615 615 EXTRN _iic_mcu_bus_status
616 616 EXTBIT _iic_mcu_busy
617 617 EXTBIT _iic_mcu_wo_dma
618 618 PUBLIC _raw_adc_temperature
619 619 PUBLIC _rcomp
620 620 PUBLIC _temp_co_up
621 621 PUBLIC _temp_co_dn
622 622 PUBLIC _PM_init
623 623 PUBLIC _PM_bt_temp_update
624 624 PUBLIC _PM_LCD_on
625 625 PUBLIC _PM_LCD_off
626 626 PUBLIC _PM_BL_set
627 627 PUBLIC _PM_LCD_vcom_set
628 628 PUBLIC _tski_vcom_set
629 629 PUBLIC _PM_sys_pow_on
630 630 PUBLIC _PM_sys_pow_off
631 631 PUBLIC _tsk_batt
632 632 PUBLIC _intp4_extdc
633 633 PUBLIC _intp5_shell
634 634 PUBLIC _intp6_PM_irq
635 635 PUBLIC _ntr_pmic_comm
636 636 PUBLIC _tski_PM_LCD_on
637 637 PUBLIC _tski_PM_LCD_off
638 638 PUBLIC _tski_PM_BL_set
639 639
640 640 ----- @@BITS BSEG
641 641 00000.0 ?L0079 DBIT
642 642
643 643 ----- @@CNST CSEG MIRRORP
644 644 00000 01 _lpf_coeff: DB 01H ; 1
645 645 00001 02 DB 02H ; 2
646 646 00002 02 DB 02H ; 2
647 647 00003 03 DB 03H ; 3
648 648 00004 03 DB 03H ; 3
649 649 00005 02 DB 02H ; 2
650 650 00006 00 DB 00H ; 0
651 651 00007 FE DB 0FEH ; 254
652 652 00008 FB DB 0FBH ; 251
653 653 00009 F7 DB 0F7H ; 247
654 654 0000A F3 DB 0F3H ; 243
655 655 0000B F0 DB 0F0H ; 240
656 656 0000C F0 DB 0F0H ; 240
657 657 0000D F3 DB 0F3H ; 243
658 658 0000E FA DB 0FAH ; 250
659 659 0000F 04 DB 04H ; 4
660 660 00010 12 DB 012H ; 18
661 661 00011 25 DB 025H ; 37
662 662 00012 38 DB 038H ; 56
663 663 00013 4D DB 04DH ; 77
664 664 00014 5F DB 05FH ; 95
665 665 00015 6E DB 06EH ; 110
666 666 00016 77 DB 077H ; 119
667 667 00017 7A DB 07AH ; 122
668 668 00018 77 DB 077H ; 119
669 669 00019 6E DB 06EH ; 110
670 670 0001A 5F DB 05FH ; 95
671 671 0001B 4D DB 04DH ; 77
672 672 0001C 38 DB 038H ; 56
673 673 0001D 25 DB 025H ; 37
674 674 0001E 12 DB 012H ; 18
675 675 0001F 04 DB 04H ; 4
676 676 00020 FA DB 0FAH ; 250
677 677 00021 F3 DB 0F3H ; 243
678 678 00022 F0 DB 0F0H ; 240
679 679 00023 F0 DB 0F0H ; 240
680 680 00024 F3 DB 0F3H ; 243
681 681 00025 F7 DB 0F7H ; 247
682 682 00026 FB DB 0FBH ; 251
683 683 00027 FE DB 0FEH ; 254
684 684 00028 00 DB 00H ; 0
685 685 00029 02 DB 02H ; 2
686 686 0002A 03 DB 03H ; 3
687 687 0002B 03 DB 03H ; 3
688 688 0002C 02 DB 02H ; 2
689 689 0002D 02 DB 02H ; 2
690 690 0002E 01 DB 01H ; 1
691 691 0002F 00 _BT_PARAM: DB 00H ; 0
692 692 00030 00 DB 00H ; 0
693 693 00031 00 DB 00H ; 0
694 694 00032 00 DB 00H ; 0
695 695 00033 00 DB 00H ; 0
696 696 00034 00 DB 00H ; 0
697 697 00035 00 DB 00H ; 0
698 698 00036 00 DB 00H ; 0
699 699 00037 00 DB 00H ; 0
700 700 00038 00 DB 00H ; 0
701 701 00039 00 DB 00H ; 0
702 702 0003A 00 DB 00H ; 0
703 703 0003B 00 DB 00H ; 0
704 704 0003C 00 DB 00H ; 0
705 705 0003D 00 DB 00H ; 0
706 706 0003E 00 DB 00H ; 0
707 707 0003F 00 DB 00H ; 0
708 708 00040 00 DB 00H ; 0
709 709 00041 00 DB 00H ; 0
710 710 00042 00 DB 00H ; 0
711 711 00043 00 DB 00H ; 0
712 712 00044 00 DB 00H ; 0
713 713 00045 00 DB 00H ; 0
714 714 00046 00 DB 00H ; 0
715 715 00047 00 DB 00H ; 0
716 716 00048 00 DB 00H ; 0
717 717 00049 00 DB 00H ; 0
718 718 0004A 00 DB 00H ; 0
719 719 0004B 00 DB 00H ; 0
720 720 0004C 00 DB 00H ; 0
721 721 0004D 00 DB 00H ; 0
722 722 0004E 00 DB 00H ; 0
723 723 0004F 00 DB 00H ; 0
724 724 00050 00 DB 00H ; 0
725 725 00051 00 DB 00H ; 0
726 726 00052 00 DB 00H ; 0
727 727 00053 00 DB 00H ; 0
728 728 00054 00 DB 00H ; 0
729 729 00055 00 DB 00H ; 0
730 730 00056 00 DB 00H ; 0
731 731 00057 00 DB 00H ; 0
732 732 00058 00 DB 00H ; 0
733 733 00059 00 DB 00H ; 0
734 734 0005A 00 DB 00H ; 0
735 735 0005B 00 DB 00H ; 0
736 736 0005C 00 DB 00H ; 0
737 737 0005D 00 DB 00H ; 0
738 738 0005E 00 DB 00H ; 0
739 739 0005F 00 DB 00H ; 0
740 740 00060 00 DB 00H ; 0
741 741 00061 00 DB 00H ; 0
742 742 00062 00 DB 00H ; 0
743 743 00063 00 DB 00H ; 0
744 744 00064 00 DB 00H ; 0
745 745 00065 00 DB 00H ; 0
746 746 00066 00 DB 00H ; 0
747 747 00067 00 DB 00H ; 0
748 748 00068 00 DB 00H ; 0
749 749 00069 00 DB 00H ; 0
750 750 0006A 00 DB 00H ; 0
751 751 0006B 00 DB 00H ; 0
752 752 0006C 00 DB 00H ; 0
753 753 0006D 00 DB 00H ; 0
754 754 0006E 00 DB 00H ; 0
755 755 0006F 00 DB 00H ; 0
756 756 00070 00 DB 00H ; 0
757 757 00071 00 DB 00H ; 0
758 758 00072 00 DB 00H ; 0
759 759 00073 00 DB 00H ; 0
760 760 00074 00 DB 00H ; 0
761 761 00075 00 DB 00H ; 0
762 762 00076 00 DB 00H ; 0
763 763 00077 00 DB 00H ; 0
764 764 00078 00 DB 00H ; 0
765 765 00079 00 DB 00H ; 0
766 766 0007A 00 DB 00H ; 0
767 767 0007B 00 DB 00H ; 0
768 768 0007C 00 DB 00H ; 0
769 769 0007D 00 DB 00H ; 0
770 770 0007E 00 DB 00H ; 0
771 771 0007F 00 DB 00H ; 0
772 772 00080 00 DB 00H ; 0
773 773 00081 00 DB 00H ; 0
774 774 00082 00 DB 00H ; 0
775 775 00083 00 DB 00H ; 0
776 776 00084 00 DB 00H ; 0
777 777 00085 00 DB 00H ; 0
778 778 00086 00 DB 00H ; 0
779 779 00087 00 DB 00H ; 0
780 780 00088 00 DB 00H ; 0
781 781 00089 00 DB 00H ; 0
782 782 0008A 00 DB 00H ; 0
783 783 0008B 00 DB 00H ; 0
784 784 0008C 00 DB 00H ; 0
785 785 0008D 00 DB 00H ; 0
786 786 0008E 00 DB 00H ; 0
787 787 0008F 00 DB 00H ; 0
788 788 00090 00 DB 00H ; 0
789 789 00091 00 DB 00H ; 0
790 790 00092 00 DB 00H ; 0
791 791 00093 00 DB 00H ; 0
792 792 00094 00 DB 00H ; 0
793 793 00095 00 DB 00H ; 0
794 794 00096 00 DB 00H ; 0
795 795 00097 00 DB 00H ; 0
796 796 00098 00 DB 00H ; 0
797 797 00099 00 DB 00H ; 0
798 798 0009A 00 DB 00H ; 0
799 799 0009B 00 DB 00H ; 0
800 800 0009C 00 DB 00H ; 0
801 801 0009D 00 DB 00H ; 0
802 802 0009E 00 DB 00H ; 0
803 803 0009F 00 DB 00H ; 0
804 804 000A0 00 DB 00H ; 0
805 805 000A1 00 DB 00H ; 0
806 806 000A2 00 DB 00H ; 0
807 807 000A3 00 DB 00H ; 0
808 808 000A4 00 DB 00H ; 0
809 809 000A5 00 DB 00H ; 0
810 810 000A6 00 DB 00H ; 0
811 811 000A7 00 DB 00H ; 0
812 812 000A8 00 DB 00H ; 0
813 813 000A9 00 DB 00H ; 0
814 814 000AA 00 DB 00H ; 0
815 815 000AB 00 DB 00H ; 0
816 816 000AC 00 DB 00H ; 0
817 817 000AD 00 DB 00H ; 0
818 818 000AE 00 DB 00H ; 0
819 819 000AF 00 DB 00H ; 0
820 820 000B0 00 DB 00H ; 0
821 821 000B1 00 DB 00H ; 0
822 822 000B2 00 DB 00H ; 0
823 823 000B3 00 DB 00H ; 0
824 824 000B4 00 DB 00H ; 0
825 825 000B5 00 DB 00H ; 0
826 826 000B6 00 DB 00H ; 0
827 827 000B7 00 DB 00H ; 0
828 828 000B8 00 DB 00H ; 0
829 829 000B9 00 DB 00H ; 0
830 830 000BA 00 DB 00H ; 0
831 831 000BB 00 DB 00H ; 0
832 832 000BC 00 DB 00H ; 0
833 833 000BD 00 DB 00H ; 0
834 834 000BE 00 DB 00H ; 0
835 835 000BF 00 DB 00H ; 0
836 836 000C0 00 DB 00H ; 0
837 837 000C1 00 DB 00H ; 0
838 838 000C2 00 DB 00H ; 0
839 839 000C3 00 DB 00H ; 0
840 840 000C4 00 DB 00H ; 0
841 841 000C5 00 DB 00H ; 0
842 842 000C6 00 DB 00H ; 0
843 843 000C7 00 DB 00H ; 0
844 844 000C8 00 DB 00H ; 0
845 845 000C9 00 DB 00H ; 0
846 846 000CA 00 DB 00H ; 0
847 847 000CB 00 DB 00H ; 0
848 848 000CC 00 DB 00H ; 0
849 849 000CD 00 DB 00H ; 0
850 850 000CE 00 DB 00H ; 0
851 851 000CF 00 DB 00H ; 0
852 852 000D0 00 DB 00H ; 0
853 853 000D1 00 DB 00H ; 0
854 854 000D2 00 DB 00H ; 0
855 855 000D3 00 DB 00H ; 0
856 856 000D4 00 DB 00H ; 0
857 857 000D5 00 DB 00H ; 0
858 858 000D6 00 DB 00H ; 0
859 859 000D7 00 DB 00H ; 0
860 860 000D8 00 DB 00H ; 0
861 861 000D9 00 DB 00H ; 0
862 862 000DA 00 DB 00H ; 0
863 863 000DB 00 DB 00H ; 0
864 864 000DC 00 DB 00H ; 0
865 865 000DD 00 DB 00H ; 0
866 866 000DE 00 DB 00H ; 0
867 867 000DF 00 DB 00H ; 0
868 868 000E0 00 DB 00H ; 0
869 869 000E1 00 DB 00H ; 0
870 870 000E2 00 DB 00H ; 0
871 871 000E3 00 DB 00H ; 0
872 872 000E4 00 DB 00H ; 0
873 873 000E5 00 DB 00H ; 0
874 874 000E6 00 DB 00H ; 0
875 875 000E7 00 DB 00H ; 0
876 876 000E8 00 DB 00H ; 0
877 877 000E9 00 DB 00H ; 0
878 878 000EA 00 DB 00H ; 0
879 879 000EB 00 DB 00H ; 0
880 880 000EC 00 DB 00H ; 0
881 881 000ED 00 DB 00H ; 0
882 882 000EE 00 DB 00H ; 0
883 883 000EF 00 DB 00H ; 0
884 884 000F0 00 DB 00H ; 0
885 885 000F1 00 DB 00H ; 0
886 886 000F2 00 DB 00H ; 0
887 887 000F3 00 DB 00H ; 0
888 888 000F4 00 DB 00H ; 0
889 889 000F5 00 DB 00H ; 0
890 890 000F6 00 DB 00H ; 0
891 891 000F7 00 DB 00H ; 0
892 892 000F8 00 DB 00H ; 0
893 893 000F9 00 DB 00H ; 0
894 894 000FA 00 DB 00H ; 0
895 895 000FB 00 DB 00H ; 0
896 896 000FC 00 DB 00H ; 0
897 897 000FD 00 DB 00H ; 0
898 898 000FE 00 DB 00H ; 0
899 899 000FF 00 DB 00H ; 0
900 900 00100 00 DB 00H ; 0
901 901 00101 00 DB 00H ; 0
902 902 00102 00 DB 00H ; 0
903 903 00103 00 DB 00H ; 0
904 904 00104 00 DB 00H ; 0
905 905 00105 00 DB 00H ; 0
906 906 00106 00 DB 00H ; 0
907 907 00107 00 DB 00H ; 0
908 908 00108 00 DB 00H ; 0
909 909 00109 00 DB 00H ; 0
910 910 0010A 00 DB 00H ; 0
911 911 0010B 00 DB 00H ; 0
912 912 0010C 00 DB 00H ; 0
913 913 0010D 00 DB 00H ; 0
914 914 0010E 00 DB 00H ; 0
915 915 0010F 00 DB 00H ; 0
916 916 00110 00 DB 00H ; 0
917 917 00111 00 DB 00H ; 0
918 918 00112 00 DB 00H ; 0
919 919 00113 00 DB 00H ; 0
920 920 00114 00 DB 00H ; 0
921 921 00115 00 DB 00H ; 0
922 922 00116 00 DB 00H ; 0
923 923 00117 00 DB 00H ; 0
924 924 00118 00 DB 00H ; 0
925 925 00119 00 DB 00H ; 0
926 926 0011A 00 DB 00H ; 0
927 927 0011B 00 DB 00H ; 0
928 928 0011C 00 DB 00H ; 0
929 929 0011D 00 DB 00H ; 0
930 930 0011E 00 DB 00H ; 0
931 931 0011F 00 DB 00H ; 0
932 932 00120 00 DB 00H ; 0
933 933 00121 00 DB 00H ; 0
934 934 00122 00 DB 00H ; 0
935 935 00123 00 DB 00H ; 0
936 936 00124 00 DB 00H ; 0
937 937 00125 00 DB 00H ; 0
938 938 00126 00 DB 00H ; 0
939 939 00127 00 DB 00H ; 0
940 940 00128 00 DB 00H ; 0
941 941 00129 00 DB 00H ; 0
942 942 0012A 00 DB 00H ; 0
943 943 0012B 00 DB 00H ; 0
944 944 0012C 00 DB 00H ; 0
945 945 0012D 00 DB 00H ; 0
946 946 0012E 00 DB 00H ; 0
947 947 0012F AD DB 0ADH ; 173
948 948 00130 30 DB 030H ; 48
949 949 00131 AE DB 0AEH ; 174
950 950 00132 70 DB 070H ; 112
951 951 00133 B0 DB 0B0H ; 176
952 952 00134 00 DB 00H ; 0
953 953 00135 B3 DB 0B3H ; 179
954 954 00136 00 DB 00H ; 0
955 955 00137 B4 DB 0B4H ; 180
956 956 00138 70 DB 070H ; 112
957 957 00139 B5 DB 0B5H ; 181
958 958 0013A A0 DB 0A0H ; 160
959 959 0013B B7 DB 0B7H ; 183
960 960 0013C 80 DB 080H ; 128
961 961 0013D BA DB 0BAH ; 186
962 962 0013E 00 DB 00H ; 0
963 963 0013F BB DB 0BBH ; 187
964 964 00140 90 DB 090H ; 144
965 965 00141 BD DB 0BDH ; 189
966 966 00142 00 DB 00H ; 0
967 967 00143 BE DB 0BEH ; 190
968 968 00144 00 DB 00H ; 0
969 969 00145 BF DB 0BFH ; 191
970 970 00146 F0 DB 0F0H ; 240
971 971 00147 C3 DB 0C3H ; 195
972 972 00148 00 DB 00H ; 0
973 973 00149 C5 DB 0C5H ; 197
974 974 0014A C0 DB 0C0H ; 192
975 975 0014B C8 DB 0C8H ; 200
976 976 0014C 00 DB 00H ; 0
977 977 0014D CA DB 0CAH ; 202
978 978 0014E C0 DB 0C0H ; 192
979 979 0014F 04 DB 04H ; 4
980 980 00150 00 DB 00H ; 0
981 981 00151 12 DB 012H ; 18
982 982 00152 00 DB 00H ; 0
983 983 00153 0C DB 0CH ; 12
984 984 00154 10 DB 010H ; 16
985 985 00155 24 DB 024H ; 36
986 986 00156 00 DB 00H ; 0
987 987 00157 10 DB 010H ; 16
988 988 00158 D0 DB 0D0H ; 208
989 989 00159 1B DB 01BH ; 27
990 990 0015A F0 DB 0F0H ; 240
991 991 0015B 0A DB 0AH ; 10
992 992 0015C F0 DB 0F0H ; 240
993 993 0015D 08 DB 08H ; 8
994 994 0015E E0 DB 0E0H ; 224
995 995 0015F 0C DB 0CH ; 12
996 996 00160 F0 DB 0F0H ; 240
997 997 00161 08 DB 08H ; 8
998 998 00162 C0 DB 0C0H ; 192
999 999 00163 08 DB 08H ; 8
1000 1000 00164 B0 DB 0B0H ; 176
1001 1001 00165 07 DB 07H ; 7
1002 1002 00166 F0 DB 0F0H ; 240
1003 1003 00167 0B DB 0BH ; 11
1004 1004 00168 00 DB 00H ; 0
1005 1005 00169 05 DB 05H ; 5
1006 1006 0016A D0 DB 0D0H ; 208
1007 1007 0016B 02 DB 02H ; 2
1008 1008 0016C 00 DB 00H ; 0
1009 1009 0016D 09 DB 09H ; 9
1010 1010 0016E 00 DB 00H ; 0
1011 1011 0016F 00 DB 00H ; 0
1012 1012 00170 00 DB 00H ; 0
1013 1013 00171 00 DB 00H ; 0
1014 1014 00172 00 DB 00H ; 0
1015 1015 00173 00 DB 00H ; 0
1016 1016 00174 00 DB 00H ; 0
1017 1017 00175 00 DB 00H ; 0
1018 1018 00176 00 DB 00H ; 0
1019 1019 00177 00 DB 00H ; 0
1020 1020 00178 00 DB 00H ; 0
1021 1021 00179 00 DB 00H ; 0
1022 1022 0017A 00 DB 00H ; 0
1023 1023 0017B 00 DB 00H ; 0
1024 1024 0017C 00 DB 00H ; 0
1025 1025 0017D 00 DB 00H ; 0
1026 1026 0017E 00 DB 00H ; 0
1027 1027 0017F 00 DB 00H ; 0
1028 1028 00180 00 DB 00H ; 0
1029 1029 00181 00 DB 00H ; 0
1030 1030 00182 00 DB 00H ; 0
1031 1031 00183 00 DB 00H ; 0
1032 1032 00184 00 DB 00H ; 0
1033 1033 00185 00 DB 00H ; 0
1034 1034 00186 00 DB 00H ; 0
1035 1035 00187 00 DB 00H ; 0
1036 1036 00188 00 DB 00H ; 0
1037 1037 00189 00 DB 00H ; 0
1038 1038 0018A 00 DB 00H ; 0
1039 1039 0018B 00 DB 00H ; 0
1040 1040 0018C 00 DB 00H ; 0
1041 1041 0018D 00 DB 00H ; 0
1042 1042 0018E 00 DB 00H ; 0
1043 1043 0018F 00 DB 00H ; 0
1044 1044 00190 00 DB 00H ; 0
1045 1045 00191 00 DB 00H ; 0
1046 1046 00192 00 DB 00H ; 0
1047 1047 00193 00 DB 00H ; 0
1048 1048 00194 00 DB 00H ; 0
1049 1049 00195 00 DB 00H ; 0
1050 1050 00196 00 DB 00H ; 0
1051 1051 00197 00 DB 00H ; 0
1052 1052 00198 00 DB 00H ; 0
1053 1053 00199 00 DB 00H ; 0
1054 1054 0019A 00 DB 00H ; 0
1055 1055 0019B 00 DB 00H ; 0
1056 1056 0019C 00 DB 00H ; 0
1057 1057 0019D 00 DB 00H ; 0
1058 1058 0019E 00 DB 00H ; 0
1059 1059 0019F 00 DB 00H ; 0
1060 1060 001A0 00 DB 00H ; 0
1061 1061 001A1 00 DB 00H ; 0
1062 1062 001A2 00 DB 00H ; 0
1063 1063 001A3 00 DB 00H ; 0
1064 1064 001A4 00 DB 00H ; 0
1065 1065 001A5 00 DB 00H ; 0
1066 1066 001A6 00 DB 00H ; 0
1067 1067 001A7 00 DB 00H ; 0
1068 1068 001A8 00 DB 00H ; 0
1069 1069 001A9 00 DB 00H ; 0
1070 1070 001AA 00 DB 00H ; 0
1071 1071 001AB 00 DB 00H ; 0
1072 1072 001AC 00 DB 00H ; 0
1073 1073 001AD 00 DB 00H ; 0
1074 1074 001AE 00 DB 00H ; 0
1075 1075 001AF AD DB 0ADH ; 173
1076 1076 001B0 30 DB 030H ; 48
1077 1077 001B1 AE DB 0AEH ; 174
1078 1078 001B2 70 DB 070H ; 112
1079 1079 001B3 B0 DB 0B0H ; 176
1080 1080 001B4 00 DB 00H ; 0
1081 1081 001B5 B3 DB 0B3H ; 179
1082 1082 001B6 00 DB 00H ; 0
1083 1083 001B7 B4 DB 0B4H ; 180
1084 1084 001B8 70 DB 070H ; 112
1085 1085 001B9 B5 DB 0B5H ; 181
1086 1086 001BA A0 DB 0A0H ; 160
1087 1087 001BB B7 DB 0B7H ; 183
1088 1088 001BC 80 DB 080H ; 128
1089 1089 001BD BA DB 0BAH ; 186
1090 1090 001BE 00 DB 00H ; 0
1091 1091 001BF BB DB 0BBH ; 187
1092 1092 001C0 90 DB 090H ; 144
1093 1093 001C1 BD DB 0BDH ; 189
1094 1094 001C2 00 DB 00H ; 0
1095 1095 001C3 BE DB 0BEH ; 190
1096 1096 001C4 00 DB 00H ; 0
1097 1097 001C5 BF DB 0BFH ; 191
1098 1098 001C6 F0 DB 0F0H ; 240
1099 1099 001C7 C3 DB 0C3H ; 195
1100 1100 001C8 00 DB 00H ; 0
1101 1101 001C9 C5 DB 0C5H ; 197
1102 1102 001CA C0 DB 0C0H ; 192
1103 1103 001CB C8 DB 0C8H ; 200
1104 1104 001CC 00 DB 00H ; 0
1105 1105 001CD CA DB 0CAH ; 202
1106 1106 001CE C0 DB 0C0H ; 192
1107 1107 001CF 04 DB 04H ; 4
1108 1108 001D0 00 DB 00H ; 0
1109 1109 001D1 12 DB 012H ; 18
1110 1110 001D2 00 DB 00H ; 0
1111 1111 001D3 0C DB 0CH ; 12
1112 1112 001D4 10 DB 010H ; 16
1113 1113 001D5 24 DB 024H ; 36
1114 1114 001D6 00 DB 00H ; 0
1115 1115 001D7 10 DB 010H ; 16
1116 1116 001D8 D0 DB 0D0H ; 208
1117 1117 001D9 1B DB 01BH ; 27
1118 1118 001DA F0 DB 0F0H ; 240
1119 1119 001DB 0A DB 0AH ; 10
1120 1120 001DC F0 DB 0F0H ; 240
1121 1121 001DD 08 DB 08H ; 8
1122 1122 001DE E0 DB 0E0H ; 224
1123 1123 001DF 0C DB 0CH ; 12
1124 1124 001E0 F0 DB 0F0H ; 240
1125 1125 001E1 08 DB 08H ; 8
1126 1126 001E2 C0 DB 0C0H ; 192
1127 1127 001E3 08 DB 08H ; 8
1128 1128 001E4 B0 DB 0B0H ; 176
1129 1129 001E5 07 DB 07H ; 7
1130 1130 001E6 F0 DB 0F0H ; 240
1131 1131 001E7 0B DB 0BH ; 11
1132 1132 001E8 00 DB 00H ; 0
1133 1133 001E9 05 DB 05H ; 5
1134 1134 001EA D0 DB 0D0H ; 208
1135 1135 001EB 02 DB 02H ; 2
1136 1136 001EC 00 DB 00H ; 0
1137 1137 001ED 09 DB 09H ; 9
1138 1138 001EE 00 DB 00H ; 0
1139 1139 001EF 87 _BT_PANA_RCOMP: DB 087H ; 135
1140 1140 001F0 9A99993E _BT_PANA_TEMPCOUP: DW 0999AH,03E99H ; 1050253722
1141 1141 001F4 0000003F _BT_PANA_TEMPCODN: DW 00000H,03F00H ; 1056964608
1142 1142
1143 1143 ----- @@R_INIT CSEG UNIT64KP
1144 1144 00000 00 DB 00H ; 0
1145 1145 00001 00 DB 00H ; 0
1146 1146 00002 00 DB 00H ; 0
1147 1147 00003 00 DB (1)
1148 1148
1149 1149 ----- @@INIT DSEG BASEP
1150 1150 00000 ?L0018: DS (1)
1151 1151 00001 ?L0077: DS (1)
1152 1152 00002 ?L0078: DS (1)
1153 1153 00003 DS (1)
1154 1154
1155 1155 ----- @@DATA DSEG BASEP
1156 1156 00000 _raw_adc_temperature: DS (1)
1157 1157 00001 _rcomp: DS (1)
1158 1158 00002 _temp_co_up: DS (4)
1159 1159 00006 _temp_co_dn: DS (4)
1160 1160 0000A ?L0019: DS (1)
1161 1161 0000B DS (1)
1162 1162 0000C ?L0020: DS (2)
1163 1163 0000E ?L0112: DS (1)
1164 1164 0000F DS (1)
1165 1165
1166 1166 ----- @@R_INIS CSEG UNIT64KP
1167 1167
1168 1168 ----- @@INIS DSEG SADDRP
1169 1169
1170 1170 ----- @@DATS DSEG SADDRP
1171 1171
1172 1172 ----- @@CNSTL CSEG PAGE64KP
1173 1173
1174 1174 ----- @@RLINIT CSEG UNIT64KP
1175 1175
1176 1176 ----- @@INITL DSEG UNIT64KP
1177 1177
1178 1178 ----- @@DATAL DSEG UNIT64KP
1179 1179
1180 1180 ----- @@CALT CSEG CALLT0
1181 1181
1182 1182 ; Sub-Routines created by CC78K0R
1183 1183
1184 1184 ----- ROM_CODE CSEG BASE
1185 1185 00000 bs_F0153:
1186 1186 00000 506C mov x,#06CH ; 108 ;[INF] 2, 1
1187 1187 00002 RED0000 br !_iic_mcu_write ;[INF] 3, 3
1188 1188 00005 es_F0153:
1189 1189
1190 1190 ----- ROM_CODE CSEG BASE
1191 1191 00005 bs_F0154:
1192 1192 00005 5084 mov x,#084H ; 132 ;[INF] 2, 1
1193 1193 00007 RED0000 br !_iic_mcu_write_a_byte ;[INF] 3, 3
1194 1194 0000A es_F0154:
1195 1195
1196 1196 ----- ROM_CODE CSEG BASE
1197 1197 0000A bs_F0155:
1198 1198 0000A 301000 movw ax,#010H ; 16 ;[INF] 3, 1
1199 1199 0000D RED0000 br !_wait_ms ;[INF] 3, 3
1200 1200 00010 es_F0155:
1201 1201
1202 1202 ----- ROM_CODE CSEG BASE
1203 1203 00010 bs_F0151:
1204 1204 00010 C1 push ax ;[INF] 1, 1
1205 1205 00011 506C mov x,#06CH ; 108 ;[INF] 2, 1
1206 1206 00013 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
1207 1207 00016 C0 pop ax ;[INF] 1, 1
1208 1208 00017 62 mov a,c ;[INF] 1, 1
1209 1209 00018 D7 ret ;[INF] 1, 6
1210 1210 00019 es_F0151:
1211 1211
1212 1212 ----- ROM_CODE CSEG BASE
1213 1213 00019 bs_S0152:
1214 1214 00019 72 mov c,a ;[INF] 1, 1
1215 1215 0001A R341300 movw de,#loww (_vreg_ctr+19) ;[INF] 3, 1
1216 1216 0001D 89 mov a,[de] ;[INF] 1, 1
1217 1217 0001E 616A or a,c ;[INF] 2, 1
1218 1218 00020 99 mov [de],a ;[INF] 1, 1
1219 1219 00021 D7 ret ;[INF] 1, 6
1220 1220 00022 es_S0152:
1221 1221
1222 1222 ----- ROM_CODE CSEG BASE
1223 1223 00022 bs_F0149:
1224 1224 00022 300400 movw ax,#04H ; 4 ;[INF] 3, 1
1225 1225 00025 C1 push ax ;[INF] 1, 1
1226 1226 00026 5084 mov x,#084H ; 132 ;[INF] 2, 1
1227 1227 00028 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
1228 1228 0002B C0 pop ax ;[INF] 1, 1
1229 1229 0002C 62 mov a,c ;[INF] 1, 1
1230 1230 0002D D7 ret ;[INF] 1, 6
1231 1231 0002E es_F0149:
1232 1232
1233 1233 ----- ROM_CODE CSEG BASE
1234 1234 0002E bs_F0150:
1235 1235 0002E C1 push ax ;[INF] 1, 1
1236 1236 0002F E6 onew ax ;[INF] 1, 1
1237 1237 00030 C1 push ax ;[INF] 1, 1
1238 1238 00031 5084 mov x,#084H ; 132 ;[INF] 2, 1
1239 1239 00033 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
1240 1240 00036 1004 addw sp,#04H ; 4 ;[INF] 2, 1
1241 1241 00038 D7 ret ;[INF] 1, 6
1242 1242 00039 es_F0150:
1243 1243
1244 1244 ----- ROM_CODE CSEG BASE
1245 1245 00039 bs_F0146:
1246 1246 00039 C1 push ax ;[INF] 1, 1
1247 1247 0003A E6 onew ax ;[INF] 1, 1
1248 1248 0003B A1 incw ax ;[INF] 1, 1
1249 1249 0003C C1 push ax ;[INF] 1, 1
1250 1250 0003D 5084 mov x,#084H ; 132 ;[INF] 2, 1
1251 1251 0003F RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
1252 1252 00042 1004 addw sp,#04H ; 4 ;[INF] 2, 1
1253 1253 00044 D7 ret ;[INF] 1, 6
1254 1254 00045 es_F0146:
1255 1255
1256 1256 ----- ROM_CODE CSEG BASE
1257 1257 00045 bs_F0147:
1258 1258 00045 300300 movw ax,#03H ; 3 ;[INF] 3, 1
1259 1259 00048 C1 push ax ;[INF] 1, 1
1260 1260 00049 5084 mov x,#084H ; 132 ;[INF] 2, 1
1261 1261 0004B RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
1262 1262 0004E C0 pop ax ;[INF] 1, 1
1263 1263 0004F 62 mov a,c ;[INF] 1, 1
1264 1264 00050 5C01 and a,#01H ; 1 ;[INF] 2, 1
1265 1265 00052 D7 ret ;[INF] 1, 6
1266 1266 00053 es_F0147:
1267 1267
1268 1268 ----- ROM_CODE CSEG BASE
1269 1269 00053 bs_F0148:
1270 1270 00053 E6 onew ax ;[INF] 1, 1
1271 1271 00054 C1 push ax ;[INF] 1, 1
1272 1272 00055 A1 incw ax ;[INF] 1, 1
1273 1273 00056 A1 incw ax ;[INF] 1, 1
1274 1274 00057 C1 push ax ;[INF] 1, 1
1275 1275 00058 5084 mov x,#084H ; 132 ;[INF] 2, 1
1276 1276 0005A RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
1277 1277 0005D 1004 addw sp,#04H ; 4 ;[INF] 2, 1
1278 1278 0005F D7 ret ;[INF] 1, 6
1279 1279 00060 es_F0148:
1280 1280
1281 1281 ----- ROM_CODE CSEG BASE
1282 1282 00060 bs_S0144:
1283 1283 00060 RAF0C00 movw ax,!?L0020 ; temperature ;[INF] 3, 1
1284 1284 00063 241400 subw ax,#014H ; 20 ;[INF] 3, 1
1285 1285 00066 12 movw bc,ax ;[INF] 1, 1
1286 1286 00067 31FF sarw ax,15 ;[INF] 2, 1
1287 1287 00069 33 xchw ax,bc ;[INF] 1, 1
1288 1288 0006A RBD00 movw _@RTARG0,ax ;[INF] 2, 1
1289 1289 0006C 13 movw ax,bc ;[INF] 1, 1
1290 1290 0006D RBD00 movw _@RTARG2,ax ;[INF] 2, 1
1291 1291 0006F D7 ret ;[INF] 1, 6
1292 1292 00070 es_S0144:
1293 1293
1294 1294 ----- ROM_CODE CSEG BASE
1295 1295 00070 bs_F0145:
1296 1296 00070 300700 movw ax,#07H ; 7 ;[INF] 3, 1
1297 1297 00073 C1 push ax ;[INF] 1, 1
1298 1298 00074 E6 onew ax ;[INF] 1, 1
1299 1299 00075 A1 incw ax ;[INF] 1, 1
1300 1300 00076 C1 push ax ;[INF] 1, 1
1301 1301 00077 5084 mov x,#084H ; 132 ;[INF] 2, 1
1302 1302 00079 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
1303 1303 0007C 1004 addw sp,#04H ; 4 ;[INF] 2, 1
1304 1304 0007E D7 ret ;[INF] 1, 6
1305 1305 0007F es_F0145:
1306 1306
1307 1307 ; *** Sub-Routine Information ***
1308 1308 ;
1309 1309 ; $SUB bs_S0144
1310 1310 ; CODE SIZE= 16 bytes
1311 1311 ;
1312 1312 ; $SUB bs_F0145
1313 1313 ; CODE SIZE= 15 bytes
1314 1314 ;
1315 1315 ; $SUB bs_F0146
1316 1316 ; CODE SIZE= 12 bytes
1317 1317 ;
1318 1318 ; $SUB bs_F0147
1319 1319 ; CODE SIZE= 14 bytes
1320 1320 ;
1321 1321 ; $SUB bs_F0148
1322 1322 ; CODE SIZE= 13 bytes
1323 1323 ;
1324 1324 ; $SUB bs_F0149
1325 1325 ; CODE SIZE= 12 bytes
1326 1326 ;
1327 1327 ; $SUB bs_F0150
1328 1328 ; CODE SIZE= 11 bytes
1329 1329 ;
1330 1330 ; $SUB bs_F0151
1331 1331 ; CODE SIZE= 9 bytes
1332 1332 ;
1333 1333 ; $SUB bs_S0152
1334 1334 ; CODE SIZE= 9 bytes
1335 1335 ;
1336 1336 ; $SUB bs_F0153
1337 1337 ; CODE SIZE= 5 bytes
1338 1338 ;
1339 1339 ; $SUB bs_F0154
1340 1340 ; CODE SIZE= 5 bytes
1341 1341 ;
1342 1342 ; $SUB bs_F0155
1343 1343 ; CODE SIZE= 6 bytes
1344 1344
1345 1345 ; End of Sub-Routines
1346 1346
1347 1347 ; line 1 : /* ========================================================
1348 1348 ; line 2 : <20><>PMIC
1349 1349 ; line 3 : <20><><EFBFBD>c<EFBFBD><63><EFBFBD>J<EFBFBD>Z
1350 1350 ; line 4 : nintendo
1351 1351 ; line 5 : '08 Dec
1352 1352 ; line 6 : ======================================================== */
1353 1353 ; line 7 : #pragma nop
1354 1354 ; line 8 :
1355 1355 ; line 9 : #include "incs.h"
1356 1356 ; line 10 : #include "adc.h"
1357 1357 ; line 11 : #include "led.h"
1358 1358 ; line 12 : #include "pm.h"
1359 1359 ; line 13 : #include "renge.h"
1360 1360 ; line 14 :
1361 1361 ; line 15 : #include "batt_params.h"
1362 1362 ; line 16 :
1363 1363 ; line 17 : #include <fsl.h>
1364 1364 ; line 18 : #include "fsl_user.h"
1365 1365 ; line 19 : extern u16 pool[];
1366 1366 ; line 20 :
1367 1367 ; line 21 : // ========================================================
1368 1368 ; line 22 :
1369 1369 ; line 23 :
1370 1370 ; line 24 : // ========================================================
1371 1371 ; line 25 : u8 raw_adc_temperature;
1372 1372 ; line 26 : u8 rcomp;
1373 1373 ; line 27 : float temp_co_up;
1374 1374 ; line 28 : float temp_co_dn;
1375 1375 ; line 29 :
1376 1376 ; line 30 : // ========================================================
1377 1377 ; line 31 : static void PM_get_batt_left();
1378 1378 ; line 32 :
1379 1379 ; line 33 :
1380 1380 ; line 34 : /******************************************************//**
1381 1381 ; line 35 : PMIC<49>B<EFBFBD>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
1382 1382 ; line 36 : \n <20>d<EFBFBD>r<EFBFBD><72><EFBFBD>[<5B>J<EFBFBD>[<5B><><EFBFBD><EFBFBD>
1383 1383 ; line 37 : \n <20>d<EFBFBD>r<EFBFBD>c<EFBFBD><63>IC<49>̃Z<CC83>b<EFBFBD>g
1384 1384 ; line 38 : \n <20>o<EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̎擾
1385 1385 ; line 39 : \n
1386 1386 ; line 40 : \n <20>ȉ<EFBFBD><C889>̃s<CC83><73><EFBFBD>͎<EFBFBD><CD8E>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ő<EFBFBD><C591><EFBFBD><EFBFBD>E<EFBFBD>Ď<EFBFBD><C48E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
1387 1387 ; line 41 : \n <20>EPM_BT_DET,_P
1388 1388 ; line 42 : *********************************************************/
1389 1389 ; line 43 : #define swap_endian_16( x ) (unsigned int)( x << 8 | x >> 8 )
1390 1390 ; line 44 :
1391 1391 ; line 45 : void PM_init( )
1392 1392 ; line 46 : {
1393 1393
1394 1394 ----- ROM_CODE CSEG BASE
1395 1395 0007F _PM_init:
1396 1396 $DGL 1,102
1397 1397 0007F C7 push hl ;[INF] 1, 1
1398 1398 00080 2008 subw sp,#08H ;[INF] 2, 1
1399 1399 00082 FBF8FF movw hl,sp ;[INF] 3, 1
1400 1400 00085 ??bf_PM_init:
1401 1401 ; line 47 : u8 temp;
1402 1402 ; line 48 : u8 origParam[4];
1403 1403 ; line 49 : union{
1404 1404 ; line 50 : u16 _u16; // <20><><EFBFBD>ł킩<C582><ED82A9><EFBFBD>悤<EFBFBD>ɁAlittle endi
1405 1405 ; an <20>ł<EFBFBD><C582>B<EFBFBD><42><EFBFBD>ӁB
1406 1406 ; line 51 : struct{
1407 1407 ; line 52 : u8 lsb;
1408 1408 ; line 53 : u8 msb;
1409 1409 ; line 54 : }chars;
1410 1410 ; line 55 : }dat_16;
1411 1411 ; line 56 :
1412 1412 ; line 57 : system_status.model = MODEL_JIKKI;
1413 1413 $DGL 0,12
1414 1414 00085 RF50300 clrb !_system_status+3 ;[INF] 3, 1
1415 1415 ; line 58 : wait_ms( 150 );
1416 1416 $DGL 0,13
1417 1417 00088 309600 movw ax,#096H ; 150 ;[INF] 3, 1
1418 1418 0008B RFD0000 call !_wait_ms ;[INF] 3, 3
1419 1419 ; line 59 :
1420 1420 ; line 60 : // -1. <20>Ȃ񂩂<C882><F182A982><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>c<EFBFBD>@<40><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă݂<C482>
1421 1421 ; line 61 : dat_16._u16 = swap_endian_16( 0x5400 ); // reset
1422 1422 $DGL 0,16
1423 1423 0008E 305400 movw ax,#054H ; 84 ;[INF] 3, 1
1424 1424 00091 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1425 1425 ; line 62 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_COMMAND, 2, &d
1426 1426 ; at_16 ); // <20><><EFBFBD><EFBFBD><EFBFBD>‚<EFBFBD>NACK<43><4B><EFBFBD>Ԃ<EFBFBD>
1427 1427 $DGL 0,17
1428 1428 00092 17 movw ax,hl ;[INF] 1, 1
1429 1429 00093 C1 push ax ;[INF] 1, 1
1430 1430 00094 E6 onew ax ;[INF] 1, 1
1431 1431 00095 A1 incw ax ;[INF] 1, 1
1432 1432 00096 C1 push ax ;[INF] 1, 1
1433 1433 00097 50FE mov x,#0FEH ; 254 ;[INF] 2, 1
1434 1434 00099 C1 push ax ;[INF] 1, 1
1435 1435 0009A RFD0000 call !bs_F0153 ;[INF] 3, 3
1436 1436 0009D 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1437 1437 ; line 63 :
1438 1438 ; line 64 : // 0. <20>o<EFBFBD>b<EFBFBD>e<EFBFBD><65><EFBFBD>c<EFBFBD><63>IC <20>N<EFBFBD>C<EFBFBD>b<EFBFBD>N<EFBFBD>X<EFBFBD>^<5E>[<5B>g
1439 1439 ; line 65 : dat_16._u16 = swap_endian_16( 0x4000 ); // quick start
1440 1440 $DGL 0,20
1441 1441 0009F 304000 movw ax,#040H ; 64 ;[INF] 3, 1
1442 1442 000A2 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1443 1443 ; line 66 : if( iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_MODE, 2, &
1444 1444 ; dat_16 ) != ERR_SUCCESS )
1445 1445 $DGL 0,21
1446 1446 000A3 17 movw ax,hl ;[INF] 1, 1
1447 1447 000A4 C1 push ax ;[INF] 1, 1
1448 1448 000A5 E6 onew ax ;[INF] 1, 1
1449 1449 000A6 A1 incw ax ;[INF] 1, 1
1450 1450 000A7 C1 push ax ;[INF] 1, 1
1451 1451 000A8 5006 mov x,#06H ; 6 ;[INF] 2, 1
1452 1452 000AA C1 push ax ;[INF] 1, 1
1453 1453 000AB RFD0000 call !bs_F0153 ;[INF] 3, 3
1454 1454 000AE 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1455 1455 000B0 D2 cmp0 c ;[INF] 1, 1
1456 1456 000B1 DD0A bz $?L0003 ;[INF] 2, 4
1457 1457 ; line 67 : {
1458 1458 000B3 ??bb00_PM_init:
1459 1459 ; line 68 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR;
1460 1460 $DGL 0,23
1461 1461 000B3 R71000E00 set1 !_vreg_ctr+14.0 ;[INF] 4, 2
1462 1462 ; line 69 : system_status.model = MODEL_TS_BOARD;
1463 1463 $DGL 0,24
1464 1464 000B7 RE50300 oneb !_system_status+3 ;[INF] 3, 1
1465 1465 000BA ??eb00_PM_init:
1466 1466 ; line 70 : }
1467 1467 $DGL 0,25
1468 1468 000BA REDB701 br !?L0004 ;[INF] 3, 3
1469 1469 000BD ?L0003:
1470 1470 ; line 71 : else
1471 1471 ; line 72 : {
1472 1472 000BD ??bb01_PM_init:
1473 1473 ; line 73 : // 1. <20><><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
1474 1474 ; line 74 : dat_16._u16 = swap_endian_16( 0x4057 ); // unlock key
1475 1475 $DGL 0,29
1476 1476 000BD 304057 movw ax,#05740H ; 22336 ;[INF] 3, 1
1477 1477 000C0 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1478 1478 ; line 75 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, &
1479 1479 ; dat_16 );
1480 1480 $DGL 0,30
1481 1481 000C1 17 movw ax,hl ;[INF] 1, 1
1482 1482 000C2 C1 push ax ;[INF] 1, 1
1483 1483 000C3 E6 onew ax ;[INF] 1, 1
1484 1484 000C4 A1 incw ax ;[INF] 1, 1
1485 1485 000C5 C1 push ax ;[INF] 1, 1
1486 1486 000C6 503E mov x,#03EH ; 62 ;[INF] 2, 1
1487 1487 000C8 C1 push ax ;[INF] 1, 1
1488 1488 000C9 RFD0000 call !bs_F0153 ;[INF] 3, 3
1489 1489 000CC 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1490 1490 ; line 76 :
1491 1491 ; line 77 : // 2. <20><><EFBFBD><EFBFBD><EFBFBD>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD>[<5B>^<5E><><EFBFBD>ꎞ<EFBFBD>ۑ<EFBFBD>
1492 1492 ; line 78 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, o
1493 1493 ; rigParam );
1494 1494 $DGL 0,33
1495 1495 000CE 17 movw ax,hl ;[INF] 1, 1
1496 1496 000CF 040300 addw ax,#03H ;[INF] 3, 1
1497 1497 000D2 C1 push ax ;[INF] 1, 1
1498 1498 000D3 300400 movw ax,#04H ; 4 ;[INF] 3, 1
1499 1499 000D6 C1 push ax ;[INF] 1, 1
1500 1500 000D7 500C mov x,#0CH ; 12 ;[INF] 2, 1
1501 1501 000D9 C1 push ax ;[INF] 1, 1
1502 1502 000DA 506C mov x,#06CH ; 108 ;[INF] 2, 1
1503 1503 000DC RFD0000 call !_iic_mcu_read ;[INF] 3, 3
1504 1504 000DF 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1505 1505 ; line 79 :
1506 1506 ; line 80 : // 3. <20>ꎞ<EFBFBD>I<EFBFBD><49>OCV<43><56><EFBFBD>ύX
1507 1507 ; line 81 : dat_16._u16 = swap_endian_16( 0xD4C0 ); // <20>}<7D>W<EFBFBD>b<EFBFBD>N<EFBFBD>i<EFBFBD><69><EFBFBD>o
1508 1508 ; <20>[<5B>I<EFBFBD>Ȃ<EFBFBD><C882>́B<CC81><42><EFBFBD>[<5B>J<EFBFBD>[<5B>w<EFBFBD><77>
1509 1509 $DGL 0,36
1510 1510 000E1 30D4C0 movw ax,#0C0D4H ; -16172 ;[INF] 3, 1
1511 1511 000E4 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1512 1512 ; line 82 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d
1513 1513 ; at_16 );
1514 1514 $DGL 0,37
1515 1515 000E5 17 movw ax,hl ;[INF] 1, 1
1516 1516 000E6 C1 push ax ;[INF] 1, 1
1517 1517 000E7 E6 onew ax ;[INF] 1, 1
1518 1518 000E8 A1 incw ax ;[INF] 1, 1
1519 1519 000E9 C1 push ax ;[INF] 1, 1
1520 1520 000EA 500E mov x,#0EH ; 14 ;[INF] 2, 1
1521 1521 000EC C1 push ax ;[INF] 1, 1
1522 1522 000ED RFD0000 call !bs_F0153 ;[INF] 3, 3
1523 1523 000F0 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1524 1524 ; line 83 :
1525 1525 ; line 84 : // 4. <20>ꎞ<EFBFBD>I<EFBFBD><49>RCOMP<4D><50><EFBFBD>ύX
1526 1526 ; line 85 : dat_16._u16 = swap_endian_16( 0xFF00 );
1527 1527 $DGL 0,40
1528 1528 000F2 F6 clrw ax ;[INF] 1, 1
1529 1529 000F3 90 dec x ;[INF] 1, 1
1530 1530 000F4 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1531 1531 ; line 86 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2,
1532 1532 ; &dat_16 );
1533 1533 $DGL 0,41
1534 1534 000F5 17 movw ax,hl ;[INF] 1, 1
1535 1535 000F6 C1 push ax ;[INF] 1, 1
1536 1536 000F7 E6 onew ax ;[INF] 1, 1
1537 1537 000F8 A1 incw ax ;[INF] 1, 1
1538 1538 000F9 C1 push ax ;[INF] 1, 1
1539 1539 000FA 500C mov x,#0CH ; 12 ;[INF] 2, 1
1540 1540 000FC C1 push ax ;[INF] 1, 1
1541 1541 000FD RFD0000 call !bs_F0153 ;[INF] 3, 3
1542 1542 00100 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1543 1543 ; line 87 :
1544 1544 ; line 88 : // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD>[<5B>J<EFBFBD>[<5B>̎<EFBFBD><CC8E><EFBFBD>
1545 1545 ; line 89 : BT_DET_P = 1;
1546 1546 $DGL 0,44
1547 1547 00102 716201 set1 P1.6 ;[INF] 3, 2
1548 1548 ; line 90 : temp = ( u8 ) ( ( get_adc( ADC_SEL_BATT_DET ) >> 5 ) -1
1549 1549 ; ); // <20><><EFBFBD>ʒl<CA92>O<EFBFBD>̔<EFBFBD><CC94><EFBFBD><EFBFBD>̕<EFBFBD><CC95>A<EFBFBD>C<EFBFBD><43><EFBFBD>f<EFBFBD>b<EFBFBD>N<EFBFBD>X<EFBFBD><58><EFBFBD>킹
1550 1550 $DGL 0,45
1551 1551 00105 300900 movw ax,#09H ; 9 ;[INF] 3, 1
1552 1552 00108 RFD0000 call !_get_adc ;[INF] 3, 3
1553 1553 0010B 62 mov a,c ;[INF] 1, 1
1554 1554 0010C 31DE shrw ax,13 ;[INF] 2, 1
1555 1555 0010E B1 decw ax ;[INF] 1, 1
1556 1556 0010F 60 mov a,x ;[INF] 1, 1
1557 1557 00110 9C07 mov [hl+7],a ; temp ;[INF] 2, 1
1558 1558 ; line 91 : BT_DET_P = 0;
1559 1559 $DGL 0,46
1560 1560 00112 716301 clr1 P1.6 ;[INF] 3, 2
1561 1561 ; line 92 :
1562 1562 ; line 93 : iic_mcu_set_wo_dma( );
1563 1563 $DGL 0,48
1564 1564 00115 ??bb02_PM_init:
1565 1565 00115 ?L0005:
1566 1566 00115 R31040002 bf _iic_mcu_busy,$?L0006 ;[INF] 4, 5
1567 1567 00119 ??bb03_PM_init:
1568 1568 00119 ??eb03_PM_init:
1569 1569 00119 EFFA br $?L0005 ;[INF] 2, 3
1570 1570 0011B ?L0006:
1571 1571 0011B R710200 set1 _iic_mcu_wo_dma ;[INF] 3, 2
1572 1572 0011E ??eb02_PM_init:
1573 1573 ; line 94 : // 5.<2E><><EFBFBD>[<5B>J<EFBFBD>[<5B>ʃp<CA83><70><EFBFBD><EFBFBD><EFBFBD>[<5B>^<5E>̃<EFBFBD><CC83>[<5B>h
1574 1574 ; line 95 : switch ( temp )
1575 1575 $DGL 0,50
1576 1576 0011E 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1
1577 1577 00120 318E shrw ax,8 ;[INF] 2, 1
1578 1578 00122 F7 clrw bc ;[INF] 1, 1
1579 1579 00123 23 subw ax,bc ;[INF] 1, 1
1580 1580 00124 DD0A bz $?L0008 ;[INF] 2, 4
1581 1581 00126 240300 subw ax,#03H ; 3 ;[INF] 3, 1
1582 1582 00129 DD0B bz $?L0009 ;[INF] 2, 4
1583 1583 0012B 240400 subw ax,#04H ; 4 ;[INF] 3, 1
1584 1584 0012E EF06 br $?L0009 ;[INF] 2, 3
1585 1585 ; line 96 : {
1586 1586 00130 ??bb04_PM_init:
1587 1587 ; line 97 : case( BT_VENDER_SHIROBAKO ):
1588 1588 00130 ?L0008:
1589 1589 ; line 98 : system_status.model = MODEL_SHIROBAKO;
1590 1590 $DGL 0,53
1591 1591 00130 RCF030002 mov !_system_status+3,#02H ; 2 ;[INF] 4, 1
1592 1592 ; line 99 : break;
1593 1593 $DGL 0,54
1594 1594 00134 EF2E br $?L0007 ;[INF] 2, 3
1595 1595 ; line 100 :
1596 1596 ; line 101 : case( BT_VENDER_PANA ):
1597 1597 00136 ?L0009:
1598 1598 ; line 102 : case( BT_VENDER_MAXELL ):
1599 1599 ; line 103 : default:
1600 1600 ; line 104 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_BT_PAR
1601 1601 ; AM, 64, &BT_PARAM[0] );
1602 1602 $DGL 0,59
1603 1603 00136 R342F00 movw de,#loww (_BT_PARAM) ;[INF] 3, 1
1604 1604 00139 C5 push de ;[INF] 1, 1
1605 1605 0013A 304000 movw ax,#040H ; 64 ;[INF] 3, 1
1606 1606 0013D C1 push ax ;[INF] 1, 1
1607 1607 0013E C1 push ax ;[INF] 1, 1
1608 1608 0013F RFD0000 call !bs_F0153 ;[INF] 3, 3
1609 1609 00142 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1610 1610 ; line 105 : rcomp = BT_PANA_RCOMP;
1611 1611 $DGL 0,60
1612 1612 00144 R8FEF01 mov a,!_BT_PANA_RCOMP ;[INF] 3, 1
1613 1613 00147 R9F0100 mov !_rcomp,a ;[INF] 3, 1
1614 1614 ; line 106 : temp_co_up = BT_PANA_TEMPCOUP;
1615 1615 $DGL 0,61
1616 1616 0014A RDBF201 movw bc,!_BT_PANA_TEMPCOUP+2 ;[INF] 3, 1
1617 1617 0014D RAFF001 movw ax,!_BT_PANA_TEMPCOUP ;[INF] 3, 1
1618 1618 00150 RBF0200 movw !_temp_co_up,ax ;[INF] 3, 1
1619 1619 00153 33 xchw ax,bc ;[INF] 1, 1
1620 1620 00154 RBF0400 movw !_temp_co_up+2,ax ;[INF] 3, 1
1621 1621 ; line 107 : temp_co_dn = BT_PANA_TEMPCODN;
1622 1622 $DGL 0,62
1623 1623 00157 RDBF601 movw bc,!_BT_PANA_TEMPCODN+2 ;[INF] 3, 1
1624 1624 0015A RAFF401 movw ax,!_BT_PANA_TEMPCODN ;[INF] 3, 1
1625 1625 0015D RBF0600 movw !_temp_co_dn,ax ;[INF] 3, 1
1626 1626 00160 33 xchw ax,bc ;[INF] 1, 1
1627 1627 00161 RBF0800 movw !_temp_co_dn+2,ax ;[INF] 3, 1
1628 1628 ; line 108 : break;
1629 1629 00164 ??eb04_PM_init:
1630 1630 ; line 109 : }
1631 1631 00164 ?L0007:
1632 1632 ; line 110 :
1633 1633 ; line 111 : // 6. 150ms<6D>ȏ<EFBFBD><C88F>҂<EFBFBD>
1634 1634 ; line 112 : wait_ms( 200 );
1635 1635 $DGL 0,67
1636 1636 00164 30C800 movw ax,#0C8H ; 200 ;[INF] 3, 1
1637 1637 00167 RFD0000 call !_wait_ms ;[INF] 3, 3
1638 1638 ; line 113 :
1639 1639 ; line 114 : // 7. OCV<43>Ɂu<C981>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>l<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1640 1640 ; line 115 : dat_16._u16 = swap_endian_16( 0xD4C0 );
1641 1641 $DGL 0,70
1642 1642 0016A 30D4C0 movw ax,#0C0D4H ; -16172 ;[INF] 3, 1
1643 1643 0016D BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1644 1644 ; line 116 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d
1645 1645 ; at_16 );
1646 1646 $DGL 0,71
1647 1647 0016E 17 movw ax,hl ;[INF] 1, 1
1648 1648 0016F C1 push ax ;[INF] 1, 1
1649 1649 00170 E6 onew ax ;[INF] 1, 1
1650 1650 00171 A1 incw ax ;[INF] 1, 1
1651 1651 00172 C1 push ax ;[INF] 1, 1
1652 1652 00173 500E mov x,#0EH ; 14 ;[INF] 2, 1
1653 1653 00175 C1 push ax ;[INF] 1, 1
1654 1654 00176 RFD0000 call !bs_F0153 ;[INF] 3, 3
1655 1655 00179 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1656 1656 ; line 117 :
1657 1657 ; line 118 : // 8. 150<35>`600ms<6D>҂B600ms<6D>͌<EFBFBD><CD8C><EFBFBD>
1658 1658 ; line 119 : wait_ms( 200 );
1659 1659 $DGL 0,74
1660 1660 0017B 30C800 movw ax,#0C8H ; 200 ;[INF] 3, 1
1661 1661 0017E RFD0000 call !_wait_ms ;[INF] 3, 3
1662 1662 ; line 120 :
1663 1663 ; line 121 : // 9. SOC<4F><43><EFBFBD>ǂށB<DE81>x<EFBFBD><78><EFBFBD>t<EFBFBD>@<40>C<EFBFBD>̂<EFBFBD><CC82>߁B
1664 1664 ; line 122 : temp = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R
1665 1665 ; EG_SOC );
1666 1666 $DGL 0,77
1667 1667 00181 300400 movw ax,#04H ; 4 ;[INF] 3, 1
1668 1668 00184 RFD1000 call !bs_F0151 ;[INF] 3, 3
1669 1669 00187 9C07 mov [hl+7],a ; temp ;[INF] 2, 1
1670 1670 ; line 123 :
1671 1671 ; line 124 : if( 0x6D == temp || temp == 0x6E || temp == 0x6F ){
1672 1672 $DGL 0,79
1673 1673 00189 4C6D cmp a,#06DH ; 109 ;[INF] 2, 1
1674 1674 0018B DD0A bz $?L0015 ;[INF] 2, 4
1675 1675 0018D 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1
1676 1676 0018F 4C6E cmp a,#06EH ; 110 ;[INF] 2, 1
1677 1677 00191 DD04 bz $?L0015 ;[INF] 2, 4
1678 1678 00193 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1
1679 1679 00195 4C6F cmp a,#06FH ; 111 ;[INF] 2, 1
1680 1680 00197 ?L0015:
1681 1681 00197 ??bb05_PM_init:
1682 1682 00197 ??eb05_PM_init:
1683 1683 ; line 125 : // <20>J<EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>f<EFBFBD><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>OK<4F>I
1684 1684 ; line 126 : }else{
1685 1685 00197 ??bb06_PM_init:
1686 1686 00197 ??eb06_PM_init:
1687 1687 ; line 127 : // <20><><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>烊<EFBFBD>g<EFBFBD><67><EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD><CC82>H
1688 1688 ; line 128 : }
1689 1689 ; line 129 :
1690 1690 ; line 130 : // 10.<2E><><EFBFBD><EFBFBD>RCOMP<4D><50>OCV<43><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߂<EFBFBD>
1691 1691 ; line 131 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4,
1692 1692 ; origParam );
1693 1693 $DGL 0,86
1694 1694 00197 17 movw ax,hl ;[INF] 1, 1
1695 1695 00198 040300 addw ax,#03H ;[INF] 3, 1
1696 1696 0019B C1 push ax ;[INF] 1, 1
1697 1697 0019C 300400 movw ax,#04H ; 4 ;[INF] 3, 1
1698 1698 0019F C1 push ax ;[INF] 1, 1
1699 1699 001A0 500C mov x,#0CH ; 12 ;[INF] 2, 1
1700 1700 001A2 C1 push ax ;[INF] 1, 1
1701 1701 001A3 RFD0000 call !bs_F0153 ;[INF] 3, 3
1702 1702 001A6 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1703 1703 ; line 132 :
1704 1704 ; line 133 : // 11. <20><><EFBFBD>b<EFBFBD>N
1705 1705 ; line 134 : dat_16._u16 = swap_endian_16( 0x0000 ); // lock key
1706 1706 $DGL 0,89
1707 1707 001A8 F6 clrw ax ;[INF] 1, 1
1708 1708 001A9 BB movw [hl],ax ; dat_16 ;[INF] 1, 1
1709 1709 ; line 135 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, &
1710 1710 ; dat_16 );
1711 1711 $DGL 0,90
1712 1712 001AA 17 movw ax,hl ;[INF] 1, 1
1713 1713 001AB C1 push ax ;[INF] 1, 1
1714 1714 001AC E6 onew ax ;[INF] 1, 1
1715 1715 001AD A1 incw ax ;[INF] 1, 1
1716 1716 001AE C1 push ax ;[INF] 1, 1
1717 1717 001AF 503E mov x,#03EH ; 62 ;[INF] 2, 1
1718 1718 001B1 C1 push ax ;[INF] 1, 1
1719 1719 001B2 RFD0000 call !bs_F0153 ;[INF] 3, 3
1720 1720 001B5 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1721 1721 001B7 ??eb01_PM_init:
1722 1722 ; line 136 :
1723 1723 ; line 137 : // <20><><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD> //
1724 1724 ; line 138 : }
1725 1725 001B7 ?L0004:
1726 1726 ; line 139 :
1727 1727 ; line 140 : // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD>x<EFBFBD><78><EFBFBD><EFBFBD>
1728 1728 ; line 141 : BT_TEMP_P = 1; // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD>x<EFBFBD>Ď<EFBFBD><C48E>X<EFBFBD>^<5E>[<5B>g
1729 1729 $DGL 0,96
1730 1730 001B7 717201 set1 P1.7 ;[INF] 3, 2
1731 1731 ; line 142 : raw_adc_temperature = get_adc( ADC_SEL_BATT_TEMP ); // <20><><EFBFBD>x<EFBFBD><78>
1732 1732 ; temp<6D>B
1733 1733 $DGL 0,97
1734 1734 001BA 300800 movw ax,#08H ; 8 ;[INF] 3, 1
1735 1735 001BD RFD0000 call !_get_adc ;[INF] 3, 3
1736 1736 001C0 62 mov a,c ;[INF] 1, 1
1737 1737 001C1 R9F0000 mov !_raw_adc_temperature,a ;[INF] 3, 1
1738 1738 ; line 143 : renge_task_immed_add( PM_bt_temp_update );
1739 1739 $DGL 0,98
1740 1740 001C4 R30CE01 movw ax,#loww (_PM_bt_temp_update) ;[INF] 3, 1
1741 1741 001C7 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3
1742 1742 ; line 144 :
1743 1743 ; line 145 : // PMIC <20>o<EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ǂݏo<DD8F><6F>
1744 1744 ; line 146 : // temp = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VER
1745 1745 ; );
1746 1746 ; line 147 : // vreg_ctr[ VREG_C_PM_INFO ] = temp;
1747 1747 ; line 148 : // <20>f<EFBFBD>o<EFBFBD>b<EFBFBD>O<EFBFBD>p<EFBFBD>͕ʂɂ܂Ƃ߂<C682>
1748 1748 ; line 149 : }
1749 1749 $DGL 0,104
1750 1750 001CA ??ef_PM_init:
1751 1751 001CA 1008 addw sp,#08H ;[INF] 2, 1
1752 1752 001CC C6 pop hl ;[INF] 1, 1
1753 1753 001CD D7 ret ;[INF] 1, 6
1754 1754 001CE ??ee_PM_init:
1755 1755 ; line 150 :
1756 1756 ; line 151 :
1757 1757 ; line 152 :
1758 1758 ; line 153 :
1759 1759 ; line 154 :
1760 1760 ; line 155 :
1761 1761 ; line 156 : /* ========================================================
1762 1762 ; line 157 : raw_adc_temperature<72>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD>ɕϊ<C995><CF8A><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƂƂ<C682><C682>ɁA
1763 1763 ; line 158 : <20>E<EFBFBD><45><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ɃZ<C983>b<EFBFBD>g
1764 1764 ; line 159 : <20>E<EFBFBD>c<EFBFBD><63>IC<49>ɃZ<C983>b<EFBFBD>g
1765 1765 ; line 160 : todo
1766 1766 ; line 161 : ======================================================== */
1767 1767 ; line 162 : task_status_immed PM_bt_temp_update( )
1768 1768 ; line 163 : {
1769 1769 001CE _PM_bt_temp_update:
1770 1770 $DGL 1,154
1771 1771 001CE C7 push hl ;[INF] 1, 1
1772 1772 001CF C1 push ax ;[INF] 1, 1
1773 1773 001D0 FBF8FF movw hl,sp ;[INF] 3, 1
1774 1774 001D3 ??bf_PM_bt_temp_update:
1775 1775 ; line 164 : static u8 count = 0; // <20><><EFBFBD>܂ɂ<DC82><C982><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɍs<C98D><73><EFBFBD>Ȃ<EFBFBD>
1776 1776 ; line 165 :
1777 1777 ; line 166 : static u8 rawdat_old;
1778 1778 ; line 167 : static s16 temperature; // todo
1779 1779 ; line 168 : u16 newrcomp;
1780 1780 ; line 169 :
1781 1781 ; line 170 : /*
1782 1782 ; line 171 : <20>T<EFBFBD>[<5B>~<7E>X<EFBFBD>^ - 10k<30><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD>̎<EFBFBD><CC8E>A
1783 1783 ; line 172 : <20><><EFBFBD>p<EFBFBD><70><EFBFBD>x<EFBFBD>ł͕<C582><CD95><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̃J<CC83>[<5B>u<EFBFBD><75><EFBFBD>قڃ<D982><DA83>j<EFBFBD>A<EFBFBD>ŁA
1784 1784 ; line 173 : <20><><EFBFBD>c T[<5B><>] = 81.48 - 111.97 x ratio
1785 1785 ; line 174 : TDK T = 81.406 - 111.81 x ratio
1786 1786 ; line 175 : */
1787 1787 ; line 176 : if( rawdat_old != raw_adc_temperature ){
1788 1788 $DGL 0,14
1789 1789 001D3 R8F0A00 mov a,!?L0019 ; rawdat_old ;[INF] 3, 1
1790 1790 001D6 R4F0000 cmp a,!_raw_adc_temperature ;[INF] 3, 1
1791 1791 001D9 DD47 bz $?L0021 ;[INF] 2, 4
1792 1792 001DB ??bb00_PM_bt_temp_update:
1793 1793 ; line 177 : DBG_P_n = 1;
1794 1794 $DGL 0,15
1795 1795 001DB 712202 set1 P2.2 ;[INF] 3, 2
1796 1796 ; line 178 : temperature = 81.45 - 111.9 * raw_adc_temperature/256.0;
1797 1797 $DGL 0,16
1798 1798 001DE R8F0000 mov a,!_raw_adc_temperature ;[INF] 3, 1
1799 1799 001E1 318E shrw ax,8 ;[INF] 2, 1
1800 1800 001E3 F7 clrw bc ;[INF] 1, 1
1801 1801 001E4 RBD00 movw _@RTARG0,ax ;[INF] 2, 1
1802 1802 001E6 13 movw ax,bc ;[INF] 1, 1
1803 1803 001E7 RBD00 movw _@RTARG2,ax ;[INF] 2, 1
1804 1804 001E9 RFD0000 call !@@lstof ;[INF] 3, 3
1805 1805 001EC RC900CDCC movw _@RTARG4,#0CCCDH ; -13107 ;[INF] 4, 1
1806 1806 001F0 30DF42 movw ax,#042DFH ; 17119 ;[INF] 3, 1
1807 1807 001F3 RFD0000 call !@@fmul ;[INF] 3, 3
1808 1808 001F6 RC9000000 movw _@RTARG4,#00H ; 0 ;[INF] 4, 1
1809 1809 001FA 308043 movw ax,#04380H ; 17280 ;[INF] 3, 1
1810 1810 001FD RFD0000 call !@@fdiv ;[INF] 3, 3
1811 1811 00200 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1
1812 1812 00202 RBD00 movw _@RTARG4,ax ;[INF] 2, 1
1813 1813 00204 RAD00 movw ax,_@RTARG2 ;[INF] 2, 1
1814 1814 00206 RC90066E6 movw _@RTARG0,#0E666H ; -6554 ;[INF] 4, 1
1815 1815 0020A RC900A242 movw _@RTARG2,#042A2H ; 17058 ;[INF] 4, 1
1816 1816 0020E RFD0000 call !@@fsub ;[INF] 3, 3
1817 1817 00211 RFD0000 call !@@ftols ;[INF] 3, 3
1818 1818 00214 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1
1819 1819 00216 RBF0C00 movw !?L0020,ax ; temperature ;[INF] 3, 1
1820 1820 ; line 179 : vreg_ctr[VREG_C_BT_TEMP] = (u8)temperature;
1821 1821 $DGL 0,17
1822 1822 00219 R8F0C00 mov a,!?L0020 ; temperature ;[INF] 3, 1
1823 1823 0021C R9F0A00 mov !_vreg_ctr+10,a ;[INF] 3, 1
1824 1824 ; line 180 : DBG_P_n = 0;
1825 1825 $DGL 0,18
1826 1826 0021F 712302 clr1 P2.2 ;[INF] 3, 2
1827 1827 00222 ??eb00_PM_bt_temp_update:
1828 1828 ; line 181 : }
1829 1829 00222 ?L0021:
1830 1830 ; line 182 :
1831 1831 ; line 183 : // <20><><EFBFBD>X<EFBFBD><58><EFBFBD><EFBFBD><EFBFBD>ɂ䂭
1832 1832 ; line 184 : if( count == 0 )
1833 1833 $DGL 0,22
1834 1834 00222 RD50000 cmp0 !?L0018 ; count ;[INF] 3, 1
1835 1835 00225 DF79 bnz $?L0031 ;[INF] 2, 4
1836 1836 ; line 185 : {
1837 1837 00227 ??bb01_PM_bt_temp_update:
1838 1838 ; line 186 : DBG_P_n = 1;
1839 1839 $DGL 0,24
1840 1840 00227 712202 set1 P2.2 ;[INF] 3, 2
1841 1841 ; line 187 : if( vreg_ctr[VREG_C_BT_TEMP] > 20 )
1842 1842 $DGL 0,25
1843 1843 0022A R400A0015 cmp !_vreg_ctr+10,#015H ; 21 ;[INF] 4, 1
1844 1844 0022E DC25 bc $?L0025 ;[INF] 2, 4
1845 1845 ; line 188 : {
1846 1846 00230 ??bb02_PM_bt_temp_update:
1847 1847 ; line 189 : newrcomp = -( ( temperature - 20 ) * temp_co_up );
1848 1848 $DGL 0,27
1849 1849 00230 RFD6000 call !bs_S0144 ;[INF] 3, 3
1850 1850 00233 RFD0000 call !@@lstof ;[INF] 3, 3
1851 1851 00236 RAF0200 movw ax,!_temp_co_up ;[INF] 3, 1
1852 1852 00239 RBD00 movw _@RTARG4,ax ;[INF] 2, 1
1853 1853 0023B RAF0400 movw ax,!_temp_co_up+2 ;[INF] 3, 1
1854 1854 0023E RFD0000 call !@@fmul ;[INF] 3, 3
1855 1855 00241 RFD0000 call !@@frev ;[INF] 3, 3
1856 1856 00244 R31720005 bt _@RTARG3.7,$?L0027 ;[INF] 4, 5
1857 1857 00248 RFD0000 call !@@ftolu ;[INF] 3, 3
1858 1858 0024B EF03 br $?L0028 ;[INF] 2, 3
1859 1859 0024D ?L0027:
1860 1860 0024D RFD0000 call !@@ftols ;[INF] 3, 3
1861 1861 00250 ?L0028:
1862 1862 00250 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1
1863 1863 00252 BB movw [hl],ax ; newrcomp ;[INF] 1, 1
1864 1864 00253 ??eb02_PM_bt_temp_update:
1865 1865 ; line 190 : }
1866 1866 $DGL 0,28
1867 1867 00253 EF23 br $?L0026 ;[INF] 2, 3
1868 1868 00255 ?L0025:
1869 1869 ; line 191 : else
1870 1870 ; line 192 : {
1871 1871 00255 ??bb03_PM_bt_temp_update:
1872 1872 ; line 193 : newrcomp = -( ( temperature - 20 ) * temp_co_dn );
1873 1873 $DGL 0,31
1874 1874 00255 RFD6000 call !bs_S0144 ;[INF] 3, 3
1875 1875 00258 RFD0000 call !@@lstof ;[INF] 3, 3
1876 1876 0025B RAF0600 movw ax,!_temp_co_dn ;[INF] 3, 1
1877 1877 0025E RBD00 movw _@RTARG4,ax ;[INF] 2, 1
1878 1878 00260 RAF0800 movw ax,!_temp_co_dn+2 ;[INF] 3, 1
1879 1879 00263 RFD0000 call !@@fmul ;[INF] 3, 3
1880 1880 00266 RFD0000 call !@@frev ;[INF] 3, 3
1881 1881 00269 R31720005 bt _@RTARG3.7,$?L0029 ;[INF] 4, 5
1882 1882 0026D RFD0000 call !@@ftolu ;[INF] 3, 3
1883 1883 00270 EF03 br $?L0030 ;[INF] 2, 3
1884 1884 00272 ?L0029:
1885 1885 00272 RFD0000 call !@@ftols ;[INF] 3, 3
1886 1886 00275 ?L0030:
1887 1887 00275 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1
1888 1888 00277 BB movw [hl],ax ; newrcomp ;[INF] 1, 1
1889 1889 00278 ??eb03_PM_bt_temp_update:
1890 1890 ; line 194 : }
1891 1891 00278 ?L0026:
1892 1892 ; line 195 : newrcomp += rcomp;
1893 1893 $DGL 0,33
1894 1894 00278 RD90100 mov x,!_rcomp ;[INF] 3, 1
1895 1895 0027B F1 clrb a ;[INF] 1, 1
1896 1896 0027C 610900 addw ax,[hl+0] ; newrcomp ;[INF] 3, 1
1897 1897 0027F BB movw [hl],ax ; newrcomp ;[INF] 1, 1
1898 1898 ; line 196 :
1899 1899 ; line 197 : newrcomp = swap_endian_16( (u16)newrcomp );
1900 1900 $DGL 0,35
1901 1901 00280 318D shlw ax,8 ;[INF] 2, 1
1902 1902 00282 08 xch a,x ;[INF] 1, 1
1903 1903 00283 6E01 or a,[hl+1] ; newrcomp ;[INF] 2, 1
1904 1904 00285 08 xch a,x ;[INF] 1, 1
1905 1905 00286 BB movw [hl],ax ; newrcomp ;[INF] 1, 1
1906 1906 ; line 198 : DBG_P_n = 0;
1907 1907 $DGL 0,36
1908 1908 00287 712302 clr1 P2.2 ;[INF] 3, 2
1909 1909 ; line 199 :
1910 1910 ; line 200 : if( iic_mcu_write
1911 1911 ; line 201 : ( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, &newrcomp
1912 1912 ; ) == ERR_SUCCESS )
1913 1913 $DGL 0,39
1914 1914 0028A 17 movw ax,hl ;[INF] 1, 1
1915 1915 0028B C1 push ax ;[INF] 1, 1
1916 1916 0028C E6 onew ax ;[INF] 1, 1
1917 1917 0028D A1 incw ax ;[INF] 1, 1
1918 1918 0028E C1 push ax ;[INF] 1, 1
1919 1919 0028F 500C mov x,#0CH ; 12 ;[INF] 2, 1
1920 1920 00291 C1 push ax ;[INF] 1, 1
1921 1921 00292 RFD0000 call !bs_F0153 ;[INF] 3, 3
1922 1922 00295 1006 addw sp,#06H ; 6 ;[INF] 2, 1
1923 1923 00297 D2 cmp0 c ;[INF] 1, 1
1924 1924 00298 DF06 bnz $?L0031 ;[INF] 2, 4
1925 1925 ; line 202 : {
1926 1926 0029A ??bb04_PM_bt_temp_update:
1927 1927 ; line 203 : rawdat_old = raw_adc_temperature;
1928 1928 $DGL 0,41
1929 1929 0029A R8F0000 mov a,!_raw_adc_temperature ;[INF] 3, 1
1930 1930 0029D R9F0A00 mov !?L0019,a ; rawdat_old ;[INF] 3, 1
1931 1931 002A0 ??eb04_PM_bt_temp_update:
1932 1932 ; line 204 : }
1933 1933 002A0 ?L0031:
1934 1934 002A0 ??eb01_PM_bt_temp_update:
1935 1935 ; line 205 : }
1936 1936 ; line 206 : count += 1;
1937 1937 $DGL 0,44
1938 1938 002A0 RA00000 inc !?L0018 ; count ;[INF] 3, 2
1939 1939 ; line 207 :
1940 1940 ; line 208 : return ( ERR_SUCCESS );
1941 1941 $DGL 0,46
1942 1942 002A3 F7 clrw bc ;[INF] 1, 1
1943 1943 ; line 209 : }
1944 1944 $DGL 0,47
1945 1945 002A4 ??ef_PM_bt_temp_update:
1946 1946 002A4 C0 pop ax ;[INF] 1, 1
1947 1947 002A5 C6 pop hl ;[INF] 1, 1
1948 1948 002A6 D7 ret ;[INF] 1, 6
1949 1949 002A7 ??ee_PM_bt_temp_update:
1950 1950 ; line 210 :
1951 1951 ; line 211 :
1952 1952 ; line 212 :
1953 1953 ; line 213 : #ifdef _PMIC_TWL_
1954 1954 ; line 214 : u8 blset;
1955 1955 ; line 215 : #endif
1956 1956 ; line 216 :
1957 1957 ; line 217 : #ifndef _PARRADIUM_
1958 1958 ; line 218 : /* ========================================================
1959 1959 ; line 219 : <20>t<EFBFBD><74><EFBFBD>n<EFBFBD>̓d<CC93><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1960 1960 ; line 220 : <20>@<40>X<EFBFBD>e<EFBFBD>[<5B>^<5E>X<EFBFBD>t<EFBFBD><74><EFBFBD>O<EFBFBD>͂<EFBFBD><CD82><EFBFBD><EFBFBD>ɗ<EFBFBD><C997>ĂĂ<C482><C482>܂<EFBFBD><DC82>B
1961 1961 ; line 221 : <20>@<40>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԃ<EFBFBD><D482><EFBFBD><EFBFBD>邵<EFBFBD>A
1962 1962 ; line 222 : <20>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>s<EFBFBD>ł<EFBFBD><C582><EFBFBD><EFBFBD>Γd<CE93><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1963 1963 ; line 223 : <20>ʂ̃^<5E>X<EFBFBD>N<EFBFBD>œd<C593><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͊Ď<CD8A><C48E><EFBFBD><EFBFBD>Ă<EFBFBD><C482>āA<C481>X<EFBFBD>e<EFBFBD>[<5B>^<5E>X<EFBFBD><58><EFBFBD>N<EFBFBD><4E><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD>
1964 1964 ; line 224 : ======================================================== */
1965 1965 ; line 225 : // BSR //
1966 1966 ; line 226 : err PM_LCD_on( )
1967 1967 ; line 227 : {
1968 1968 002A7 _PM_LCD_on:
1969 1969 $DGL 1,184
1970 1970 002A7 C7 push hl ;[INF] 1, 1
1971 1971 002A8 ??bf_PM_LCD_on:
1972 1972 ; line 228 : u8 rv;
1973 1973 ; line 229 :
1974 1974 ; line 230 : PM_VDDLCD_on( );
1975 1975 $DGL 0,4
1976 1976 002A8 RFD7000 call !bs_F0145 ;[INF] 3, 3
1977 1977 ; line 231 :
1978 1978 ; line 232 : wait_ms( DELAY_PM_TSS_50B_AND_TCOM );
1979 1979 $DGL 0,6
1980 1980 002AB 301100 movw ax,#011H ; 17 ;[INF] 3, 1
1981 1981 002AE RFD0000 call !_wait_ms ;[INF] 3, 3
1982 1982 ; line 233 :
1983 1983 ; line 234 : PM_TCOM_on( );
1984 1984 $DGL 0,8
1985 1985 002B1 300F00 movw ax,#0FH ; 15 ;[INF] 3, 1
1986 1986 002B4 RFD3900 call !bs_F0146 ;[INF] 3, 3
1987 1987 ; line 235 :
1988 1988 ; line 236 : wait_ms( DELAY_PM_TCOM_TO_VCS );
1989 1989 $DGL 0,10
1990 1990 002B7 300300 movw ax,#03H ; 3 ;[INF] 3, 1
1991 1991 002BA RFD0000 call !_wait_ms ;[INF] 3, 3
1992 1992 ; line 237 :
1993 1993 ; line 238 : PM_VCS_on( );
1994 1994 $DGL 0,12
1995 1995 002BD 301F00 movw ax,#01FH ; 31 ;[INF] 3, 1
1996 1996 002C0 RFD3900 call !bs_F0146 ;[INF] 3, 3
1997 1997 ; line 239 :
1998 1998 ; line 240 : wait_ms( DELAY_PM_VCS_TO_BL );
1999 1999 $DGL 0,14
2000 2000 002C3 301600 movw ax,#016H ; 22 ;[INF] 3, 1
2001 2001 002C6 RFD0000 call !_wait_ms ;[INF] 3, 3
2002 2002 ; line 241 : #ifdef _PM_BUG_
2003 2003 ; line 242 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0x4A ); // <20>o<EFBFBD>O<EFBFBD><4F>
2004 2004 ; <20><>PMIC<49>΍<EFBFBD>
2005 2005 ; line 243 : #endif
2006 2006 ; line 244 :
2007 2007 ; line 245 : rv = PM_chk_LDSW( );
2008 2008 $DGL 0,19
2009 2009 002C9 RFD4500 call !bs_F0147 ;[INF] 3, 3
2010 2010 002CC 76 mov l,a ;[INF] 1, 1
2011 2011 ; line 246 :
2012 2012 ; line 247 : if( rv != 0 )
2013 2013 $DGL 0,21
2014 2014 002CD D1 cmp0 a ;[INF] 1, 1
2015 2015 002CE DD0D bz $?L0035 ;[INF] 2, 4
2016 2016 ; line 248 : {
2017 2017 002D0 ??bb00_PM_LCD_on:
2018 2018 ; line 249 : // <20>d<EFBFBD><64><EFBFBD>N<EFBFBD><4E><EFBFBD>G<EFBFBD><47><EFBFBD>[<5B>Ȃ<EFBFBD><C882>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD>؂<EFBFBD><D882>Ă<EFBFBD><C482>܂<EFBFBD><DC82>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>ł̓P<CD83>A<EFBFBD><41><EFBFBD><EFBFBD>
2019 2019 ; <20><>
2020 2020 ; line 250 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW;
2021 2021 $DGL 0,24
2022 2022 002D0 R71700F00 set1 !_vreg_ctr+15.7 ;[INF] 4, 2
2023 2023 ; line 251 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON );
2024 2024 $DGL 0,25
2025 2025 002D4 E6 onew ax ;[INF] 1, 1
2026 2026 002D5 A1 incw ax ;[INF] 1, 1
2027 2027 002D6 C1 push ax ;[INF] 1, 1
2028 2028 002D7 5013 mov x,#013H ; 19 ;[INF] 2, 1
2029 2029 002D9 RFD0000 call !_set_irq ;[INF] 3, 3
2030 2030 002DC C0 pop ax ;[INF] 1, 1
2031 2031 ; line 252 :
2032 2032 ; line 253 : SND_DEPOP_DEACT; // 1<>Ń~<7E><><EFBFBD>[<5B>g
2033 2033 002DD ??eb00_PM_LCD_on:
2034 2034 ; line 254 : }
2035 2035 002DD ?L0035:
2036 2036 ; line 255 :
2037 2037 ; line 256 : #ifdef _PMIC_TWL_
2038 2038 ; line 257 : PM_TEG_LCD_dis( 0 );
2039 2039 ; line 258 : blset = ( PM_REG_BIT_BL_U | PM_REG_BIT_BL_L );
2040 2040 ; line 259 : #endif
2041 2041 ; line 260 : return ( rv );
2042 2042 $DGL 0,34
2043 2043 002DD 17 movw ax,hl ;[INF] 1, 1
2044 2044 002DE F1 clrb a ;[INF] 1, 1
2045 2045 002DF 12 movw bc,ax ;[INF] 1, 1
2046 2046 ; line 261 : }
2047 2047 $DGL 0,35
2048 2048 002E0 ??ef_PM_LCD_on:
2049 2049 002E0 C6 pop hl ;[INF] 1, 1
2050 2050 002E1 D7 ret ;[INF] 1, 6
2051 2051 002E2 ??ee_PM_LCD_on:
2052 2052 ; line 262 :
2053 2053 ; line 263 : // BSR //
2054 2054 ; line 264 : void PM_LCD_off()
2055 2055 ; line 265 : {
2056 2056 002E2 _PM_LCD_off:
2057 2057 $DGL 1,195
2058 2058 002E2 C7 push hl ;[INF] 1, 1
2059 2059 002E3 ??bf_PM_LCD_off:
2060 2060 ; line 266 : SND_DEPOP_ACT;
2061 2061 ; line 267 :
2062 2062 ; line 268 : // BL<42>‚<EFBFBD><C282>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2063 2063 ; line 269 : #ifdef _PMIC_TWL_
2064 2064 ; line 270 : if( blset != 0 )
2065 2065 ; line 271 : #else
2066 2066 ; line 272 : if( ( iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) &
2067 2067 ; 0x03 ) != 0 )
2068 2068 $DGL 0,8
2069 2069 002E3 RFD2200 call !bs_F0149 ;[INF] 3, 3
2070 2070 002E6 5C03 and a,#03H ; 3 ;[INF] 2, 1
2071 2071 002E8 D1 cmp0 a ;[INF] 1, 1
2072 2072 002E9 DD3C bz $?L0039 ;[INF] 2, 4
2073 2073 ; line 273 : #endif
2074 2074 ; line 274 : {
2075 2075 002EB ??bb00_PM_LCD_off:
2076 2076 ; line 275 : u8 tot;
2077 2077 ; line 276 :
2078 2078 ; line 277 : PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF )
2079 2079 ; ;
2080 2080 $DGL 0,13
2081 2081 002EB 301400 movw ax,#014H ; 20 ;[INF] 3, 1
2082 2082 002EE RFD4203 call !_PM_BL_set ;[INF] 3, 3
2083 2083 ; line 278 : vreg_ctr[VREG_C_STATUS] &= 0b10011111;
2084 2084 $DGL 0,14
2085 2085 002F1 R340F00 movw de,#loww (_vreg_ctr+15) ;[INF] 3, 1
2086 2086 002F4 89 mov a,[de] ;[INF] 1, 1
2087 2087 002F5 5C9F and a,#09FH ; 159 ;[INF] 2, 1
2088 2088 002F7 99 mov [de],a ;[INF] 1, 1
2089 2089 ; line 279 :
2090 2090 ; line 280 : if( (( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr
2091 2091 ; [ VREG_C_IRQ_MASK3 ] ) != 0 )
2092 2092 $DGL 0,16
2093 2093 002F8 8A0C mov a,[de+12] ;[INF] 2, 1
2094 2094 002FA 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1
2095 2095 002FC 50FF mov x,#0FFH ; 255 ;[INF] 2, 1
2096 2096 002FE 5C14 and a,#014H ; 20 ;[INF] 2, 1
2097 2097 00300 D1 cmp0 a ;[INF] 1, 1
2098 2098 00301 DD1D bz $?L0041 ;[INF] 2, 4
2099 2099 ; line 281 : {
2100 2100 00303 ??bb01_PM_LCD_off:
2101 2101 ; line 282 : vreg_ctr[ VREG_C_IRQ3 ] |= ( ( REG_BIT_BL_U_OFF | RE
2102 2102 ; G_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] );
2103 2103 $DGL 0,18
2104 2104 00303 8A0C mov a,[de+12] ;[INF] 2, 1
2105 2105 00305 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1
2106 2106 00307 5C14 and a,#014H ; 20 ;[INF] 2, 1
2107 2107 00309 RFD1900 call !bs_S0152 ;[INF] 3, 3
2108 2108 ; line 283 : IRQ0_neg;
2109 2109 $DGL 0,19
2110 2110 0030C ??bb02_PM_LCD_off:
2111 2111 0030C 716A27 set1 PM7.6 ;[INF] 3, 2
2112 2112 0030F ??eb02_PM_LCD_off:
2113 2113 ; line 284 : tot = 0;
2114 2114 $DGL 0,20
2115 2115 0030F 5600 mov l,#00H ; 0 ;[INF] 2, 1
2116 2116 ; line 285 : while( !IRQ0 && ( ++tot != 0 ) ){;}
2117 2117 $DGL 0,21
2118 2118 00311 ?L0043:
2119 2119 00311 31620705 bt P7.6,$?L0044 ;[INF] 4, 5
2120 2120 00315 86 inc l ;[INF] 1, 1
2121 2121 00316 66 mov a,l ;[INF] 1, 1
2122 2122 00317 D1 cmp0 a ;[INF] 1, 1
2123 2123 00318 DFF7 bnz $?L0043 ;[INF] 2, 4
2124 2124 0031A ??bb03_PM_LCD_off:
2125 2125 0031A ??eb03_PM_LCD_off:
2126 2126 0031A ?L0044:
2127 2127 ; line 286 : IRQ0_ast;
2128 2128 $DGL 0,22
2129 2129 0031A ??bb04_PM_LCD_off:
2130 2130 0031A 716307 clr1 P7.6 ;[INF] 3, 2
2131 2131 0031D 716B27 clr1 PM7.6 ;[INF] 3, 2
2132 2132 00320 ??eb04_PM_LCD_off:
2133 2133 00320 ??eb01_PM_LCD_off:
2134 2134 ; line 287 : }
2135 2135 00320 ?L0041:
2136 2136 ; line 288 : vreg_ctr[VREG_C_COMMAND2] &= ~( REG_BIT_CMD_BL_U_OFF | R
2137 2137 ; EG_BIT_CMD_BL_L_OFF );
2138 2138 $DGL 0,24
2139 2139 00320 R342200 movw de,#loww (_vreg_ctr+34) ;[INF] 3, 1
2140 2140 00323 89 mov a,[de] ;[INF] 1, 1
2141 2141 00324 5CEB and a,#0EBH ; 235 ;[INF] 2, 1
2142 2142 00326 99 mov [de],a ;[INF] 1, 1
2143 2143 00327 ??eb00_PM_LCD_off:
2144 2144 ; line 289 : }
2145 2145 00327 ?L0039:
2146 2146 ; line 290 :
2147 2147 ; line 291 : #ifdef _PMIC_TWL_
2148 2148 ; line 292 : PM_TEG_LCD_dis( 1 );
2149 2149 ; line 293 : blset = 0;
2150 2150 ; line 294 : #endif
2151 2151 ; line 295 :
2152 2152 ; line 296 : PM_TCOM_VCS_off( );
2153 2153 $DGL 0,32
2154 2154 00327 RFD7000 call !bs_F0145 ;[INF] 3, 3
2155 2155 ; line 297 : wait_ms( DELAY_PM_LCD_OFF );
2156 2156 $DGL 0,33
2157 2157 0032A 303300 movw ax,#033H ; 51 ;[INF] 3, 1
2158 2158 0032D RFD0000 call !_wait_ms ;[INF] 3, 3
2159 2159 ; line 298 :
2160 2160 ; line 299 : PM_VDDLCD_off( ); // <20>c<EFBFBD><63><EFBFBD>Ă<EFBFBD><C482>̑S<CC91><53><EFBFBD>~<7E>߂܂<DF82><DC82>B
2161 2161 $DGL 0,35
2162 2162 00330 F6 clrw ax ;[INF] 1, 1
2163 2163 00331 RFD3900 call !bs_F0146 ;[INF] 3, 3
2164 2164 ; line 300 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW;
2165 2165 $DGL 0,36
2166 2166 00334 R71780F00 clr1 !_vreg_ctr+15.7 ;[INF] 4, 2
2167 2167 ; line 301 :
2168 2168 ; line 302 :
2169 2169 ; line 303 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF );
2170 2170 $DGL 0,39
2171 2171 00338 E6 onew ax ;[INF] 1, 1
2172 2172 00339 C1 push ax ;[INF] 1, 1
2173 2173 0033A 5013 mov x,#013H ; 19 ;[INF] 2, 1
2174 2174 0033C RFD0000 call !_set_irq ;[INF] 3, 3
2175 2175 0033F C0 pop ax ;[INF] 1, 1
2176 2176 ; line 304 : }
2177 2177 $DGL 0,40
2178 2178 00340 ??ef_PM_LCD_off:
2179 2179 00340 C6 pop hl ;[INF] 1, 1
2180 2180 00341 D7 ret ;[INF] 1, 6
2181 2181 00342 ??ee_PM_LCD_off:
2182 2182 ; line 305 :
2183 2183 ; line 306 :
2184 2184 ; line 307 :
2185 2185 ; line 308 : /* ========================================================
2186 2186 ; line 309 : <20>@<40>o<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>C<EFBFBD>g<EFBFBD>̌•<CC8C>on/off
2187 2187 ; line 310 : <20>@<40><><EFBFBD>󂩂<EFBFBD><F382A982>@on/off/<2F>ێ<EFBFBD><DB8E>@<40>̃t<CC83><74><EFBFBD>O<EFBFBD>Ȃ̂Ŗʓ|
2188 2188 ; line 311 : <20>@<40>@<40>Ⴆ<EFBFBD>΁ABL on/on <20>̏<EFBFBD><CC8F>ԂŁAon/on<6F>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ƌ<EFBFBD><C68C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>Aon/on<6F><6E><EFBFBD><EFBFBD>
2189 2189 ; <20><><EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
2190 2190 ; line 312 : ======================================================== */
2191 2191 ; line 313 : err PM_BL_set( u8 dat )
2192 2192 ; line 314 : {
2193 2193 00342 _PM_BL_set:
2194 2194 $DGL 1,223
2195 2195 00342 C7 push hl ;[INF] 1, 1
2196 2196 00343 C1 push ax ;[INF] 1, 1
2197 2197 00344 2004 subw sp,#04H ;[INF] 2, 1
2198 2198 00346 FBF8FF movw hl,sp ;[INF] 3, 1
2199 2199 00349 ??bf_PM_BL_set:
2200 2200 ; line 315 : #ifndef _PMIC_TWL_
2201 2201 ; line 316 : u8 blset;
2202 2202 ; line 317 : #endif
2203 2203 ; line 318 : u8 intset = 0;
2204 2204 $DGL 0,5
2205 2205 00349 CC0200 mov [hl+2],#00H ; intset,0 ;[INF] 3, 1
2206 2206 ; line 319 : // RMW<4D><57><EFBFBD>s<EFBFBD><73>
2207 2207 ; line 320 :
2208 2208 ; line 321 : #ifndef _PMIC_TWL_
2209 2209 ; line 322 : // Read
2210 2210 ; line 323 : blset = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL )
2211 2211 ; ;
2212 2212 $DGL 0,10
2213 2213 0034C RFD2200 call !bs_F0149 ;[INF] 3, 3
2214 2214 0034F 9C03 mov [hl+3],a ; blset ;[INF] 2, 1
2215 2215 ; line 324 : #endif
2216 2216 ; line 325 :
2217 2217 ; line 326 : // Modify
2218 2218 ; line 327 : // ue
2219 2219 ; line 328 : if(( dat & REG_BIT_CMD_BL_U_ON ) != 0 )
2220 2220 $DGL 0,15
2221 2221 00351 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1
2222 2222 00353 5C20 and a,#020H ; 32 ;[INF] 2, 1
2223 2223 00355 D1 cmp0 a ;[INF] 1, 1
2224 2224 00356 DD0E bz $?L0047 ;[INF] 2, 4
2225 2225 ; line 329 : {
2226 2226 00358 ??bb00_PM_BL_set:
2227 2227 ; line 330 : blset |= PM_REG_BIT_BL_U;
2228 2228 $DGL 0,17
2229 2229 00358 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2230 2230 0035A 6C01 or a,#01H ; 1 ;[INF] 2, 1
2231 2231 0035C 9C03 mov [hl+3],a ; blset ;[INF] 2, 1
2232 2232 ; line 331 : intset |= REG_BIT_BL_U_ON;
2233 2233 $DGL 0,18
2234 2234 0035E 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1
2235 2235 00360 6C20 or a,#020H ; 32 ;[INF] 2, 1
2236 2236 00362 9C02 mov [hl+2],a ; intset ;[INF] 2, 1
2237 2237 00364 ??eb00_PM_BL_set:
2238 2238 ; line 332 : }
2239 2239 $DGL 0,19
2240 2240 00364 EF13 br $?L0049 ;[INF] 2, 3
2241 2241 00366 ?L0047:
2242 2242 ; line 333 : else if(( dat & REG_BIT_CMD_BL_U_OFF ) != 0 )
2243 2243 $DGL 0,20
2244 2244 00366 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1
2245 2245 00368 5C10 and a,#010H ; 16 ;[INF] 2, 1
2246 2246 0036A D1 cmp0 a ;[INF] 1, 1
2247 2247 0036B DD0C bz $?L0049 ;[INF] 2, 4
2248 2248 ; line 334 : {
2249 2249 0036D ??bb01_PM_BL_set:
2250 2250 ; line 335 : blset &= ~PM_REG_BIT_BL_U;
2251 2251 $DGL 0,22
2252 2252 0036D 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2253 2253 0036F 5CFE and a,#0FEH ; 254 ;[INF] 2, 1
2254 2254 00371 9C03 mov [hl+3],a ; blset ;[INF] 2, 1
2255 2255 ; line 336 : intset |= REG_BIT_BL_U_OFF;
2256 2256 $DGL 0,23
2257 2257 00373 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1
2258 2258 00375 6C10 or a,#010H ; 16 ;[INF] 2, 1
2259 2259 00377 9C02 mov [hl+2],a ; intset ;[INF] 2, 1
2260 2260 00379 ??eb01_PM_BL_set:
2261 2261 ; line 337 : }
2262 2262 00379 ?L0049:
2263 2263 ; line 338 :
2264 2264 ; line 339 : // shita
2265 2265 ; line 340 : if(( dat & REG_BIT_CMD_BL_L_ON ) != 0 )
2266 2266 $DGL 0,27
2267 2267 00379 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1
2268 2268 0037B 5C08 and a,#08H ; 8 ;[INF] 2, 1
2269 2269 0037D D1 cmp0 a ;[INF] 1, 1
2270 2270 0037E DD0E bz $?L0051 ;[INF] 2, 4
2271 2271 ; line 341 : {
2272 2272 00380 ??bb02_PM_BL_set:
2273 2273 ; line 342 : blset |= PM_REG_BIT_BL_L;
2274 2274 $DGL 0,29
2275 2275 00380 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2276 2276 00382 6C02 or a,#02H ; 2 ;[INF] 2, 1
2277 2277 00384 9C03 mov [hl+3],a ; blset ;[INF] 2, 1
2278 2278 ; line 343 : intset |= REG_BIT_BL_L_ON;
2279 2279 $DGL 0,30
2280 2280 00386 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1
2281 2281 00388 6C08 or a,#08H ; 8 ;[INF] 2, 1
2282 2282 0038A 9C02 mov [hl+2],a ; intset ;[INF] 2, 1
2283 2283 0038C ??eb02_PM_BL_set:
2284 2284 ; line 344 : }
2285 2285 $DGL 0,31
2286 2286 0038C EF13 br $?L0053 ;[INF] 2, 3
2287 2287 0038E ?L0051:
2288 2288 ; line 345 : else if(( dat & REG_BIT_CMD_BL_L_OFF ) != 0 )
2289 2289 $DGL 0,32
2290 2290 0038E 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1
2291 2291 00390 5C04 and a,#04H ; 4 ;[INF] 2, 1
2292 2292 00392 D1 cmp0 a ;[INF] 1, 1
2293 2293 00393 DD0C bz $?L0053 ;[INF] 2, 4
2294 2294 ; line 346 : {
2295 2295 00395 ??bb03_PM_BL_set:
2296 2296 ; line 347 : blset &= ~PM_REG_BIT_BL_L;
2297 2297 $DGL 0,34
2298 2298 00395 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2299 2299 00397 5CFD and a,#0FDH ; 253 ;[INF] 2, 1
2300 2300 00399 9C03 mov [hl+3],a ; blset ;[INF] 2, 1
2301 2301 ; line 348 : intset |= REG_BIT_BL_L_OFF;
2302 2302 $DGL 0,35
2303 2303 0039B 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1
2304 2304 0039D 6C04 or a,#04H ; 4 ;[INF] 2, 1
2305 2305 0039F 9C02 mov [hl+2],a ; intset ;[INF] 2, 1
2306 2306 003A1 ??eb03_PM_BL_set:
2307 2307 ; line 349 : }
2308 2308 003A1 ?L0053:
2309 2309 ; line 350 :
2310 2310 ; line 351 : /*
2311 2311 ; line 352 : SoC<6F><43>PWM<57><4D><EFBFBD>o<EFBFBD><6F><EFBFBD>悤<EFBFBD><E682A4><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>x<EFBFBD><78><EFBFBD><EFBFBD><EFBFBD>L<EFBFBD>邽<EFBFBD>߁A<DF81>X<EFBFBD>e<EFBFBD>[
2312 2312 ; <20>^<5E>X<EFBFBD><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2313 2313 ; line 353 : <20>X<EFBFBD>V<EFBFBD><56><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD><DC82>B
2314 2314 ; line 354 : // Write
2315 2315 ; line 355 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset );
2316 2316 ; line 356 : if( blset != 0x00 ){
2317 2317 ; line 357 : wait_ms( 10 );
2318 2318 ; line 358 : }
2319 2319 ; line 359 : */
2320 2320 ; line 360 : vreg_ctr[VREG_C_STATUS] = (( vreg_ctr[VREG_C_STATUS] & 0b100
2321 2321 ; 11111 )
2322 2322 ; line 361 : | (( blset << 6 ) | ( blset << 4 )
2323 2323 ; ) & 0b01100000 );
2324 2324 $DGL 0,48
2325 2325 003A1 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1
2326 2326 003A4 5C9F and a,#09FH ; 159 ;[INF] 2, 1
2327 2327 003A6 72 mov c,a ;[INF] 1, 1
2328 2328 003A7 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2329 2329 003A9 318E shrw ax,8 ;[INF] 2, 1
2330 2330 003AB 316D shlw ax,6 ;[INF] 2, 1
2331 2331 003AD 14 movw de,ax ;[INF] 1, 1
2332 2332 003AE 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2333 2333 003B0 318E shrw ax,8 ;[INF] 2, 1
2334 2334 003B2 314D shlw ax,4 ;[INF] 2, 1
2335 2335 003B4 616D or a,d ;[INF] 2, 1
2336 2336 003B6 08 xch a,x ;[INF] 1, 1
2337 2337 003B7 616C or a,e ;[INF] 2, 1
2338 2338 003B9 5C60 and a,#060H ; 96 ;[INF] 2, 1
2339 2339 003BB 6162 or c,a ;[INF] 2, 1
2340 2340 003BD 62 mov a,c ;[INF] 1, 1
2341 2341 003BE R9F0F00 mov !_vreg_ctr+15,a ;[INF] 3, 1
2342 2342 ; line 362 : // PMIC<49><43>BL<42>̃r<CC83>b<EFBFBD>g<EFBFBD>ƁAMCU<43><55>STATUS<55><53><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̃r<CC83>b<EFBFBD>g<EFBFBD>ʒu<CA92><75><EFBFBD>t<EFBFBD><74>
2343 2343 ; <20><><EFBFBD>ߓ<EFBFBD><DF93><EFBFBD><EFBFBD>ւ<EFBFBD>
2344 2344 ; line 363 :
2345 2345 ; line 364 : {
2346 2346 003C1 ??bb04_PM_BL_set:
2347 2347 ; line 365 : u8 tot;
2348 2348 ; line 366 :
2349 2349 ; line 367 : if( ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 )
2350 2350 $DGL 0,54
2351 2351 003C1 R8F1B00 mov a,!_vreg_ctr+27 ;[INF] 3, 1
2352 2352 003C4 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1
2353 2353 003C6 50FF mov x,#0FFH ; 255 ;[INF] 2, 1
2354 2354 003C8 5E02 and a,[hl+2] ; intset ;[INF] 2, 1
2355 2355 003CA D1 cmp0 a ;[INF] 1, 1
2356 2356 003CB DD22 bz $?L0055 ;[INF] 2, 4
2357 2357 ; line 368 : {
2358 2358 003CD ??bb05_PM_BL_set:
2359 2359 ; line 369 : vreg_ctr[ VREG_C_IRQ3 ] |= ( intset & ~vreg_ctr[ VRE
2360 2360 ; G_C_IRQ_MASK3 ] );
2361 2361 $DGL 0,56
2362 2362 003CD R8F1B00 mov a,!_vreg_ctr+27 ;[INF] 3, 1
2363 2363 003D0 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1
2364 2364 003D2 5E02 and a,[hl+2] ; intset ;[INF] 2, 1
2365 2365 003D4 RFD1900 call !bs_S0152 ;[INF] 3, 3
2366 2366 ; line 370 : IRQ0_neg;
2367 2367 $DGL 0,57
2368 2368 003D7 ??bb06_PM_BL_set:
2369 2369 003D7 716A27 set1 PM7.6 ;[INF] 3, 2
2370 2370 003DA ??eb06_PM_BL_set:
2371 2371 ; line 371 : tot = 0;
2372 2372 $DGL 0,58
2373 2373 003DA CC0100 mov [hl+1],#00H ; tot,0 ;[INF] 3, 1
2374 2374 ; line 372 : while( !IRQ0 && ( ++tot != 0 ) ){;} // <20><><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD>
2375 2375 ; <20>꒼<EFBFBD><EA92BC>
2376 2376 $DGL 0,59
2377 2377 003DD ?L0057:
2378 2378 003DD 31620708 bt P7.6,$?L0058 ;[INF] 4, 5
2379 2379 003E1 615901 inc [hl+1] ; tot ;[INF] 3, 2
2380 2380 003E4 8C01 mov a,[hl+1] ; tot ;[INF] 2, 1
2381 2381 003E6 D1 cmp0 a ;[INF] 1, 1
2382 2382 003E7 DFF4 bnz $?L0057 ;[INF] 2, 4
2383 2383 003E9 ??bb07_PM_BL_set:
2384 2384 003E9 ??eb07_PM_BL_set:
2385 2385 003E9 ?L0058:
2386 2386 ; line 373 : IRQ0_ast;
2387 2387 $DGL 0,60
2388 2388 003E9 ??bb08_PM_BL_set:
2389 2389 003E9 716307 clr1 P7.6 ;[INF] 3, 2
2390 2390 003EC 716B27 clr1 PM7.6 ;[INF] 3, 2
2391 2391 003EF ??eb08_PM_BL_set:
2392 2392 003EF ??eb05_PM_BL_set:
2393 2393 ; line 374 : }
2394 2394 003EF ?L0055:
2395 2395 003EF ??eb04_PM_BL_set:
2396 2396 ; line 375 : }
2397 2397 ; line 376 :
2398 2398 ; line 377 : // Write
2399 2399 ; line 378 : if( blset != 0 ) // BL<42><4C><EFBFBD>t<EFBFBD><74><EFBFBD><EFBFBD><EFBFBD>ꍇ<EFBFBD>̓E<CD83>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>܂Ȃ<DC82><C882><EFBFBD>PWM
2400 2400 ; <20><><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>炸
2401 2401 $DGL 0,65
2402 2402 003EF 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2403 2403 003F1 D1 cmp0 a ;[INF] 1, 1
2404 2404 003F2 DD06 bz $?L0059 ;[INF] 2, 4
2405 2405 ; line 379 : /// <20>V<EFBFBD><56><EFBFBD>b<EFBFBD>g<EFBFBD>_<EFBFBD>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD>邱<EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD><EFBFBD>
2406 2406 ; line 380 : {
2407 2407 003F4 ??bb09_PM_BL_set:
2408 2408 ; line 381 : wait_ms( 10 );
2409 2409 $DGL 0,68
2410 2410 003F4 300A00 movw ax,#0AH ; 10 ;[INF] 3, 1
2411 2411 003F7 RFD0000 call !_wait_ms ;[INF] 3, 3
2412 2412 003FA ??eb09_PM_BL_set:
2413 2413 ; line 382 : }
2414 2414 003FA ?L0059:
2415 2415 ; line 383 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset );
2416 2416 $DGL 0,70
2417 2417 003FA 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1
2418 2418 003FC 318E shrw ax,8 ;[INF] 2, 1
2419 2419 003FE C1 push ax ;[INF] 1, 1
2420 2420 003FF 5004 mov x,#04H ; 4 ;[INF] 2, 1
2421 2421 00401 C1 push ax ;[INF] 1, 1
2422 2422 00402 RFD0500 call !bs_F0154 ;[INF] 3, 3
2423 2423 00405 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2424 2424 ; line 384 :
2425 2425 ; line 385 : return( ERR_SUCCESS ); // <20><><EFBFBD><EFBFBD><EFBFBD>łُ͈<CD88><D98F>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD>s<EFBFBD>v
2426 2426 $DGL 0,72
2427 2427 00407 F7 clrw bc ;[INF] 1, 1
2428 2428 ; line 386 : }
2429 2429 $DGL 0,73
2430 2430 00408 ??ef_PM_BL_set:
2431 2431 00408 1006 addw sp,#06H ;[INF] 2, 1
2432 2432 0040A C6 pop hl ;[INF] 1, 1
2433 2433 0040B D7 ret ;[INF] 1, 6
2434 2434 0040C ??ee_PM_BL_set:
2435 2435 ; line 387 :
2436 2436 ; line 388 :
2437 2437 ; line 389 :
2438 2438 ; line 390 : /* ========================================================
2439 2439 ; line 391 : <20>t<EFBFBD><74><EFBFBD>̑Ό<CC91><CE8C>d<EFBFBD><64><EFBFBD>̐ݒ<CC90><DD92><EFBFBD><EFBFBD>s<EFBFBD><73><EFBFBD>܂<EFBFBD><DC82>B
2440 2440 ; line 392 : <20><><EFBFBD>z<EFBFBD><7A><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̓<EFBFBD><CC93>e<EFBFBD>𑗂邾<F0919782><E982BE>
2441 2441 ; line 393 : ======================================================== */
2442 2442 ; line 394 : err PM_LCD_vcom_set( )
2443 2443 ; line 395 : {
2444 2444 0040C _PM_LCD_vcom_set:
2445 2445 $DGL 1,274
2446 2446 0040C C7 push hl ;[INF] 1, 1
2447 2447 0040D ??bf_PM_LCD_vcom_set:
2448 2448 ; line 396 : u8 rv;
2449 2449 ; line 397 :
2450 2450 ; line 398 : rv = iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC
2451 2451 ; 1, vreg_ctr[VREG_C_VCOM_T] ); // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>ƂɁAPMIC<49>̓o<CD83>[<5B>X
2452 2452 ; <20>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݕs<DD95><73>
2453 2453 $DGL 0,4
2454 2454 0040D RD90300 mov x,!_vreg_ctr+3 ;[INF] 3, 1
2455 2455 00410 F1 clrb a ;[INF] 1, 1
2456 2456 00411 C1 push ax ;[INF] 1, 1
2457 2457 00412 5006 mov x,#06H ; 6 ;[INF] 2, 1
2458 2458 00414 C1 push ax ;[INF] 1, 1
2459 2459 00415 RFD0500 call !bs_F0154 ;[INF] 3, 3
2460 2460 00418 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2461 2461 0041A 62 mov a,c ;[INF] 1, 1
2462 2462 0041B 76 mov l,a ;[INF] 1, 1
2463 2463 ; line 399 : rv |= iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DA
2464 2464 ; C2, vreg_ctr[VREG_C_VCOM_B] );
2465 2465 $DGL 0,5
2466 2466 0041C RD90400 mov x,!_vreg_ctr+4 ;[INF] 3, 1
2467 2467 0041F F1 clrb a ;[INF] 1, 1
2468 2468 00420 C1 push ax ;[INF] 1, 1
2469 2469 00421 5007 mov x,#07H ; 7 ;[INF] 2, 1
2470 2470 00423 C1 push ax ;[INF] 1, 1
2471 2471 00424 RFD0500 call !bs_F0154 ;[INF] 3, 3
2472 2472 00427 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2473 2473 00429 62 mov a,c ;[INF] 1, 1
2474 2474 0042A 6166 or l,a ;[INF] 2, 1
2475 2475 ; line 400 : return ( rv );
2476 2476 $DGL 0,6
2477 2477 0042C 17 movw ax,hl ;[INF] 1, 1
2478 2478 0042D F1 clrb a ;[INF] 1, 1
2479 2479 0042E 12 movw bc,ax ;[INF] 1, 1
2480 2480 ; line 401 : }
2481 2481 $DGL 0,7
2482 2482 0042F ??ef_PM_LCD_vcom_set:
2483 2483 0042F C6 pop hl ;[INF] 1, 1
2484 2484 00430 D7 ret ;[INF] 1, 6
2485 2485 00431 ??ee_PM_LCD_vcom_set:
2486 2486 ; line 402 :
2487 2487 ; line 403 :
2488 2488 ; line 404 :
2489 2489 ; line 405 : #else
2490 2490 ; line 406 : // <20>p<EFBFBD><70><EFBFBD>f<EFBFBD>B<EFBFBD>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SoC<6F>Ń`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682>APMIC<49><43><EFBFBD>t<EFBFBD><74><EFBFBD><EFBFBD><EFBFBD>‚Ȃ<C282><C882><EFBFBD>
2491 2491 ; <20>ĂȂ<C482><C882>̂<EFBFBD>
2492 2492 ; line 407 : // <20>ُ<EFBFBD><D98F>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>悤<EFBFBD>Ƀ_<C983>~<7E>[<5B>֐<EFBFBD><D690>ɂ<EFBFBD><C982><EFBFBD>
2493 2493 ; line 408 : err PM_LCD_on( )
2494 2494 ; line 409 : {
2495 2495 ; line 410 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW;
2496 2496 ; line 411 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON );
2497 2497 ; line 412 : SND_DEPOP_DEACT; // 1<>Ń~<7E><><EFBFBD>[<5B>g
2498 2498 ; line 413 : return ( ERR_SUCCESS );
2499 2499 ; line 414 : }
2500 2500 ; line 415 :
2501 2501 ; line 416 :
2502 2502 ; line 417 : void PM_LCD_off( )
2503 2503 ; line 418 : {
2504 2504 ; line 419 : SND_DEPOP_ACT;
2505 2505 ; line 420 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW;
2506 2506 ; line 421 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF );
2507 2507 ; line 422 : }
2508 2508 ; line 423 :
2509 2509 ; line 424 :
2510 2510 ; line 425 : err PM_BL_set( u8 )
2511 2511 ; line 426 : {
2512 2512 ; line 427 : wait_ms( 10 );
2513 2513 ; line 428 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & ~(
2514 2514 ; REG_BIT_BL_U | REG_BIT_BL_L )
2515 2515 ; line 429 : | ( command_bl_set & REG_BIT_CMD_BL_U_ON )? REG_BIT_BL_U
2516 2516 ; line 430 : | ( command_bl_set & REG_BIT_CMD_BL_L_ON )? REG_BIT_BL_L
2517 2517 ; line 431 : );
2518 2518 ; line 432 : return ( PM_chk_LDSW( ) );
2519 2519 ; line 433 : }
2520 2520 ; line 434 :
2521 2521 ; line 435 :
2522 2522 ; line 436 : err PM_LCD_vcom_set( )
2523 2523 ; line 437 : {
2524 2524 ; line 438 : return ( ERR_SUCCESS );
2525 2525 ; line 439 : }
2526 2526 ; line 440 :
2527 2527 ; line 441 : #endif
2528 2528 ; line 442 :
2529 2529 ; line 443 :
2530 2530 ; line 444 :
2531 2531 ; line 445 : /* ========================================================
2532 2532 ; line 446 : <20><><EFBFBD>ŁA<C581><41><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>鎞<EFBFBD>̂<EFBFBD><CC82><EFBFBD>
2533 2533 ; line 447 : <20>@I2C<32>̎<EFBFBD><CC8E>荇<EFBFBD><E88D87><EFBFBD>̊֌W<D68C>ł<EFBFBD><C582><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD>
2534 2534 ; line 448 : ======================================================== */
2535 2535 ; line 449 : task_status_immed tski_vcom_set( )
2536 2536 ; line 450 : {
2537 2537 00431 _tski_vcom_set:
2538 2538 $DGL 1,281
2539 2539 00431 ??bf_tski_vcom_set:
2540 2540 ; line 451 : PM_LCD_vcom_set( );
2541 2541 $DGL 0,2
2542 2542 00431 RFD0C04 call !_PM_LCD_vcom_set ;[INF] 3, 3
2543 2543 ; line 452 : return ( ERR_FINISED );
2544 2544 $DGL 0,3
2545 2545 00434 F7 clrw bc ;[INF] 1, 1
2546 2546 ; line 453 : }
2547 2547 $DGL 0,4
2548 2548 00435 ??ef_tski_vcom_set:
2549 2549 00435 D7 ret ;[INF] 1, 6
2550 2550 00436 ??ee_tski_vcom_set:
2551 2551 ; line 454 :
2552 2552 ; line 455 :
2553 2553 ; line 456 :
2554 2554 ; line 457 : /* ========================================================
2555 2555 ; line 458 : <20>V<EFBFBD>[<5B>P<EFBFBD><50><EFBFBD>X<EFBFBD>̒ʂ<CC92><CA82>d<EFBFBD><64><EFBFBD>𗧂<EFBFBD><F097A782>グ<EFBFBD>Ă䂫<C482>܂<EFBFBD><DC82>B
2556 2556 ; line 459 : <20>Ԓl 0 <20>Ō<EFBFBD><C58C>܂Ő<DC82><C590><EFBFBD><EFBFBD>Ɋ<EFBFBD><C98A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B
2557 2557 ; line 460 : 1 <20>V<EFBFBD><56><EFBFBD>[<5B>g<EFBFBD>Ȃǂœd<C593><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>肫<EFBFBD><E882AB><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD><EFBFBD>
2558 2558 ; line 461 :
2559 2559 ; line 462 : <20>ȉ<EFBFBD><C889>̃s<CC83><73><EFBFBD>͎<EFBFBD><CD8E>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ő<EFBFBD><C591><EFBFBD><EFBFBD>E<EFBFBD>Ď<EFBFBD><C48E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
2560 2560 ; line 463 : <20>EPOW_CONT1,2 TEG<45>d<EFBFBD><64><EFBFBD>̂<EFBFBD>
2561 2561 ; line 464 : ======================================================== */
2562 2562 ; line 465 : err PM_sys_pow_on( )
2563 2563 ; line 466 : {
2564 2564 00436 _PM_sys_pow_on:
2565 2565 $DGL 1,287
2566 2566 00436 C7 push hl ;[INF] 1, 1
2567 2567 00437 ??bf_PM_sys_pow_on:
2568 2568 ; line 467 : #ifdef _PMIC_CTR_
2569 2569 ; line 468 : u8 temp;
2570 2570 ; line 469 :
2571 2571 ; line 470 : // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD>x<EFBFBD><78><EFBFBD><EFBFBD>
2572 2572 ; line 471 : while( ADCEN != 0 )
2573 2573 $DGL 0,6
2574 2574 00437 ?L0067:
2575 2575 00437 C7 push hl ;[INF] 1, 1
2576 2576 00438 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1
2577 2577 0043B 71D4 mov1 CY,[hl].5 ;[INF] 2, 1
2578 2578 0043D C6 pop hl ;[INF] 1, 1
2579 2579 0043E DCF7 bc $?L0067 ;[INF] 2, 4
2580 2580 ; line 472 : {;
2581 2581 00440 ??bb00_PM_sys_pow_on:
2582 2582 00440 ??eb00_PM_sys_pow_on:
2583 2583 ; line 473 : }
2584 2584 ; line 474 : BT_TEMP_P = 1;
2585 2585 $DGL 0,9
2586 2586 00440 717201 set1 P1.7 ;[INF] 3, 2
2587 2587 ; line 475 : vreg_ctr[VREG_C_BT_TEMP] = get_adc( ADC_SEL_BATT_TEMP );
2588 2588 $DGL 0,10
2589 2589 00443 300800 movw ax,#08H ; 8 ;[INF] 3, 1
2590 2590 00446 RFD0000 call !_get_adc ;[INF] 3, 3
2591 2591 00449 62 mov a,c ;[INF] 1, 1
2592 2592 0044A R9F0A00 mov !_vreg_ctr+10,a ;[INF] 3, 1
2593 2593 ; line 476 : BT_TEMP_P = 0;
2594 2594 $DGL 0,11
2595 2595 0044D 717301 clr1 P1.7 ;[INF] 3, 2
2596 2596 ; line 477 : PM_bt_temp_update( ); // <20><><EFBFBD>x<EFBFBD><78>temp<6D>B<EFBFBD>@<40>c<EFBFBD><63>IC<49>ɍs<C98D><73><EFBFBD>܂<EFBFBD>
2597 2597 $DGL 0,12
2598 2598 00450 RFDCE01 call !_PM_bt_temp_update ;[INF] 3, 3
2599 2599 ; line 478 :
2600 2600 ; line 479 : // <20>c<EFBFBD>ʃ`<60>F<EFBFBD>b<EFBFBD>N
2601 2601 ; line 480 : PM_get_batt_left(); // <20><><EFBFBD>ɁAPM_init()<29><><EFBFBD><EFBFBD><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD>
2602 2602 ; <20><><EFBFBD>K<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B(<28><><EFBFBD><EFBFBD><EFBFBD>v)
2603 2603 $DGL 0,15
2604 2604 00453 RFD2106 call !_PM_get_batt_left ;[INF] 3, 3
2605 2605 ; line 481 : // todo: batt remain -> volatage?
2606 2606 ; line 482 : if( vreg_ctr[VREG_C_BT_REMAIN] < 0 )
2607 2607 $DGL 0,17
2608 2608 00456 RD50B00 cmp0 !_vreg_ctr+11 ;[INF] 3, 1
2609 2609 00459 DE03 bnc $?L0069 ;[INF] 2, 4
2610 2610 ; line 483 : {
2611 2611 0045B ??bb01_PM_sys_pow_on:
2612 2612 ; line 484 : return ( 1 );
2613 2613 $DGL 0,19
2614 2614 0045B E7 onew bc ;[INF] 1, 1
2615 2615 0045C EF49 br $?L0066 ;[INF] 2, 3
2616 2616 0045E ??eb01_PM_sys_pow_on:
2617 2617 ; line 485 : }
2618 2618 0045E ?L0069:
2619 2619 ; line 486 :
2620 2620 ; line 487 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>グ
2621 2621 ; line 488 : // PM_reset_ast( ); <20>s<EFBFBD>v PM_LDSW_on<6F>܂<EFBFBD><DC82><EFBFBD>
2622 2622 ; line 489 : RESET2_ast;
2623 2623 $DGL 0,24
2624 2624 0045E ??bb02_PM_sys_pow_on:
2625 2625 0045E 711300 clr1 P0.1 ;[INF] 3, 2
2626 2626 00461 711B20 clr1 PM0.1 ;[INF] 3, 2
2627 2627 00464 ??eb02_PM_sys_pow_on:
2628 2628 ; line 490 : FCRAM_RST_ast;
2629 2629 $DGL 0,25
2630 2630 00464 ??bb03_PM_sys_pow_on:
2631 2631 00464 710303 clr1 P3.0 ;[INF] 3, 2
2632 2632 00467 ??eb03_PM_sys_pow_on:
2633 2633 ; line 491 :
2634 2634 ; line 492 : PM_LDSW_on( );
2635 2635 $DGL 0,27
2636 2636 00467 RFD5300 call !bs_F0148 ;[INF] 3, 3
2637 2637 ; line 493 :
2638 2638 ; line 494 : wait_ms( 1 );
2639 2639 $DGL 0,29
2640 2640 0046A E6 onew ax ;[INF] 1, 1
2641 2641 0046B RFD0000 call !_wait_ms ;[INF] 3, 3
2642 2642 ; line 495 : #ifdef _PM_BUG_
2643 2643 ; line 496 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0xCA ); // <20>o<EFBFBD>O<EFBFBD><4F>
2644 2644 ; <20><>PMIC<49>΍<EFBFBD> OVP<56><50><EFBFBD><EFBFBD>
2645 2645 ; line 497 : #endif
2646 2646 ; line 498 :
2647 2647 ; line 499 : wait_ms( DELAY_PM_TW_PWUP );
2648 2648 $DGL 0,34
2649 2649 0046E RFD0A00 call !bs_F0155 ;[INF] 3, 3
2650 2650 ; line 500 :
2651 2651 ; line 501 : PM_VDD_on( );
2652 2652 $DGL 0,36
2653 2653 00471 300F00 movw ax,#0FH ; 15 ;[INF] 3, 1
2654 2654 00474 RFD2E00 call !bs_F0150 ;[INF] 3, 3
2655 2655 ; line 502 : wait_ms( DELAY_PM_TW_PWUP );
2656 2656 $DGL 0,37
2657 2657 00477 RFD0A00 call !bs_F0155 ;[INF] 3, 3
2658 2658 ; line 503 :
2659 2659 ; line 504 : PM_VDD50A_on( ); // <20>t<EFBFBD><74><EFBFBD>d<EFBFBD><64><EFBFBD>ł͂Ȃ<CD82><C882>Aled<65>Ƃ<EFBFBD><C682>Ɏg<C98E><67><EFBFBD><EFBFBD><EFBFBD>̂ł<CC82>
2660 2660 $DGL 0,39
2661 2661 0047A 301F00 movw ax,#01FH ; 31 ;[INF] 3, 1
2662 2662 0047D RFD2E00 call !bs_F0150 ;[INF] 3, 3
2663 2663 ; line 505 :
2664 2664 ; line 506 : wait_ms( DELAY_PM_TW_PWUP );
2665 2665 $DGL 0,41
2666 2666 00480 RFD0A00 call !bs_F0155 ;[INF] 3, 3
2667 2667 ; line 507 :
2668 2668 ; line 508 : PM_VDD_normMode();
2669 2669 $DGL 0,43
2670 2670 00483 F6 clrw ax ;[INF] 1, 1
2671 2671 00484 C1 push ax ;[INF] 1, 1
2672 2672 00485 5005 mov x,#05H ; 5 ;[INF] 2, 1
2673 2673 00487 C1 push ax ;[INF] 1, 1
2674 2674 00488 RFD0500 call !bs_F0154 ;[INF] 3, 3
2675 2675 0048B 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2676 2676 ; line 509 : #ifdef _PM_BUG_
2677 2677 ; line 510 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, 0x
2678 2678 ; 03 ); // <20>o<EFBFBD>O<EFBFBD><4F><EFBFBD><EFBFBD>PMIC<49>΍<EFBFBD> <20><><EFBFBD><EFBFBD>PWM
2679 2679 ; line 511 : #endif
2680 2680 ; line 512 : if( PM_chk_LDSW( ) == 0 )
2681 2681 $DGL 0,47
2682 2682 0048D RFD4500 call !bs_F0147 ;[INF] 3, 3
2683 2683 00490 D1 cmp0 a ;[INF] 1, 1
2684 2684 00491 DF03 bnz $?L0071 ;[INF] 2, 4
2685 2685 ; line 513 : {
2686 2686 00493 ??bb04_PM_sys_pow_on:
2687 2687 ; line 514 : return ( ERR_ERR );
2688 2688 $DGL 0,49
2689 2689 00493 E7 onew bc ;[INF] 1, 1
2690 2690 00494 EF11 br $?L0066 ;[INF] 2, 3
2691 2691 00496 ??eb04_PM_sys_pow_on:
2692 2692 ; line 515 : }
2693 2693 00496 ?L0071:
2694 2694 ; line 516 : FCRAM_RST_neg;
2695 2695 $DGL 0,51
2696 2696 00496 ??bb05_PM_sys_pow_on:
2697 2697 00496 710203 set1 P3.0 ;[INF] 3, 2
2698 2698 00499 ??eb05_PM_sys_pow_on:
2699 2699 ; line 517 : PM_reset_neg();
2700 2700 $DGL 0,52
2701 2701 00499 300300 movw ax,#03H ; 3 ;[INF] 3, 1
2702 2702 0049C C1 push ax ;[INF] 1, 1
2703 2703 0049D C1 push ax ;[INF] 1, 1
2704 2704 0049E RFD0500 call !bs_F0154 ;[INF] 3, 3
2705 2705 004A1 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2706 2706 ; line 518 : RESET2_neg;
2707 2707 $DGL 0,53
2708 2708 004A3 ??bb06_PM_sys_pow_on:
2709 2709 004A3 711A20 set1 PM0.1 ;[INF] 3, 2
2710 2710 004A6 ??eb06_PM_sys_pow_on:
2711 2711 ; line 519 : /*
2712 2712 ; line 520 : wait_ms( 100 );
2713 2713 ; line 521 : {
2714 2714 ; line 522 : // CODEC <20>s<EFBFBD>背<EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2715 2715 ; line 523 : u8 codec_reg_init[3] = { 0,0,0 };
2716 2716 ; line 524 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg
2717 2717 ; _init );
2718 2718 ; line 525 : }
2719 2719 ; line 526 : */
2720 2720 ; line 527 :
2721 2721 ; line 528 : #else
2722 2722 ; line 529 : // TWL PMIC
2723 2723 ; line 530 : u8 temp;
2724 2724 ; line 531 :
2725 2725 ; line 532 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2726 2726 ; line 533 : PM_reset_ast();
2727 2727 ; line 534 : RESET2_ast;
2728 2728 ; line 535 : FCRAM_RST_ast;
2729 2729 ; line 536 :
2730 2730 ; line 537 : PM_TEG_PWSW = 1;
2731 2731 ; line 538 : wait_ms( 160 );
2732 2732 ; line 539 : PM_TEG_PWSW = 0;
2733 2733 ; line 540 :
2734 2734 ; line 541 :
2735 2735 ; line 542 : // <20>c<EFBFBD>ʊm<CA8A>F
2736 2736 ; line 543 : temp = 99;
2737 2737 ; line 544 : if( temp < 5 )
2738 2738 ; line 545 : {
2739 2739 ; line 546 : return ( ERR_ERR );
2740 2740 ; line 547 : }
2741 2741 ; line 548 : vreg_ctr[VREG_C_BT_REMAIN] = temp;
2742 2742 ; line 549 : FCRAM_RST_neg;
2743 2743 ; line 550 : PM_reset_neg();
2744 2744 ; line 551 : RESET2_neg;
2745 2745 ; line 552 : wait_ms( 100 );
2746 2746 ; line 553 : if( !RESET1_n )
2747 2747 ; line 554 : {
2748 2748 ; line 555 : // <20>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>s
2749 2749 ; line 556 : PM_reset_ast();
2750 2750 ; line 557 : RESET2_ast;
2751 2751 ; line 558 : FCRAM_RST_ast;
2752 2752 ; line 559 : return ( ERR_ERR );
2753 2753 ; line 560 : }
2754 2754 ; line 561 : /*
2755 2755 ; line 562 : { // CODEC <20>s<EFBFBD>背<EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2756 2756 ; line 563 : u8 codec_reg_init[3] = { 0,0,0 };
2757 2757 ; line 564 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg
2758 2758 ; _init );
2759 2759 ; line 565 : }
2760 2760 ; line 566 : */
2761 2761 ; line 567 : #endif
2762 2762 ; line 568 :
2763 2763 ; line 569 : return ( ERR_SUCCESS );
2764 2764 $DGL 0,104
2765 2765 004A6 F7 clrw bc ;[INF] 1, 1
2766 2766 ; line 570 : }
2767 2767 004A7 ?L0066:
2768 2768 $DGL 0,105
2769 2769 004A7 ??ef_PM_sys_pow_on:
2770 2770 004A7 C6 pop hl ;[INF] 1, 1
2771 2771 004A8 D7 ret ;[INF] 1, 6
2772 2772 004A9 ??ee_PM_sys_pow_on:
2773 2773 ; line 571 :
2774 2774 ; line 572 :
2775 2775 ; line 573 :
2776 2776 ; line 574 :
2777 2777 ; line 575 :
2778 2778 ; line 576 :
2779 2779 ; line 577 :
2780 2780 ; line 578 : /* ========================================================
2781 2781 ; line 579 : <20>d<EFBFBD><64>OFF<46>V<EFBFBD>[<5B>P<EFBFBD><50><EFBFBD>X
2782 2782 ; line 580 : todo: <20>d<EFBFBD><64><EFBFBD>ُ<EFBFBD><D98F>f<EFBFBD>̏ꍇ
2783 2783 ; line 581 : ======================================================== */
2784 2784 ; line 582 : err PM_sys_pow_off( )
2785 2785 ; line 583 : {
2786 2786 004A9 _PM_sys_pow_off:
2787 2787 $DGL 1,322
2788 2788 004A9 ??bf_PM_sys_pow_off:
2789 2789 ; line 584 : #ifdef _PMIC_CTR_
2790 2790 ; line 585 : // PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF );
2791 2791 ; line 586 : // PM_LCD_off( ); // TCOM,VCS OFF <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD>
2792 2792 ; <20>܂<EFBFBD><DC82>B
2793 2793 ; line 587 :
2794 2794 ; line 588 : PM_reset_ast( );
2795 2795 $DGL 0,6
2796 2796 004A9 RFD5300 call !bs_F0148 ;[INF] 3, 3
2797 2797 ; line 589 : RESET2_ast;
2798 2798 $DGL 0,7
2799 2799 004AC ??bb00_PM_sys_pow_off:
2800 2800 004AC 711300 clr1 P0.1 ;[INF] 3, 2
2801 2801 004AF 711B20 clr1 PM0.1 ;[INF] 3, 2
2802 2802 004B2 ??eb00_PM_sys_pow_off:
2803 2803 ; line 590 : FCRAM_RST_ast;
2804 2804 $DGL 0,8
2805 2805 004B2 ??bb01_PM_sys_pow_off:
2806 2806 004B2 710303 clr1 P3.0 ;[INF] 3, 2
2807 2807 004B5 ??eb01_PM_sys_pow_off:
2808 2808 ; line 591 :
2809 2809 ; line 592 : PM_off( );
2810 2810 $DGL 0,10
2811 2811 004B5 F6 clrw ax ;[INF] 1, 1
2812 2812 004B6 RFD2E00 call !bs_F0150 ;[INF] 3, 3
2813 2813 ; line 593 :
2814 2814 ; line 594 : PM_LDSW_off( );
2815 2815 $DGL 0,12
2816 2816 004B9 F6 clrw ax ;[INF] 1, 1
2817 2817 004BA C1 push ax ;[INF] 1, 1
2818 2818 004BB 5003 mov x,#03H ; 3 ;[INF] 2, 1
2819 2819 004BD C1 push ax ;[INF] 1, 1
2820 2820 004BE RFD0500 call !bs_F0154 ;[INF] 3, 3
2821 2821 004C1 1004 addw sp,#04H ; 4 ;[INF] 2, 1
2822 2822 ; line 595 : #else
2823 2823 ; line 596 :
2824 2824 ; line 597 : if( RESET1_n )
2825 2825 ; line 598 : {
2826 2826 ; line 599 : PM_reset_ast();
2827 2827 ; line 600 : RESET2_ast;
2828 2828 ; line 601 : FCRAM_RST_ast;
2829 2829 ; line 602 : PM_TEG_PWSW = 1;
2830 2830 ; line 603 : wait_ms( 250 );
2831 2831 ; line 604 : wait_ms( 250 );
2832 2832 ; line 605 : wait_ms( 250 );
2833 2833 ; line 606 : PM_TEG_PWSW = 0;
2834 2834 ; line 607 : }
2835 2835 ; line 608 : PM_reset_ast();
2836 2836 ; line 609 : RESET2_ast;
2837 2837 ; line 610 : FCRAM_RST_ast;
2838 2838 ; line 611 :
2839 2839 ; line 612 : #endif
2840 2840 ; line 613 : return ( ERR_SUCCESS );
2841 2841 $DGL 0,31
2842 2842 004C3 F7 clrw bc ;[INF] 1, 1
2843 2843 ; line 614 : }
2844 2844 $DGL 0,32
2845 2845 004C4 ??ef_PM_sys_pow_off:
2846 2846 004C4 D7 ret ;[INF] 1, 6
2847 2847 004C5 ??ee_PM_sys_pow_off:
2848 2848 ; line 615 :
2849 2849 ; line 616 :
2850 2850 ; line 617 :
2851 2851 ; line 618 : /* ========================================================
2852 2852 ; line 619 : <20>d<EFBFBD>r<EFBFBD>̊Ǘ<CC8A>
2853 2853 ; line 620 :
2854 2854 ; line 621 : <20>ȉ<EFBFBD><C889>̃s<CC83><73><EFBFBD>͎<EFBFBD><CD8E>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ő<EFBFBD><C591><EFBFBD><EFBFBD>E<EFBFBD>Ď<EFBFBD><C48E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
2855 2855 ; line 622 : <20>EPM_BT_AUTH <20><><EFBFBD><EFBFBD><EFBFBD>AGPI in
2856 2856 ; line 623 : <20>EPM_CHARGE_n CCIC /CHG in
2857 2857 ; line 624 : <20>EPM_CHARGE_ERR_n /FLT in
2858 2858 ; line 625 : <20>EPM_EXTDC_n /DOK INTP4 in
2859 2859 ; line 626 : <20>EPM_CHARGE_EN_n /CEN out
2860 2860 ; line 627 :
2861 2861 ; line 628 : <20>ȉ<EFBFBD><C889>̕<EFBFBD><CC95>͊֌W<D68C><57><EFBFBD>肻<EFBFBD><E882BB><EFBFBD>ł<EFBFBD><C582><EFBFBD><EFBFBD>ʂ̂Ƃ<CC82><C682><EFBFBD><EFBFBD>Ŏ<EFBFBD><C58E>ɊĎ<C98A><C48E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD><DC82>B
2862 2862 ; line 629 : <20>ELED_Pow R, B, Charge tsk_LED
2863 2863 ; line 630 : <20>EBT_TEMP,_P tsk_ADC
2864 2864 ; line 631 :
2865 2865 ; line 632 : PM_EXTDC<44>͊<EFBFBD><CD8A>荞<EFBFBD>݃<EFBFBD><DD83>C<EFBFBD><43><EFBFBD>ɂ<EFBFBD><C982>邩<EFBFBD><E982A9>
2866 2866 ; line 633 : ======================================================== */
2867 2867 ; line 634 : #define INTERVAL_TSK_BATT 250
2868 2868 ; line 635 :
2869 2869 ; line 636 : void tsk_batt( )
2870 2870 ; line 637 : {
2871 2871 004C5 _tsk_batt:
2872 2872 $DGL 1,336
2873 2873 004C5 ??bf_tsk_batt:
2874 2874 ; line 638 : static u8 task_interval = 0;
2875 2875 ; line 639 : static u8 charge_hys = 0; // <20>q<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD>V<EFBFBD>X<EFBFBD>ŏ<EFBFBD><C58F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD>
2876 2876 ; <20><><EFBFBD>Ƃ<EFBFBD><C682>P
2877 2877 ; line 640 : static bit pm_extdc_old;
2878 2878 ; line 641 :
2879 2879 ; line 642 : if( task_interval-- != 0 )
2880 2880 $DGL 0,6
2881 2881 004C5 R8F0100 mov a,!?L0077 ; task_interval ;[INF] 3, 1
2882 2882 004C8 RB00100 dec !?L0077 ; task_interval ;[INF] 3, 2
2883 2883 004CB D1 cmp0 a ;[INF] 1, 1
2884 2884 004CC 61E8 skz ;[INF] 2, 1
2885 2885 004CE RED6C05 br !?L0076 ;[INF] 3, 3
2886 2886 ; line 643 : {
2887 2887 004D1 ??bb00_tsk_batt:
2888 2888 ; line 644 : return;
2889 2889 004D1 ??eb00_tsk_batt:
2890 2890 ; line 645 : }
2891 2891 ; line 646 : else
2892 2892 ; line 647 : {
2893 2893 004D1 ??bb01_tsk_batt:
2894 2894 ; line 648 : task_interval = (u8)( INTERVAL_TSK_BATT / SYS_INTERVAL_T
2895 2895 ; ICK );
2896 2896 $DGL 0,12
2897 2897 004D1 RCF010080 mov !?L0077,#080H ; task_interval,128 ;[INF] 4, 1
2898 2898 004D5 ??eb01_tsk_batt:
2899 2899 ; line 649 : }
2900 2900 ; line 650 :
2901 2901 ; line 651 :
2902 2902 ; line 652 : // <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E>H //
2903 2903 ; line 653 : if( pm_extdc_old != !PM_EXTDC_n )
2904 2904 $DGL 0,17
2905 2905 004D5 710407 mov1 CY,P7.0 ;[INF] 3, 1
2906 2906 004D8 E6 onew ax ;[INF] 1, 1
2907 2907 004D9 6130 subc x,a ;[INF] 2, 1
2908 2908 004DB 12 movw bc,ax ;[INF] 1, 1
2909 2909 004DC F6 clrw ax ;[INF] 1, 1
2910 2910 004DD R710400 mov1 CY,?L0079 ;[INF] 3, 1
2911 2911 004E0 6110 addc x,a ;[INF] 2, 1
2912 2912 004E2 43 cmpw ax,bc ;[INF] 1, 1
2913 2913 004E3 DD2B bz $?L0085 ;[INF] 2, 4
2914 2914 ; line 654 : {
2915 2915 004E5 ??bb02_tsk_batt:
2916 2916 ; line 655 : pm_extdc_old = !PM_EXTDC_n;
2917 2917 $DGL 0,19
2918 2918 004E5 710407 mov1 CY,P7.0 ;[INF] 3, 1
2919 2919 004E8 E6 onew ax ;[INF] 1, 1
2920 2920 004E9 6130 subc x,a ;[INF] 2, 1
2921 2921 004EB 60 mov a,x ;[INF] 1, 1
2922 2922 004EC 61FB rorc a,1 ;[INF] 2, 1
2923 2923 004EE R710100 mov1 ?L0079,CY ;[INF] 3, 2
2924 2924 ; line 656 : if( pm_extdc_old )
2925 2925 $DGL 0,20
2926 2926 004F1 R3104000F bf ?L0079,$?L0088 ;[INF] 4, 5
2927 2927 ; line 657 : {
2928 2928 004F5 ??bb03_tsk_batt:
2929 2929 ; line 658 : set_bit( 1, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP
2930 2930 ; PLY );
2931 2931 $DGL 0,22
2932 2932 004F5 ??bb04_tsk_batt:
2933 2933 004F5 ??bb05_tsk_batt:
2934 2934 004F5 R71300F00 set1 !_vreg_ctr+15.3 ;[INF] 4, 2
2935 2935 004F9 ??eb05_tsk_batt:
2936 2936 004F9 ??bb06_tsk_batt:
2937 2937 004F9 ??eb06_tsk_batt:
2938 2938 ; line 659 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_CONNECT );
2939 2939 $DGL 0,23
2940 2940 004F9 ??eb04_tsk_batt:
2941 2941 004F9 E6 onew ax ;[INF] 1, 1
2942 2942 004FA A1 incw ax ;[INF] 1, 1
2943 2943 004FB C1 push ax ;[INF] 1, 1
2944 2944 004FC 5011 mov x,#011H ; 17 ;[INF] 2, 1
2945 2945 004FE RFD0000 call !_set_irq ;[INF] 3, 3
2946 2946 00501 C0 pop ax ;[INF] 1, 1
2947 2947 00502 ??eb03_tsk_batt:
2948 2948 ; line 660 : }
2949 2949 $DGL 0,24
2950 2950 00502 EF0C br $?L0085 ;[INF] 2, 3
2951 2951 ; line 661 : else
2952 2952 ; line 662 : {
2953 2953 00504 ??bb07_tsk_batt:
2954 2954 ; line 663 : set_bit( 0, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP
2955 2955 ; PLY );
2956 2956 $DGL 0,27
2957 2957 00504 ??bb08_tsk_batt:
2958 2958 00504 ??bb09_tsk_batt:
2959 2959 00504 ??eb09_tsk_batt:
2960 2960 00504 ?L0088:
2961 2961 00504 ??bb0A_tsk_batt:
2962 2962 00504 R71380F00 clr1 !_vreg_ctr+15.3 ;[INF] 4, 2
2963 2963 00508 ??eb0A_tsk_batt:
2964 2964 00508 ??eb08_tsk_batt:
2965 2965 ; line 664 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_DISC );
2966 2966 $DGL 0,28
2967 2967 00508 E6 onew ax ;[INF] 1, 1
2968 2968 00509 C1 push ax ;[INF] 1, 1
2969 2969 0050A 5011 mov x,#011H ; 17 ;[INF] 2, 1
2970 2970 0050C RFD0000 call !_set_irq ;[INF] 3, 3
2971 2971 0050F C0 pop ax ;[INF] 1, 1
2972 2972 00510 ??eb07_tsk_batt:
2973 2973 ; line 665 : }
2974 2974 00510 ?L0085:
2975 2975 00510 ??eb02_tsk_batt:
2976 2976 ; line 666 : }
2977 2977 ; line 667 :
2978 2978 ; line 668 :
2979 2979 ; line 669 : // <20>[<5B>d ///////////////////////////
2980 2980 ; line 670 : // <20><><EFBFBD>x<EFBFBD>t<EFBFBD><74><EFBFBD>q<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD>V<EFBFBD>X
2981 2981 ; line 671 : if( vreg_ctr[VREG_C_BT_TEMP] < 0x36 )
2982 2982 $DGL 0,35
2983 2983 00510 R400A0036 cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1
2984 2984 00514 61D8 sknc ;[INF] 2, 1
2985 2985 ; line 672 : {
2986 2986 00516 ??bb0B_tsk_batt:
2987 2987 ; line 673 : charge_hys = 1;
2988 2988 $DGL 0,37
2989 2989 00516 RE50200 oneb !?L0078 ; charge_hys ;[INF] 3, 1
2990 2990 00519 ??eb0B_tsk_batt:
2991 2991 ; line 674 : }
2992 2992 00519 ?L0090:
2993 2993 ; line 675 :
2994 2994 ; line 676 : if( ( 1 < vreg_ctr[VREG_C_BT_TEMP] )
2995 2995 ; line 677 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) )
2996 2996 $DGL 0,41
2997 2997 00519 R400A0002 cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1
2998 2998 0051D DC09 bc $?L0092 ;[INF] 2, 4
2999 2999 0051F R400A002C cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1
3000 3000 00523 61D8 sknc ;[INF] 2, 1
3001 3001 ; line 678 : {
3002 3002 00525 ??bb0C_tsk_batt:
3003 3003 ; line 679 : charge_hys = 0;
3004 3004 $DGL 0,43
3005 3005 00525 RF50200 clrb !?L0078 ; charge_hys ;[INF] 3, 1
3006 3006 00528 ??eb0C_tsk_batt:
3007 3007 ; line 680 : }
3008 3008 00528 ?L0092:
3009 3009 ; line 681 :
3010 3010 ; line 682 : if( ( ( charge_hys == 1 )
3011 3011 ; line 683 : && ( 1 < vreg_ctr[VREG_C_BT_TEMP] )
3012 3012 ; line 684 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) )
3013 3013 ; line 685 : ||
3014 3014 $DGL 0,49
3015 3015 00528 R40020001 cmp !?L0078,#01H ; charge_hys,1 ;[INF] 4, 1
3016 3016 0052C DF0C bnz $?L0097 ;[INF] 2, 4
3017 3017 0052E R400A0002 cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1
3018 3018 00532 DC06 bc $?L0097 ;[INF] 2, 4
3019 3019 00534 R400A002C cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1
3020 3020 00538 DC0B bc $?L0096 ;[INF] 2, 4
3021 3021 0053A ?L0097:
3022 3022 ; line 686 : ( ( charge_hys == 0 )
3023 3023 $DGL 0,50
3024 3024 0053A RD50200 cmp0 !?L0078 ; charge_hys ;[INF] 3, 1
3025 3025 0053D DF0B bnz $?L0094 ;[INF] 2, 4
3026 3026 ; line 687 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) ) )
3027 3027 $DGL 0,51
3028 3028 0053F R400A0036 cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1
3029 3029 00543 DE05 bnc $?L0094 ;[INF] 2, 4
3030 3030 00545 ?L0096:
3031 3031 ; line 688 : {
3032 3032 00545 ??bb0D_tsk_batt:
3033 3033 ; line 689 : #ifndef _MODEL_WM0_
3034 3034 ; line 690 : BT_CHG_ENABLE(); // <20><><EFBFBD>x<EFBFBD>͈<EFBFBD>OK<4F>ŏ[<5B>d<EFBFBD>ĊJ
3035 3035 $DGL 0,54
3036 3036 00545 713304 clr1 P4.3 ;[INF] 3, 2
3037 3037 00548 ??eb0D_tsk_batt:
3038 3038 ; line 691 : }
3039 3039 $DGL 0,55
3040 3040 00548 EF03 br $?L0095 ;[INF] 2, 3
3041 3041 0054A ?L0094:
3042 3042 ; line 692 : else
3043 3043 ; line 693 : {
3044 3044 0054A ??bb0E_tsk_batt:
3045 3045 ; line 694 : BT_CHG_DISABLE(); // <20><><EFBFBD>x<EFBFBD>댯<EFBFBD>I<EFBFBD>@<40>[<5B>d<EFBFBD><64><EFBFBD>~
3046 3046 $DGL 0,58
3047 3047 0054A 713204 set1 P4.3 ;[INF] 3, 2
3048 3048 0054D ??eb0E_tsk_batt:
3049 3049 ; line 695 : #endif
3050 3050 ; line 696 : }
3051 3051 0054D ?L0095:
3052 3052 ; line 697 : #ifdef _MODEL_WM0_
3053 3053 ; line 698 : // CHG_ENABLE<4C>s<EFBFBD><73><EFBFBD><EFBFBD> /WL_RST <20>ɔz<C994><7A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>̂<EFBFBD>
3054 3054 ; line 699 : #endif
3055 3055 ; line 700 :
3056 3056 ; line 701 : // <20>[<5B>d //
3057 3057 ; line 702 : // <20><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD>݁Bmisc<73>̒<EFBFBD><CC92>ł<EFBFBD><C582>낵<EFBFBD><EB82B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>B
3058 3058 ; line 703 : set_bit( !BT_CHG_n, vreg_ctr[VREG_C_STATUS], REG_BIT_BATT_CH
3059 3059 ; ARGE );
3060 3060 $DGL 0,67
3061 3061 0054D ??bb0F_tsk_batt:
3062 3062 0054D 31120506 bt P5.1,$?L0098 ;[INF] 4, 5
3063 3063 00551 ??bb10_tsk_batt:
3064 3064 00551 R71400F00 set1 !_vreg_ctr+15.4 ;[INF] 4, 2
3065 3065 00555 ??eb10_tsk_batt:
3066 3066 00555 EF04 br $?L0099 ;[INF] 2, 3
3067 3067 00557 ?L0098:
3068 3068 00557 ??bb11_tsk_batt:
3069 3069 00557 R71480F00 clr1 !_vreg_ctr+15.4 ;[INF] 4, 2
3070 3070 0055B ??eb11_tsk_batt:
3071 3071 0055B ?L0099:
3072 3072 0055B ??eb0F_tsk_batt:
3073 3073 ; line 704 : LED_CHARGE = !BT_CHG_n ? 1 : 0;
3074 3074 $DGL 0,68
3075 3075 0055B 31120503 bt P5.1,$?L0100 ;[INF] 4, 5
3076 3076 0055F E6 onew ax ;[INF] 1, 1
3077 3077 00560 EF01 br $?L0101 ;[INF] 2, 3
3078 3078 00562 ?L0100:
3079 3079 00562 F6 clrw ax ;[INF] 1, 1
3080 3080 00563 ?L0101:
3081 3081 00563 60 mov a,x ;[INF] 1, 1
3082 3082 00564 61FB rorc a,1 ;[INF] 2, 1
3083 3083 00566 714102 mov1 P2.4,CY ;[INF] 3, 2
3084 3084 ; line 705 :
3085 3085 ; line 706 :
3086 3086 ; line 707 : // <20>d<EFBFBD>r<EFBFBD>c<EFBFBD><63> //
3087 3087 ; line 708 : PM_get_batt_left();
3088 3088 $DGL 0,72
3089 3089 00569 RFD2106 call !_PM_get_batt_left ;[INF] 3, 3
3090 3090 ; line 709 :
3091 3091 ; line 710 : // dubug monitor
3092 3092 ; line 711 :
3093 3093 ; line 712 : return;
3094 3094 ; line 713 : }
3095 3095 0056C ?L0076:
3096 3096 $DGL 0,77
3097 3097 0056C ??ef_tsk_batt:
3098 3098 0056C D7 ret ;[INF] 1, 6
3099 3099 0056D ??ee_tsk_batt:
3100 3100 ; line 714 :
3101 3101 ; line 715 :
3102 3102 ; line 716 :
3103 3103 ; line 717 :
3104 3104 ; line 718 : /*=========================================================
3105 3105 ; line 719 : extDC<44><43><EFBFBD>荞<EFBFBD><E88D9E>
3106 3106 ; line 720 : <20>d<EFBFBD><64>OFF<46><46><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>i<EFBFBD>[<5B>d<EFBFBD>̉<EFBFBD><CC89>x<EFBFBD>Ď<EFBFBD><C48E>̂<EFBFBD><CC82>߁j<DF81>̂<EFBFBD>
3107 3107 ; line 721 : <20><><EFBFBD>i<EFBFBD>̓|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O(pm)
3108 3108 ; line 722 : =========================================================*/
3109 3109 ; line 723 : __interrupt void intp4_extdc( )
3110 3110 ; line 724 : {
3111 3111
3112 3112 ----- @@BASE CSEG BASE
3113 3113 00000 _intp4_extdc:
3114 3114 $DGL 1,417
3115 3115 00000 ??bf_intp4_extdc:
3116 3116 ; line 725 : ;
3117 3117 ; line 726 : }
3118 3118 $DGL 0,3
3119 3119 00000 ??ef_intp4_extdc:
3120 3120 00000 61FC reti ;[INF] 2, 6
3121 3121 00002 ??ee_intp4_extdc:
3122 3122 ; line 727 :
3123 3123 ; line 728 :
3124 3124 ; line 729 :
3125 3125 ; line 730 : /*=========================================================
3126 3126 ; line 731 : <20>t<EFBFBD>^<5E>J<EFBFBD><4A><EFBFBD>‚ߊ<C282><DF8A>荞<EFBFBD><E88D9E>
3127 3127 ; line 732 : <20><><EFBFBD>i<EFBFBD>̓|<7C>[<5B><><EFBFBD>O(misc)
3128 3128 ; line 733 : =========================================================*/
3129 3129 ; line 734 : __interrupt void intp5_shell( )
3130 3130 ; line 735 : {
3131 3131 00002 _intp5_shell:
3132 3132 $DGL 1,423
3133 3133 00002 ??bf_intp5_shell:
3134 3134 ; line 736 : ;
3135 3135 ; line 737 : }
3136 3136 $DGL 0,3
3137 3137 00002 ??ef_intp5_shell:
3138 3138 00002 61FC reti ;[INF] 2, 6
3139 3139 00004 ??ee_intp5_shell:
3140 3140 ; line 738 :
3141 3141 ; line 739 :
3142 3142 ; line 740 : /*=========================================================
3143 3143 ; line 741 : <20><>PMIC<49>ւ̃R<CC83>}<7D><><EFBFBD>h<EFBFBD><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
3144 3144 ; line 742 : =========================================================*/
3145 3145 ; line 743 : __interrupt void intp6_PM_irq( )
3146 3146 ; line 744 : {
3147 3147 00004 _intp6_PM_irq:
3148 3148 $DGL 1,429
3149 3149 00004 C1 push ax ;[INF] 1, 1
3150 3150 00005 C3 push bc ;[INF] 1, 1
3151 3151 00006 C5 push de ;[INF] 1, 1
3152 3152 00007 C7 push hl ;[INF] 1, 1
3153 3153 00008 520C mov c,#0CH ;[INF] 2, 1
3154 3154 0000A 92 dec c ;[INF] 1, 1
3155 3155 0000B 92 dec c ;[INF] 1, 1
3156 3156 0000C R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1
3157 3157 0000F C1 push ax ;[INF] 1, 1
3158 3158 00010 DFF8 bnz $$-6 ;[INF] 2, 4
3159 3159 00012 8EFD mov a,ES ;[INF] 2, 1
3160 3160 00014 70 mov x,a ;[INF] 1, 1
3161 3161 00015 8EFC mov a,CS ;[INF] 2, 1
3162 3162 00017 C1 push ax ;[INF] 1, 1
3163 3163 00018 ??bf_intp6_PM_irq:
3164 3164 ; line 745 : if( system_status.pwr_state == ON )
3165 3165 $DGL 0,2
3166 3166 00018 R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1
3167 3167 0001C DF09 bnz $?L0108 ;[INF] 2, 4
3168 3168 ; line 746 : {
3169 3169 0001E ??bb00_intp6_PM_irq:
3170 3170 ; line 747 : EI();
3171 3171 $DGL 0,4
3172 3172 0001E 717AFA ei ;[INF] 3, 4
3173 3173 ; line 748 : renge_task_immed_add( ntr_pmic_comm );
3174 3174 $DGL 0,5
3175 3175 00021 R306D05 movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1
3176 3176 00024 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3
3177 3177 00027 ??eb00_intp6_PM_irq:
3178 3178 ; line 749 : }
3179 3179 00027 ?L0108:
3180 3180 ; line 750 : }
3181 3181 $DGL 0,7
3182 3182 00027 ??ef_intp6_PM_irq:
3183 3183 00027 C0 pop ax ;[INF] 1, 1
3184 3184 00028 9EFC mov CS,a ;[INF] 2, 1
3185 3185 0002A 60 mov a,x ;[INF] 1, 1
3186 3186 0002B 9EFD mov ES,a ;[INF] 2, 1
3187 3187 0002D R340000 movw de,#_@SEGAX ;[INF] 3, 1
3188 3188 00030 5206 mov c,#06H ;[INF] 2, 1
3189 3189 00032 C0 pop ax ;[INF] 1, 1
3190 3190 00033 B9 movw [de],ax ;[INF] 1, 1
3191 3191 00034 A5 incw de ;[INF] 1, 1
3192 3192 00035 A5 incw de ;[INF] 1, 1
3193 3193 00036 92 dec c ;[INF] 1, 1
3194 3194 00037 DFF9 bnz $$-5 ;[INF] 2, 4
3195 3195 00039 C6 pop hl ;[INF] 1, 1
3196 3196 0003A C4 pop de ;[INF] 1, 1
3197 3197 0003B C2 pop bc ;[INF] 1, 1
3198 3198 0003C C0 pop ax ;[INF] 1, 1
3199 3199 0003D 61FC reti ;[INF] 2, 6
3200 3200 0003F ??ee_intp6_PM_irq:
3201 3201 ; line 751 :
3202 3202 ; line 752 :
3203 3203 ; line 753 :
3204 3204 ; line 754 : extern u8 temp_debug_3;
3205 3205 ; line 755 :
3206 3206 ; line 756 : /* ========================================================
3207 3207 ; line 757 : PMIC<49><43><EFBFBD><EFBFBD><EFBFBD>̊<EFBFBD><CC8A>荞<EFBFBD>݂<EFBFBD><DD82>󂯂āANTR PMIC<49>݊<EFBFBD><DD8A><EFBFBD><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD>烊<EFBFBD>[<5B>h
3208 3208 ; line 758 : ======================================================== */
3209 3209 ; line 759 : task_status_immed ntr_pmic_comm( )
3210 3210 ; line 760 : {
3211 3211
3212 3212 ----- ROM_CODE CSEG BASE
3213 3213 0056D _ntr_pmic_comm:
3214 3214 $DGL 1,439
3215 3215 0056D C7 push hl ;[INF] 1, 1
3216 3216 0056E ??bf_ntr_pmic_comm:
3217 3217 ; line 761 : static u8 reg_shadow;
3218 3218 ; line 762 : u8 reg1_old;
3219 3219 ; line 763 : u8 irq_work = 0;
3220 3220 $DGL 0,4
3221 3221 0056E 5700 mov h,#00H ; 0 ;[INF] 2, 1
3222 3222 ; line 764 :
3223 3223 ; line 765 : reg1_old = reg_shadow;
3224 3224 $DGL 0,6
3225 3225 00570 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3226 3226 00573 76 mov l,a ;[INF] 1, 1
3227 3227 ; line 766 : reg_shadow = iic_mcu_read_a_byte( IIC_SLA_CODEC, CODEC_REG_P
3228 3228 ; M );
3229 3229 $DGL 0,7
3230 3230 00574 301000 movw ax,#010H ; 16 ;[INF] 3, 1
3231 3231 00577 C1 push ax ;[INF] 1, 1
3232 3232 00578 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1
3233 3233 0057A RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
3234 3234 0057D C0 pop ax ;[INF] 1, 1
3235 3235 0057E 62 mov a,c ;[INF] 1, 1
3236 3236 0057F R9F0E00 mov !?L0112,a ; reg_shadow ;[INF] 3, 1
3237 3237 ; line 767 : if( iic_mcu_bus_status != ERR_SUCCESS )
3238 3238 $DGL 0,8
3239 3239 00582 RD50000 cmp0 !_iic_mcu_bus_status ;[INF] 3, 1
3240 3240 00585 DD04 bz $?L0113 ;[INF] 2, 4
3241 3241 ; line 768 : {
3242 3242 00587 ??bb00_ntr_pmic_comm:
3243 3243 ; line 769 : return ( ERR_FINISED );
3244 3244 $DGL 0,10
3245 3245 00587 F7 clrw bc ;[INF] 1, 1
3246 3246 00588 RED1F06 br !?L0111 ;[INF] 3, 3
3247 3247 0058B ??eb00_ntr_pmic_comm:
3248 3248 ; line 770 : }
3249 3249 0058B ?L0113:
3250 3250 ; line 771 :
3251 3251 ; line 772 : DI( );
3252 3252 $DGL 0,13
3253 3253 0058B 717BFA di ;[INF] 3, 4
3254 3254 ; line 773 :
3255 3255 ; line 774 : // <20>o<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>C<EFBFBD>g <20><> ////////////////////////////////////
3256 3256 ; line 775 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_U ) !=
3257 3257 ; 0 )
3258 3258 $DGL 0,16
3259 3259 0058E 66 mov a,l ;[INF] 1, 1
3260 3260 0058F R7F0E00 xor a,!?L0112 ; reg_shadow ;[INF] 3, 1
3261 3261 00592 5C08 and a,#08H ; 8 ;[INF] 2, 1
3262 3262 00594 D1 cmp0 a ;[INF] 1, 1
3263 3263 00595 DD1E bz $?L0118 ;[INF] 2, 4
3264 3264 ; line 776 : {
3265 3265 00597 ??bb01_ntr_pmic_comm:
3266 3266 ; line 777 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_U ) == 0 )
3267 3267 ; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
3268 3268 $DGL 0,18
3269 3269 00597 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3270 3270 0059A 5C08 and a,#08H ; 8 ;[INF] 2, 1
3271 3271 0059C D1 cmp0 a ;[INF] 1, 1
3272 3272 0059D DF0C bnz $?L0117 ;[INF] 2, 4
3273 3273 ; line 778 : {
3274 3274 0059F ??bb02_ntr_pmic_comm:
3275 3275 ; line 779 : // irq_work = REG_BIT_TWL_BL_U_OFF;
3276 3276 ; line 780 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_OFF );
3277 3277 $DGL 0,21
3278 3278 0059F 301000 movw ax,#010H ; 16 ;[INF] 3, 1
3279 3279 005A2 C1 push ax ;[INF] 1, 1
3280 3280 005A3 5012 mov x,#012H ; 18 ;[INF] 2, 1
3281 3281 005A5 RFD0000 call !_set_irq ;[INF] 3, 3
3282 3282 005A8 C0 pop ax ;[INF] 1, 1
3283 3283 005A9 ??eb02_ntr_pmic_comm:
3284 3284 ; line 781 : }
3285 3285 $DGL 0,22
3286 3286 005A9 EF0A br $?L0118 ;[INF] 2, 3
3287 3287 005AB ?L0117:
3288 3288 ; line 782 : else
3289 3289 ; line 783 : {
3290 3290 005AB ??bb03_ntr_pmic_comm:
3291 3291 ; line 784 : // irq_work = REG_BIT_TWL_BL_U_ON;
3292 3292 ; line 785 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_ON );
3293 3293 $DGL 0,26
3294 3294 005AB 302000 movw ax,#020H ; 32 ;[INF] 3, 1
3295 3295 005AE C1 push ax ;[INF] 1, 1
3296 3296 005AF 5012 mov x,#012H ; 18 ;[INF] 2, 1
3297 3297 005B1 RFD0000 call !_set_irq ;[INF] 3, 3
3298 3298 005B4 C0 pop ax ;[INF] 1, 1
3299 3299 005B5 ??eb03_ntr_pmic_comm:
3300 3300 ; line 786 : }
3301 3301 005B5 ?L0118:
3302 3302 005B5 ??eb01_ntr_pmic_comm:
3303 3303 ; line 787 : }
3304 3304 ; line 788 :
3305 3305 ; line 789 : // <20>o<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>C<EFBFBD>g <20><>
3306 3306 ; line 790 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_L ) !=
3307 3307 ; 0 )
3308 3308 $DGL 0,31
3309 3309 005B5 66 mov a,l ;[INF] 1, 1
3310 3310 005B6 R7F0E00 xor a,!?L0112 ; reg_shadow ;[INF] 3, 1
3311 3311 005B9 5C04 and a,#04H ; 4 ;[INF] 2, 1
3312 3312 005BB D1 cmp0 a ;[INF] 1, 1
3313 3313 005BC DD1E bz $?L0122 ;[INF] 2, 4
3314 3314 ; line 791 : {
3315 3315 005BE ??bb04_ntr_pmic_comm:
3316 3316 ; line 792 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_L ) == 0 )
3317 3317 ; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
3318 3318 $DGL 0,33
3319 3319 005BE R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3320 3320 005C1 5C04 and a,#04H ; 4 ;[INF] 2, 1
3321 3321 005C3 D1 cmp0 a ;[INF] 1, 1
3322 3322 005C4 DF0C bnz $?L0121 ;[INF] 2, 4
3323 3323 ; line 793 : {
3324 3324 005C6 ??bb05_ntr_pmic_comm:
3325 3325 ; line 794 : // irq_work = REG_BIT_TWL_BL_L_OFF;
3326 3326 ; line 795 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_OFF );
3327 3327 $DGL 0,36
3328 3328 005C6 300400 movw ax,#04H ; 4 ;[INF] 3, 1
3329 3329 005C9 C1 push ax ;[INF] 1, 1
3330 3330 005CA 5012 mov x,#012H ; 18 ;[INF] 2, 1
3331 3331 005CC RFD0000 call !_set_irq ;[INF] 3, 3
3332 3332 005CF C0 pop ax ;[INF] 1, 1
3333 3333 005D0 ??eb05_ntr_pmic_comm:
3334 3334 ; line 796 : }
3335 3335 $DGL 0,37
3336 3336 005D0 EF0A br $?L0122 ;[INF] 2, 3
3337 3337 005D2 ?L0121:
3338 3338 ; line 797 : else
3339 3339 ; line 798 : {
3340 3340 005D2 ??bb06_ntr_pmic_comm:
3341 3341 ; line 799 : // irq_work = REG_BIT_TWL_BL_L_ON;
3342 3342 ; line 800 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_ON );
3343 3343 $DGL 0,41
3344 3344 005D2 300800 movw ax,#08H ; 8 ;[INF] 3, 1
3345 3345 005D5 C1 push ax ;[INF] 1, 1
3346 3346 005D6 5012 mov x,#012H ; 18 ;[INF] 2, 1
3347 3347 005D8 RFD0000 call !_set_irq ;[INF] 3, 3
3348 3348 005DB C0 pop ax ;[INF] 1, 1
3349 3349 005DC ??eb06_ntr_pmic_comm:
3350 3350 ; line 801 : }
3351 3351 005DC ?L0122:
3352 3352 005DC ??eb04_ntr_pmic_comm:
3353 3353 ; line 802 : }
3354 3354 ; line 803 :
3355 3355 ; line 804 : #if 0
3356 3356 ; line 805 : irq_work &= ~VREG_C_IRQ_MASK2;
3357 3357 ; line 806 : // set_irq <20><><EFBFBD><EFBFBD><EFBFBD>i
3358 3358 ; line 807 : if( irq_work != 0 )
3359 3359 ; line 808 : {
3360 3360 ; line 809 : u8 tot;
3361 3361 ; line 810 :
3362 3362 ; line 811 : DI();
3363 3363 ; line 812 : vreg_ctr[ VREG_C_IRQ2 ] |= irq_work;
3364 3364 ; line 813 : EI();
3365 3365 ; line 814 : IRQ0_neg; // <20><><EFBFBD>u<EFBFBD>グ<EFBFBD>ăp<C483><70><EFBFBD>X<EFBFBD>𑗂蒼<F0919782><E892BC>
3366 3366 ; line 815 : tot = 0;
3367 3367 ; line 816 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.D<>Ȃ̂ł<CC82><C582><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
3368 3368 ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD><CC82>҂<EFBFBD> <20><> IRQ_mcu <20><>L<EFBFBD>ɔ<EFBFBD><C994><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>ƍ<EFBFBD><C68D><EFBFBD>(<28><><EFBFBD>•s<C295><73>)
3369 3369 ; line 817 : IRQ0_ast;
3370 3370 ; line 818 : }
3371 3371 ; line 819 : #endif
3372 3372 ; line 820 :
3373 3373 ; line 821 : #if 0
3374 3374 ; line 822 : // <20>o<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>C<EFBFBD>g<EFBFBD>ݒ<EFBFBD>
3375 3375 ; line 823 : // <20><><EFBFBD><EFBFBD><EFBFBD>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD>
3376 3376 ; line 824 : /// <20><><EFBFBD>̂Ƃ<CC82><C682>낳<EFBFBD><EB82B3><EFBFBD>ɍׂ<C98D><D782><EFBFBD><EFBFBD>͕<EFBFBD><CD95><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD>ǁc
3377 3377 ; line 825 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_BL_U | REG_BIT_TWL_REQ_
3378 3378 ; BL_U ) ) == 0 )
3379 3379 ; line 826 : {
3380 3380 ; line 827 : vreg_ctr[ VREG_C_COMMAND2 ] = ( REG_BIT_CMD_BL_U_OFF | R
3381 3381 ; EG_BIT_CMD_BL_U_OFF );
3382 3382 ; line 828 : renge_task_immed_add( tski_PM_BL_set );
3383 3383 ; line 829 : }
3384 3384 ; line 830 : #endif
3385 3385 ; line 831 :
3386 3386 ; line 832 : // off<66><66><EFBFBD>N<EFBFBD>G<EFBFBD>X<EFBFBD>g //////////////////////////////////////
3387 3387 ; line 833 : if( ( reg_shadow & REG_BIT_TWL_REQ_OFF_REQ ) != 0 )
3388 3388 $DGL 0,74
3389 3389 005DC R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3390 3390 005DF 5C40 and a,#040H ; 64 ;[INF] 2, 1
3391 3391 005E1 D1 cmp0 a ;[INF] 1, 1
3392 3392 005E2 DD09 bz $?L0123 ;[INF] 2, 4
3393 3393 ; line 834 : {
3394 3394 005E4 ??bb07_ntr_pmic_comm:
3395 3395 ; line 835 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );
3396 3396 $DGL 0,76
3397 3397 005E4 E6 onew ax ;[INF] 1, 1
3398 3398 005E5 A1 incw ax ;[INF] 1, 1
3399 3399 005E6 C1 push ax ;[INF] 1, 1
3400 3400 005E7 5012 mov x,#012H ; 18 ;[INF] 2, 1
3401 3401 005E9 RFD0000 call !_set_irq ;[INF] 3, 3
3402 3402 005EC C0 pop ax ;[INF] 1, 1
3403 3403 005ED ??eb07_ntr_pmic_comm:
3404 3404 ; line 836 : }
3405 3405 005ED ?L0123:
3406 3406 ; line 837 :
3407 3407 ; line 838 : // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD>N<EFBFBD>G<EFBFBD>X<EFBFBD>g /////////////////////////////////
3408 3408 ; line 839 : if( ( reg_shadow & REG_BIT_TWL_REQ_RST_REQ ) != 0 )
3409 3409 $DGL 0,80
3410 3410 005ED R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3411 3411 005F0 5C01 and a,#01H ; 1 ;[INF] 2, 1
3412 3412 005F2 D1 cmp0 a ;[INF] 1, 1
3413 3413 005F3 DD08 bz $?L0125 ;[INF] 2, 4
3414 3414 ; line 840 : {
3415 3415 005F5 ??bb08_ntr_pmic_comm:
3416 3416 ; line 841 : // CODEC<45>o<EFBFBD>O<EFBFBD><4F><EFBFBD><EFBFBD>
3417 3417 ; line 842 : // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD>P<EFBFBD>i<EFBFBD>łȂ<C582><C882><EFBFBD><EFBFBD><EFBFBD><EFBFBD>疳<EFBFBD><E796B3>
3418 3418 ; line 843 : // codec <20>C<EFBFBD><43><EFBFBD>ρ<EFBFBD>
3419 3419 ; line 844 : // if( ( reg1_old ^ reg_shadow ) == REG_BIT_TWL_REQ_RST_R
3420 3420 ; EQ )
3421 3421 ; line 845 : {
3422 3422 005F5 ??bb09_ntr_pmic_comm:
3423 3423 ; line 846 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );
3424 3424 $DGL 0,87
3425 3425 005F5 E6 onew ax ;[INF] 1, 1
3426 3426 005F6 C1 push ax ;[INF] 1, 1
3427 3427 005F7 5012 mov x,#012H ; 18 ;[INF] 2, 1
3428 3428 005F9 RFD0000 call !_set_irq ;[INF] 3, 3
3429 3429 005FC C0 pop ax ;[INF] 1, 1
3430 3430 005FD ??eb09_ntr_pmic_comm:
3431 3431 ; line 847 : }
3432 3432 005FD ??eb08_ntr_pmic_comm:
3433 3433 ; line 848 : }
3434 3434 005FD ?L0125:
3435 3435 ; line 849 :
3436 3436 ; line 850 : // <20>o<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>}<7D>X<EFBFBD>N<EFBFBD><4E><EFBFBD>ď<EFBFBD><C48F><EFBFBD><EFBFBD>߂<EFBFBD>
3437 3437 ; line 851 : EI( );
3438 3438 $DGL 0,92
3439 3439 005FD 717AFA ei ;[INF] 3, 4
3440 3440 ; line 852 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R
3441 3441 ; EQ_RST_REQ )) != 0 )
3442 3442 $DGL 0,93
3443 3443 00600 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1
3444 3444 00603 5C41 and a,#041H ; 65 ;[INF] 2, 1
3445 3445 00605 D1 cmp0 a ;[INF] 1, 1
3446 3446 00606 DD16 bz $?L0127 ;[INF] 2, 4
3447 3447 ; line 853 : {
3448 3448 00608 ??bb0A_ntr_pmic_comm:
3449 3449 ; line 854 : reg_shadow &= ~( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R
3450 3450 ; EQ_RST_REQ );
3451 3451 $DGL 0,95
3452 3452 00608 R340E00 movw de,#loww (?L0112) ; reg_shadow ;[INF] 3, 1
3453 3453 0060B 89 mov a,[de] ;[INF] 1, 1
3454 3454 0060C 5CBE and a,#0BEH ; 190 ;[INF] 2, 1
3455 3455 0060E 99 mov [de],a ;[INF] 1, 1
3456 3456 ; line 855 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_PM, reg_s
3457 3457 ; hadow );
3458 3458 $DGL 0,96
3459 3459 0060F RD90E00 mov x,!?L0112 ; reg_shadow ;[INF] 3, 1
3460 3460 00612 F1 clrb a ;[INF] 1, 1
3461 3461 00613 C1 push ax ;[INF] 1, 1
3462 3462 00614 5010 mov x,#010H ; 16 ;[INF] 2, 1
3463 3463 00616 C1 push ax ;[INF] 1, 1
3464 3464 00617 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1
3465 3465 00619 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
3466 3466 0061C 1004 addw sp,#04H ; 4 ;[INF] 2, 1
3467 3467 0061E ??eb0A_ntr_pmic_comm:
3468 3468 ; line 856 : }
3469 3469 0061E ?L0127:
3470 3470 ; line 857 : return ( ERR_FINISED );
3471 3471 $DGL 0,98
3472 3472 0061E F7 clrw bc ;[INF] 1, 1
3473 3473 ; line 858 : }
3474 3474 0061F ?L0111:
3475 3475 $DGL 0,99
3476 3476 0061F ??ef_ntr_pmic_comm:
3477 3477 0061F C6 pop hl ;[INF] 1, 1
3478 3478 00620 D7 ret ;[INF] 1, 6
3479 3479 00621 ??ee_ntr_pmic_comm:
3480 3480 ; line 859 :
3481 3481 ; line 860 :
3482 3482 ; line 861 :
3483 3483 ; line 862 : /**********************************************************
3484 3484 ; line 863 : <20>d<EFBFBD>r<EFBFBD>c<EFBFBD><63>IC<49><43><EFBFBD><EFBFBD><EFBFBD>c<EFBFBD>ʂ<EFBFBD><CA82>擾<EFBFBD><E693BE><EFBFBD>A<EFBFBD><41><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ށB
3485 3485 ; line 864 : <20>@<40>d<EFBFBD>r<EFBFBD>c<EFBFBD><63>IC<49><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>E<EFBFBD>̏<EFBFBD><CC8F>Ȃǂ̎<C782><CC8E>͂Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>c<EFBFBD><63>99%<25>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>B
3486 3486 ; line 865 : <20>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40><><EFBFBD><EFBFBD> status_1<5F>Ŋm<C58A>F<EFBFBD>”\<5C>B<EFBFBD>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƀ`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E>
3487 3487 ; <20>Ă<EFBFBD><C482>܂<EFBFBD><DC82>B
3488 3488 ; line 866 : <20>@PM_init()<29><><EFBFBD><EFBFBD><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>K<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
3489 3489 ; line 867 : **********************************************************/
3490 3490 ; line 868 : static void PM_get_batt_left(){
3491 3491 00621 _PM_get_batt_left:
3492 3492 $DGL 1,492
3493 3493 00621 C7 push hl ;[INF] 1, 1
3494 3494 00622 C1 push ax ;[INF] 1, 1
3495 3495 00623 FBF8FF movw hl,sp ;[INF] 3, 1
3496 3496 00626 ??bf_PM_get_batt_left:
3497 3497 ; line 869 : if(( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_GASGAUGE_ERR ) ==
3498 3498 ; 0 )
3499 3499 $DGL 0,2
3500 3500 00626 R8F0E00 mov a,!_vreg_ctr+14 ;[INF] 3, 1
3501 3501 00629 5C01 and a,#01H ; 1 ;[INF] 2, 1
3502 3502 0062B D1 cmp0 a ;[INF] 1, 1
3503 3503 0062C DF22 bnz $?L0131 ;[INF] 2, 4
3504 3504 ; line 870 : {
3505 3505 0062E ??bb00_PM_get_batt_left:
3506 3506 ; line 871 : // <20>d<EFBFBD>r<EFBFBD>c<EFBFBD>ʂ̎擾
3507 3507 ; line 872 : {
3508 3508 0062E ??bb01_PM_get_batt_left:
3509 3509 ; line 873 : u8 temp[2];
3510 3510 ; line 874 :
3511 3511 ; line 875 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC, 2,
3512 3512 ; temp );
3513 3513 $DGL 0,8
3514 3514 0062E 17 movw ax,hl ;[INF] 1, 1
3515 3515 0062F C1 push ax ;[INF] 1, 1
3516 3516 00630 E6 onew ax ;[INF] 1, 1
3517 3517 00631 A1 incw ax ;[INF] 1, 1
3518 3518 00632 C1 push ax ;[INF] 1, 1
3519 3519 00633 A1 incw ax ;[INF] 1, 1
3520 3520 00634 A1 incw ax ;[INF] 1, 1
3521 3521 00635 C1 push ax ;[INF] 1, 1
3522 3522 00636 506C mov x,#06CH ; 108 ;[INF] 2, 1
3523 3523 00638 RFD0000 call !_iic_mcu_read ;[INF] 3, 3
3524 3524 0063B 1006 addw sp,#06H ; 6 ;[INF] 2, 1
3525 3525 ; line 876 :
3526 3526 ; line 877 : vreg_ctr[ VREG_C_BT_REMAIN ] = temp[0];
3527 3527 $DGL 0,10
3528 3528 0063D 8B mov a,[hl] ; temp ;[INF] 1, 1
3529 3529 0063E R9F0B00 mov !_vreg_ctr+11,a ;[INF] 3, 1
3530 3530 ; line 878 : vreg_ctr[ VREG_C_BT_REMAIN_FINE ] = temp[1];
3531 3531 $DGL 0,11
3532 3532 00641 8C01 mov a,[hl+1] ; temp ;[INF] 2, 1
3533 3533 00643 R9F0C00 mov !_vreg_ctr+12,a ;[INF] 3, 1
3534 3534 00646 ??eb01_PM_get_batt_left:
3535 3535 ; line 879 : // todo 臒l<E88792>𒴂<EFBFBD><F092B482><EFBFBD><EFBFBD>犄<EFBFBD>荞<EFBFBD><E88D9E>
3536 3536 ; line 880 : }
3537 3537 ; line 881 :
3538 3538 ; line 882 : vreg_ctr[ VREG_C_BT_VOLTAGE ] = iic_mcu_read_a_byte( IIC
3539 3539 ; _SLA_BT_GAUGE, BT_GAUGE_REG_VCELL );
3540 3540 $DGL 0,15
3541 3541 00646 E6 onew ax ;[INF] 1, 1
3542 3542 00647 A1 incw ax ;[INF] 1, 1
3543 3543 00648 RFD1000 call !bs_F0151 ;[INF] 3, 3
3544 3544 0064B R9F0D00 mov !_vreg_ctr+13,a ;[INF] 3, 1
3545 3545 0064E ??eb00_PM_get_batt_left:
3546 3546 ; line 883 : }
3547 3547 $DGL 0,16
3548 3548 0064E EF04 br $?L0132 ;[INF] 2, 3
3549 3549 00650 ?L0131:
3550 3550 ; line 884 : else
3551 3551 ; line 885 : {
3552 3552 00650 ??bb02_PM_get_batt_left:
3553 3553 ; line 886 : vreg_ctr[ VREG_C_BT_REMAIN ] = 99;
3554 3554 $DGL 0,19
3555 3555 00650 RCF0B0063 mov !_vreg_ctr+11,#063H ; 99 ;[INF] 4, 1
3556 3556 00654 ??eb02_PM_get_batt_left:
3557 3557 ; line 887 : }
3558 3558 00654 ?L0132:
3559 3559 ; line 888 :
3560 3560 ; line 889 : // PMIC-NTR<54>ɓd<C993>r<EFBFBD>c<EFBFBD>ʂ<EFBFBD><CA82><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD>
3561 3561 ; line 890 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_BT,
3562 3562 ; line 891 : ( vreg_ctr[ VREG_C_BT_REMAIN ] < 5 )?
3563 3563 ; 1 : 0 ); // 1<>œd<C593>r<EFBFBD>؂<EFBFBD>
3564 3564 $DGL 0,24
3565 3565 00654 R400B0005 cmp !_vreg_ctr+11,#05H ; 5 ;[INF] 4, 1
3566 3566 00658 DE03 bnc $?L0133 ;[INF] 2, 4
3567 3567 0065A E6 onew ax ;[INF] 1, 1
3568 3568 0065B EF01 br $?L0134 ;[INF] 2, 3
3569 3569 0065D ?L0133:
3570 3570 0065D F6 clrw ax ;[INF] 1, 1
3571 3571 0065E ?L0134:
3572 3572 0065E F1 clrb a ;[INF] 1, 1
3573 3573 0065F C1 push ax ;[INF] 1, 1
3574 3574 00660 5012 mov x,#012H ; 18 ;[INF] 2, 1
3575 3575 00662 C1 push ax ;[INF] 1, 1
3576 3576 00663 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1
3577 3577 00665 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
3578 3578 00668 1004 addw sp,#04H ; 4 ;[INF] 2, 1
3579 3579 ; line 892 :
3580 3580 ; line 893 : }
3581 3581 $DGL 0,26
3582 3582 0066A ??ef_PM_get_batt_left:
3583 3583 0066A C0 pop ax ;[INF] 1, 1
3584 3584 0066B C6 pop hl ;[INF] 1, 1
3585 3585 0066C D7 ret ;[INF] 1, 6
3586 3586 0066D ??ee_PM_get_batt_left:
3587 3587 ; line 894 :
3588 3588 ; line 895 :
3589 3589 ; line 896 :
3590 3590 ; line 897 :
3591 3591 ; line 898 :
3592 3592 ; line 899 : /**********************************************************
3593 3593 ; line 900 : command2 <20>t<EFBFBD><74><EFBFBD>n
3594 3594 ; line 901 : <20>@ <20><><EFBFBD>b<EFBFBD>p<EFBFBD>[<5B>I<EFBFBD>ȕ<EFBFBD><C895>BERR_SUCCESS<53><53><EFBFBD><EFBFBD><EFBFBD>Ԃ<EFBFBD><D482>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD>c
3595 3595 ; line 902 : **********************************************************/
3596 3596 ; line 903 : task_status_immed tski_PM_LCD_on()
3597 3597 ; line 904 : {
3598 3598 0066D _tski_PM_LCD_on:
3599 3599 $DGL 1,512
3600 3600 0066D ??bf_tski_PM_LCD_on:
3601 3601 ; line 905 : PM_LCD_on();
3602 3602 $DGL 0,2
3603 3603 0066D RFDA702 call !_PM_LCD_on ;[INF] 3, 3
3604 3604 ; line 906 : return( ERR_SUCCESS );
3605 3605 $DGL 0,3
3606 3606 00670 F7 clrw bc ;[INF] 1, 1
3607 3607 ; line 907 : }
3608 3608 $DGL 0,4
3609 3609 00671 ??ef_tski_PM_LCD_on:
3610 3610 00671 D7 ret ;[INF] 1, 6
3611 3611 00672 ??ee_tski_PM_LCD_on:
3612 3612 ; line 908 :
3613 3613 ; line 909 : task_status_immed tski_PM_LCD_off()
3614 3614 ; line 910 : {
3615 3615 00672 _tski_PM_LCD_off:
3616 3616 $DGL 1,518
3617 3617 00672 ??bf_tski_PM_LCD_off:
3618 3618 ; line 911 : PM_LCD_off();
3619 3619 $DGL 0,2
3620 3620 00672 RFDE202 call !_PM_LCD_off ;[INF] 3, 3
3621 3621 ; line 912 : return( ERR_SUCCESS );
3622 3622 $DGL 0,3
3623 3623 00675 F7 clrw bc ;[INF] 1, 1
3624 3624 ; line 913 : }
3625 3625 $DGL 0,4
3626 3626 00676 ??ef_tski_PM_LCD_off:
3627 3627 00676 D7 ret ;[INF] 1, 6
3628 3628 00677 ??ee_tski_PM_LCD_off:
3629 3629 ; line 914 :
3630 3630 ; line 915 : task_status_immed tski_PM_BL_set()
3631 3631 ; line 916 : {
3632 3632 00677 _tski_PM_BL_set:
3633 3633 $DGL 1,524
3634 3634 00677 C7 push hl ;[INF] 1, 1
3635 3635 00678 ??bf_tski_PM_BL_set:
3636 3636 ; line 917 : u8 cmd_BL; // <20><>volatile<6C>Ƃ<EFBFBD><C682>t<EFBFBD><74><EFBFBD>Ȃ<EFBFBD><C882>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD>
3637 3637 ; <20>v<EFBFBD>݂<EFBFBD><DD82><EFBFBD>
3638 3638 ; line 918 :
3639 3639 ; line 919 : do
3640 3640 00678 ?L0141:
3641 3641 ; line 920 : {
3642 3642 00678 ??bb00_tski_PM_BL_set:
3643 3643 ; line 921 : cmd_BL = vreg_ctr[VREG_C_COMMAND2];
3644 3644 $DGL 0,6
3645 3645 00678 R8F2200 mov a,!_vreg_ctr+34 ;[INF] 3, 1
3646 3646 0067B 76 mov l,a ;[INF] 1, 1
3647 3647 ; line 922 : PM_BL_set( cmd_BL ); // <20>}<7D>X<EFBFBD>N<EFBFBD>ς<EFBFBD>
3648 3648 $DGL 0,7
3649 3649 0067C 17 movw ax,hl ;[INF] 1, 1
3650 3650 0067D F1 clrb a ;[INF] 1, 1
3651 3651 0067E RFD4203 call !_PM_BL_set ;[INF] 3, 3
3652 3652 00681 ??eb00_tski_PM_BL_set:
3653 3653 ; line 923 : }
3654 3654 ; line 924 : while( cmd_BL != vreg_ctr[VREG_C_COMMAND2] );
3655 3655 $DGL 0,9
3656 3656 00681 66 mov a,l ;[INF] 1, 1
3657 3657 00682 R4F2200 cmp a,!_vreg_ctr+34 ;[INF] 3, 1
3658 3658 00685 DFF1 bnz $?L0141 ;[INF] 2, 4
3659 3659 ; line 925 : vreg_ctr[VREG_C_COMMAND2] = 0;
3660 3660 $DGL 0,10
3661 3661 00687 RF52200 clrb !_vreg_ctr+34 ;[INF] 3, 1
3662 3662 ; line 926 :
3663 3663 ; line 927 : return( ERR_SUCCESS );
3664 3664 $DGL 0,12
3665 3665 0068A F7 clrw bc ;[INF] 1, 1
3666 3666 ; line 928 : }
3667 3667 $DGL 0,13
3668 3668 0068B ??ef_tski_PM_BL_set:
3669 3669 0068B C6 pop hl ;[INF] 1, 1
3670 3670 0068C D7 ret ;[INF] 1, 6
3671 3671 0068D ??ee_tski_PM_BL_set:
3672 3672
3673 3673 ----- @@CODEL CSEG
3674 3674 END
3675 3675
3676 3676
3677 3677 ; *** Code Information ***
3678 3678 ;
3679 3679 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c
3680 3680 ;
3681 3681 ; $FUNC PM_init(46)
3682 3682 ; void=(void)
3683 3683 ; CODE SIZE= 335 bytes, CLOCK_SIZE= 294 clocks, STACK_SIZE= 20 bytes
3684 3684 ;
3685 3685 ; $CALL wait_ms(58)
3686 3686 ; void=(int:ax)
3687 3687 ;
3688 3688 ; $CALL iic_mcu_write(62)
3689 3689 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3690 3690 ;
3691 3691 ; $CALL iic_mcu_write(66)
3692 3692 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3693 3693 ;
3694 3694 ; $CALL iic_mcu_write(75)
3695 3695 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3696 3696 ;
3697 3697 ; $CALL iic_mcu_read(78)
3698 3698 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3699 3699 ;
3700 3700 ; $CALL iic_mcu_write(82)
3701 3701 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3702 3702 ;
3703 3703 ; $CALL iic_mcu_write(86)
3704 3704 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3705 3705 ;
3706 3706 ; $CALL get_adc(90)
3707 3707 ; bc=(int:ax)
3708 3708 ;
3709 3709 ; $CALL iic_mcu_write(104)
3710 3710 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3711 3711 ;
3712 3712 ; $CALL wait_ms(112)
3713 3713 ; void=(int:ax)
3714 3714 ;
3715 3715 ; $CALL iic_mcu_write(116)
3716 3716 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3717 3717 ;
3718 3718 ; $CALL wait_ms(119)
3719 3719 ; void=(int:ax)
3720 3720 ;
3721 3721 ; $CALL iic_mcu_read_a_byte(122)
3722 3722 ; bc=(int:ax, int:[sp+4])
3723 3723 ;
3724 3724 ; $CALL iic_mcu_write(131)
3725 3725 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3726 3726 ;
3727 3727 ; $CALL iic_mcu_write(135)
3728 3728 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3729 3729 ;
3730 3730 ; $CALL get_adc(142)
3731 3731 ; bc=(int:ax)
3732 3732 ;
3733 3733 ; $CALL renge_task_immed_add(143)
3734 3734 ; bc=(pointer:ax)
3735 3735 ;
3736 3736 ; $FUNC PM_bt_temp_update(163)
3737 3737 ; bc=(void)
3738 3738 ; CODE SIZE= 217 bytes, CLOCK_SIZE= 196 clocks, STACK_SIZE= 14 bytes
3739 3739 ;
3740 3740 ; $CALL iic_mcu_write(201)
3741 3741 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3742 3742 ;
3743 3743 ; $FUNC PM_LCD_on(227)
3744 3744 ; bc=(void)
3745 3745 ; CODE SIZE= 59 bytes, CLOCK_SIZE= 114 clocks, STACK_SIZE= 14 bytes
3746 3746 ;
3747 3747 ; $CALL iic_mcu_write_a_byte(230)
3748 3748 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3749 3749 ;
3750 3750 ; $CALL wait_ms(232)
3751 3751 ; void=(int:ax)
3752 3752 ;
3753 3753 ; $CALL iic_mcu_write_a_byte(234)
3754 3754 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3755 3755 ;
3756 3756 ; $CALL wait_ms(236)
3757 3757 ; void=(int:ax)
3758 3758 ;
3759 3759 ; $CALL iic_mcu_write_a_byte(238)
3760 3760 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3761 3761 ;
3762 3762 ; $CALL wait_ms(240)
3763 3763 ; void=(int:ax)
3764 3764 ;
3765 3765 ; $CALL iic_mcu_read_a_byte(245)
3766 3766 ; bc=(int:ax, int:[sp+4])
3767 3767 ;
3768 3768 ; $CALL set_irq(251)
3769 3769 ; void=(int:ax, int:[sp+4])
3770 3770 ;
3771 3771 ; $FUNC PM_LCD_off(265)
3772 3772 ; void=(void)
3773 3773 ; CODE SIZE= 96 bytes, CLOCK_SIZE= 139 clocks, STACK_SIZE= 14 bytes
3774 3774 ;
3775 3775 ; $CALL iic_mcu_read_a_byte(272)
3776 3776 ; bc=(int:ax, int:[sp+4])
3777 3777 ;
3778 3778 ; $CALL PM_BL_set(277)
3779 3779 ; bc=(int:ax)
3780 3780 ;
3781 3781 ; $CALL iic_mcu_write_a_byte(296)
3782 3782 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3783 3783 ;
3784 3784 ; $CALL wait_ms(297)
3785 3785 ; void=(int:ax)
3786 3786 ;
3787 3787 ; $CALL iic_mcu_write_a_byte(299)
3788 3788 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3789 3789 ;
3790 3790 ; $CALL set_irq(303)
3791 3791 ; void=(int:ax, int:[sp+4])
3792 3792 ;
3793 3793 ; $FUNC PM_BL_set(314)
3794 3794 ; bc=(unsigned char dat:x)
3795 3795 ; CODE SIZE= 202 bytes, CLOCK_SIZE= 176 clocks, STACK_SIZE= 18 bytes
3796 3796 ;
3797 3797 ; $CALL iic_mcu_read_a_byte(323)
3798 3798 ; bc=(int:ax, int:[sp+4])
3799 3799 ;
3800 3800 ; $CALL wait_ms(381)
3801 3801 ; void=(int:ax)
3802 3802 ;
3803 3803 ; $CALL iic_mcu_write_a_byte(383)
3804 3804 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3805 3805 ;
3806 3806 ; $FUNC PM_LCD_vcom_set(395)
3807 3807 ; bc=(void)
3808 3808 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 41 clocks, STACK_SIZE= 10 bytes
3809 3809 ;
3810 3810 ; $CALL iic_mcu_write_a_byte(398)
3811 3811 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3812 3812 ;
3813 3813 ; $CALL iic_mcu_write_a_byte(399)
3814 3814 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3815 3815 ;
3816 3816 ; $FUNC tski_vcom_set(450)
3817 3817 ; bc=(void)
3818 3818 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes
3819 3819 ;
3820 3820 ; $CALL PM_LCD_vcom_set(451)
3821 3821 ; bc=(void)
3822 3822 ;
3823 3823 ; $FUNC PM_sys_pow_on(466)
3824 3824 ; bc=(void)
3825 3825 ; CODE SIZE= 115 bytes, CLOCK_SIZE= 182 clocks, STACK_SIZE= 14 bytes
3826 3826 ;
3827 3827 ; $CALL get_adc(475)
3828 3828 ; bc=(int:ax)
3829 3829 ;
3830 3830 ; $CALL PM_bt_temp_update(477)
3831 3831 ; bc=(void)
3832 3832 ;
3833 3833 ; $CALL PM_get_batt_left(480)
3834 3834 ; void=(void)
3835 3835 ;
3836 3836 ; $CALL iic_mcu_write_a_byte(492)
3837 3837 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3838 3838 ;
3839 3839 ; $CALL wait_ms(494)
3840 3840 ; void=(int:ax)
3841 3841 ;
3842 3842 ; $CALL wait_ms(499)
3843 3843 ; void=(int:ax)
3844 3844 ;
3845 3845 ; $CALL iic_mcu_write_a_byte(501)
3846 3846 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3847 3847 ;
3848 3848 ; $CALL wait_ms(502)
3849 3849 ; void=(int:ax)
3850 3850 ;
3851 3851 ; $CALL iic_mcu_write_a_byte(504)
3852 3852 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3853 3853 ;
3854 3854 ; $CALL wait_ms(506)
3855 3855 ; void=(int:ax)
3856 3856 ;
3857 3857 ; $CALL iic_mcu_write_a_byte(508)
3858 3858 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3859 3859 ;
3860 3860 ; $CALL iic_mcu_read_a_byte(512)
3861 3861 ; bc=(int:ax, int:[sp+4])
3862 3862 ;
3863 3863 ; $CALL iic_mcu_write_a_byte(517)
3864 3864 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3865 3865 ;
3866 3866 ; $FUNC PM_sys_pow_off(583)
3867 3867 ; bc=(void)
3868 3868 ; CODE SIZE= 28 bytes, CLOCK_SIZE= 62 clocks, STACK_SIZE= 12 bytes
3869 3869 ;
3870 3870 ; $CALL iic_mcu_write_a_byte(588)
3871 3871 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3872 3872 ;
3873 3873 ; $CALL iic_mcu_write_a_byte(592)
3874 3874 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3875 3875 ;
3876 3876 ; $CALL iic_mcu_write_a_byte(594)
3877 3877 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3878 3878 ;
3879 3879 ; $FUNC tsk_batt(637)
3880 3880 ; void=(void)
3881 3881 ; CODE SIZE= 168 bytes, CLOCK_SIZE= 133 clocks, STACK_SIZE= 6 bytes
3882 3882 ;
3883 3883 ; $CALL set_irq(659)
3884 3884 ; void=(int:ax, int:[sp+4])
3885 3885 ;
3886 3886 ; $CALL set_irq(664)
3887 3887 ; void=(int:ax, int:[sp+4])
3888 3888 ;
3889 3889 ; $CALL PM_get_batt_left(708)
3890 3890 ; void=(void)
3891 3891 ;
3892 3892 ; $FUNC intp4_extdc(724)
3893 3893 ; void=(void)
3894 3894 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
3895 3895 ;
3896 3896 ; $FUNC intp5_shell(735)
3897 3897 ; void=(void)
3898 3898 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
3899 3899 ;
3900 3900 ; $FUNC intp6_PM_irq(744)
3901 3901 ; void=(void)
3902 3902 ; CODE SIZE= 59 bytes, CLOCK_SIZE= 55 clocks, STACK_SIZE= 26 bytes
3903 3903 ;
3904 3904 ; $CALL renge_task_immed_add(748)
3905 3905 ; bc=(pointer:ax)
3906 3906 ;
3907 3907 ; $FUNC ntr_pmic_comm(760)
3908 3908 ; bc=(void)
3909 3909 ; CODE SIZE= 180 bytes, CLOCK_SIZE= 152 clocks, STACK_SIZE= 10 bytes
3910 3910 ;
3911 3911 ; $CALL iic_mcu_read_a_byte(766)
3912 3912 ; bc=(int:ax, int:[sp+4])
3913 3913 ;
3914 3914 ; $CALL set_irq(780)
3915 3915 ; void=(int:ax, int:[sp+4])
3916 3916 ;
3917 3917 ; $CALL set_irq(785)
3918 3918 ; void=(int:ax, int:[sp+4])
3919 3919 ;
3920 3920 ; $CALL set_irq(795)
3921 3921 ; void=(int:ax, int:[sp+4])
3922 3922 ;
3923 3923 ; $CALL set_irq(800)
3924 3924 ; void=(int:ax, int:[sp+4])
3925 3925 ;
3926 3926 ; $CALL set_irq(835)
3927 3927 ; void=(int:ax, int:[sp+4])
3928 3928 ;
3929 3929 ; $CALL set_irq(846)
3930 3930 ; void=(int:ax, int:[sp+4])
3931 3931 ;
3932 3932 ; $CALL iic_mcu_write_a_byte(855)
3933 3933 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3934 3934 ;
3935 3935 ; $FUNC PM_get_batt_left(868)
3936 3936 ; void=(void)
3937 3937 ; CODE SIZE= 76 bytes, CLOCK_SIZE= 77 clocks, STACK_SIZE= 14 bytes
3938 3938 ;
3939 3939 ; $CALL iic_mcu_read(875)
3940 3940 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
3941 3941 ;
3942 3942 ; $CALL iic_mcu_read_a_byte(882)
3943 3943 ; bc=(int:ax, int:[sp+4])
3944 3944 ;
3945 3945 ; $CALL iic_mcu_write_a_byte(891)
3946 3946 ; bc=(int:ax, int:[sp+4], int:[sp+6])
3947 3947 ;
3948 3948 ; $FUNC tski_PM_LCD_on(904)
3949 3949 ; bc=(void)
3950 3950 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes
3951 3951 ;
3952 3952 ; $CALL PM_LCD_on(905)
3953 3953 ; bc=(void)
3954 3954 ;
3955 3955 ; $FUNC tski_PM_LCD_off(910)
3956 3956 ; bc=(void)
3957 3957 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes
3958 3958 ;
3959 3959 ; $CALL PM_LCD_off(911)
3960 3960 ; void=(void)
3961 3961 ;
3962 3962 ; $FUNC tski_PM_BL_set(916)
3963 3963 ; bc=(void)
3964 3964 ; CODE SIZE= 22 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 6 bytes
3965 3965 ;
3966 3966 ; $CALL PM_BL_set(922)
3967 3967 ; bc=(int:ax)
3968 3968
3969 3969 ; Target chip : uPD79F0104
3970 3970 ; Device file : E1.00b
Segment informations:
ADRS LEN NAME
00000 00000H.1 @@BITS
00000 001F8H @@CNST
00000 00004H @@R_INIT
00000 00004H @@INIT
00000 00010H @@DATA
00000 00000H @@R_INIS
00000 00000H @@INIS
00000 00000H @@DATS
00000 00000H @@CNSTL
00000 00000H @@RLINIT
00000 00000H @@INITL
00000 00000H @@DATAL
00000 00000H @@CALT
00000 0068DH ROM_CODE
00000 0003FH @@BASE
00000 00000H @@CODEL
Target chip : uPD79F0104
Device file : E1.00b
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)

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