mirror of
https://github.com/rvtr/ctr_mcu.git
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dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
370 lines
12 KiB
NASM
370 lines
12 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_debug.c
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; In-file : task_debug.c
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; Asm-file : inter_asm\task_debug.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 05CH, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, task_debug.c
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$DGS MOD_NAM, task_debug, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _tsk_debug, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 050H, 00H, 00H
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$DGS BEG_FUN, ??bf_tsk_debug, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 010H, 02H, 04AH
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$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
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$DGS STA_SYM, _count, ?L0003, U, 0CH, 03H, 00H, 00H
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$DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H
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$DGS BEG_BLK, ??bb00_tsk_debug, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 00H
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$DGS END_BLK, ??eb00_tsk_debug, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 015H
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$DGS END_FUN, ??ef_tsk_debug, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 017H
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$DGS GLV_SYM, _tsk_debug2, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 05CH, 00H, 00H
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$DGS BEG_FUN, ??bf_tsk_debug2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 02BH, 04H, 056H
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$DGS AUT_VAR, _str, 00H, 0FFFFH, 0CH, 01H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H
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$DGS BEG_BLK, ??bb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 05H, 00H, 00H
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$DGS END_BLK, ??eb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01CH
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$DGS END_FUN, ??ef_tsk_debug2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 01EH
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$DGS GLV_SYM, _temp_debug_3, U, U, 0CH, 026H, 00H, 00H
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$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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EXTRN _system_status
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EXTRN _vreg_ctr
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EXTRN _iic_mcu_write
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PUBLIC _tsk_debug
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PUBLIC _temp_debug_3
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PUBLIC _tsk_debug2
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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DB 025H ; 37
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DB 038H ; 56
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DB 04DH ; 77
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DB 05FH ; 95
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DB 06EH ; 110
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DB 077H ; 119
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DB 07AH ; 122
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DB 077H ; 119
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DB 06EH ; 110
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DB 05FH ; 95
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DB 04DH ; 77
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DB 038H ; 56
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DB 025H ; 37
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DB 012H ; 18
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DB 04H ; 4
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DB 0FAH ; 250
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0F7H ; 247
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DB 0FBH ; 251
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DB 0FEH ; 254
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DB 00H ; 0
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 02H ; 2
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DB 01H ; 1
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DB (1)
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@@R_INIT CSEG UNIT64KP
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DB 00H ; 0
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DB (1)
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@@INIT DSEG BASEP
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?L0003: DS (1)
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DS (1)
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@@DATA DSEG BASEP
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?L0004: DS (1)
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_temp_debug_3: DS (1)
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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@@CNSTL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : #pragma SFR
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; line 2 : #pragma NOP
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; line 3 : #pragma HALT
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; line 4 : #pragma STOP
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; line 5 :
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; line 6 : #include "incs.h"
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; line 7 : #include "renge.h"
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; line 8 : #include "pm.h"
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; line 9 :
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; line 10 : #include "accero.h"
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; line 11 :
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; line 12 :
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; line 13 : /* ========================================================
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; line 14 : ======================================================== */
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; line 15 : void tsk_debug( )
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; line 16 : {
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ROM_CODE CSEG BASE
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_tsk_debug:
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$DGL 1,67
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push hl ;[INF] 1, 1
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??bf_tsk_debug:
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; line 17 : u8 temp;
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; line 18 : static u8 count = 0;
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; line 19 : static u8 task_interval;
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; line 20 :
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; line 21 : if( system_status.pwr_state == ON_TRIG ){
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$DGL 0,6
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cmp !_system_status,#02H ; 2 ;[INF] 4, 1
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??bb00_tsk_debug:
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??eb00_tsk_debug:
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; line 22 :
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; line 23 : #ifdef _MODEL_WM0_
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; line 24 : PM_CHG_TIMEOUT_DISABLE(); //
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; /WL_RST <20>ɔz<C994><7A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD>
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; line 25 : #endif
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; line 26 : #ifndef _MODEL_CTR_
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; line 27 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 ); //
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; ACR<43><52>0x80 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>[<5B>h<EFBFBD><68>
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; line 28 : #endif
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; line 29 :
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; line 30 : /*
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; line 31 : temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_
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; DO );
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; line 32 : count += 1;
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; line 33 : iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, co
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; unt );
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; line 34 : iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count );
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; line 35 : */
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; line 36 : }
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; line 37 : return;
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; line 38 : }
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$DGL 0,23
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??ef_tsk_debug:
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pop hl ;[INF] 1, 1
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ret ;[INF] 1, 6
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??ee_tsk_debug:
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; line 39 :
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; line 40 : u8 temp_debug_3;
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; line 41 :
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; line 42 : void tsk_debug2( )
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; line 43 : {
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_tsk_debug2:
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$DGL 1,80
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push hl ;[INF] 1, 1
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subw sp,#04H ;[INF] 2, 1
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movw hl,sp ;[INF] 3, 1
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??bf_tsk_debug2:
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; line 44 : u8 str[4];
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; line 45 :
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; line 46 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr
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; _state == SLEEP ) )
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$DGL 0,4
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cmp !_system_status,#03H ; 3 ;[INF] 4, 1
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bz $?L0011 ;[INF] 2, 4
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cmp !_system_status,#05H ; 5 ;[INF] 4, 1
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bnz $?L0009 ;[INF] 2, 4
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?L0011:
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; line 47 : {
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??bb00_tsk_debug2:
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; line 48 : /*
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; line 49 : str[3] = vreg_ctr[ VREG_C_FREE0 ];
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; line 50 : str[2] = vreg_ctr[ VREG_C_FREE1 ];
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; line 51 : str[1] = vreg_ctr[ VREG_C_STATUS ];
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; line 52 : str[0] = vreg_ctr[ VREG_C_RTC_SEC ];
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; line 53 : */
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; line 54 : str[3] = vreg_ctr[ VREG_C_SND_VOL ];
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$DGL 0,12
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mov a,!_vreg_ctr+9 ;[INF] 3, 1
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mov [hl+3],a ; str ;[INF] 2, 1
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; line 55 : str[2] = vreg_ctr[ VREG_C_TUNE ];
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$DGL 0,13
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mov a,!_vreg_ctr+8 ;[INF] 3, 1
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mov [hl+2],a ; str ;[INF] 2, 1
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; line 56 : str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ];
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$DGL 0,14
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mov a,!_vreg_ctr+64 ;[INF] 3, 1
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mov [hl+1],a ; str ;[INF] 2, 1
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; line 57 : str[0] = SEC;
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$DGL 0,15
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mov a,SEC ;[INF] 2, 1
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mov [hl],a ; str ;[INF] 1, 1
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; line 58 :
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; line 59 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR
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; EG_C_IRQ1 ] );
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; line 60 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura );
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; line 61 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
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; EG_C_SND_VOL ] );
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; line 62 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
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; EG_TUNE ] );
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; line 63 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR
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; EG_C_ACC_ZH ] );
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; line 64 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VR
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; EG_C_TUNE ] );
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; line 65 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR
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; EG_C_SND_VOL ] );
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; line 66 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
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; EG_C_STATUS ] );
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; line 67 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR
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; EG_C_ACC_ZH ] );
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; line 68 :
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; line 69 : iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] );
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$DGL 0,27
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movw ax,hl ;[INF] 1, 1
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push ax ;[INF] 1, 1
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movw ax,#04H ; 4 ;[INF] 3, 1
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push ax ;[INF] 1, 1
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clrw ax ;[INF] 1, 1
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push ax ;[INF] 1, 1
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mov x,#044H ; 68 ;[INF] 2, 1
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call !_iic_mcu_write ;[INF] 3, 3
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addw sp,#06H ; 6 ;[INF] 2, 1
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??eb00_tsk_debug2:
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; line 70 : }
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?L0009:
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; line 71 : return;
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; line 72 : }
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$DGL 0,30
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??ef_tsk_debug2:
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addw sp,#04H ;[INF] 2, 1
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pop hl ;[INF] 1, 1
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ret ;[INF] 1, 6
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??ee_tsk_debug2:
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@@CODEL CSEG
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@@BASE CSEG BASE
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END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c
|
||
;
|
||
; $FUNC tsk_debug(16)
|
||
; void=(void)
|
||
; CODE SIZE= 7 bytes, CLOCK_SIZE= 9 clocks, STACK_SIZE= 2 bytes
|
||
;
|
||
; $FUNC tsk_debug2(43)
|
||
; void=(void)
|
||
; CODE SIZE= 55 bytes, CLOCK_SIZE= 40 clocks, STACK_SIZE= 16 bytes
|
||
;
|
||
; $CALL iic_mcu_write(69)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|