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ctr_mcu/trunk/vreg_ctr.h
fujita_ryohei cd8c1a1590 0.10 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@106 013db118-44a6-b54f-8bf7-843cb86687b1
2010-03-30 07:41:46 +00:00

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#ifndef __vreg_ctr__
#define __vreg_ctr__
#include "config.h"
#define REG_BIT__SYS_MODE0 0b01000000
#define REG_BIT_MCU_FIRMBROKEN 0b10000000
// VREG_C_MCU_STATUS
#define REG_BIT_STATUS_WDT_RESET ( 1 << 1 )
#define REG_BIT_RTC_BLACKOUT ( 1 << 0 )
// VREG_C_STATUS,
#define REG_BIT_LCD_POW ( 1 << 7 )
#define REG_BIT_BL_U ( 1 << 6 )
#define REG_BIT_BL_L ( 1 << 5 )
#define REG_BIT_BATT_CHARGE ( 1 << 4 )
#define REG_BIT_POW_SUPPLY ( 1 << 3 )
// –¢Žg—p ( 1 << 2 )
#define REG_BIT_ST_SHELL_OPEN ( 1 << 1 )
// –¢Žg—p ( 1 << 0 )
// VREG_C_STATUS_X
// –¢Žg—p ( 1 << 6 )
// –¢Žg—p ( 1 << 5 )
// –¢Žg—p ( 1 << 4 )
// –¢Žg—p ( 1 << 3 )
// –¢Žg—p ( 1 << 2 )
#define REG_BIT_ACCERO_ERR ( 1 << 1 )
#define REG_BIT_GASGAUGE_ERR ( 1 << 0 )
// VREG_C_IRQ0
#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 7 )
#define REG_BIT_IRQ_WDT_RESET ( 1 << 7 )
#define REG_BIT_SHELL_OPEN ( 1 << 6 )
#define REG_BIT_SHELL_CLOSE ( 1 << 5 )
#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
#define REG_BIT_SW_HOME_HOLD ( 1 << 3 )
#define REG_BIT_SW_HOME_CLICK ( 1 << 2 )
#define REG_BIT_SW_POW_HOLD ( 1 << 1 )
#define REG_BIT_SW_POW_CLICK ( 1 << 0 )
// VREG_C_IRQ1
#define REG_BIT_BT_CHG_START ( 1 << 7 )
#define REG_BIT_BT_CHG_STOP ( 1 << 6 )
#define REG_BIT_BT_REMAIN ( 1 << 5 )
#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
#define REG_BIT_ACC_ACK ( 1 << 3 )
#define REG_BIT_RTC_ALARM ( 1 << 2 )
#define REG_BIT_BT_DC_CONNECT ( 1 << 1 )
#define REG_BIT_BT_DC_DISC ( 1 << 0 )
// VREG_C_IRQ2
#define REG_BIT_TWL_SNDVOL_CHANGE ( 1 << 6 )
#define REG_BIT_TWL_BL_U_ON ( 1 << 5 )
#define REG_BIT_TWL_BL_U_OFF ( 1 << 4 )
#define REG_BIT_TWL_BL_L_ON ( 1 << 3 )
#define REG_BIT_TWL_BL_L_OFF ( 1 << 2 )
#define REG_BIT_TWL_OFF_REQ ( 1 << 1 )
#define REG_BIT_TWL_RESET_REQ ( 1 << 0 )
// VREG_C_IRQ3
#define REG_BIT_BL_U_ON ( 1 << 5 )
#define REG_BIT_BL_U_OFF ( 1 << 4 )
#define REG_BIT_BL_L_ON ( 1 << 3 )
#define REG_BIT_BL_L_OFF ( 1 << 2 )
#define REG_BIT_LCD_ON ( 1 << 1 )
#define REG_BIT_LCD_OFF ( 1 << 0 )
// ‚»‚Ì‚¤‚¿‚Ç‚±‚©‚É...
//#define REG_BIT_VR_TUNE_CHANGE ( 1 << 7 )
// VREG_C_COMMAND0
//#define REG_BIT_CMD_LCD_ON ( 1 << 7 )
//#define REG_BIT_CMD_LCD_OFF ( 1 << 6 )
//#define REG_BIT_CMD_BL_ON ( 1 << 5 )
//#define REG_BIT_CMD_BL_OFF ( 1 << 4 )
#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
#define REG_BIT_RESET2_REQ ( 1 << 2 )
#define REG_BIT_RESET1_REQ ( 1 << 1 )
#define REG_BIT_OFF_REQ ( 1 << 0 )
// VREG_C_COMMAND1 (TWL‚ÉŠ„‚è<E2809A>ž‚Ý‚ð“ü‚ê‚é)
// –¢Žg—p ( 1 << 7 )
// –¢Žg—p ( 1 << 6 )
#define REG_BIT_SEND_TWL_VOL_CLICK ( 1 << 5 )
#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
#define REG_BIT_SEND_TWL_OFF_DET ( 1 << 2 )
#define REG_BIT_SEND_TWL_RESET_DET ( 1 << 1 )
#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
// VREG_C_COMMAND2 ‰t<E280B0>»ŠÖŒW
#define REG_BIT_CMD_BL_U_ON ( 1 << 5 )
#define REG_BIT_CMD_BL_U_OFF ( 1 << 4 )
#define REG_BIT_CMD_BL_L_ON ( 1 << 3 )
#define REG_BIT_CMD_BL_L_OFF ( 1 << 2 )
#define REG_BIT_CMD_LCD_ON ( 1 << 1 )
#define REG_BIT_CMD_LCD_OFF ( 1 << 0 )
#define REG_BITS_CMD_BL ( REG_BIT_CMD_BL_U_ON | REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_ON | REG_BIT_CMD_BL_L_OFF )
// <20>ªTWL‚É’Ê’m‚·‚éIRQƒŒƒWƒXƒ^
#define REG_BIT_TWL_IRQ_PWSW_DET 0x08
#define REG_BIT_TWL_IRQ_RESET 0x01
#define REG_BIT_TWL_IRQ_OFF 0x02
#define REG_BIT_TWL_IRQ_BT_LOW 0x20
#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
// CODEC<45>ã‚ÌPMIC NTR ‚Ì‘ã—<C3A3>ƒŒƒWƒXƒ^
#define REG_BIT_TWL_REQ_OFF ( 1 << 6 )
#define REG_BIT_TWL_REQ_BL_U ( 1 << 3 )
#define REG_BIT_TWL_REQ_BL_L ( 1 << 2 )
#define REG_BIT_TWL_REQ_RESET ( 1 << 0 )
/*
ƒeƒ“ƒvƒŒ
#define REG_BIT_ ( 1 << 7 )
#define REG_BIT_ ( 1 << 6 )
#define REG_BIT_ ( 1 << 5 )
#define REG_BIT_ ( 1 << 4 )
#define REG_BIT_ ( 1 << 3 )
#define REG_BIT_ ( 1 << 2 )
#define REG_BIT_ ( 1 << 1 )
#define REG_BIT_ ( 1 << 0 )
*/
/*============================================================================*/
extern u8 vreg_ctr[];
/*============================================================================*/
enum VREG_C
{ // –¢’è‹`ƒAƒhƒŒƒX‚Ö<E2809A>‘‚«<E2809A>ž‚ñ‚¾<E2809A>Û‚Ì“®<E2809C>ì‚Í•s’è
VREG_C_MCU_VER_MAJOR = 0x00,
VREG_C_MCU_VER_MINOR,
VREG_C_MCU_STATUS,
VREG_C_VCOM_T = 0x03,
VREG_C_VCOM_B,
VREG_C_DBG1 = 0x05,
VREG_C_DBG2,
VREG_C_DBG3,
VREG_C_TUNE = 0x08,
VREG_C_SND_VOL,
VREG_C_BT_TEMP,
VREG_C_BT_REMAIN,
VREG_C_BT_REMAIN_FINE,
VREG_C_BT_VOLTAGE,
VREG_C_STATUS_1 = 0x0E,
VREG_C_STATUS = 0x0F,
VREG_C_IRQ0 = 0x10,
VREG_C_IRQ1,
VREG_C_IRQ2,
VREG_C_IRQ3,
VREG_C_IRQ4,
VREG_C_IRQ_MASK0 = 0x18,
VREG_C_IRQ_MASK1,
VREG_C_IRQ_MASK2,
VREG_C_IRQ_MASK3,
VREG_C_IRQ_MASK4,
VREG_C_COMMAND0 = 0x20,
VREG_C_COMMAND1,
VREG_C_COMMAND2,
VREG_C_COMMAND3, // 'r' ‚Ń}ƒCƒRƒ“ƒŠƒZƒbƒg
VREG_C_DBG20 = 0x24,
VREG_C_DBG21,
VREG_C_DBG22,
VREG_C_DBG23,
VREG_C_LED_BRIGHT = 0x28,
VREG_C_LED_POW,
VREG_C_LED_WIFI,
VREG_C_LED_CAM,
VREG_C_LED_TUNE,
VREG_C_LED_NOTIFY,
VREG_C_RTC_SEC = 0x30,
VREG_C_RTC_MIN,
VREG_C_RTC_HOUR,
VREG_C_RTC_YOBI,
VREG_C_RTC_DAY,
VREG_C_RTC_MONTH,
VREG_C_RTC_YEAR,
VREG_C_RTC_COMP,
VREG_C_RTC_ALARM_MIN = 0x38,
VREG_C_RTC_ALARM_HOUR,
VREG_C_RTC_ALARM_DAY,
VREG_C_RTC_ALARM_MONTH,
VREG_C_RTC_ALARM_YEAR,
VREG_C_RTC_SEC_FINE_L,
VREG_C_RTC_SEC_FINE_H,
VREG_C_ACC_CONFIG = 0x40,
VREG_C_ACC_R_ADRS,
VREG_C_ACC_RESERVE,
VREG_C_ACC_W_ADRS,
VREG_C_ACC_W_BUF,
VREG_C_ACC_XL = 0x45,
VREG_C_ACC_XH,
VREG_C_ACC_YL,
VREG_C_ACC_YH,
VREG_C_ACC_ZL,
VREG_C_ACC_ZH,
VREG_C_ACC_HOSU_L = 0x4B,
VREG_C_ACC_HOSU_M,
VREG_C_ACC_HOSU_H,
VREG_C_ACC_HOSU_SETTING,
VREG_C_ACC_HOSU_HIST = 0x4F,
// VREG_C_AMBIENT_BRIGHTNESS = 0x60,
// •à<E280A2>”Œv‚Ì•]‰¿‚Ì‚½‚ß...
VREG_C_FREE_0 = 0x50,
VREG_C_FREE_1,
VREG_C_FREE_2,
VREG_C_FREE_3,
VREG_C_FREE_4,
VREG_C_FREE_5,
VREG_C_FREE_6,
VREG_C_FREE_7,
VREG_C_FREE_8,
VREG_C_FREE_9,
VREG_C_FREE_A,
VREG_C_FREE_B,
VREG_C_FREE_C,
VREG_C_FREE_D,
VREG_C_FREE_E,
VREG_C_FREE_F,
VREG_C_ENDMARK_
};
#define VREG_C_INFO 0x7F
/*
VREG_C_PM_INFO, // –¢Žg—p
VREG_C_BT_INFO, // –¢Žg—p
*/
/*============================================================================*/
void vreg_ctr_init( );
void vreg_ctr_write( u8 adrs, u8 data );
u8 vreg_ctr_read( u8 phy_adrs );
void vreg_ctr_after_read( u8 adrs );
void set_irq( u8 irqreg, u8 irq_flg );
#endif
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