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ctr_mcu/branches/sim/sim/simOnWin.h
n2232 3c14958ea8 リファクタリング 
RBR対応
ROM上固定アドレスにバージョン埋めた
HALを埋める準備

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@351 013db118-44a6-b54f-8bf7-843cb86687b1
2011-07-07 07:32:13 +00:00

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#ifndef _sim_on_win_
#define _sim_on_win_
//#pragma warning(disable:4068)
// ‘g‚Ý<E2809A>ž‚ÝŠÖ<C5A0>” ///////////////////////////////////////////
void HALT();
void STOP();
void NOP();
void EI();
void DI();
unsigned char bcdtob( unsigned char );
// pragma“I‚È•¨
#define __interrupt
#define __far
enum // sfr
{
sfr_ADCRH = 0,
sfr_ADM,
sfr_ADS,
sfr_KRM,
sfr_EGP0,
sfr_EGN0,
sfr_ISC,
sfr_TIS0,
sfr_IICA0,
sfr_IICS0,
sfr_IICF0,
sfr_SEC,
sfr_MIN,
sfr_HOUR,
sfr_WEEK,
sfr_DAY,
sfr_MONTH,
sfr_YEAR,
sfr_SUBCUD,
sfr_ALARMWM,
sfr_ALARMWH,
sfr_ALARMWW,
sfr_RTCC0,
sfr_RTCC1,
sfr_RTCC2,
sfr_CMC,
sfr_CSC,
sfr_OSTC,
sfr_OSTS,
sfr_CKC,
sfr_CKS0,
sfr_CKS1,
sfr_RESF,
sfr_LVIM,
sfr_LVIS,
sfr_WDTE,
sfr_DSA0,
sfr_DSA1,
sfr_DMC0,
sfr_DMC1,
sfr_DRC0,
sfr_DRC1,
sfr_BECTL,
sfr_PFCMD,
sfr_PFS,
sfr_FLPMC,
sfr_PMC,
sfr_TXD0_SIO00,
sfr_RXD0_SIO01,
sfr_TDR00,
sfr_TDR01,
sfr_TXD1,
sfr_SIO10,
sfr_RXD1,
sfr_TDR03,
sfr_TDR04,
sfr_TDR05,
sfr_TDR06,
sfr_TDR07,
sfr_RSUBC,
sfr_DRA0L,
sfr_DRA0H,
sfr_DRA1L,
sfr_DRA1H,
sfr_DBC0L,
sfr_DBC0H,
sfr_DBC1L,
sfr_DBC1H,
sfr_IF2L,
sfr_IF2H,
sfr_MK2L,
sfr_MK2HL,
sfr_PR02L,
sfr_PR02H,
sfr_PR12L,
sfr_PR12H,
sfr_IF0,
// sfr_IF0L,
// sfr_IF0H,
sfr_IF1,
// sfr_IF1L,
// sfr_IF1H,
sfr_MK0,
// sfr_MK0L,
// sfr_MK0H,
sfr_MK1,
// sfr_MK1L,
// sfr_MK1H,
sfr_PR00,
// sfr_PR00L,
// sfr_PR00H,
sfr_PR01,
// sfr_PR01L,
// sfr_PR01H,
sfr_PR10,
// sfr_PR10L,
// sfr_PR10H,
sfr_PR11,
// sfr_PR11L,
// sfr_PR11H,
sfr_MDAL_MULA,
sfr_MDAH_MULB,
sfr_MDBH_MULOH,
sfr_MDBL_MULOL,
sfr_P0,
sfr_PM0,
sfr_PM1,
sfr_P1,
sfr_P2,
sfr_PM2,
sfr_P3,
sfr_PM3,
sfr_P4,
sfr_PM4,
sfr_P5,
sfr_PM5,
sfr_P6,
sfr_PM6,
sfr_P7,
sfr_PM7,
sfr_P12,
sfr_PM12,
sfr_P14,
sfr_PM14,
sfr_P15,
sfr_PM15,
sfr_PM20,
sfr_P20,
_MCU_SFR_MAX_
};
enum // 2nd sfr
{
sfr_ADPC,
sfr_PU0,
sfr_PU1,
sfr_PU3,
sfr_PU4,
sfr_PU5,
sfr_PU7,
sfr_PU12,
sfr_PU14,
sfr_PIM3,
sfr_PIM7,
sfr_POM3,
sfr_POM7,
sfr_NFEN0,
sfr_NFEN1,
sfr_NFEN2,
sfr_MDCL,
sfr_MDCH,
sfr_MDUC,
sfr_PER0,
sfr_PER2,
sfr_OSMC,
sfr_BCDADJ,
sfr_SSR00L,
sfr_SSR00,
sfr_SSR01L,
sfr_SSR01,
sfr_SSR02L,
sfr_SSR02,
sfr_SSR03L,
sfr_SSR03,
sfr_SIR00L,
sfr_SIR00,
sfr_SIR01L,
sfr_SIR02L,
sfr_SIR01,
sfr_SIR02,
sfr_SIR03L,
sfr_SIR03,
sfr_SMR00,
sfr_SMR01,
sfr_SMR02,
sfr_SMR03,
sfr_SCR00,
sfr_SCR01,
sfr_SCR02,
sfr_SCR03,
sfr_SE0L,
sfr_SE0,
sfr_SS0L,
sfr_SS0,
sfr_ST0L,
sfr_ST0,
sfr_SPS0L,
sfr_SPS0,
sfr_SO0,
sfr_SOE0L,
sfr_SOE0,
sfr_SOL0L,
sfr_SOL0,
sfr_TCR00,
sfr_TCR01,
sfr_TCR02,
sfr_TCR07,
sfr_TO0L,
sfr_TOL0L,
sfr_TPS0L,
sfr_TSR07L,
sfr_TMR00,
sfr_TMR02,
sfr_TMR04,
sfr_TMR06,
sfr_TSR00L,
sfr_TOE0L,
sfr_TMR01,
sfr_TMR03,
sfr_TMR05,
sfr_TMR07,
sfr_TT0L,
sfr_TOM0L,
sfr_TE0L,
sfr_TS0L,
sfr_IICCTL01,
sfr_IICCTL11,
sfr_IICS1,
sfr_PER3,
sfr_PU20,
sfr_TCR04,
sfr_TCR06,
sfr_EGN2,
sfr_EGP2,
sfr_IICWH0,
sfr_IICWH1,
sfr_IICWL0,
sfr_IICWL1,
sfr_SVA0,
sfr_SVA1,
sfr_IICA1,
sfr_IICCTL00,
sfr_IICCTL10,
sfr_IICF1,
sfr_TCR03,
sfr_TCR05,
sfr_TSR01L,
sfr_TSR02L,
sfr_TSR03L,
sfr_TSR04L,
sfr_TSR05L,
sfr_TSR06L,
sfr_TE0,
sfr_TO0,
sfr_TOE0,
sfr_TOL0,
sfr_TOM0,
sfr_TPS0,
sfr_TS0,
sfr_TSR07,
sfr_TT0,
sfr_TSR00,
sfr_TSR01,
sfr_TSR02,
sfr_TSR03,
sfr_TSR04,
sfr_TSR05,
sfr_TSR06,
_MCU_SFR2_MAX_
};
enum
{
_P0_0 = 0, _P0_1,
_P1_0, _P1_1, _P1_2, _P1_3, _P1_4, _P1_5, _P1_6, _P1_7,
_P2_0, _P2_1, _P2_2, _P2_3, _P2_4, _P2_5, _P2_6, _P2_7,
_P3_0, _P3_1, _P3_2, _P3_3,
_P4_0, _P4_1, _P4_2, _P4_3,
_P5_0, _P5_1, _P5_2, _P5_3,
_P6_0, _P6_1,
_P7_0, _P7_1, _P7_2, _P7_3, _P7_4, _P7_5, _P7_6, _P7_7,
_P12_0, _P12_1, _P12_2, _P12_3, _P12_4,
_P14_0, _P14_1,
_P15_0, _P15_1,
_P20_0, _P20_1, _P20_2, _P20_3, _P20_4, _P20_5,
_MCU_PORTS_MAX_
};
unsigned char mcuRegPM[ _MCU_PORTS_MAX_ ];
unsigned char mcuRegP[ _MCU_PORTS_MAX_ ];
unsigned char mcuRegPU[ _MCU_PORTS_MAX_ ];
/*
typedef struct
{
unsigned _7 :1;
unsigned _6 :1;
unsigned _5 :1;
unsigned _4 :1;
unsigned _3 :1;
unsigned _2 :1;
unsigned _1 :1;
unsigned _0 :1;
}mcu_reg;
*/
/*
typedef unsigned char mcu_reg;
mcu_reg P0;
mcu_reg PM0;
mcu_reg PM1;
mcu_reg P1;
mcu_reg P2;
mcu_reg PM2;
mcu_reg PM3;
mcu_reg P3;
mcu_reg P4;
mcu_reg P5;
mcu_reg PM5;
//mcu_reg PU5;
mcu_reg P6;
mcu_reg PM6;
mcu_reg P7;
mcu_reg PM7;
mcu_reg P12;
mcu_reg PM12;
mcu_reg P14;
mcu_reg PM14;
mcu_reg P15;
mcu_reg PM15;
//mcu_reg PU20;
mcu_reg PM20;
mcu_reg P20;
*/
unsigned short mcuSfr[ _MCU_SFR_MAX_ ];
unsigned short mcuSfr2[ _MCU_SFR2_MAX_ ];
// sfr
#define ADCRH mcuSfr[ sfr_ADCRH ]
#define ADM mcuSfr[ sfr_ADM ]
#define ADS mcuSfr[ sfr_ADS ]
#define KRM mcuSfr[ sfr_KRM ]
#define EGP0 mcuSfr[ sfr_EGP0 ]
#define EGN0 mcuSfr[ sfr_EGN0 ]
#define ISC mcuSfr[ sfr_ISC ]
#define TIS0 mcuSfr[ sfr_TIS0 ]
#define IICA0 mcuSfr[ sfr_IICA0 ]
#define IICS0 mcuSfr[ sfr_IICS0 ]
#define IICF0 mcuSfr[ sfr_IICF0 ]
#define SEC mcuSfr[ sfr_SEC ]
#define MIN mcuSfr[ sfr_MIN ]
#define HOUR mcuSfr[ sfr_HOUR ]
#define WEEK mcuSfr[ sfr_WEEK ]
#define DAY mcuSfr[ sfr_DAY ]
#define MONTH mcuSfr[ sfr_MONTH ]
#define YEAR mcuSfr[ sfr_YEAR ]
#define SUBCUD mcuSfr[ sfr_SUBCUD ]
#define ALARMWM mcuSfr[ sfr_ALARMWM ]
#define ALARMWH mcuSfr[ sfr_ALARMWH ]
#define ALARMWW mcuSfr[ sfr_ALARMWW ]
#define RTCC0 mcuSfr[ sfr_RTCC0 ]
#define RTCC1 mcuSfr[ sfr_RTCC1 ]
#define RTCC2 mcuSfr[ sfr_RTCC2 ]
#define CMC mcuSfr[ sfr_CMC ]
#define CSC mcuSfr[ sfr_CSC ]
#define OSTC mcuSfr[ sfr_OSTC ]
#define OSTS mcuSfr[ sfr_OSTS ]
#define CKC mcuSfr[ sfr_CKC ]
#define CKS0 mcuSfr[ sfr_CKS0 ]
#define CKS1 mcuSfr[ sfr_CKS1 ]
#define RESF mcuSfr[ sfr_RESF ]
#define LVIM mcuSfr[ sfr_LVIM ]
#define LVIS mcuSfr[ sfr_LVIS ]
#define WDTE mcuSfr[ sfr_WDTE ]
#define DSA0 mcuSfr[ sfr_DSA0 ]
#define DSA1 mcuSfr[ sfr_DSA1 ]
#define DMC0 mcuSfr[ sfr_DMC0 ]
#define DMC1 mcuSfr[ sfr_DMC1 ]
#define DRC0 mcuSfr[ sfr_DRC0 ]
#define DRC1 mcuSfr[ sfr_DRC1 ]
#define BECTL mcuSfr[ sfr_BECTL ]
#define PFCMD mcuSfr[ sfr_PFCMD ]
#define PFS mcuSfr[ sfr_PFS ]
#define FLPMC mcuSfr[ sfr_FLPMC ]
#define PMC mcuSfr[ sfr_PMC ]
#define TXD0_SIO00 mcuSfr[ sfr_TXD0_SIO00 ]
#define RXD0_SIO01 mcuSfr[ sfr_RXD0_SIO01 ]
#define TDR00 mcuSfr[ sfr_TDR00 ]
#define TDR01 mcuSfr[ sfr_TDR01 ]
#define TXD1 mcuSfr[ sfr_TXD1 ]
#define SIO10 mcuSfr[ sfr_SIO10 ]
#define RXD1 mcuSfr[ sfr_RXD1 ]
#define TDR03 mcuSfr[ sfr_TDR03 ]
#define TDR04 mcuSfr[ sfr_TDR04 ]
#define TDR05 mcuSfr[ sfr_TDR05 ]
#define TDR06 mcuSfr[ sfr_TDR06 ]
#define TDR07 mcuSfr[ sfr_TDR07 ]
#define RSUBC mcuSfr[ sfr_RSUBC ]
#define DRA0L mcuSfr[ sfr_DRA0L ]
#define DRA0H mcuSfr[ sfr_DRA0H ]
#define DRA1L mcuSfr[ sfr_DRA1L ]
#define DRA1H mcuSfr[ sfr_DRA1H ]
#define DBC0L mcuSfr[ sfr_DBC0L ]
#define DBC0H mcuSfr[ sfr_DBC0H ]
#define DBC1L mcuSfr[ sfr_DBC1L ]
#define DBC1H mcuSfr[ sfr_DBC1H ]
#define IF2L mcuSfr[ sfr_IF2L ]
#define IF2H mcuSfr[ sfr_IF2H ]
#define MK2L mcuSfr[ sfr_MK2L ]
#define MK2HL mcuSfr[ sfr_MK2HL ]
#define PR02L mcuSfr[ sfr_PR02L ]
#define PR02H mcuSfr[ sfr_PR02H ]
#define PR12L mcuSfr[ sfr_PR12L ]
#define PR12H mcuSfr[ sfr_PR12H ]
//#define IF0L mcuSfr[ sfr_IF0L ]
//#define IF0H mcuSfr[ sfr_IF0H ]
#define IF0 mcuSfr[ sfr_IF0 ]
//#define IF1L mcuSfr[ sfr_IF1L ]
//#define IF1H mcuSfr[ sfr_IF1H ]
#define IF1H mcuSfr[ sfr_IF1 ]
//#define MK0L mcuSfr[ sfr_MK0L ]
//#define MK0H mcuSfr[ sfr_MK0H ]
#define MK0L mcuSfr[ sfr_MK0 ]
//#define MK1L mcuSfr[ sfr_MK1L ]
//#define MK1H mcuSfr[ sfr_MK1H ]
#define MK1H mcuSfr[ sfr_MK1 ]
#define PR00 mcuSfr[ sfr_PR00 ]
//#define PR00L mcuSfr[ sfr_PR00L ]
//#define PR00H mcuSfr[ sfr_PR00H ]
#define PR01 mcuSfr[ sfr_PR01 ]
//#define PR01L mcuSfr[ sfr_PR01L ]
//#define PR01H mcuSfr[ sfr_PR01H ]
#define PR10 mcuSfr[ sfr_PR10 ]
//#define PR10L mcuSfr[ sfr_PR10L ]
//#define PR10H mcuSfr[ sfr_PR10H ]
#define PR11 mcuSfr[ sfr_PR11 ]
//#define PR11L mcuSfr[ sfr_PR11L ]
//#define PR11H mcuSfr[ sfr_PR11H ]
#define MDAL_MULA mcuSfr[ sfr_MDAL_MULA ]
#define MDAH_MULB mcuSfr[ sfr_MDAH_MULB ]
#define MDBH_MULOH mcuSfr[ sfr_MDBH_MULOH ]
#define MDBL_MULOL mcuSfr[ sfr_MDBL_MULOL ]
#define P0 mcuSfr[ sfr_P0 ]
#define PM0 mcuSfr[ sfr_PM0 ]
#define PM1 mcuSfr[ sfr_PM1 ]
#define P1 mcuSfr[ sfr_P1 ]
#define P2 mcuSfr[ sfr_P2 ]
#define PM2 mcuSfr[ sfr_PM2 ]
#define PM3 mcuSfr[ sfr_PM3 ]
#define P3 mcuSfr[ sfr_P3 ]
#define P4 mcuSfr[ sfr_P4 ]
#define PM4 mcuSfr[ sfr_PM4 ]
#define P5 mcuSfr[ sfr_P5 ]
#define PM5 mcuSfr[ sfr_PM5 ]
#define P6 mcuSfr[ sfr_P6 ]
#define PM6 mcuSfr[ sfr_PM6 ]
#define P7 mcuSfr[ sfr_P7 ]
#define PM7 mcuSfr[ sfr_PM7 ]
#define P12 mcuSfr[ sfr_P12 ]
#define PM12 mcuSfr[ sfr_PM12 ]
#define P14 mcuSfr[ sfr_P14 ]
#define PM14 mcuSfr[ sfr_PM14 ]
#define P15 mcuSfr[ sfr_P15 ]
#define PM15 mcuSfr[ sfr_PM15 ]
// 2nd sfr
#define ADPC mcuSfr2[ sfr_ADPC ]
#define PU0 mcuSfr2[ sfr_PU0 ]
#define PU1 mcuSfr2[ sfr_PU1 ]
#define PU3 mcuSfr2[ sfr_PU3 ]
#define PU4 mcuSfr2[ sfr_PU4 ]
#define PU5 mcuSfr2[ sfr_PU5 ]
#define PU7 mcuSfr2[ sfr_PU7 ]
#define PU12 mcuSfr2[ sfr_PU12 ]
#define PU14 mcuSfr2[ sfr_PU14 ]
#define PIM3 mcuSfr2[ sfr_PIM3 ]
#define PIM7 mcuSfr2[ sfr_PIM7 ]
#define POM3 mcuSfr2[ sfr_POM3 ]
#define POM7 mcuSfr2[ sfr_POM7 ]
#define NFEN0 mcuSfr2[ sfr_NFEN0 ]
#define NFEN1 mcuSfr2[ sfr_NFEN1 ]
#define NFEN2 mcuSfr2[ sfr_NFEN2 ]
#define MDCL mcuSfr2[ sfr_MDCL ]
#define MDCH mcuSfr2[ sfr_MDCH ]
#define MDUC mcuSfr2[ sfr_MDUC ]
#define PER0 mcuSfr2[ sfr_PER0 ]
#define PER2 mcuSfr2[ sfr_PER2 ]
#define OSMC mcuSfr2[ sfr_OSMC ]
#define BCDADJ mcuSfr2[ sfr_BCDADJ ]
#define SSR00L mcuSfr2[ sfr_SSR00L ]
#define SSR00 mcuSfr2[ sfr_SSR00 ]
#define SSR01L mcuSfr2[ sfr_SSR01L ]
#define SSR01 mcuSfr2[ sfr_SSR01 ]
#define SSR02L mcuSfr2[ sfr_SSR02L ]
#define SSR02 mcuSfr2[ sfr_SSR02 ]
#define SSR03L mcuSfr2[ sfr_SSR03L ]
#define SSR03 mcuSfr2[ sfr_SSR03 ]
#define SIR00L mcuSfr2[ sfr_SIR00L ]
#define SIR00 mcuSfr2[ sfr_SIR00 ]
#define SIR01L mcuSfr2[ sfr_SIR01L ]
#define SIR02L mcuSfr2[ sfr_SIR02L ]
#define SIR01 mcuSfr2[ sfr_SIR01 ]
#define SIR02 mcuSfr2[ sfr_SIR02 ]
#define SIR03L mcuSfr2[ sfr_SIR03L ]
#define SIR03 mcuSfr2[ sfr_SIR03 ]
#define SMR00 mcuSfr2[ sfr_SMR00 ]
#define SMR01 mcuSfr2[ sfr_SMR01 ]
#define SMR02 mcuSfr2[ sfr_SMR02 ]
#define SMR03 mcuSfr2[ sfr_SMR03 ]
#define SCR00 mcuSfr2[ sfr_SCR00 ]
#define SCR01 mcuSfr2[ sfr_SCR01 ]
#define SCR02 mcuSfr2[ sfr_SCR02 ]
#define SCR03 mcuSfr2[ sfr_SCR03 ]
#define SE0L mcuSfr2[ sfr_SE0L ]
#define SE0 mcuSfr2[ sfr_SE0 ]
#define SS0L mcuSfr2[ sfr_SS0L ]
#define SS0 mcuSfr2[ sfr_SS0 ]
#define ST0L mcuSfr2[ sfr_ST0L ]
#define ST0 mcuSfr2[ sfr_ST0 ]
#define SPS0L mcuSfr2[ sfr_SPS0L ]
#define SPS0 mcuSfr2[ sfr_SPS0 ]
#define SO0 mcuSfr2[ sfr_SO0 ]
#define SOE0L mcuSfr2[ sfr_SOE0L ]
#define SOE0 mcuSfr2[ sfr_SOE0 ]
#define SOL0L mcuSfr2[ sfr_SOL0L ]
#define SOL0 mcuSfr2[ sfr_SOL0 ]
#define TCR00 mcuSfr2[ sfr_TCR00 ]
#define TCR01 mcuSfr2[ sfr_TCR01 ]
#define TCR02 mcuSfr2[ sfr_TCR02 ]
#define TCR07 mcuSfr2[ sfr_TCR07 ]
#define TO0L mcuSfr2[ sfr_TO0L ]
#define TOL0L mcuSfr2[ sfr_TOL0L ]
#define TPS0L mcuSfr2[ sfr_TPS0L ]
#define TSR07L mcuSfr2[ sfr_TSR07L ]
#define TMR00 mcuSfr2[ sfr_TMR00 ]
#define TMR02 mcuSfr2[ sfr_TMR02 ]
#define TMR04 mcuSfr2[ sfr_TMR04 ]
#define TMR06 mcuSfr2[ sfr_TMR06 ]
#define TSR00L mcuSfr2[ sfr_TSR00L ]
#define TOE0L mcuSfr2[ sfr_TOE0L ]
#define TMR01 mcuSfr2[ sfr_TMR01 ]
#define TMR03 mcuSfr2[ sfr_TMR03 ]
#define TMR05 mcuSfr2[ sfr_TMR05 ]
#define TMR07 mcuSfr2[ sfr_TMR07 ]
#define TT0L mcuSfr2[ sfr_TT0L ]
#define TOM0L mcuSfr2[ sfr_TOM0L ]
#define TE0L mcuSfr2[ sfr_TE0L ]
#define TS0L mcuSfr2[ sfr_TS0L ]
#define IICCTL01 mcuSfr2[ sfr_IICCTL01 ]
#define IICCTL11 mcuSfr2[ sfr_IICCTL11 ]
#define IICS1 mcuSfr2[ sfr_IICS1 ]
#define PER3 mcuSfr2[ sfr_PER3 ]
#define PU20 mcuSfr2[ sfr_PU20 ]
#define TCR04 mcuSfr2[ sfr_TCR04 ]
#define TCR06 mcuSfr2[ sfr_TCR06 ]
#define EGN2 mcuSfr2[ sfr_EGN2 ]
#define EGP2 mcuSfr2[ sfr_EGP2 ]
#define IICWH0 mcuSfr2[ sfr_IICWH0 ]
#define IICWH1 mcuSfr2[ sfr_IICWH1 ]
#define IICWL0 mcuSfr2[ sfr_IICWL0 ]
#define IICWL1 mcuSfr2[ sfr_IICWL1 ]
#define SVA0 mcuSfr2[ sfr_SVA0 ]
#define SVA1 mcuSfr2[ sfr_SVA1 ]
#define IICA1 mcuSfr2[ sfr_IICA1 ]
#define IICCTL00 mcuSfr2[ sfr_IICCTL00 ]
#define IICCTL10 mcuSfr2[ sfr_IICCTL10 ]
#define IICF1 mcuSfr2[ sfr_IICF1 ]
#define P20 mcuSfr2[ sfr_P20 ]
#define PM20 mcuSfr2[ sfr_PM20 ]
#define TCR03 mcuSfr2[ sfr_TCR03 ]
#define TCR05 mcuSfr2[ sfr_TCR05 ]
#define TSR01L mcuSfr2[ sfr_TSR01L ]
#define TSR02L mcuSfr2[ sfr_TSR02L ]
#define TSR03L mcuSfr2[ sfr_TSR03L ]
#define TSR04L mcuSfr2[ sfr_TSR04L ]
#define TSR05L mcuSfr2[ sfr_TSR05L ]
#define TSR06L mcuSfr2[ sfr_TSR06L ]
#define TE0 mcuSfr2[ sfr_TE0 ]
#define TO0 mcuSfr2[ sfr_TO0 ]
#define TOE0 mcuSfr2[ sfr_TOE0 ]
#define TOL0 mcuSfr2[ sfr_TOL0 ]
#define TOM0 mcuSfr2[ sfr_TOM0 ]
#define TPS0 mcuSfr2[ sfr_TPS0 ]
#define TS0 mcuSfr2[ sfr_TS0 ]
#define TSR07 mcuSfr2[ sfr_TSR07 ]
#define TT0 mcuSfr2[ sfr_TT0 ]
#define TSR00 mcuSfr2[ sfr_TSR00 ]
#define TSR01 mcuSfr2[ sfr_TSR01 ]
#define TSR02 mcuSfr2[ sfr_TSR02 ]
#define TSR03 mcuSfr2[ sfr_TSR03 ]
#define TSR04 mcuSfr2[ sfr_TSR04 ]
#define TSR05 mcuSfr2[ sfr_TSR05 ]
#define TSR06 mcuSfr2[ sfr_TSR06 ]
typedef unsigned char bit;
bit ACKD1;
bit ACKE0;
bit ACKE1;
bit ADCEN;
bit ADCS;
bit ADIF;
bit ADMK;
bit COI1;
bit DBC1;
bit DEN1;
bit DFC1;
bit DMAIF1;
bit DMAMK1;
bit DRA1;
bit DST1;
bit IF1;
bit IF2;
bit IICA0EN;
bit IICA1EN;
bit IICAIF0;
bit IICAIF1;
bit IICAMK0;
bit IICAMK1;
bit IICAPR00;
bit IICAPR01;
bit IICAPR10;
bit IICAPR11;
bit IICE0;
bit IICE1;
bit IICIF10;
bit IICMK10;
bit IICRSV0;
bit IICRSV1;
bit LREL0;
bit LREL1;
bit MK0;
bit MK1;
bit MK2;
bit PIF0;
bit PIF21;
bit PMK23;
bit PMK6;
bit RCLOE0;
bit RTCE;
bit RTCEN;
bit RTCIF;
bit RTCIIF;
bit RTCIMK;
bit RTCMK;
bit RWAIT;
bit RWST;
bit SAU0EN;
bit SDR02;
bit SLP_ACK;
bit SMC0;
bit SMC1;
bit SPD1;
bit SPIE0;
bit SPIE1;
bit STCEN0;
bit STCEN1;
bit STD1;
bit TAU0EN;
bit TDR02;
bit WALE;
bit WREL0;
bit WREL1;
bit WTIM0;
bit WTIM1;
bit BECTL_7;
#include "sfrAlias.h"
#endif
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