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ctr_mcu/branches/0.10(X3)/inter_asm/self_flash.asm
N2232 dc469bd4c6 0.10のX3対応版を登録 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
2010-06-23 07:16:15 +00:00

1311 lines
43 KiB
NASM
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; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no self_flash.c
; In-file : self_flash.c
; Asm-file : inter_asm\self_flash.asm
; Para-file :
$PROCESSOR(9F0104)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
$DGS FIL_NAM, .file, 0B4H, 0FFFEH, 03FH, 067H, 01H, 00H
$DGS AUX_FIL, self_flash.c
$DGS MOD_NAM, self_flash, 00H, 0FFFEH, 00H, 077H, 00H, 00H
$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
$DGS AUX_TAG, 01H, 019H
$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
$DGS AUX_EOS, 013H, 01H
$DGS LAB_SYM, bs_F0064, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_F0064, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, bs_S0062, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_S0062, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, bs_F0063, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_F0063, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, bs_F0061, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_F0061, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, bs_S0060, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_S0060, U, U, 00H, 06H, 00H, 00H
$DGS GLV_SYM, _firm_update, U, U, 0CH, 026H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H
$DGS BEG_FUN, ??bf_firm_update, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 061H, 06H, 029H
$DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H
$DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H
$DGS BEG_BLK, ??bb00_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 015H, 00H, 02DH
$DGS END_BLK, ??eb00_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 017H
$DGS BEG_BLK, ??bb01_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 01FH, 00H, 02FH
$DGS BEG_BLK, ??bb02_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 028H, 00H, 035H
$DGS AUT_VAR, _p_buffer, 02H, 0FFFFH, 0CH, 01H, 01H, 01H
$DGS AUX_STR, 00H, 029H, 02H, 00H, 00H, 00H, 00H, 01H
$DGS AUT_VAR, _buffer_fill, 01H, 0FFFFH, 0CH, 01H, 01H, 00H
$DGS AUX_STR, 00H, 02AH, 01H, 00H, 00H, 00H, 00H, 00H
$DGS BEG_BLK, ??bb03_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 030H, 00H, 037H
$DGS BEG_BLK, ??bb04_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 031H, 00H, 03DH
$DGS END_BLK, ??eb04_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 031H
$DGS END_BLK, ??eb03_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 037H
$DGS BEG_BLK, ??bb05_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 043H, 00H, 043H
$DGS END_BLK, ??eb05_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04AH
$DGS END_BLK, ??eb02_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04CH
$DGS BEG_BLK, ??bb06_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 04EH, 00H, 047H
$DGS END_BLK, ??eb06_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 051H
$DGS BEG_BLK, ??bb07_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 054H, 00H, 04DH
$DGS END_BLK, ??eb07_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 056H
$DGS END_BLK, ??eb01_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 057H
$DGS BEG_BLK, ??bb08_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 05CH, 00H, 053H
$DGS AUT_VAR, _i, 03H, 0FFFFH, 0CH, 01H, 01H, 00H
$DGS AUX_STR, 00H, 05DH, 01H, 00H, 00H, 00H, 00H, 00H
$DGS AUT_VAR, _comp, 02H, 0FFFFH, 0CH, 01H, 01H, 00H
$DGS AUX_STR, 00H, 05EH, 01H, 00H, 00H, 00H, 00H, 00H
$DGS BEG_BLK, ??bb09_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 062H, 00H, 057H
$DGS END_BLK, ??eb09_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 064H
$DGS BEG_BLK, ??bb0A_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 066H, 00H, 05BH
$DGS END_BLK, ??eb0A_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 06CH
$DGS BEG_BLK, ??bb0B_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 06EH, 00H, 00H
$DGS END_BLK, ??eb0B_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 075H
$DGS END_BLK, ??eb08_firm_update, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 076H
$DGS END_FUN, ??ef_firm_update, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 077H
$DGS GLV_SYM, _firm_restore, U, U, 0CH, 026H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H
$DGS BEG_FUN, ??bf_firm_restore, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 0E3H, 00H, 069H
$DGS END_FUN, ??ef_firm_restore, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 013H
$DGS STA_SYM, _FSL_Open, U, U, 01H, 03H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 077H, 00H, 00H
$DGS BEG_FUN, ??bf_FSL_Open, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 0FCH, 00H, 06DH
$DGS BEG_BLK, ??bb00_FSL_Open, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 014H, 00H, 071H
$DGS END_BLK, ??eb00_FSL_Open, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 014H
$DGS BEG_BLK, ??bb01_FSL_Open, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 01BH, 00H, 00H
$DGS END_BLK, ??eb01_FSL_Open, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 01BH
$DGS END_FUN, ??ef_FSL_Open, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 01CH
$DGS STA_SYM, _FSL_Close, U, U, 01H, 03H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H
$DGS BEG_FUN, ??bf_FSL_Close, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 011FH, 00H, 07BH
$DGS BEG_BLK, ??bb00_FSL_Close, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 04H, 00H, 00H
$DGS END_BLK, ??eb00_FSL_Close, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04H
$DGS END_FUN, ??ef_FSL_Close, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 0EH
$DGS STA_SYM, _firm_duplicate, U, U, 0CH, 03H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 0A8H, 00H, 00H
$DGS BEG_FUN, ??bf_firm_duplicate, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 0139H, 0AH, 08AH
$DGS FUN_ARG, _p_rom, 06H, 0FFFFH, 0CH, 09H, 01H, 01H
$DGS AUX_STR, 00H, 00H, 04H, 00H, 00H, 00H, 00H, 02H
$DGS FUN_ARG, _block_dest, 010H, 0FFFFH, 0CH, 09H, 00H, 00H
$DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H
$DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H
$DGS BEG_BLK, ??bb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 09H, 00H, 08CH
$DGS BEG_BLK, ??bb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 0DH, 00H, 090H
$DGS END_BLK, ??eb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 0FH
$DGS BEG_BLK, ??bb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 015H, 00H, 096H
$DGS AUT_VAR, _buffer_fill, 03H, 0FFFFH, 0CH, 01H, 01H, 00H
$DGS AUX_STR, 00H, 016H, 01H, 00H, 00H, 00H, 00H, 00H
$DGS AUT_VAR, _p_buff, 00H, 0FFFFH, 0CH, 01H, 01H, 01H
$DGS AUX_STR, 00H, 017H, 02H, 00H, 00H, 00H, 00H, 01H
$DGS BEG_BLK, ??bb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 01DH, 00H, 09AH
$DGS END_BLK, ??eb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 022H
$DGS BEG_BLK, ??bb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 02CH, 00H, 0A0H
$DGS END_BLK, ??eb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 02FH
$DGS END_BLK, ??eb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 030H
$DGS BEG_BLK, ??bb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 033H, 00H, 00H
$DGS END_BLK, ??eb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 036H
$DGS END_BLK, ??eb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 037H
$DGS END_FUN, ??ef_firm_duplicate, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 03AH
$DGS STA_SYM, _my_FSL_Init, U, U, 0CH, 03H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 0AEH, 00H, 00H
$DGS BEG_FUN, ??bf_my_FSL_Init, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 0179H, 00H, 0AEH
$DGS END_FUN, ??ef_my_FSL_Init, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 0CH
$DGS GLV_SYM, _tski_mcu_reset, U, U, 0AH, 026H, 01H, 02H
$DGS AUX_FUN, 013H, U, U, 0B4H, 00H, 00H
$DGS BEG_FUN, ??bf_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 0188H, 00H, 0B4H
$DGS END_FUN, ??ef_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 0BH
$DGS GLV_SYM, _fsl_fx_MHz_u08, U, U, 0500CH, 026H, 00H, 00H
$DGS GLV_SYM, _fsl_low_voltage_u08, U, U, 0500CH, 026H, 00H, 00H
$DGS GLV_SYM, _FSL_Erase, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_IVerify, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _FSL_Write, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _pool, U, U, 0DH, 02H, 01H, 03H
$DGS AUX_STR, 00H, 00H, 02H, 01H, 00H, 00H, 00H, 00H
$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_SwapBootCluster, U, U, 01H, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_InvertBootFlag, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, @@iscmp, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _FSL_BlankCheck, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_Init, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_ModeCheck, U, U, 0CH, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _FSL_ForceReset, U, U, 01H, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
EXTRN _FSL_Erase
EXTRN _FSL_IVerify
EXTRN _@RTARG0
EXTRN _@RTARG2
EXTRN _FSL_Write
EXTRN _pool
EXTRN _WDT_Restart
EXTRN _FSL_SwapBootCluster
EXTRN _FSL_InvertBootFlag
EXTRN @@iscmp
EXTRN _FSL_BlankCheck
EXTRN _FSL_Init
EXTRN _FSL_ModeCheck
EXTRN _FSL_ForceReset
PUBLIC _fsl_fx_MHz_u08
PUBLIC _fsl_low_voltage_u08
PUBLIC _firm_update
PUBLIC _firm_restore
PUBLIC _tski_mcu_reset
@@BITS BSEG
@@CNST CSEG MIRRORP
_fsl_fx_MHz_u08: DB 08H ; 8
_fsl_low_voltage_u08: DB 01H ; 1
@@R_INIT CSEG UNIT64KP
@@INIT DSEG BASEP
@@DATA DSEG BASEP
@@R_INIS CSEG UNIT64KP
@@INIS DSEG SADDRP
@@DATS DSEG SADDRP
LDR_CNSL CSEG PAGE64KP
@@RLINIT CSEG UNIT64KP
@@INITL DSEG UNIT64KP
@@DATAL DSEG UNIT64KP
@@CALT CSEG CALLT0
; Sub-Routines created by CC78K0R
LDR_CODE CSEG BASE
bs_F0064:
mov a,[hl+5] ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
br !_FSL_Erase ;[INF] 3, 3
es_F0064:
LDR_CODE CSEG BASE
bs_S0062:
push hl ;[INF] 1, 1
movw hl,#0541H ; 1345 ;[INF] 3, 1
mov1 CY,[hl].0 ;[INF] 2, 1
pop hl ;[INF] 1, 1
ret ;[INF] 1, 6
es_S0062:
LDR_CODE CSEG BASE
bs_F0063:
mov a,[hl+5] ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
call !_FSL_IVerify ;[INF] 3, 3
cmp0 c ;[INF] 1, 1
ret ;[INF] 1, 6
es_F0063:
LDR_CODE CSEG BASE
bs_F0061:
movw _@RTARG0,ax ;[INF] 2, 1
sarw ax,15 ;[INF] 2, 1
movw _@RTARG2,ax ;[INF] 2, 1
movw bc,_@RTARG2 ;[INF] 2, 1
movw ax,_@RTARG0 ;[INF] 2, 1
br !_FSL_Write ;[INF] 3, 3
es_F0061:
LDR_CODE CSEG BASE
bs_S0060:
mov a,[hl+5] ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
shlw ax,10 ;[INF] 2, 1
movw bc,ax ;[INF] 1, 1
mov a,[hl+4] ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
shlw ax,8 ;[INF] 2, 1
addw ax,bc ;[INF] 1, 1
ret ;[INF] 1, 6
es_S0060:
; *** Sub-Routine Information ***
;
; $SUB bs_S0060
; CODE SIZE= 15 bytes
;
; $SUB bs_F0061
; CODE SIZE= 13 bytes
;
; $SUB bs_S0062
; CODE SIZE= 8 bytes
;
; $SUB bs_F0063
; CODE SIZE= 9 bytes
;
; $SUB bs_F0064
; CODE SIZE= 7 bytes
; End of Sub-Routines
; line 1 : /* ========================================================
; line 2 : <20><><EFBFBD>ȃA<C883>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^
; line 3 : ======================================================== */
; line 4 : #pragma SFR
; line 5 : #pragma di
; line 6 : #pragma ei
; line 7 : #pragma nop
; line 8 : #pragma stop
; line 9 : #pragma halt
; line 10 :
; line 11 :
; line 12 : #include "incs_loader.h"
; line 13 :
; line 14 : #include <fsl.h>
; line 15 : #include "fsl_user.h"
; line 16 : #include "i2c_ctr.h"
; line 17 :
; line 18 :
; line 19 :
; line 20 : // ========================================================
; line 21 : const u8 fsl_fx_MHz_u08 = 8;
; line 22 : const u8 fsl_low_voltage_u08 = 1;
; line 23 :
; line 24 :
; line 25 : // <20><><EFBFBD>ȃt<C883><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD>[<5B>^
; line 26 : #define SAM_BLOCK_SIZE 1024
; line 27 : #define SELF_UPDATE_BUFF_SIZE 256
; line 28 : #define SELF_UPDATE_SPLIT_WRITE_NUM ( SAM_BLOCK_SIZE / SELF_U
; PDATE_BUFF_SIZE )
; line 29 : #define SAM_WORD_SIZE 4
; line 30 :
; line 31 : // <20><><EFBFBD>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ԍ<EFBFBD><D48D>i1<69>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E>
; 1kB<6B>j
; line 32 : #define INACTIVE_BOOTSECT_TOP 4
; line 33 : #define FIRM_TOP 8
; line 34 : #define FIRM_SIZE 12
; line 35 : #define UPDATE_BLOCK_LAST ( FIRM_TOP + FIRM_SIZE - 1
; )
; line 36 :
; line 37 :
; line 38 : #ifdef _MCU_BSR_
; line 39 :
; line 40 :
; line 41 : #define ACKD ACKD1
; line 42 : #define ACKE ACKE1
; line 43 : #define COI COI1
; line 44 : #define IICAEN IICA1EN
; line 45 : #define IICAPR0 IICAPR10
; line 46 : #define IICRSV IICRSV1
; line 47 : #define IICA IICA1
; line 48 : #define IICAIF IICAIF1
; line 49 : #define IICAMK IICAMK1
; line 50 : #define IICAPR1 IICAPR11
; line 51 : #define IICCTL0 IICCTL01
; line 52 : #define IICE IICE1
; line 53 : #define IICF IICF1
; line 54 : #define IICS IICS1
; line 55 : #define IICWH IICWH1
; line 56 : #define IICWL IICWL1
; line 57 : #define LREL LREL1
; line 58 : #define SPD SPD1
; line 59 : #define SPIE SPIE1
; line 60 : #define STCEN STCEN1
; line 61 : #define STD STD1
; line 62 : #define SVA SVA1
; line 63 : #define WREL WREL1
; line 64 : #define WTIM WTIM1
; line 65 : #endif
; line 66 :
; line 67 :
; line 68 :
; line 69 : // ========================================================
; line 70 : static void FSL_Open( void );
; line 71 : static void FSL_Close( void );
; line 72 : err firm_restore( );
; line 73 :
; line 74 : static err my_FSL_Init();
; line 75 : static err firm_duplicate( __far u8 * p_rom, u8 block_dest );
; line 76 :
; line 77 :
; line 78 :
; line 79 : // ========================================================
; line 80 : extern u16 pool[];
; line 81 :
; line 82 :
; line 83 : // 0.D<>ȍ~ <20>V<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD><EFBFBD>
; line 84 : #define N_MGC_L 0x1FF6
; line 85 : #define N_MGC_T 0x4FF6
; line 86 :
; line 87 :
; line 88 :
; line 89 : /* ========================================================
; line 90 : I2C<32>Ŏ<EFBFBD><C58E>M<EFBFBD><4D><EFBFBD>āA
; line 91 : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݁A
; line 92 : <20>`<60>F<EFBFBD>b<EFBFBD>NOK<4F>@<40><><EFBFBD>@<40>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>ɐ؂<C990><D882>ւ<EFBFBD><D682>čċN<C48B><4E>
; line 93 : <20>@<40>@<40>@<40>@NG<4E>@<40><><EFBFBD>@<40><><EFBFBD>i<EFBFBD><69><EFBFBD>j<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>ɖ߂<C996><DF82>čċN<C48B><4E>
; line 94 : <20>i<EFBFBD><69><EFBFBD>̊֐<CC8A><D690><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͖߂<CD96><DF82>܂<EFBFBD><DC82><EFBFBD><EFBFBD>j
; line 95 : ======================================================== */
; line 96 : err firm_update( )
; line 97 : {
LDR_CODE CSEG BASE
_firm_update:
$DGL 1,35
push hl ;[INF] 1, 1
subw sp,#06H ;[INF] 2, 1
movw hl,sp ;[INF] 3, 1
??bf_firm_update:
; line 98 : u8 target_block;
; line 99 : u8 split_write_count; // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ւ<EFBFBD><D682>܂<EFBFBD><DC82>܏<EFBFBD><DC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ރJ<DE83>E
; <20><><EFBFBD>^
; line 100 :
; line 101 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682>O<EFBFBD><4F><EFBFBD><EFBFBD> /////////////////////////////////////
; line 102 : my_FSL_Init();
$DGL 0,6
call !_my_FSL_Init ;[INF] 3, 3
; line 103 :
; line 104 : /* <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̃o<CC83>b<EFBFBD>N<EFBFBD>A<EFBFBD>b<EFBFBD>v
; line 105 : 0x2000 - 0x4FFF <20><>
; line 106 : 0x5000 - 0x7FFF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 20 - 31) <20>ɃR<C983>s<EFBFBD>[
; line 107 : */
; line 108 : firm_duplicate( ( __far u8 * ) 0x2000,
; line 109 : ( 0x5000 / 0x0400 ) );
$DGL 0,13
movw ax,#014H ; 20 ;[INF] 3, 1
push ax ;[INF] 1, 1
movw ax,#02000H ; 8192 ;[INF] 3, 1
clrw bc ;[INF] 1, 1
call !_firm_duplicate ;[INF] 3, 3
pop ax ;[INF] 1, 1
; line 110 :
; line 111 : // <20>S<EFBFBD>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>폜 /////////////////////////////////////
; line 112 : // <20>d<EFBFBD><64><EFBFBD>f<EFBFBD>𔻒肷<F094BB92>邽<EFBFBD>߁A<DF81>ŏ<EFBFBD><C58F>ɑS<C991>N<EFBFBD><4E><EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 113 : //<2F>i<EFBFBD>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>Ɏc<C98E><63><EFBFBD>Ă<EFBFBD><C482>A<EFBFBD>ȑO<C891>̃t<CC83>@<40>[<5B><><EFBFBD>̃t
; <20>b<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>j
; line 114 : for( target_block = INACTIVE_BOOTSECT_TOP;
$DGL 0,18
mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1
?L0003:
; line 115 : target_block <= UPDATE_BLOCK_LAST;
$DGL 0,19
mov a,[hl+5] ; target_block ;[INF] 2, 1
cmp a,#014H ; 20 ;[INF] 2, 1
bnc $?L0004 ;[INF] 2, 4
; line 116 : target_block += 1 )
; line 117 : {
??bb00_firm_update:
; line 118 : FSL_Erase( target_block );
$DGL 0,22
call !bs_F0064 ;[INF] 3, 3
??eb00_firm_update:
; line 119 : }
$DGL 0,23
inc [hl+5] ; target_block ;[INF] 3, 2
br $?L0003 ;[INF] 2, 3
?L0004:
; line 120 :
; line 121 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD> ///////////////////////////////////////////
; line 122 : // <20><><EFBFBD>X<EFBFBD>g<EFBFBD>b<EFBFBD>v<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂ő<DC82><C591><EFBFBD><EFBFBD><EFBFBD>
; line 123 : // <20><><EFBFBD>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>[<5B>`<60><><EFBFBD>ɔ<EFBFBD><C994><EFBFBD>
; line 124 : for( target_block = INACTIVE_BOOTSECT_TOP;
$DGL 0,28
mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1
?L0006:
; line 125 : target_block <= UPDATE_BLOCK_LAST;
$DGL 0,29
mov a,[hl+5] ; target_block ;[INF] 2, 1
cmp a,#014H ; 20 ;[INF] 2, 1
bnc $?L0007 ;[INF] 2, 4
; line 126 : target_block += 1 )
; line 127 : {
??bb01_firm_update:
; line 128 : // <20>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>̈<EFBFBD><CC88>폜
; line 129 : FSL_Erase( target_block );
$DGL 0,33
call !bs_F0064 ;[INF] 3, 3
; line 130 :
; line 131 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 132 : for( split_write_count = 0;
$DGL 0,36
mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1
?L0009:
; line 133 : ( ( split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM
; )
; line 134 : && ( !SPD ) );
$DGL 0,38
mov a,[hl+4] ; split_write_count ;[INF] 2, 1
cmp a,#04H ; 4 ;[INF] 2, 1
bnc $?L0010 ;[INF] 2, 4
call !bs_S0062 ;[INF] 3, 3
bc $?L0010 ;[INF] 2, 4
; line 135 : split_write_count += 1 )
; line 136 : {
??bb02_firm_update:
; line 137 : u8* p_buffer = pool;
$DGL 0,41
movw ax,#loww (_pool) ;[INF] 3, 1
movw [hl+2],ax ; p_buffer ;[INF] 2, 1
; line 138 : u8 buffer_fill = 0;
$DGL 0,42
mov [hl+1],#00H ; buffer_fill,0 ;[INF] 3, 1
; line 139 :
; line 140 : WDT_Restart( );
$DGL 0,44
call !_WDT_Restart ;[INF] 3, 3
; line 141 :
; line 142 : // I2C<32><43><EFBFBD>珑<EFBFBD><E78F91><EFBFBD><EFBFBD><EFBFBD>݃f<DD83>[<5B>^<5E><><EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@<40>ɂ<EFBFBD><C982>߂<EFBFBD>
; line 143 : do
?L0012:
; line 144 : {
??bb03_firm_update:
; line 145 : while( !IICAIF && !SPD ){;}
$DGL 0,49
bt IF2H.3,$?L0016 ;[INF] 4, 5
call !bs_S0062 ;[INF] 3, 3
bnc $?L0012 ;[INF] 2, 4
??bb04_firm_update:
??eb04_firm_update:
?L0016:
; line 146 : IICAIF = 0;
$DGL 0,50
clr1 IF2H.3 ;[INF] 3, 2
; line 147 : *p_buffer = IICA;
$DGL 0,51
movw ax,[hl+2] ; p_buffer ;[INF] 2, 1
movw de,ax ;[INF] 1, 1
mov a,!IICA1 ;[INF] 3, 1
mov [de],a ;[INF] 1, 1
; line 148 : WREL = 1;
$DGL 0,52
set1 !IICCTL01.5 ;[INF] 4, 2
; line 149 : p_buffer += 1;
$DGL 0,53
incw [hl+2] ; p_buffer ;[INF] 3, 2
; line 150 : buffer_fill += 1;
$DGL 0,54
inc [hl+1] ; buffer_fill ;[INF] 3, 2
??eb03_firm_update:
; line 151 : }
; line 152 : while( ( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE
; ) && !SPD );
$DGL 0,56
mov a,[hl+1] ; buffer_fill ;[INF] 2, 1
cmp0 a ;[INF] 1, 1
bz $?L0017 ;[INF] 2, 4
call !bs_S0062 ;[INF] 3, 3
bnc $?L0012 ;[INF] 2, 4
?L0017:
; line 153 :
; line 154 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 155 : // <20>Ōゾ<C58C>ƁA<C681>S<EFBFBD>~<7E><><EFBFBD>p<EFBFBD>f<EFBFBD>B<EFBFBD><42><EFBFBD>O<EFBFBD><4F><EFBFBD>邪<EFBFBD>ʂɂ<CA82><C982>܂<EFBFBD><DC82>Ȃ<EFBFBD>
; line 156 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC
; K_SIZE
; line 157 : +
; line 158 : split_write_count *
; line 159 : SELF_UPDATE_BUFF_SIZE
; ),
; line 160 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE
; / SAM_WORD_SIZE ) )
; line 161 :
; line 162 : != FSL_OK )
$DGL 0,66
movw ax,#040H ; 64 ;[INF] 3, 1
push ax ;[INF] 1, 1
call !bs_S0060 ;[INF] 3, 3
call !bs_F0061 ;[INF] 3, 3
pop ax ;[INF] 1, 1
cmp0 c ;[INF] 1, 1
bz $?L0018 ;[INF] 2, 4
; line 163 : {
??bb05_firm_update:
; line 164 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݌<EFBFBD><DD8C>̃`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD>G<EFBFBD><47><EFBFBD>[
; line 165 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD>̂̂<CC82><CC82>A<EFBFBD><41><EFBFBD>X<EFBFBD>g<EFBFBD>A
; line 166 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
; line 167 : FSL_SwapBootCluster( );
$DGL 0,71
call !_FSL_SwapBootCluster ;[INF] 3, 3
; line 168 : // FSL_Close( );
; line 169 : return ( ERR_ERR );
$DGL 0,73
onew bc ;[INF] 1, 1
br $?L0030 ;[INF] 2, 3
??eb05_firm_update:
; line 170 : }
?L0018:
??eb02_firm_update:
; line 171 :
; line 172 : }
$DGL 0,76
inc [hl+4] ; split_write_count ;[INF] 3, 2
br $?L0009 ;[INF] 2, 3
?L0010:
; line 173 : // 1<>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݊<EFBFBD><DD8A><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD><78><EFBFBD>t<EFBFBD>@<40>C<EFBFBD><43><EFBFBD>s<EFBFBD><73>
; line 174 : if( FSL_IVerify( target_block ) != FSL_OK ){
$DGL 0,78
call !bs_F0063 ;[INF] 3, 3
skz ;[INF] 2, 1
??bb06_firm_update:
; line 175 : // todo <20>ēx<C493><78><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>x<EFBFBD><78><EFBFBD>t<EFBFBD>@<40>C<EFBFBD><43><EFBFBD>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD><D482><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; <20><><EFBFBD>_<EFBFBD><5F><EFBFBD>ł<EFBFBD><C582><EFBFBD>...
; line 176 : NOP();
$DGL 0,80
nop ;[INF] 1, 1
??eb06_firm_update:
; line 177 : }
?L0020:
; line 178 :
; line 179 : if( SPD )
$DGL 0,83
call !bs_S0062 ;[INF] 3, 3
bc $?L0007 ;[INF] 2, 4
; line 180 : {
??bb07_firm_update:
; line 181 : break;
??eb07_firm_update:
; line 182 : }
??eb01_firm_update:
; line 183 : }
$DGL 0,87
inc [hl+5] ; target_block ;[INF] 3, 2
br $?L0006 ;[INF] 2, 3
?L0007:
; line 184 :
; line 185 : LREL = 1;
$DGL 0,89
set1 !IICCTL01.6 ;[INF] 4, 2
; line 186 :
; line 187 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>񂾃t<F182BE83>@<40>[<5B><><EFBFBD>̃`<60>F<EFBFBD>b<EFBFBD>N //
; line 188 : {
??bb08_firm_update:
; line 189 : u8 i;
; line 190 : u8 comp = 0;
$DGL 0,94
mov [hl+2],#00H ; comp,0 ;[INF] 3, 1
; line 191 :
; line 192 : // <20><><EFBFBD>[<5B>_<EFBFBD>[<5B>̃}<7D>W<EFBFBD>b<EFBFBD>N<EFBFBD>ƁA<C681>{<7B><><EFBFBD>̖<EFBFBD><CC96><EFBFBD><EFBFBD>̃}<7D>W<EFBFBD>b<EFBFBD>N<EFBFBD>͓<EFBFBD><CD93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>m<EFBFBD>F
; line 193 : for( i = 0; i < sizeof( __TIME__ ); i++ )
$DGL 0,97
mov [hl+3],#00H ; i,0 ;[INF] 3, 1
?L0024:
mov a,[hl+3] ; i ;[INF] 2, 1
cmp a,#09H ; 9 ;[INF] 2, 1
bnc $?L0025 ;[INF] 2, 4
; line 194 : {
??bb09_firm_update:
; line 195 : comp += ( *( u8 * ) ( N_MGC_L + i ) == *( u8 * ) ( N
; _MGC_T + i ) ) ? 0 : 1;
$DGL 0,99
mov a,[hl+3] ; i ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
movw bc,ax ;[INF] 1, 1
mov a,8182[bc] ;[INF] 3, 1
mov c,a ;[INF] 1, 1
mov a,[hl+3] ; i ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
addw ax,#04FF6H ; 20470 ;[INF] 3, 1
movw de,ax ;[INF] 1, 1
mov a,[de] ;[INF] 1, 1
cmp c,a ;[INF] 2, 1
bnz $?L0027 ;[INF] 2, 4
clrw ax ;[INF] 1, 1
br $?L0028 ;[INF] 2, 3
?L0027:
onew ax ;[INF] 1, 1
?L0028:
mov a,x ;[INF] 1, 1
add a,[hl+2] ; comp ;[INF] 2, 1
mov [hl+2],a ; comp ;[INF] 2, 1
??eb09_firm_update:
; line 196 : }
$DGL 0,100
inc [hl+3] ; i ;[INF] 3, 2
br $?L0024 ;[INF] 2, 3
?L0025:
; line 197 : if( comp == 0 )
$DGL 0,101
mov a,[hl+2] ; comp ;[INF] 2, 1
cmp0 a ;[INF] 1, 1
bnz $?L0029 ;[INF] 2, 4
; line 198 : {
??bb0A_firm_update:
; line 199 : FSL_InvertBootFlag( );
$DGL 0,103
call !_FSL_InvertBootFlag ;[INF] 3, 3
; line 200 : FSL_SwapBootCluster( ); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>ɓ<EFBFBD><C993><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BF
; SL_Close<73>͕s<CD95>v
$DGL 0,104
call !_FSL_SwapBootCluster ;[INF] 3, 3
??eb0A_firm_update:
; line 201 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
; line 202 : // FSL_SwapActiveBootCluster(); // <20><><EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD>
; <20>܂<EFBFBD><DC82>̂ŁA<C581><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ꂸ<EFBFBD>\<5C><><EFBFBD>I
; line 203 : // <20>߂<EFBFBD><DF82>Ă<EFBFBD><C482>Ȃ<EFBFBD> //
; line 204 : }
$DGL 0,108
br $?L0030 ;[INF] 2, 3
?L0029:
; line 205 : else
; line 206 : {
??bb0B_firm_update:
; line 207 : // <20>f<EFBFBD>[<5B>^<5E>G<EFBFBD><47><EFBFBD>[
; line 208 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD>̂̂<CC82><CC82>A<EFBFBD><41><EFBFBD>X<EFBFBD>g<EFBFBD>A
; line 209 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
; line 210 : FSL_SwapBootCluster( );
$DGL 0,114
call !_FSL_SwapBootCluster ;[INF] 3, 3
??eb0B_firm_update:
; line 211 : // FSL_Close( );
; line 212 : // <20>߂<EFBFBD><DF82>Ă<EFBFBD><C482>Ȃ<EFBFBD> //
; line 213 : }
?L0030:
??eb08_firm_update:
; line 214 : }
; line 215 : }
$DGL 0,119
??ef_firm_update:
addw sp,#06H ;[INF] 2, 1
pop hl ;[INF] 1, 1
ret ;[INF] 1, 6
??ee_firm_update:
; line 216 :
; line 217 :
; line 218 :
; line 219 :
; line 220 : /* ========================================================
; line 221 : <20>@<40><><EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>b<EFBFBD>N<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>̈悩<CC88>烊<EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD>܂<EFBFBD><DC82>B
; line 222 : <20>@<40>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>A<EFBFBD>Ō<EFBFBD><C58C>̍Ō<CC8D><C58C>Ńu<C583>[<5B>g<EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD>̂ŁA
; line 223 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD>ł̓u<CD83>[<5B>g<EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD>͕s<CD95>v<EFBFBD>ł<EFBFBD><C582>B
; line 224 :
; line 225 : ======================================================== */
; line 226 : err firm_restore( )
; line 227 : {
_firm_restore:
$DGL 1,99
??bf_firm_restore:
; line 228 : my_FSL_Init();
$DGL 0,2
call !_my_FSL_Init ;[INF] 3, 3
; line 229 :
; line 230 : /* <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̃<EFBFBD><CC83>X<EFBFBD>g<EFBFBD>A
; line 231 : 0x4800 - 0x7FFF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 18 - 27) <20><><EFBFBD><EFBFBD>
; line 232 : 0x2000 - 0x47FF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 8 - 17) <20>փR<D683>s<EFBFBD>[
; line 233 : */
; line 234 : firm_duplicate( ( __far u8 * ) 0x5000,
; line 235 : FIRM_TOP );
$DGL 0,9
movw ax,#08H ; 8 ;[INF] 3, 1
push ax ;[INF] 1, 1
movw ax,#05000H ; 20480 ;[INF] 3, 1
clrw bc ;[INF] 1, 1
call !_firm_duplicate ;[INF] 3, 3
pop ax ;[INF] 1, 1
; line 236 :
; line 237 : // todo
; line 238 : // <20>@<40><><EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ALED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD><EFBFBD><EFBFBD>āA<C481>T<EFBFBD>[<5B>r<EFBFBD>X<EFBFBD><58>
; <20><><EFBFBD>ɂ<EFBFBD><C982>Ă<EFBFBD><C482>炤
; line 239 :
; line 240 : // <20><><EFBFBD>u<EFBFBD>[<5B>g
; line 241 : // <20>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD>͕s<CD95>v<EFBFBD>ł<EFBFBD><C582>I
; line 242 : FSL_SwapBootCluster();
$DGL 0,16
call !_FSL_SwapBootCluster ;[INF] 3, 3
; line 243 : // FSL_ForceReset( );
; line 244 : return ( ERR_SUCCESS );
$DGL 0,18
clrw bc ;[INF] 1, 1
; line 245 : }
$DGL 0,19
??ef_firm_restore:
ret ;[INF] 1, 6
??ee_firm_restore:
; line 246 :
; line 247 :
; line 248 :
; line 249 :
; line 250 : // ========================================================
; line 251 : static void FSL_Open( void )
; line 252 : {
_FSL_Open:
$DGL 1,105
??bf_FSL_Open:
; line 253 : /* save the configuration of the interrupt controller and se
; t */
; line 254 : #ifdef FSL_INT_BACKUP
; line 255 : fsl_MK0L_bak_u08 = MK0L; /* if (interrupt backup required
; ) */
; line 256 : fsl_MK0H_bak_u08 = MK0H; /* {
; */
; line 257 : fsl_MK1L_bak_u08 = MK1L; /*
; */
; line 258 : fsl_MK1H_bak_u08 = MK1H; /* save interrupt control
; ler */
; line 259 : fsl_MK2L_bak_u08 = MK2L; /* configuration
; */
; line 260 : fsl_MK2H_bak_u08 = MK2H; /*
; */
; line 261 : MK0L = FSL_MK0L_MASK; /*
; */
; line 262 : MK0H = FSL_MK0H_MASK; /*
; */
; line 263 : MK1L = FSL_MK1L_MASK; /* prepare interrupt cont
; roller */
; line 264 : MK1H = FSL_MK1H_MASK; /* for selfprogramming
; */
; line 265 : MK2L = FSL_MK2L_MASK; /*
; */
; line 266 : MK2H = FSL_MK2H_MASK; /* }
; */
; line 267 : #endif
; line 268 :
; line 269 : // <20><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD>H
; line 270 : // todo DMA<4D><41><EFBFBD>~<7E>߂<EFBFBD>
; line 271 : while( DST1 ){;}
$DGL 0,20
?L0035:
bf DRC1.0,$?L0036 ;[INF] 4, 5
??bb00_FSL_Open:
??eb00_FSL_Open:
br $?L0035 ;[INF] 2, 3
?L0036:
; line 272 : DEN1 = 0;
$DGL 0,21
clr1 DRC1.7 ;[INF] 3, 2
; line 273 :
; line 274 : MK0 = 0xFFFF;
$DGL 0,23
movw MK0,#0FFFFH ; -1 ;[INF] 4, 1
; line 275 : MK1 = 0xFFFF;
$DGL 0,24
movw MK1,#0FFFFH ; -1 ;[INF] 4, 1
; line 276 : MK2 = 0xFFFF;
$DGL 0,25
movw MK2,#0FFFFH ; -1 ;[INF] 4, 1
; line 277 :
; line 278 : FSL_FLMD0_HIGH; // <20>t<EFBFBD><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682><EFBFBD><EFBFBD><EFBFBD>
$DGL 0,27
??bb01_FSL_Open:
set1 BECTL.7 ;[INF] 3, 2
??eb01_FSL_Open:
; line 279 : }
$DGL 0,28
??ef_FSL_Open:
ret ;[INF] 1, 6
??ee_FSL_Open:
; line 280 :
; line 281 :
; line 282 :
; line 283 : /*--------------------------------------------------------------
; --------------------------------*/
; line 284 : /* leave the "user room" and restore previous conditions
; */
; line 285 : /*--------------------------------------------------------------
; --------------------------------*/
; line 286 : static void FSL_Close( void )
; line 287 : {
_FSL_Close:
$DGL 1,119
??bf_FSL_Close:
; line 288 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n<EFBFBD><6E><EFBFBD>H
; line 289 :
; line 290 : FSL_FLMD0_LOW; // <20>t<EFBFBD><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>C<EFBFBD>g<EFBFBD>v<EFBFBD><76><EFBFBD>e<EFBFBD>N<EFBFBD>g
$DGL 0,4
??bb00_FSL_Close:
clr1 BECTL.7 ;[INF] 3, 2
??eb00_FSL_Close:
; line 291 :
; line 292 : #ifdef FSL_INT_BACKUP
; line 293 : MK0L = fsl_MK0L_bak_u08; /* do{
; */
; line 294 : MK0H = fsl_MK0H_bak_u08; /* restore interrupt cont
; roller */
; line 295 : MK1L = fsl_MK1L_bak_u08; /* configuration
; */
; line 296 : MK1H = fsl_MK1H_bak_u08; /*
; */
; line 297 : MK2L = fsl_MK2L_bak_u08; /*
; */
; line 298 : MK2H = fsl_MK2H_bak_u08; /* }
; */
; line 299 : #endif
; line 300 : }
$DGL 0,14
??ef_FSL_Close:
ret ;[INF] 1, 6
??ee_FSL_Close:
; line 301 :
; line 302 :
; line 303 :
; line 304 : /* ========================================================
; line 305 : <20>@<40>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD><EFBFBD><EFBFBD>Ńt<C583>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>܂<EFBFBD><DC82>B
; line 306 : __far u8 * p_rom <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>̐擪<CC90>A<EFBFBD>h<EFBFBD><68><EFBFBD>X
; line 307 : block_dest <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>̐擪<CC90>u<EFBFBD><75><EFBFBD>b<EFBFBD>N
; line 308 :
; line 309 : <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>悤<EFBFBD><E682A4>my_FSL_Init<69><74><EFBFBD><EFBFBD><EFBFBD>炩<EFBFBD><E782A9><EFBFBD>ߎ<EFBFBD><DF8E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>K<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; <20>܂<EFBFBD><DC82>B
; line 310 : ======================================================== */
; line 311 : static err firm_duplicate( __far u8 * p_rom,
; line 312 : u8 block_dest )
; line 313 : {
_firm_duplicate:
$DGL 1,129
push hl ;[INF] 1, 1
push bc ;[INF] 1, 1
push ax ;[INF] 1, 1
subw sp,#06H ;[INF] 2, 1
movw hl,sp ;[INF] 3, 1
??bf_firm_duplicate:
; line 314 : u8 target_block;
; line 315 : u8 split_write_count; // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ւ<EFBFBD><D682>܂<EFBFBD><DC82>܏<EFBFBD><DC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ރJ<DE83>E
; <20><><EFBFBD>^
; line 316 :
; line 317 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݐ<EFBFBD><DD90>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD>
; line 318 : for( target_block = block_dest;
$DGL 0,6
mov a,[hl+16] ; block_dest ;[INF] 2, 1
mov [hl+5],a ; target_block ;[INF] 2, 1
?L0041:
; line 319 : target_block < block_dest + FIRM_SIZE;
$DGL 0,7
mov a,[hl+16] ; block_dest ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
addw ax,#0CH ; 12 ;[INF] 3, 1
movw bc,ax ;[INF] 1, 1
mov a,[hl+5] ; target_block ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
movw _@RTARG0,ax ;[INF] 2, 1
movw ax,bc ;[INF] 1, 1
call !@@iscmp ;[INF] 3, 3
bnc $?L0042 ;[INF] 2, 4
; line 320 : target_block += 1 )
; line 321 : {
??bb00_firm_duplicate:
; line 322 : WDT_Restart( );
$DGL 0,10
call !_WDT_Restart ;[INF] 3, 3
; line 323 : // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
; line 324 : while( FSL_BlankCheck( target_block ) != FSL_OK )
$DGL 0,12
?L0044:
mov a,[hl+5] ; target_block ;[INF] 2, 1
shrw ax,8 ;[INF] 2, 1
call !_FSL_BlankCheck ;[INF] 3, 3
cmp0 c ;[INF] 1, 1
bz $?L0045 ;[INF] 2, 4
; line 325 : {
??bb01_firm_duplicate:
; line 326 : FSL_Erase( target_block );
$DGL 0,14
call !bs_F0064 ;[INF] 3, 3
??eb01_firm_duplicate:
; line 327 : }
$DGL 0,15
br $?L0044 ;[INF] 2, 3
?L0045:
; line 328 :
; line 329 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݕ<EFBFBD><DD95>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD>
; line 330 : for( split_write_count = 0;
$DGL 0,18
mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1
?L0046:
; line 331 : split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM;
$DGL 0,19
mov a,[hl+4] ; split_write_count ;[INF] 2, 1
cmp a,#04H ; 4 ;[INF] 2, 1
bnc $?L0047 ;[INF] 2, 4
; line 332 : split_write_count += 1 )
; line 333 : {
??bb02_firm_duplicate:
; line 334 : u8 buffer_fill;
; line 335 : u8* p_buff;
; line 336 :
; line 337 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݃f<DD83>[<5B>^<5E><><EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@<40>ɂ<EFBFBD><C982>߂<EFBFBD>
; line 338 : buffer_fill = 0;
$DGL 0,26
mov [hl+3],#00H ; buffer_fill,0 ;[INF] 3, 1
; line 339 : p_buff = pool;
$DGL 0,27
movw ax,#loww (_pool) ;[INF] 3, 1
movw [hl],ax ; p_buff ;[INF] 1, 1
; line 340 : do
?L0049:
; line 341 : {
??bb03_firm_duplicate:
; line 342 : *p_buff = *p_rom;
$DGL 0,30
movw ax,[hl+6] ; p_rom ;[INF] 2, 1
movw de,ax ;[INF] 1, 1
mov a,[hl+8] ; p_rom ;[INF] 2, 1
mov ES,a ;[INF] 2, 1
mov a,ES:[de] ;[INF] 2, 2
mov c,a ;[INF] 1, 1
movw ax,[hl] ; p_buff ;[INF] 1, 1
movw de,ax ;[INF] 1, 1
mov a,c ;[INF] 1, 1
mov [de],a ;[INF] 1, 1
; line 343 : p_rom += 1;
$DGL 0,31
movw ax,[hl+6] ; p_rom ;[INF] 2, 1
incw ax ;[INF] 1, 1
movw [hl+6],ax ; p_rom ;[INF] 2, 1
; line 344 : p_buff += 1;
$DGL 0,32
incw [hl+0] ; p_buff ;[INF] 3, 2
; line 345 : buffer_fill +=1;
$DGL 0,33
inc [hl+3] ; buffer_fill ;[INF] 3, 2
??eb03_firm_duplicate:
; line 346 : }
; line 347 : while( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE )
; ;
$DGL 0,35
mov a,[hl+3] ; buffer_fill ;[INF] 2, 1
cmp0 a ;[INF] 1, 1
bnz $?L0049 ;[INF] 2, 4
; line 348 :
; line 349 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 350 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC
; K_SIZE
; line 351 : +
; line 352 : split_write_count *
; line 353 : SELF_UPDATE_BUFF_SIZE
; ),
; line 354 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE
; / SAM_WORD_SIZE ) )
; line 355 : != FSL_OK )
$DGL 0,43
movw ax,#040H ; 64 ;[INF] 3, 1
push ax ;[INF] 1, 1
call !bs_S0060 ;[INF] 3, 3
call !bs_F0061 ;[INF] 3, 3
pop ax ;[INF] 1, 1
cmp0 c ;[INF] 1, 1
bz $?L0052 ;[INF] 2, 4
; line 356 : {
??bb04_firm_duplicate:
; line 357 : FSL_Close( );
$DGL 0,45
call !_FSL_Close ;[INF] 3, 3
; line 358 : return ( ERR_ERR );
$DGL 0,46
onew bc ;[INF] 1, 1
br $?L0040 ;[INF] 2, 3
??eb04_firm_duplicate:
; line 359 : }
?L0052:
??eb02_firm_duplicate:
; line 360 : }
$DGL 0,48
inc [hl+4] ; split_write_count ;[INF] 3, 2
br $?L0046 ;[INF] 2, 3
?L0047:
; line 361 :
; line 362 : // 1<>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݊<EFBFBD><DD8A><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>d<EFBFBD><64><EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD><73>
; line 363 : while( FSL_IVerify( target_block ) != FSL_OK ){
$DGL 0,51
call !bs_F0063 ;[INF] 3, 3
bnz $?L0047 ;[INF] 2, 4
??bb05_firm_duplicate:
; line 364 : // todo
; line 365 : ;
??eb05_firm_duplicate:
; line 366 : }
??eb00_firm_duplicate:
; line 367 : }
$DGL 0,55
inc [hl+5] ; target_block ;[INF] 3, 2
br $?L0041 ;[INF] 2, 3
?L0042:
; line 368 : return( ERR_SUCCESS );
$DGL 0,56
clrw bc ;[INF] 1, 1
; line 369 :
; line 370 : }
?L0040:
$DGL 0,58
??ef_firm_duplicate:
addw sp,#0AH ;[INF] 2, 1
pop hl ;[INF] 1, 1
ret ;[INF] 1, 6
??ee_firm_duplicate:
; line 371 :
; line 372 :
; line 373 :
; line 374 : /* ========================================================
; line 375 : ======================================================== */
; line 376 : static err my_FSL_Init()
; line 377 : {
_my_FSL_Init:
$DGL 1,168
??bf_my_FSL_Init:
; line 378 : RTCE = 0;
$DGL 0,2
clr1 RTCC0.7 ;[INF] 3, 2
; line 379 :
; line 380 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682>O<EFBFBD><4F><EFBFBD><EFBFBD> //
; line 381 : DI( );
$DGL 0,5
di ;[INF] 3, 4
; line 382 : FSL_Open( ); // <20><><EFBFBD>荞<EFBFBD>݋֎~<7E>Ȃ<EFBFBD>
$DGL 0,6
call !_FSL_Open ;[INF] 3, 3
; line 383 :
; line 384 : FSL_Init( pool ); // <20><><EFBFBD>C<EFBFBD>u<EFBFBD><75><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD>荞<EFBFBD>ݒ<EFBFBD><DD92>f<EFBFBD>l<EFBFBD><6C>
; <20><><EFBFBD><EFBFBD>
$DGL 0,8
movw ax,#loww (_pool) ;[INF] 3, 1
call !_FSL_Init ;[INF] 3, 3
; line 385 : FSL_ModeCheck( ); // <20><><EFBFBD>C<EFBFBD>g<EFBFBD>v<EFBFBD><76><EFBFBD>e<EFBFBD>N<EFBFBD>g<EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD>B<EFBFBD><42><EFBFBD>s<EFBFBD><73><EFBFBD>邱
; <20>Ƃ<EFBFBD><C682>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
$DGL 0,9
call !_FSL_ModeCheck ;[INF] 3, 3
; line 386 :
; line 387 : return( ERR_SUCCESS );
$DGL 0,11
clrw bc ;[INF] 1, 1
; line 388 : }
$DGL 0,12
??ef_my_FSL_Init:
ret ;[INF] 1, 6
??ee_my_FSL_Init:
; line 389 :
; line 390 :
; line 391 : task_status_immed tski_mcu_reset()
; line 392 : {
_tski_mcu_reset:
$DGL 1,174
??bf_tski_mcu_reset:
; line 393 : // <20><><EFBFBD>ʂɍċN<C48B><4E>
; line 394 : my_FSL_Init();
$DGL 0,3
call !_my_FSL_Init ;[INF] 3, 3
; line 395 : FSL_Close( );
$DGL 0,4
call !_FSL_Close ;[INF] 3, 3
; line 396 : // FSL_SwapBootCluster();
; line 397 : FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
$DGL 0,6
call !_FSL_ForceReset ;[INF] 3, 3
; line 398 :
; line 399 : // <20>ی<EFBFBD><DB8C>H //
; line 400 : WDTE = 0xAA; // WDT<44>ōċN<C48B><4E><EFBFBD>i<EFBFBD>e<EFBFBD>X<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>j
$DGL 0,9
mov WDTE,#0AAH ; 170 ;[INF] 3, 1
; line 401 : return( ERR_SUCCESS ); // no reach
$DGL 0,10
clrw bc ;[INF] 1, 1
; line 402 : }
$DGL 0,11
??ef_tski_mcu_reset:
ret ;[INF] 1, 6
??ee_tski_mcu_reset:
LDR_CODL CSEG
@@BASE CSEG BASE
END
; *** Code Information ***
;
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c
;
; $FUNC firm_update(97)
; bc=(void)
; CODE SIZE= 227 bytes, CLOCK_SIZE= 287 clocks, STACK_SIZE= 16 bytes
;
; $CALL my_FSL_Init(102)
; bc=(void)
;
; $CALL firm_duplicate(109)
; bc=(pointer:ax,bc, int:[sp+4])
;
; $CALL FSL_Erase(118)
; bc=(unsigned int:ax)
;
; $CALL FSL_Erase(129)
; bc=(unsigned int:ax)
;
; $CALL WDT_Restart(140)
; void=(void)
;
; $CALL FSL_Write(162)
; bc=(unsigned long:ax,bc, int:[sp+4])
;
; $CALL FSL_SwapBootCluster(167)
; void=(void)
;
; $CALL FSL_IVerify(174)
; bc=(unsigned int:ax)
;
; $CALL FSL_InvertBootFlag(199)
; bc=(void)
;
; $CALL FSL_SwapBootCluster(200)
; void=(void)
;
; $CALL FSL_SwapBootCluster(210)
; void=(void)
;
; $FUNC firm_restore(227)
; bc=(void)
; CODE SIZE= 20 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 6 bytes
;
; $CALL my_FSL_Init(228)
; bc=(void)
;
; $CALL firm_duplicate(235)
; bc=(pointer:ax,bc, int:[sp+4])
;
; $CALL FSL_SwapBootCluster(242)
; void=(void)
;
; $FUNC FSL_Open(252)
; void=(void)
; CODE SIZE= 25 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 0 bytes
;
; $FUNC FSL_Close(287)
; void=(void)
; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes
;
; $FUNC firm_duplicate(313)
; bc=(pointer p_rom:ax,bc, unsigned char block_dest:[sp+4])
; CODE SIZE= 136 bytes, CLOCK_SIZE= 161 clocks, STACK_SIZE= 20 bytes
;
; $CALL WDT_Restart(322)
; void=(void)
;
; $CALL FSL_BlankCheck(324)
; bc=(unsigned int:ax)
;
; $CALL FSL_Erase(326)
; bc=(unsigned int:ax)
;
; $CALL FSL_Write(355)
; bc=(unsigned long:ax,bc, int:[sp+4])
;
; $CALL FSL_Close(357)
; void=(void)
;
; $CALL FSL_IVerify(363)
; bc=(unsigned int:ax)
;
; $FUNC my_FSL_Init(377)
; bc=(void)
; CODE SIZE= 20 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 4 bytes
;
; $CALL FSL_Open(382)
; void=(void)
;
; $CALL FSL_Init(384)
; bc=(pointer:ax)
;
; $CALL FSL_ModeCheck(385)
; bc=(void)
;
; $FUNC tski_mcu_reset(392)
; bc=(void)
; CODE SIZE= 14 bytes, CLOCK_SIZE= 17 clocks, STACK_SIZE= 4 bytes
;
; $CALL my_FSL_Init(394)
; bc=(void)
;
; $CALL FSL_Close(395)
; void=(void)
;
; $CALL FSL_ForceReset(397)
; void=(void)
; Target chip : uPD79F0104
; Device file : E1.00b
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