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https://github.com/rvtr/ctr_mcu.git
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6acd9cc0f6
・時計あわせで何もしなくて良い ・歩数計を止めている間のケアも不要 ・読み出し時、先頭に最終記録時刻[Hour]を付ける ・ログの一括クリア実装 歩数計ログ、自己アップデートに使っていた u8 pool[512] → u16 pool[256]に 歩数計でこちらの方が都合がよい 自己書き換えは影響受けず（一応チェック済） 電源投入時に、ロードスイッチの前に /resetをアサートしていたのをやめた。 意味がないので 互換性検証100115用にリリース git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@81 013db118-44a6-b54f-8bf7-843cb86687b1
246 lines
6.8 KiB
C
246 lines
6.8 KiB
C
#ifndef __vreg_ctr__
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#define __vreg_ctr__
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#include "config.h"
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#define REG_BIT_RTC_BLACKOUT 0b00000001
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#define REG_BIT__SYS_MODE0 0b01000000
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#define REG_BIT_MCU_FIRMBROKEN 0b10000000
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// VREG_C_STATUS,
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#define REG_BIT_LCD_POW ( 1 << 7 )
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#define REG_BIT_BL_U ( 1 << 6 )
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#define REG_BIT_BL_L ( 1 << 5 )
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#define REG_BIT_BATT_CHARGE ( 1 << 4 )
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#define REG_BIT_POW_SUPPLY ( 1 << 3 )
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// –¢Žg—p ( 1 << 2 )
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#define REG_BIT_ST_SHELL_OPEN ( 1 << 1 )
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// –¢Žg—p ( 1 << 0 )
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// VREG_C_STATUS_X
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// –¢Žg—p ( 1 << 6 )
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// –¢Žg—p ( 1 << 5 )
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// –¢Žg—p ( 1 << 4 )
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// –¢Žg—p ( 1 << 3 )
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// –¢Žg—p ( 1 << 2 )
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#define REG_BIT_ACCERO_ERR ( 1 << 1 )
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#define REG_BIT_GASGAUGE_ERR ( 1 << 0 )
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// VREG_C_IRQ0
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#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 7 )
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#define REG_BIT_SHELL_OPEN ( 1 << 6 )
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#define REG_BIT_SHELL_CLOSE ( 1 << 5 )
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#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
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#define REG_BIT_SW_POW_HOLD ( 1 << 3 )
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#define REG_BIT_SW_POW_CLICK ( 1 << 2 )
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#define REG_BIT_SW_HOME_HOLD ( 1 << 1 )
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#define REG_BIT_SW_HOME_CLICK ( 1 << 0 )
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// VREG_C_IRQ1
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#define REG_BIT_BT_CHG_START ( 1 << 7 )
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#define REG_BIT_BT_CHG_STOP ( 1 << 6 )
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#define REG_BIT_BT_REMAIN ( 1 << 5 )
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#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
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#define REG_BIT_ACC_ACK ( 1 << 3 )
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#define REG_BIT_RTC_ALARM ( 1 << 2 )
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#define REG_BIT_BT_DC_CONNECT ( 1 << 1 )
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#define REG_BIT_BT_DC_DISC ( 1 << 0 )
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// VREG_C_IRQ2
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#define REG_BIT_TWL_BL_U_ON ( 1 << 5 )
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#define REG_BIT_TWL_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_TWL_BL_L_ON ( 1 << 3 )
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#define REG_BIT_TWL_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_TWL_OFF_REQ ( 1 << 1 )
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#define REG_BIT_TWL_RESET_REQ ( 1 << 0 )
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// VREG_C_IRQ3
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#define REG_BIT_BL_U_ON ( 1 << 5 )
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#define REG_BIT_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_BL_L_ON ( 1 << 3 )
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#define REG_BIT_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_LCD_ON ( 1 << 1 )
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#define REG_BIT_LCD_OFF ( 1 << 0 )
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// ‚»‚Ì‚¤‚¿‚Ç‚±‚©‚É...
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//#define REG_BIT_VR_TUNE_CHANGE ( 1 << 7 )
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// VREG_C_COMMAND0
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//#define REG_BIT_CMD_LCD_ON ( 1 << 7 )
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//#define REG_BIT_CMD_LCD_OFF ( 1 << 6 )
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//#define REG_BIT_CMD_BL_ON ( 1 << 5 )
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//#define REG_BIT_CMD_BL_OFF ( 1 << 4 )
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#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
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#define REG_BIT_RESET2_REQ ( 1 << 2 )
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#define REG_BIT_RESET1_REQ ( 1 << 1 )
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#define REG_BIT_OFF_REQ ( 1 << 0 )
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// VREG_C_COMMAND1 (TWL‚ÉŠ„‚è<E2809A>ž‚Ý‚ð“ü‚ê‚é)
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// –¢Žg—p ( 1 << 7 )
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// –¢Žg—p ( 1 << 6 )
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#define REG_BIT_SEND_TWL_VOL_CLICK ( 1 << 5 )
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#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
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#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
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#define REG_BIT_SEND_TWL_OFF_DET ( 1 << 2 )
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#define REG_BIT_SEND_TWL_RESET_DET ( 1 << 1 )
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#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
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// VREG_C_COMMAND2 ‰t<E280B0>»ŠÖŒW
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#define REG_BIT_CMD_BL_U_ON ( 1 << 5 )
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#define REG_BIT_CMD_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_CMD_BL_L_ON ( 1 << 3 )
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#define REG_BIT_CMD_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_CMD_LCD_ON ( 1 << 1 )
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#define REG_BIT_CMD_LCD_OFF ( 1 << 0 )
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#define REG_BITS_CMD_BL ( REG_BIT_CMD_BL_U_ON | REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_ON | REG_BIT_CMD_BL_L_OFF )
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// <20>ªTWL‚É’Ê’m‚·‚éIRQƒŒƒWƒXƒ^
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#define REG_BIT_TWL_IRQ_PWSW_DET 0x08
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#define REG_BIT_TWL_IRQ_RESET 0x01
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#define REG_BIT_TWL_IRQ_OFF 0x02
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#define REG_BIT_TWL_IRQ_BT_LOW 0x20
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#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
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#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
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// CODEC<45>ã‚ÌPMIC NTR ‚Ì‘ã—<C3A3>ƒŒƒWƒXƒ^
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#define REG_BIT_TWL_REQ_OFF ( 1 << 6 )
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#define REG_BIT_TWL_REQ_BL_U ( 1 << 3 )
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#define REG_BIT_TWL_REQ_BL_L ( 1 << 2 )
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#define REG_BIT_TWL_REQ_RESET ( 1 << 0 )
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/*
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ƒeƒ“ƒvƒŒ
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#define REG_BIT_ ( 1 << 7 )
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#define REG_BIT_ ( 1 << 6 )
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#define REG_BIT_ ( 1 << 5 )
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#define REG_BIT_ ( 1 << 4 )
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#define REG_BIT_ ( 1 << 3 )
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#define REG_BIT_ ( 1 << 2 )
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#define REG_BIT_ ( 1 << 1 )
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#define REG_BIT_ ( 1 << 0 )
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*/
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/*============================================================================*/
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extern u8 vreg_ctr[];
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/*============================================================================*/
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enum VREG_C
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{ // –¢’è‹`ƒAƒhƒŒƒX‚Ö<E2809A>‘‚«<E2809A>ž‚ñ‚¾<E2809A>Û‚Ì“®<E2809C>ì‚Í•s’è
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VREG_C_MCU_VER_MAJOR = 0x00,
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VREG_C_MCU_VER_MINOR,
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VREG_C_MCU_STATUS,
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VREG_C_VCOM_T = 0x03,
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VREG_C_VCOM_B,
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VREG_C_DBG1 = 0x05,
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VREG_C_DBG2,
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VREG_C_DBG3,
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VREG_C_TUNE = 0x08,
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VREG_C_SND_VOL,
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VREG_C_BT_TEMP,
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VREG_C_BT_REMAIN,
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VREG_C_BT_REMAIN_FINE,
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VREG_C_BT_VOLTAGE,
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VREG_C_STATUS_1 = 0x0E,
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VREG_C_STATUS = 0x0F,
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VREG_C_IRQ0 = 0x10,
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VREG_C_IRQ1,
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VREG_C_IRQ2,
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VREG_C_IRQ3,
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VREG_C_IRQ4,
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VREG_C_IRQ_MASK0 = 0x18,
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VREG_C_IRQ_MASK1,
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VREG_C_IRQ_MASK2,
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VREG_C_IRQ_MASK3,
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VREG_C_IRQ_MASK4,
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VREG_C_COMMAND0 = 0x20,
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VREG_C_COMMAND1,
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VREG_C_COMMAND2,
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VREG_C_COMMAND3, // 'r' ‚Ń}ƒCƒRƒ“ƒŠƒZƒbƒg
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VREG_C_FREE0 = 0x24,
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VREG_C_FREE1,
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VREG_C_FREE2,
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VREG_C_FREE3,
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VREG_C_LED_BRIGHT = 0x28,
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VREG_C_LED_POW,
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VREG_C_LED_WIFI,
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VREG_C_LED_CAM,
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VREG_C_LED_TUNE,
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VREG_C_LED_NOTIFY,
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VREG_C_RTC_SEC = 0x30,
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VREG_C_RTC_MIN,
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VREG_C_RTC_HOUR,
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VREG_C_RTC_YOBI,
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VREG_C_RTC_DAY,
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VREG_C_RTC_MONTH,
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VREG_C_RTC_YEAR,
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VREG_C_RTC_COMP,
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VREG_C_RTC_ALARM_MIN = 0x38,
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VREG_C_RTC_ALARM_HOUR,
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VREG_C_RTC_ALARM_DAY,
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VREG_C_RTC_ALARM_MONTH,
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VREG_C_RTC_ALARM_YEAR,
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VREG_C_ACC_CONFIG = 0x40,
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VREG_C_ACC_R_ADRS,
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VREG_C_ACC_RESERVE,
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VREG_C_ACC_W_ADRS,
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VREG_C_ACC_W_BUF,
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VREG_C_ACC_XL = 0x45,
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VREG_C_ACC_XH,
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VREG_C_ACC_YL,
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VREG_C_ACC_YH,
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VREG_C_ACC_ZL,
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VREG_C_ACC_ZH,
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VREG_C_ACC_HOSU_L = 0x4B,
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VREG_C_ACC_HOSU_M,
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VREG_C_ACC_HOSU_H,
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VREG_C_ACC_HOSU_SETTING,
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VREG_C_ACC_HOSU_HIST = 0x4F,
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// VREG_C_AMBIENT_BRIGHTNESS = 0x60,
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VREG_C_ENDMARK_
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};
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/*
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VREG_C_PM_INFO, // –¢Žg—p
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VREG_C_BT_INFO, // –¢Žg—p
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*/
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/*============================================================================*/
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void vreg_ctr_init( );
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void vreg_ctr_write( u8 adrs, u8 data );
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u8 vreg_ctr_read( u8 phy_adrs );
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void vreg_ctr_after_read( u8 adrs );
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void set_irq( u8 irqreg, u8 irq_flg );
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#endif
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