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5e9ec34e61
ctr_mcu/trunk/vreg_ctr.h
fujita_ryohei 5e9ec34e61 V0.6 ベータ 
全ファイルをindentに通した
ほか、たくさん修正

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@12 013db118-44a6-b54f-8bf7-843cb86687b1
2009-10-19 11:16:14 +00:00

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#ifndef __vreg_ctr__
#define __vreg_ctr__
#include "config.h"
#if MCU_VER_MINOR >= 4
#define REG_BIT_RTC_BLACKOUT 0b00000001
#define REG_BIT__SYS_MODE0 0b01000000
#define REG_BIT_MCU_FIRMBROKEN 0b10000000
// VREG_C_IRQ0
#define REG_BIT_VR_TUNE_CHANGE ( 1 << 7 )
#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 6 )
#define REG_BIT_SW_TUNE_CLICK ( 1 << 5 )
#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
#define REG_BIT_SW_POW_HOLD ( 1 << 3 )
#define REG_BIT_SW_POW_CLICK ( 1 << 2 )
#define REG_BIT_SW_HOME_HOLD ( 1 << 1 )
#define REG_BIT_SW_HOME_CLICK ( 1 << 0 )
// VREG_C_IRQ1
#define REG_BIT_WDT_DET ( 1 << 5 )
#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
#define REG_BIT_ACC_ACK ( 1 << 3 )
#define REG_BIT_RTC_ALARM ( 1 << 2 )
#define REG_BIT_BT_REMAIN ( 1 << 1 )
// VREG_C_IRQ2
#define REG_BIT_BT_CHG_START ( 1 << 7 )
#define REG_BIT_BT_CHG_STOP ( 1 << 6 )
#define REG_BIT_BT_DC_CONNECT ( 1 << 5 )
#define REG_BIT_BT_DC_DISC ( 1 << 4 )
#define REG_BIT_EXTOPT_OPEN ( 1 << 3 )
#define REG_BIT_EXTOPT_LOCK ( 1 << 2 )
#define REG_BIT_SHELL_OPEN ( 1 << 1 )
#define REG_BIT_SHELL_CLOSE ( 1 << 0 )
// VREG_C_IRQ3
#define REG_BIT_TWL_BL_ON ( 1 << 7 )
#define REG_BIT_TWL_BL_OFF ( 1 << 6 )
#define REG_BIT_TWL_OFF_REQ ( 1 << 5 )
#define REG_BIT_TWL_RESET_REQ ( 1 << 4 )
#define REG_BIT_LCD_ON ( 1 << 3 )
#define REG_BIT_LCD_OFF ( 1 << 2 )
#define REG_BIT_BL_ON ( 1 << 1 )
#define REG_BIT_BL_OFF ( 1 << 0 )
// VREG_C_STATUS,
#define REG_BIT_LCD_POW ( 1 << 7 )
#define REG_BIT_BL ( 1 << 6 )
// #define REG_BIT_BATT_CHARGE_ERR ( 1 << 5 )
#define REG_BIT_BATT_CHARGE ( 1 << 4 )
#define REG_BIT_POW_SUPPLY ( 1 << 3 )
#define REG_BIT_ST_EXT_OPT_OPEN ( 1 << 2 )
#define REG_BIT_ST_SHELL_CLOSED ( 1 << 1 )
// VREG_C_COMMAND0
#define REG_BIT_CMD_LCD_ON ( 1 << 7 )
#define REG_BIT_CMD_LCD_OFF ( 1 << 6 )
#define REG_BIT_CMD_BL_ON ( 1 << 5 )
#define REG_BIT_CMD_BL_OFF ( 1 << 4 )
#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
#define REG_BIT_RESET2_REQ ( 1 << 2 )
#define REG_BIT_RESET1_REQ ( 1 << 1 )
#define REG_BIT_OFF_REQ ( 1 << 0 )
// VREG_C_COMMAND1
#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
#define REG_BIT_SEND_TWL_OFF_REQ ( 1 << 2 )
#define REG_BIT_SEND_TWL_RESET_REQ ( 1 << 1 )
#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
// VREG_C_WIFI_LED
enum
{
WIFI_LED_OFF = 0,
WIFI_LED_ON,
WIFI_LED_TXAUTO,
WIFI_LED_PTN0,
WIFI_LED_PTN1
};
// VREG_C_CAM_LED
enum
{
CAM_LED_OFF = 0,
CAM_LED_BLINK,
CAM_LED_ON,
CAM_LED_BY_TWL,
CAM_LED_ON_PLUSE,
CAM_LED_OFF_PLUSE
};
// TWL<57>ɑ<EFBFBD><C991><EFBFBD><EFBFBD>R<EFBFBD>}<7D><><EFBFBD>h
// command2
#define REG_BIT_TWL_CMD_PWSW_DET 0x01
#define REG_BIT_TWL_CMD_RESET 0x02
#define REG_BIT_TWL_CMD_OFF 0x04
#define REG_BIT_TWL_CMD_BT_LOW 0x08
#define REG_BIT_TWL_CMD_BT_EMPTY 0x10
#define REG_BIT_TWL_CMD_VOL_CHANGE 0x20
// <20><>TWL<57><4C>
#define REG_BIT_TWL_IRQ_PWSW_DET 0x08
#define REG_BIT_TWL_IRQ_RESET 0x01
#define REG_BIT_TWL_IRQ_OFF 0x02
#define REG_BIT_TWL_IRQ_BT_LOW 0x20
#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
// TWL<57><4C>SPI<50><49>PMIC<49>ɓ<EFBFBD><C993><EFBFBD><EFBFBD><EFBFBD><EFBFBD>R<EFBFBD>}<7D><><EFBFBD>h
#define REG_BIT_TWL_REQ_OFF_REQ ( 1 << 6 )
#define REG_BIT_TWL_REQ_RST_REQ ( 1 << 0 )
#define REG_BIT_TWL_REQ_BL ( 3 << 2 )
/*
<20>e<EFBFBD><65><EFBFBD>v<EFBFBD><76>
#define REG_BIT_ ( 1 << 7 )
#define REG_BIT_ ( 1 << 6 )
#define REG_BIT_ ( 1 << 5 )
#define REG_BIT_ ( 1 << 4 )
#define REG_BIT_ ( 1 << 3 )
#define REG_BIT_ ( 1 << 2 )
#define REG_BIT_ ( 1 << 1 )
#define REG_BIT_ ( 1 << 0 )
*/
/*============================================================================*/
extern u8 vreg_ctr[];
/*============================================================================*/
enum VREG_C
{ // <20><><EFBFBD><EFBFBD><EFBFBD>`<60>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>֏<EFBFBD><D68F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>񂾍ۂ̓<DB82><CC93><EFBFBD><EFBFBD>͕s<CD95><73>
VREG_C_MCU_VER_MAJOR = 0x00,
VREG_C_MCU_VER_MINOR,
VREG_C_MCU_STATUS,
VREG_C_VCOM_T = 0x03,
VREG_C_VCOM_B,
VREG_C_DBG1 = 0x05,
VREG_C_DBG2,
VREG_C_DBG3,
VREG_C_TUNE = 0x08,
VREG_C_SND_VOL,
VREG_C_BT_REMAIN,
VREG_C_BT_TEMP,
VREG_C_STATUS_X = 0x0E,
VREG_C_STATUS = 0x0F,
VREG_C_IRQ0 = 0x10,
VREG_C_IRQ1,
VREG_C_IRQ2,
VREG_C_IRQ3,
VREG_C_IRQ_MASK0 = 0x18,
VREG_C_IRQ_MASK1,
VREG_C_IRQ_MASK2,
VREG_C_IRQ_MASK3,
VREG_C_COMMAND0 = 0x20,
VREG_C_COMMAND1,
VREG_C_COMMAND2,
VREG_C_COMMAND3,
VREG_C_FREE0 = 0x24,
VREG_C_FREE1,
VREG_C_FREE2,
VREG_C_FREE3,
VREG_C_LED_BRIGHT = 0x28,
VREG_C_LED_POW,
VREG_C_LED_WIFI,
VREG_C_LED_CAM,
VREG_C_LED_TUNE,
VREG_C_RTC_SEC = 0x30,
VREG_C_RTC_MIN,
VREG_C_RTC_HOUR,
VREG_C_RTC_YOBI,
VREG_C_RTC_DAY,
VREG_C_RTC_MONTH,
VREG_C_RTC_YEAR,
VREG_C_RTC_COMP,
VREG_C_RTC_ALARM_MIN = 0x38,
VREG_C_RTC_ALARM_HOUR,
VREG_C_RTC_ALARM_DAY,
VREG_C_RTC_ALARM_MONTH,
VREG_C_RTC_ALARM_YEAR,
VREG_C_ACC_CONFIG = 0x40,
VREG_C_ACC_R_ADRS,
VREG_C_RESERVED5,
VREG_C_ACC_W_ADRS,
VREG_C_ACC_W_BUF,
VREG_C_ACC_XL = 0x45,
VREG_C_ACC_XH,
VREG_C_ACC_YL,
VREG_C_ACC_YH,
VREG_C_ACC_ZL,
VREG_C_ACC_ZH,
VREG_C_ACC_HOSU_L = 0x4B,
VREG_C_ACC_HOSU_M,
VREG_C_ACC_HOSU_H,
VREG_C_ACC_HOSU_HIST = 0x4E,
VREG_C_ENDMARK_
};
/*
VREG_C_PM_INFO, // <20><><EFBFBD>g<EFBFBD>p
VREG_C_BT_INFO, // <20><><EFBFBD>g<EFBFBD>p
*/
#else
<EFBFBD>E@"<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƕς<EFBFBD><EFBFBD>Ă<EFBFBD><EFBFBD>܂<EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂ŁA<EFBFBD><EFBFBD><EFBFBD>ł̃f<EFBFBD>B<EFBFBD><EFBFBD><EFBFBD>N<EFBFBD>g<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>g<EFBFBD>p<EFBFBD><EFBFBD><EFBFBD>ĉ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B"
#endif
/*============================================================================*/
void vreg_ctr_init( );
void vreg_ctr_write( u8 adrs, u8 data );
u8 vreg_ctr_read( u8 phy_adrs );
void vreg_ctr_after_read( u8 adrs );
#endif
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