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中途半端ではあるがいったんバックアップをかねてコミット git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@8 013db118-44a6-b54f-8bf7-843cb86687b1
197 lines
5.0 KiB
C
197 lines
5.0 KiB
C
#ifndef __vreg_ctr__
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#define __vreg_ctr__
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#define REG_BIT_RTC_BLACKOUT 0b00000001
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#define REG_BIT__SYS_MODE0 0b01000000
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#define REG_BIT_MCU_FIRMBROKEN 0b10000000
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// VREG_C_IRQ0
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#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 7 )
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#define REG_BIT_VR_TUNE_CHANGE ( 1 << 6 )
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#define REG_BIT_SW_TUNE_CLICK ( 1 << 5 )
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#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
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#define REG_BIT_SW_POW_HOLD ( 1 << 3 )
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#define REG_BIT_SW_POW_CLICK ( 1 << 2 )
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#define REG_BIT_SW_HOME_HOLD ( 1 << 1 )
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#define REG_BIT_SW_HOME_CLICK ( 1 << 0 )
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// VREG_C_IRQ1
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#define REG_BIT_TWL_OFF_REQ ( 1 << 7 )
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#define REG_BIT_TWL_RESET_REQ ( 1 << 6 )
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#define REG_BIT_WDT_DET ( 1 << 5 )
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#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
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#define REG_BIT_ACC_ACK ( 1 << 3 )
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#define REG_BIT_RTC_ALARM ( 1 << 2 )
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#define REG_BIT_BT_REMAIN ( 1 << 1 )
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#define REG_BIT_STAT_CHANGE ( 1 << 0 )
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// VREG_C_STATUS0,
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#define REG_BIT_BATT_CHARGE_ERR ( 1 << 5 )
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#define REG_BIT_BATT_CHARGE ( 1 << 4 )
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#define REG_BIT_POW_SUPPLY ( 1 << 3 )
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#define REG_BIT_EXT_OPT_LOCK ( 1 << 2 )
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#define REG_BIT_SHELL_CLOSE ( 1 << 1 )
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#define REG_BIT_BL ( 1 << 6 )
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#define REG_BIT_LCD_POW ( 1 << 7 )
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// VREG_C_COMMAND0
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#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
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#define REG_BIT_RESET2_REQ ( 1 << 2 )
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#define REG_BIT_RESET1_REQ ( 1 << 1 )
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#define REG_BIT_OFF_REQ ( 1 << 0 )
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#define REG_BIT_BL_ON ( 1 << 5 )
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#define REG_BIT_BL_OFF ( 1 << 4 )
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#define REG_BIT_LCD_ON ( 1 << 7 )
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#define REG_BIT_LCD_OFF ( 1 << 6 )
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// VREG_C_COMMAND1
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#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
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#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
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#define REG_BIT_SEND_TWL_OFF_REQ ( 1 << 2 )
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#define REG_BIT_SEND_TWL_RESET_REQ ( 1 << 1 )
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#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
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// VREG_C_WIFI_LED
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#define REG_BIT_WIFI_BLINK_ENA ( 1 << 1 )
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#define REG_BIT_WIFI_ON ( 1 << 0 )
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// command2
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#define REG_BIT_TWL_CMD_PWSW_DET 0x01
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#define REG_BIT_TWL_CMD_RESET 0x02
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#define REG_BIT_TWL_CMD_OFF 0x04
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#define REG_BIT_TWL_CMD_BT_LOW 0x08
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#define REG_BIT_TWL_CMD_BT_EMPTY 0x10
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#define REG_BIT_TWL_CMD_VOL_CHANGE 0x20
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// <20><>TWL<57><4C>
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#define REG_BIT_TWL_IRQ_PWSW_DET 0x80
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#define REG_BIT_TWL_IRQ_RESET 0x01
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#define REG_BIT_TWL_IRQ_OFF 0x02
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#define REG_BIT_TWL_IRQ_BT_LOW 0x20
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#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
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#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
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/*
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<20>e<EFBFBD><65><EFBFBD>v<EFBFBD><76>
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#define REG_BIT_ ( 1 << 7 )
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#define REG_BIT_ ( 1 << 6 )
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#define REG_BIT_ ( 1 << 5 )
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#define REG_BIT_ ( 1 << 4 )
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#define REG_BIT_ ( 1 << 3 )
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#define REG_BIT_ ( 1 << 2 )
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#define REG_BIT_ ( 1 << 1 )
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#define REG_BIT_ ( 1 << 0 )
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*/
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/*============================================================================*/
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extern u8 vreg_ctr[];
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/*============================================================================*/
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enum VREG_C{ // <20><><EFBFBD><EFBFBD><EFBFBD>`<60>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>֏<EFBFBD><D68F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ۂ̓<DB82><CC93><EFBFBD><EFBFBD>͕s<CD95><73>
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VREG_C_IRQ0,
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VREG_C_IRQ1,
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VREG_C_IRQ2,
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VREG_C_STATUS0,
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VREG_C_STATUS1,
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VREG_C_IRQ_MASK0,
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VREG_C_IRQ_MASK1,
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VREG_C_IRQ_MASK2,
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VREG_C_TUNE = 0x08,
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VREG_C_SND_VOL,
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VREG_C_BT_REMAIN,
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VREG_C_COMMAND0,
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VREG_C_COMMAND1,
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VREG_C_LED_BRIGHT,
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VREG_C_LED_POW_ILUMI,
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VREG_C_WIFI_LED,
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VREG_C_CAM_LED,
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VREG_C_MCU_VER_MAJOR = 0x11,
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VREG_C_MCU_VER_MINOR,
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VREG_C_MCU_STATUS,
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VREG_C_VCOM_T,
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VREG_C_VCOM_B,
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VREG_C_PM_INFO, // <20><><EFBFBD>g<EFBFBD>p
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VREG_C_BT_INFO, // <20><><EFBFBD>g<EFBFBD>p
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VREG_C_BT_TEMP,
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VREG_C_RESERVED1,
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VREG_C_RTC_SEC = 0x1A,
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VREG_C_RTC_MIN,
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VREG_C_RTC_HOUR,
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VREG_C_RTC_YOBI,
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VREG_C_RTC_DAY,
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VREG_C_RTC_MONTH,
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VREG_C_RTC_YEAR,
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VREG_C_RESERVED2, // <20><><EFBFBD>g<EFBFBD>p
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VREG_C_RTC_ALARM_MIN,
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VREG_C_RTC_ALARM_HOUR,
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VREG_C_RTC_ALARM_DAY,
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VREG_C_RTC_ALARM_MONTH,
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VREG_C_RTC_ALARM_YEAR,
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VREG_C_RTC_COMP,
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VREG_C_ACC_CONFIG_HOSU = 0x28,
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VREG_C_ACC_CONFIG,
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VREG_C_ACC_R_ADRS,
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VREG_C_RESERVED5,
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VREG_C_ACC_W_ADRS,
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VREG_C_ACC_W_BUF,
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VREG_C_ACC_XL,
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VREG_C_ACC_XH,
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VREG_C_ACC_YL,
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VREG_C_ACC_YH,
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VREG_C_ACC_ZL,
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VREG_C_ACC_ZH,
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VREG_C_ACC_HOSU_L = 0x34,
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VREG_C_ACC_HOSU_M,
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VREG_C_ACC_HOSU_H,
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VREG_C_ACC_HOSU_HIST,
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VREG_C_DIAG,
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VREG_C_FREE0 = 0x39,
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VREG_C_FREE1,
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VREG_C_FREE2,
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VREG_C_FREE3,
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VREG_C_DBG0,
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VREG_C_DBG1,
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VREG_C_DBG2,
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VREG_C_DBG3,
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VREG_C_ENDMARK_
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};
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/*============================================================================*/
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void vreg_ctr_init();
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void vreg_ctr_write( u8 adrs, u8 data );
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u8 vreg_ctr_read( u8 phy_adrs );
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void vreg_ctr_after_read( u8 adrs );
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void vreg_c_iic_release();
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#endif
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