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ctr_mcu/branches/0.10(X3)/self_flash.prn
N2232 dc469bd4c6 0.10のX3対応版を登録 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
2010-06-23 07:16:15 +00:00

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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\self_flash.asm
Para-file:
In-file: inter_asm\self_flash.asm
Obj-file: self_flash.rel
Prn-file: self_flash.prn
Assemble list
ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
2 2
3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no self_flash.c
6 6 ; In-file : self_flash.c
7 7 ; Asm-file : inter_asm\self_flash.asm
8 8 ; Para-file :
9 9
10 10 $PROCESSOR(9F0104)
11 11 $DEBUG
12 12 $NODEBUGA
13 13 $KANJICODE SJIS
14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
15 15
16 16 $DGS FIL_NAM, .file, 0B4H, 0FFFEH, 03FH, 067H, 01H, 00H
17 17 $DGS AUX_FIL, self_flash.c
18 18 $DGS MOD_NAM, self_flash, 00H, 0FFFEH, 00H, 077H, 00H, 00H
19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
35 35 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
36 36 $DGS AUX_TAG, 01H, 019H
37 37 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
38 38 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
39 39 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
40 40 $DGS AUX_EOS, 013H, 01H
41 41 $DGS LAB_SYM, bs_F0064, U, U, 00H, 06H, 00H, 00H
42 42 $DGS LAB_SYM, es_F0064, U, U, 00H, 06H, 00H, 00H
43 43 $DGS LAB_SYM, bs_S0062, U, U, 00H, 06H, 00H, 00H
44 44 $DGS LAB_SYM, es_S0062, U, U, 00H, 06H, 00H, 00H
45 45 $DGS LAB_SYM, bs_F0063, U, U, 00H, 06H, 00H, 00H
46 46 $DGS LAB_SYM, es_F0063, U, U, 00H, 06H, 00H, 00H
47 47 $DGS LAB_SYM, bs_F0061, U, U, 00H, 06H, 00H, 00H
48 48 $DGS LAB_SYM, es_F0061, U, U, 00H, 06H, 00H, 00H
49 49 $DGS LAB_SYM, bs_S0060, U, U, 00H, 06H, 00H, 00H
50 50 $DGS LAB_SYM, es_S0060, U, U, 00H, 06H, 00H, 00H
51 51 $DGS GLV_SYM, _firm_update, U, U, 0CH, 026H, 01H, 02H
52 52 $DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H
53 53 $DGS BEG_FUN, ??bf_firm_update, U, U, 00H, 065H, 01H, 00H
54 54 $DGS AUX_BEG, 061H, 06H, 029H
55 55 $DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H
56 56 $DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H
57 57 $DGS BEG_BLK, ??bb00_firm_update, U, U, 00H, 064H, 01H, 00H
58 58 $DGS AUX_BEG, 015H, 00H, 02DH
59 59 $DGS END_BLK, ??eb00_firm_update, U, U, 00H, 064H, 01H, 00H
60 60 $DGS AUX_END, 017H
61 61 $DGS BEG_BLK, ??bb01_firm_update, U, U, 00H, 064H, 01H, 00H
62 62 $DGS AUX_BEG, 01FH, 00H, 02FH
63 63 $DGS BEG_BLK, ??bb02_firm_update, U, U, 00H, 064H, 01H, 00H
64 64 $DGS AUX_BEG, 028H, 00H, 035H
65 65 $DGS AUT_VAR, _p_buffer, 02H, 0FFFFH, 0CH, 01H, 01H, 01H
66 66 $DGS AUX_STR, 00H, 029H, 02H, 00H, 00H, 00H, 00H, 01H
67 67 $DGS AUT_VAR, _buffer_fill, 01H, 0FFFFH, 0CH, 01H, 01H, 00H
68 68 $DGS AUX_STR, 00H, 02AH, 01H, 00H, 00H, 00H, 00H, 00H
69 69 $DGS BEG_BLK, ??bb03_firm_update, U, U, 00H, 064H, 01H, 00H
70 70 $DGS AUX_BEG, 030H, 00H, 037H
71 71 $DGS BEG_BLK, ??bb04_firm_update, U, U, 00H, 064H, 01H, 00H
72 72 $DGS AUX_BEG, 031H, 00H, 03DH
73 73 $DGS END_BLK, ??eb04_firm_update, U, U, 00H, 064H, 01H, 00H
74 74 $DGS AUX_END, 031H
75 75 $DGS END_BLK, ??eb03_firm_update, U, U, 00H, 064H, 01H, 00H
76 76 $DGS AUX_END, 037H
77 77 $DGS BEG_BLK, ??bb05_firm_update, U, U, 00H, 064H, 01H, 00H
78 78 $DGS AUX_BEG, 043H, 00H, 043H
79 79 $DGS END_BLK, ??eb05_firm_update, U, U, 00H, 064H, 01H, 00H
80 80 $DGS AUX_END, 04AH
81 81 $DGS END_BLK, ??eb02_firm_update, U, U, 00H, 064H, 01H, 00H
82 82 $DGS AUX_END, 04CH
83 83 $DGS BEG_BLK, ??bb06_firm_update, U, U, 00H, 064H, 01H, 00H
84 84 $DGS AUX_BEG, 04EH, 00H, 047H
85 85 $DGS END_BLK, ??eb06_firm_update, U, U, 00H, 064H, 01H, 00H
86 86 $DGS AUX_END, 051H
87 87 $DGS BEG_BLK, ??bb07_firm_update, U, U, 00H, 064H, 01H, 00H
88 88 $DGS AUX_BEG, 054H, 00H, 04DH
89 89 $DGS END_BLK, ??eb07_firm_update, U, U, 00H, 064H, 01H, 00H
90 90 $DGS AUX_END, 056H
91 91 $DGS END_BLK, ??eb01_firm_update, U, U, 00H, 064H, 01H, 00H
92 92 $DGS AUX_END, 057H
93 93 $DGS BEG_BLK, ??bb08_firm_update, U, U, 00H, 064H, 01H, 00H
94 94 $DGS AUX_BEG, 05CH, 00H, 053H
95 95 $DGS AUT_VAR, _i, 03H, 0FFFFH, 0CH, 01H, 01H, 00H
96 96 $DGS AUX_STR, 00H, 05DH, 01H, 00H, 00H, 00H, 00H, 00H
97 97 $DGS AUT_VAR, _comp, 02H, 0FFFFH, 0CH, 01H, 01H, 00H
98 98 $DGS AUX_STR, 00H, 05EH, 01H, 00H, 00H, 00H, 00H, 00H
99 99 $DGS BEG_BLK, ??bb09_firm_update, U, U, 00H, 064H, 01H, 00H
100 100 $DGS AUX_BEG, 062H, 00H, 057H
101 101 $DGS END_BLK, ??eb09_firm_update, U, U, 00H, 064H, 01H, 00H
102 102 $DGS AUX_END, 064H
103 103 $DGS BEG_BLK, ??bb0A_firm_update, U, U, 00H, 064H, 01H, 00H
104 104 $DGS AUX_BEG, 066H, 00H, 05BH
105 105 $DGS END_BLK, ??eb0A_firm_update, U, U, 00H, 064H, 01H, 00H
106 106 $DGS AUX_END, 06CH
107 107 $DGS BEG_BLK, ??bb0B_firm_update, U, U, 00H, 064H, 01H, 00H
108 108 $DGS AUX_BEG, 06EH, 00H, 00H
109 109 $DGS END_BLK, ??eb0B_firm_update, U, U, 00H, 064H, 01H, 00H
110 110 $DGS AUX_END, 075H
111 111 $DGS END_BLK, ??eb08_firm_update, U, U, 00H, 064H, 01H, 00H
112 112 $DGS AUX_END, 076H
113 113 $DGS END_FUN, ??ef_firm_update, U, U, 00H, 065H, 01H, 00H
114 114 $DGS AUX_END, 077H
115 115 $DGS GLV_SYM, _firm_restore, U, U, 0CH, 026H, 01H, 02H
116 116 $DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H
117 117 $DGS BEG_FUN, ??bf_firm_restore, U, U, 00H, 065H, 01H, 00H
118 118 $DGS AUX_BEG, 0E3H, 00H, 069H
119 119 $DGS END_FUN, ??ef_firm_restore, U, U, 00H, 065H, 01H, 00H
120 120 $DGS AUX_END, 013H
121 121 $DGS STA_SYM, _FSL_Open, U, U, 01H, 03H, 01H, 02H
122 122 $DGS AUX_FUN, 00H, U, U, 077H, 00H, 00H
123 123 $DGS BEG_FUN, ??bf_FSL_Open, U, U, 00H, 065H, 01H, 00H
124 124 $DGS AUX_BEG, 0FCH, 00H, 06DH
125 125 $DGS BEG_BLK, ??bb00_FSL_Open, U, U, 00H, 064H, 01H, 00H
126 126 $DGS AUX_BEG, 014H, 00H, 071H
127 127 $DGS END_BLK, ??eb00_FSL_Open, U, U, 00H, 064H, 01H, 00H
128 128 $DGS AUX_END, 014H
129 129 $DGS BEG_BLK, ??bb01_FSL_Open, U, U, 00H, 064H, 01H, 00H
130 130 $DGS AUX_BEG, 01BH, 00H, 00H
131 131 $DGS END_BLK, ??eb01_FSL_Open, U, U, 00H, 064H, 01H, 00H
132 132 $DGS AUX_END, 01BH
133 133 $DGS END_FUN, ??ef_FSL_Open, U, U, 00H, 065H, 01H, 00H
134 134 $DGS AUX_END, 01CH
135 135 $DGS STA_SYM, _FSL_Close, U, U, 01H, 03H, 01H, 02H
136 136 $DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H
137 137 $DGS BEG_FUN, ??bf_FSL_Close, U, U, 00H, 065H, 01H, 00H
138 138 $DGS AUX_BEG, 011FH, 00H, 07BH
139 139 $DGS BEG_BLK, ??bb00_FSL_Close, U, U, 00H, 064H, 01H, 00H
140 140 $DGS AUX_BEG, 04H, 00H, 00H
141 141 $DGS END_BLK, ??eb00_FSL_Close, U, U, 00H, 064H, 01H, 00H
142 142 $DGS AUX_END, 04H
143 143 $DGS END_FUN, ??ef_FSL_Close, U, U, 00H, 065H, 01H, 00H
144 144 $DGS AUX_END, 0EH
145 145 $DGS STA_SYM, _firm_duplicate, U, U, 0CH, 03H, 01H, 02H
146 146 $DGS AUX_FUN, 00H, U, U, 0A8H, 00H, 00H
147 147 $DGS BEG_FUN, ??bf_firm_duplicate, U, U, 00H, 065H, 01H, 00H
148 148 $DGS AUX_BEG, 0139H, 0AH, 08AH
149 149 $DGS FUN_ARG, _p_rom, 06H, 0FFFFH, 0CH, 09H, 01H, 01H
150 150 $DGS AUX_STR, 00H, 00H, 04H, 00H, 00H, 00H, 00H, 02H
151 151 $DGS FUN_ARG, _block_dest, 010H, 0FFFFH, 0CH, 09H, 00H, 00H
152 152 $DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H
153 153 $DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H
154 154 $DGS BEG_BLK, ??bb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H
155 155 $DGS AUX_BEG, 09H, 00H, 08CH
156 156 $DGS BEG_BLK, ??bb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H
157 157 $DGS AUX_BEG, 0DH, 00H, 090H
158 158 $DGS END_BLK, ??eb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H
159 159 $DGS AUX_END, 0FH
160 160 $DGS BEG_BLK, ??bb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H
161 161 $DGS AUX_BEG, 015H, 00H, 096H
162 162 $DGS AUT_VAR, _buffer_fill, 03H, 0FFFFH, 0CH, 01H, 01H, 00H
163 163 $DGS AUX_STR, 00H, 016H, 01H, 00H, 00H, 00H, 00H, 00H
164 164 $DGS AUT_VAR, _p_buff, 00H, 0FFFFH, 0CH, 01H, 01H, 01H
165 165 $DGS AUX_STR, 00H, 017H, 02H, 00H, 00H, 00H, 00H, 01H
166 166 $DGS BEG_BLK, ??bb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H
167 167 $DGS AUX_BEG, 01DH, 00H, 09AH
168 168 $DGS END_BLK, ??eb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H
169 169 $DGS AUX_END, 022H
170 170 $DGS BEG_BLK, ??bb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H
171 171 $DGS AUX_BEG, 02CH, 00H, 0A0H
172 172 $DGS END_BLK, ??eb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H
173 173 $DGS AUX_END, 02FH
174 174 $DGS END_BLK, ??eb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H
175 175 $DGS AUX_END, 030H
176 176 $DGS BEG_BLK, ??bb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H
177 177 $DGS AUX_BEG, 033H, 00H, 00H
178 178 $DGS END_BLK, ??eb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H
179 179 $DGS AUX_END, 036H
180 180 $DGS END_BLK, ??eb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H
181 181 $DGS AUX_END, 037H
182 182 $DGS END_FUN, ??ef_firm_duplicate, U, U, 00H, 065H, 01H, 00H
183 183 $DGS AUX_END, 03AH
184 184 $DGS STA_SYM, _my_FSL_Init, U, U, 0CH, 03H, 01H, 02H
185 185 $DGS AUX_FUN, 00H, U, U, 0AEH, 00H, 00H
186 186 $DGS BEG_FUN, ??bf_my_FSL_Init, U, U, 00H, 065H, 01H, 00H
187 187 $DGS AUX_BEG, 0179H, 00H, 0AEH
188 188 $DGS END_FUN, ??ef_my_FSL_Init, U, U, 00H, 065H, 01H, 00H
189 189 $DGS AUX_END, 0CH
190 190 $DGS GLV_SYM, _tski_mcu_reset, U, U, 0AH, 026H, 01H, 02H
191 191 $DGS AUX_FUN, 013H, U, U, 0B4H, 00H, 00H
192 192 $DGS BEG_FUN, ??bf_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H
193 193 $DGS AUX_BEG, 0188H, 00H, 0B4H
194 194 $DGS END_FUN, ??ef_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H
195 195 $DGS AUX_END, 0BH
196 196 $DGS GLV_SYM, _fsl_fx_MHz_u08, U, U, 0500CH, 026H, 00H, 00H
197 197 $DGS GLV_SYM, _fsl_low_voltage_u08, U, U, 0500CH, 026H, 00H, 00H
198 198 $DGS GLV_SYM, _FSL_Erase, U, U, 0CH, 02H, 01H, 02H
199 199 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
200 200 $DGS GLV_SYM, _FSL_IVerify, U, U, 0CH, 02H, 01H, 02H
201 201 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
202 202 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
203 203 $DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H
204 204 $DGS GLV_SYM, _FSL_Write, U, U, 0CH, 02H, 01H, 02H
205 205 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
206 206 $DGS GLV_SYM, _pool, U, U, 0DH, 02H, 01H, 03H
207 207 $DGS AUX_STR, 00H, 00H, 02H, 01H, 00H, 00H, 00H, 00H
208 208 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
209 209 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
210 210 $DGS GLV_SYM, _FSL_SwapBootCluster, U, U, 01H, 02H, 01H, 02H
211 211 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
212 212 $DGS GLV_SYM, _FSL_InvertBootFlag, U, U, 0CH, 02H, 01H, 02H
213 213 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
214 214 $DGS GLV_SYM, @@iscmp, U, U, 00H, 02H, 00H, 00H
215 215 $DGS GLV_SYM, _FSL_BlankCheck, U, U, 0CH, 02H, 01H, 02H
216 216 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
217 217 $DGS GLV_SYM, _FSL_Init, U, U, 0CH, 02H, 01H, 02H
218 218 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
219 219 $DGS GLV_SYM, _FSL_ModeCheck, U, U, 0CH, 02H, 01H, 02H
220 220 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
221 221 $DGS GLV_SYM, _FSL_ForceReset, U, U, 01H, 02H, 01H, 02H
222 222 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
223 223
224 224 EXTRN _FSL_Erase
225 225 EXTRN _FSL_IVerify
226 226 EXTRN _@RTARG0
227 227 EXTRN _@RTARG2
228 228 EXTRN _FSL_Write
229 229 EXTRN _pool
230 230 EXTRN _WDT_Restart
231 231 EXTRN _FSL_SwapBootCluster
232 232 EXTRN _FSL_InvertBootFlag
233 233 EXTRN @@iscmp
234 234 EXTRN _FSL_BlankCheck
235 235 EXTRN _FSL_Init
236 236 EXTRN _FSL_ModeCheck
237 237 EXTRN _FSL_ForceReset
238 238 PUBLIC _fsl_fx_MHz_u08
239 239 PUBLIC _fsl_low_voltage_u08
240 240 PUBLIC _firm_update
241 241 PUBLIC _firm_restore
242 242 PUBLIC _tski_mcu_reset
243 243
244 244 ----- @@BITS BSEG
245 245
246 246 ----- @@CNST CSEG MIRRORP
247 247 00000 08 _fsl_fx_MHz_u08: DB 08H ; 8
248 248 00001 01 _fsl_low_voltage_u08: DB 01H ; 1
249 249
250 250 ----- @@R_INIT CSEG UNIT64KP
251 251
252 252 ----- @@INIT DSEG BASEP
253 253
254 254 ----- @@DATA DSEG BASEP
255 255
256 256 ----- @@R_INIS CSEG UNIT64KP
257 257
258 258 ----- @@INIS DSEG SADDRP
259 259
260 260 ----- @@DATS DSEG SADDRP
261 261
262 262 ----- LDR_CNSL CSEG PAGE64KP
263 263
264 264 ----- @@RLINIT CSEG UNIT64KP
265 265
266 266 ----- @@INITL DSEG UNIT64KP
267 267
268 268 ----- @@DATAL DSEG UNIT64KP
269 269
270 270 ----- @@CALT CSEG CALLT0
271 271
272 272 ; Sub-Routines created by CC78K0R
273 273
274 274 ----- LDR_CODE CSEG BASE
275 275 00000 bs_F0064:
276 276 00000 8C05 mov a,[hl+5] ;[INF] 2, 1
277 277 00002 318E shrw ax,8 ;[INF] 2, 1
278 278 00004 RED0000 br !_FSL_Erase ;[INF] 3, 3
279 279 00007 es_F0064:
280 280
281 281 ----- LDR_CODE CSEG BASE
282 282 00007 bs_S0062:
283 283 00007 C7 push hl ;[INF] 1, 1
284 284 00008 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1
285 285 0000B 7184 mov1 CY,[hl].0 ;[INF] 2, 1
286 286 0000D C6 pop hl ;[INF] 1, 1
287 287 0000E D7 ret ;[INF] 1, 6
288 288 0000F es_S0062:
289 289
290 290 ----- LDR_CODE CSEG BASE
291 291 0000F bs_F0063:
292 292 0000F 8C05 mov a,[hl+5] ;[INF] 2, 1
293 293 00011 318E shrw ax,8 ;[INF] 2, 1
294 294 00013 RFD0000 call !_FSL_IVerify ;[INF] 3, 3
295 295 00016 D2 cmp0 c ;[INF] 1, 1
296 296 00017 D7 ret ;[INF] 1, 6
297 297 00018 es_F0063:
298 298
299 299 ----- LDR_CODE CSEG BASE
300 300 00018 bs_F0061:
301 301 00018 RBD00 movw _@RTARG0,ax ;[INF] 2, 1
302 302 0001A 31FF sarw ax,15 ;[INF] 2, 1
303 303 0001C RBD00 movw _@RTARG2,ax ;[INF] 2, 1
304 304 0001E RDA00 movw bc,_@RTARG2 ;[INF] 2, 1
305 305 00020 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1
306 306 00022 RED0000 br !_FSL_Write ;[INF] 3, 3
307 307 00025 es_F0061:
308 308
309 309 ----- LDR_CODE CSEG BASE
310 310 00025 bs_S0060:
311 311 00025 8C05 mov a,[hl+5] ;[INF] 2, 1
312 312 00027 318E shrw ax,8 ;[INF] 2, 1
313 313 00029 31AD shlw ax,10 ;[INF] 2, 1
314 314 0002B 12 movw bc,ax ;[INF] 1, 1
315 315 0002C 8C04 mov a,[hl+4] ;[INF] 2, 1
316 316 0002E 318E shrw ax,8 ;[INF] 2, 1
317 317 00030 318D shlw ax,8 ;[INF] 2, 1
318 318 00032 03 addw ax,bc ;[INF] 1, 1
319 319 00033 D7 ret ;[INF] 1, 6
320 320 00034 es_S0060:
321 321
322 322 ; *** Sub-Routine Information ***
323 323 ;
324 324 ; $SUB bs_S0060
325 325 ; CODE SIZE= 15 bytes
326 326 ;
327 327 ; $SUB bs_F0061
328 328 ; CODE SIZE= 13 bytes
329 329 ;
330 330 ; $SUB bs_S0062
331 331 ; CODE SIZE= 8 bytes
332 332 ;
333 333 ; $SUB bs_F0063
334 334 ; CODE SIZE= 9 bytes
335 335 ;
336 336 ; $SUB bs_F0064
337 337 ; CODE SIZE= 7 bytes
338 338
339 339 ; End of Sub-Routines
340 340
341 341 ; line 1 : /* ========================================================
342 342 ; line 2 : <20><><EFBFBD>ȃA<C883>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^
343 343 ; line 3 : ======================================================== */
344 344 ; line 4 : #pragma SFR
345 345 ; line 5 : #pragma di
346 346 ; line 6 : #pragma ei
347 347 ; line 7 : #pragma nop
348 348 ; line 8 : #pragma stop
349 349 ; line 9 : #pragma halt
350 350 ; line 10 :
351 351 ; line 11 :
352 352 ; line 12 : #include "incs_loader.h"
353 353 ; line 13 :
354 354 ; line 14 : #include <fsl.h>
355 355 ; line 15 : #include "fsl_user.h"
356 356 ; line 16 : #include "i2c_ctr.h"
357 357 ; line 17 :
358 358 ; line 18 :
359 359 ; line 19 :
360 360 ; line 20 : // ========================================================
361 361 ; line 21 : const u8 fsl_fx_MHz_u08 = 8;
362 362 ; line 22 : const u8 fsl_low_voltage_u08 = 1;
363 363 ; line 23 :
364 364 ; line 24 :
365 365 ; line 25 : // <20><><EFBFBD>ȃt<C883><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD>[<5B>^
366 366 ; line 26 : #define SAM_BLOCK_SIZE 1024
367 367 ; line 27 : #define SELF_UPDATE_BUFF_SIZE 256
368 368 ; line 28 : #define SELF_UPDATE_SPLIT_WRITE_NUM ( SAM_BLOCK_SIZE / SELF_U
369 369 ; PDATE_BUFF_SIZE )
370 370 ; line 29 : #define SAM_WORD_SIZE 4
371 371 ; line 30 :
372 372 ; line 31 : // <20><><EFBFBD>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ԍ<EFBFBD><D48D>i1<69>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E>
373 373 ; 1kB<6B>j
374 374 ; line 32 : #define INACTIVE_BOOTSECT_TOP 4
375 375 ; line 33 : #define FIRM_TOP 8
376 376 ; line 34 : #define FIRM_SIZE 12
377 377 ; line 35 : #define UPDATE_BLOCK_LAST ( FIRM_TOP + FIRM_SIZE - 1
378 378 ; )
379 379 ; line 36 :
380 380 ; line 37 :
381 381 ; line 38 : #ifdef _MCU_BSR_
382 382 ; line 39 :
383 383 ; line 40 :
384 384 ; line 41 : #define ACKD ACKD1
385 385 ; line 42 : #define ACKE ACKE1
386 386 ; line 43 : #define COI COI1
387 387 ; line 44 : #define IICAEN IICA1EN
388 388 ; line 45 : #define IICAPR0 IICAPR10
389 389 ; line 46 : #define IICRSV IICRSV1
390 390 ; line 47 : #define IICA IICA1
391 391 ; line 48 : #define IICAIF IICAIF1
392 392 ; line 49 : #define IICAMK IICAMK1
393 393 ; line 50 : #define IICAPR1 IICAPR11
394 394 ; line 51 : #define IICCTL0 IICCTL01
395 395 ; line 52 : #define IICE IICE1
396 396 ; line 53 : #define IICF IICF1
397 397 ; line 54 : #define IICS IICS1
398 398 ; line 55 : #define IICWH IICWH1
399 399 ; line 56 : #define IICWL IICWL1
400 400 ; line 57 : #define LREL LREL1
401 401 ; line 58 : #define SPD SPD1
402 402 ; line 59 : #define SPIE SPIE1
403 403 ; line 60 : #define STCEN STCEN1
404 404 ; line 61 : #define STD STD1
405 405 ; line 62 : #define SVA SVA1
406 406 ; line 63 : #define WREL WREL1
407 407 ; line 64 : #define WTIM WTIM1
408 408 ; line 65 : #endif
409 409 ; line 66 :
410 410 ; line 67 :
411 411 ; line 68 :
412 412 ; line 69 : // ========================================================
413 413 ; line 70 : static void FSL_Open( void );
414 414 ; line 71 : static void FSL_Close( void );
415 415 ; line 72 : err firm_restore( );
416 416 ; line 73 :
417 417 ; line 74 : static err my_FSL_Init();
418 418 ; line 75 : static err firm_duplicate( __far u8 * p_rom, u8 block_dest );
419 419 ; line 76 :
420 420 ; line 77 :
421 421 ; line 78 :
422 422 ; line 79 : // ========================================================
423 423 ; line 80 : extern u16 pool[];
424 424 ; line 81 :
425 425 ; line 82 :
426 426 ; line 83 : // 0.D<>ȍ~ <20>V<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD><EFBFBD>
427 427 ; line 84 : #define N_MGC_L 0x1FF6
428 428 ; line 85 : #define N_MGC_T 0x4FF6
429 429 ; line 86 :
430 430 ; line 87 :
431 431 ; line 88 :
432 432 ; line 89 : /* ========================================================
433 433 ; line 90 : I2C<32>Ŏ<EFBFBD><C58E>M<EFBFBD><4D><EFBFBD>āA
434 434 ; line 91 : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݁A
435 435 ; line 92 : <20>`<60>F<EFBFBD>b<EFBFBD>NOK<4F>@<40><><EFBFBD>@<40>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>ɐ؂<C990><D882>ւ<EFBFBD><D682>čċN<C48B><4E>
436 436 ; line 93 : <20>@<40>@<40>@<40>@NG<4E>@<40><><EFBFBD>@<40><><EFBFBD>i<EFBFBD><69><EFBFBD>j<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>ɖ߂<C996><DF82>čċN<C48B><4E>
437 437 ; line 94 : <20>i<EFBFBD><69><EFBFBD>̊֐<CC8A><D690><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͖߂<CD96><DF82>܂<EFBFBD><DC82><EFBFBD><EFBFBD>j
438 438 ; line 95 : ======================================================== */
439 439 ; line 96 : err firm_update( )
440 440 ; line 97 : {
441 441
442 442 ----- LDR_CODE CSEG BASE
443 443 00034 _firm_update:
444 444 $DGL 1,35
445 445 00034 C7 push hl ;[INF] 1, 1
446 446 00035 2006 subw sp,#06H ;[INF] 2, 1
447 447 00037 FBF8FF movw hl,sp ;[INF] 3, 1
448 448 0003A ??bf_firm_update:
449 449 ; line 98 : u8 target_block;
450 450 ; line 99 : u8 split_write_count; // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ւ<EFBFBD><D682>܂<EFBFBD><DC82>܏<EFBFBD><DC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ރJ<DE83>E
451 451 ; <20><><EFBFBD>^
452 452 ; line 100 :
453 453 ; line 101 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682>O<EFBFBD><4F><EFBFBD><EFBFBD> /////////////////////////////////////
454 454 ; line 102 : my_FSL_Init();
455 455 $DGL 0,6
456 456 0003A RFDD001 call !_my_FSL_Init ;[INF] 3, 3
457 457 ; line 103 :
458 458 ; line 104 : /* <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̃o<CC83>b<EFBFBD>N<EFBFBD>A<EFBFBD>b<EFBFBD>v
459 459 ; line 105 : 0x2000 - 0x4FFF <20><>
460 460 ; line 106 : 0x5000 - 0x7FFF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 20 - 31) <20>ɃR<C983>s<EFBFBD>[
461 461 ; line 107 : */
462 462 ; line 108 : firm_duplicate( ( __far u8 * ) 0x2000,
463 463 ; line 109 : ( 0x5000 / 0x0400 ) );
464 464 $DGL 0,13
465 465 0003D 301400 movw ax,#014H ; 20 ;[INF] 3, 1
466 466 00040 C1 push ax ;[INF] 1, 1
467 467 00041 300020 movw ax,#02000H ; 8192 ;[INF] 3, 1
468 468 00044 F7 clrw bc ;[INF] 1, 1
469 469 00045 RFD4801 call !_firm_duplicate ;[INF] 3, 3
470 470 00048 C0 pop ax ;[INF] 1, 1
471 471 ; line 110 :
472 472 ; line 111 : // <20>S<EFBFBD>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>폜 /////////////////////////////////////
473 473 ; line 112 : // <20>d<EFBFBD><64><EFBFBD>f<EFBFBD>𔻒肷<F094BB92>邽<EFBFBD>߁A<DF81>ŏ<EFBFBD><C58F>ɑS<C991>N<EFBFBD><4E><EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
474 474 ; line 113 : //<2F>i<EFBFBD>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>Ɏc<C98E><63><EFBFBD>Ă<EFBFBD><C482>A<EFBFBD>ȑO<C891>̃t<CC83>@<40>[<5B><><EFBFBD>̃t
475 475 ; <20>b<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>j
476 476 ; line 114 : for( target_block = INACTIVE_BOOTSECT_TOP;
477 477 $DGL 0,18
478 478 00049 CC0504 mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1
479 479 0004C ?L0003:
480 480 ; line 115 : target_block <= UPDATE_BLOCK_LAST;
481 481 $DGL 0,19
482 482 0004C 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1
483 483 0004E 4C14 cmp a,#014H ; 20 ;[INF] 2, 1
484 484 00050 DE08 bnc $?L0004 ;[INF] 2, 4
485 485 ; line 116 : target_block += 1 )
486 486 ; line 117 : {
487 487 00052 ??bb00_firm_update:
488 488 ; line 118 : FSL_Erase( target_block );
489 489 $DGL 0,22
490 490 00052 RFD0000 call !bs_F0064 ;[INF] 3, 3
491 491 00055 ??eb00_firm_update:
492 492 ; line 119 : }
493 493 $DGL 0,23
494 494 00055 615905 inc [hl+5] ; target_block ;[INF] 3, 2
495 495 00058 EFF2 br $?L0003 ;[INF] 2, 3
496 496 0005A ?L0004:
497 497 ; line 120 :
498 498 ; line 121 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD> ///////////////////////////////////////////
499 499 ; line 122 : // <20><><EFBFBD>X<EFBFBD>g<EFBFBD>b<EFBFBD>v<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂ő<DC82><C591><EFBFBD><EFBFBD><EFBFBD>
500 500 ; line 123 : // <20><><EFBFBD>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>[<5B>`<60><><EFBFBD>ɔ<EFBFBD><C994><EFBFBD>
501 501 ; line 124 : for( target_block = INACTIVE_BOOTSECT_TOP;
502 502 $DGL 0,28
503 503 0005A CC0504 mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1
504 504 0005D ?L0006:
505 505 ; line 125 : target_block <= UPDATE_BLOCK_LAST;
506 506 $DGL 0,29
507 507 0005D 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1
508 508 0005F 4C14 cmp a,#014H ; 20 ;[INF] 2, 1
509 509 00061 DE6C bnc $?L0007 ;[INF] 2, 4
510 510 ; line 126 : target_block += 1 )
511 511 ; line 127 : {
512 512 00063 ??bb01_firm_update:
513 513 ; line 128 : // <20>V<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>̈<EFBFBD><CC88>폜
514 514 ; line 129 : FSL_Erase( target_block );
515 515 $DGL 0,33
516 516 00063 RFD0000 call !bs_F0064 ;[INF] 3, 3
517 517 ; line 130 :
518 518 ; line 131 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
519 519 ; line 132 : for( split_write_count = 0;
520 520 $DGL 0,36
521 521 00066 CC0400 mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1
522 522 00069 ?L0009:
523 523 ; line 133 : ( ( split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM
524 524 ; )
525 525 ; line 134 : && ( !SPD ) );
526 526 $DGL 0,38
527 527 00069 8C04 mov a,[hl+4] ; split_write_count ;[INF] 2, 1
528 528 0006B 4C04 cmp a,#04H ; 4 ;[INF] 2, 1
529 529 0006D DE50 bnc $?L0010 ;[INF] 2, 4
530 530 0006F RFD0700 call !bs_S0062 ;[INF] 3, 3
531 531 00072 DC4B bc $?L0010 ;[INF] 2, 4
532 532 ; line 135 : split_write_count += 1 )
533 533 ; line 136 : {
534 534 00074 ??bb02_firm_update:
535 535 ; line 137 : u8* p_buffer = pool;
536 536 $DGL 0,41
537 537 00074 R300000 movw ax,#loww (_pool) ;[INF] 3, 1
538 538 00077 BC02 movw [hl+2],ax ; p_buffer ;[INF] 2, 1
539 539 ; line 138 : u8 buffer_fill = 0;
540 540 $DGL 0,42
541 541 00079 CC0100 mov [hl+1],#00H ; buffer_fill,0 ;[INF] 3, 1
542 542 ; line 139 :
543 543 ; line 140 : WDT_Restart( );
544 544 $DGL 0,44
545 545 0007C RFD0000 call !_WDT_Restart ;[INF] 3, 3
546 546 ; line 141 :
547 547 ; line 142 : // I2C<32><43><EFBFBD>珑<EFBFBD><E78F91><EFBFBD><EFBFBD><EFBFBD>݃f<DD83>[<5B>^<5E><><EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@<40>ɂ<EFBFBD><C982>߂<EFBFBD>
548 548 ; line 143 : do
549 549 0007F ?L0012:
550 550 ; line 144 : {
551 551 0007F ??bb03_firm_update:
552 552 ; line 145 : while( !IICAIF && !SPD ){;}
553 553 $DGL 0,49
554 554 0007F 31B2D105 bt IF2H.3,$?L0016 ;[INF] 4, 5
555 555 00083 RFD0700 call !bs_S0062 ;[INF] 3, 3
556 556 00086 DEF7 bnc $?L0012 ;[INF] 2, 4
557 557 00088 ??bb04_firm_update:
558 558 00088 ??eb04_firm_update:
559 559 00088 ?L0016:
560 560 ; line 146 : IICAIF = 0;
561 561 $DGL 0,50
562 562 00088 713BD1 clr1 IF2H.3 ;[INF] 3, 2
563 563 ; line 147 : *p_buffer = IICA;
564 564 $DGL 0,51
565 565 0008B AC02 movw ax,[hl+2] ; p_buffer ;[INF] 2, 1
566 566 0008D 14 movw de,ax ;[INF] 1, 1
567 567 0008E 8F4005 mov a,!IICA1 ;[INF] 3, 1
568 568 00091 99 mov [de],a ;[INF] 1, 1
569 569 ; line 148 : WREL = 1;
570 570 $DGL 0,52
571 571 00092 71505005 set1 !IICCTL01.5 ;[INF] 4, 2
572 572 ; line 149 : p_buffer += 1;
573 573 $DGL 0,53
574 574 00096 617902 incw [hl+2] ; p_buffer ;[INF] 3, 2
575 575 ; line 150 : buffer_fill += 1;
576 576 $DGL 0,54
577 577 00099 615901 inc [hl+1] ; buffer_fill ;[INF] 3, 2
578 578 0009C ??eb03_firm_update:
579 579 ; line 151 : }
580 580 ; line 152 : while( ( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE
581 581 ; ) && !SPD );
582 582 $DGL 0,56
583 583 0009C 8C01 mov a,[hl+1] ; buffer_fill ;[INF] 2, 1
584 584 0009E D1 cmp0 a ;[INF] 1, 1
585 585 0009F DD05 bz $?L0017 ;[INF] 2, 4
586 586 000A1 RFD0700 call !bs_S0062 ;[INF] 3, 3
587 587 000A4 DED9 bnc $?L0012 ;[INF] 2, 4
588 588 000A6 ?L0017:
589 589 ; line 153 :
590 590 ; line 154 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
591 591 ; line 155 : // <20>Ōゾ<C58C>ƁA<C681>S<EFBFBD>~<7E><><EFBFBD>p<EFBFBD>f<EFBFBD>B<EFBFBD><42><EFBFBD>O<EFBFBD><4F><EFBFBD>邪<EFBFBD>ʂɂ<CA82><C982>܂<EFBFBD><DC82>Ȃ<EFBFBD>
592 592 ; line 156 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC
593 593 ; K_SIZE
594 594 ; line 157 : +
595 595 ; line 158 : split_write_count *
596 596 ; line 159 : SELF_UPDATE_BUFF_SIZE
597 597 ; ),
598 598 ; line 160 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE
599 599 ; / SAM_WORD_SIZE ) )
600 600 ; line 161 :
601 601 ; line 162 : != FSL_OK )
602 602 $DGL 0,66
603 603 000A6 304000 movw ax,#040H ; 64 ;[INF] 3, 1
604 604 000A9 C1 push ax ;[INF] 1, 1
605 605 000AA RFD2500 call !bs_S0060 ;[INF] 3, 3
606 606 000AD RFD1800 call !bs_F0061 ;[INF] 3, 3
607 607 000B0 C0 pop ax ;[INF] 1, 1
608 608 000B1 D2 cmp0 c ;[INF] 1, 1
609 609 000B2 DD06 bz $?L0018 ;[INF] 2, 4
610 610 ; line 163 : {
611 611 000B4 ??bb05_firm_update:
612 612 ; line 164 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݌<EFBFBD><DD8C>̃`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD>G<EFBFBD><47><EFBFBD>[
613 613 ; line 165 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD>̂̂<CC82><CC82>A<EFBFBD><41><EFBFBD>X<EFBFBD>g<EFBFBD>A
614 614 ; line 166 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
615 615 ; line 167 : FSL_SwapBootCluster( );
616 616 $DGL 0,71
617 617 000B4 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3
618 618 ; line 168 : // FSL_Close( );
619 619 ; line 169 : return ( ERR_ERR );
620 620 $DGL 0,73
621 621 000B7 E7 onew bc ;[INF] 1, 1
622 622 000B8 EF59 br $?L0030 ;[INF] 2, 3
623 623 000BA ??eb05_firm_update:
624 624 ; line 170 : }
625 625 000BA ?L0018:
626 626 000BA ??eb02_firm_update:
627 627 ; line 171 :
628 628 ; line 172 : }
629 629 $DGL 0,76
630 630 000BA 615904 inc [hl+4] ; split_write_count ;[INF] 3, 2
631 631 000BD EFAA br $?L0009 ;[INF] 2, 3
632 632 000BF ?L0010:
633 633 ; line 173 : // 1<>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݊<EFBFBD><DD8A><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD><78><EFBFBD>t<EFBFBD>@<40>C<EFBFBD><43><EFBFBD>s<EFBFBD><73>
634 634 ; line 174 : if( FSL_IVerify( target_block ) != FSL_OK ){
635 635 $DGL 0,78
636 636 000BF RFD0F00 call !bs_F0063 ;[INF] 3, 3
637 637 000C2 61E8 skz ;[INF] 2, 1
638 638 000C4 ??bb06_firm_update:
639 639 ; line 175 : // todo <20>ēx<C493><78><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>x<EFBFBD><78><EFBFBD>t<EFBFBD>@<40>C<EFBFBD><43><EFBFBD>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD><D482><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
640 640 ; <20><><EFBFBD>_<EFBFBD><5F><EFBFBD>ł<EFBFBD><C582><EFBFBD>...
641 641 ; line 176 : NOP();
642 642 $DGL 0,80
643 643 000C4 00 nop ;[INF] 1, 1
644 644 000C5 ??eb06_firm_update:
645 645 ; line 177 : }
646 646 000C5 ?L0020:
647 647 ; line 178 :
648 648 ; line 179 : if( SPD )
649 649 $DGL 0,83
650 650 000C5 RFD0700 call !bs_S0062 ;[INF] 3, 3
651 651 000C8 DC05 bc $?L0007 ;[INF] 2, 4
652 652 ; line 180 : {
653 653 000CA ??bb07_firm_update:
654 654 ; line 181 : break;
655 655 000CA ??eb07_firm_update:
656 656 ; line 182 : }
657 657 000CA ??eb01_firm_update:
658 658 ; line 183 : }
659 659 $DGL 0,87
660 660 000CA 615905 inc [hl+5] ; target_block ;[INF] 3, 2
661 661 000CD EF8E br $?L0006 ;[INF] 2, 3
662 662 000CF ?L0007:
663 663 ; line 184 :
664 664 ; line 185 : LREL = 1;
665 665 $DGL 0,89
666 666 000CF 71605005 set1 !IICCTL01.6 ;[INF] 4, 2
667 667 ; line 186 :
668 668 ; line 187 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>񂾃t<F182BE83>@<40>[<5B><><EFBFBD>̃`<60>F<EFBFBD>b<EFBFBD>N //
669 669 ; line 188 : {
670 670 000D3 ??bb08_firm_update:
671 671 ; line 189 : u8 i;
672 672 ; line 190 : u8 comp = 0;
673 673 $DGL 0,94
674 674 000D3 CC0200 mov [hl+2],#00H ; comp,0 ;[INF] 3, 1
675 675 ; line 191 :
676 676 ; line 192 : // <20><><EFBFBD>[<5B>_<EFBFBD>[<5B>̃}<7D>W<EFBFBD>b<EFBFBD>N<EFBFBD>ƁA<C681>{<7B><><EFBFBD>̖<EFBFBD><CC96><EFBFBD><EFBFBD>̃}<7D>W<EFBFBD>b<EFBFBD>N<EFBFBD>͓<EFBFBD><CD93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>m<EFBFBD>F
677 677 ; line 193 : for( i = 0; i < sizeof( __TIME__ ); i++ )
678 678 $DGL 0,97
679 679 000D6 CC0300 mov [hl+3],#00H ; i,0 ;[INF] 3, 1
680 680 000D9 ?L0024:
681 681 000D9 8C03 mov a,[hl+3] ; i ;[INF] 2, 1
682 682 000DB 4C09 cmp a,#09H ; 9 ;[INF] 2, 1
683 683 000DD DE24 bnc $?L0025 ;[INF] 2, 4
684 684 ; line 194 : {
685 685 000DF ??bb09_firm_update:
686 686 ; line 195 : comp += ( *( u8 * ) ( N_MGC_L + i ) == *( u8 * ) ( N
687 687 ; _MGC_T + i ) ) ? 0 : 1;
688 688 $DGL 0,99
689 689 000DF 8C03 mov a,[hl+3] ; i ;[INF] 2, 1
690 690 000E1 318E shrw ax,8 ;[INF] 2, 1
691 691 000E3 12 movw bc,ax ;[INF] 1, 1
692 692 000E4 49F61F mov a,8182[bc] ;[INF] 3, 1
693 693 000E7 72 mov c,a ;[INF] 1, 1
694 694 000E8 8C03 mov a,[hl+3] ; i ;[INF] 2, 1
695 695 000EA 318E shrw ax,8 ;[INF] 2, 1
696 696 000EC 04F64F addw ax,#04FF6H ; 20470 ;[INF] 3, 1
697 697 000EF 14 movw de,ax ;[INF] 1, 1
698 698 000F0 89 mov a,[de] ;[INF] 1, 1
699 699 000F1 6142 cmp c,a ;[INF] 2, 1
700 700 000F3 DF03 bnz $?L0027 ;[INF] 2, 4
701 701 000F5 F6 clrw ax ;[INF] 1, 1
702 702 000F6 EF01 br $?L0028 ;[INF] 2, 3
703 703 000F8 ?L0027:
704 704 000F8 E6 onew ax ;[INF] 1, 1
705 705 000F9 ?L0028:
706 706 000F9 60 mov a,x ;[INF] 1, 1
707 707 000FA 0E02 add a,[hl+2] ; comp ;[INF] 2, 1
708 708 000FC 9C02 mov [hl+2],a ; comp ;[INF] 2, 1
709 709 000FE ??eb09_firm_update:
710 710 ; line 196 : }
711 711 $DGL 0,100
712 712 000FE 615903 inc [hl+3] ; i ;[INF] 3, 2
713 713 00101 EFD6 br $?L0024 ;[INF] 2, 3
714 714 00103 ?L0025:
715 715 ; line 197 : if( comp == 0 )
716 716 $DGL 0,101
717 717 00103 8C02 mov a,[hl+2] ; comp ;[INF] 2, 1
718 718 00105 D1 cmp0 a ;[INF] 1, 1
719 719 00106 DF08 bnz $?L0029 ;[INF] 2, 4
720 720 ; line 198 : {
721 721 00108 ??bb0A_firm_update:
722 722 ; line 199 : FSL_InvertBootFlag( );
723 723 $DGL 0,103
724 724 00108 RFD0000 call !_FSL_InvertBootFlag ;[INF] 3, 3
725 725 ; line 200 : FSL_SwapBootCluster( ); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>ɓ<EFBFBD><C993><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BF
726 726 ; SL_Close<73>͕s<CD95>v
727 727 $DGL 0,104
728 728 0010B RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3
729 729 0010E ??eb0A_firm_update:
730 730 ; line 201 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
731 731 ; line 202 : // FSL_SwapActiveBootCluster(); // <20><><EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD>
732 732 ; <20>܂<EFBFBD><DC82>̂ŁA<C581><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ꂸ<EFBFBD>\<5C><><EFBFBD>I
733 733 ; line 203 : // <20>߂<EFBFBD><DF82>Ă<EFBFBD><C482>Ȃ<EFBFBD> //
734 734 ; line 204 : }
735 735 $DGL 0,108
736 736 0010E EF03 br $?L0030 ;[INF] 2, 3
737 737 00110 ?L0029:
738 738 ; line 205 : else
739 739 ; line 206 : {
740 740 00110 ??bb0B_firm_update:
741 741 ; line 207 : // <20>f<EFBFBD>[<5B>^<5E>G<EFBFBD><47><EFBFBD>[
742 742 ; line 208 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD>̂̂<CC82><CC82>A<EFBFBD><41><EFBFBD>X<EFBFBD>g<EFBFBD>A
743 743 ; line 209 : // FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
744 744 ; line 210 : FSL_SwapBootCluster( );
745 745 $DGL 0,114
746 746 00110 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3
747 747 00113 ??eb0B_firm_update:
748 748 ; line 211 : // FSL_Close( );
749 749 ; line 212 : // <20>߂<EFBFBD><DF82>Ă<EFBFBD><C482>Ȃ<EFBFBD> //
750 750 ; line 213 : }
751 751 00113 ?L0030:
752 752 00113 ??eb08_firm_update:
753 753 ; line 214 : }
754 754 ; line 215 : }
755 755 $DGL 0,119
756 756 00113 ??ef_firm_update:
757 757 00113 1006 addw sp,#06H ;[INF] 2, 1
758 758 00115 C6 pop hl ;[INF] 1, 1
759 759 00116 D7 ret ;[INF] 1, 6
760 760 00117 ??ee_firm_update:
761 761 ; line 216 :
762 762 ; line 217 :
763 763 ; line 218 :
764 764 ; line 219 :
765 765 ; line 220 : /* ========================================================
766 766 ; line 221 : <20>@<40><><EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>b<EFBFBD>N<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>̈悩<CC88>烊<EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD>܂<EFBFBD><DC82>B
767 767 ; line 222 : <20>@<40>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>A<EFBFBD>Ō<EFBFBD><C58C>̍Ō<CC8D><C58C>Ńu<C583>[<5B>g<EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD>̂ŁA
768 768 ; line 223 : <20>@<40><><EFBFBD><EFBFBD><EFBFBD>ł̓u<CD83>[<5B>g<EFBFBD>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD>͕s<CD95>v<EFBFBD>ł<EFBFBD><C582>B
769 769 ; line 224 :
770 770 ; line 225 : ======================================================== */
771 771 ; line 226 : err firm_restore( )
772 772 ; line 227 : {
773 773 00117 _firm_restore:
774 774 $DGL 1,99
775 775 00117 ??bf_firm_restore:
776 776 ; line 228 : my_FSL_Init();
777 777 $DGL 0,2
778 778 00117 RFDD001 call !_my_FSL_Init ;[INF] 3, 3
779 779 ; line 229 :
780 780 ; line 230 : /* <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̃<EFBFBD><CC83>X<EFBFBD>g<EFBFBD>A
781 781 ; line 231 : 0x4800 - 0x7FFF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 18 - 27) <20><><EFBFBD><EFBFBD>
782 782 ; line 232 : 0x2000 - 0x47FF (<28>u<EFBFBD><75><EFBFBD>b<EFBFBD>N 8 - 17) <20>փR<D683>s<EFBFBD>[
783 783 ; line 233 : */
784 784 ; line 234 : firm_duplicate( ( __far u8 * ) 0x5000,
785 785 ; line 235 : FIRM_TOP );
786 786 $DGL 0,9
787 787 0011A 300800 movw ax,#08H ; 8 ;[INF] 3, 1
788 788 0011D C1 push ax ;[INF] 1, 1
789 789 0011E 300050 movw ax,#05000H ; 20480 ;[INF] 3, 1
790 790 00121 F7 clrw bc ;[INF] 1, 1
791 791 00122 RFD4801 call !_firm_duplicate ;[INF] 3, 3
792 792 00125 C0 pop ax ;[INF] 1, 1
793 793 ; line 236 :
794 794 ; line 237 : // todo
795 795 ; line 238 : // <20>@<40><><EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ALED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD><EFBFBD><EFBFBD>āA<C481>T<EFBFBD>[<5B>r<EFBFBD>X<EFBFBD><58>
796 796 ; <20><><EFBFBD>ɂ<EFBFBD><C982>Ă<EFBFBD><C482>炤
797 797 ; line 239 :
798 798 ; line 240 : // <20><><EFBFBD>u<EFBFBD>[<5B>g
799 799 ; line 241 : // <20>X<EFBFBD><58><EFBFBD>b<EFBFBD>v<EFBFBD>͕s<CD95>v<EFBFBD>ł<EFBFBD><C582>I
800 800 ; line 242 : FSL_SwapBootCluster();
801 801 $DGL 0,16
802 802 00126 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3
803 803 ; line 243 : // FSL_ForceReset( );
804 804 ; line 244 : return ( ERR_SUCCESS );
805 805 $DGL 0,18
806 806 00129 F7 clrw bc ;[INF] 1, 1
807 807 ; line 245 : }
808 808 $DGL 0,19
809 809 0012A ??ef_firm_restore:
810 810 0012A D7 ret ;[INF] 1, 6
811 811 0012B ??ee_firm_restore:
812 812 ; line 246 :
813 813 ; line 247 :
814 814 ; line 248 :
815 815 ; line 249 :
816 816 ; line 250 : // ========================================================
817 817 ; line 251 : static void FSL_Open( void )
818 818 ; line 252 : {
819 819 0012B _FSL_Open:
820 820 $DGL 1,105
821 821 0012B ??bf_FSL_Open:
822 822 ; line 253 : /* save the configuration of the interrupt controller and se
823 823 ; t */
824 824 ; line 254 : #ifdef FSL_INT_BACKUP
825 825 ; line 255 : fsl_MK0L_bak_u08 = MK0L; /* if (interrupt backup required
826 826 ; ) */
827 827 ; line 256 : fsl_MK0H_bak_u08 = MK0H; /* {
828 828 ; */
829 829 ; line 257 : fsl_MK1L_bak_u08 = MK1L; /*
830 830 ; */
831 831 ; line 258 : fsl_MK1H_bak_u08 = MK1H; /* save interrupt control
832 832 ; ler */
833 833 ; line 259 : fsl_MK2L_bak_u08 = MK2L; /* configuration
834 834 ; */
835 835 ; line 260 : fsl_MK2H_bak_u08 = MK2H; /*
836 836 ; */
837 837 ; line 261 : MK0L = FSL_MK0L_MASK; /*
838 838 ; */
839 839 ; line 262 : MK0H = FSL_MK0H_MASK; /*
840 840 ; */
841 841 ; line 263 : MK1L = FSL_MK1L_MASK; /* prepare interrupt cont
842 842 ; roller */
843 843 ; line 264 : MK1H = FSL_MK1H_MASK; /* for selfprogramming
844 844 ; */
845 845 ; line 265 : MK2L = FSL_MK2L_MASK; /*
846 846 ; */
847 847 ; line 266 : MK2H = FSL_MK2H_MASK; /* }
848 848 ; */
849 849 ; line 267 : #endif
850 850 ; line 268 :
851 851 ; line 269 : // <20><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD>H
852 852 ; line 270 : // todo DMA<4D><41><EFBFBD>~<7E>߂<EFBFBD>
853 853 ; line 271 : while( DST1 ){;}
854 854 $DGL 0,20
855 855 0012B ?L0035:
856 856 0012B 3184BD02 bf DRC1.0,$?L0036 ;[INF] 4, 5
857 857 0012F ??bb00_FSL_Open:
858 858 0012F ??eb00_FSL_Open:
859 859 0012F EFFA br $?L0035 ;[INF] 2, 3
860 860 00131 ?L0036:
861 861 ; line 272 : DEN1 = 0;
862 862 $DGL 0,21
863 863 00131 717BBD clr1 DRC1.7 ;[INF] 3, 2
864 864 ; line 273 :
865 865 ; line 274 : MK0 = 0xFFFF;
866 866 $DGL 0,23
867 867 00134 CBE4FFFF movw MK0,#0FFFFH ; -1 ;[INF] 4, 1
868 868 ; line 275 : MK1 = 0xFFFF;
869 869 $DGL 0,24
870 870 00138 CBE6FFFF movw MK1,#0FFFFH ; -1 ;[INF] 4, 1
871 871 ; line 276 : MK2 = 0xFFFF;
872 872 $DGL 0,25
873 873 0013C CBD4FFFF movw MK2,#0FFFFH ; -1 ;[INF] 4, 1
874 874 ; line 277 :
875 875 ; line 278 : FSL_FLMD0_HIGH; // <20>t<EFBFBD><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682><EFBFBD><EFBFBD><EFBFBD>
876 876 $DGL 0,27
877 877 00140 ??bb01_FSL_Open:
878 878 00140 717ABE set1 BECTL.7 ;[INF] 3, 2
879 879 00143 ??eb01_FSL_Open:
880 880 ; line 279 : }
881 881 $DGL 0,28
882 882 00143 ??ef_FSL_Open:
883 883 00143 D7 ret ;[INF] 1, 6
884 884 00144 ??ee_FSL_Open:
885 885 ; line 280 :
886 886 ; line 281 :
887 887 ; line 282 :
888 888 ; line 283 : /*--------------------------------------------------------------
889 889 ; --------------------------------*/
890 890 ; line 284 : /* leave the "user room" and restore previous conditions
891 891 ; */
892 892 ; line 285 : /*--------------------------------------------------------------
893 893 ; --------------------------------*/
894 894 ; line 286 : static void FSL_Close( void )
895 895 ; line 287 : {
896 896 00144 _FSL_Close:
897 897 $DGL 1,119
898 898 00144 ??bf_FSL_Close:
899 899 ; line 288 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n<EFBFBD><6E><EFBFBD>H
900 900 ; line 289 :
901 901 ; line 290 : FSL_FLMD0_LOW; // <20>t<EFBFBD><74><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>C<EFBFBD>g<EFBFBD>v<EFBFBD><76><EFBFBD>e<EFBFBD>N<EFBFBD>g
902 902 $DGL 0,4
903 903 00144 ??bb00_FSL_Close:
904 904 00144 717BBE clr1 BECTL.7 ;[INF] 3, 2
905 905 00147 ??eb00_FSL_Close:
906 906 ; line 291 :
907 907 ; line 292 : #ifdef FSL_INT_BACKUP
908 908 ; line 293 : MK0L = fsl_MK0L_bak_u08; /* do{
909 909 ; */
910 910 ; line 294 : MK0H = fsl_MK0H_bak_u08; /* restore interrupt cont
911 911 ; roller */
912 912 ; line 295 : MK1L = fsl_MK1L_bak_u08; /* configuration
913 913 ; */
914 914 ; line 296 : MK1H = fsl_MK1H_bak_u08; /*
915 915 ; */
916 916 ; line 297 : MK2L = fsl_MK2L_bak_u08; /*
917 917 ; */
918 918 ; line 298 : MK2H = fsl_MK2H_bak_u08; /* }
919 919 ; */
920 920 ; line 299 : #endif
921 921 ; line 300 : }
922 922 $DGL 0,14
923 923 00147 ??ef_FSL_Close:
924 924 00147 D7 ret ;[INF] 1, 6
925 925 00148 ??ee_FSL_Close:
926 926 ; line 301 :
927 927 ; line 302 :
928 928 ; line 303 :
929 929 ; line 304 : /* ========================================================
930 930 ; line 305 : <20>@<40>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD><EFBFBD><EFBFBD>Ńt<C583>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>܂<EFBFBD><DC82>B
931 931 ; line 306 : __far u8 * p_rom <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>̐擪<CC90>A<EFBFBD>h<EFBFBD><68><EFBFBD>X
932 932 ; line 307 : block_dest <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>̐擪<CC90>u<EFBFBD><75><EFBFBD>b<EFBFBD>N
933 933 ; line 308 :
934 934 ; line 309 : <20>R<EFBFBD>s<EFBFBD>[<5B><><EFBFBD>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>悤<EFBFBD><E682A4>my_FSL_Init<69><74><EFBFBD><EFBFBD><EFBFBD>炩<EFBFBD><E782A9><EFBFBD>ߎ<EFBFBD><DF8E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>K<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
935 935 ; <20>܂<EFBFBD><DC82>B
936 936 ; line 310 : ======================================================== */
937 937 ; line 311 : static err firm_duplicate( __far u8 * p_rom,
938 938 ; line 312 : u8 block_dest )
939 939 ; line 313 : {
940 940 00148 _firm_duplicate:
941 941 $DGL 1,129
942 942 00148 C7 push hl ;[INF] 1, 1
943 943 00149 C3 push bc ;[INF] 1, 1
944 944 0014A C1 push ax ;[INF] 1, 1
945 945 0014B 2006 subw sp,#06H ;[INF] 2, 1
946 946 0014D FBF8FF movw hl,sp ;[INF] 3, 1
947 947 00150 ??bf_firm_duplicate:
948 948 ; line 314 : u8 target_block;
949 949 ; line 315 : u8 split_write_count; // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>ւ<EFBFBD><D682>܂<EFBFBD><DC82>܏<EFBFBD><DC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ރJ<DE83>E
950 950 ; <20><><EFBFBD>^
951 951 ; line 316 :
952 952 ; line 317 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݐ<EFBFBD><DD90>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD>
953 953 ; line 318 : for( target_block = block_dest;
954 954 $DGL 0,6
955 955 00150 8C10 mov a,[hl+16] ; block_dest ;[INF] 2, 1
956 956 00152 9C05 mov [hl+5],a ; target_block ;[INF] 2, 1
957 957 00154 ?L0041:
958 958 ; line 319 : target_block < block_dest + FIRM_SIZE;
959 959 $DGL 0,7
960 960 00154 8C10 mov a,[hl+16] ; block_dest ;[INF] 2, 1
961 961 00156 318E shrw ax,8 ;[INF] 2, 1
962 962 00158 040C00 addw ax,#0CH ; 12 ;[INF] 3, 1
963 963 0015B 12 movw bc,ax ;[INF] 1, 1
964 964 0015C 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1
965 965 0015E 318E shrw ax,8 ;[INF] 2, 1
966 966 00160 RBD00 movw _@RTARG0,ax ;[INF] 2, 1
967 967 00162 13 movw ax,bc ;[INF] 1, 1
968 968 00163 RFD0000 call !@@iscmp ;[INF] 3, 3
969 969 00166 DE63 bnc $?L0042 ;[INF] 2, 4
970 970 ; line 320 : target_block += 1 )
971 971 ; line 321 : {
972 972 00168 ??bb00_firm_duplicate:
973 973 ; line 322 : WDT_Restart( );
974 974 $DGL 0,10
975 975 00168 RFD0000 call !_WDT_Restart ;[INF] 3, 3
976 976 ; line 323 : // <20>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
977 977 ; line 324 : while( FSL_BlankCheck( target_block ) != FSL_OK )
978 978 $DGL 0,12
979 979 0016B ?L0044:
980 980 0016B 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1
981 981 0016D 318E shrw ax,8 ;[INF] 2, 1
982 982 0016F RFD0000 call !_FSL_BlankCheck ;[INF] 3, 3
983 983 00172 D2 cmp0 c ;[INF] 1, 1
984 984 00173 DD05 bz $?L0045 ;[INF] 2, 4
985 985 ; line 325 : {
986 986 00175 ??bb01_firm_duplicate:
987 987 ; line 326 : FSL_Erase( target_block );
988 988 $DGL 0,14
989 989 00175 RFD0000 call !bs_F0064 ;[INF] 3, 3
990 990 00178 ??eb01_firm_duplicate:
991 991 ; line 327 : }
992 992 $DGL 0,15
993 993 00178 EFF1 br $?L0044 ;[INF] 2, 3
994 994 0017A ?L0045:
995 995 ; line 328 :
996 996 ; line 329 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݕ<EFBFBD><DD95>J<EFBFBD><4A><EFBFBD>Ԃ<EFBFBD>
997 997 ; line 330 : for( split_write_count = 0;
998 998 $DGL 0,18
999 999 0017A CC0400 mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1
1000 1000 0017D ?L0046:
1001 1001 ; line 331 : split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM;
1002 1002 $DGL 0,19
1003 1003 0017D 8C04 mov a,[hl+4] ; split_write_count ;[INF] 2, 1
1004 1004 0017F 4C04 cmp a,#04H ; 4 ;[INF] 2, 1
1005 1005 00181 DE3E bnc $?L0047 ;[INF] 2, 4
1006 1006 ; line 332 : split_write_count += 1 )
1007 1007 ; line 333 : {
1008 1008 00183 ??bb02_firm_duplicate:
1009 1009 ; line 334 : u8 buffer_fill;
1010 1010 ; line 335 : u8* p_buff;
1011 1011 ; line 336 :
1012 1012 ; line 337 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݃f<DD83>[<5B>^<5E><><EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@<40>ɂ<EFBFBD><C982>߂<EFBFBD>
1013 1013 ; line 338 : buffer_fill = 0;
1014 1014 $DGL 0,26
1015 1015 00183 CC0300 mov [hl+3],#00H ; buffer_fill,0 ;[INF] 3, 1
1016 1016 ; line 339 : p_buff = pool;
1017 1017 $DGL 0,27
1018 1018 00186 R300000 movw ax,#loww (_pool) ;[INF] 3, 1
1019 1019 00189 BB movw [hl],ax ; p_buff ;[INF] 1, 1
1020 1020 ; line 340 : do
1021 1021 0018A ?L0049:
1022 1022 ; line 341 : {
1023 1023 0018A ??bb03_firm_duplicate:
1024 1024 ; line 342 : *p_buff = *p_rom;
1025 1025 $DGL 0,30
1026 1026 0018A AC06 movw ax,[hl+6] ; p_rom ;[INF] 2, 1
1027 1027 0018C 14 movw de,ax ;[INF] 1, 1
1028 1028 0018D 8C08 mov a,[hl+8] ; p_rom ;[INF] 2, 1
1029 1029 0018F 9EFD mov ES,a ;[INF] 2, 1
1030 1030 00191 1189 mov a,ES:[de] ;[INF] 2, 2
1031 1031 00193 72 mov c,a ;[INF] 1, 1
1032 1032 00194 AB movw ax,[hl] ; p_buff ;[INF] 1, 1
1033 1033 00195 14 movw de,ax ;[INF] 1, 1
1034 1034 00196 62 mov a,c ;[INF] 1, 1
1035 1035 00197 99 mov [de],a ;[INF] 1, 1
1036 1036 ; line 343 : p_rom += 1;
1037 1037 $DGL 0,31
1038 1038 00198 AC06 movw ax,[hl+6] ; p_rom ;[INF] 2, 1
1039 1039 0019A A1 incw ax ;[INF] 1, 1
1040 1040 0019B BC06 movw [hl+6],ax ; p_rom ;[INF] 2, 1
1041 1041 ; line 344 : p_buff += 1;
1042 1042 $DGL 0,32
1043 1043 0019D 617900 incw [hl+0] ; p_buff ;[INF] 3, 2
1044 1044 ; line 345 : buffer_fill +=1;
1045 1045 $DGL 0,33
1046 1046 001A0 615903 inc [hl+3] ; buffer_fill ;[INF] 3, 2
1047 1047 001A3 ??eb03_firm_duplicate:
1048 1048 ; line 346 : }
1049 1049 ; line 347 : while( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE )
1050 1050 ; ;
1051 1051 $DGL 0,35
1052 1052 001A3 8C03 mov a,[hl+3] ; buffer_fill ;[INF] 2, 1
1053 1053 001A5 D1 cmp0 a ;[INF] 1, 1
1054 1054 001A6 DFE2 bnz $?L0049 ;[INF] 2, 4
1055 1055 ; line 348 :
1056 1056 ; line 349 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1057 1057 ; line 350 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC
1058 1058 ; K_SIZE
1059 1059 ; line 351 : +
1060 1060 ; line 352 : split_write_count *
1061 1061 ; line 353 : SELF_UPDATE_BUFF_SIZE
1062 1062 ; ),
1063 1063 ; line 354 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE
1064 1064 ; / SAM_WORD_SIZE ) )
1065 1065 ; line 355 : != FSL_OK )
1066 1066 $DGL 0,43
1067 1067 001A8 304000 movw ax,#040H ; 64 ;[INF] 3, 1
1068 1068 001AB C1 push ax ;[INF] 1, 1
1069 1069 001AC RFD2500 call !bs_S0060 ;[INF] 3, 3
1070 1070 001AF RFD1800 call !bs_F0061 ;[INF] 3, 3
1071 1071 001B2 C0 pop ax ;[INF] 1, 1
1072 1072 001B3 D2 cmp0 c ;[INF] 1, 1
1073 1073 001B4 DD06 bz $?L0052 ;[INF] 2, 4
1074 1074 ; line 356 : {
1075 1075 001B6 ??bb04_firm_duplicate:
1076 1076 ; line 357 : FSL_Close( );
1077 1077 $DGL 0,45
1078 1078 001B6 RFD4401 call !_FSL_Close ;[INF] 3, 3
1079 1079 ; line 358 : return ( ERR_ERR );
1080 1080 $DGL 0,46
1081 1081 001B9 E7 onew bc ;[INF] 1, 1
1082 1082 001BA EF10 br $?L0040 ;[INF] 2, 3
1083 1083 001BC ??eb04_firm_duplicate:
1084 1084 ; line 359 : }
1085 1085 001BC ?L0052:
1086 1086 001BC ??eb02_firm_duplicate:
1087 1087 ; line 360 : }
1088 1088 $DGL 0,48
1089 1089 001BC 615904 inc [hl+4] ; split_write_count ;[INF] 3, 2
1090 1090 001BF EFBC br $?L0046 ;[INF] 2, 3
1091 1091 001C1 ?L0047:
1092 1092 ; line 361 :
1093 1093 ; line 362 : // 1<>u<EFBFBD><75><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>݊<EFBFBD><DD8A><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>d<EFBFBD><64><EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD><73>
1094 1094 ; line 363 : while( FSL_IVerify( target_block ) != FSL_OK ){
1095 1095 $DGL 0,51
1096 1096 001C1 RFD0F00 call !bs_F0063 ;[INF] 3, 3
1097 1097 001C4 DFFB bnz $?L0047 ;[INF] 2, 4
1098 1098 001C6 ??bb05_firm_duplicate:
1099 1099 ; line 364 : // todo
1100 1100 ; line 365 : ;
1101 1101 001C6 ??eb05_firm_duplicate:
1102 1102 ; line 366 : }
1103 1103 001C6 ??eb00_firm_duplicate:
1104 1104 ; line 367 : }
1105 1105 $DGL 0,55
1106 1106 001C6 615905 inc [hl+5] ; target_block ;[INF] 3, 2
1107 1107 001C9 EF89 br $?L0041 ;[INF] 2, 3
1108 1108 001CB ?L0042:
1109 1109 ; line 368 : return( ERR_SUCCESS );
1110 1110 $DGL 0,56
1111 1111 001CB F7 clrw bc ;[INF] 1, 1
1112 1112 ; line 369 :
1113 1113 ; line 370 : }
1114 1114 001CC ?L0040:
1115 1115 $DGL 0,58
1116 1116 001CC ??ef_firm_duplicate:
1117 1117 001CC 100A addw sp,#0AH ;[INF] 2, 1
1118 1118 001CE C6 pop hl ;[INF] 1, 1
1119 1119 001CF D7 ret ;[INF] 1, 6
1120 1120 001D0 ??ee_firm_duplicate:
1121 1121 ; line 371 :
1122 1122 ; line 372 :
1123 1123 ; line 373 :
1124 1124 ; line 374 : /* ========================================================
1125 1125 ; line 375 : ======================================================== */
1126 1126 ; line 376 : static err my_FSL_Init()
1127 1127 ; line 377 : {
1128 1128 001D0 _my_FSL_Init:
1129 1129 $DGL 1,168
1130 1130 001D0 ??bf_my_FSL_Init:
1131 1131 ; line 378 : RTCE = 0;
1132 1132 $DGL 0,2
1133 1133 001D0 717B9D clr1 RTCC0.7 ;[INF] 3, 2
1134 1134 ; line 379 :
1135 1135 ; line 380 : // <20><><EFBFBD><EFBFBD><EFBFBD>ւ<EFBFBD><D682>O<EFBFBD><4F><EFBFBD><EFBFBD> //
1136 1136 ; line 381 : DI( );
1137 1137 $DGL 0,5
1138 1138 001D3 717BFA di ;[INF] 3, 4
1139 1139 ; line 382 : FSL_Open( ); // <20><><EFBFBD>荞<EFBFBD>݋֎~<7E>Ȃ<EFBFBD>
1140 1140 $DGL 0,6
1141 1141 001D6 RFD2B01 call !_FSL_Open ;[INF] 3, 3
1142 1142 ; line 383 :
1143 1143 ; line 384 : FSL_Init( pool ); // <20><><EFBFBD>C<EFBFBD>u<EFBFBD><75><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD>荞<EFBFBD>ݒ<EFBFBD><DD92>f<EFBFBD>l<EFBFBD><6C>
1144 1144 ; <20><><EFBFBD><EFBFBD>
1145 1145 $DGL 0,8
1146 1146 001D9 R300000 movw ax,#loww (_pool) ;[INF] 3, 1
1147 1147 001DC RFD0000 call !_FSL_Init ;[INF] 3, 3
1148 1148 ; line 385 : FSL_ModeCheck( ); // <20><><EFBFBD>C<EFBFBD>g<EFBFBD>v<EFBFBD><76><EFBFBD>e<EFBFBD>N<EFBFBD>g<EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD>B<EFBFBD><42><EFBFBD>s<EFBFBD><73><EFBFBD>邱
1149 1149 ; <20>Ƃ<EFBFBD><C682>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1150 1150 $DGL 0,9
1151 1151 001DF RFD0000 call !_FSL_ModeCheck ;[INF] 3, 3
1152 1152 ; line 386 :
1153 1153 ; line 387 : return( ERR_SUCCESS );
1154 1154 $DGL 0,11
1155 1155 001E2 F7 clrw bc ;[INF] 1, 1
1156 1156 ; line 388 : }
1157 1157 $DGL 0,12
1158 1158 001E3 ??ef_my_FSL_Init:
1159 1159 001E3 D7 ret ;[INF] 1, 6
1160 1160 001E4 ??ee_my_FSL_Init:
1161 1161 ; line 389 :
1162 1162 ; line 390 :
1163 1163 ; line 391 : task_status_immed tski_mcu_reset()
1164 1164 ; line 392 : {
1165 1165 001E4 _tski_mcu_reset:
1166 1166 $DGL 1,174
1167 1167 001E4 ??bf_tski_mcu_reset:
1168 1168 ; line 393 : // <20><><EFBFBD>ʂɍċN<C48B><4E>
1169 1169 ; line 394 : my_FSL_Init();
1170 1170 $DGL 0,3
1171 1171 001E4 RFDD001 call !_my_FSL_Init ;[INF] 3, 3
1172 1172 ; line 395 : FSL_Close( );
1173 1173 $DGL 0,4
1174 1174 001E7 RFD4401 call !_FSL_Close ;[INF] 3, 3
1175 1175 ; line 396 : // FSL_SwapBootCluster();
1176 1176 ; line 397 : FSL_ForceReset(); // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
1177 1177 $DGL 0,6
1178 1178 001EA RFD0000 call !_FSL_ForceReset ;[INF] 3, 3
1179 1179 ; line 398 :
1180 1180 ; line 399 : // <20>ی<EFBFBD><DB8C>H //
1181 1181 ; line 400 : WDTE = 0xAA; // WDT<44>ōċN<C48B><4E><EFBFBD>i<EFBFBD>e<EFBFBD>X<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>j
1182 1182 $DGL 0,9
1183 1183 001ED CEABAA mov WDTE,#0AAH ; 170 ;[INF] 3, 1
1184 1184 ; line 401 : return( ERR_SUCCESS ); // no reach
1185 1185 $DGL 0,10
1186 1186 001F0 F7 clrw bc ;[INF] 1, 1
1187 1187 ; line 402 : }
1188 1188 $DGL 0,11
1189 1189 001F1 ??ef_tski_mcu_reset:
1190 1190 001F1 D7 ret ;[INF] 1, 6
1191 1191 001F2 ??ee_tski_mcu_reset:
1192 1192
1193 1193 ----- LDR_CODL CSEG
1194 1194
1195 1195 ----- @@BASE CSEG BASE
1196 1196 END
1197 1197
1198 1198
1199 1199 ; *** Code Information ***
1200 1200 ;
1201 1201 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c
1202 1202 ;
1203 1203 ; $FUNC firm_update(97)
1204 1204 ; bc=(void)
1205 1205 ; CODE SIZE= 227 bytes, CLOCK_SIZE= 287 clocks, STACK_SIZE= 16 bytes
1206 1206 ;
1207 1207 ; $CALL my_FSL_Init(102)
1208 1208 ; bc=(void)
1209 1209 ;
1210 1210 ; $CALL firm_duplicate(109)
1211 1211 ; bc=(pointer:ax,bc, int:[sp+4])
1212 1212 ;
1213 1213 ; $CALL FSL_Erase(118)
1214 1214 ; bc=(unsigned int:ax)
1215 1215 ;
1216 1216 ; $CALL FSL_Erase(129)
1217 1217 ; bc=(unsigned int:ax)
1218 1218 ;
1219 1219 ; $CALL WDT_Restart(140)
1220 1220 ; void=(void)
1221 1221 ;
1222 1222 ; $CALL FSL_Write(162)
1223 1223 ; bc=(unsigned long:ax,bc, int:[sp+4])
1224 1224 ;
1225 1225 ; $CALL FSL_SwapBootCluster(167)
1226 1226 ; void=(void)
1227 1227 ;
1228 1228 ; $CALL FSL_IVerify(174)
1229 1229 ; bc=(unsigned int:ax)
1230 1230 ;
1231 1231 ; $CALL FSL_InvertBootFlag(199)
1232 1232 ; bc=(void)
1233 1233 ;
1234 1234 ; $CALL FSL_SwapBootCluster(200)
1235 1235 ; void=(void)
1236 1236 ;
1237 1237 ; $CALL FSL_SwapBootCluster(210)
1238 1238 ; void=(void)
1239 1239 ;
1240 1240 ; $FUNC firm_restore(227)
1241 1241 ; bc=(void)
1242 1242 ; CODE SIZE= 20 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 6 bytes
1243 1243 ;
1244 1244 ; $CALL my_FSL_Init(228)
1245 1245 ; bc=(void)
1246 1246 ;
1247 1247 ; $CALL firm_duplicate(235)
1248 1248 ; bc=(pointer:ax,bc, int:[sp+4])
1249 1249 ;
1250 1250 ; $CALL FSL_SwapBootCluster(242)
1251 1251 ; void=(void)
1252 1252 ;
1253 1253 ; $FUNC FSL_Open(252)
1254 1254 ; void=(void)
1255 1255 ; CODE SIZE= 25 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 0 bytes
1256 1256 ;
1257 1257 ; $FUNC FSL_Close(287)
1258 1258 ; void=(void)
1259 1259 ; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes
1260 1260 ;
1261 1261 ; $FUNC firm_duplicate(313)
1262 1262 ; bc=(pointer p_rom:ax,bc, unsigned char block_dest:[sp+4])
1263 1263 ; CODE SIZE= 136 bytes, CLOCK_SIZE= 161 clocks, STACK_SIZE= 20 bytes
1264 1264 ;
1265 1265 ; $CALL WDT_Restart(322)
1266 1266 ; void=(void)
1267 1267 ;
1268 1268 ; $CALL FSL_BlankCheck(324)
1269 1269 ; bc=(unsigned int:ax)
1270 1270 ;
1271 1271 ; $CALL FSL_Erase(326)
1272 1272 ; bc=(unsigned int:ax)
1273 1273 ;
1274 1274 ; $CALL FSL_Write(355)
1275 1275 ; bc=(unsigned long:ax,bc, int:[sp+4])
1276 1276 ;
1277 1277 ; $CALL FSL_Close(357)
1278 1278 ; void=(void)
1279 1279 ;
1280 1280 ; $CALL FSL_IVerify(363)
1281 1281 ; bc=(unsigned int:ax)
1282 1282 ;
1283 1283 ; $FUNC my_FSL_Init(377)
1284 1284 ; bc=(void)
1285 1285 ; CODE SIZE= 20 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 4 bytes
1286 1286 ;
1287 1287 ; $CALL FSL_Open(382)
1288 1288 ; void=(void)
1289 1289 ;
1290 1290 ; $CALL FSL_Init(384)
1291 1291 ; bc=(pointer:ax)
1292 1292 ;
1293 1293 ; $CALL FSL_ModeCheck(385)
1294 1294 ; bc=(void)
1295 1295 ;
1296 1296 ; $FUNC tski_mcu_reset(392)
1297 1297 ; bc=(void)
1298 1298 ; CODE SIZE= 14 bytes, CLOCK_SIZE= 17 clocks, STACK_SIZE= 4 bytes
1299 1299 ;
1300 1300 ; $CALL my_FSL_Init(394)
1301 1301 ; bc=(void)
1302 1302 ;
1303 1303 ; $CALL FSL_Close(395)
1304 1304 ; void=(void)
1305 1305 ;
1306 1306 ; $CALL FSL_ForceReset(397)
1307 1307 ; void=(void)
1308 1308
1309 1309 ; Target chip : uPD79F0104
1310 1310 ; Device file : E1.00b
Segment informations:
ADRS LEN NAME
00000 00000H.0 @@BITS
00000 00002H @@CNST
00000 00000H @@R_INIT
00000 00000H @@INIT
00000 00000H @@DATA
00000 00000H @@R_INIS
00000 00000H @@INIS
00000 00000H @@DATS
00000 00000H LDR_CNSL
00000 00000H @@RLINIT
00000 00000H @@INITL
00000 00000H @@DATAL
00000 00000H @@CALT
00000 001F2H LDR_CODE
00000 00000H LDR_CODL
00000 00000H @@BASE
Target chip : uPD79F0104
Device file : E1.00b
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)

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