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https://github.com/rvtr/ctr_mcu.git
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rengeの即時実行の方のタスク登録やらがおかしかったので修正。 タスクの管理?に不整合が出てしまう。タスク登録処理中に、割り込みからも登録しようとすると不整合が出る。 タスクを登録するが、呼ばなくなってしまう。 登録中に割り込み禁止にすると、I2Cのステートがおかしくなってしまう。 ↑解消のため、I2C_CTRをすべて割り込みドリブンにした。 RTCアラーム実装 IRQマスク実装 未:TWL側とのやりとり 歩数計 今回のタスク管理の修正で評価に入れる状態になったと思われ git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@9 013db118-44a6-b54f-8bf7-843cb86687b1
174 lines
4.8 KiB
C
174 lines
4.8 KiB
C
/* ========================================================
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TWL互換側のI2Cレジスタ
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======================================================== */
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#include "incs.h"
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#include "jhl_defs.h"
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#include "vreg_twl.h"
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u8 vreg_twl[ REG_TWL_INT_ADRS_TIME_PWSW_THRESHOLD +1 ];
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/* ========================================================
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仮想レジスタの初期化
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======================================================== */
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void vreg_twl_init(){
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vreg_twl[ REG_TWL_INT_ADRS_VER_INFO ] = 0x35;
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vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F;
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vreg_twl[ REG_TWL_INT_ADRS_POWER_SAVE ] = 0x07;
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vreg_twl[ REG_TWL_INT_ADRS_BL ] = 0x03;
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vreg_twl[ REG_TWL_INT_ADRS_CODEC_MIC_GAIN ] = 0x01;
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vreg_twl[ REG_TWL_INT_ADRS_ADC_CALIB_STATUS ] = 0x01;
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vreg_twl[ REG_TWL_INT_ADRS_ADC_CALIB_VALUE ] = 0x60;
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}
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// ========================================================
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// I2C仮想レジスタに書きます。
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// 引数 adrs は内部アドレス
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// 存在しないアドレスにアクセスした場合、何もしません。
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void vreg_twl_write( u8 adrs, u8 data ){
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switch( adrs ){
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case( REG_TWL_INT_ADRS_COMMAND ):
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case( REG_TWL_INT_ADRS_MODE ):
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case( REG_TWL_INT_ADRS_POWER_SAVE ):
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case( REG_TWL_INT_ADRS_WIFI ):
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case( REG_TWL_INT_ADRS_CAM ):
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case( REG_TWL_INT_ADRS_VOL ):
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case( REG_TWL_INT_ADRS_BL ):
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/*
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REG_TWL_INT_ADRS_CODEC_MIC_GAIN, // 0x50,
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REG_TWL_INT_ADRS_CODEC_MIC_GAIN_RELOAD,
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REG_TWL_INT_ADRS_ADC_CALIB, // 0x60,
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REG_TWL_INT_ADRS_ADC_CALIB_VALUE,
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REG_TWL_INT_ADRS_POWER_LED,
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*/
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case( REG_TWL_INT_ADRS_TEMP0 ):
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case( REG_TWL_INT_ADRS_TEMP1 ):
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case( REG_TWL_INT_ADRS_TEMP2 ):
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case( REG_TWL_INT_ADRS_TEMP3 ):
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case( REG_TWL_INT_ADRS_TEMP4 ):
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case( REG_TWL_INT_ADRS_TEMP5 ):
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case( REG_TWL_INT_ADRS_TEMP6 ):
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case( REG_TWL_INT_ADRS_TEMP7 ):
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// REG_TWL_INT_ADRS_TIME_PWSW_DELAY,
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// REG_TWL_INT_ADRS_TIME_PWSW_THRESHOLD
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vreg_twl[ adrs ] = data;
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break;
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}
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// TWLレジスタに書かれて何かアクションする
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switch( adrs ){
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case( REG_TWL_INT_ADRS_COMMAND ):
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if( data != 0 ){
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renge_task_immed_add( command_from_twl );
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break;
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}
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default:
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break;
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}
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return;
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}
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// ========================================================
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// I2C仮想レジスタから読みます。
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// 引数 adrs 外から見たときの、アドレス
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// 戻り xx データ
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// 存在しないアドレスにアクセスした場合、戻り値は0x5A
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u8 vreg_twl_read( u8 phy_adrs ){
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u8 dat;
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dat = vreg_twl[ phy_adrs ];
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// リードがトリガで何かをするなら↓
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return( dat );
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}
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// ========================================================
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// 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える
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// 0xFFは存在しないアドレス。
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u8 adrs_table_twl_ext2int( u8 img ){
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u8 adrsH, adrsL;
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adrsH = ( img & 0xF0 );
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adrsL = ( img & 0x0F );
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if( adrsH > 0x80 ){
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return( 0xFF );
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}
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if( adrsH == 0x50 ){
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return( 0xFF );
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}
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if( adrsH <= 0x30 ){ // 0x00 - 0x3F
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if( adrsH <= 0x10 ){ // 0x00 - 0x1F
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if( adrsH == 0x10 ){ // 0x1*
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if( adrsL <= ( REG_TWL_ADRS_MODE & 0x0F ) ){
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return( REG_TWL_INT_ADRS_IRQ + adrsL );
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}
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}else{ // 0x0*
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if( adrsL <= ( REG_TWL_ADRS_BATT_INFO & 0x0F ) ){
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return( REG_TWL_INT_ADRS_VER_INFO + adrsL );
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}
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}
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}else{ // 0x20 - 0x3F
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if( adrsH == 0x20 ){ // 0x2?
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if( adrsL <= ( REG_TWL_ADRS_POWER_SAVE & 0x0F ) ){
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return( REG_TWL_INT_ADRS_POWER_INFO + adrsL );
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}
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}else{ // 0x3*
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if( adrsL <= ( REG_TWL_ADRS_CAM & 0x0F ) ){
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return( REG_TWL_INT_ADRS_WIFI + adrsL );
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}
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}
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}
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}else{
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if( adrsH <= 0x60 ){
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if( adrsH == 0x60 ){
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if( adrsL <= ( REG_TWL_ADRS_POWER_LED & 0x0F ) ){
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return( REG_TWL_INT_ADRS_ADC_CALIB + adrsL );
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}
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}else{ // 40台
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if( adrsL <= ( REG_TWL_ADRS_BL & 0x0F ) ){
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return( REG_TWL_INT_ADRS_VOL + adrsL );
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}
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}
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}else{
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if( adrsH == 0x70 ){
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if( adrsL <= ( REG_TWL_ADRS_TEMP7 & 0x0F ) ){
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return( REG_TWL_INT_ADRS_TEMP0 + adrsL );
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}
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}else{ // 80台
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if( adrsL <= ( REG_TWL_ADRS_TIME_PWSW_THRESHOLD & 0x0F ) ){
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return( REG_TWL_INT_ADRS_TIME_PWSW_DELAY + adrsL );
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}
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}
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}
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}
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return( 0xFF );
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}
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/* ========================================================
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TWLからのコマンド
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・リセット
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・電源断
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======================================================== */
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task_status_immed command_from_twl(){
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vreg_ctr[ VREG_C_IRQ2 ] |= REG_BIT_TWL_RESET_REQ;
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if( ( vreg_ctr[ VREG_C_IRQ_MASK2 ] & REG_BIT_TWL_RESET_REQ ) == 0 ){
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IRQ0_ast;
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}
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return( ERR_FINISED );
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}
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