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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@539 013db118-44a6-b54f-8bf7-843cb86687b1
323 lines
9.8 KiB
C
323 lines
9.8 KiB
C
#ifndef __vreg_ctr__
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#define __vreg_ctr__
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/*
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$Id$
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*/
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#include "config.h"
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// VREG_C_MCU_STATUS
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// bit[7.6] twl.sys_modeの[1.0] ctrから書けないが、fcr_reset時に適当にリセット
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// bit[5] 〃 [7] ctrから書けないが、fcr_reset時に適当にリセット
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#define REG_BIT_STATUS_WDT_RESET ( 1 << 1 )
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#define REG_BIT_RTC_BLACKOUT ( 1 << 0 )
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// VREG_C_STATUS,
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#define REG_BIT_LCD_POW ( 1 << 7 )
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#define REG_BIT_BL_U ( 1 << 6 )
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#define REG_BIT_BL_L ( 1 << 5 )
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#define REG_BIT_BATT_CHARGE ( 1 << 4 )
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#define REG_BIT_POW_SUPPLY ( 1 << 3 )
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// 未使用 ( 1 << 2 )
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#define REG_BIT_ST_SHELL_OPEN ( 1 << 1 )
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// 未使用 ( 1 << 0 )
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// VREG_C_STATUS_X
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// 未使用 ( 1 << 6 )
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// 未使用 ( 1 << 5 )
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#define REG_BIT_WIFI_TX ( 1 << 4 )
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// twl bl のミラー[1: ( 1 << 3 )
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// 0]( 1 << 2 )
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#define REG_BIT_ACCERO_ERR ( 1 << 1 )
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#define REG_BIT_MGIC_ERR ( 1 << 0 )
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#define REG_BIT_MASK_STATUS1_NTR_PM_REG 0x0C
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// VREG_C_IRQ0
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#define REG_BIT_IRQ_WDT_RESET ( 1 << 7 )
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#define REG_BIT_SHELL_OPEN ( 1 << 6 )
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#define REG_BIT_SHELL_CLOSE ( 1 << 5 )
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#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
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#define REG_BIT_SW_HOME_RELEASE ( 1 << 3 )
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#define REG_BIT_SW_HOME_CLICK ( 1 << 2 )
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#define REG_BIT_SW_POW_HOLD ( 1 << 1 )
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#define REG_BIT_SW_POW_CLICK ( 1 << 0 )
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// VREG_C_IRQ1
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#define REG_BIT_BT_CHG_START ( 1 << 7 )
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#define REG_BIT_BT_CHG_STOP ( 1 << 6 )
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#define REG_BIT_BT_REMAIN ( 1 << 5 )
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#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
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#define REG_BIT_ACC_ACK ( 1 << 3 )
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#define REG_BIT_RTC_ALARM ( 1 << 2 )
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#define REG_BIT_BT_DC_CONNECT ( 1 << 1 )
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#define REG_BIT_BT_DC_DISC ( 1 << 0 )
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// VREG_C_IRQ2
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#define REG_BIT_TWL_VER_READ ( 1 << 7 )
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//#define REG_BIT_TWL_SNDVOL_CHANGE ( 1 << 6 ) 廃止
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#define REG_BIT_SLIDE_VOL_ACROSS_TWL_BOUNDARY ( 1 << 6 )
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#define REG_BIT_TWL_BL_U_ON ( 1 << 5 )
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#define REG_BIT_TWL_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_TWL_BL_L_ON ( 1 << 3 )
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#define REG_BIT_TWL_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_TWL_OFF_REQ ( 1 << 1 )
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#define REG_BIT_TWL_RESET_REQ ( 1 << 0 )
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// VREG_C_IRQ3
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#define REG_BIT_BL_U_ON ( 1 << 5 )
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#define REG_BIT_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_BL_L_ON ( 1 << 3 )
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#define REG_BIT_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_LCD_ON ( 1 << 1 )
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#define REG_BIT_LCD_OFF ( 1 << 0 )
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// そのうちどこかに...
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//#define REG_BIT_VR_3D_CHANGE ( 1 << 7 )
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// VREG_C_COMMAND0
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//#define REG_BIT_CMD_LCD_ON ( 1 << 7 )
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//#define REG_BIT_CMD_LCD_OFF ( 1 << 6 )
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//#define REG_BIT_CMD_BL_ON ( 1 << 5 )
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//#define REG_BIT_CMD_BL_OFF ( 1 << 4 )
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#define REG_BIT_GOING_TO_SLEEP ( 1 << 4 )
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#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
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#define REG_BIT_RESET2_REQ ( 1 << 2 )
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#define REG_BIT_RESET1_REQ ( 1 << 1 )
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#define REG_BIT_OFF_REQ ( 1 << 0 )
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// VREG_C_COMMAND1 (TWLに割り込みを入れる)
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// 未使用 ( 1 << 7 )
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// 未使用 ( 1 << 6 )
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#define REG_BIT_SEND_TWL_VOL_CLICK ( 1 << 5 )
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#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
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#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
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#define REG_BIT_SEND_TWL_OFF_DET ( 1 << 2 )
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#define REG_BIT_SEND_TWL_RESET_DET ( 1 << 1 )
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#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
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// VREG_C_COMMAND2 液晶関係
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#define REG_BIT_CMD_BL_U_ON ( 1 << 5 )
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#define REG_BIT_CMD_BL_U_OFF ( 1 << 4 )
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#define REG_BIT_CMD_BL_L_ON ( 1 << 3 )
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#define REG_BIT_CMD_BL_L_OFF ( 1 << 2 )
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#define REG_BIT_CMD_LCD_ON ( 1 << 1 )
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#define REG_BIT_CMD_LCD_OFF ( 1 << 0 )
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#define REG_BITS_CMD_BL ( REG_BIT_CMD_BL_U_ON | REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_ON | REG_BIT_CMD_BL_L_OFF )
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// ↑TWLに通知するIRQレジスタ
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#define REG_BIT_TWL_IRQ_PWSW_DET 0x08
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#define REG_BIT_TWL_IRQ_RESET 0x01
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#define REG_BIT_TWL_IRQ_OFF 0x02
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#define REG_BIT_TWL_IRQ_BT_LOW 0x20
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#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
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#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
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// CODEC上のPMIC NTR の代理レジスタ
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#define REG_BIT_TWL_REQ_OFF ( 1 << 6 )
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#define REG_BIT_TWL_REQ_BL_U ( 1 << 3 )
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#define REG_BIT_TWL_REQ_BL_L ( 1 << 2 )
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#define REG_BIT_TWL_REQ_RESET ( 1 << 0 )
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// VREG_C_LED_NOTIFY_FLAG
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#define REG_BIT_IN_LOOP ( 1 << 0 )
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// HAL bitfields 0
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#define REG_BIT_HAL0_PM_EXTDC_n ( 1 << 7 )
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#define REG_BIT_HAL0_BT_IN_CHG_n ( 1 << 6 )
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//#define REG_BIT_HAL0_PM_IRQ_n // 使わない
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#define REG_BIT_HAL0_RSV_5 ( 1 << 5 )
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#define REG_BIT_HAL0_WL_TX ( 1 << 4 )
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#define REG_BIT_HAL0_SHELL_OPEN ( 1 << 3 ) // statusにあります
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#define REG_BIT_HAL0_SW_WIFI_n ( 1 << 2 )
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#define REG_BIT_HAL0_SW_HOME_n ( 1 << 1 )
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#define REG_BIT_HAL0_SW_POW_n ( 1 << 0 )
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// HAL bitfields 1
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#define REG_BIT_HAL1_DIPSW_1 ( 1 << 3 )
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#define REG_BIT_HAL1_DIPSW_0 ( 1 << 2 )
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#define REG_BIT_HAL1_HW_DET_1 ( 1 << 1 )
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#define REG_BIT_HAL1_HW_DET_0 ( 1 << 0 )
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// VREG_C_WIFI_CALIB
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#define REG_BIT_WIFI_CALIB_32K_HI_Z ( 1 << 1 )
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#define REG_BIT_WIFI_CALIB_RSTS_AST ( 1 << 0 )
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/*
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テンプレ
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#define REG_BIT_ ( 1 << 7 )
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#define REG_BIT_ ( 1 << 6 )
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#define REG_BIT_ ( 1 << 5 )
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#define REG_BIT_ ( 1 << 4 )
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#define REG_BIT_ ( 1 << 3 )
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#define REG_BIT_ ( 1 << 2 )
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#define REG_BIT_ ( 1 << 1 )
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#define REG_BIT_ ( 1 << 0 )
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*/
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/*============================================================================*/
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extern u8 vreg_ctr[];
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/*============================================================================*/
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enum VREG_C_ADRS
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{ // 未定義アドレスへ書き込んだ際の動作は不定
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VREG_C_MCU_VER_MAJOR = 0x00,
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VREG_C_MCU_VER_MINOR,
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VREG_C_MCU_STATUS,
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VREG_C_VCOM_T = 0x03,
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VREG_C_VCOM_B,
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VREG_C_DBG01 = 0x05,
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VREG_C_DBG02,
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VREG_C_DBG03,
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VREG_C_3D = 0x08,
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VREG_C_SND_VOL,
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VREG_C_BT_TEMP,
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VREG_C_BT_REMAIN,
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VREG_C_BT_REMAIN_FINE,
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VREG_C_BT_VOLTAGE,
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VREG_C_STATUS_1 = 0x0E,
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VREG_C_STATUS = 0x0F,
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VREG_C_IRQ0 = 0x10,
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VREG_C_IRQ1,
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VREG_C_IRQ2,
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VREG_C_IRQ3,
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VREG_C_IRQ4,
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VREG_C_IRQ_MASK0 = 0x18,
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VREG_C_IRQ_MASK1,
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VREG_C_IRQ_MASK2,
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VREG_C_IRQ_MASK3,
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VREG_C_IRQ_MASK4,
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VREG_C_COMMAND0 = 0x20,
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VREG_C_COMMAND1,
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VREG_C_COMMAND2,
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VREG_C_COMMAND3, // 'r' でマイコンリセット、 'w' でWDTリセット
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VREG_C_OFF_DELAY = 0x24,
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// VREG_C_VOL_DIGITAL = 0x25, // todo 消すよ
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// VREG_C_VOL_OPTION,
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VREG_C_VOL_ADC_RAW = 0x27,
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VREG_C_LED_BRIGHT = 0x28,
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VREG_C_LED_POW,
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VREG_C_LED_WIFI,
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VREG_C_LED_CAM,
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VREG_C_LED_3D,
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VREG_C_LED_NOTIFY_DATA,
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VREG_C_LED_NOTIFY_FLAG,
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VREG_C_RBR_CONTROL = 0x2F, // 廃止
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VREG_C_RTC_SEC = 0x30,
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VREG_C_RTC_MIN,
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VREG_C_RTC_HOUR,
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VREG_C_RTC_YOBI,
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VREG_C_RTC_DAY,
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VREG_C_RTC_MONTH,
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VREG_C_RTC_YEAR,
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VREG_C_RTC_COMP,
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VREG_C_RTC_ALARM_MIN = 0x38,
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VREG_C_RTC_ALARM_HOUR,
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VREG_C_RTC_ALARM_DAY,
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VREG_C_RTC_ALARM_MONTH,
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VREG_C_RTC_ALARM_YEAR,
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VREG_C_RTC_SEC_FINE_L,
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VREG_C_RTC_SEC_FINE_H,
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VREG_C_WIFI_CALIB = 0x3F,
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VREG_C_ACC_CONFIG = 0x40,
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VREG_C_ACC_R_ADRS,
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VREG_C_ACC_RESERVE,
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VREG_C_ACC_W_ADRS,
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VREG_C_ACC_W_BUF, // r,w 共用
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VREG_C_ACC_XL = 0x45,
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VREG_C_ACC_XH,
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VREG_C_ACC_YL,
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VREG_C_ACC_YH,
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VREG_C_ACC_ZL,
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VREG_C_ACC_ZH,
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VREG_C_ACC_HOSU_L = 0x4B,
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VREG_C_ACC_HOSU_M,
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VREG_C_ACC_HOSU_H,
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VREG_C_ACC_HOSU_SETTING,
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VREG_C_ACC_HOSU_HIST = 0x4F,
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VREG_C_ACC_HOSU_HOUR_BOUNDARY = 0x50,
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VREG_C_ACC_HOSU_HOUR_BOUNDARY_SEC,
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VREG_C_HAL_OVW_CONT0 = 0x52,
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VREG_C_HAL_OVW_DAT0,
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VREG_C_HAL_OVW_CONT1, // reserved
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VREG_C_HAL_OVW_DAT1, // reserved
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VREG_C_HAL_OVW_BT_FUEL = 0x56,
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VREG_C_HAL_OVW_BT_VOLTAGE,
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VREG_C_VOL_CAL_MIN = 0x58,
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VREG_C_VOL_CAL_MAX,
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VREG_C_HAL_OVW_TEMPERATURE = 0x5A,
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VREG_C_ENDMARK_
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};
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// ↓間は抜けにして、メモリも確保しないために 別に define してる
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#define VREG_CX_INFO 0x7F
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#define VREG_CX_FREE_ADRS 0x60
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#define VREG_CX_FREE_DATA 0x61
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// VREG_C_AMBIENT_BRIGHTNESS = 0xXX,
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/*============================================================================*/
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void vreg_ctr_init( );
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void vreg_ctr_reset( );
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void vreg_ctr_write( u8 adrs, u8 data );
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u8 vreg_ctr_read( u8 phy_adrs );
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void vreg_ctr_after_read( u8 adrs, u8 data );
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void set_irq( u8 irqreg, u8 irq_flg );
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#define is_wifi_calib_resets_ast ( vreg_ctr[ VREG_C_WIFI_CALIB ] & REG_BIT_WIFI_CALIB_RSTS_AST )
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#define vreg_stop_acc ( vreg_ctr[ VREG_C_ACC_CONFIG ] &= ~( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ ) )
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#define vreg_set_acc_error ( vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR )
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#define is_acc_on ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_ACQ )
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#define is_pedo_on ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_HOSU )
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#define is_mgic_error ( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_MGIC_ERR )
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#define vreg_set_mgic_error ( vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_MGIC_ERR )
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#define vreg_clear_mgic_error ( vreg_ctr[ VREG_C_STATUS_1 ] &= ~(REG_BIT_MGIC_ERR) )
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#define is_bt_charging ( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARGE )
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#define is_shell_open ( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_OPEN )
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#endif
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