mirror of
https://github.com/rvtr/ctr_mcu.git
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dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
1321 lines
41 KiB
NASM
1321 lines
41 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_sys.c
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; In-file : task_sys.c
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; Asm-file : inter_asm\task_sys.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 0C7H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, task_sys.c
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$DGS MOD_NAM, task_sys, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 047H
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$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 041H, 01H
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$DGS LAB_SYM, bs_F0057, U, U, 00H, 06H, 00H, 00H
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$DGS LAB_SYM, es_F0057, U, U, 00H, 06H, 00H, 00H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _tsk_sys, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0A6H, 00H, 00H
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$DGS BEG_FUN, ??bf_tsk_sys, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 023H, 00H, 050H
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$DGS STA_SYM, _timeout, ?L0003, U, 0CH, 03H, 00H, 00H
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$DGS BEG_BLK, ??bb00_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 05H, 00H, 052H
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$DGS BEG_BLK, ??bb01_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0BH, 00H, 054H
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$DGS BEG_BLK, ??bb02_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 010H, 00H, 058H
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$DGS END_BLK, ??eb02_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 012H
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$DGS BEG_BLK, ??bb03_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 014H, 00H, 05CH
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$DGS END_BLK, ??eb03_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 016H
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$DGS BEG_BLK, ??bb04_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 018H, 00H, 060H
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$DGS END_BLK, ??eb04_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01CH
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$DGS BEG_BLK, ??bb05_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01FH, 00H, 066H
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$DGS END_BLK, ??eb05_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 022H
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$DGS END_BLK, ??eb01_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 029H
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$DGS BEG_BLK, ??bb06_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 034H, 00H, 06AH
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$DGS END_BLK, ??eb06_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 039H
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$DGS BEG_BLK, ??bb07_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 048H, 00H, 06EH
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$DGS END_BLK, ??eb07_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 04BH
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$DGS BEG_BLK, ??bb08_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 04DH, 00H, 072H
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$DGS END_BLK, ??eb08_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 051H
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$DGS BEG_BLK, ??bb09_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 065H, 00H, 076H
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$DGS END_BLK, ??eb09_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 067H
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$DGS BEG_BLK, ??bb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 069H, 00H, 07AH
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$DGS END_BLK, ??eb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 069H
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$DGS BEG_BLK, ??bb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 084H, 00H, 07EH
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$DGS END_BLK, ??eb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 087H
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$DGS BEG_BLK, ??bb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 092H, 00H, 082H
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$DGS END_BLK, ??eb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0A1H
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$DGS BEG_BLK, ??bb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0A9H, 00H, 086H
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$DGS END_BLK, ??eb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0ABH
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$DGS BEG_BLK, ??bb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0B1H, 00H, 08AH
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$DGS END_BLK, ??eb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0B1H
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$DGS BEG_BLK, ??bb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0C4H, 00H, 08EH
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$DGS END_BLK, ??eb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0C7H
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$DGS BEG_BLK, ??bb10_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0DEH, 00H, 090H
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$DGS BEG_BLK, ??bb11_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0E5H, 00H, 096H
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$DGS END_BLK, ??eb11_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0EAH
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$DGS END_BLK, ??eb10_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0ECH
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$DGS BEG_BLK, ??bb12_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0EEH, 00H, 098H
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$DGS BEG_BLK, ??bb13_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0F2H, 00H, 09EH
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$DGS END_BLK, ??eb13_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0F2H
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$DGS END_BLK, ??eb12_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0110H
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$DGS BEG_BLK, ??bb14_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0114H, 00H, 00H
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$DGS END_BLK, ??eb14_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0117H
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$DGS END_BLK, ??eb00_tsk_sys, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0119H
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$DGS END_FUN, ??ef_tsk_sys, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 011AH
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$DGS STA_SYM, _chk_emergencyExit, U, U, 01H, 03H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 0C1H, 00H, 00H
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$DGS BEG_FUN, ??bf_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0143H, 00H, 0ABH
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$DGS STA_SYM, _state, ?L0048, U, 04H, 03H, 00H, 00H
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$DGS BEG_BLK, ??bb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 0ADH
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$DGS BEG_BLK, ??bb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 08H, 00H, 0B1H
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$DGS END_BLK, ??eb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0CH
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$DGS BEG_BLK, ??bb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0EH, 00H, 0B3H
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$DGS BEG_BLK, ??bb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 010H, 00H, 0BBH
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$DGS END_BLK, ??eb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 017H
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$DGS END_BLK, ??eb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 018H
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$DGS END_BLK, ??eb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 019H
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$DGS BEG_BLK, ??bb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01BH, 00H, 00H
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$DGS END_BLK, ??eb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01DH
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$DGS END_FUN, ??ef_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 01FH
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$DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 026H, 01H, 02H
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$DGS AUX_FUN, 041H, U, U, 0C7H, 00H, 00H
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$DGS BEG_FUN, ??bf_tski_firm_update, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0181H, 00H, 0C7H
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$DGS END_FUN, ??ef_tski_firm_update, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 04H
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$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 02H, 00H, 00H
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$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _LED_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _LED_stop, U, U, 01H, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 02H, 00H, 00H
|
||
$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
$DGS GLV_SYM, _firm_update, U, U, 0CH, 02H, 01H, 02H
|
||
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
|
||
EXTRN _iic_mcu_write_a_byte
|
||
EXTRN _system_status
|
||
EXTRN _SW_pow_count
|
||
EXTRN _iic_mcu_start
|
||
EXTRN _PM_init
|
||
EXTRN _PM_sys_pow_on
|
||
EXTRN _iic_mcu_stop
|
||
EXTRN _PM_LCD_vcom_set
|
||
EXTRN _vreg_ctr
|
||
EXTRN _LED_init
|
||
EXTRN _IIC_ctr_Init
|
||
EXTRN _set_irq
|
||
EXTRN _IIC_twl_Init
|
||
EXTRN _wait_ms
|
||
EXTRN _LED_stop
|
||
EXTRN _IIC_ctr_Stop
|
||
EXTRN _IIC_twl_Stop
|
||
EXTRN _PM_sys_pow_off
|
||
EXTRN _SW_wifi_count
|
||
EXTRN _iic_mcu_read_a_byte
|
||
EXTRN _do_command0
|
||
EXTRN _renge_task_immed_add
|
||
EXTRN _firm_update
|
||
EXTBIT _renge_task_interval_run_force
|
||
PUBLIC _tsk_sys
|
||
PUBLIC _tski_firm_update
|
||
|
||
@@BITS BSEG
|
||
|
||
@@CNST CSEG MIRRORP
|
||
_lpf_coeff: DB 01H ; 1
|
||
DB 02H ; 2
|
||
DB 02H ; 2
|
||
DB 03H ; 3
|
||
DB 03H ; 3
|
||
DB 02H ; 2
|
||
DB 00H ; 0
|
||
DB 0FEH ; 254
|
||
DB 0FBH ; 251
|
||
DB 0F7H ; 247
|
||
DB 0F3H ; 243
|
||
DB 0F0H ; 240
|
||
DB 0F0H ; 240
|
||
DB 0F3H ; 243
|
||
DB 0FAH ; 250
|
||
DB 04H ; 4
|
||
DB 012H ; 18
|
||
DB 025H ; 37
|
||
DB 038H ; 56
|
||
DB 04DH ; 77
|
||
DB 05FH ; 95
|
||
DB 06EH ; 110
|
||
DB 077H ; 119
|
||
DB 07AH ; 122
|
||
DB 077H ; 119
|
||
DB 06EH ; 110
|
||
DB 05FH ; 95
|
||
DB 04DH ; 77
|
||
DB 038H ; 56
|
||
DB 025H ; 37
|
||
DB 012H ; 18
|
||
DB 04H ; 4
|
||
DB 0FAH ; 250
|
||
DB 0F3H ; 243
|
||
DB 0F0H ; 240
|
||
DB 0F0H ; 240
|
||
DB 0F3H ; 243
|
||
DB 0F7H ; 247
|
||
DB 0FBH ; 251
|
||
DB 0FEH ; 254
|
||
DB 00H ; 0
|
||
DB 02H ; 2
|
||
DB 03H ; 3
|
||
DB 03H ; 3
|
||
DB 02H ; 2
|
||
DB 02H ; 2
|
||
DB 01H ; 1
|
||
DB (1)
|
||
|
||
@@R_INIT CSEG UNIT64KP
|
||
DB 00H ; 0
|
||
DB (1)
|
||
|
||
@@INIT DSEG BASEP
|
||
?L0003: DS (1)
|
||
DS (1)
|
||
|
||
@@DATA DSEG BASEP
|
||
?L0048: DS (2)
|
||
|
||
@@R_INIS CSEG UNIT64KP
|
||
|
||
@@INIS DSEG SADDRP
|
||
|
||
@@DATS DSEG SADDRP
|
||
|
||
@@CNSTL CSEG PAGE64KP
|
||
|
||
@@RLINIT CSEG UNIT64KP
|
||
|
||
@@INITL DSEG UNIT64KP
|
||
|
||
@@DATAL DSEG UNIT64KP
|
||
|
||
@@CALT CSEG CALLT0
|
||
|
||
; Sub-Routines created by CC78K0R
|
||
|
||
ROM_CODE CSEG BASE
|
||
bs_F0057:
|
||
push ax ;[INF] 1, 1
|
||
mov x,#05H ; 5 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#084H ; 132 ;[INF] 2, 1
|
||
call !_iic_mcu_write_a_byte ;[INF] 3, 3
|
||
addw sp,#04H ; 4 ;[INF] 2, 1
|
||
ret ;[INF] 1, 6
|
||
es_F0057:
|
||
|
||
; *** Sub-Routine Information ***
|
||
;
|
||
; $SUB bs_F0057
|
||
; CODE SIZE= 12 bytes
|
||
|
||
; End of Sub-Routines
|
||
|
||
; line 1 : #pragma SFR
|
||
; line 2 : #pragma NOP
|
||
; line 3 : #pragma HALT
|
||
; line 4 : #pragma STOP
|
||
; line 5 :
|
||
; line 6 : #include "incs.h"
|
||
; line 7 :
|
||
; line 8 : #include "i2c_twl.h"
|
||
; line 9 : #include "i2c_ctr.h"
|
||
; line 10 : #include "led.h"
|
||
; line 11 : #include "accero.h"
|
||
; line 12 : #include "pm.h"
|
||
; line 13 : #include "rtc.h"
|
||
; line 14 : #include "sw.h"
|
||
; line 15 : #include "adc.h"
|
||
; line 16 :
|
||
; line 17 :
|
||
; line 18 :
|
||
; line 19 : //=========================================================
|
||
; line 20 : static void chk_emergencyExit();
|
||
; line 21 :
|
||
; line 22 :
|
||
; line 23 :
|
||
; line 24 : //=========================================================
|
||
; line 25 :
|
||
; line 26 :
|
||
; line 27 :
|
||
; line 28 : /* ========================================================
|
||
; line 29 : <20>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŕK<C595>v<EFBFBD>Ȃ<EFBFBD><C882><EFBFBD>
|
||
; line 30 : <20>E<EFBFBD>ȓd<C893>͂ɓ<CD82><C993><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 31 : <20>@system_status.pwr_state == OFF_TRIG <20>ŁA<C581><41><EFBFBD>̃^<5E>X<EFBFBD>N<EFBFBD><4E><EFBFBD>Ă<C482><CE82><EFBFBD>
|
||
; <20>ƁA
|
||
; line 32 : <20>ȓd<C893>̓<EFBFBD><CD83>[<5B>h<EFBFBD>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
; line 33 : ======================================================== */
|
||
; line 34 : void tsk_sys( )
|
||
; line 35 : {
|
||
|
||
ROM_CODE CSEG BASE
|
||
_tsk_sys:
|
||
$DGL 1,75
|
||
??bf_tsk_sys:
|
||
; line 36 : static u8 timeout = 0;
|
||
; line 37 :
|
||
; line 38 : switch ( system_status.pwr_state )
|
||
$DGL 0,4
|
||
mov a,!_system_status ;[INF] 3, 1
|
||
sarw ax,8 ;[INF] 2, 1
|
||
onew bc ;[INF] 1, 1
|
||
subw ax,#00H ; 0 ;[INF] 3, 1
|
||
sknz ;[INF] 2, 1
|
||
br !?L0010 ;[INF] 3, 3
|
||
subw ax,bc ;[INF] 1, 1
|
||
bz $?L0005 ;[INF] 2, 4
|
||
subw ax,bc ;[INF] 1, 1
|
||
bz $?L0006 ;[INF] 2, 4
|
||
subw ax,bc ;[INF] 1, 1
|
||
sknz ;[INF] 2, 1
|
||
br !?L0007 ;[INF] 3, 3
|
||
subw ax,bc ;[INF] 1, 1
|
||
sknz ;[INF] 2, 1
|
||
br !?L0008 ;[INF] 3, 3
|
||
subw ax,bc ;[INF] 1, 1
|
||
sknz ;[INF] 2, 1
|
||
br !?L0009 ;[INF] 3, 3
|
||
subw ax,bc ;[INF] 1, 1
|
||
sknz ;[INF] 2, 1
|
||
br !?L0011 ;[INF] 3, 3
|
||
br !?L0038 ;[INF] 3, 3
|
||
; line 39 : {
|
||
??bb00_tsk_sys:
|
||
; line 40 : case OFF: //-------------------------------
|
||
; ------------------------
|
||
?L0005:
|
||
; line 41 : // <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD>ȂǂŊ<C782><C58A>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>X<EFBFBD><58><EFBFBD>[<5B>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>ɗ<EFBFBD><C997>܂<EFBFBD><DC82>B
|
||
; line 42 :
|
||
; line 43 : #ifndef _PARRADIUM_
|
||
; line 44 : switch ( system_status.poweron_reason )
|
||
$DGL 0,10
|
||
mov a,!_system_status+1 ;[INF] 3, 1
|
||
sarw ax,8 ;[INF] 2, 1
|
||
subw ax,#02H ; 2 ;[INF] 3, 1
|
||
bz $?L0015 ;[INF] 2, 4
|
||
; line 45 : {
|
||
??bb01_tsk_sys:
|
||
; line 46 : default:
|
||
; line 47 : // <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>œd<C593><64>on
|
||
; line 48 :
|
||
; line 49 : if( SW_pow_count != 0 )
|
||
$DGL 0,15
|
||
cmp0 !_SW_pow_count ;[INF] 3, 1
|
||
bz $?L0018 ;[INF] 2, 4
|
||
; line 50 : {
|
||
??bb02_tsk_sys:
|
||
; line 51 : timeout = 0;
|
||
$DGL 0,17
|
||
clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
??eb02_tsk_sys:
|
||
; line 52 : }
|
||
$DGL 0,18
|
||
br $?L0019 ;[INF] 2, 3
|
||
?L0018:
|
||
; line 53 : else
|
||
; line 54 : {
|
||
??bb03_tsk_sys:
|
||
; line 55 : timeout += 1;
|
||
$DGL 0,21
|
||
inc !?L0003 ; timeout ;[INF] 3, 2
|
||
??eb03_tsk_sys:
|
||
; line 56 : }
|
||
?L0019:
|
||
; line 57 : if( timeout > 127 )
|
||
$DGL 0,23
|
||
mov a,!?L0003 ; timeout ;[INF] 3, 1
|
||
addw ax,ax ;[INF] 1, 1
|
||
bnc $?L0020 ;[INF] 2, 4
|
||
; line 58 : {
|
||
??bb04_tsk_sys:
|
||
; line 59 : system_status.pwr_state = OFF_TRIG; // <20>X<EFBFBD>C<EFBFBD>b
|
||
; <20>`<60>̓m<CD83>C<EFBFBD>Y<EFBFBD><59><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD>Q<EFBFBD><51><EFBFBD>B
|
||
$DGL 0,25
|
||
clrb !_system_status ;[INF] 3, 1
|
||
; line 60 : renge_task_interval_run_force = 1;
|
||
$DGL 0,26
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 61 : return;
|
||
$DGL 0,27
|
||
ret ;[INF] 1, 6
|
||
??eb04_tsk_sys:
|
||
; line 62 : }
|
||
?L0020:
|
||
; line 63 :
|
||
; line 64 : if( SW_pow_count < 3 )
|
||
$DGL 0,30
|
||
cmp !_SW_pow_count,#03H ; 3 ;[INF] 4, 1
|
||
sknc ;[INF] 2, 1
|
||
br !?L0004 ;[INF] 3, 3
|
||
; line 65 : {
|
||
??bb05_tsk_sys:
|
||
; line 66 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>̗l<CC97>q<EFBFBD><71><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 67 : return;
|
||
??eb05_tsk_sys:
|
||
; line 68 : }
|
||
; line 69 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 70 : system_status.poweron_reason = PWSW;
|
||
$DGL 0,36
|
||
oneb !_system_status+1 ;[INF] 3, 1
|
||
; line 71 : break;
|
||
; line 72 :
|
||
; line 73 : case ( RTC_ALARM ):
|
||
; line 74 : break;
|
||
??eb01_tsk_sys:
|
||
; line 75 : }
|
||
?L0015:
|
||
; line 76 :
|
||
; line 77 : timeout = 0;
|
||
$DGL 0,43
|
||
clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
; line 78 :
|
||
; line 79 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD> //
|
||
; line 80 : iic_mcu_start( );
|
||
$DGL 0,46
|
||
call !_iic_mcu_start ;[INF] 3, 3
|
||
; line 81 :
|
||
; line 82 : // <20><><EFBFBD>œd<C593>r<EFBFBD>c<EFBFBD><63>IC<49>̋N<CC8B><4E><EFBFBD>҂<EFBFBD><D282>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD>Ȃǂ<C882><C782><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
; line 83 : PM_init( ); // <20>d<EFBFBD>r<EFBFBD>c<EFBFBD><63>IC<49>̐ݒ<CC90>
|
||
$DGL 0,49
|
||
call !_PM_init ;[INF] 3, 3
|
||
; line 84 :
|
||
; line 85 : if( PM_sys_pow_on( ) != ERR_SUCCESS )
|
||
$DGL 0,51
|
||
call !_PM_sys_pow_on ;[INF] 3, 3
|
||
cmp0 c ;[INF] 1, 1
|
||
bz $?L0024 ;[INF] 2, 4
|
||
; line 86 : { // <20>d<EFBFBD><64><EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD>G<C283><47><EFBFBD>[
|
||
??bb06_tsk_sys:
|
||
; line 87 : renge_task_interval_run_force = 1;
|
||
$DGL 0,53
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 88 : iic_mcu_stop( );
|
||
$DGL 0,54
|
||
call !_iic_mcu_stop ;[INF] 3, 3
|
||
; line 89 : system_status.pwr_state = OFF_TRIG;
|
||
$DGL 0,55
|
||
clrb !_system_status ;[INF] 3, 1
|
||
; line 90 : return;
|
||
$DGL 0,56
|
||
ret ;[INF] 1, 6
|
||
??eb06_tsk_sys:
|
||
; line 91 : }
|
||
?L0024:
|
||
; line 92 : PM_CHG_TIMEOUT_ENABLE();
|
||
; line 93 : // IRQ0_active;
|
||
; line 94 :
|
||
; line 95 : #else
|
||
; line 96 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR;
|
||
; line 97 : system_status.poweron_reason = PWSW;
|
||
; line 98 : #endif // _PARADDIUM_
|
||
; line 99 :
|
||
; line 100 : PM_LCD_vcom_set( ); // LCD<43>̑Ό<CC91><CE8C>d<EFBFBD><64><EFBFBD>l<EFBFBD>ȂǏ<C882><C78F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
$DGL 0,66
|
||
call !_PM_LCD_vcom_set ;[INF] 3, 3
|
||
; line 101 : #ifdef _PMIC_TWL_
|
||
; line 102 : PM_TEG_LCD_dis( 0 );
|
||
; line 103 : #endif
|
||
; line 104 :
|
||
; line 105 : if( system_status.poweron_reason == PWSW )
|
||
$DGL 0,71
|
||
cmp !_system_status+1,#01H ; 1 ;[INF] 4, 1
|
||
bnz $?L0026 ;[INF] 2, 4
|
||
; line 106 : {
|
||
??bb07_tsk_sys:
|
||
; line 107 : // <20>d<EFBFBD><64><EFBFBD>{<7B>^<5E><><EFBFBD>ł<EFBFBD>on<6F>̎<EFBFBD><CC8E>́ALED<45><44><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 108 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO;
|
||
$DGL 0,74
|
||
clrb !_vreg_ctr+41 ;[INF] 3, 1
|
||
??eb07_tsk_sys:
|
||
; line 109 : }
|
||
$DGL 0,75
|
||
br $?L0027 ;[INF] 2, 3
|
||
?L0026:
|
||
; line 110 : else
|
||
; line 111 : {
|
||
??bb08_tsk_sys:
|
||
; line 112 : // <20>Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>ALED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԂŋN<C58B><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 113 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF;
|
||
$DGL 0,79
|
||
mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1
|
||
??eb08_tsk_sys:
|
||
; line 114 : // todo?
|
||
; line 115 : }
|
||
?L0027:
|
||
; line 116 : system_status.pwr_state = ON_TRIG;
|
||
$DGL 0,82
|
||
mov !_system_status,#02H ; 2 ;[INF] 4, 1
|
||
; line 117 : // <20><><EFBFBD><EFBFBD><EFBFBD>܂ŗ<DC82><C597><EFBFBD><EFBFBD>ƁA<C681>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>m<EFBFBD><6D>
|
||
; line 118 : break;
|
||
$DGL 0,84
|
||
ret ;[INF] 1, 6
|
||
; line 119 :
|
||
; line 120 : case ON_TRIG: //-------------------------------
|
||
; ------------------------
|
||
?L0006:
|
||
; line 121 :
|
||
; line 122 : LED_init( );
|
||
$DGL 0,88
|
||
call !_LED_init ;[INF] 3, 3
|
||
; line 123 :
|
||
; line 124 : PU7 = 0b00011101; // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_
|
||
; EXTDC_n
|
||
$DGL 0,90
|
||
mov !PU7,#01DH ; 29 ;[INF] 4, 1
|
||
; line 125 :
|
||
; line 126 : IIC_ctr_Init( );
|
||
$DGL 0,92
|
||
call !_IIC_ctr_Init ;[INF] 3, 3
|
||
; line 127 : if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT
|
||
; _RESET )
|
||
; line 128 : /*
|
||
; line 129 : if( vreg_ctr[ VREG_C_IRQ0 ]
|
||
; line 130 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
; line 131 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
; line 132 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
; line 133 : */
|
||
; line 134 : != 0 )
|
||
$DGL 0,100
|
||
mov a,!_vreg_ctr+2 ;[INF] 3, 1
|
||
and a,#02H ; 2 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0028 ;[INF] 2, 4
|
||
; line 135 : {
|
||
??bb09_tsk_sys:
|
||
; line 136 : set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
|
||
$DGL 0,102
|
||
movw ax,#080H ; 128 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#010H ; 16 ;[INF] 2, 1
|
||
call !_set_irq ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
??eb09_tsk_sys:
|
||
; line 137 : }
|
||
?L0028:
|
||
; line 138 : IIC_twl_Init( );
|
||
$DGL 0,104
|
||
call !_IIC_twl_Init ;[INF] 3, 3
|
||
; line 139 : RTC_32k_on( );
|
||
$DGL 0,105
|
||
??bb0A_tsk_sys:
|
||
set1 RTCC0.4 ;[INF] 3, 2
|
||
??eb0A_tsk_sys:
|
||
; line 140 :
|
||
; line 141 : KRM = 0b00000000;
|
||
$DGL 0,107
|
||
clrb !KRM ;[INF] 3, 1
|
||
; line 142 :
|
||
; line 143 : system_status.poweron_reason = NONE;
|
||
$DGL 0,109
|
||
clrb !_system_status+1 ;[INF] 3, 1
|
||
; line 144 : renge_task_interval_run_force = 1;
|
||
$DGL 0,110
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 145 :
|
||
; line 146 : MK0 = INT_MSK0_RSV;
|
||
$DGL 0,112
|
||
movw MK0,#0EF3FH ; -4289 ;[INF] 4, 1
|
||
; line 147 : MK1 = INT_MSK1_RSV;
|
||
$DGL 0,113
|
||
movw MK1,#0F0F6H ; -3850 ;[INF] 4, 1
|
||
; line 148 : #ifdef _MCU_BSR_
|
||
; line 149 : // MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT
|
||
; _MSK2_CODEC_PMIRQ );
|
||
; line 150 : // PMK21 = 0; // wifi <20>g<EFBFBD><67><EFBFBD>Ȃ<EFBFBD>
|
||
; line 151 : PMK6 = 0; // pm_irq
|
||
$DGL 0,117
|
||
clr1 MK2L.3 ;[INF] 3, 2
|
||
; line 152 : #else
|
||
; line 153 : MK2L = ~INT_MSK2_WIFI_TX_KE3;
|
||
; line 154 : #endif
|
||
; line 155 :
|
||
; line 156 : system_status.reboot = 0;
|
||
$DGL 0,122
|
||
clr1 !_system_status+2.3 ;[INF] 4, 2
|
||
; line 157 : system_status.pwr_state = ON;
|
||
$DGL 0,123
|
||
mov !_system_status,#03H ; 3 ;[INF] 4, 1
|
||
; line 158 : break;
|
||
$DGL 0,124
|
||
ret ;[INF] 1, 6
|
||
; line 159 :
|
||
; line 160 : case ON: //-------------------------------
|
||
; --------------
|
||
?L0007:
|
||
; line 161 : // PMIC<49>ɂ<EFBFBD><C982>鋭<EFBFBD><E98BAD><EFBFBD>d<EFBFBD><64><EFBFBD>f<EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N
|
||
; line 162 : // <20>f<EFBFBD>o<EFBFBD>b<EFBFBD>K<EFBFBD><4B>reset1<74><31><EFBFBD>A<EFBFBD>T<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>邱<EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD>̂Ƃ<CC82><C682>͑S
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
; line 163 : chk_emergencyExit();
|
||
$DGL 0,129
|
||
call !_chk_emergencyExit ;[INF] 3, 3
|
||
; line 164 :
|
||
; line 165 : // SLP<4C>Ď<EFBFBD>
|
||
; line 166 : if( SLP_REQ ){
|
||
$DGL 0,132
|
||
bf P12.0,$?L0030 ;[INF] 4, 5
|
||
??bb0B_tsk_sys:
|
||
; line 167 : system_status.pwr_state = SLEEP_TRIG;
|
||
$DGL 0,133
|
||
mov !_system_status,#04H ; 4 ;[INF] 4, 1
|
||
; line 168 : renge_task_interval_run_force = 1;
|
||
$DGL 0,134
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
??eb0B_tsk_sys:
|
||
; line 169 : }
|
||
?L0030:
|
||
; line 170 : break;
|
||
$DGL 0,136
|
||
ret ;[INF] 1, 6
|
||
; line 171 :
|
||
; line 172 : case SLEEP_TRIG: //-------------------------------
|
||
; ------
|
||
?L0008:
|
||
; line 173 : PM_VDD_ecoMode();
|
||
$DGL 0,139
|
||
movw ax,#027H ; 39 ;[INF] 3, 1
|
||
call !bs_F0057 ;[INF] 3, 3
|
||
; line 174 : system_status.pwr_state = SLEEP;
|
||
$DGL 0,140
|
||
mov !_system_status,#05H ; 5 ;[INF] 4, 1
|
||
; line 175 : break;
|
||
$DGL 0,141
|
||
ret ;[INF] 1, 6
|
||
; line 176 :
|
||
; line 177 : case SLEEP: //-------------------------------
|
||
; -----------
|
||
?L0009:
|
||
; line 178 : chk_emergencyExit();
|
||
$DGL 0,144
|
||
call !_chk_emergencyExit ;[INF] 3, 3
|
||
; line 179 : // <20>X<EFBFBD><58><EFBFBD>[<5B>v<EFBFBD><76><EFBFBD>畜<EFBFBD>A
|
||
; line 180 : if( !SLP_REQ ){
|
||
$DGL 0,146
|
||
bt P12.0,$?L0032 ;[INF] 4, 5
|
||
??bb0C_tsk_sys:
|
||
; line 181 : PM_VDD_normMode();
|
||
$DGL 0,147
|
||
clrw ax ;[INF] 1, 1
|
||
call !bs_F0057 ;[INF] 3, 3
|
||
; line 182 : wait_ms( 5 ); // tdly_sw
|
||
$DGL 0,148
|
||
movw ax,#05H ; 5 ;[INF] 3, 1
|
||
call !_wait_ms ;[INF] 3, 3
|
||
; line 183 :
|
||
; line 184 : #ifdef _MODEL_CTR_
|
||
; line 185 : SLP_ACK = 1;
|
||
$DGL 0,151
|
||
set1 P7.7 ;[INF] 3, 2
|
||
; line 186 : NOP(); // <20>K<EFBFBD><4B><EFBFBD>E<EFBFBD>F<EFBFBD>C<EFBFBD>g
|
||
$DGL 0,152
|
||
nop ;[INF] 1, 1
|
||
; line 187 : NOP();
|
||
$DGL 0,153
|
||
nop ;[INF] 1, 1
|
||
; line 188 : NOP();
|
||
$DGL 0,154
|
||
nop ;[INF] 1, 1
|
||
; line 189 : NOP();
|
||
$DGL 0,155
|
||
nop ;[INF] 1, 1
|
||
; line 190 : SLP_ACK = 0;
|
||
$DGL 0,156
|
||
clr1 P7.7 ;[INF] 3, 2
|
||
; line 191 : #endif
|
||
; line 192 :
|
||
; line 193 : system_status.pwr_state = ON_TRIG;
|
||
$DGL 0,159
|
||
mov !_system_status,#02H ; 2 ;[INF] 4, 1
|
||
; line 194 : renge_task_interval_run_force = 1;
|
||
$DGL 0,160
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
??eb0C_tsk_sys:
|
||
; line 195 : }
|
||
?L0032:
|
||
; line 196 :
|
||
; line 197 : break;
|
||
$DGL 0,163
|
||
ret ;[INF] 1, 6
|
||
; line 198 :
|
||
; line 199 : case OFF_TRIG: //-------------------------------
|
||
; --------
|
||
?L0010:
|
||
; line 200 : // LED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>҂<EFBFBD>
|
||
; line 201 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF;
|
||
$DGL 0,167
|
||
mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1
|
||
; line 202 : if(( LED_duty_pow_H != 0 ) || ( LED_duty_pow_L != 0 ))
|
||
$DGL 0,168
|
||
clrw ax ;[INF] 1, 1
|
||
cmpw ax,!TDR06 ;[INF] 3, 1
|
||
bnz $?L0036 ;[INF] 2, 4
|
||
cmpw ax,!TDR07 ;[INF] 3, 1
|
||
skz ;[INF] 2, 1
|
||
?L0036:
|
||
; line 203 : {
|
||
??bb0D_tsk_sys:
|
||
; line 204 : return;
|
||
$DGL 0,170
|
||
ret ;[INF] 1, 6
|
||
??eb0D_tsk_sys:
|
||
; line 205 : }
|
||
?L0034:
|
||
; line 206 :
|
||
; line 207 : PM_CHG_TIMEOUT_ENABLE();
|
||
; line 208 : LED_stop( );
|
||
$DGL 0,174
|
||
call !_LED_stop ;[INF] 3, 3
|
||
; line 209 : IIC_ctr_Stop( );
|
||
$DGL 0,175
|
||
call !_IIC_ctr_Stop ;[INF] 3, 3
|
||
; line 210 : IIC_twl_Stop( );
|
||
$DGL 0,176
|
||
call !_IIC_twl_Stop ;[INF] 3, 3
|
||
; line 211 : RTC_32k_off();
|
||
$DGL 0,177
|
||
??bb0E_tsk_sys:
|
||
clr1 RTCC0.4 ;[INF] 3, 2
|
||
??eb0E_tsk_sys:
|
||
; line 212 :
|
||
; line 213 : vreg_ctr[VREG_C_IRQ0] = 0;
|
||
$DGL 0,179
|
||
clrb !_vreg_ctr+16 ;[INF] 3, 1
|
||
; line 214 : vreg_ctr[VREG_C_IRQ1] = 0;
|
||
$DGL 0,180
|
||
clrb !_vreg_ctr+17 ;[INF] 3, 1
|
||
; line 215 : vreg_ctr[VREG_C_IRQ2] = 0;
|
||
$DGL 0,181
|
||
clrb !_vreg_ctr+18 ;[INF] 3, 1
|
||
; line 216 : vreg_ctr[VREG_C_IRQ3] = 0;
|
||
$DGL 0,182
|
||
clrb !_vreg_ctr+19 ;[INF] 3, 1
|
||
; line 217 :
|
||
; line 218 : // <20>d<EFBFBD><64><EFBFBD>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̊<EFBFBD><CC8A>荞<EFBFBD>݃Z<DD83>b<EFBFBD>g
|
||
; line 219 : // PWSW KR3 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>L
|
||
; line 220 : // BG24 KR4
|
||
; line 221 : // <20>ӂ<EFBFBD><D382>J<EFBFBD><4A> INTP5 <20><EFBFBD><C282><EFBFBD><EFBFBD><EFBFBD>L
|
||
; line 222 : // AC<41>A<EFBFBD>_<EFBFBD>v<EFBFBD>^ INTP4 <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>L
|
||
; line 223 : // RTC
|
||
; line 224 :
|
||
; line 225 : #ifdef _PMIC_TWL_
|
||
; line 226 : PM_TEG_LCD_dis( 1 );
|
||
; line 227 : #endif
|
||
; line 228 : // IRQ0_deactive;
|
||
; line 229 : // pullup_off(); <20><>
|
||
; line 230 : {
|
||
??bb0F_tsk_sys:
|
||
; line 231 : PU5 = 0b00000011; // PM_CHG,PM_CHGERR
|
||
$DGL 0,197
|
||
mov !PU5,#03H ; 3 ;[INF] 4, 1
|
||
; line 232 : PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC
|
||
$DGL 0,198
|
||
mov !PU7,#019H ; 25 ;[INF] 4, 1
|
||
??eb0F_tsk_sys:
|
||
; line 233 : }
|
||
; line 234 :
|
||
; line 235 : PM_sys_pow_off( );
|
||
$DGL 0,201
|
||
call !_PM_sys_pow_off ;[INF] 3, 3
|
||
; line 236 :
|
||
; line 237 : KRM = ( KR_SW_POW ); // Mask <20>ł͂Ȃ<CD82><C882>AMode<64>Ȃ̂<C882><CC82><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>킵<EFBFBD><ED82B5>
|
||
$DGL 0,203
|
||
mov KRM,#08H ; 8 ;[INF] 3, 1
|
||
; line 238 : // intp20<32>n<EFBFBD>͌<EFBFBD><CD8C>ق<EFBFBD>
|
||
; line 239 : MK0 = ~( INT_MSK0_EXTDC );
|
||
$DGL 0,205
|
||
movw MK0,#0FFBFH ; -65 ;[INF] 4, 1
|
||
; line 240 : MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCALARM | INT_MSK1_RTCI
|
||
; NTVAL );
|
||
$DGL 0,206
|
||
movw MK1,#0F1FFH ; -3585 ;[INF] 4, 1
|
||
; line 241 : MK2L = 0b11111111;
|
||
$DGL 0,207
|
||
mov MK2L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 242 :
|
||
; line 243 : IF0 = 0;
|
||
$DGL 0,209
|
||
clrw ax ;[INF] 1, 1
|
||
movw IF0,ax ;[INF] 2, 1
|
||
; line 244 : IF1 = 0;
|
||
$DGL 0,210
|
||
movw IF1,ax ;[INF] 2, 1
|
||
; line 245 : IF2 = 0;
|
||
$DGL 0,211
|
||
movw IF2,ax ;[INF] 2, 1
|
||
; line 246 :
|
||
; line 247 : timeout = 0;
|
||
$DGL 0,213
|
||
clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
; line 248 :
|
||
; line 249 : system_status.pwr_state = BT_CHARGE;
|
||
$DGL 0,215
|
||
mov !_system_status,#06H ; 6 ;[INF] 4, 1
|
||
; line 250 : SW_pow_count = 0;
|
||
$DGL 0,216
|
||
clrb !_SW_pow_count ;[INF] 3, 1
|
||
; line 251 : SW_wifi_count = 0;
|
||
$DGL 0,217
|
||
clrb !_SW_wifi_count ;[INF] 3, 1
|
||
; line 252 : // no break //
|
||
; line 253 :
|
||
; line 254 : case BT_CHARGE:
|
||
?L0011:
|
||
; line 255 : if( !PM_EXTDC_n )
|
||
$DGL 0,221
|
||
bt P7.0,$?L0037 ;[INF] 4, 5
|
||
; line 256 : {
|
||
??bb10_tsk_sys:
|
||
; line 257 : // <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E>L<EFBFBD><4C><EFBFBD>F<EFBFBD>[<5B>d<EFBFBD><64><EFBFBD>x<EFBFBD>Ď<EFBFBD>
|
||
; line 258 : BT_TEMP_P = 1;
|
||
$DGL 0,224
|
||
set1 P1.7 ;[INF] 3, 2
|
||
; line 259 :
|
||
; line 260 : // <20>d<EFBFBD><64>on<6F>H
|
||
; line 261 : if( ( SW_pow_count > 3 ) || ( SW_wifi_count > 3 )
|
||
; line 262 : || ( system_status.poweron_reason == RTC_ALARM )
|
||
; )
|
||
$DGL 0,228
|
||
cmp !_SW_pow_count,#04H ; 4 ;[INF] 4, 1
|
||
bnc $?L0041 ;[INF] 2, 4
|
||
cmp !_SW_wifi_count,#04H ; 4 ;[INF] 4, 1
|
||
bnc $?L0041 ;[INF] 2, 4
|
||
cmp !_system_status+1,#02H ; 2 ;[INF] 4, 1
|
||
bnz $?L0004 ;[INF] 2, 4
|
||
?L0041:
|
||
; line 263 : {
|
||
??bb11_tsk_sys:
|
||
; line 264 : system_status.pwr_state = OFF; // <20><EFBFBD><E18AB1><EFBFBD>R<EFBFBD>L<EFBFBD>邪
|
||
; ...
|
||
$DGL 0,230
|
||
oneb !_system_status ;[INF] 3, 1
|
||
; line 265 : renge_task_interval_run_force = 1;
|
||
$DGL 0,231
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 266 : KRMK = 1;
|
||
$DGL 0,232
|
||
set1 MK1H.3 ;[INF] 3, 2
|
||
; line 267 : return;
|
||
$DGL 0,233
|
||
ret ;[INF] 1, 6
|
||
??eb11_tsk_sys:
|
||
; line 268 : }
|
||
; line 269 : return;
|
||
??eb10_tsk_sys:
|
||
; line 270 : }
|
||
?L0037:
|
||
; line 271 : else
|
||
; line 272 : {
|
||
??bb12_tsk_sys:
|
||
; line 273 : // <20>ȓd<C893>͂ֈڍs
|
||
; line 274 : BT_TEMP_P = 0;
|
||
$DGL 0,240
|
||
clr1 P1.7 ;[INF] 3, 2
|
||
; line 275 : while( RWST )
|
||
$DGL 0,241
|
||
?L0042:
|
||
bf RTCC1.1,$?L0043 ;[INF] 4, 5
|
||
; line 276 : {;}
|
||
$DGL 0,242
|
||
??bb13_tsk_sys:
|
||
??eb13_tsk_sys:
|
||
br $?L0042 ;[INF] 2, 3
|
||
?L0043:
|
||
; line 277 :
|
||
; line 278 : iic_mcu_stop( );
|
||
$DGL 0,244
|
||
call !_iic_mcu_stop ;[INF] 3, 3
|
||
; line 279 :
|
||
; line 280 : // <20><><EFBFBD>荞<EFBFBD>ݑ҂<DD91><D282>ŐQ<C590><51> //
|
||
; line 281 : RTCIMK = 1;
|
||
$DGL 0,247
|
||
set1 MK1H.2 ;[INF] 3, 2
|
||
; line 282 : #ifndef _PARRADIUM_
|
||
; line 283 :
|
||
; line 284 : #ifdef _MCU_BSR_
|
||
; line 285 : CKC = 0b00001001;
|
||
$DGL 0,251
|
||
mov CKC,#09H ; 9 ;[INF] 3, 1
|
||
; line 286 : OSMC = 0x00;
|
||
$DGL 0,252
|
||
clrb !OSMC ;[INF] 3, 1
|
||
; line 287 : #endif
|
||
; line 288 : STOP( );
|
||
$DGL 0,254
|
||
stop ;[INF] 2, 3
|
||
; line 289 : #ifdef _MCU_BSR_
|
||
; line 290 : OSMC = 0x01;
|
||
$DGL 0,256
|
||
oneb !OSMC ;[INF] 3, 1
|
||
; line 291 : CKC = 0b00001000;
|
||
$DGL 0,257
|
||
mov CKC,#08H ; 8 ;[INF] 3, 1
|
||
; line 292 : #endif
|
||
; line 293 :
|
||
; line 294 : #endif
|
||
; line 295 : RTCIMK = 0;
|
||
$DGL 0,261
|
||
clr1 MK1H.2 ;[INF] 3, 2
|
||
; line 296 : // <20>N<EFBFBD><4E><EFBFBD><EFBFBD> //
|
||
; line 297 :
|
||
; line 298 : // <20>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 299 : // <20>EKeyReturn<72><6E><EFBFBD>荞<EFBFBD>݁i<DD81>d<EFBFBD><64><EFBFBD>{<7B><><EFBFBD><EFBFBD><EFBFBD>j
|
||
; line 300 : // <20>ERTC<54>A<EFBFBD><41><EFBFBD>[<5B><>
|
||
; line 301 : // <20>E<EFBFBD>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E>}<7D><>
|
||
; line 302 : system_status.pwr_state = OFF; //
|
||
$DGL 0,268
|
||
oneb !_system_status ;[INF] 3, 1
|
||
; line 303 : renge_task_interval_run_force = 1;
|
||
$DGL 0,269
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 304 : KRMK = 1;
|
||
$DGL 0,270
|
||
set1 MK1H.3 ;[INF] 3, 2
|
||
; line 305 : return;
|
||
$DGL 0,271
|
||
ret ;[INF] 1, 6
|
||
??eb12_tsk_sys:
|
||
; line 306 : }
|
||
?L0038:
|
||
; line 307 :
|
||
; line 308 : default:
|
||
; line 309 : while( 1 )
|
||
; line 310 : {
|
||
??bb14_tsk_sys:
|
||
; line 311 : NOP( );
|
||
$DGL 0,277
|
||
nop ;[INF] 1, 1
|
||
??eb14_tsk_sys:
|
||
; line 312 : // <20><><EFBFBD>蓾<EFBFBD>Ȃ<EFBFBD><C882>X<EFBFBD>e<EFBFBD>[<5B>g
|
||
; line 313 : }
|
||
$DGL 0,279
|
||
br $?L0038 ;[INF] 2, 3
|
||
??eb00_tsk_sys:
|
||
; line 314 :
|
||
; line 315 : }
|
||
?L0004:
|
||
; line 316 : }
|
||
$DGL 0,282
|
||
??ef_tsk_sys:
|
||
ret ;[INF] 1, 6
|
||
??ee_tsk_sys:
|
||
; line 317 :
|
||
; line 318 :
|
||
; line 319 :
|
||
; line 320 : /*******************************************************//**
|
||
; line 321 : PMIC<49><43><EFBFBD>d<EFBFBD><64><EFBFBD>ُ<EFBFBD><D98F>Ŏ~<7E>߂<EFBFBD><DF82><EFBFBD><EFBFBD>m<EFBFBD>F
|
||
; line 322 : **********************************************************/
|
||
; line 323 : static void chk_emergencyExit(){
|
||
_chk_emergencyExit:
|
||
$DGL 1,166
|
||
??bf_chk_emergencyExit:
|
||
; line 324 : #ifndef _PARRADIUM_
|
||
; line 325 : static state;
|
||
; line 326 :
|
||
; line 327 : if( !RESET1_n )
|
||
$DGL 0,5
|
||
bt P0.0,$?L0049 ;[INF] 4, 5
|
||
; line 328 : {
|
||
??bb00_chk_emergencyExit:
|
||
; line 329 : if( PM_chk_LDSW( ) == 0 )
|
||
$DGL 0,7
|
||
movw ax,#03H ; 3 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#084H ; 132 ;[INF] 2, 1
|
||
call !_iic_mcu_read_a_byte ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
mov a,c ;[INF] 1, 1
|
||
and a,#01H ; 1 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0051 ;[INF] 2, 4
|
||
; line 330 : {
|
||
??bb01_chk_emergencyExit:
|
||
; line 331 : // PMIC<49><43><EFBFBD>ُ<EFBFBD><D98F>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>f<EFBFBD><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 332 : system_status.pwr_state = OFF_TRIG;
|
||
$DGL 0,10
|
||
clrb !_system_status ;[INF] 3, 1
|
||
; line 333 : renge_task_interval_run_force = 1;
|
||
$DGL 0,11
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
??eb01_chk_emergencyExit:
|
||
; line 334 : }
|
||
$DGL 0,12
|
||
ret ;[INF] 1, 6
|
||
?L0051:
|
||
; line 335 : else
|
||
; line 336 : {
|
||
??bb02_chk_emergencyExit:
|
||
; line 337 : if( state == 0 )
|
||
$DGL 0,15
|
||
clrw ax ;[INF] 1, 1
|
||
cmpw ax,!?L0048 ; state ;[INF] 3, 1
|
||
bnz $?L0050 ;[INF] 2, 4
|
||
; line 338 : {
|
||
??bb03_chk_emergencyExit:
|
||
; line 339 : state = 1;
|
||
$DGL 0,17
|
||
onew ax ;[INF] 1, 1
|
||
movw !?L0048,ax ; state ;[INF] 3, 1
|
||
; line 340 : // <20>f<EFBFBD>o<EFBFBD>b<EFBFBD>K<EFBFBD>Ȃ肪<C882><E882AA><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 341 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL,
|
||
; 0 );
|
||
$DGL 0,19
|
||
clrw ax ;[INF] 1, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#04H ; 4 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,#084H ; 132 ;[INF] 2, 1
|
||
call !_iic_mcu_write_a_byte ;[INF] 3, 3
|
||
addw sp,#04H ; 4 ;[INF] 2, 1
|
||
; line 342 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS]
|
||
; & 0b10011111 );
|
||
$DGL 0,20
|
||
mov a,!_vreg_ctr+15 ;[INF] 3, 1
|
||
and a,#09FH ; 159 ;[INF] 2, 1
|
||
mov !_vreg_ctr+15,a ;[INF] 3, 1
|
||
; line 343 : vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ;
|
||
$DGL 0,21
|
||
set1 !_vreg_ctr+32.1 ;[INF] 4, 2
|
||
; line 344 : renge_task_immed_add( do_command0 );
|
||
$DGL 0,22
|
||
movw ax,#loww (_do_command0) ;[INF] 3, 1
|
||
call !_renge_task_immed_add ;[INF] 3, 3
|
||
??eb03_chk_emergencyExit:
|
||
; line 345 : }
|
||
; line 346 : }
|
||
??eb02_chk_emergencyExit:
|
||
; line 347 : }
|
||
$DGL 0,25
|
||
??eb00_chk_emergencyExit:
|
||
ret ;[INF] 1, 6
|
||
?L0049:
|
||
; line 348 : else
|
||
; line 349 : {
|
||
??bb04_chk_emergencyExit:
|
||
; line 350 : state = 0;
|
||
$DGL 0,28
|
||
clrw ax ;[INF] 1, 1
|
||
movw !?L0048,ax ; state ;[INF] 3, 1
|
||
??eb04_chk_emergencyExit:
|
||
; line 351 : }
|
||
?L0050:
|
||
; line 352 : #endif
|
||
; line 353 : }
|
||
$DGL 0,31
|
||
??ef_chk_emergencyExit:
|
||
ret ;[INF] 1, 6
|
||
??ee_chk_emergencyExit:
|
||
; line 354 :
|
||
; line 355 :
|
||
; line 356 :
|
||
; line 357 :
|
||
; line 358 :
|
||
; line 359 : /* ========================================================
|
||
; line 360 : CPU<50><55><EFBFBD><EFBFBD><EFBFBD>̃X<CC83><58><EFBFBD>[<5B>v<EFBFBD>v<EFBFBD><76>
|
||
; line 361 : <20>@<40>|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD>ɂ<EFBFBD><C982>܂<EFBFBD><DC82><EFBFBD><EFBFBD>B
|
||
; line 362 : ======================================================== */
|
||
; line 363 : /*
|
||
; line 364 : __interrupt void intp0_slp( )
|
||
; line 365 : { // SLP
|
||
; line 366 : if( SLP_REQ ){
|
||
; line 367 : system_status.pwr_state = SLEEP_TRIG;
|
||
; line 368 : }else{
|
||
; line 369 : system_status.pwr_state = ON_TRIG;
|
||
; line 370 : if( PM_BL_set() != ERR_SUCCESS ){
|
||
; line 371 : renge_task_interval_run_force = 1;
|
||
; line 372 : iic_mcu_stop();
|
||
; line 373 : system_status.pwr_state = OFF_TRIG;
|
||
; line 374 : }
|
||
; line 375 : }
|
||
; line 376 : renge_task_interval_run_force = 1;
|
||
; line 377 : }
|
||
; line 378 : */
|
||
; line 379 :
|
||
; line 380 :
|
||
; line 381 :
|
||
; line 382 : /*******************************************************//**
|
||
; line 383 : <20>S<EFBFBD><53><EFBFBD>Ӗ<EFBFBD><D396>Ȃ<EFBFBD><C882>ł<EFBFBD><C582><EFBFBD><EFBFBD>A<EFBFBD>C<EFBFBD><43><EFBFBD>I<EFBFBD>ȕ<EFBFBD><C895><EFBFBD>...
|
||
; line 384 : **********************************************************/
|
||
; line 385 : task_status_immed tski_firm_update(){
|
||
_tski_firm_update:
|
||
$DGL 1,193
|
||
??bf_tski_firm_update:
|
||
; line 386 : firm_update();
|
||
$DGL 0,2
|
||
call !_firm_update ;[INF] 3, 3
|
||
; line 387 : return( ERR_SUCCESS );
|
||
$DGL 0,3
|
||
clrw bc ;[INF] 1, 1
|
||
; line 388 : }
|
||
$DGL 0,4
|
||
??ef_tski_firm_update:
|
||
ret ;[INF] 1, 6
|
||
??ee_tski_firm_update:
|
||
|
||
@@CODEL CSEG
|
||
|
||
@@BASE CSEG BASE
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c
|
||
;
|
||
; $FUNC tsk_sys(35)
|
||
; void=(void)
|
||
; CODE SIZE= 433 bytes, CLOCK_SIZE= 384 clocks, STACK_SIZE= 12 bytes
|
||
;
|
||
; $CALL iic_mcu_start(80)
|
||
; void=(void)
|
||
;
|
||
; $CALL PM_init(83)
|
||
; void=(void)
|
||
;
|
||
; $CALL PM_sys_pow_on(85)
|
||
; bc=(void)
|
||
;
|
||
; $CALL iic_mcu_stop(88)
|
||
; void=(void)
|
||
;
|
||
; $CALL PM_LCD_vcom_set(100)
|
||
; bc=(void)
|
||
;
|
||
; $CALL LED_init(122)
|
||
; void=(void)
|
||
;
|
||
; $CALL IIC_ctr_Init(126)
|
||
; void=(void)
|
||
;
|
||
; $CALL set_irq(136)
|
||
; void=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL IIC_twl_Init(138)
|
||
; void=(void)
|
||
;
|
||
; $CALL chk_emergencyExit(163)
|
||
; void=(void)
|
||
;
|
||
; $CALL iic_mcu_write_a_byte(173)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
;
|
||
; $CALL chk_emergencyExit(178)
|
||
; void=(void)
|
||
;
|
||
; $CALL iic_mcu_write_a_byte(181)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
;
|
||
; $CALL wait_ms(182)
|
||
; void=(int:ax)
|
||
;
|
||
; $CALL LED_stop(208)
|
||
; void=(void)
|
||
;
|
||
; $CALL IIC_ctr_Stop(209)
|
||
; void=(void)
|
||
;
|
||
; $CALL IIC_twl_Stop(210)
|
||
; void=(void)
|
||
;
|
||
; $CALL PM_sys_pow_off(235)
|
||
; bc=(void)
|
||
;
|
||
; $CALL iic_mcu_stop(278)
|
||
; void=(void)
|
||
;
|
||
; $FUNC chk_emergencyExit(323)
|
||
; void=(void)
|
||
; CODE SIZE= 73 bytes, CLOCK_SIZE= 68 clocks, STACK_SIZE= 8 bytes
|
||
;
|
||
; $CALL iic_mcu_read_a_byte(329)
|
||
; bc=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL iic_mcu_write_a_byte(341)
|
||
; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
;
|
||
; $CALL renge_task_immed_add(344)
|
||
; bc=(pointer:ax)
|
||
;
|
||
; $FUNC tski_firm_update(385)
|
||
; bc=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes
|
||
;
|
||
; $CALL firm_update(386)
|
||
; bc=(void)
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|