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ctr_mcu/branches/0.10(X3)/inter_asm/sw.asm
N2232 dc469bd4c6 0.10のX3対応版を登録 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
2010-06-23 07:16:15 +00:00

860 lines
27 KiB
NASM
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; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no sw.c
; In-file : sw.c
; Asm-file : inter_asm\sw.asm
; Para-file :
$PROCESSOR(9F0104)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
$DGS FIL_NAM, .file, 0CDH, 0FFFEH, 03FH, 067H, 01H, 00H
$DGS AUX_FIL, sw.c
$DGS MOD_NAM, sw, 00H, 0FFFEH, 00H, 077H, 00H, 00H
$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
$DGS AUX_TAG, 01H, 01EH
$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
$DGS AUX_EOS, 013H, 01H
$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
$DGS AUX_TAG, 01H, 025H
$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
$DGS AUX_EOS, 01EH, 01H
$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
$DGS AUX_TAG, 01H, 02FH
$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
$DGS AUX_EOS, 025H, 01H
$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
$DGS AUX_TAG, 04H, 041H
$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
$DGS AUX_BIT, 00H, 01H
$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
$DGS AUX_BIT, 00H, 01H
$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
$DGS AUX_BIT, 00H, 01H
$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
$DGS AUX_BIT, 00H, 01H
$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
$DGS AUX_EOS, 02FH, 04H
$DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H
$DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H
$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
$DGS GLV_SYM, _tsk_sw, U, U, 01H, 026H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 0CDH, 00H, 00H
$DGS BEG_FUN, ??bf_tsk_sw, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 038H, 02H, 04BH
$DGS STA_SYM, _cnt_force_off, ?L0003, U, 0CH, 03H, 00H, 00H
$DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H
$DGS BEG_BLK, ??bb00_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 06H, 00H, 04FH
$DGS END_BLK, ??eb00_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 014H
$DGS BEG_BLK, ??bb01_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 017H, 00H, 053H
$DGS END_BLK, ??eb01_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 019H
$DGS BEG_BLK, ??bb02_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 01BH, 00H, 057H
$DGS END_BLK, ??eb02_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 01DH
$DGS BEG_BLK, ??bb03_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 021H, 00H, 059H
$DGS BEG_BLK, ??bb04_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 028H, 00H, 05BH
$DGS BEG_BLK, ??bb05_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 02AH, 00H, 061H
$DGS END_BLK, ??eb05_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 030H
$DGS END_BLK, ??eb04_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 031H
$DGS BEG_BLK, ??bb06_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 033H, 00H, 065H
$DGS END_BLK, ??eb06_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 039H
$DGS BEG_BLK, ??bb07_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 03BH, 00H, 069H
$DGS END_BLK, ??eb07_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 03FH
$DGS BEG_BLK, ??bb08_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 043H, 00H, 06BH
$DGS BEG_BLK, ??bb09_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 046H, 00H, 071H
$DGS END_BLK, ??eb09_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04AH
$DGS END_BLK, ??eb08_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04BH
$DGS BEG_BLK, ??bb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 04DH, 00H, 075H
$DGS END_BLK, ??eb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 04FH
$DGS BEG_BLK, ??bb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 053H, 00H, 079H
$DGS END_BLK, ??eb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 05FH
$DGS BEG_BLK, ??bb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 062H, 00H, 07BH
$DGS BEG_BLK, ??bb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 064H, 00H, 081H
$DGS END_BLK, ??eb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 066H
$DGS END_BLK, ??eb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 067H
$DGS BEG_BLK, ??bb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 069H, 00H, 085H
$DGS END_BLK, ??eb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 06BH
$DGS BEG_BLK, ??bb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 06FH, 00H, 08BH
$DGS END_BLK, ??eb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 071H
$DGS END_BLK, ??eb03_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 074H
$DGS BEG_BLK, ??bb10_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07DH, 00H, 08DH
$DGS BEG_BLK, ??bb11_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07EH, 00H, 08FH
$DGS BEG_BLK, ??bb12_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07EH, 00H, 093H
$DGS END_BLK, ??eb12_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 07EH
$DGS BEG_BLK, ??bb13_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07EH, 00H, 095H
$DGS BEG_BLK, ??bb14_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07EH, 00H, 099H
$DGS END_BLK, ??eb14_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 07EH
$DGS BEG_BLK, ??bb15_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 07EH, 00H, 0A1H
$DGS END_BLK, ??eb15_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 07EH
$DGS END_BLK, ??eb13_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 07EH
$DGS END_BLK, ??eb11_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 07EH
$DGS BEG_BLK, ??bb16_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 080H, 00H, 0A3H
$DGS BEG_BLK, ??bb17_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 080H, 00H, 0A7H
$DGS END_BLK, ??eb17_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 080H
$DGS BEG_BLK, ??bb18_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 080H, 00H, 0A9H
$DGS BEG_BLK, ??bb19_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 080H, 00H, 0ADH
$DGS END_BLK, ??eb19_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 080H
$DGS BEG_BLK, ??bb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 080H, 00H, 0B5H
$DGS END_BLK, ??eb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 080H
$DGS END_BLK, ??eb18_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 080H
$DGS END_BLK, ??eb16_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 080H
$DGS BEG_BLK, ??bb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 082H, 00H, 0B7H
$DGS BEG_BLK, ??bb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 082H, 00H, 0BBH
$DGS END_BLK, ??eb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 082H
$DGS BEG_BLK, ??bb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 082H, 00H, 0BDH
$DGS BEG_BLK, ??bb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 082H, 00H, 0C1H
$DGS END_BLK, ??eb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 082H
$DGS BEG_BLK, ??bb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 082H, 00H, 00H
$DGS END_BLK, ??eb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 082H
$DGS END_BLK, ??eb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 082H
$DGS END_BLK, ??eb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 082H
$DGS END_BLK, ??eb10_tsk_sw, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 083H
$DGS END_FUN, ??ef_tsk_sw, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 086H
$DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 026H, 00H, 00H
$DGS GLV_SYM, _SW_home_count, U, U, 0CH, 026H, 00H, 00H
$DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 026H, 00H, 00H
$DGS GLV_SYM, _SW_pow_mask, U, U, 034CH, 027H, 00H, 00H
$DGS GLV_SYM, _SW_home_mask, U, U, 034CH, 027H, 00H, 00H
$DGS GLV_SYM, _SW_wifi_mask, U, U, 034CH, 027H, 00H, 00H
$DGS GLV_SYM, _SW_HOME_n, U, U, 034CH, 027H, 00H, 00H
$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H
EXTRN _set_irq
EXTRN _system_status
EXTRN _vreg_ctr
EXTBIT _renge_task_interval_run_force
PUBLIC _SW_pow_count
PUBLIC _SW_home_count
PUBLIC _SW_wifi_count
PUBLIC _SW_pow_mask
PUBLIC _SW_home_mask
PUBLIC _SW_wifi_mask
PUBLIC _SW_HOME_n
PUBLIC _tsk_sw
@@BITS BSEG
_SW_pow_mask DBIT
_SW_home_mask DBIT
_SW_wifi_mask DBIT
_SW_HOME_n DBIT
@@CNST CSEG MIRRORP
_lpf_coeff: DB 01H ; 1
DB 02H ; 2
DB 02H ; 2
DB 03H ; 3
DB 03H ; 3
DB 02H ; 2
DB 00H ; 0
DB 0FEH ; 254
DB 0FBH ; 251
DB 0F7H ; 247
DB 0F3H ; 243
DB 0F0H ; 240
DB 0F0H ; 240
DB 0F3H ; 243
DB 0FAH ; 250
DB 04H ; 4
DB 012H ; 18
DB 025H ; 37
DB 038H ; 56
DB 04DH ; 77
DB 05FH ; 95
DB 06EH ; 110
DB 077H ; 119
DB 07AH ; 122
DB 077H ; 119
DB 06EH ; 110
DB 05FH ; 95
DB 04DH ; 77
DB 038H ; 56
DB 025H ; 37
DB 012H ; 18
DB 04H ; 4
DB 0FAH ; 250
DB 0F3H ; 243
DB 0F0H ; 240
DB 0F0H ; 240
DB 0F3H ; 243
DB 0F7H ; 247
DB 0FBH ; 251
DB 0FEH ; 254
DB 00H ; 0
DB 02H ; 2
DB 03H ; 3
DB 03H ; 3
DB 02H ; 2
DB 02H ; 2
DB 01H ; 1
DB (1)
@@R_INIT CSEG UNIT64KP
DB 00H ; 0
DB 00H ; 0
@@INIT DSEG BASEP
?L0003: DS (1)
?L0004: DS (1)
@@DATA DSEG BASEP
_SW_pow_count: DS (1)
_SW_home_count: DS (1)
_SW_wifi_count: DS (1)
DS (1)
@@R_INIS CSEG UNIT64KP
@@INIS DSEG SADDRP
@@DATS DSEG SADDRP
@@CNSTL CSEG PAGE64KP
@@RLINIT CSEG UNIT64KP
@@INITL DSEG UNIT64KP
@@DATAL DSEG UNIT64KP
@@CALT CSEG CALLT0
; Sub-Routines created by CC78K0R
ROM_CODE CSEG BASE
bs_F0060:
push ax ;[INF] 1, 1
mov x,#010H ; 16 ;[INF] 2, 1
call !_set_irq ;[INF] 3, 3
pop ax ;[INF] 1, 1
ret ;[INF] 1, 6
es_F0060:
; *** Sub-Routine Information ***
;
; $SUB bs_F0060
; CODE SIZE= 8 bytes
; End of Sub-Routines
; line 1 : #pragma SFR
; line 2 : #pragma NOP
; line 3 : #pragma HALT
; line 4 : #pragma STOP
; line 5 :
; line 6 : #include "incs.h"
; line 7 :
; line 8 : #include "i2c_twl.h"
; line 9 : #include "i2c_ctr.h"
; line 10 : #include "led.h"
; line 11 : #include "accero.h"
; line 12 : #include "pm.h"
; line 13 : #include "rtc.h"
; line 14 :
; line 15 :
; line 16 :
; line 17 : //=========================================================
; line 18 : #define INTERVAL_TSK_SW 16
; line 19 : #define CLICK_THRESHOLD 1
; line 20 : #define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW )
; line 21 :
; line 22 :
; line 23 :
; line 24 : //=========================================================
; line 25 : u8 SW_pow_count, SW_home_count, SW_wifi_count;
; line 26 : bit SW_pow_mask, SW_home_mask, SW_wifi_mask;
; line 27 :
; line 28 : bit SW_HOME_n;
; line 29 :
; line 30 :
; line 31 : //=========================================================
; line 32 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԃ𐔂<D482><F0909482><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ςȂ<CF82><C882>ł<EFBFBD>0<EFBFBD>ɖ߂<C996><DF82>Ȃ<EFBFBD>
; line 33 : // mask<73><6B><EFBFBD><EFBFBD>0<EFBFBD>̎<EFBFBD><CC8E>́A<CD81><41><EFBFBD>x<EFBFBD><78><EFBFBD><EFBFBD><EFBFBD>܂Ŗ<DC82><C596><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 34 : #define count_sw_n( sw, counter, mask ) \
; line 35 : { \
; line 36 : if( sw ){ \
; line 37 : mask = 0; \
; line 38 : counter = 0; \
; line 39 : }else{ \
; line 40 : if( mask != 0 ){ \
; line 41 : counter = 0; \
; line 42 : }else{ \
; line 43 : counter += 1; \
; line 44 : if( counter == 0 ) counter = 255; \
; line 45 : } \
; line 46 : } \
; line 47 : }
; line 48 :
; line 49 :
; line 50 :
; line 51 : /* ========================================================
; line 52 : <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>̊Ď<CC8A>
; line 53 : <20>@<40>`<60><><EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><4F><EFBFBD>͂˂<CD82><CB82><EFBFBD><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>g<EFBFBD><67><EFBFBD>K<EFBFBD>Ȃǂ̌<C782><CC8C>o<EFBFBD>Ȃ<EFBFBD>
; line 54 : ======================================================== */
; line 55 : void tsk_sw( )
; line 56 : {
ROM_CODE CSEG BASE
_tsk_sw:
$DGL 1,69
push hl ;[INF] 1, 1
??bf_tsk_sw:
; line 57 : static u8 cnt_force_off = 0;
; line 58 : static u8 task_interval = 0;
; line 59 :
; line 60 : switch ( system_status.pwr_state )
$DGL 0,5
mov a,!_system_status ;[INF] 3, 1
sarw ax,8 ;[INF] 2, 1
clrw bc ;[INF] 1, 1
subw ax,bc ;[INF] 1, 1
bz $?L0006 ;[INF] 2, 4
subw ax,#02H ; 2 ;[INF] 3, 1
bz $?L0007 ;[INF] 2, 4
br $?L0005 ;[INF] 2, 3
; line 61 : {
??bb00_tsk_sw:
; line 62 : case ( OFF_TRIG ):
?L0006:
; line 63 : SW_pow_count = 0;
$DGL 0,8
clrb !_SW_pow_count ;[INF] 3, 1
; line 64 : SW_wifi_count = 0;
$DGL 0,9
clrb !_SW_wifi_count ;[INF] 3, 1
; line 65 : SW_home_count = 0;
$DGL 0,10
clrb !_SW_home_count ;[INF] 3, 1
; line 66 : cnt_force_off = 0;
$DGL 0,11
clrb !?L0003 ; cnt_force_off ;[INF] 3, 1
; line 67 : break;
$DGL 0,12
br $?L0005 ;[INF] 2, 3
; line 68 :
; line 69 : case ( ON_TRIG ):
?L0007:
; line 70 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; line 71 : SW_pow_mask = 1;
$DGL 0,16
set1 _SW_pow_mask ;[INF] 3, 2
; line 72 : SW_home_mask = 1;
$DGL 0,17
set1 _SW_home_mask ;[INF] 3, 2
; line 73 : SW_wifi_mask = 1;
$DGL 0,18
set1 _SW_wifi_mask ;[INF] 3, 2
; line 74 : break;
??eb00_tsk_sw:
; line 75 : }
?L0005:
; line 76 :
; line 77 : if( task_interval-- != 0 )
$DGL 0,22
mov a,!?L0004 ; task_interval ;[INF] 3, 1
dec !?L0004 ; task_interval ;[INF] 3, 2
cmp0 a ;[INF] 1, 1
skz ;[INF] 2, 1
br !?L0058 ;[INF] 3, 3
; line 78 : {
??bb01_tsk_sw:
; line 79 : return;
??eb01_tsk_sw:
; line 80 : }
; line 81 : else
; line 82 : {
??bb02_tsk_sw:
; line 83 : task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TIC
; K );
$DGL 0,28
mov !?L0004,#08H ; task_interval,8 ;[INF] 4, 1
??eb02_tsk_sw:
; line 84 : }
; line 85 :
; line 86 :
; line 87 : switch ( system_status.pwr_state )
$DGL 0,32
mov a,!_system_status ;[INF] 3, 1
sarw ax,8 ;[INF] 2, 1
onew bc ;[INF] 1, 1
movw de,#02H ; 2 ;[INF] 3, 1
subw ax,bc ;[INF] 1, 1
bz $?L0013 ;[INF] 2, 4
subw ax,de ;[INF] 1, 1
bz $?L0013 ;[INF] 2, 4
subw ax,de ;[INF] 1, 1
subw ax,bc ;[INF] 1, 1
sknh ;[INF] 2, 1
br !?L0012 ;[INF] 3, 3
; line 88 : {
??bb03_tsk_sw:
; line 89 : case ( ON ):
?L0013:
; line 90 : case ( SLEEP ):
; line 91 : case ( BT_CHARGE ):
; line 92 : case ( OFF ):
; line 93 : // <20>d<EFBFBD><64><EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>̊Ď<CC8A> //
; line 94 : if( SW_POW_n )
$DGL 0,39
bf P7.3,$?L0016 ;[INF] 4, 5
; line 95 : {
??bb04_tsk_sw:
; line 96 : if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_c
; ount <= HOLD_THREASHOLD ) )
$DGL 0,41
cmp !_SW_pow_count,#02H ; 2 ;[INF] 4, 1
bc $?L0022 ;[INF] 2, 4
cmp !_SW_pow_count,#026H ; 38 ;[INF] 4, 1
bnc $?L0022 ;[INF] 2, 4
; line 97 : {
??bb05_tsk_sw:
; line 98 : #ifdef _SW_HOME_ENABLE_
; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK );
$DGL 0,44
onew ax ;[INF] 1, 1
call !bs_F0060 ;[INF] 3, 3
??eb05_tsk_sw:
; line 100 : #else
; line 101 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK );
; line 102 : #endif
; line 103 : }
; line 104 : }
$DGL 0,49
??eb04_tsk_sw:
br $?L0022 ;[INF] 2, 3
?L0016:
; line 105 : else if( SW_pow_count == HOLD_THREASHOLD )
$DGL 0,50
cmp !_SW_pow_count,#025H ; 37 ;[INF] 4, 1
bnz $?L0020 ;[INF] 2, 4
; line 106 : {
??bb06_tsk_sw:
; line 107 : #ifdef _SW_HOME_ENABLE_
; line 108 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD );
$DGL 0,53
onew ax ;[INF] 1, 1
incw ax ;[INF] 1, 1
call !bs_F0060 ;[INF] 3, 3
??eb06_tsk_sw:
; line 109 : #else
; line 110 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD );
; line 111 : #endif
; line 112 : }
$DGL 0,57
br $?L0022 ;[INF] 2, 3
?L0020:
; line 113 : else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) )
$DGL 0,58
cmp !_SW_pow_count,#094H ; 148 ;[INF] 4, 1
bnz $?L0022 ;[INF] 2, 4
; line 114 : { // todo
??bb07_tsk_sw:
; line 115 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED;
$DGL 0,60
mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1
; line 116 : system_status.pwr_state = OFF_TRIG;
$DGL 0,61
clrb !_system_status ;[INF] 3, 1
; line 117 : renge_task_interval_run_force = 1;
$DGL 0,62
set1 _renge_task_interval_run_force ;[INF] 3, 2
??eb07_tsk_sw:
; line 118 : }
?L0022:
; line 119 :
; line 120 : // <20>d<EFBFBD><64>OFF<46><46><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD>ꂽ<EFBFBD><EA82BD><EFBFBD>c
; line 121 : if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0
; )
$DGL 0,66
mov a,!_vreg_ctr+16 ;[INF] 3, 1
and a,#02H ; 2 ;[INF] 2, 1
cmp0 a ;[INF] 1, 1
bz $?L0024 ;[INF] 2, 4
; line 122 : {
??bb08_tsk_sw:
; line 123 : cnt_force_off += 1;
$DGL 0,68
inc !?L0003 ; cnt_force_off ;[INF] 3, 2
; line 124 : if( cnt_force_off >= 13 )
$DGL 0,69
cmp !?L0003,#0DH ; cnt_force_off,13 ;[INF] 4, 1
bc $?L0025 ;[INF] 2, 4
; line 125 : { // <20>c<EFBFBD>Ԏ<EFBFBD><D48E><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>I<EFBFBD>ɐ؂<C990><D882>B
??bb09_tsk_sw:
; line 126 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RE
; D;
$DGL 0,71
mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1
; line 127 : system_status.pwr_state = OFF_TRIG;
$DGL 0,72
clrb !_system_status ;[INF] 3, 1
; line 128 : renge_task_interval_run_force = 1;
$DGL 0,73
set1 _renge_task_interval_run_force ;[INF] 3, 2
??eb09_tsk_sw:
; line 129 : }
; line 130 : }
$DGL 0,75
??eb08_tsk_sw:
br $?L0025 ;[INF] 2, 3
?L0024:
; line 131 : else
; line 132 : {
??bb0A_tsk_sw:
; line 133 : cnt_force_off = 0;
$DGL 0,78
clrb !?L0003 ; cnt_force_off ;[INF] 3, 1
??eb0A_tsk_sw:
; line 134 : }
?L0025:
; line 135 :
; line 136 : // HOME <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>` //
; line 137 : switch( system_status.model )
$DGL 0,82
mov a,!_system_status+3 ;[INF] 3, 1
sarw ax,8 ;[INF] 2, 1
onew bc ;[INF] 1, 1
subw ax,#00H ; 0 ;[INF] 3, 1
bz $?L0029 ;[INF] 2, 4
decw ax ;[INF] 1, 1
subw ax,bc ;[INF] 1, 1
bnh $?L0030 ;[INF] 3, 4
br $?L0031 ;[INF] 2, 3
; line 138 : {
??bb0B_tsk_sw:
; line 139 : #ifdef _MODEL_CTR_
; line 140 : case( MODEL_JIKKI ):
?L0029:
; line 141 : SW_HOME_n = SW_HOME_n_JIKKI;
$DGL 0,86
movw hl,#0510H ; 1296 ;[INF] 3, 1
mov1 CY,[hl].4 ;[INF] 2, 1
mov1 _SW_HOME_n,CY ;[INF] 3, 2
; line 142 : break;
$DGL 0,87
br $?L0028 ;[INF] 2, 3
; line 143 : #endif
; line 144 : case( MODEL_TS_BOARD ):
?L0030:
; line 145 : case( MODEL_SHIROBAKO ):
; line 146 : SW_HOME_n = SW_HOME_n_TSBOARD;
$DGL 0,91
mov1 CY,P2.0 ;[INF] 3, 1
mov1 _SW_HOME_n,CY ;[INF] 3, 2
; line 147 : break;
$DGL 0,92
br $?L0028 ;[INF] 2, 3
; line 148 : default:
?L0031:
; line 149 : SW_HOME_n = 1;
$DGL 0,94
set1 _SW_HOME_n ;[INF] 3, 2
??eb0B_tsk_sw:
; line 150 : }
?L0028:
; line 151 :
; line 152 : if( SW_HOME_n )
$DGL 0,97
bf _SW_HOME_n,$?L0034 ;[INF] 4, 5
; line 153 : {
??bb0C_tsk_sw:
; line 154 : if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home
; _count <= HOLD_THREASHOLD ) )
$DGL 0,99
cmp !_SW_home_count,#02H ; 2 ;[INF] 4, 1
bc $?L0038 ;[INF] 2, 4
cmp !_SW_home_count,#026H ; 38 ;[INF] 4, 1
bnc $?L0038 ;[INF] 2, 4
; line 155 : {
??bb0D_tsk_sw:
; line 156 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK );
$DGL 0,101
movw ax,#04H ; 4 ;[INF] 3, 1
call !bs_F0060 ;[INF] 3, 3
??eb0D_tsk_sw:
; line 157 : }
; line 158 : }
$DGL 0,103
??eb0C_tsk_sw:
br $?L0038 ;[INF] 2, 3
?L0034:
; line 159 : else if( SW_home_count == HOLD_THREASHOLD )
$DGL 0,104
cmp !_SW_home_count,#025H ; 37 ;[INF] 4, 1
bnz $?L0038 ;[INF] 2, 4
; line 160 : {
??bb0E_tsk_sw:
; line 161 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD );
$DGL 0,106
movw ax,#08H ; 8 ;[INF] 3, 1
call !bs_F0060 ;[INF] 3, 3
??eb0E_tsk_sw:
; line 162 : }
?L0038:
; line 163 :
; line 164 : // wifi sw //
; line 165 : if( SW_wifi_count == CLICK_THRESHOLD )
$DGL 0,110
cmp !_SW_wifi_count,#01H ; 1 ;[INF] 4, 1
bnz $?L0012 ;[INF] 2, 4
; line 166 : {
??bb0F_tsk_sw:
; line 167 : set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK );
$DGL 0,112
movw ax,#010H ; 16 ;[INF] 3, 1
push ax ;[INF] 1, 1
call !_set_irq ;[INF] 3, 3
pop ax ;[INF] 1, 1
??eb0F_tsk_sw:
; line 168 : }
; line 169 :
; line 170 : break;
??eb03_tsk_sw:
; line 171 : }
?L0012:
; line 172 :
; line 173 : // <20>{<7B>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԃ̃J<CC83>E<EFBFBD><45><EFBFBD>g
; line 174 : /*
; line 175 : if( ( system_status.pwr_state == ON )
; line 176 : || ( system_status.pwr_state == OFF )
; line 177 : || ( system_status.pwr_state == BT_CHARGE ) )
; line 178 : */
; line 179 :
; line 180 : {
??bb10_tsk_sw:
; line 181 : count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask );
$DGL 0,126
??bb11_tsk_sw:
bf P7.3,$?L0042 ;[INF] 4, 5
??bb12_tsk_sw:
clr1 _SW_pow_mask ;[INF] 3, 2
clrb !_SW_pow_count ;[INF] 3, 1
??eb12_tsk_sw:
br $?L0046 ;[INF] 2, 3
?L0042:
??bb13_tsk_sw:
bf _SW_pow_mask,$?L0044 ;[INF] 4, 5
??bb14_tsk_sw:
clrb !_SW_pow_count ;[INF] 3, 1
??eb14_tsk_sw:
br $?L0046 ;[INF] 2, 3
?L0044:
??bb15_tsk_sw:
inc !_SW_pow_count ;[INF] 3, 2
cmp0 !_SW_pow_count ;[INF] 3, 1
sknz ;[INF] 2, 1
mov !_SW_pow_count,#0FFH ; 255 ;[INF] 4, 1
?L0046:
??eb15_tsk_sw:
??eb13_tsk_sw:
??eb11_tsk_sw:
; line 182 : #ifdef _SW_HOME_ENABLE_
; line 183 : count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask );
$DGL 0,128
??bb16_tsk_sw:
bf _SW_HOME_n,$?L0048 ;[INF] 4, 5
??bb17_tsk_sw:
clr1 _SW_home_mask ;[INF] 3, 2
clrb !_SW_home_count ;[INF] 3, 1
??eb17_tsk_sw:
br $?L0052 ;[INF] 2, 3
?L0048:
??bb18_tsk_sw:
bf _SW_home_mask,$?L0050 ;[INF] 4, 5
??bb19_tsk_sw:
clrb !_SW_home_count ;[INF] 3, 1
??eb19_tsk_sw:
br $?L0052 ;[INF] 2, 3
?L0050:
??bb1A_tsk_sw:
inc !_SW_home_count ;[INF] 3, 2
cmp0 !_SW_home_count ;[INF] 3, 1
sknz ;[INF] 2, 1
mov !_SW_home_count,#0FFH ; 255 ;[INF] 4, 1
?L0052:
??eb1A_tsk_sw:
??eb18_tsk_sw:
??eb16_tsk_sw:
; line 184 : #endif
; line 185 : count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask );
$DGL 0,130
??bb1B_tsk_sw:
bf P7.4,$?L0054 ;[INF] 4, 5
??bb1C_tsk_sw:
clr1 _SW_wifi_mask ;[INF] 3, 2
clrb !_SW_wifi_count ;[INF] 3, 1
??eb1C_tsk_sw:
br $?L0058 ;[INF] 2, 3
?L0054:
??bb1D_tsk_sw:
bf _SW_wifi_mask,$?L0056 ;[INF] 4, 5
??bb1E_tsk_sw:
clrb !_SW_wifi_count ;[INF] 3, 1
??eb1E_tsk_sw:
br $?L0058 ;[INF] 2, 3
?L0056:
??bb1F_tsk_sw:
inc !_SW_wifi_count ;[INF] 3, 2
cmp0 !_SW_wifi_count ;[INF] 3, 1
sknz ;[INF] 2, 1
mov !_SW_wifi_count,#0FFH ; 255 ;[INF] 4, 1
?L0058:
??eb1F_tsk_sw:
??eb1D_tsk_sw:
??eb1B_tsk_sw:
??eb10_tsk_sw:
; line 186 : }
; line 187 :
; line 188 : return;
; line 189 : }
$DGL 0,134
??ef_tsk_sw:
pop hl ;[INF] 1, 1
ret ;[INF] 1, 6
??ee_tsk_sw:
@@CODEL CSEG
@@BASE CSEG BASE
END
; *** Code Information ***
;
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c
;
; $FUNC tsk_sw(56)
; void=(void)
; CODE SIZE= 351 bytes, CLOCK_SIZE= 329 clocks, STACK_SIZE= 12 bytes
;
; $CALL set_irq(99)
; void=(int:ax, int:[sp+4])
;
; $CALL set_irq(108)
; void=(int:ax, int:[sp+4])
;
; $CALL set_irq(156)
; void=(int:ax, int:[sp+4])
;
; $CALL set_irq(161)
; void=(int:ax, int:[sp+4])
;
; $CALL set_irq(167)
; void=(int:ax, int:[sp+4])
; Target chip : uPD79F0104
; Device file : E1.00b
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