mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
921 lines
28 KiB
NASM
921 lines
28 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c
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; In-file : i2c_ctr.c
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; Asm-file : inter_asm\i2c_ctr.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 07CH, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, i2c_ctr.c
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$DGS MOD_NAM, i2c_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _int_iic_ctr, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 070H, 00H, 00H
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$DGS BEG_FUN, ??bf_int_iic_ctr, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 041H, 016H, 01EH
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$DGS STA_SYM, _state, ?L0003, U, 0CH, 03H, 00H, 00H
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$DGS STA_SYM, _reg_adrs, ?L0004, U, 0CH, 03H, 00H, 00H
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$DGS STA_SYM, _reg_adrs_internal, ?L0005, U, 0CH, 03H, 00H, 00H
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$DGS STA_SYM, _tx_buf, ?L0006, U, 0CH, 03H, 00H, 00H
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$DGS REG_VAR, _rx_buf, 06H, 0FFFFH, 010CH, 04H, 00H, 00H
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$DGS BEG_BLK, ??bb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0CH, 00H, 020H
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$DGS BEG_BLK, ??bb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 014H, 00H, 022H
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$DGS BEG_BLK, ??bb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 015H, 00H, 026H
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$DGS END_BLK, ??eb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 015H
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$DGS BEG_BLK, ??bb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01BH, 00H, 028H
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$DGS BEG_BLK, ??bb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01CH, 00H, 02CH
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$DGS END_BLK, ??eb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01CH
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$DGS BEG_BLK, ??bb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01DH, 00H, 036H
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$DGS END_BLK, ??eb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01DH
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$DGS END_BLK, ??eb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01EH
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$DGS END_BLK, ??eb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01FH
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$DGS END_BLK, ??eb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 026H
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$DGS BEG_BLK, ??bb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02AH, 00H, 03AH
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$DGS END_BLK, ??eb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 030H
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$DGS BEG_BLK, ??bb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 033H, 00H, 03CH
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$DGS BEG_BLK, ??bb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 037H, 00H, 042H
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$DGS END_BLK, ??eb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03AH
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$DGS END_BLK, ??eb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03BH
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$DGS BEG_BLK, ??bb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03EH, 00H, 044H
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$DGS BEG_BLK, ??bb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 04CH, 00H, 048H
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$DGS END_BLK, ??eb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 04EH
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$DGS BEG_BLK, ??bb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 050H, 00H, 04CH
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$DGS END_BLK, ??eb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 052H
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$DGS BEG_BLK, ??bb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 059H, 00H, 04EH
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$DGS BEG_BLK, ??bb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 05CH, 00H, 052H
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$DGS END_BLK, ??eb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 05FH
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$DGS BEG_BLK, ??bb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 061H, 00H, 058H
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$DGS END_BLK, ??eb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 067H
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$DGS END_BLK, ??eb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 068H
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$DGS BEG_BLK, ??bb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06AH, 00H, 05CH
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$DGS END_BLK, ??eb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 06DH
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$DGS BEG_BLK, ??bb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 071H, 00H, 060H
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$DGS END_BLK, ??eb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 074H
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$DGS BEG_BLK, ??bb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 076H, 00H, 064H
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$DGS END_BLK, ??eb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 07AH
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$DGS BEG_BLK, ??bb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 07EH, 00H, 068H
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$DGS END_BLK, ??eb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 080H
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$DGS BEG_BLK, ??bb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 083H, 00H, 00H
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$DGS END_BLK, ??eb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 085H
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$DGS END_BLK, ??eb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 087H
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$DGS END_FUN, ??ef_int_iic_ctr, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 088H
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$DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 076H, 00H, 00H
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$DGS BEG_FUN, ??bf_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0CEH, 00H, 076H
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$DGS END_FUN, ??ef_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 02CH
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$DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 07CH, 00H, 00H
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$DGS BEG_FUN, ??bf_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0FFH, 00H, 07CH
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$DGS END_FUN, ??ef_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 04H
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$DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 026H, 00H, 00H
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$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _irq_readed, U, U, 034CH, 02H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _hosu_read_end, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _rtc_unlock, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
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EXTRN _@SEGAX
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EXTRN _@SEGDE
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EXTRN _@RTARG0
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EXTRN _vreg_ctr
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EXTRN _hosu_read_end
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EXTRN _rtc_unlock
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EXTRN _vreg_ctr_read
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EXTRN _vreg_ctr_after_read
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EXTRN _vreg_ctr_write
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EXTBIT _irq_readed
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PUBLIC _iic_burst_state
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PUBLIC _int_iic_ctr
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PUBLIC _IIC_ctr_Init
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PUBLIC _IIC_ctr_Stop
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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DB 025H ; 37
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DB 038H ; 56
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DB 04DH ; 77
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DB 05FH ; 95
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DB 06EH ; 110
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DB 077H ; 119
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DB 07AH ; 122
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DB 077H ; 119
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DB 06EH ; 110
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DB 05FH ; 95
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DB 04DH ; 77
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DB 038H ; 56
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DB 025H ; 37
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DB 012H ; 18
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DB 04H ; 4
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DB 0FAH ; 250
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0F7H ; 247
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DB 0FBH ; 251
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DB 0FEH ; 254
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DB 00H ; 0
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 02H ; 2
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DB 01H ; 1
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DB (1)
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@@R_INIT CSEG UNIT64KP
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DB 00H ; 0
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DB (1)
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@@INIT DSEG BASEP
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?L0003: DS (1)
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DS (1)
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@@DATA DSEG BASEP
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_iic_burst_state: DS (1)
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?L0004: DS (1)
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?L0005: DS (1)
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?L0006: DS (1)
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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@@CNSTL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : /* ========================================================
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; line 2 : <20><>SoC <20>V<EFBFBD>K<EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD>l<EFBFBD><6C> I2C<32>ʐM
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; line 3 : <20><><EFBFBD>c<EFBFBD><63><EFBFBD>J<EFBFBD>Z.nintendo
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; line 4 : '09 Apr
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; line 5 : ======================================================== */
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; line 6 : #include "incs.h"
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; line 7 : #include "accero.h"
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; line 8 :
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; line 9 : #ifdef _MCU_BSR_
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; line 10 : // #ifdef _MODEL_TS0_ || _MODEL_WM0_
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; line 11 :
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; line 12 : // <20><><EFBFBD>[<5B>L<EFBFBD><4C><EFBFBD>O<EFBFBD><4F><EFBFBD>f<EFBFBD><66><EFBFBD><EFBFBD>I2C<32><43><EFBFBD>t
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; line 13 : // TEG<45>͉<EFBFBD><CD89>H<EFBFBD>}<7D>Ńe<C583><65><EFBFBD>R
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; line 14 : #define ACKD ACKD1
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; line 15 : #define ACKE ACKE1
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; line 16 : #define COI COI1
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; line 17 : #define IICAEN IICA1EN
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; line 18 : #define IICRSV IICRSV1
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; line 19 : #define IICA IICA1
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; line 20 : #define IICAIF IICAIF1
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; line 21 : #define IICAMK IICAMK1
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; line 22 : #define IICAPR0 IICAPR11
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; line 23 : #define IICAPR1 IICAPR01
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; line 24 : #define IICCTL0 IICCTL10
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; line 25 : #define IICE IICE1
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; line 26 : #define IICF IICF1
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; line 27 : #define IICS IICS1
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; line 28 : #define IICWH IICWH1
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; line 29 : #define IICWL IICWL1
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; line 30 : #define LREL LREL1
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; line 31 : #define SPD SPD1
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; line 32 : #define SPIE SPIE1
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; line 33 : #define STCEN STCEN1
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; line 34 : #define STD STD1
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; line 35 : #define SVA SVA1
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; line 36 : #define WREL WREL1
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; line 37 : #define WTIM WTIM1
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; line 38 : #define TRC TRC1
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; line 39 : #define SMC SMC1
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; line 40 : #define DFC DFC1
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; line 41 :
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; line 42 :
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; line 43 : #endif
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; line 44 :
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; line 45 : // ==============================================
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; line 46 : extern bit irq_readed; // <20><><EFBFBD><EFBFBD><EFBFBD>ꂩ<EFBFBD><EA82A9>IRQ<52><51><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><>
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; <20>ǂ܂ꂽ
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; line 47 :
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; line 48 : u8 iic_burst_state;
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; line 49 :
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; line 50 :
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; line 51 : /* ========================================================
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; line 52 : ======================================================== */
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; line 53 : enum
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; line 54 : {
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; line 55 : IIC_IDLE = 0,
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; line 56 : IIC_RCV_REG_ADRS,
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; line 57 : IIC_TX_OR_RX,
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; line 58 : IIC_TX,
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; line 59 : IIC_RX
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; line 60 : };
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; line 61 :
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; line 62 :
|
||
; line 63 : // 1<>o<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>̓x<CC93>Ɋ<EFBFBD><C98A>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD>
|
||
; line 64 : __interrupt void int_iic_ctr( )
|
||
; line 65 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_int_iic_ctr:
|
||
$DGL 1,21
|
||
push ax ;[INF] 1, 1
|
||
push bc ;[INF] 1, 1
|
||
push de ;[INF] 1, 1
|
||
push hl ;[INF] 1, 1
|
||
mov c,#0CH ;[INF] 2, 1
|
||
dec c ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
movw ax,_@SEGAX[c] ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
bnz $$-6 ;[INF] 2, 4
|
||
mov a,ES ;[INF] 2, 1
|
||
mov x,a ;[INF] 1, 1
|
||
mov a,CS ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
??bf_int_iic_ctr:
|
||
; line 66 : static u8 state = IIC_IDLE;
|
||
; line 67 : static u8 reg_adrs;
|
||
; line 68 : static u8 reg_adrs_internal;
|
||
; line 69 : static u8 tx_buf;
|
||
; line 70 : u8 rx_buf;
|
||
; line 71 :
|
||
; line 72 : EI();
|
||
$DGL 0,8
|
||
ei ;[INF] 3, 4
|
||
; line 73 :
|
||
; line 74 : // <20>ǂݏo<DD8F><6F><EFBFBD>I<EFBFBD><49>
|
||
; line 75 : if( !ACKD ) // <20><><EFBFBD>荞<EFBFBD>ݗv<DD97><76><EFBFBD><EFBFBD>NAK<41>i<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD>M
|
||
; <20>̍Ō<CC8D><C58C>j
|
||
$DGL 0,11
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0541H ; 1345 ;[INF] 3, 1
|
||
mov1 CY,[hl].2 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bc $?L0007 ;[INF] 2, 4
|
||
; line 76 : {
|
||
??bb00_int_iic_ctr:
|
||
; line 77 : state = IIC_IDLE;
|
||
$DGL 0,13
|
||
clrb !?L0003 ; state ;[INF] 3, 1
|
||
; line 78 : SPIE = 0;
|
||
$DGL 0,14
|
||
clr1 !IICCTL01.4 ;[INF] 4, 2
|
||
; line 79 : LREL = 1;
|
||
$DGL 0,15
|
||
set1 !IICCTL01.6 ;[INF] 4, 2
|
||
; line 80 :
|
||
; line 81 : // <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD>[<5B>h<EFBFBD>ŁA<C581><41><EFBFBD>荞<EFBFBD>݃s<DD83><73><EFBFBD><EFBFBD><EFBFBD>l<EFBFBD>Q<EFBFBD>[<5B>g
|
||
; line 82 : // <20>܂<EFBFBD><DC82>ǂ܂<C782><DC82>ĂȂ<C482><C882><EFBFBD><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<CE81>ēx<C493>A<EFBFBD>T<EFBFBD>[<5B>g
|
||
; line 83 : if( irq_readed )
|
||
$DGL 0,19
|
||
bf _irq_readed,$?L0011 ;[INF] 4, 5
|
||
; line 84 : {
|
||
??bb01_int_iic_ctr:
|
||
; line 85 : IRQ0_neg;
|
||
$DGL 0,21
|
||
??bb02_int_iic_ctr:
|
||
set1 PM7.6 ;[INF] 3, 2
|
||
??eb02_int_iic_ctr:
|
||
; line 86 : irq_readed = 0;
|
||
$DGL 0,22
|
||
clr1 _irq_readed ;[INF] 3, 2
|
||
; line 87 : if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 )
|
||
; line 88 : && ( vreg_ctr[VREG_C_IRQ1] == 0 )
|
||
; line 89 : && ( vreg_ctr[VREG_C_IRQ2] == 0 )
|
||
; line 90 : && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) )
|
||
$DGL 0,26
|
||
cmp0 !_vreg_ctr+16 ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
cmp0 !_vreg_ctr+17 ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
cmp0 !_vreg_ctr+18 ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
cmp0 !_vreg_ctr+19 ;[INF] 3, 1
|
||
bz $?L0011 ;[INF] 2, 4
|
||
?L0013:
|
||
; line 91 : {
|
||
??bb03_int_iic_ctr:
|
||
; line 92 : while( !IRQ0 ){;} // <20><><EFBFBD>ԉ҂<D489><D282>s<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD>
|
||
$DGL 0,28
|
||
bt P7.6,$?L0015 ;[INF] 4, 5
|
||
??bb04_int_iic_ctr:
|
||
??eb04_int_iic_ctr:
|
||
br $?L0013 ;[INF] 2, 3
|
||
?L0015:
|
||
; line 93 : IRQ0_ast;
|
||
$DGL 0,29
|
||
??bb05_int_iic_ctr:
|
||
clr1 P7.6 ;[INF] 3, 2
|
||
clr1 PM7.6 ;[INF] 3, 2
|
||
??eb05_int_iic_ctr:
|
||
??eb03_int_iic_ctr:
|
||
; line 94 : }
|
||
?L0011:
|
||
??eb01_int_iic_ctr:
|
||
; line 95 : }
|
||
; line 96 :
|
||
; line 97 : // <20><><EFBFBD><EFBFBD><EFBFBD>v<EFBFBD>ǂݏo<DD8F><6F><EFBFBD>I<EFBFBD><49>
|
||
; line 98 : hosu_read_end( );
|
||
$DGL 0,34
|
||
call !_hosu_read_end ;[INF] 3, 3
|
||
; line 99 : rtc_unlock( );
|
||
$DGL 0,35
|
||
call !_rtc_unlock ;[INF] 3, 3
|
||
; line 100 : iic_burst_state = 0;
|
||
$DGL 0,36
|
||
clrb !_iic_burst_state ;[INF] 3, 1
|
||
; line 101 : return;
|
||
$DGL 0,37
|
||
br !?L0023 ;[INF] 3, 3
|
||
??eb00_int_iic_ctr:
|
||
; line 102 : }
|
||
?L0007:
|
||
; line 103 :
|
||
; line 104 : if( SPD ) // <20><><EFBFBD>荞<EFBFBD>ݗv<DD97><76><EFBFBD>̓X<CD83>g<EFBFBD>b<EFBFBD>v<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B
|
||
; <20>V<EFBFBD><56><EFBFBD><EFBFBD>
|
||
$DGL 0,40
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0541H ; 1345 ;[INF] 3, 1
|
||
mov1 CY,[hl].0 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0016 ;[INF] 2, 4
|
||
; line 105 : // <20>ʐM<CA90>̍Ō<CC8D><C58C>B<EFBFBD><42><EFBFBD><EFBFBD> !ACKD <20>ɗ<EFBFBD><C997><EFBFBD>
|
||
; <20>Ƃ<EFBFBD><C682>͊<EFBFBD><CD8A>荞<EFBFBD>ݗ<EFBFBD><DD97>Ȃ<EFBFBD> (SPIE = 0 <20>̂<EFBFBD><CC82><EFBFBD> )
|
||
; line 106 : {
|
||
??bb06_int_iic_ctr:
|
||
; line 107 : state = IIC_IDLE;
|
||
$DGL 0,43
|
||
clrb !?L0003 ; state ;[INF] 3, 1
|
||
; line 108 : SPIE = 0;
|
||
$DGL 0,44
|
||
clr1 !IICCTL01.4 ;[INF] 4, 2
|
||
; line 109 : // I2C<32>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>ɉ<EFBFBD><C989><EFBFBD><EFBFBD><EFBFBD><EFBFBD>镨 //
|
||
; line 110 : rtc_unlock( );
|
||
$DGL 0,46
|
||
call !_rtc_unlock ;[INF] 3, 3
|
||
; line 111 : return;
|
||
$DGL 0,47
|
||
br !?L0023 ;[INF] 3, 3
|
||
??eb06_int_iic_ctr:
|
||
; line 112 : }
|
||
?L0016:
|
||
; line 113 :
|
||
; line 114 : if( STD ) // <20><><EFBFBD>荞<EFBFBD>ݗv<DD97><76><EFBFBD>F<EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B
|
||
; <20>V<EFBFBD><56><EFBFBD><EFBFBD>
|
||
$DGL 0,50
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0541H ; 1345 ;[INF] 3, 1
|
||
mov1 CY,[hl].1 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0020 ;[INF] 2, 4
|
||
; line 115 : {
|
||
??bb07_int_iic_ctr:
|
||
; line 116 : if( ( state == IIC_TX ) || ( state == IIC_RX )
|
||
; line 117 : || ( state == IIC_RCV_REG_ADRS )
|
||
$DGL 0,53
|
||
cmp !?L0003,#03H ; state,3 ;[INF] 4, 1
|
||
bz $?L0022 ;[INF] 2, 4
|
||
cmp !?L0003,#04H ; state,4 ;[INF] 4, 1
|
||
bz $?L0022 ;[INF] 2, 4
|
||
cmp !?L0003,#01H ; state,1 ;[INF] 4, 1
|
||
sknz ;[INF] 2, 1
|
||
?L0022:
|
||
; line 118 : )
|
||
; line 119 : {
|
||
??bb08_int_iic_ctr:
|
||
; line 120 : state = IIC_IDLE;
|
||
$DGL 0,56
|
||
clrb !?L0003 ; state ;[INF] 3, 1
|
||
??eb08_int_iic_ctr:
|
||
; line 121 : // no break //
|
||
; line 122 : }
|
||
?L0020:
|
||
??eb07_int_iic_ctr:
|
||
; line 123 : }
|
||
; line 124 :
|
||
; line 125 : switch ( state )
|
||
$DGL 0,61
|
||
mov x,!?L0003 ; state ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
onew bc ;[INF] 1, 1
|
||
subw ax,#00H ; 0 ;[INF] 3, 1
|
||
bz $?L0024 ;[INF] 2, 4
|
||
subw ax,bc ;[INF] 1, 1
|
||
bz $?L0025 ;[INF] 2, 4
|
||
subw ax,bc ;[INF] 1, 1
|
||
bz $?L0026 ;[INF] 2, 4
|
||
br $?L0033 ;[INF] 2, 3
|
||
; line 126 : {
|
||
??bb09_int_iic_ctr:
|
||
; line 127 : case ( IIC_IDLE ):
|
||
?L0024:
|
||
; line 128 : // <20><><EFBFBD>njĂяo<D18F><6F><EFBFBD>ɉ<EFBFBD><C989><EFBFBD><EFBFBD>B
|
||
; line 129 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
; line 130 : SPIE = 1;
|
||
$DGL 0,66
|
||
set1 !IICCTL01.4 ;[INF] 4, 2
|
||
; line 131 : state = IIC_RCV_REG_ADRS;
|
||
$DGL 0,67
|
||
oneb !?L0003 ; state ;[INF] 3, 1
|
||
; line 132 : WREL = 1; // <20>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD>
|
||
$DGL 0,68
|
||
set1 !IICCTL01.5 ;[INF] 4, 2
|
||
; line 133 : break;
|
||
$DGL 0,69
|
||
br !?L0023 ;[INF] 3, 3
|
||
; line 134 :
|
||
; line 135 : case ( IIC_RCV_REG_ADRS ): // <20>Q<EFBFBD>o<EFBFBD>C<EFBFBD>g<EFBFBD>ځi<DA81><69><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>j
|
||
; <20><><EFBFBD>M<EFBFBD><4D><EFBFBD>ɗ<EFBFBD><C997><EFBFBD>
|
||
?L0025:
|
||
; line 136 : // <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD><58><EFBFBD>M
|
||
; line 137 : reg_adrs = IICA;
|
||
$DGL 0,73
|
||
mov a,!IICA1 ;[INF] 3, 1
|
||
mov !?L0004,a ; reg_adrs ;[INF] 3, 1
|
||
; line 138 : tx_buf = vreg_ctr_read( reg_adrs ); // <20>f<EFBFBD>[<5B>^<5E>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>Ă<EFBFBD><C482><EFBFBD>
|
||
$DGL 0,74
|
||
mov x,!?L0004 ; reg_adrs ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
call !_vreg_ctr_read ;[INF] 3, 3
|
||
mov a,c ;[INF] 1, 1
|
||
mov !?L0006,a ; tx_buf ;[INF] 3, 1
|
||
; line 139 : if( reg_adrs != VREG_C_INFO )
|
||
$DGL 0,75
|
||
cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1
|
||
bz $?L0030 ;[INF] 2, 4
|
||
; line 140 : {
|
||
??bb0A_int_iic_ctr:
|
||
; line 141 : state = IIC_TX_OR_RX;
|
||
$DGL 0,77
|
||
mov !?L0003,#02H ; state,2 ;[INF] 4, 1
|
||
??eb0A_int_iic_ctr:
|
||
; line 142 : }
|
||
$DGL 0,78
|
||
br $?L0031 ;[INF] 2, 3
|
||
?L0030:
|
||
; line 143 : else
|
||
; line 144 : {
|
||
??bb0B_int_iic_ctr:
|
||
; line 145 : state = IIC_IDLE;
|
||
$DGL 0,81
|
||
clrb !?L0003 ; state ;[INF] 3, 1
|
||
??eb0B_int_iic_ctr:
|
||
; line 146 : }
|
||
?L0031:
|
||
; line 147 : WREL = 1;
|
||
$DGL 0,83
|
||
set1 !IICCTL01.5 ;[INF] 4, 2
|
||
; line 148 : break;
|
||
$DGL 0,84
|
||
br $?L0023 ;[INF] 2, 3
|
||
; line 149 :
|
||
; line 150 : case ( IIC_TX_OR_RX ): // <20><><EFBFBD>̎<EFBFBD><CC8E>ɗ<EFBFBD><C997>銄<EFBFBD>荞<EFBFBD>݁BST<53>Ȃ瑗
|
||
; <20>M<EFBFBD><4D><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>珑<EFBFBD><E78F91><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
?L0026:
|
||
; line 151 : // if( TRC ){ // <20><><EFBFBD>M<EFBFBD><4D><EFBFBD><EFBFBD><EFBFBD>t<EFBFBD><74><EFBFBD>O <20>ŋ<EFBFBD><C58B>ʂ<EFBFBD><CA82><EFBFBD><EFBFBD>̂́A<CD81><41><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>ݒx<DD92><78><EFBFBD><EFBFBD><EFBFBD>ɕs<C995><EFBFBD><EF8D87><EFBFBD>N<EFBFBD><4E><EFBFBD>肦<EFBFBD><E882A6>
|
||
; line 152 : if( STD )
|
||
$DGL 0,88
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0541H ; 1345 ;[INF] 3, 1
|
||
mov1 CY,[hl].1 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0032 ;[INF] 2, 4
|
||
; line 153 : { // <20>X<EFBFBD>^<5E>[<5B>g<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>t<EFBFBD><74>
|
||
; <20>O
|
||
??bb0C_int_iic_ctr:
|
||
; line 154 : // <20><><EFBFBD>[<5B>h<EFBFBD><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 155 : if( COI )
|
||
$DGL 0,91
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0541H ; 1345 ;[INF] 3, 1
|
||
mov1 CY,[hl].4 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0034 ;[INF] 2, 4
|
||
; line 156 : { // <20>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD><58><EFBFBD>v<EFBFBD>t<EFBFBD><74><EFBFBD>O
|
||
??bb0D_int_iic_ctr:
|
||
; line 157 : state = IIC_TX;
|
||
$DGL 0,93
|
||
mov !?L0003,#03H ; state,3 ;[INF] 4, 1
|
||
??eb0D_int_iic_ctr:
|
||
; line 158 : // no break, no return //
|
||
; line 159 : }
|
||
$DGL 0,95
|
||
br $?L0033 ;[INF] 2, 3
|
||
?L0034:
|
||
; line 160 : else
|
||
; line 161 : {
|
||
??bb0E_int_iic_ctr:
|
||
; line 162 : // <20><><EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>ňႤ<C588>f<EFBFBD>o<EFBFBD>C<EFBFBD>X<EFBFBD><58><EFBFBD>Ăꂽ<CE82>I
|
||
; line 163 : state = IIC_IDLE; // <20>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
$DGL 0,99
|
||
clrb !?L0003 ; state ;[INF] 3, 1
|
||
; line 164 : SPIE = 0;
|
||
$DGL 0,100
|
||
clr1 !IICCTL01.4 ;[INF] 4, 2
|
||
; line 165 : LREL = 1; // <20>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD>?
|
||
$DGL 0,101
|
||
set1 !IICCTL01.6 ;[INF] 4, 2
|
||
; line 166 : return;
|
||
$DGL 0,102
|
||
br $?L0023 ;[INF] 2, 3
|
||
??eb0E_int_iic_ctr:
|
||
; line 167 : }
|
||
; line 168 : }
|
||
??eb0C_int_iic_ctr:
|
||
?L0032:
|
||
; line 169 : else
|
||
; line 170 : {
|
||
??bb0F_int_iic_ctr:
|
||
; line 171 : state = IIC_RX; // <20>f<EFBFBD>[<5B>^1<>o<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>M<EFBFBD>̊<EFBFBD><CC8A>荞<EFBFBD>݂<EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD>
|
||
$DGL 0,107
|
||
mov !?L0003,#04H ; state,4 ;[INF] 4, 1
|
||
??eb0F_int_iic_ctr:
|
||
; line 172 : // no break, no return //
|
||
; line 173 : }
|
||
?L0033:
|
||
; line 174 :
|
||
; line 175 : default: // <20>o<EFBFBD>[<5B>X<EFBFBD>g R/W <20>ł<EFBFBD><C582><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><EFBFBD><CE82>邱<EFBFBD>ƂɂȂ<C982>
|
||
; line 176 : if( state == IIC_TX )
|
||
$DGL 0,112
|
||
cmp !?L0003,#03H ; state,3 ;[INF] 4, 1
|
||
bnz $?L0036 ;[INF] 2, 4
|
||
; line 177 : { // <20><><EFBFBD>M
|
||
??bb10_int_iic_ctr:
|
||
; line 178 : IICA = tx_buf;
|
||
$DGL 0,114
|
||
mov a,!?L0006 ; tx_buf ;[INF] 3, 1
|
||
mov !IICA1,a ;[INF] 3, 1
|
||
; line 179 : vreg_ctr_after_read( reg_adrs ); // <20>ǂ<C782><F182BE82>N<EFBFBD><4E><EFBFBD>A
|
||
; <20>Ȃǂ̏<C782><CC8F><EFBFBD>
|
||
$DGL 0,115
|
||
mov x,!?L0004 ; reg_adrs ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
call !_vreg_ctr_after_read ;[INF] 3, 3
|
||
??eb10_int_iic_ctr:
|
||
; line 180 : }
|
||
$DGL 0,116
|
||
br $?L0037 ;[INF] 2, 3
|
||
?L0036:
|
||
; line 181 : else
|
||
; line 182 : { // <20><><EFBFBD>M
|
||
??bb11_int_iic_ctr:
|
||
; line 183 : rx_buf = IICA;
|
||
$DGL 0,119
|
||
mov a,!IICA1 ;[INF] 3, 1
|
||
mov l,a ;[INF] 1, 1
|
||
; line 184 : vreg_ctr_write( reg_adrs, rx_buf );
|
||
$DGL 0,120
|
||
movw ax,hl ;[INF] 1, 1
|
||
clrb a ;[INF] 1, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,!?L0004 ; reg_adrs ;[INF] 3, 1
|
||
call !_vreg_ctr_write ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
; line 185 : WREL = 1;
|
||
$DGL 0,121
|
||
set1 !IICCTL01.5 ;[INF] 4, 2
|
||
??eb11_int_iic_ctr:
|
||
; line 186 : }
|
||
?L0037:
|
||
; line 187 : //
|
||
; line 188 : if( ( reg_adrs != VREG_C_ACC_HOSU_HIST )
|
||
; line 189 : && ( reg_adrs != VREG_C_INFO ) )
|
||
$DGL 0,125
|
||
cmp !?L0004,#04FH ; reg_adrs,79 ;[INF] 4, 1
|
||
bz $?L0038 ;[INF] 2, 4
|
||
cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1
|
||
skz ;[INF] 2, 1
|
||
; line 190 : { // <20><><EFBFBD>̓<EFBFBD><CC93>̃<C282><CC83>W<EFBFBD>X<EFBFBD>^<5E>͓<EFBFBD><CD93><EFBFBD><EFBFBD>ȃA<C883>N<EFBFBD>Z<EFBFBD>X<EFBFBD><58><EFBFBD>@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD>A<EFBFBD>N
|
||
; <20>Z<EFBFBD>X<EFBFBD>|<7C>C<EFBFBD><43><EFBFBD>^<5E><><EFBFBD>i<EFBFBD>߂Ȃ<DF82><C882>B
|
||
??bb12_int_iic_ctr:
|
||
; line 191 : reg_adrs += 1;
|
||
$DGL 0,127
|
||
inc !?L0004 ; reg_adrs ;[INF] 3, 2
|
||
??eb12_int_iic_ctr:
|
||
; line 192 : }
|
||
?L0038:
|
||
; line 193 :
|
||
; line 194 : if( state == IIC_TX )
|
||
$DGL 0,130
|
||
cmp !?L0003,#03H ; state,3 ;[INF] 4, 1
|
||
bnz $?L0023 ;[INF] 2, 4
|
||
; line 195 : { // <20><><EFBFBD><EFBFBD><EFBFBD>ɂ<C982><C282>ɑ<EFBFBD><C991><EFBFBD><EFBFBD>f<EFBFBD>[<5B>^<5E>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>V<EFBFBD>e<EFBFBD>I<EFBFBD>N<EFBFBD>BSP<53><50><EFBFBD><EFBFBD><EFBFBD>Ďg<C48E><67><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
??bb13_int_iic_ctr:
|
||
; line 196 : tx_buf = vreg_ctr_read( reg_adrs );
|
||
$DGL 0,132
|
||
mov x,!?L0004 ; reg_adrs ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
call !_vreg_ctr_read ;[INF] 3, 3
|
||
mov a,c ;[INF] 1, 1
|
||
mov !?L0006,a ; tx_buf ;[INF] 3, 1
|
||
??eb13_int_iic_ctr:
|
||
; line 197 : }
|
||
; line 198 : break;
|
||
??eb09_int_iic_ctr:
|
||
; line 199 : }
|
||
?L0023:
|
||
; line 200 : }
|
||
$DGL 0,136
|
||
??ef_int_iic_ctr:
|
||
pop ax ;[INF] 1, 1
|
||
mov CS,a ;[INF] 2, 1
|
||
mov a,x ;[INF] 1, 1
|
||
mov ES,a ;[INF] 2, 1
|
||
movw de,#_@SEGAX ;[INF] 3, 1
|
||
mov c,#06H ;[INF] 2, 1
|
||
pop ax ;[INF] 1, 1
|
||
movw [de],ax ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $$-5 ;[INF] 2, 4
|
||
pop hl ;[INF] 1, 1
|
||
pop de ;[INF] 1, 1
|
||
pop bc ;[INF] 1, 1
|
||
pop ax ;[INF] 1, 1
|
||
reti ;[INF] 2, 6
|
||
??ee_int_iic_ctr:
|
||
; line 201 :
|
||
; line 202 :
|
||
; line 203 :
|
||
; line 204 : // ========================================================
|
||
; line 205 : void IIC_ctr_Init( void )
|
||
; line 206 : {
|
||
|
||
ROM_CODE CSEG BASE
|
||
_IIC_ctr_Init:
|
||
$DGL 1,112
|
||
??bf_IIC_ctr_Init:
|
||
; line 207 :
|
||
; line 208 : IICAEN = 1;
|
||
$DGL 0,3
|
||
set1 !PER3.0 ;[INF] 4, 2
|
||
; line 209 :
|
||
; line 210 : IICE = 0; /* IICA disable */
|
||
$DGL 0,5
|
||
clr1 !IICCTL01.7 ;[INF] 4, 2
|
||
; line 211 :
|
||
; line 212 : IICAMK = 1; /* INTIICA disable */
|
||
$DGL 0,7
|
||
set1 MK2H.3 ;[INF] 3, 2
|
||
; line 213 : IICAIF = 0; /* clear INTIICA interrupt flag
|
||
; */
|
||
$DGL 0,8
|
||
clr1 IF2H.3 ;[INF] 3, 2
|
||
; line 214 :
|
||
; line 215 : IICAPR0 = 1; /* set INTIICA high priority */
|
||
$DGL 0,10
|
||
set1 PR12H.3 ;[INF] 3, 2
|
||
; line 216 : IICAPR1 = 0; /* set INTIICA high priority */
|
||
$DGL 0,11
|
||
clr1 PR02H.3 ;[INF] 3, 2
|
||
; line 217 :
|
||
; line 218 : #ifdef _MODEL_TEG2_
|
||
; line 219 : P6 &= ~0x3;
|
||
; line 220 : #else
|
||
; line 221 : P20 &= ~0x3;
|
||
$DGL 0,16
|
||
mov a,!P20 ;[INF] 3, 1
|
||
and a,#0FCH ; 252 ;[INF] 2, 1
|
||
mov !P20,a ;[INF] 3, 1
|
||
; line 222 : #endif
|
||
; line 223 :
|
||
; line 224 : SVA = IIC_C_SLAVEADDRESS;
|
||
$DGL 0,19
|
||
mov !SVA1,#04AH ; 74 ;[INF] 4, 1
|
||
; line 225 : IICF = 0x01;
|
||
$DGL 0,20
|
||
oneb !IICF1 ;[INF] 3, 1
|
||
; line 226 :
|
||
; line 227 : STCEN = 1; // <20><><EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>̋<EFBFBD><CC8B><EFBFBD>
|
||
$DGL 0,22
|
||
set1 !IICF1.1 ;[INF] 4, 2
|
||
; line 228 : IICRSV = 1; // <20>ʐM<CA90>\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>:<3A>X<EFBFBD><58><EFBFBD>[<5B>u<EFBFBD><75>
|
||
; <20>O<EFBFBD><4F><EFBFBD><EFBFBD>
|
||
$DGL 0,23
|
||
set1 !IICF1.0 ;[INF] 4, 2
|
||
; line 229 :
|
||
; line 230 : SPIE = 0; // <20>X<EFBFBD>g<EFBFBD>b<EFBFBD>v<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>ł̊<C582><CC8A><EFBFBD>
|
||
; <20><><EFBFBD>݂<EFBFBD><DD82>֎~
|
||
$DGL 0,25
|
||
clr1 !IICCTL01.4 ;[INF] 4, 2
|
||
; line 231 : WTIM = 1; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ACK<43><4B><EFBFBD>Ԃ<EFBFBD><D482><EFBFBD><EFBFBD><EFBFBD>clk<6C><6B>L<EFBFBD>Ɍ<EFBFBD>
|
||
; <20>肷<EFBFBD><E882B7>
|
||
$DGL 0,26
|
||
set1 !IICCTL01.3 ;[INF] 4, 2
|
||
; line 232 : ACKE = 1; // <20>_<EFBFBD><5F>CPU<50>͖<EFBFBD><CD96><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ď<EFBFBD><C48E>̒ʐM<CA90><4D><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>߂邩<DF82><E982A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD>ő<EFBFBD><C591><EFBFBD>clk<6C><6B><EFBFBD>J<EFBFBD><4A><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
$DGL 0,27
|
||
set1 !IICCTL01.2 ;[INF] 4, 2
|
||
; line 233 :
|
||
; line 234 : IICWH = 5;
|
||
$DGL 0,29
|
||
mov !IICWH1,#05H ; 5 ;[INF] 4, 1
|
||
; line 235 : IICWL = 10; // L<><4C><EFBFBD>Ԃ̒<D482><CC92><EFBFBD>
|
||
$DGL 0,30
|
||
mov !IICWL1,#0AH ; 10 ;[INF] 4, 1
|
||
; line 236 :
|
||
; line 237 : SMC = 1; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>[<5B>h
|
||
$DGL 0,32
|
||
set1 !IICCTL11.3 ;[INF] 4, 2
|
||
; line 238 : DFC = 1; // <20>f<EFBFBD>W<EFBFBD>^<5E><><EFBFBD>t<EFBFBD>B<EFBFBD><42><EFBFBD>^on (@fast mod
|
||
; e)
|
||
$DGL 0,33
|
||
set1 !IICCTL11.2 ;[INF] 4, 2
|
||
; line 239 :
|
||
; line 240 : IICAMK = 0; // <20><><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD>
|
||
$DGL 0,35
|
||
clr1 MK2H.3 ;[INF] 3, 2
|
||
; line 241 :
|
||
; line 242 : IICE = 1;
|
||
$DGL 0,37
|
||
set1 !IICCTL01.7 ;[INF] 4, 2
|
||
; line 243 :
|
||
; line 244 : #ifdef _MODEL_TEG2_
|
||
; line 245 : PM6 &= ~0x3; /* set clock pin for IICA */
|
||
; line 246 : #else
|
||
; line 247 : PM20 &= ~0x3; /* set clock pin for IICA */
|
||
$DGL 0,42
|
||
mov a,!PM20 ;[INF] 3, 1
|
||
and a,#0FCH ; 252 ;[INF] 2, 1
|
||
mov !PM20,a ;[INF] 3, 1
|
||
; line 248 : #endif
|
||
; line 249 : }
|
||
$DGL 0,44
|
||
??ef_IIC_ctr_Init:
|
||
ret ;[INF] 1, 6
|
||
??ee_IIC_ctr_Init:
|
||
; line 250 :
|
||
; line 251 :
|
||
; line 252 :
|
||
; line 253 : // ========================================================
|
||
; line 254 : void IIC_ctr_Stop( void )
|
||
; line 255 : {
|
||
_IIC_ctr_Stop:
|
||
$DGL 1,118
|
||
??bf_IIC_ctr_Stop:
|
||
; line 256 : IICE = 0; /* IICA disable */
|
||
$DGL 0,2
|
||
clr1 !IICCTL01.7 ;[INF] 4, 2
|
||
; line 257 : IICAEN = 0;
|
||
$DGL 0,3
|
||
clr1 !PER3.0 ;[INF] 4, 2
|
||
; line 258 : }
|
||
$DGL 0,4
|
||
??ef_IIC_ctr_Stop:
|
||
ret ;[INF] 1, 6
|
||
??ee_IIC_ctr_Stop:
|
||
|
||
@@CODEL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c
|
||
;
|
||
; $FUNC int_iic_ctr(65)
|
||
; void=(void)
|
||
; CODE SIZE= 355 bytes, CLOCK_SIZE= 278 clocks, STACK_SIZE= 28 bytes
|
||
;
|
||
; $CALL hosu_read_end(98)
|
||
; void=(void)
|
||
;
|
||
; $CALL rtc_unlock(99)
|
||
; void=(void)
|
||
;
|
||
; $CALL rtc_unlock(110)
|
||
; void=(void)
|
||
;
|
||
; $CALL vreg_ctr_read(138)
|
||
; bc=(int:ax)
|
||
;
|
||
; $CALL vreg_ctr_after_read(179)
|
||
; void=(int:ax)
|
||
;
|
||
; $CALL vreg_ctr_write(184)
|
||
; void=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL vreg_ctr_read(196)
|
||
; bc=(int:ax)
|
||
;
|
||
; $FUNC IIC_ctr_Init(206)
|
||
; void=(void)
|
||
; CODE SIZE= 87 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC IIC_ctr_Stop(255)
|
||
; void=(void)
|
||
; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|