78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\vreg_ctr.asm Para-file: In-file: inter_asm\vreg_ctr.asm Obj-file: vreg_ctr.rel Prn-file: vreg_ctr.prn Assemble list ALNO STNO ADRS OBJECT M I SOURCE STATEMENT 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 2 2 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_ctr.c 6 6 ; In-file : vreg_ctr.c 7 7 ; Asm-file : inter_asm\vreg_ctr.asm 8 8 ; Para-file : 9 9 10 10 $PROCESSOR(9F0104) 11 11 $DEBUG 12 12 $NODEBUGA 13 13 $KANJICODE SJIS 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H 15 15 16 16 $DGS FIL_NAM, .file, 0A1H, 0FFFEH, 03FH, 067H, 01H, 00H 17 17 $DGS AUX_FIL, vreg_ctr.c 18 18 $DGS MOD_NAM, vreg_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H 35 35 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 36 36 $DGS AUX_TAG, 01H, 019H 37 37 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H 38 38 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H 39 39 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 40 40 $DGS AUX_EOS, 013H, 01H 41 41 $DGS LAB_SYM, bs_S0105, U, U, 00H, 06H, 00H, 00H 42 42 $DGS LAB_SYM, es_S0105, U, U, 00H, 06H, 00H, 00H 43 43 $DGS LAB_SYM, bs_S0106, U, U, 00H, 06H, 00H, 00H 44 44 $DGS LAB_SYM, es_S0106, U, U, 00H, 06H, 00H, 00H 45 45 $DGS LAB_SYM, bs_S0104, U, U, 00H, 06H, 00H, 00H 46 46 $DGS LAB_SYM, es_S0104, U, U, 00H, 06H, 00H, 00H 47 47 $DGS LAB_SYM, bs_F0102, U, U, 00H, 06H, 00H, 00H 48 48 $DGS LAB_SYM, es_F0102, U, U, 00H, 06H, 00H, 00H 49 49 $DGS LAB_SYM, bs_S0103, U, U, 00H, 06H, 00H, 00H 50 50 $DGS LAB_SYM, es_S0103, U, U, 00H, 06H, 00H, 00H 51 51 $DGS LAB_SYM, bs_F0101, U, U, 00H, 06H, 00H, 00H 52 52 $DGS LAB_SYM, es_F0101, U, U, 00H, 06H, 00H, 00H 53 53 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H 54 54 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H 55 55 $DGS GLV_SYM, _vreg_ctr_init, U, U, 01H, 026H, 01H, 02H 56 56 $DGS AUX_FUN, 00H, U, U, 02DH, 00H, 00H 57 57 $DGS BEG_FUN, ??bf_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H 58 58 $DGS AUX_BEG, 02AH, 00H, 02DH 59 59 $DGS END_FUN, ??ef_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H 60 60 $DGS AUX_END, 0DH 61 61 $DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 026H, 01H, 02H 62 62 $DGS AUX_FUN, 00H, U, U, 059H, 00H, 00H 63 63 $DGS BEG_FUN, ??bf_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H 64 64 $DGS AUX_BEG, 042H, 02H, 033H 65 65 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H 66 66 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H 67 67 $DGS BEG_BLK, ??bb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 68 68 $DGS AUX_BEG, 06H, 00H, 035H 69 69 $DGS BEG_BLK, ??bb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 70 70 $DGS AUX_BEG, 01CH, 00H, 039H 71 71 $DGS END_BLK, ??eb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 72 72 $DGS AUX_END, 01FH 73 73 $DGS BEG_BLK, ??bb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 74 74 $DGS AUX_BEG, 02DH, 00H, 03DH 75 75 $DGS END_BLK, ??eb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 76 76 $DGS AUX_END, 02FH 77 77 $DGS BEG_BLK, ??bb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 78 78 $DGS AUX_BEG, 036H, 00H, 041H 79 79 $DGS END_BLK, ??eb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 80 80 $DGS AUX_END, 038H 81 81 $DGS BEG_BLK, ??bb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 82 82 $DGS AUX_BEG, 03AH, 00H, 045H 83 83 $DGS END_BLK, ??eb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 84 84 $DGS AUX_END, 03CH 85 85 $DGS BEG_BLK, ??bb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 86 86 $DGS AUX_BEG, 041H, 00H, 049H 87 87 $DGS END_BLK, ??eb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 88 88 $DGS AUX_END, 044H 89 89 $DGS BEG_BLK, ??bb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 90 90 $DGS AUX_BEG, 049H, 00H, 04DH 91 91 $DGS END_BLK, ??eb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 92 92 $DGS AUX_END, 055H 93 93 $DGS BEG_BLK, ??bb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 94 94 $DGS AUX_BEG, 0D1H, 00H, 051H 95 95 $DGS END_BLK, ??eb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 96 96 $DGS AUX_END, 0D3H 97 97 $DGS BEG_BLK, ??bb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 98 98 $DGS AUX_BEG, 0D9H, 00H, 00H 99 99 $DGS END_BLK, ??eb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 100 100 $DGS AUX_END, 0E3H 101 101 $DGS END_BLK, ??eb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H 102 102 $DGS AUX_END, 0E4H 103 103 $DGS END_FUN, ??ef_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H 104 104 $DGS AUX_END, 0E6H 105 105 $DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 026H, 01H, 02H 106 106 $DGS AUX_FUN, 00H, U, U, 07DH, 00H, 00H 107 107 $DGS BEG_FUN, ??bf_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H 108 108 $DGS AUX_BEG, 0131H, 02H, 05FH 109 109 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H 110 110 $DGS STA_SYM, _rsub_temp, ?L0073, U, 0DH, 03H, 00H, 00H 111 111 $DGS BEG_BLK, ??bb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 112 112 $DGS AUX_BEG, 06H, 00H, 063H 113 113 $DGS END_BLK, ??eb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 114 114 $DGS AUX_END, 08H 115 115 $DGS BEG_BLK, ??bb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 116 116 $DGS AUX_BEG, 0AH, 00H, 067H 117 117 $DGS END_BLK, ??eb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 118 118 $DGS AUX_END, 0CH 119 119 $DGS BEG_BLK, ??bb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 120 120 $DGS AUX_BEG, 0EH, 00H, 06BH 121 121 $DGS END_BLK, ??eb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 122 122 $DGS AUX_END, 010H 123 123 $DGS BEG_BLK, ??bb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 124 124 $DGS AUX_BEG, 012H, 00H, 06FH 125 125 $DGS END_BLK, ??eb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 126 126 $DGS AUX_END, 015H 127 127 $DGS BEG_BLK, ??bb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 128 128 $DGS AUX_BEG, 017H, 00H, 073H 129 129 $DGS END_BLK, ??eb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 130 130 $DGS AUX_END, 019H 131 131 $DGS BEG_BLK, ??bb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 132 132 $DGS AUX_BEG, 01BH, 00H, 077H 133 133 $DGS END_BLK, ??eb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 134 134 $DGS AUX_END, 01FH 135 135 $DGS BEG_BLK, ??bb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 136 136 $DGS AUX_BEG, 023H, 00H, 00H 137 137 $DGS END_BLK, ??eb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H 138 138 $DGS AUX_END, 027H 139 139 $DGS END_FUN, ??ef_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H 140 140 $DGS AUX_END, 02AH 141 141 $DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 026H, 01H, 02H 142 142 $DGS AUX_FUN, 00H, U, U, 088H, 00H, 00H 143 143 $DGS BEG_FUN, ??bf_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H 144 144 $DGS AUX_BEG, 0161H, 02H, 082H 145 145 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H 146 146 $DGS BEG_BLK, ??bb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H 147 147 $DGS AUX_BEG, 05H, 00H, 00H 148 148 $DGS END_BLK, ??eb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H 149 149 $DGS AUX_END, 011H 150 150 $DGS END_FUN, ??ef_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H 151 151 $DGS AUX_END, 012H 152 152 $DGS GLV_SYM, _set_irq, U, U, 01H, 026H, 01H, 02H 153 153 $DGS AUX_FUN, 00H, U, U, 0A1H, 00H, 00H 154 154 $DGS BEG_FUN, ??bf_set_irq, U, U, 00H, 065H, 01H, 00H 155 155 $DGS AUX_BEG, 018AH, 04H, 08FH 156 156 $DGS FUN_ARG, _irqreg, 02H, 0FFFFH, 0CH, 09H, 00H, 00H 157 157 $DGS FUN_ARG, _irq_flg, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H 158 158 $DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 00H, 00H 159 159 $DGS BEG_BLK, ??bb00_set_irq, U, U, 00H, 064H, 01H, 00H 160 160 $DGS AUX_BEG, 05H, 00H, 091H 161 161 $DGS BEG_BLK, ??bb01_set_irq, U, U, 00H, 064H, 01H, 00H 162 162 $DGS AUX_BEG, 07H, 00H, 095H 163 163 $DGS END_BLK, ??eb01_set_irq, U, U, 00H, 064H, 01H, 00H 164 164 $DGS AUX_END, 07H 165 165 $DGS BEG_BLK, ??bb02_set_irq, U, U, 00H, 064H, 01H, 00H 166 166 $DGS AUX_BEG, 0AH, 00H, 099H 167 167 $DGS END_BLK, ??eb02_set_irq, U, U, 00H, 064H, 01H, 00H 168 168 $DGS AUX_END, 0AH 169 169 $DGS BEG_BLK, ??bb03_set_irq, U, U, 00H, 064H, 01H, 00H 170 170 $DGS AUX_BEG, 0BH, 00H, 00H 171 171 $DGS END_BLK, ??eb03_set_irq, U, U, 00H, 064H, 01H, 00H 172 172 $DGS AUX_END, 0BH 173 173 $DGS END_BLK, ??eb00_set_irq, U, U, 00H, 064H, 01H, 00H 174 174 $DGS AUX_END, 0CH 175 175 $DGS END_FUN, ??ef_set_irq, U, U, 00H, 065H, 01H, 00H 176 176 $DGS AUX_END, 0EH 177 177 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 026H, 01H, 03H 178 178 $DGS AUX_STR, 00H, 00H, 060H, 060H, 00H, 00H, 00H, 00H 179 179 $DGS GLV_SYM, _irq_readed, U, U, 034CH, 027H, 00H, 00H 180 180 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H 181 181 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H 182 182 $DGS GLV_SYM, _set_rtc, U, U, 01H, 02H, 01H, 02H 183 183 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 184 184 $DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 02H, 01H, 02H 185 185 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 186 186 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H 187 187 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 188 188 $DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 02H, 01H, 02H 189 189 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 190 190 $DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H 191 191 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 192 192 $DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 02H, 01H, 02H 193 193 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 194 194 $DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 02H, 01H, 02H 195 195 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 196 196 $DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 02H, 01H, 02H 197 197 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 198 198 $DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 02H, 00H, 00H 199 199 $DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 02H, 01H, 02H 200 200 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 201 201 $DGS GLV_SYM, _acc_read, U, U, 0AH, 02H, 01H, 02H 202 202 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 203 203 $DGS GLV_SYM, _acc_write, U, U, 0AH, 02H, 01H, 02H 204 204 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 205 205 $DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 02H, 01H, 02H 206 206 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 207 207 $DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 02H, 01H, 02H 208 208 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 209 209 $DGS GLV_SYM, _hosu_read, U, U, 0CH, 02H, 01H, 02H 210 210 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 211 211 $DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 02H, 01H, 02H 212 212 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H 213 213 214 214 EXTRN _vreg_twl 215 215 EXTRN _set_rtc 216 216 EXTRN _tski_vcom_set 217 217 EXTRN _renge_task_immed_add 218 218 EXTRN _tski_firm_update 219 219 EXTRN _do_command0 220 220 EXTRN _tski_PM_LCD_on 221 221 EXTRN _tski_PM_LCD_off 222 222 EXTRN _tski_PM_BL_set 223 223 EXTRN _acc_hosu_set 224 224 EXTRN _acc_read 225 225 EXTRN _acc_write 226 226 EXTRN _clear_hosu_hist 227 227 EXTRN _rtc_buf_reflesh 228 228 EXTRN _hosu_read 229 229 EXTRN _tski_mcu_info_read 230 230 EXTBIT _rtc_alarm_dirty 231 231 PUBLIC _vreg_ctr 232 232 PUBLIC _irq_readed 233 233 PUBLIC _vreg_ctr_init 234 234 PUBLIC _vreg_ctr_write 235 235 PUBLIC _vreg_ctr_read 236 236 PUBLIC _vreg_ctr_after_read 237 237 PUBLIC _set_irq 238 238 239 239 ----- @@BITS BSEG 240 240 00000.0 _irq_readed DBIT 241 241 242 242 ----- @@CNST CSEG MIRRORP 243 243 00000 01 _lpf_coeff: DB 01H ; 1 244 244 00001 02 DB 02H ; 2 245 245 00002 02 DB 02H ; 2 246 246 00003 03 DB 03H ; 3 247 247 00004 03 DB 03H ; 3 248 248 00005 02 DB 02H ; 2 249 249 00006 00 DB 00H ; 0 250 250 00007 FE DB 0FEH ; 254 251 251 00008 FB DB 0FBH ; 251 252 252 00009 F7 DB 0F7H ; 247 253 253 0000A F3 DB 0F3H ; 243 254 254 0000B F0 DB 0F0H ; 240 255 255 0000C F0 DB 0F0H ; 240 256 256 0000D F3 DB 0F3H ; 243 257 257 0000E FA DB 0FAH ; 250 258 258 0000F 04 DB 04H ; 4 259 259 00010 12 DB 012H ; 18 260 260 00011 25 DB 025H ; 37 261 261 00012 38 DB 038H ; 56 262 262 00013 4D DB 04DH ; 77 263 263 00014 5F DB 05FH ; 95 264 264 00015 6E DB 06EH ; 110 265 265 00016 77 DB 077H ; 119 266 266 00017 7A DB 07AH ; 122 267 267 00018 77 DB 077H ; 119 268 268 00019 6E DB 06EH ; 110 269 269 0001A 5F DB 05FH ; 95 270 270 0001B 4D DB 04DH ; 77 271 271 0001C 38 DB 038H ; 56 272 272 0001D 25 DB 025H ; 37 273 273 0001E 12 DB 012H ; 18 274 274 0001F 04 DB 04H ; 4 275 275 00020 FA DB 0FAH ; 250 276 276 00021 F3 DB 0F3H ; 243 277 277 00022 F0 DB 0F0H ; 240 278 278 00023 F0 DB 0F0H ; 240 279 279 00024 F3 DB 0F3H ; 243 280 280 00025 F7 DB 0F7H ; 247 281 281 00026 FB DB 0FBH ; 251 282 282 00027 FE DB 0FEH ; 254 283 283 00028 00 DB 00H ; 0 284 284 00029 02 DB 02H ; 2 285 285 0002A 03 DB 03H ; 3 286 286 0002B 03 DB 03H ; 3 287 287 0002C 02 DB 02H ; 2 288 288 0002D 02 DB 02H ; 2 289 289 0002E 01 DB 01H ; 1 290 290 0002F 00 DB (1) 291 291 292 292 ----- @@R_INIT CSEG UNIT64KP 293 293 294 294 ----- @@INIT DSEG BASEP 295 295 296 296 ----- @@DATA DSEG BASEP 297 297 00000 _vreg_ctr: DS (96) 298 298 00060 ?L0073: DS (2) 299 299 300 300 ----- @@R_INIS CSEG UNIT64KP 301 301 302 302 ----- @@INIS DSEG SADDRP 303 303 304 304 ----- @@DATS DSEG SADDRP 305 305 306 306 ----- @@CNSTL CSEG PAGE64KP 307 307 308 308 ----- @@RLINIT CSEG UNIT64KP 309 309 310 310 ----- @@INITL DSEG UNIT64KP 311 311 312 312 ----- @@DATAL DSEG UNIT64KP 313 313 314 314 ----- @@CALT CSEG CALLT0 315 315 316 316 ; Sub-Routines created by CC78K0R 317 317 318 318 ----- ROM_CODE CSEG BASE 319 319 00000 bs_S0105: 320 320 00000 66 mov a,l ;[INF] 1, 1 321 321 00001 73 mov b,a ;[INF] 1, 1 322 322 00002 67 mov a,h ;[INF] 1, 1 323 323 00003 R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 324 324 00006 D7 ret ;[INF] 1, 6 325 325 00007 es_S0105: 326 326 327 327 ----- ROM_CODE CSEG BASE 328 328 00007 bs_S0106: 329 329 00007 R340100 movw de,#loww (_vreg_twl+1) ;[INF] 3, 1 330 330 0000A 89 mov a,[de] ;[INF] 1, 1 331 331 0000B 6168 or a,x ;[INF] 2, 1 332 332 0000D 99 mov [de],a ;[INF] 1, 1 333 333 0000E D7 ret ;[INF] 1, 6 334 334 0000F es_S0106: 335 335 336 336 ----- ROM_CODE CSEG BASE 337 337 0000F bs_S0104: 338 338 0000F 72 mov c,a ;[INF] 1, 1 339 339 00010 66 mov a,l ;[INF] 1, 1 340 340 00011 73 mov b,a ;[INF] 1, 1 341 341 00012 62 mov a,c ;[INF] 1, 1 342 342 00013 R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 343 343 00016 D7 ret ;[INF] 1, 6 344 344 00017 es_S0104: 345 345 346 346 ----- ROM_CODE CSEG BASE 347 347 00017 bs_F0102: 348 348 00017 318E shrw ax,8 ;[INF] 2, 1 349 349 00019 C1 push ax ;[INF] 1, 1 350 350 0001A 17 movw ax,hl ;[INF] 1, 1 351 351 0001B F1 clrb a ;[INF] 1, 1 352 352 0001C 243000 subw ax,#030H ; 48 ;[INF] 3, 1 353 353 0001F RFD0000 call !_set_rtc ;[INF] 3, 3 354 354 00022 C0 pop ax ;[INF] 1, 1 355 355 00023 D7 ret ;[INF] 1, 6 356 356 00024 es_F0102: 357 357 358 358 ----- ROM_CODE CSEG BASE 359 359 00024 bs_S0103: 360 360 00024 67 mov a,h ;[INF] 1, 1 361 361 00025 5C3F and a,#03FH ; 63 ;[INF] 2, 1 362 362 00027 72 mov c,a ;[INF] 1, 1 363 363 00028 66 mov a,l ;[INF] 1, 1 364 364 00029 73 mov b,a ;[INF] 1, 1 365 365 0002A 62 mov a,c ;[INF] 1, 1 366 366 0002B R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 367 367 0002E D7 ret ;[INF] 1, 6 368 368 0002F es_S0103: 369 369 370 370 ----- ROM_CODE CSEG BASE 371 371 0002F bs_F0101: 372 372 0002F 5C3F and a,#03FH ; 63 ;[INF] 2, 1 373 373 00031 318E shrw ax,8 ;[INF] 2, 1 374 374 00033 C1 push ax ;[INF] 1, 1 375 375 00034 17 movw ax,hl ;[INF] 1, 1 376 376 00035 F1 clrb a ;[INF] 1, 1 377 377 00036 243000 subw ax,#030H ; 48 ;[INF] 3, 1 378 378 00039 RFD0000 call !_set_rtc ;[INF] 3, 3 379 379 0003C C0 pop ax ;[INF] 1, 1 380 380 0003D D7 ret ;[INF] 1, 6 381 381 0003E es_F0101: 382 382 383 383 ; *** Sub-Routine Information *** 384 384 ; 385 385 ; $SUB bs_F0101 386 386 ; CODE SIZE= 15 bytes 387 387 ; 388 388 ; $SUB bs_F0102 389 389 ; CODE SIZE= 13 bytes 390 390 ; 391 391 ; $SUB bs_S0103 392 392 ; CODE SIZE= 11 bytes 393 393 ; 394 394 ; $SUB bs_S0104 395 395 ; CODE SIZE= 8 bytes 396 396 ; 397 397 ; $SUB bs_S0105 398 398 ; CODE SIZE= 7 bytes 399 399 ; 400 400 ; $SUB bs_S0106 401 401 ; CODE SIZE= 8 bytes 402 402 403 403 ; End of Sub-Routines 404 404 405 405 ; line 1 : /* ======================================================== 406 406 ; line 2 : 407 407 ; line 3 : CTR MCU I2Cレジスタ 408 408 ; line 4 : 409 409 ; line 5 : ====================================================== */ 410 410 ; line 6 : #include "incs.h" 411 411 ; line 7 : #include "vreg_ctr.h" 412 412 ; line 8 : #include "rtc.h" 413 413 ; line 9 : #include "led.h" 414 414 ; line 10 : #include "accero.h" 415 415 ; line 11 : #include "pm.h" 416 416 ; line 12 : 417 417 ; line 13 : #include 418 418 ; line 14 : #include "fsl_user.h" 419 419 ; line 15 : 420 420 ; line 16 : extern u8 mcu_info_read(); // task_misc.c 421 421 ; line 17 : 422 422 ; line 18 : 423 423 ; line 19 : 424 424 ; line 20 : // ******************************************************** 425 425 ; line 21 : u8 vreg_ctr[VREG_C_ENDMARK_]; 426 426 ; line 22 : 427 427 ; line 23 : bit irq_readed; // AAA型のため。 428 428 ; line 24 : 429 429 ; line 25 : extern bit update; 430 430 ; line 26 : extern u16 pool[]; 431 431 ; line 27 : 432 432 ; line 28 : 433 433 ; line 29 : // ******************************************************** 434 434 ; line 30 : extern task_status_immed tski_firm_update(); 435 435 ; line 31 : extern task_status_immed tski_mcu_info_read(); 436 436 ; line 32 : 437 437 ; line 33 : // ******************************************************** 438 438 ; line 34 : #ifdef _MCU_BSR_ 439 439 ; line 35 : #define IICAMK IICAMK1 440 440 ; line 36 : #endif 441 441 ; line 37 : 442 442 ; line 38 : 443 443 ; line 39 : // ******************************************************** 444 444 ; line 40 : // 非ゼロの初期値の指定が必要なアドレス 445 445 ; line 41 : void vreg_ctr_init( ) 446 446 ; line 42 : { 447 447 448 448 ----- ROM_CODE CSEG BASE 449 449 0003E _vreg_ctr_init: 450 450 $DGL 1,39 451 451 0003E ??bf_vreg_ctr_init: 452 452 ; line 43 : vreg_ctr[VREG_C_LED_BRIGHT] = 0xFF; 453 453 $DGL 0,2 454 454 0003E RCF2800FF mov !_vreg_ctr+40,#0FFH ; 255 ;[INF] 4, 1 455 455 ; line 44 : 456 456 ; line 45 : #ifdef _PMIC_TWL_ 457 457 ; line 46 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR; 458 458 ; line 47 : #else 459 459 ; line 48 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR | 0x10; 460 460 $DGL 0,7 461 461 00042 RCF000010 mov !_vreg_ctr,#010H ; 16 ;[INF] 4, 1 462 462 ; line 49 : #endif 463 463 ; line 50 : vreg_ctr[VREG_C_MCU_VER_MINOR] = MCU_VER_MINOR; 464 464 $DGL 0,9 465 465 00046 RCF010010 mov !_vreg_ctr+1,#010H ; 16 ;[INF] 4, 1 466 466 ; line 51 : 467 467 ; line 52 : vreg_ctr[VREG_C_VCOM_T] = VCOM_DEFAULT_T; 468 468 $DGL 0,11 469 469 0004A RCF03005C mov !_vreg_ctr+3,#05CH ; 92 ;[INF] 4, 1 470 470 ; line 53 : vreg_ctr[VREG_C_VCOM_B] = VCOM_DEFAULT_B; 471 471 $DGL 0,12 472 472 0004E RCF04005F mov !_vreg_ctr+4,#05FH ; 95 ;[INF] 4, 1 473 473 ; line 54 : } 474 474 $DGL 0,13 475 475 00052 ??ef_vreg_ctr_init: 476 476 00052 D7 ret ;[INF] 1, 6 477 477 00053 ??ee_vreg_ctr_init: 478 478 ; line 55 : 479 479 ; line 56 : 480 480 ; line 57 : 481 481 ; line 58 : 482 482 ; line 59 : // ******************************************************** 483 483 ; line 60 : // I2C仮想レジスタに書きます。 484 484 ; line 61 : //　引数 adrs は内部アドレス 485 485 ; line 62 : // 　書けないアドレスにアクセスした場合、何もしません。 486 486 ; line 63 : // ●書き込んだ結果、I2C_mcu通信が発生する場合、renge_task_immed 487 487 ; _add() 488 488 ; line 64 : // を使用しないと、I2C_mcu使用中でエラー終了した場合にリトライし 489 489 ; ません。 490 490 ; line 65 : void vreg_ctr_write( u8 adrs, u8 data ) 491 491 ; line 66 : { 492 492 00053 _vreg_ctr_write: 493 493 $DGL 1,45 494 494 00053 C7 push hl ;[INF] 1, 1 495 495 00054 8806 mov a,[sp+6] ;[INF] 2, 1 496 496 00056 16 movw hl,ax ;[INF] 1, 1 497 497 00057 ??bf_vreg_ctr_write: 498 498 ; line 67 : if( adrs >= VREG_C_ENDMARK_ ) 499 499 $DGL 0,2 500 500 00057 66 mov a,l ;[INF] 1, 1 501 501 00058 4C60 cmp a,#060H ; 96 ;[INF] 2, 1 502 502 0005A 61C8 skc ;[INF] 2, 1 503 503 0005C REDE502 br !?L0067 ;[INF] 3, 3 504 504 ; line 68 : return; 505 505 ; line 69 : 506 506 ; line 70 : switch ( adrs ) 507 507 $DGL 0,5 508 508 0005F 17 movw ax,hl ;[INF] 1, 1 509 509 00060 F1 clrb a ;[INF] 1, 1 510 510 00061 E7 onew bc ;[INF] 1, 1 511 511 00062 340200 movw de,#02H ; 2 ;[INF] 3, 1 512 512 00065 25 subw ax,de ;[INF] 1, 1 513 513 00066 61F8 sknz ;[INF] 2, 1 514 514 00068 RED4001 br !?L0008 ;[INF] 3, 3 515 515 0006B B1 decw ax ;[INF] 1, 1 516 516 0006C 23 subw ax,bc ;[INF] 1, 1 517 517 0006D 61E3 skh ;[INF] 2, 1 518 518 0006F RED4D01 br !?L0009 ;[INF] 3, 3 519 519 00072 B1 decw ax ;[INF] 1, 1 520 520 00073 23 subw ax,bc ;[INF] 1, 1 521 521 00074 61E3 skh ;[INF] 2, 1 522 522 00076 RED5901 br !?L0010 ;[INF] 3, 3 523 523 00079 23 subw ax,bc ;[INF] 1, 1 524 524 0007A 61F8 sknz ;[INF] 2, 1 525 525 0007C RED5F01 br !?L0011 ;[INF] 3, 3 526 526 0007F 241100 subw ax,#011H ; 17 ;[INF] 3, 1 527 527 00082 240500 subw ax,#05H ; 5 ;[INF] 3, 1 528 528 00085 61D8 sknc ;[INF] 2, 1 529 529 00087 RED7E01 br !?L0012 ;[INF] 3, 3 530 530 0008A 240300 subw ax,#03H ; 3 ;[INF] 3, 1 531 531 0008D 61F8 sknz ;[INF] 2, 1 532 532 0008F RED8401 br !?L0013 ;[INF] 3, 3 533 533 00092 23 subw ax,bc ;[INF] 1, 1 534 534 00093 61F8 sknz ;[INF] 2, 1 535 535 00095 REDCA01 br !?L0015 ;[INF] 3, 3 536 536 00098 23 subw ax,bc ;[INF] 1, 1 537 537 00099 61F8 sknz ;[INF] 2, 1 538 538 0009B RED9B01 br !?L0014 ;[INF] 3, 3 539 539 0009E 23 subw ax,bc ;[INF] 1, 1 540 540 0009F 61F8 sknz ;[INF] 2, 1 541 541 000A1 REDD302 br !?L0038 ;[INF] 3, 3 542 542 000A4 B1 decw ax ;[INF] 1, 1 543 543 000A5 240400 subw ax,#04H ; 4 ;[INF] 3, 1 544 544 000A8 61D8 sknc ;[INF] 2, 1 545 545 000AA RED2802 br !?L0016 ;[INF] 3, 3 546 546 000AD 240000 subw ax,#00H ; 0 ;[INF] 3, 1 547 547 000B0 61F8 sknz ;[INF] 2, 1 548 548 000B2 RED3402 br !?L0018 ;[INF] 3, 3 549 549 000B5 B1 decw ax ;[INF] 1, 1 550 550 000B6 240500 subw ax,#05H ; 5 ;[INF] 3, 1 551 551 000B9 61D8 sknc ;[INF] 2, 1 552 552 000BB RED3A02 br !?L0019 ;[INF] 3, 3 553 553 000BE 25 subw ax,de ;[INF] 1, 1 554 554 000BF 23 subw ax,bc ;[INF] 1, 1 555 555 000C0 61E3 skh ;[INF] 2, 1 556 556 000C2 RED4302 br !?L0020 ;[INF] 3, 3 557 557 000C5 23 subw ax,bc ;[INF] 1, 1 558 558 000C6 61F8 sknz ;[INF] 2, 1 559 559 000C8 RED4C02 br !?L0021 ;[INF] 3, 3 560 560 000CB 23 subw ax,bc ;[INF] 1, 1 561 561 000CC 61F8 sknz ;[INF] 2, 1 562 562 000CE RED5302 br !?L0022 ;[INF] 3, 3 563 563 000D1 23 subw ax,bc ;[INF] 1, 1 564 564 000D2 61F8 sknz ;[INF] 2, 1 565 565 000D4 RED5C02 br !?L0023 ;[INF] 3, 3 566 566 000D7 23 subw ax,bc ;[INF] 1, 1 567 567 000D8 61F8 sknz ;[INF] 2, 1 568 568 000DA RED6302 br !?L0024 ;[INF] 3, 3 569 569 000DD 23 subw ax,bc ;[INF] 1, 1 570 570 000DE 61F8 sknz ;[INF] 2, 1 571 571 000E0 RED6B02 br !?L0025 ;[INF] 3, 3 572 572 000E3 23 subw ax,bc ;[INF] 1, 1 573 573 000E4 61F8 sknz ;[INF] 2, 1 574 574 000E6 RED7102 br !?L0026 ;[INF] 3, 3 575 575 000E9 23 subw ax,bc ;[INF] 1, 1 576 576 000EA 61F8 sknz ;[INF] 2, 1 577 577 000EC RED7802 br !?L0027 ;[INF] 3, 3 578 578 000EF 23 subw ax,bc ;[INF] 1, 1 579 579 000F0 61F8 sknz ;[INF] 2, 1 580 580 000F2 RED8302 br !?L0028 ;[INF] 3, 3 581 581 000F5 23 subw ax,bc ;[INF] 1, 1 582 582 000F6 61F8 sknz ;[INF] 2, 1 583 583 000F8 RED8B02 br !?L0029 ;[INF] 3, 3 584 584 000FB 23 subw ax,bc ;[INF] 1, 1 585 585 000FC 61F8 sknz ;[INF] 2, 1 586 586 000FE RED9002 br !?L0030 ;[INF] 3, 3 587 587 00101 23 subw ax,bc ;[INF] 1, 1 588 588 00102 61F8 sknz ;[INF] 2, 1 589 589 00104 RED9802 br !?L0031 ;[INF] 3, 3 590 590 00107 240400 subw ax,#04H ; 4 ;[INF] 3, 1 591 591 0010A 61F8 sknz ;[INF] 2, 1 592 592 0010C RED9D02 br !?L0032 ;[INF] 3, 3 593 593 0010F 23 subw ax,bc ;[INF] 1, 1 594 594 00110 61F8 sknz ;[INF] 2, 1 595 595 00112 REDA802 br !?L0033 ;[INF] 3, 3 596 596 00115 25 subw ax,de ;[INF] 1, 1 597 597 00116 61F8 sknz ;[INF] 2, 1 598 598 00118 REDB302 br !?L0034 ;[INF] 3, 3 599 599 0011B 23 subw ax,bc ;[INF] 1, 1 600 600 0011C 61F8 sknz ;[INF] 2, 1 601 601 0011E REDB802 br !?L0035 ;[INF] 3, 3 602 602 00121 240700 subw ax,#07H ; 7 ;[INF] 3, 1 603 603 00124 240300 subw ax,#03H ; 3 ;[INF] 3, 1 604 604 00127 61D8 sknc ;[INF] 2, 1 605 605 00129 REDC302 br !?L0036 ;[INF] 3, 3 606 606 0012C 240000 subw ax,#00H ; 0 ;[INF] 3, 1 607 607 0012F 61F8 sknz ;[INF] 2, 1 608 608 00131 REDC802 br !?L0037 ;[INF] 3, 3 609 609 00134 25 subw ax,de ;[INF] 1, 1 610 610 00135 241000 subw ax,#010H ; 16 ;[INF] 3, 1 611 611 00138 61D8 sknc ;[INF] 2, 1 612 612 0013A RED2E02 br !?L0017 ;[INF] 3, 3 613 613 0013D REDE502 br !?L0067 ;[INF] 3, 3 614 614 ; line 71 : { 615 615 00140 ??bb00_vreg_ctr_write: 616 616 ; line 72 : 617 617 ; line 73 : case ( VREG_C_MCU_STATUS ): 618 618 00140 ?L0008: 619 619 ; line 74 : vreg_ctr[adrs] = data; 620 620 $DGL 0,9 621 621 00140 RFD0000 call !bs_S0105 ;[INF] 3, 3 622 622 ; line 75 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( ( data & 0xC0 ) >> 623 623 ; 6 ); 624 624 $DGL 0,10 625 625 00143 5CC0 and a,#0C0H ; 192 ;[INF] 2, 1 626 626 00145 316A shr a,6 ;[INF] 2, 1 627 627 00147 R9F0300 mov !_vreg_twl+3,a ;[INF] 3, 1 628 628 ; line 76 : break; 629 629 $DGL 0,11 630 630 0014A REDE502 br !?L0067 ;[INF] 3, 3 631 631 ; line 77 : 632 632 ; line 78 : case ( VREG_C_VCOM_T ): 633 633 0014D ?L0009: 634 634 ; line 79 : case ( VREG_C_VCOM_B ): 635 635 ; line 80 : renge_task_immed_add( tski_vcom_set ); 636 636 $DGL 0,15 637 637 0014D R300000 movw ax,#loww (_tski_vcom_set) ;[INF] 3, 1 638 638 00150 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 639 639 ; line 81 : vreg_ctr[adrs] = data; 640 640 $DGL 0,16 641 641 00153 RFD0000 call !bs_S0105 ;[INF] 3, 3 642 642 ; line 82 : break; 643 643 $DGL 0,17 644 644 00156 REDE502 br !?L0067 ;[INF] 3, 3 645 645 ; line 83 : 646 646 ; line 84 : case ( VREG_C_DBG1 ): 647 647 00159 ?L0010: 648 648 ; line 85 : case ( VREG_C_DBG2 ): 649 649 ; line 86 : vreg_ctr[adrs] = data; 650 650 $DGL 0,21 651 651 00159 RFD0000 call !bs_S0105 ;[INF] 3, 3 652 652 ; line 87 : break; 653 653 $DGL 0,22 654 654 0015C REDE502 br !?L0067 ;[INF] 3, 3 655 655 ; line 88 : case ( VREG_C_DBG3 ): 656 656 0015F ?L0011: 657 657 ; line 89 : vreg_ctr[adrs] = data; 658 658 $DGL 0,24 659 659 0015F RFD0000 call !bs_S0105 ;[INF] 3, 3 660 660 ; line 90 : if( ( vreg_ctr[VREG_C_DBG1] == 'j' ) 661 661 ; line 91 : && ( vreg_ctr[VREG_C_DBG2] == 'h' ) 662 662 ; line 92 : && ( data == 'l' ) ) 663 663 $DGL 0,27 664 664 00162 R4005006A cmp !_vreg_ctr+5,#06AH ; 106 ;[INF] 4, 1 665 665 00166 DF13 bnz $?L0041 ;[INF] 2, 4 666 666 00168 R40060068 cmp !_vreg_ctr+6,#068H ; 104 ;[INF] 4, 1 667 667 0016C DF0D bnz $?L0041 ;[INF] 2, 4 668 668 0016E 4C6C cmp a,#06CH ; 108 ;[INF] 2, 1 669 669 00170 DF09 bnz $?L0041 ;[INF] 2, 4 670 670 ; line 93 : { 671 671 00172 ??bb01_vreg_ctr_write: 672 672 ; line 94 : renge_task_immed_add( tski_firm_update ); 673 673 $DGL 0,29 674 674 00172 R300000 movw ax,#loww (_tski_firm_update) ;[INF] 3, 1 675 675 00175 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 676 676 ; line 95 : IICAMK = 1; 677 677 $DGL 0,30 678 678 00178 713AD5 set1 MK2H.3 ;[INF] 3, 2 679 679 0017B ??eb01_vreg_ctr_write: 680 680 ; line 96 : } 681 681 0017B ?L0041: 682 682 ; line 97 : break; 683 683 $DGL 0,32 684 684 0017B REDE502 br !?L0067 ;[INF] 3, 3 685 685 ; line 98 : 686 686 ; line 99 : case ( VREG_C_IRQ_MASK0 ): 687 687 0017E ?L0012: 688 688 ; line 100 : case ( VREG_C_IRQ_MASK1 ): 689 689 ; line 101 : case ( VREG_C_IRQ_MASK2 ): 690 690 ; line 102 : case ( VREG_C_IRQ_MASK3 ): 691 691 ; line 103 : case ( VREG_C_IRQ_MASK4 ): 692 692 ; line 104 : vreg_ctr[adrs] = data; 693 693 $DGL 0,39 694 694 0017E RFD0000 call !bs_S0105 ;[INF] 3, 3 695 695 ; line 105 : break; 696 696 $DGL 0,40 697 697 00181 REDE502 br !?L0067 ;[INF] 3, 3 698 698 ; line 106 : 699 699 ; line 107 : case ( VREG_C_COMMAND0 ): 700 700 00184 ?L0013: 701 701 ; line 108 : vreg_ctr[adrs] |= data; 702 702 $DGL 0,43 703 703 00184 17 movw ax,hl ;[INF] 1, 1 704 704 00185 F1 clrb a ;[INF] 1, 1 705 705 00186 R040000 addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 706 706 00189 14 movw de,ax ;[INF] 1, 1 707 707 0018A 89 mov a,[de] ;[INF] 1, 1 708 708 0018B 616F or a,h ;[INF] 2, 1 709 709 0018D 99 mov [de],a ;[INF] 1, 1 710 710 ; line 109 : if( data != 0 ) 711 711 $DGL 0,44 712 712 0018E 67 mov a,h ;[INF] 1, 1 713 713 0018F D1 cmp0 a ;[INF] 1, 1 714 714 00190 DD06 bz $?L0043 ;[INF] 2, 4 715 715 ; line 110 : { 716 716 00192 ??bb02_vreg_ctr_write: 717 717 ; line 111 : renge_task_immed_add( do_command0 ); 718 718 $DGL 0,46 719 719 00192 R300000 movw ax,#loww (_do_command0) ;[INF] 3, 1 720 720 00195 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 721 721 00198 ??eb02_vreg_ctr_write: 722 722 ; line 112 : } 723 723 00198 ?L0043: 724 724 ; line 113 : break; 725 725 $DGL 0,48 726 726 00198 REDE502 br !?L0067 ;[INF] 3, 3 727 727 ; line 114 : 728 728 ; line 115 : case ( VREG_C_COMMAND2 ): 729 729 0019B ?L0014: 730 730 ; line 116 : // こちらからの完了割り込みを待ってくれないそうです。 #- 731 731 ; ω-) 何のための割り込みだ 732 732 ; line 117 : // 液晶電源 733 733 ; line 118 : if(( data & REG_BIT_CMD_LCD_ON ) != 0 ) 734 734 $DGL 0,53 735 735 0019B 67 mov a,h ;[INF] 1, 1 736 736 0019C 5C02 and a,#02H ; 2 ;[INF] 2, 1 737 737 0019E D1 cmp0 a ;[INF] 1, 1 738 738 0019F DD08 bz $?L0045 ;[INF] 2, 4 739 739 ; line 119 : { 740 740 001A1 ??bb03_vreg_ctr_write: 741 741 ; line 120 : renge_task_immed_add( tski_PM_LCD_on ); 742 742 $DGL 0,55 743 743 001A1 R300000 movw ax,#loww (_tski_PM_LCD_on) ;[INF] 3, 1 744 744 001A4 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 745 745 001A7 ??eb03_vreg_ctr_write: 746 746 ; line 121 : } 747 747 $DGL 0,56 748 748 001A7 EF0C br $?L0047 ;[INF] 2, 3 749 749 001A9 ?L0045: 750 750 ; line 122 : else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 ) 751 751 $DGL 0,57 752 752 001A9 67 mov a,h ;[INF] 1, 1 753 753 001AA 5C01 and a,#01H ; 1 ;[INF] 2, 1 754 754 001AC D1 cmp0 a ;[INF] 1, 1 755 755 001AD DD06 bz $?L0047 ;[INF] 2, 4 756 756 ; line 123 : { 757 757 001AF ??bb04_vreg_ctr_write: 758 758 ; line 124 : renge_task_immed_add( tski_PM_LCD_off ); 759 759 $DGL 0,59 760 760 001AF R300000 movw ax,#loww (_tski_PM_LCD_off) ;[INF] 3, 1 761 761 001B2 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 762 762 001B5 ??eb04_vreg_ctr_write: 763 763 ; line 125 : } 764 764 001B5 ?L0047: 765 765 ; line 126 : 766 766 ; line 127 : // バックライト設定 767 767 ; line 128 : /// 今のところさらに細かくは分けないけど… 768 768 ; line 129 : if(( data & REG_BITS_CMD_BL ) != 0 ) 769 769 $DGL 0,64 770 770 001B5 67 mov a,h ;[INF] 1, 1 771 771 001B6 5C3C and a,#03CH ; 60 ;[INF] 2, 1 772 772 001B8 D1 cmp0 a ;[INF] 1, 1 773 773 001B9 DD0C bz $?L0049 ;[INF] 2, 4 774 774 ; line 130 : { 775 775 001BB ??bb05_vreg_ctr_write: 776 776 ; line 131 : vreg_ctr[adrs] = ( data & REG_BITS_CMD_BL ); 777 777 $DGL 0,66 778 778 001BB 67 mov a,h ;[INF] 1, 1 779 779 001BC 5C3C and a,#03CH ; 60 ;[INF] 2, 1 780 780 001BE RFD0F00 call !bs_S0104 ;[INF] 3, 3 781 781 ; line 132 : renge_task_immed_add( tski_PM_BL_set ); 782 782 $DGL 0,67 783 783 001C1 R300000 movw ax,#loww (_tski_PM_BL_set) ;[INF] 3, 1 784 784 001C4 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 785 785 001C7 ??eb05_vreg_ctr_write: 786 786 ; line 133 : } 787 787 001C7 ?L0049: 788 788 ; line 134 : break; 789 789 $DGL 0,69 790 790 001C7 REDE502 br !?L0067 ;[INF] 3, 3 791 791 ; line 135 : 792 792 ; line 136 : case ( VREG_C_COMMAND1 ): 793 793 001CA ?L0015: 794 794 ; line 137 : if( data != 0 ) 795 795 $DGL 0,72 796 796 001CA 67 mov a,h ;[INF] 1, 1 797 797 001CB D1 cmp0 a ;[INF] 1, 1 798 798 001CC DD57 bz $?L0051 ;[INF] 2, 4 799 799 ; line 138 : { 800 800 001CE ??bb06_vreg_ctr_write: 801 801 ; line 139 : // TWLに割り込みを入れる 802 802 ; line 140 : /// 実際に割り込みを入れるのはSoC 803 803 ; line 141 : vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT 804 804 ; _SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; 805 805 ; //pwsw_det 806 806 $DGL 0,76 807 807 001CE 5C01 and a,#01H ; 1 ;[INF] 2, 1 808 808 001D0 D1 cmp0 a ;[INF] 1, 1 809 809 001D1 DD05 bz $?L0053 ;[INF] 2, 4 810 810 001D3 300800 movw ax,#08H ; 8 ;[INF] 3, 1 811 811 001D6 EF01 br $?L0054 ;[INF] 2, 3 812 812 001D8 ?L0053: 813 813 001D8 F6 clrw ax ;[INF] 1, 1 814 814 001D9 ?L0054: 815 815 001D9 60 mov a,x ;[INF] 1, 1 816 816 001DA R9F0100 mov !_vreg_twl+1,a ;[INF] 3, 1 817 817 ; line 142 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT 818 818 ; _SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; 819 819 ; //reset_req 820 820 $DGL 0,77 821 821 001DD 67 mov a,h ;[INF] 1, 1 822 822 001DE 5C02 and a,#02H ; 2 ;[INF] 2, 1 823 823 001E0 D1 cmp0 a ;[INF] 1, 1 824 824 001E1 DD03 bz $?L0055 ;[INF] 2, 4 825 825 001E3 E6 onew ax ;[INF] 1, 1 826 826 001E4 EF01 br $?L0056 ;[INF] 2, 3 827 827 001E6 ?L0055: 828 828 001E6 F6 clrw ax ;[INF] 1, 1 829 829 001E7 ?L0056: 830 830 001E7 RFD0700 call !bs_S0106 ;[INF] 3, 3 831 831 ; line 143 : 832 832 ; line 144 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT 833 833 ; _SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //of 834 834 ; f_req 835 835 $DGL 0,79 836 836 001EA 67 mov a,h ;[INF] 1, 1 837 837 001EB 5C04 and a,#04H ; 4 ;[INF] 2, 1 838 838 001ED D1 cmp0 a ;[INF] 1, 1 839 839 001EE DD04 bz $?L0057 ;[INF] 2, 4 840 840 001F0 E6 onew ax ;[INF] 1, 1 841 841 001F1 A1 incw ax ;[INF] 1, 1 842 842 001F2 EF01 br $?L0058 ;[INF] 2, 3 843 843 001F4 ?L0057: 844 844 001F4 F6 clrw ax ;[INF] 1, 1 845 845 001F5 ?L0058: 846 846 001F5 RFD0700 call !bs_S0106 ;[INF] 3, 3 847 847 ; line 145 : 848 848 ; line 146 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT 849 849 ; _SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; 850 850 ; //batt_low 851 851 $DGL 0,81 852 852 001F8 67 mov a,h ;[INF] 1, 1 853 853 001F9 5C08 and a,#08H ; 8 ;[INF] 2, 1 854 854 001FB D1 cmp0 a ;[INF] 1, 1 855 855 001FC DD05 bz $?L0059 ;[INF] 2, 4 856 856 001FE 302000 movw ax,#020H ; 32 ;[INF] 3, 1 857 857 00201 EF01 br $?L0060 ;[INF] 2, 3 858 858 00203 ?L0059: 859 859 00203 F6 clrw ax ;[INF] 1, 1 860 860 00204 ?L0060: 861 861 00204 RFD0700 call !bs_S0106 ;[INF] 3, 3 862 862 ; line 147 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT 863 863 ; _SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; 864 864 ; //batt_empty 865 865 $DGL 0,82 866 866 00207 67 mov a,h ;[INF] 1, 1 867 867 00208 5C10 and a,#010H ; 16 ;[INF] 2, 1 868 868 0020A D1 cmp0 a ;[INF] 1, 1 869 869 0020B DD05 bz $?L0061 ;[INF] 2, 4 870 870 0020D 301000 movw ax,#010H ; 16 ;[INF] 3, 1 871 871 00210 EF01 br $?L0062 ;[INF] 2, 3 872 872 00212 ?L0061: 873 873 00212 F6 clrw ax ;[INF] 1, 1 874 874 00213 ?L0062: 875 875 00213 RFD0700 call !bs_S0106 ;[INF] 3, 3 876 876 ; line 148 : 877 877 ; line 149 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT 878 878 ; _SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00 879 879 ; ; //vol_changed 880 880 $DGL 0,84 881 881 00216 67 mov a,h ;[INF] 1, 1 882 882 00217 5C20 and a,#020H ; 32 ;[INF] 2, 1 883 883 00219 D1 cmp0 a ;[INF] 1, 1 884 884 0021A DD05 bz $?L0063 ;[INF] 2, 4 885 885 0021C 304000 movw ax,#040H ; 64 ;[INF] 3, 1 886 886 0021F EF01 br $?L0064 ;[INF] 2, 3 887 887 00221 ?L0063: 888 888 00221 F6 clrw ax ;[INF] 1, 1 889 889 00222 ?L0064: 890 890 00222 RFD0700 call !bs_S0106 ;[INF] 3, 3 891 891 00225 ??eb06_vreg_ctr_write: 892 892 ; line 150 : } 893 893 00225 ?L0051: 894 894 ; line 151 : break; 895 895 $DGL 0,86 896 896 00225 REDE502 br !?L0067 ;[INF] 3, 3 897 897 ; line 152 : 898 898 ; line 153 : case ( VREG_C_DBG20 ): 899 899 00228 ?L0016: 900 900 ; line 154 : case ( VREG_C_DBG21 ): 901 901 ; line 155 : case ( VREG_C_DBG22 ): 902 902 ; line 156 : case ( VREG_C_DBG23 ): 903 903 ; line 157 : vreg_ctr[adrs] = data; 904 904 $DGL 0,92 905 905 00228 RFD0000 call !bs_S0105 ;[INF] 3, 3 906 906 ; line 158 : break; 907 907 $DGL 0,93 908 908 0022B REDE502 br !?L0067 ;[INF] 3, 3 909 909 ; line 159 : 910 910 ; line 160 : case ( VREG_C_FREE_0 ): 911 911 0022E ?L0017: 912 912 ; line 161 : case ( VREG_C_FREE_1 ): 913 913 ; line 162 : case ( VREG_C_FREE_2 ): 914 914 ; line 163 : case ( VREG_C_FREE_3 ): 915 915 ; line 164 : case ( VREG_C_FREE_4 ): 916 916 ; line 165 : case ( VREG_C_FREE_5 ): 917 917 ; line 166 : case ( VREG_C_FREE_6 ): 918 918 ; line 167 : case ( VREG_C_FREE_7 ): 919 919 ; line 168 : case ( VREG_C_FREE_8 ): 920 920 ; line 169 : case ( VREG_C_FREE_9 ): 921 921 ; line 170 : case ( VREG_C_FREE_A ): 922 922 ; line 171 : case ( VREG_C_FREE_B ): 923 923 ; line 172 : case ( VREG_C_FREE_C ): 924 924 ; line 173 : case ( VREG_C_FREE_D ): 925 925 ; line 174 : case ( VREG_C_FREE_E ): 926 926 ; line 175 : case ( VREG_C_FREE_F ): 927 927 ; line 176 : vreg_ctr[adrs] = data; 928 928 $DGL 0,111 929 929 0022E RFD0000 call !bs_S0105 ;[INF] 3, 3 930 930 ; line 177 : break; 931 931 $DGL 0,112 932 932 00231 REDE502 br !?L0067 ;[INF] 3, 3 933 933 ; line 178 : 934 934 ; line 179 : case ( VREG_C_LED_BRIGHT ): 935 935 00234 ?L0018: 936 936 ; line 180 : vreg_ctr[adrs] = data; 937 937 $DGL 0,115 938 938 00234 RFD0000 call !bs_S0105 ;[INF] 3, 3 939 939 ; line 181 : break; 940 940 $DGL 0,116 941 941 00237 REDE502 br !?L0067 ;[INF] 3, 3 942 942 ; line 182 : 943 943 ; line 183 : case ( VREG_C_LED_POW ): 944 944 0023A ?L0019: 945 945 ; line 184 : case ( VREG_C_LED_WIFI ): 946 946 ; line 185 : case ( VREG_C_LED_CAM ): 947 947 ; line 186 : case ( VREG_C_LED_TUNE ): 948 948 ; line 187 : case ( VREG_C_LED_NOTIFY ): 949 949 ; line 188 : vreg_ctr[adrs] = data & 0x0F; 950 950 $DGL 0,123 951 951 0023A 67 mov a,h ;[INF] 1, 1 952 952 0023B 5C0F and a,#0FH ; 15 ;[INF] 2, 1 953 953 0023D RFD0F00 call !bs_S0104 ;[INF] 3, 3 954 954 ; line 189 : break; 955 955 $DGL 0,124 956 956 00240 REDE502 br !?L0067 ;[INF] 3, 3 957 957 ; line 190 : 958 958 ; line 191 : /// 非同期で動いているためここでは書かない。 959 959 ; line 192 : // 予約するだけでstopで書く 960 960 ; line 193 : case ( VREG_C_RTC_SEC ): 961 961 00243 ?L0020: 962 962 ; line 194 : case ( VREG_C_RTC_MIN ): 963 963 ; line 195 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F ); 964 964 $DGL 0,130 965 965 00243 67 mov a,h ;[INF] 1, 1 966 966 00244 5C7F and a,#07FH ; 127 ;[INF] 2, 1 967 967 00246 RFD1700 call !bs_F0102 ;[INF] 3, 3 968 968 ; line 196 : break; 969 969 $DGL 0,131 970 970 00249 REDE502 br !?L0067 ;[INF] 3, 3 971 971 ; line 197 : 972 972 ; line 198 : case ( VREG_C_RTC_HOUR ): 973 973 0024C ?L0021: 974 974 ; line 199 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); 975 975 $DGL 0,134 976 976 0024C 67 mov a,h ;[INF] 1, 1 977 977 0024D RFD2F00 call !bs_F0101 ;[INF] 3, 3 978 978 ; line 200 : break; 979 979 $DGL 0,135 980 980 00250 REDE502 br !?L0067 ;[INF] 3, 3 981 981 ; line 201 : 982 982 ; line 202 : case ( VREG_C_RTC_YOBI ): 983 983 00253 ?L0022: 984 984 ; line 203 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 ); 985 985 $DGL 0,138 986 986 00253 67 mov a,h ;[INF] 1, 1 987 987 00254 5C07 and a,#07H ; 7 ;[INF] 2, 1 988 988 00256 RFD1700 call !bs_F0102 ;[INF] 3, 3 989 989 ; line 204 : break; 990 990 $DGL 0,139 991 991 00259 REDE502 br !?L0067 ;[INF] 3, 3 992 992 ; line 205 : 993 993 ; line 206 : case ( VREG_C_RTC_DAY ): 994 994 0025C ?L0023: 995 995 ; line 207 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); 996 996 $DGL 0,142 997 997 0025C 67 mov a,h ;[INF] 1, 1 998 998 0025D RFD2F00 call !bs_F0101 ;[INF] 3, 3 999 999 ; line 208 : break; 1000 1000 $DGL 0,143 1001 1001 00260 REDE502 br !?L0067 ;[INF] 3, 3 1002 1002 ; line 209 : 1003 1003 ; line 210 : case ( VREG_C_RTC_MONTH ): 1004 1004 00263 ?L0024: 1005 1005 ; line 211 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F ); 1006 1006 $DGL 0,146 1007 1007 00263 67 mov a,h ;[INF] 1, 1 1008 1008 00264 5C1F and a,#01FH ; 31 ;[INF] 2, 1 1009 1009 00266 RFD1700 call !bs_F0102 ;[INF] 3, 3 1010 1010 ; line 212 : break; 1011 1011 $DGL 0,147 1012 1012 00269 EF7A br $?L0067 ;[INF] 2, 3 1013 1013 ; line 213 : 1014 1014 ; line 214 : case ( VREG_C_RTC_YEAR ): 1015 1015 0026B ?L0025: 1016 1016 ; line 215 : set_rtc( adrs - VREG_C_RTC_SEC, data ); 1017 1017 $DGL 0,150 1018 1018 0026B 67 mov a,h ;[INF] 1, 1 1019 1019 0026C RFD1700 call !bs_F0102 ;[INF] 3, 3 1020 1020 ; line 216 : break; 1021 1021 $DGL 0,151 1022 1022 0026F EF74 br $?L0067 ;[INF] 2, 3 1023 1023 ; line 217 : 1024 1024 ; line 218 : case ( VREG_C_RTC_COMP ): 1025 1025 00271 ?L0026: 1026 1026 ; line 219 : vreg_ctr[adrs] = data; 1027 1027 $DGL 0,154 1028 1028 00271 RFD0000 call !bs_S0105 ;[INF] 3, 3 1029 1029 ; line 220 : SUBCUD = data; 1030 1030 $DGL 0,155 1031 1031 00274 9E99 mov SUBCUD,a ;[INF] 2, 1 1032 1032 ; line 221 : break; 1033 1033 $DGL 0,156 1034 1034 00276 EF6D br $?L0067 ;[INF] 2, 3 1035 1035 ; line 222 : 1036 1036 ; line 223 : case ( VREG_C_RTC_ALARM_MIN ): 1037 1037 00278 ?L0027: 1038 1038 ; line 224 : vreg_ctr[adrs] = ( data & 0x7F ); 1039 1039 $DGL 0,159 1040 1040 00278 67 mov a,h ;[INF] 1, 1 1041 1041 00279 5C7F and a,#07FH ; 127 ;[INF] 2, 1 1042 1042 0027B RFD0F00 call !bs_S0104 ;[INF] 3, 3 1043 1043 ; line 225 : rtc_alarm_dirty = 1; 1044 1044 $DGL 0,160 1045 1045 0027E R710200 set1 _rtc_alarm_dirty ;[INF] 3, 2 1046 1046 ; line 226 : break; 1047 1047 $DGL 0,161 1048 1048 00281 EF62 br $?L0067 ;[INF] 2, 3 1049 1049 ; line 227 : 1050 1050 ; line 228 : case ( VREG_C_RTC_ALARM_HOUR ): 1051 1051 00283 ?L0028: 1052 1052 ; line 229 : vreg_ctr[adrs] = ( data & 0x3F ); 1053 1053 $DGL 0,164 1054 1054 00283 RFD2400 call !bs_S0103 ;[INF] 3, 3 1055 1055 ; line 230 : rtc_alarm_dirty = 1; 1056 1056 $DGL 0,165 1057 1057 00286 R710200 set1 _rtc_alarm_dirty ;[INF] 3, 2 1058 1058 ; line 231 : break; 1059 1059 $DGL 0,166 1060 1060 00289 EF5A br $?L0067 ;[INF] 2, 3 1061 1061 ; line 232 : 1062 1062 ; line 233 : // 書くだけでよい 1063 1063 ; line 234 : case ( VREG_C_RTC_ALARM_DAY ): 1064 1064 0028B ?L0029: 1065 1065 ; line 235 : vreg_ctr[adrs] = ( data & 0x3F ); 1066 1066 $DGL 0,170 1067 1067 0028B RFD2400 call !bs_S0103 ;[INF] 3, 3 1068 1068 ; line 236 : break; 1069 1069 $DGL 0,171 1070 1070 0028E EF55 br $?L0067 ;[INF] 2, 3 1071 1071 ; line 237 : 1072 1072 ; line 238 : case ( VREG_C_RTC_ALARM_MONTH ): 1073 1073 00290 ?L0030: 1074 1074 ; line 239 : vreg_ctr[adrs] = ( data & 0x1F ); 1075 1075 $DGL 0,174 1076 1076 00290 67 mov a,h ;[INF] 1, 1 1077 1077 00291 5C1F and a,#01FH ; 31 ;[INF] 2, 1 1078 1078 00293 RFD0F00 call !bs_S0104 ;[INF] 3, 3 1079 1079 ; line 240 : break; 1080 1080 $DGL 0,175 1081 1081 00296 EF4D br $?L0067 ;[INF] 2, 3 1082 1082 ; line 241 : 1083 1083 ; line 242 : case ( VREG_C_RTC_ALARM_YEAR ): 1084 1084 00298 ?L0031: 1085 1085 ; line 243 : vreg_ctr[adrs] = data; 1086 1086 $DGL 0,178 1087 1087 00298 RFD0000 call !bs_S0105 ;[INF] 3, 3 1088 1088 ; line 244 : break; 1089 1089 $DGL 0,179 1090 1090 0029B EF48 br $?L0067 ;[INF] 2, 3 1091 1091 ; line 245 : 1092 1092 ; line 246 : 1093 1093 ; line 247 : case ( VREG_C_ACC_CONFIG ): 1094 1094 0029D ?L0032: 1095 1095 ; line 248 : vreg_ctr[adrs] = data; 1096 1096 $DGL 0,183 1097 1097 0029D RFD0000 call !bs_S0105 ;[INF] 3, 3 1098 1098 ; line 249 : renge_task_immed_add( acc_hosu_set ); 1099 1099 $DGL 0,184 1100 1100 002A0 R300000 movw ax,#loww (_acc_hosu_set) ;[INF] 3, 1 1101 1101 002A3 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 1102 1102 ; line 250 : break; 1103 1103 $DGL 0,185 1104 1104 002A6 EF3D br $?L0067 ;[INF] 2, 3 1105 1105 ; line 251 : 1106 1106 ; line 252 : case ( VREG_C_ACC_R_ADRS ): 1107 1107 002A8 ?L0033: 1108 1108 ; line 253 : vreg_ctr[adrs] = data; 1109 1109 $DGL 0,188 1110 1110 002A8 RFD0000 call !bs_S0105 ;[INF] 3, 3 1111 1111 ; line 254 : renge_task_immed_add( acc_read ); 1112 1112 $DGL 0,189 1113 1113 002AB R300000 movw ax,#loww (_acc_read) ;[INF] 3, 1 1114 1114 002AE RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 1115 1115 ; line 255 : break; 1116 1116 $DGL 0,190 1117 1117 002B1 EF32 br $?L0067 ;[INF] 2, 3 1118 1118 ; line 256 : 1119 1119 ; line 257 : case ( VREG_C_ACC_W_ADRS ): 1120 1120 002B3 ?L0034: 1121 1121 ; line 258 : vreg_ctr[adrs] = data; 1122 1122 $DGL 0,193 1123 1123 002B3 RFD0000 call !bs_S0105 ;[INF] 3, 3 1124 1124 ; line 259 : break; 1125 1125 $DGL 0,194 1126 1126 002B6 EF2D br $?L0067 ;[INF] 2, 3 1127 1127 ; line 260 : 1128 1128 ; line 261 : case ( VREG_C_ACC_W_BUF ): 1129 1129 002B8 ?L0035: 1130 1130 ; line 262 : vreg_ctr[adrs] = data; 1131 1131 $DGL 0,197 1132 1132 002B8 RFD0000 call !bs_S0105 ;[INF] 3, 3 1133 1133 ; line 263 : renge_task_immed_add( acc_write ); 1134 1134 $DGL 0,198 1135 1135 002BB R300000 movw ax,#loww (_acc_write) ;[INF] 3, 1 1136 1136 002BE RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 1137 1137 ; line 264 : break; 1138 1138 $DGL 0,199 1139 1139 002C1 EF22 br $?L0067 ;[INF] 2, 3 1140 1140 ; line 265 : 1141 1141 ; line 266 : case ( VREG_C_ACC_HOSU_L ): 1142 1142 002C3 ?L0036: 1143 1143 ; line 267 : case ( VREG_C_ACC_HOSU_M ): 1144 1144 ; line 268 : case ( VREG_C_ACC_HOSU_H ): 1145 1145 ; line 269 : vreg_ctr[adrs] = data; 1146 1146 $DGL 0,204 1147 1147 002C3 RFD0000 call !bs_S0105 ;[INF] 3, 3 1148 1148 ; line 270 : break; 1149 1149 $DGL 0,205 1150 1150 002C6 EF1D br $?L0067 ;[INF] 2, 3 1151 1151 ; line 271 : 1152 1152 ; line 272 : case ( VREG_C_ACC_HOSU_SETTING ): 1153 1153 002C8 ?L0037: 1154 1154 ; line 273 : if( ( data & 0x01 ) != 0 ) 1155 1155 $DGL 0,208 1156 1156 002C8 67 mov a,h ;[INF] 1, 1 1157 1157 002C9 5C01 and a,#01H ; 1 ;[INF] 2, 1 1158 1158 002CB D1 cmp0 a ;[INF] 1, 1 1159 1159 002CC DD17 bz $?L0067 ;[INF] 2, 4 1160 1160 ; line 274 : { 1161 1161 002CE ??bb07_vreg_ctr_write: 1162 1162 ; line 275 : clear_hosu_hist(); // 履歴クリア 1163 1163 $DGL 0,210 1164 1164 002CE RFD0000 call !_clear_hosu_hist ;[INF] 3, 3 1165 1165 002D1 ??eb07_vreg_ctr_write: 1166 1166 ; line 276 : } 1167 1167 ; line 277 : break; 1168 1168 $DGL 0,212 1169 1169 002D1 EF12 br $?L0067 ;[INF] 2, 3 1170 1170 ; line 278 : 1171 1171 ; line 279 : case ( VREG_C_COMMAND3 ): 1172 1172 002D3 ?L0038: 1173 1173 ; line 280 : vreg_ctr[adrs] = data; 1174 1174 $DGL 0,215 1175 1175 002D3 RFD0000 call !bs_S0105 ;[INF] 3, 3 1176 1176 ; line 281 : switch ( data ) 1177 1177 $DGL 0,216 1178 1178 002D6 318E shrw ax,8 ;[INF] 2, 1 1179 1179 002D8 247200 subw ax,#072H ; 114 ;[INF] 3, 1 1180 1180 002DB DD05 bz $?L0068 ;[INF] 2, 4 1181 1181 002DD 240500 subw ax,#05H ; 5 ;[INF] 3, 1 1182 1182 002E0 61F8 sknz ;[INF] 2, 1 1183 1183 ; line 282 : { 1184 1184 002E2 ??bb08_vreg_ctr_write: 1185 1185 ; line 283 : case ( 'r' ): 1186 1186 002E2 ?L0068: 1187 1187 ; line 284 : // 割り込みルーチンからFSLライブラリを呼ぶのは禁止の 1188 1188 ; ため 1189 1189 ; line 285 : // renge_task_immed_add( tski_mcu_reset ); 1190 1190 ; line 286 : // break; 1191 1191 ; line 287 : 1192 1192 ; line 288 : case ( 'w' ): 1193 1193 ; line 289 : // WDTで再起動（テスト向け） 1194 1194 ; line 290 : WDTE = 0xAA; 1195 1195 $DGL 0,225 1196 1196 002E2 CEABAA mov WDTE,#0AAH ; 170 ;[INF] 3, 1 1197 1197 ; line 291 : break; 1198 1198 002E5 ??eb08_vreg_ctr_write: 1199 1199 ; line 292 : } 1200 1200 002E5 ?L0067: 1201 1201 002E5 ??eb00_vreg_ctr_write: 1202 1202 ; line 293 : } 1203 1203 ; line 294 : return; 1204 1204 ; line 295 : } 1205 1205 $DGL 0,230 1206 1206 002E5 ??ef_vreg_ctr_write: 1207 1207 002E5 C6 pop hl ;[INF] 1, 1 1208 1208 002E6 D7 ret ;[INF] 1, 6 1209 1209 002E7 ??ee_vreg_ctr_write: 1210 1210 ; line 296 : 1211 1211 ; line 297 : 1212 1212 ; line 298 : 1213 1213 ; line 299 : // ******************************************************** 1214 1214 ; line 300 : // I2C仮想レジスタから読みます。 1215 1215 ; line 301 : // 戻り： xx データ 1216 1216 ; line 302 : // 注意：次のアドレスの準備で呼ばれる ので、 1217 1217 ; line 303 : // リードされたらクリアなどは気をつける 1218 1218 ; line 304 : u8 vreg_ctr_read( u8 adrs ) 1219 1219 ; line 305 : { 1220 1220 002E7 _vreg_ctr_read: 1221 1221 $DGL 1,89 1222 1222 002E7 C7 push hl ;[INF] 1, 1 1223 1223 002E8 16 movw hl,ax ;[INF] 1, 1 1224 1224 002E9 ??bf_vreg_ctr_read: 1225 1225 ; line 306 : static u16 rsub_temp; 1226 1226 ; line 307 : 1227 1227 ; line 308 : // RTCは読み出し途中に繰り上がるのを避けるため 1228 1228 ; line 309 : if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR 1229 1229 ; ) ) 1230 1230 $DGL 0,5 1231 1231 002E9 66 mov a,l ;[INF] 1, 1 1232 1232 002EA 4C30 cmp a,#030H ; 48 ;[INF] 2, 1 1233 1233 002EC DC09 bc $?L0074 ;[INF] 2, 4 1234 1234 002EE 4C37 cmp a,#037H ; 55 ;[INF] 2, 1 1235 1235 002F0 DE05 bnc $?L0074 ;[INF] 2, 4 1236 1236 ; line 310 : { 1237 1237 002F2 ??bb00_vreg_ctr_read: 1238 1238 ; line 311 : rtc_buf_reflesh( ); 1239 1239 $DGL 0,7 1240 1240 002F2 RFD0000 call !_rtc_buf_reflesh ;[INF] 3, 3 1241 1241 002F5 ??eb00_vreg_ctr_read: 1242 1242 ; line 312 : } 1243 1243 $DGL 0,8 1244 1244 002F5 EF51 br $?L0084 ;[INF] 2, 3 1245 1245 002F7 ?L0074: 1246 1246 ; line 313 : else if( adrs == VREG_C_MCU_STATUS ) 1247 1247 $DGL 0,9 1248 1248 002F7 66 mov a,l ;[INF] 1, 1 1249 1249 002F8 4C02 cmp a,#02H ; 2 ;[INF] 2, 1 1250 1250 002FA DF11 bnz $?L0076 ;[INF] 2, 4 1251 1251 ; line 314 : { 1252 1252 002FC ??bb01_vreg_ctr_read: 1253 1253 ; line 315 : return( vreg_ctr[ VREG_C_MCU_STATUS ] | ( ( vreg_twl[ RE 1254 1254 ; G_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) ); 1255 1255 $DGL 0,11 1256 1256 002FC R8F0300 mov a,!_vreg_twl+3 ;[INF] 3, 1 1257 1257 002FF 5C03 and a,#03H ; 3 ;[INF] 2, 1 1258 1258 00301 318E shrw ax,8 ;[INF] 2, 1 1259 1259 00303 316D shlw ax,6 ;[INF] 2, 1 1260 1260 00305 08 xch a,x ;[INF] 1, 1 1261 1261 00306 R6F0200 or a,!_vreg_ctr+2 ;[INF] 3, 1 1262 1262 00309 08 xch a,x ;[INF] 1, 1 1263 1263 0030A 12 movw bc,ax ;[INF] 1, 1 1264 1264 0030B EF4D br $?L0072 ;[INF] 2, 3 1265 1265 0030D ??eb01_vreg_ctr_read: 1266 1266 ; line 316 : } 1267 1267 0030D ?L0076: 1268 1268 ; line 317 : else if( adrs == VREG_C_ACC_HOSU_HIST ) 1269 1269 $DGL 0,13 1270 1270 0030D 66 mov a,l ;[INF] 1, 1 1271 1271 0030E 4C4F cmp a,#04FH ; 79 ;[INF] 2, 1 1272 1272 00310 DF06 bnz $?L0078 ;[INF] 2, 4 1273 1273 ; line 318 : { 1274 1274 00312 ??bb02_vreg_ctr_read: 1275 1275 ; line 319 : return( hosu_read() ); 1276 1276 $DGL 0,15 1277 1277 00312 RFD0000 call !_hosu_read ;[INF] 3, 3 1278 1278 00315 F3 clrb b ;[INF] 1, 1 1279 1279 00316 EF42 br $?L0072 ;[INF] 2, 3 1280 1280 00318 ??eb02_vreg_ctr_read: 1281 1281 ; line 320 : } 1282 1282 00318 ?L0078: 1283 1283 ; line 321 : else if( adrs == VREG_C_RTC_SEC_FINE_L ) 1284 1284 $DGL 0,17 1285 1285 00318 66 mov a,l ;[INF] 1, 1 1286 1286 00319 4C3D cmp a,#03DH ; 61 ;[INF] 2, 1 1287 1287 0031B DF0C bnz $?L0080 ;[INF] 2, 4 1288 1288 ; line 322 : { 1289 1289 0031D ??bb03_vreg_ctr_read: 1290 1290 ; line 323 : rsub_temp = RSUBC; 1291 1291 $DGL 0,19 1292 1292 0031D AE90 movw ax,RSUBC ;[INF] 2, 1 1293 1293 0031F RBF6000 movw !?L0073,ax ; rsub_temp ;[INF] 3, 1 1294 1294 ; line 324 : return( (u8)( rsub_temp & 0xFF ) ); 1295 1295 $DGL 0,20 1296 1296 00322 RD96000 mov x,!?L0073 ; rsub_temp ;[INF] 3, 1 1297 1297 00325 F1 clrb a ;[INF] 1, 1 1298 1298 00326 12 movw bc,ax ;[INF] 1, 1 1299 1299 00327 EF31 br $?L0072 ;[INF] 2, 3 1300 1300 00329 ??eb03_vreg_ctr_read: 1301 1301 ; line 325 : } 1302 1302 00329 ?L0080: 1303 1303 ; line 326 : else if( adrs == VREG_C_RTC_SEC_FINE_H ) 1304 1304 $DGL 0,22 1305 1305 00329 66 mov a,l ;[INF] 1, 1 1306 1306 0032A 4C3E cmp a,#03EH ; 62 ;[INF] 2, 1 1307 1307 0032C DF07 bnz $?L0082 ;[INF] 2, 4 1308 1308 ; line 327 : { 1309 1309 0032E ??bb04_vreg_ctr_read: 1310 1310 ; line 328 : return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) ); 1311 1311 $DGL 0,24 1312 1312 0032E RD96100 mov x,!?L0073+1 ; rsub_temp ;[INF] 3, 1 1313 1313 00331 F1 clrb a ;[INF] 1, 1 1314 1314 00332 12 movw bc,ax ;[INF] 1, 1 1315 1315 00333 EF25 br $?L0072 ;[INF] 2, 3 1316 1316 00335 ??eb04_vreg_ctr_read: 1317 1317 ; line 329 : } 1318 1318 00335 ?L0082: 1319 1319 ; line 330 : else if( adrs == VREG_C_INFO ) 1320 1320 $DGL 0,26 1321 1321 00335 66 mov a,l ;[INF] 1, 1 1322 1322 00336 4C7F cmp a,#07FH ; 127 ;[INF] 2, 1 1323 1323 00338 DF0E bnz $?L0084 ;[INF] 2, 4 1324 1324 ; line 331 : { 1325 1325 0033A ??bb05_vreg_ctr_read: 1326 1326 ; line 332 : renge_task_immed_add( tski_mcu_info_read ); 1327 1327 $DGL 0,28 1328 1328 0033A R300000 movw ax,#loww (_tski_mcu_info_read) ;[INF] 3, 1 1329 1329 0033D RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 1330 1330 ; line 333 : IICAMK = 1; 1331 1331 $DGL 0,29 1332 1332 00340 713AD5 set1 MK2H.3 ;[INF] 3, 2 1333 1333 ; line 334 : return( 0x4A ); 1334 1334 $DGL 0,30 1335 1335 00343 324A00 movw bc,#04AH ; 74 ;[INF] 3, 1 1336 1336 00346 EF12 br $?L0072 ;[INF] 2, 3 1337 1337 00348 ??eb05_vreg_ctr_read: 1338 1338 ; line 335 : } 1339 1339 00348 ?L0084: 1340 1340 ; line 336 : 1341 1341 ; line 337 : #if 1 1342 1342 ; line 338 : if( adrs >= VREG_C_ENDMARK_ ) 1343 1343 $DGL 0,34 1344 1344 00348 66 mov a,l ;[INF] 1, 1 1345 1345 00349 4C60 cmp a,#060H ; 96 ;[INF] 2, 1 1346 1346 0034B DC05 bc $?L0086 ;[INF] 2, 4 1347 1347 ; line 339 : { 1348 1348 0034D ??bb06_vreg_ctr_read: 1349 1349 ; line 340 : // VREG_C_INFO > VREG_C_ENDMARK_ なので 1350 1350 ; line 341 : // いじるときは注意 1351 1351 ; line 342 : return( 0xEE ); 1352 1352 $DGL 0,38 1353 1353 0034D 32EE00 movw bc,#0EEH ; 238 ;[INF] 3, 1 1354 1354 00350 EF08 br $?L0072 ;[INF] 2, 3 1355 1355 00352 ??eb06_vreg_ctr_read: 1356 1356 ; line 343 : } 1357 1357 00352 ?L0086: 1358 1358 ; line 344 : #endif 1359 1359 ; line 345 : return ( vreg_ctr[adrs] ); 1360 1360 $DGL 0,41 1361 1361 00352 66 mov a,l ;[INF] 1, 1 1362 1362 00353 73 mov b,a ;[INF] 1, 1 1363 1363 00354 R090000 mov a,_vreg_ctr[b] ;[INF] 3, 1 1364 1364 00357 318E shrw ax,8 ;[INF] 2, 1 1365 1365 00359 12 movw bc,ax ;[INF] 1, 1 1366 1366 ; line 346 : } 1367 1367 0035A ?L0072: 1368 1368 $DGL 0,42 1369 1369 0035A ??ef_vreg_ctr_read: 1370 1370 0035A C6 pop hl ;[INF] 1, 1 1371 1371 0035B D7 ret ;[INF] 1, 6 1372 1372 0035C ??ee_vreg_ctr_read: 1373 1373 ; line 347 : 1374 1374 ; line 348 : 1375 1375 ; line 349 : 1376 1376 ; line 350 : // ******************************************************** 1377 1377 ; line 351 : // I2C仮想レジスタから読まれて何かするレジスタ 1378 1378 ; line 352 : void vreg_ctr_after_read( u8 adrs ) 1379 1379 ; line 353 : { 1380 1380 0035C _vreg_ctr_after_read: 1381 1381 $DGL 1,125 1382 1382 0035C C7 push hl ;[INF] 1, 1 1383 1383 0035D 16 movw hl,ax ;[INF] 1, 1 1384 1384 0035E ??bf_vreg_ctr_after_read: 1385 1385 ; line 354 : 1386 1386 ; line 355 : // 割り込みフラグはリードでクリア 1387 1387 ; line 356 : switch( adrs ) 1388 1388 $DGL 0,4 1389 1389 0035E 17 movw ax,hl ;[INF] 1, 1 1390 1390 0035F F1 clrb a ;[INF] 1, 1 1391 1391 00360 241000 subw ax,#010H ; 16 ;[INF] 3, 1 1392 1392 00363 240500 subw ax,#05H ; 5 ;[INF] 3, 1 1393 1393 00366 DE09 bnc $?L0092 ;[INF] 2, 4 1394 1394 ; line 357 : { 1395 1395 00368 ??bb00_vreg_ctr_after_read: 1396 1396 ; line 358 : case VREG_C_IRQ0: 1397 1397 ; line 359 : case VREG_C_IRQ1: 1398 1398 ; line 360 : case VREG_C_IRQ2: 1399 1399 ; line 361 : case VREG_C_IRQ3: 1400 1400 ; line 362 : case VREG_C_IRQ4: 1401 1401 ; line 363 : vreg_ctr[ adrs ] = 0; 1402 1402 $DGL 0,11 1403 1403 00368 66 mov a,l ;[INF] 1, 1 1404 1404 00369 72 mov c,a ;[INF] 1, 1 1405 1405 0036A R38000000 mov _vreg_ctr[c],#00H ; 0 ;[INF] 4, 1 1406 1406 ; line 364 : irq_readed = 1; 1407 1407 $DGL 0,12 1408 1408 0036E R710200 set1 _irq_readed ;[INF] 3, 2 1409 1409 ; line 365 : break; 1410 1410 ; line 366 : 1411 1411 ; line 367 : default: 1412 1412 00371 ?L0092: 1413 1413 ; line 368 : break; 1414 1414 00371 ??eb00_vreg_ctr_after_read: 1415 1415 ; line 369 : } 1416 1416 ; line 370 : } 1417 1417 $DGL 0,18 1418 1418 00371 ??ef_vreg_ctr_after_read: 1419 1419 00371 C6 pop hl ;[INF] 1, 1 1420 1420 00372 D7 ret ;[INF] 1, 6 1421 1421 00373 ??ee_vreg_ctr_after_read: 1422 1422 ; line 371 : 1423 1423 ; line 372 : 1424 1424 ; line 373 : 1425 1425 ; line 374 : 1426 1426 ; line 375 : 1427 1427 ; line 376 : 1428 1428 ; line 377 : /*************************************************************** 1429 1429 ; *************** 1430 1430 ; line 378 : 割り込みを入れる 1431 1431 ; line 379 : 割り込みマスクが必要と言うことでこんな事をする羽目になりました 1432 1432 ; line 380 : *************************************************************** 1433 1433 ; **************/ 1434 1434 ; line 381 : #if 0 1435 1435 ; line 382 : // マスクされてたら、フラグは立てるが、割り込みは入れない。 1436 1436 ; line 383 : #define set_irq( irqreg, bitpos ) \ 1437 1437 ; line 384 : { \ 1438 1438 ; line 385 : vreg_ctr[ irqreg ] |= bitpos; \ 1439 1439 ; line 386 : if( ( vreg_ctr[ irqreg+8 ] & bitpos ) == 0 ){ \ 1440 1440 ; line 387 : IRQ0_ast; \ 1441 1441 ; line 388 : } \ 1442 1442 ; line 389 : } 1443 1443 ; line 390 : #endif 1444 1444 ; line 391 : 1445 1445 ; line 392 : // マスクされてたら、フラグも立てず、割り込みも入れない。 1446 1446 ; line 393 : void set_irq( u8 irqreg, u8 irq_flg ) 1447 1447 ; line 394 : { 1448 1448 00373 _set_irq: 1449 1449 $DGL 1,136 1450 1450 00373 717BFA di ;[INF] 3, 4 1451 1451 00376 C7 push hl ;[INF] 1, 1 1452 1452 00377 C1 push ax ;[INF] 1, 1 1453 1453 00378 C1 push ax ;[INF] 1, 1 1454 1454 00379 FBF8FF movw hl,sp ;[INF] 3, 1 1455 1455 0037C ??bf_set_irq: 1456 1456 ; line 395 : u8 tot; 1457 1457 ; line 396 : 1458 1458 ; line 397 : DI(); 1459 1459 ; line 398 : if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 ){ 1460 1460 $DGL 0,5 1461 1461 0037C 8C02 mov a,[hl+2] ; irqreg ;[INF] 2, 1 1462 1462 0037E 73 mov b,a ;[INF] 1, 1 1463 1463 0037F R090800 mov a,_vreg_ctr+8[b] ;[INF] 3, 1 1464 1464 00382 5E0A and a,[hl+10] ; irq_flg ;[INF] 2, 1 1465 1465 00384 D1 cmp0 a ;[INF] 1, 1 1466 1466 00385 DF24 bnz $?L0097 ;[INF] 2, 4 1467 1467 00387 ??bb00_set_irq: 1468 1468 ; line 399 : vreg_ctr[ irqreg ] |= irq_flg; 1469 1469 $DGL 0,6 1470 1470 00387 8C02 mov a,[hl+2] ; irqreg ;[INF] 2, 1 1471 1471 00389 318E shrw ax,8 ;[INF] 2, 1 1472 1472 0038B R040000 addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 1473 1473 0038E 14 movw de,ax ;[INF] 1, 1 1474 1474 0038F 89 mov a,[de] ;[INF] 1, 1 1475 1475 00390 6E0A or a,[hl+10] ; irq_flg ;[INF] 2, 1 1476 1476 00392 99 mov [de],a ;[INF] 1, 1 1477 1477 ; line 400 : IRQ0_neg; // 一瞬上げて落とし直す。 1478 1478 $DGL 0,7 1479 1479 00393 ??bb01_set_irq: 1480 1480 00393 716A27 set1 PM7.6 ;[INF] 3, 2 1481 1481 00396 ??eb01_set_irq: 1482 1482 ; line 401 : // EI(); 1483 1483 ; line 402 : tot = 0; 1484 1484 $DGL 0,9 1485 1485 00396 CC0100 mov [hl+1],#00H ; tot,0 ;[INF] 3, 1 1486 1486 ; line 403 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.D.なのでちゃん 1487 1487 ; とあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) 1488 1488 $DGL 0,10 1489 1489 00399 ?L0099: 1490 1490 00399 31620708 bt P7.6,$?L0100 ;[INF] 4, 5 1491 1491 0039D 615901 inc [hl+1] ; tot ;[INF] 3, 2 1492 1492 003A0 8C01 mov a,[hl+1] ; tot ;[INF] 2, 1 1493 1493 003A2 D1 cmp0 a ;[INF] 1, 1 1494 1494 003A3 DFF4 bnz $?L0099 ;[INF] 2, 4 1495 1495 003A5 ??bb02_set_irq: 1496 1496 003A5 ??eb02_set_irq: 1497 1497 003A5 ?L0100: 1498 1498 ; line 404 : IRQ0_ast; 1499 1499 $DGL 0,11 1500 1500 003A5 ??bb03_set_irq: 1501 1501 003A5 716307 clr1 P7.6 ;[INF] 3, 2 1502 1502 003A8 716B27 clr1 PM7.6 ;[INF] 3, 2 1503 1503 003AB ??eb03_set_irq: 1504 1504 003AB ??eb00_set_irq: 1505 1505 ; line 405 : } 1506 1506 003AB ?L0097: 1507 1507 ; line 406 : EI(); 1508 1508 ; line 407 : } 1509 1509 $DGL 0,14 1510 1510 003AB ??ef_set_irq: 1511 1511 003AB 1004 addw sp,#04H ;[INF] 2, 1 1512 1512 003AD C6 pop hl ;[INF] 1, 1 1513 1513 003AE 717AFA ei ;[INF] 3, 4 1514 1514 003B1 D7 ret ;[INF] 1, 6 1515 1515 003B2 ??ee_set_irq: 1516 1516 1517 1517 ----- @@CODEL CSEG 1518 1518 1519 1519 ----- @@BASE CSEG BASE 1520 1520 END 1521 1521 1522 1522 1523 1523 ; *** Code Information *** 1524 1524 ; 1525 1525 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c 1526 1526 ; 1527 1527 ; $FUNC vreg_ctr_init(42) 1528 1528 ; void=(void) 1529 1529 ; CODE SIZE= 21 bytes, CLOCK_SIZE= 11 clocks, STACK_SIZE= 0 bytes 1530 1530 ; 1531 1531 ; $FUNC vreg_ctr_write(66) 1532 1532 ; void=(unsigned char adrs:x, unsigned char data:[sp+6]) 1533 1533 ; CODE SIZE= 660 bytes, CLOCK_SIZE= 961 clocks, STACK_SIZE= 12 bytes 1534 1534 ; 1535 1535 ; $CALL renge_task_immed_add(80) 1536 1536 ; bc=(pointer:ax) 1537 1537 ; 1538 1538 ; $CALL renge_task_immed_add(94) 1539 1539 ; bc=(pointer:ax) 1540 1540 ; 1541 1541 ; $CALL renge_task_immed_add(111) 1542 1542 ; bc=(pointer:ax) 1543 1543 ; 1544 1544 ; $CALL renge_task_immed_add(120) 1545 1545 ; bc=(pointer:ax) 1546 1546 ; 1547 1547 ; $CALL renge_task_immed_add(124) 1548 1548 ; bc=(pointer:ax) 1549 1549 ; 1550 1550 ; $CALL renge_task_immed_add(132) 1551 1551 ; bc=(pointer:ax) 1552 1552 ; 1553 1553 ; $CALL set_rtc(195) 1554 1554 ; void=(int:ax, int:[sp+4]) 1555 1555 ; 1556 1556 ; $CALL set_rtc(199) 1557 1557 ; void=(int:ax, int:[sp+4]) 1558 1558 ; 1559 1559 ; $CALL set_rtc(203) 1560 1560 ; void=(int:ax, int:[sp+4]) 1561 1561 ; 1562 1562 ; $CALL set_rtc(207) 1563 1563 ; void=(int:ax, int:[sp+4]) 1564 1564 ; 1565 1565 ; $CALL set_rtc(211) 1566 1566 ; void=(int:ax, int:[sp+4]) 1567 1567 ; 1568 1568 ; $CALL set_rtc(215) 1569 1569 ; void=(int:ax, int:[sp+4]) 1570 1570 ; 1571 1571 ; $CALL renge_task_immed_add(249) 1572 1572 ; bc=(pointer:ax) 1573 1573 ; 1574 1574 ; $CALL renge_task_immed_add(254) 1575 1575 ; bc=(pointer:ax) 1576 1576 ; 1577 1577 ; $CALL renge_task_immed_add(263) 1578 1578 ; bc=(pointer:ax) 1579 1579 ; 1580 1580 ; $CALL clear_hosu_hist(275) 1581 1581 ; void=(void) 1582 1582 ; 1583 1583 ; $FUNC vreg_ctr_read(305) 1584 1584 ; bc=(unsigned char adrs:x) 1585 1585 ; CODE SIZE= 117 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 6 bytes 1586 1586 ; 1587 1587 ; $CALL rtc_buf_reflesh(311) 1588 1588 ; void=(void) 1589 1589 ; 1590 1590 ; $CALL hosu_read(319) 1591 1591 ; bc=(void) 1592 1592 ; 1593 1593 ; $CALL renge_task_immed_add(332) 1594 1594 ; bc=(pointer:ax) 1595 1595 ; 1596 1596 ; $FUNC vreg_ctr_after_read(353) 1597 1597 ; void=(unsigned char adrs:x) 1598 1598 ; CODE SIZE= 23 bytes, CLOCK_SIZE= 22 clocks, STACK_SIZE= 2 bytes 1599 1599 ; 1600 1600 ; $FUNC set_irq(394) 1601 1601 ; void=(unsigned char irqreg:x, unsigned char irq_flg:[sp+4]) 1602 1602 ; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 6 bytes 1603 1603 1604 1604 ; Target chip : uPD79F0104 1605 1605 ; Device file : E1.00b Segment informations: ADRS LEN NAME 00000 00000H.1 @@BITS 00000 00030H @@CNST 00000 00000H @@R_INIT 00000 00000H @@INIT 00000 00062H @@DATA 00000 00000H @@R_INIS 00000 00000H @@INIS 00000 00000H @@DATS 00000 00000H @@CNSTL 00000 00000H @@RLINIT 00000 00000H @@INITL 00000 00000H @@DATAL 00000 00000H @@CALT 00000 003B2H ROM_CODE 00000 00000H @@CODEL 00000 00000H @@BASE Target chip : uPD79F0104 Device file : E1.00b Assembly complete, 0 error(s) and 0 warning(s) found. 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