78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_misc.asm Para-file: In-file: inter_asm\task_misc.asm Obj-file: task_misc.rel Prn-file: task_misc.prn Assemble list ALNO STNO ADRS OBJECT M I SOURCE STATEMENT 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 2 2 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_misc.c 6 6 ; In-file : task_misc.c 7 7 ; Asm-file : inter_asm\task_misc.asm 8 8 ; Para-file : 9 9 10 10 $PROCESSOR(9F0104) 11 11 $DEBUG 12 12 $NODEBUGA 13 13 $KANJICODE SJIS 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H 15 15 16 16 $DGS FIL_NAM, .file, 0EAH, 0FFFEH, 03FH, 067H, 01H, 00H 17 17 $DGS AUX_FIL, task_misc.c 18 18 $DGS MOD_NAM, task_misc, 00H, 0FFFEH, 00H, 077H, 00H, 00H 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 36 36 $DGS AUX_TAG, 01H, 01EH 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 45 45 $DGS AUX_EOS, 013H, 01H 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 47 47 $DGS AUX_TAG, 01H, 025H 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 52 52 $DGS AUX_EOS, 01EH, 01H 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 54 54 $DGS AUX_TAG, 01H, 02FH 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 62 62 $DGS AUX_EOS, 025H, 01H 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H 64 64 $DGS AUX_TAG, 04H, 041H 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H 70 70 $DGS AUX_BIT, 00H, 01H 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H 72 72 $DGS AUX_BIT, 00H, 01H 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H 74 74 $DGS AUX_BIT, 00H, 01H 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H 76 76 $DGS AUX_BIT, 00H, 01H 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H 80 80 $DGS AUX_EOS, 02FH, 04H 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 82 82 $DGS AUX_TAG, 01H, 047H 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 86 86 $DGS AUX_EOS, 041H, 01H 87 87 $DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H 88 88 $DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H 89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H 90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H 91 91 $DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 026H, 01H, 02H 92 92 $DGS AUX_FUN, 00H, U, U, 098H, 00H, 00H 93 93 $DGS BEG_FUN, ??bf_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H 94 94 $DGS AUX_BEG, 037H, 02H, 052H 95 95 $DGS STA_SYM, _interval_task_misc_stat, ?L0003, U, 0CH, 03H, 00H, 00H 96 96 $DGS STA_SYM, _state_old, ?L0004, U, 0CH, 03H, 00H, 00H 97 97 $DGS REG_VAR, _diff, 06H, 0FFFFH, 010CH, 04H, 00H, 00H 98 98 $DGS BEG_BLK, ??bb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 99 99 $DGS AUX_BEG, 0AH, 00H, 056H 100 100 $DGS END_BLK, ??eb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 101 101 $DGS AUX_END, 0DH 102 102 $DGS BEG_BLK, ??bb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 103 103 $DGS AUX_BEG, 0FH, 00H, 05AH 104 104 $DGS END_BLK, ??eb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 105 105 $DGS AUX_END, 011H 106 106 $DGS BEG_BLK, ??bb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 107 107 $DGS AUX_BEG, 013H, 00H, 05CH 108 108 $DGS BEG_BLK, ??bb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 109 109 $DGS AUX_BEG, 013H, 00H, 060H 110 110 $DGS END_BLK, ??eb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 111 111 $DGS AUX_END, 013H 112 112 $DGS BEG_BLK, ??bb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 113 113 $DGS AUX_BEG, 013H, 00H, 066H 114 114 $DGS END_BLK, ??eb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 115 115 $DGS AUX_END, 013H 116 116 $DGS END_BLK, ??eb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 117 117 $DGS AUX_END, 013H 118 118 $DGS BEG_BLK, ??bb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 119 119 $DGS AUX_BEG, 017H, 00H, 068H 120 120 $DGS BEG_BLK, ??bb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 121 121 $DGS AUX_BEG, 020H, 00H, 06AH 122 122 $DGS BEG_BLK, ??bb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 123 123 $DGS AUX_BEG, 024H, 00H, 06CH 124 124 $DGS BEG_BLK, ??bb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 125 125 $DGS AUX_BEG, 027H, 00H, 070H 126 126 $DGS END_BLK, ??eb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 127 127 $DGS AUX_END, 029H 128 128 $DGS BEG_BLK, ??bb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 129 129 $DGS AUX_BEG, 02BH, 00H, 076H 130 130 $DGS END_BLK, ??eb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 131 131 $DGS AUX_END, 02DH 132 132 $DGS END_BLK, ??eb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 133 133 $DGS AUX_END, 02EH 134 134 $DGS BEG_BLK, ??bb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 135 135 $DGS AUX_BEG, 031H, 00H, 078H 136 136 $DGS BEG_BLK, ??bb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 137 137 $DGS AUX_BEG, 034H, 00H, 07CH 138 138 $DGS END_BLK, ??eb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 139 139 $DGS AUX_END, 036H 140 140 $DGS BEG_BLK, ??bb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 141 141 $DGS AUX_BEG, 038H, 00H, 084H 142 142 $DGS END_BLK, ??eb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 143 143 $DGS AUX_END, 03AH 144 144 $DGS END_BLK, ??eb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 145 145 $DGS AUX_END, 03BH 146 146 $DGS END_BLK, ??eb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 147 147 $DGS AUX_END, 03CH 148 148 $DGS BEG_BLK, ??bb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 149 149 $DGS AUX_BEG, 049H, 00H, 086H 150 150 $DGS BEG_BLK, ??bb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 151 151 $DGS AUX_BEG, 04BH, 00H, 088H 152 152 $DGS BEG_BLK, ??bb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 153 153 $DGS AUX_BEG, 04CH, 00H, 090H 154 154 $DGS END_BLK, ??eb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 155 155 $DGS AUX_END, 04EH 156 156 $DGS END_BLK, ??eb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 157 157 $DGS AUX_END, 04FH 158 158 $DGS END_BLK, ??eb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 159 159 $DGS AUX_END, 050H 160 160 $DGS BEG_BLK, ??bb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 161 161 $DGS AUX_BEG, 054H, 00H, 00H 162 162 $DGS END_BLK, ??eb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 163 163 $DGS AUX_END, 057H 164 164 $DGS END_BLK, ??eb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H 165 165 $DGS AUX_END, 058H 166 166 $DGS END_FUN, ??ef_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H 167 167 $DGS AUX_END, 05AH 168 168 $DGS GLV_SYM, _do_command0, U, U, 0AH, 026H, 01H, 02H 169 169 $DGS AUX_FUN, 041H, U, U, 0CEH, 00H, 00H 170 170 $DGS BEG_FUN, ??bf_do_command0, U, U, 00H, 065H, 01H, 00H 171 171 $DGS AUX_BEG, 09FH, 00H, 09CH 172 172 $DGS BEG_BLK, ??bb00_do_command0, U, U, 00H, 064H, 01H, 00H 173 173 $DGS AUX_BEG, 04H, 00H, 09EH 174 174 $DGS BEG_BLK, ??bb01_do_command0, U, U, 00H, 064H, 01H, 00H 175 175 $DGS AUX_BEG, 06H, 00H, 0A2H 176 176 $DGS END_BLK, ??eb01_do_command0, U, U, 00H, 064H, 01H, 00H 177 177 $DGS AUX_END, 08H 178 178 $DGS BEG_BLK, ??bb02_do_command0, U, U, 00H, 064H, 01H, 00H 179 179 $DGS AUX_BEG, 0AH, 00H, 0A4H 180 180 $DGS BEG_BLK, ??bb03_do_command0, U, U, 00H, 064H, 01H, 00H 181 181 $DGS AUX_BEG, 0CH, 00H, 0A6H 182 182 $DGS BEG_BLK, ??bb04_do_command0, U, U, 00H, 064H, 01H, 00H 183 183 $DGS AUX_BEG, 0EH, 00H, 0AAH 184 184 $DGS END_BLK, ??eb04_do_command0, U, U, 00H, 064H, 01H, 00H 185 185 $DGS AUX_END, 0EH 186 186 $DGS BEG_BLK, ??bb05_do_command0, U, U, 00H, 064H, 01H, 00H 187 187 $DGS AUX_BEG, 0FH, 00H, 0B0H 188 188 $DGS END_BLK, ??eb05_do_command0, U, U, 00H, 064H, 01H, 00H 189 189 $DGS AUX_END, 0FH 190 190 $DGS END_BLK, ??eb03_do_command0, U, U, 00H, 064H, 01H, 00H 191 191 $DGS AUX_END, 010H 192 192 $DGS BEG_BLK, ??bb06_do_command0, U, U, 00H, 064H, 01H, 00H 193 193 $DGS AUX_BEG, 012H, 00H, 0B2H 194 194 $DGS BEG_BLK, ??bb07_do_command0, U, U, 00H, 064H, 01H, 00H 195 195 $DGS AUX_BEG, 013H, 00H, 0B8H 196 196 $DGS END_BLK, ??eb07_do_command0, U, U, 00H, 064H, 01H, 00H 197 197 $DGS AUX_END, 013H 198 198 $DGS END_BLK, ??eb06_do_command0, U, U, 00H, 064H, 01H, 00H 199 199 $DGS AUX_END, 014H 200 200 $DGS BEG_BLK, ??bb08_do_command0, U, U, 00H, 064H, 01H, 00H 201 201 $DGS AUX_BEG, 016H, 00H, 0BAH 202 202 $DGS BEG_BLK, ??bb09_do_command0, U, U, 00H, 064H, 01H, 00H 203 203 $DGS AUX_BEG, 017H, 00H, 0C0H 204 204 $DGS END_BLK, ??eb09_do_command0, U, U, 00H, 064H, 01H, 00H 205 205 $DGS AUX_END, 017H 206 206 $DGS END_BLK, ??eb08_do_command0, U, U, 00H, 064H, 01H, 00H 207 207 $DGS AUX_END, 018H 208 208 $DGS BEG_BLK, ??bb0A_do_command0, U, U, 00H, 064H, 01H, 00H 209 209 $DGS AUX_BEG, 01AH, 00H, 0C4H 210 210 $DGS END_BLK, ??eb0A_do_command0, U, U, 00H, 064H, 01H, 00H 211 211 $DGS AUX_END, 01AH 212 212 $DGS BEG_BLK, ??bb0B_do_command0, U, U, 00H, 064H, 01H, 00H 213 213 $DGS AUX_BEG, 01CH, 00H, 00H 214 214 $DGS END_BLK, ??eb0B_do_command0, U, U, 00H, 064H, 01H, 00H 215 215 $DGS AUX_END, 01CH 216 216 $DGS END_BLK, ??eb02_do_command0, U, U, 00H, 064H, 01H, 00H 217 217 $DGS AUX_END, 025H 218 218 $DGS END_BLK, ??eb00_do_command0, U, U, 00H, 064H, 01H, 00H 219 219 $DGS AUX_END, 026H 220 220 $DGS END_FUN, ??ef_do_command0, U, U, 00H, 065H, 01H, 00H 221 221 $DGS AUX_END, 02AH 222 222 $DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 026H, 01H, 02H 223 223 $DGS AUX_FUN, 041H, U, U, 0EAH, 00H, 00H 224 224 $DGS BEG_FUN, ??bf_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H 225 225 $DGS AUX_BEG, 0D9H, 02H, 0D3H 226 226 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H 227 227 $DGS BEG_BLK, ??bb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 228 228 $DGS AUX_BEG, 06H, 00H, 0D7H 229 229 $DGS END_BLK, ??eb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 230 230 $DGS AUX_END, 08H 231 231 $DGS BEG_BLK, ??bb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 232 232 $DGS AUX_BEG, 0BH, 00H, 0DBH 233 233 $DGS END_BLK, ??eb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 234 234 $DGS AUX_END, 0DH 235 235 $DGS BEG_BLK, ??bb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 236 236 $DGS AUX_BEG, 010H, 00H, 0DFH 237 237 $DGS END_BLK, ??eb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 238 238 $DGS AUX_END, 012H 239 239 $DGS BEG_BLK, ??bb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 240 240 $DGS AUX_BEG, 014H, 00H, 0E3H 241 241 $DGS END_BLK, ??eb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 242 242 $DGS AUX_END, 016H 243 243 $DGS BEG_BLK, ??bb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 244 244 $DGS AUX_BEG, 018H, 00H, 00H 245 245 $DGS END_BLK, ??eb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H 246 246 $DGS AUX_END, 031H 247 247 $DGS LAB_SYM, _end, ?L0046, U, 00H, 06H, 00H, 00H 248 248 $DGS END_FUN, ??ef_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H 249 249 $DGS AUX_END, 03AH 250 250 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H 251 251 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 252 252 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H 253 253 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H 254 254 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H 255 255 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H 256 256 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H 257 257 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 258 258 $DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 02H, 01H, 02H 259 259 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H 260 260 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H 261 261 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 262 262 $DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 02H, 01H, 02H 263 263 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H 264 264 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H 265 265 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 266 266 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H 267 267 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 268 268 $DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 02H, 00H, 00H 269 269 $DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H 270 270 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 271 271 272 272 EXTRN _iic_mcu_read_a_byte 273 273 EXTRN _vreg_ctr 274 274 EXTRN _system_status 275 275 EXTRN _set_irq 276 276 EXTRN _tsk_cbk_accero 277 277 EXTRN _renge_task_immed_add 278 278 EXTRN _ntr_pmic_comm 279 279 EXTRN _iic_mcu_write_a_byte 280 280 EXTRN _wait_ms 281 281 EXTRN _iic_burst_state 282 282 EXTRN _get_adc 283 283 PUBLIC _tsk_misc_stat 284 284 PUBLIC _do_command0 285 285 PUBLIC _tski_mcu_info_read 286 286 287 287 ----- @@BITS BSEG 288 288 289 289 ----- @@CNST CSEG MIRRORP 290 290 00000 01 _lpf_coeff: DB 01H ; 1 291 291 00001 02 DB 02H ; 2 292 292 00002 02 DB 02H ; 2 293 293 00003 03 DB 03H ; 3 294 294 00004 03 DB 03H ; 3 295 295 00005 02 DB 02H ; 2 296 296 00006 00 DB 00H ; 0 297 297 00007 FE DB 0FEH ; 254 298 298 00008 FB DB 0FBH ; 251 299 299 00009 F7 DB 0F7H ; 247 300 300 0000A F3 DB 0F3H ; 243 301 301 0000B F0 DB 0F0H ; 240 302 302 0000C F0 DB 0F0H ; 240 303 303 0000D F3 DB 0F3H ; 243 304 304 0000E FA DB 0FAH ; 250 305 305 0000F 04 DB 04H ; 4 306 306 00010 12 DB 012H ; 18 307 307 00011 25 DB 025H ; 37 308 308 00012 38 DB 038H ; 56 309 309 00013 4D DB 04DH ; 77 310 310 00014 5F DB 05FH ; 95 311 311 00015 6E DB 06EH ; 110 312 312 00016 77 DB 077H ; 119 313 313 00017 7A DB 07AH ; 122 314 314 00018 77 DB 077H ; 119 315 315 00019 6E DB 06EH ; 110 316 316 0001A 5F DB 05FH ; 95 317 317 0001B 4D DB 04DH ; 77 318 318 0001C 38 DB 038H ; 56 319 319 0001D 25 DB 025H ; 37 320 320 0001E 12 DB 012H ; 18 321 321 0001F 04 DB 04H ; 4 322 322 00020 FA DB 0FAH ; 250 323 323 00021 F3 DB 0F3H ; 243 324 324 00022 F0 DB 0F0H ; 240 325 325 00023 F0 DB 0F0H ; 240 326 326 00024 F3 DB 0F3H ; 243 327 327 00025 F7 DB 0F7H ; 247 328 328 00026 FB DB 0FBH ; 251 329 329 00027 FE DB 0FEH ; 254 330 330 00028 00 DB 00H ; 0 331 331 00029 02 DB 02H ; 2 332 332 0002A 03 DB 03H ; 3 333 333 0002B 03 DB 03H ; 3 334 334 0002C 02 DB 02H ; 2 335 335 0002D 02 DB 02H ; 2 336 336 0002E 01 DB 01H ; 1 337 337 0002F 00 DB (1) 338 338 339 339 ----- @@R_INIT CSEG UNIT64KP 340 340 00000 00 DB 00H ; 0 341 341 00001 00 DB (1) 342 342 343 343 ----- @@INIT DSEG BASEP 344 344 00000 ?L0003: DS (1) 345 345 00001 DS (1) 346 346 347 347 ----- @@DATA DSEG BASEP 348 348 00000 ?L0004: DS (1) 349 349 00001 DS (1) 350 350 351 351 ----- @@R_INIS CSEG UNIT64KP 352 352 353 353 ----- @@INIS DSEG SADDRP 354 354 355 355 ----- @@DATS DSEG SADDRP 356 356 357 357 ----- @@CNSTL CSEG PAGE64KP 358 358 359 359 ----- @@RLINIT CSEG UNIT64KP 360 360 361 361 ----- @@INITL DSEG UNIT64KP 362 362 363 363 ----- @@DATAL DSEG UNIT64KP 364 364 365 365 ----- @@CALT CSEG CALLT0 366 366 367 367 ; Sub-Routines created by CC78K0R 368 368 369 369 ----- ROM_CODE CSEG BASE 370 370 00000 bs_F0060: 371 371 00000 C1 push ax ;[INF] 1, 1 372 372 00001 506C mov x,#06CH ; 108 ;[INF] 2, 1 373 373 00003 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 374 374 00006 C0 pop ax ;[INF] 1, 1 375 375 00007 62 mov a,c ;[INF] 1, 1 376 376 00008 9F4005 mov !IICA1,a ;[INF] 3, 1 377 377 0000B D7 ret ;[INF] 1, 6 378 378 0000C es_F0060: 379 379 380 380 ; *** Sub-Routine Information *** 381 381 ; 382 382 ; $SUB bs_F0060 383 383 ; CODE SIZE= 12 bytes 384 384 385 385 ; End of Sub-Routines 386 386 387 387 ; line 1 : #pragma SFR 388 388 ; line 2 : #pragma NOP 389 389 ; line 3 : #pragma HALT 390 390 ; line 4 : #pragma STOP 391 391 ; line 5 : 392 392 ; line 6 : #include "incs.h" 393 393 ; line 7 : #include "renge.h" 394 394 ; line 8 : #include "pm.h" 395 395 ; line 9 : 396 396 ; line 10 : #include "accero.h" 397 397 ; line 11 : #include "adc.h" 398 398 ; line 12 : #include "i2c_mcu.h" 399 399 ; line 13 : 400 400 ; line 14 : 401 401 ; line 15 : #ifdef _MCU_BSR_ 402 402 ; line 16 : #define ACKD ACKD1 403 403 ; line 17 : #define ACKE ACKE1 404 404 ; line 18 : #define COI COI1 405 405 ; line 19 : #define IICAEN IICA1EN 406 406 ; line 20 : #define IICRSV IICRSV1 407 407 ; line 21 : #define IICA IICA1 408 408 ; line 22 : #define IICAIF IICAIF1 409 409 ; line 23 : #define IICAMK IICAMK1 410 410 ; line 24 : #define IICAPR0 IICAPR11 411 411 ; line 25 : #define IICAPR1 IICAPR01 412 412 ; line 26 : #define IICCTL0 IICCTL10 413 413 ; line 27 : #define IICE IICE1 414 414 ; line 28 : #define IICF IICF1 415 415 ; line 29 : #define IICS IICS1 416 416 ; line 30 : #define IICWH IICWH1 417 417 ; line 31 : #define IICWL IICWL1 418 418 ; line 32 : #define LREL LREL1 419 419 ; line 33 : #define SPD SPD1 420 420 ; line 34 : #define SPIE SPIE1 421 421 ; line 35 : #define STCEN STCEN1 422 422 ; line 36 : #define STD STD1 423 423 ; line 37 : #define SVA SVA1 424 424 ; line 38 : #define WREL WREL1 425 425 ; line 39 : #define WTIM WTIM1 426 426 ; line 40 : #define TRC TRC1 427 427 ; line 41 : #define SMC SMC1 428 428 ; line 42 : #define DFC DFC1 429 429 ; line 43 : #endif 430 430 ; line 44 : 431 431 ; line 45 : 432 432 ; line 46 : 433 433 ; line 47 : // ======================================================== 434 434 ; line 48 : #define INTERVAL_TSK_MISC_STAT 4 435 435 ; line 49 : 436 436 ; line 50 : 437 437 ; line 51 : /* ======================================================== 438 438 ; line 52 : ステータスレジスタなど 439 439 ; line 53 : ======================================================== */ 440 440 ; line 54 : void tsk_misc_stat( ) 441 441 ; line 55 : { 442 442 443 443 ----- ROM_CODE CSEG BASE 444 444 0000C _tsk_misc_stat: 445 445 $DGL 1,75 446 446 0000C C7 push hl ;[INF] 1, 1 447 447 0000D ??bf_tsk_misc_stat: 448 448 ; line 56 : static u8 interval_task_misc_stat = 0; 449 449 ; line 57 : static u8 state_old; // ステータス変化検出→割り込み 450 450 ; の為 451 451 ; line 58 : #ifdef _BL_INDEPENDENT_ 452 452 ; line 59 : static u8 state2_old; 453 453 ; line 60 : #endif 454 454 ; line 61 : u8 diff; 455 455 ; line 62 : 456 456 ; line 63 : if( interval_task_misc_stat != 0 ) 457 457 $DGL 0,9 458 458 0000D RD50000 cmp0 !?L0003 ; interval_task_misc_stat ;[INF] 3, 1 459 459 00010 DD06 bz $?L0005 ;[INF] 2, 4 460 460 ; line 64 : { 461 461 00012 ??bb00_tsk_misc_stat: 462 462 ; line 65 : interval_task_misc_stat -= 1; 463 463 $DGL 0,11 464 464 00012 RB00000 dec !?L0003 ; interval_task_misc_stat ;[INF] 3, 2 465 465 ; line 66 : return; 466 466 $DGL 0,12 467 467 00015 REDB700 br !?L0028 ;[INF] 3, 3 468 468 00018 ??eb00_tsk_misc_stat: 469 469 ; line 67 : } 470 470 00018 ?L0005: 471 471 ; line 68 : else 472 472 ; line 69 : { 473 473 00018 ??bb01_tsk_misc_stat: 474 474 ; line 70 : interval_task_misc_stat = ( INTERVAL_TSK_MISC_STAT / SYS 475 475 ; _INTERVAL_TICK ); 476 476 $DGL 0,16 477 477 00018 RCF000002 mov !?L0003,#02H ; interval_task_misc_stat,2 ;[INF] 4, 1 478 478 0001C ??eb01_tsk_misc_stat: 479 479 ; line 71 : } 480 480 ; line 72 : 481 481 ; line 73 : set_bit( SHELL_OPEN, vreg_ctr[VREG_C_STATUS], REG_BIT_ST_SHE 482 482 ; LL_OPEN ); 483 483 $DGL 0,19 484 484 0001C ??bb02_tsk_misc_stat: 485 485 0001C 31140706 bf P7.1,$?L0007 ;[INF] 4, 5 486 486 00020 ??bb03_tsk_misc_stat: 487 487 00020 R71100F00 set1 !_vreg_ctr+15.1 ;[INF] 4, 2 488 488 00024 ??eb03_tsk_misc_stat: 489 489 00024 EF04 br $?L0008 ;[INF] 2, 3 490 490 00026 ?L0007: 491 491 00026 ??bb04_tsk_misc_stat: 492 492 00026 R71180F00 clr1 !_vreg_ctr+15.1 ;[INF] 4, 2 493 493 0002A ??eb04_tsk_misc_stat: 494 494 0002A ?L0008: 495 495 0002A ??eb02_tsk_misc_stat: 496 496 ; line 74 : 497 497 ; line 75 : // ステータスレジスタ関係 → 割り込み // 498 498 ; line 76 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr 499 499 ; _state == SLEEP ) ) 500 500 $DGL 0,22 501 501 0002A R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 502 502 0002E DD09 bz $?L0011 ;[INF] 2, 4 503 503 00030 R40000005 cmp !_system_status,#05H ; 5 ;[INF] 4, 1 504 504 00034 61E8 skz ;[INF] 2, 1 505 505 00036 REDB700 br !?L0028 ;[INF] 3, 3 506 506 00039 ?L0011: 507 507 ; line 77 : { 508 508 00039 ??bb05_tsk_misc_stat: 509 509 ; line 78 : // pm.c で、その場で行います。 510 510 ; line 79 : // REG_BIT_LCD_ON/OFF 511 511 ; line 80 : // REG_BIT_BL_ON/OFF 512 512 ; line 81 : // REG_BIT_BT_DC_CONNECT/DISC 513 513 ; line 82 : 514 514 ; line 83 : 515 515 ; line 84 : diff = vreg_ctr[VREG_C_STATUS] ^ state_old; 516 516 $DGL 0,30 517 517 00039 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 518 518 0003C R7F0000 xor a,!?L0004 ; state_old ;[INF] 3, 1 519 519 0003F 76 mov l,a ;[INF] 1, 1 520 520 ; line 85 : if( diff != 0 ) 521 521 $DGL 0,31 522 522 00040 D1 cmp0 a ;[INF] 1, 1 523 523 00041 DD4E bz $?L0021 ;[INF] 2, 4 524 524 ; line 86 : { 525 525 00043 ??bb06_tsk_misc_stat: 526 526 ; line 87 : state_old = vreg_ctr[VREG_C_STATUS]; 527 527 $DGL 0,33 528 528 00043 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 529 529 00046 R9F0000 mov !?L0004,a ; state_old ;[INF] 3, 1 530 530 ; line 88 : 531 531 ; line 89 : if( diff & REG_BIT_BATT_CHARGE ) 532 532 $DGL 0,35 533 533 00049 66 mov a,l ;[INF] 1, 1 534 534 0004A 5C10 and a,#010H ; 16 ;[INF] 2, 1 535 535 0004C D1 cmp0 a ;[INF] 1, 1 536 536 0004D DD1E bz $?L0017 ;[INF] 2, 4 537 537 ; line 90 : { 538 538 0004F ??bb07_tsk_misc_stat: 539 539 ; line 91 : // 充電状態に以下略 540 540 ; line 92 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARG 541 541 ; E ) 542 542 $DGL 0,38 543 543 0004F R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 544 544 00052 5C10 and a,#010H ; 16 ;[INF] 2, 1 545 545 00054 D1 cmp0 a ;[INF] 1, 1 546 546 00055 DD0C bz $?L0016 ;[INF] 2, 4 547 547 ; line 93 : { 548 548 00057 ??bb08_tsk_misc_stat: 549 549 ; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_START ) 550 550 ; ; 551 551 $DGL 0,40 552 552 00057 308000 movw ax,#080H ; 128 ;[INF] 3, 1 553 553 0005A C1 push ax ;[INF] 1, 1 554 554 0005B 5011 mov x,#011H ; 17 ;[INF] 2, 1 555 555 0005D RFD0000 call !_set_irq ;[INF] 3, 3 556 556 00060 C0 pop ax ;[INF] 1, 1 557 557 00061 ??eb08_tsk_misc_stat: 558 558 ; line 95 : } 559 559 $DGL 0,41 560 560 00061 EF0A br $?L0017 ;[INF] 2, 3 561 561 00063 ?L0016: 562 562 ; line 96 : else 563 563 ; line 97 : { 564 564 00063 ??bb09_tsk_misc_stat: 565 565 ; line 98 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_STOP ); 566 566 $DGL 0,44 567 567 00063 304000 movw ax,#040H ; 64 ;[INF] 3, 1 568 568 00066 C1 push ax ;[INF] 1, 1 569 569 00067 5011 mov x,#011H ; 17 ;[INF] 2, 1 570 570 00069 RFD0000 call !_set_irq ;[INF] 3, 3 571 571 0006C C0 pop ax ;[INF] 1, 1 572 572 0006D ??eb09_tsk_misc_stat: 573 573 ; line 99 : } 574 574 0006D ?L0017: 575 575 0006D ??eb07_tsk_misc_stat: 576 576 ; line 100 : } 577 577 ; line 101 : 578 578 ; line 102 : if( diff & REG_BIT_ST_SHELL_OPEN ) 579 579 $DGL 0,48 580 580 0006D 66 mov a,l ;[INF] 1, 1 581 581 0006E 5C02 and a,#02H ; 2 ;[INF] 2, 1 582 582 00070 D1 cmp0 a ;[INF] 1, 1 583 583 00071 DD1E bz $?L0021 ;[INF] 2, 4 584 584 ; line 103 : { 585 585 00073 ??bb0A_tsk_misc_stat: 586 586 ; line 104 : // 蓋の開け閉め 587 587 ; line 105 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_O 588 588 ; PEN ) 589 589 $DGL 0,51 590 590 00073 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 591 591 00076 5C02 and a,#02H ; 2 ;[INF] 2, 1 592 592 00078 D1 cmp0 a ;[INF] 1, 1 593 593 00079 DD0C bz $?L0020 ;[INF] 2, 4 594 594 ; line 106 : { 595 595 0007B ??bb0B_tsk_misc_stat: 596 596 ; line 107 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_OPEN ); 597 597 $DGL 0,53 598 598 0007B 304000 movw ax,#040H ; 64 ;[INF] 3, 1 599 599 0007E C1 push ax ;[INF] 1, 1 600 600 0007F 5010 mov x,#010H ; 16 ;[INF] 2, 1 601 601 00081 RFD0000 call !_set_irq ;[INF] 3, 3 602 602 00084 C0 pop ax ;[INF] 1, 1 603 603 00085 ??eb0B_tsk_misc_stat: 604 604 ; line 108 : } 605 605 $DGL 0,54 606 606 00085 EF0A br $?L0021 ;[INF] 2, 3 607 607 00087 ?L0020: 608 608 ; line 109 : else 609 609 ; line 110 : { 610 610 00087 ??bb0C_tsk_misc_stat: 611 611 ; line 111 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_CLOSE ); 612 612 $DGL 0,57 613 613 00087 302000 movw ax,#020H ; 32 ;[INF] 3, 1 614 614 0008A C1 push ax ;[INF] 1, 1 615 615 0008B 5010 mov x,#010H ; 16 ;[INF] 2, 1 616 616 0008D RFD0000 call !_set_irq ;[INF] 3, 3 617 617 00090 C0 pop ax ;[INF] 1, 1 618 618 00091 ??eb0C_tsk_misc_stat: 619 619 ; line 112 : } 620 620 00091 ?L0021: 621 621 00091 ??eb0A_tsk_misc_stat: 622 622 ; line 113 : } 623 623 00091 ??eb06_tsk_misc_stat: 624 624 ; line 114 : } 625 625 ; line 115 : 626 626 ; line 116 : 627 627 ; line 117 : //#ifdef _MCU_KE3_ 628 628 ; line 118 : // KE3では必須です。 629 629 ; line 119 : /* ===================================================== 630 630 ; === 631 631 ; line 120 : 加速度センサ割り込みピンがオリジナルマイコンには無いの 632 632 ; で 633 633 ; line 121 : ポーリングする。 634 634 ; line 122 : 歩数計用 635 635 ; line 123 : BSRマイコンはaccero.cで割り込みルーチンからタスク登録 636 636 ; します。 637 637 ; line 124 : ===================================================== 638 638 ; === */ 639 639 ; line 125 : // 割り込みの取りこぼし？ 640 640 ; line 126 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) 641 641 $DGL 0,72 642 642 00091 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 643 643 00094 5C03 and a,#03H ; 3 ;[INF] 2, 1 644 644 00096 D1 cmp0 a ;[INF] 1, 1 645 645 00097 DD13 bz $?L0026 ;[INF] 2, 4 646 646 ; line 127 : { 647 647 00099 ??bb0D_tsk_misc_stat: 648 648 ; line 128 : if( ACC_VALID ) 649 649 $DGL 0,74 650 650 00099 C7 push hl ;[INF] 1, 1 651 651 0009A 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 652 652 0009D 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 653 653 0009F C6 pop hl ;[INF] 1, 1 654 654 000A0 DE0A bnc $?L0026 ;[INF] 2, 4 655 655 ; line 129 : { 656 656 000A2 ??bb0E_tsk_misc_stat: 657 657 ; line 130 : if( renge_task_immed_add( tsk_cbk_accero ) == ER 658 658 ; R_SUCCESS ){ 659 659 $DGL 0,76 660 660 000A2 R300000 movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1 661 661 000A5 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 662 662 000A8 D2 cmp0 c ;[INF] 1, 1 663 663 000A9 61F8 sknz ;[INF] 2, 1 664 664 000AB ??bb0F_tsk_misc_stat: 665 665 ; line 131 : NOP(); 666 666 $DGL 0,77 667 667 000AB 00 nop ;[INF] 1, 1 668 668 000AC ??eb0F_tsk_misc_stat: 669 669 ; line 132 : } 670 670 000AC ?L0026: 671 671 000AC ??eb0E_tsk_misc_stat: 672 672 ; line 133 : } 673 673 000AC ??eb0D_tsk_misc_stat: 674 674 ; line 134 : } 675 675 ; line 135 : //#endif 676 676 ; line 136 : 677 677 ; line 137 : // 割り込みの取りこぼし？ 678 678 ; line 138 : if( !PM_IRQ_n ){ 679 679 $DGL 0,84 680 680 000AC 31220707 bt P7.2,$?L0028 ;[INF] 4, 5 681 681 000B0 ??bb10_tsk_misc_stat: 682 682 ; line 139 : renge_task_immed_add( ntr_pmic_comm ); 683 683 $DGL 0,85 684 684 000B0 R300000 movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1 685 685 000B3 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 686 686 ; line 140 : NOP(); 687 687 $DGL 0,86 688 688 000B6 00 nop ;[INF] 1, 1 689 689 000B7 ??eb10_tsk_misc_stat: 690 690 ; line 141 : } 691 691 000B7 ?L0028: 692 692 000B7 ??eb05_tsk_misc_stat: 693 693 ; line 142 : } 694 694 ; line 143 : return; 695 695 ; line 144 : } 696 696 $DGL 0,90 697 697 000B7 ??ef_tsk_misc_stat: 698 698 000B7 C6 pop hl ;[INF] 1, 1 699 699 000B8 D7 ret ;[INF] 1, 6 700 700 000B9 ??ee_tsk_misc_stat: 701 701 ; line 145 : 702 702 ; line 146 : 703 703 ; line 147 : 704 704 ; line 148 : 705 705 ; line 149 : 706 706 ; line 150 : /* ======================================================== 707 707 ; line 151 : 逐一起動タスク 708 708 ; line 152 : ======================================================== */ 709 709 ; line 153 : 710 710 ; line 154 : /* ======================================================== 711 711 ; line 155 : COMMANDレジスタへの書き込み 712 712 ; line 156 : 　 0なら呼ばれません。ケア不要 713 713 ; line 157 : ======================================================== */ 714 714 ; line 158 : task_status_immed do_command0( ) 715 715 ; line 159 : { 716 716 000B9 _do_command0: 717 717 $DGL 1,152 718 718 000B9 ??bf_do_command0: 719 719 ; line 160 : // command0 本体電源など 720 720 ; line 161 : if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BI 721 721 ; T_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) ! 722 722 ; = 0x00 ) 723 723 $DGL 0,3 724 724 000B9 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 725 725 000BC 5C0F and a,#0FH ; 15 ;[INF] 2, 1 726 726 000BE D1 cmp0 a ;[INF] 1, 1 727 727 000BF DD5D bz $?L0035 ;[INF] 2, 4 728 728 ; line 162 : { 729 729 000C1 ??bb00_do_command0: 730 730 ; line 163 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ ) 731 731 $DGL 0,5 732 732 000C1 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 733 733 000C4 5C01 and a,#01H ; 1 ;[INF] 2, 1 734 734 000C6 D1 cmp0 a ;[INF] 1, 1 735 735 000C7 DD05 bz $?L0034 ;[INF] 2, 4 736 736 ; line 164 : { 737 737 000C9 ??bb01_do_command0: 738 738 ; line 165 : system_status.pwr_state = OFF_TRIG; 739 739 $DGL 0,7 740 740 000C9 RF50000 clrb !_system_status ;[INF] 3, 1 741 741 000CC ??eb01_do_command0: 742 742 ; line 166 : } 743 743 $DGL 0,8 744 744 000CC EF50 br $?L0035 ;[INF] 2, 3 745 745 000CE ?L0034: 746 746 ; line 167 : else 747 747 ; line 168 : { 748 748 000CE ??bb02_do_command0: 749 749 ; line 169 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ ) 750 750 $DGL 0,11 751 751 000CE R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 752 752 000D1 5C02 and a,#02H ; 2 ;[INF] 2, 1 753 753 000D3 D1 cmp0 a ;[INF] 1, 1 754 754 000D4 DD15 bz $?L0036 ;[INF] 2, 4 755 755 ; line 170 : { 756 756 000D6 ??bb03_do_command0: 757 757 ; line 171 : PM_reset_ast( ); 758 758 $DGL 0,13 759 759 000D6 E6 onew ax ;[INF] 1, 1 760 760 000D7 C1 push ax ;[INF] 1, 1 761 761 000D8 A1 incw ax ;[INF] 1, 1 762 762 000D9 A1 incw ax ;[INF] 1, 1 763 763 000DA C1 push ax ;[INF] 1, 1 764 764 000DB 5084 mov x,#084H ; 132 ;[INF] 2, 1 765 765 000DD RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 766 766 000E0 1004 addw sp,#04H ; 4 ;[INF] 2, 1 767 767 ; line 172 : RESET2_ast; 768 768 $DGL 0,14 769 769 000E2 ??bb04_do_command0: 770 770 000E2 711300 clr1 P0.1 ;[INF] 3, 2 771 771 000E5 711B20 clr1 PM0.1 ;[INF] 3, 2 772 772 000E8 ??eb04_do_command0: 773 773 ; line 173 : FCRAM_RST_ast; 774 774 $DGL 0,15 775 775 000E8 ??bb05_do_command0: 776 776 000E8 710303 clr1 P3.0 ;[INF] 3, 2 777 777 000EB ??eb05_do_command0: 778 778 000EB ??eb03_do_command0: 779 779 ; line 174 : } 780 780 000EB ?L0036: 781 781 ; line 175 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_ 782 782 ; REQ ) 783 783 $DGL 0,17 784 784 000EB R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 785 785 000EE 5C08 and a,#08H ; 8 ;[INF] 2, 1 786 786 000F0 D1 cmp0 a ;[INF] 1, 1 787 787 000F1 DD05 bz $?L0038 ;[INF] 2, 4 788 788 ; line 176 : { 789 789 000F3 ??bb06_do_command0: 790 790 ; line 177 : FCRAM_RST_ast; 791 791 $DGL 0,19 792 792 000F3 ??bb07_do_command0: 793 793 000F3 710303 clr1 P3.0 ;[INF] 3, 2 794 794 000F6 ??eb07_do_command0: 795 795 000F6 ??eb06_do_command0: 796 796 ; line 178 : } 797 797 $DGL 0,20 798 798 000F6 EF0E br $?L0040 ;[INF] 2, 3 799 799 000F8 ?L0038: 800 800 ; line 179 : else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_ 801 801 ; REQ ) 802 802 $DGL 0,21 803 803 000F8 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 804 804 000FB 5C04 and a,#04H ; 4 ;[INF] 2, 1 805 805 000FD D1 cmp0 a ;[INF] 1, 1 806 806 000FE DD06 bz $?L0040 ;[INF] 2, 4 807 807 ; line 180 : { 808 808 00100 ??bb08_do_command0: 809 809 ; line 181 : RESET2_ast; 810 810 $DGL 0,23 811 811 00100 ??bb09_do_command0: 812 812 00100 711300 clr1 P0.1 ;[INF] 3, 2 813 813 00103 711B20 clr1 PM0.1 ;[INF] 3, 2 814 814 00106 ??eb09_do_command0: 815 815 00106 ??eb08_do_command0: 816 816 ; line 182 : } 817 817 00106 ?L0040: 818 818 ; line 183 : wait_ms( 5 ); 819 819 $DGL 0,25 820 820 00106 300500 movw ax,#05H ; 5 ;[INF] 3, 1 821 821 00109 RFD0000 call !_wait_ms ;[INF] 3, 3 822 822 ; line 184 : FCRAM_RST_neg; 823 823 $DGL 0,26 824 824 0010C ??bb0A_do_command0: 825 825 0010C 710203 set1 P3.0 ;[INF] 3, 2 826 826 0010F ??eb0A_do_command0: 827 827 ; line 185 : PM_reset_neg(); 828 828 $DGL 0,27 829 829 0010F 300300 movw ax,#03H ; 3 ;[INF] 3, 1 830 830 00112 C1 push ax ;[INF] 1, 1 831 831 00113 C1 push ax ;[INF] 1, 1 832 832 00114 5084 mov x,#084H ; 132 ;[INF] 2, 1 833 833 00116 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 834 834 00119 1004 addw sp,#04H ; 4 ;[INF] 2, 1 835 835 ; line 186 : RESET2_neg; 836 836 $DGL 0,28 837 837 0011B ??bb0B_do_command0: 838 838 0011B 711A20 set1 PM0.1 ;[INF] 3, 2 839 839 0011E ??eb0B_do_command0: 840 840 0011E ??eb02_do_command0: 841 841 ; line 187 : /* 842 842 ; line 188 : // CODEC 不定レジスタ初期化 843 843 ; line 189 : wait_ms( 100 ); 844 844 ; line 190 : { 845 845 ; line 191 : u8 codec_reg_init[3] = { 0,0,0 }; 846 846 ; line 192 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, c 847 847 ; odec_reg_init ); 848 848 ; line 193 : } 849 849 ; line 194 : */ 850 850 ; line 195 : } 851 851 0011E ?L0035: 852 852 0011E ??eb00_do_command0: 853 853 ; line 196 : } 854 854 ; line 197 : 855 855 ; line 198 : vreg_ctr[VREG_C_COMMAND0] = 0; 856 856 $DGL 0,40 857 857 0011E RF52000 clrb !_vreg_ctr+32 ;[INF] 3, 1 858 858 ; line 199 : return ( ERR_FINISED ); 859 859 $DGL 0,41 860 860 00121 F7 clrw bc ;[INF] 1, 1 861 861 ; line 200 : } 862 862 $DGL 0,42 863 863 00122 ??ef_do_command0: 864 864 00122 D7 ret ;[INF] 1, 6 865 865 00123 ??ee_do_command0: 866 866 ; line 201 : 867 867 ; line 202 : 868 868 ; line 203 : 869 869 ; line 204 : /* ======================================================== 870 870 ; line 205 : 　互換向け、TWLアプリへの割り込み 871 871 ; line 206 : 仮想レジスタの書き込み時に行います。 872 872 ; line 207 : ======================================================== */ 873 873 ; line 208 : // task_status_immed do_command1( ) 874 874 ; line 209 : 875 875 ; line 210 : 876 876 ; line 211 : extern u8 iic_burst_state; 877 877 ; line 212 : /* ======================================================== 878 878 ; line 213 : 　デバッグ用にいろいろ読んできます。 879 879 ; line 214 : 　返値はデータそのもの 880 880 ; line 215 : ======================================================== */ 881 881 ; line 216 : task_status_immed tski_mcu_info_read() 882 882 ; line 217 : { 883 883 00123 _tski_mcu_info_read: 884 884 $DGL 1,206 885 885 00123 C7 push hl ;[INF] 1, 1 886 886 00124 ??bf_tski_mcu_info_read: 887 887 ; line 218 : u8 temp; 888 888 ; line 219 : 889 889 ; line 220 : 890 890 ; line 221 : if( SPD ) 891 891 $DGL 0,5 892 892 00124 C7 push hl ;[INF] 1, 1 893 893 00125 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 894 894 00128 7184 mov1 CY,[hl].0 ;[INF] 2, 1 895 895 0012A C6 pop hl ;[INF] 1, 1 896 896 0012B DC6E bc $?L0046 ;[INF] 2, 4 897 897 ; line 222 : { 898 898 0012D ??bb00_tski_mcu_info_read: 899 899 ; line 223 : goto end; 900 900 0012D ??eb00_tski_mcu_info_read: 901 901 ; line 224 : } 902 902 ; line 225 : 903 903 ; line 226 : if( STD ) 904 904 $DGL 0,10 905 905 0012D C7 push hl ;[INF] 1, 1 906 906 0012E 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 907 907 00131 7194 mov1 CY,[hl].1 ;[INF] 2, 1 908 908 00133 C6 pop hl ;[INF] 1, 1 909 909 00134 61D8 sknc ;[INF] 2, 1 910 910 ; line 227 : { 911 911 00136 ??bb01_tski_mcu_info_read: 912 912 ; line 228 : SPIE = 1; 913 913 $DGL 0,12 914 914 00136 71405005 set1 !IICCTL01.4 ;[INF] 4, 2 915 915 0013A ??eb01_tski_mcu_info_read: 916 916 ; line 229 : } 917 917 0013A ?L0047: 918 918 ; line 230 : 919 919 ; line 231 : if( IICAIF == 0 ) 920 920 $DGL 0,15 921 921 0013A 31B2D103 bt IF2H.3,$?L0049 ;[INF] 4, 5 922 922 ; line 232 : { 923 923 0013E ??bb02_tski_mcu_info_read: 924 924 ; line 233 : return( ERR_CONTINUE ); 925 925 $DGL 0,17 926 926 0013E E7 onew bc ;[INF] 1, 1 927 927 0013F EF69 br $?L0043 ;[INF] 2, 3 928 928 00141 ??eb02_tski_mcu_info_read: 929 929 ; line 234 : } 930 930 00141 ?L0049: 931 931 ; line 235 : else 932 932 ; line 236 : { 933 933 00141 ??bb03_tski_mcu_info_read: 934 934 ; line 237 : IICAIF = 0; 935 935 $DGL 0,21 936 936 00141 713BD1 clr1 IF2H.3 ;[INF] 3, 2 937 937 00144 ??eb03_tski_mcu_info_read: 938 938 ; line 238 : } 939 939 ; line 239 : 940 940 ; line 240 : switch( iic_burst_state++ ){ 941 941 $DGL 0,24 942 942 00144 R8F0000 mov a,!_iic_burst_state ;[INF] 3, 1 943 943 00147 RA00000 inc !_iic_burst_state ;[INF] 3, 2 944 944 0014A 318E shrw ax,8 ;[INF] 2, 1 945 945 0014C E7 onew bc ;[INF] 1, 1 946 946 0014D 240000 subw ax,#00H ; 0 ;[INF] 3, 1 947 947 00150 DD0E bz $?L0052 ;[INF] 2, 4 948 948 00152 23 subw ax,bc ;[INF] 1, 1 949 949 00153 DD13 bz $?L0053 ;[INF] 2, 4 950 950 00155 23 subw ax,bc ;[INF] 1, 1 951 951 00156 DD1E bz $?L0054 ;[INF] 2, 4 952 952 00158 23 subw ax,bc ;[INF] 1, 1 953 953 00159 DD2F bz $?L0055 ;[INF] 2, 4 954 954 0015B 23 subw ax,bc ;[INF] 1, 1 955 955 0015C DD34 bz $?L0056 ;[INF] 2, 4 956 956 0015E EF3B br $?L0046 ;[INF] 2, 3 957 957 00160 ??bb04_tski_mcu_info_read: 958 958 ; line 241 : case( 0 ): // 本体種類識別 959 959 00160 ?L0052: 960 960 ; line 242 : IICA = (u8)system_status.model; 961 961 $DGL 0,26 962 962 00160 R8F0300 mov a,!_system_status+3 ;[INF] 3, 1 963 963 00163 9F4005 mov !IICA1,a ;[INF] 3, 1 964 964 ; line 243 : break; 965 965 $DGL 0,27 966 966 00166 EF30 br $?L0051 ;[INF] 2, 3 967 967 ; line 244 : 968 968 ; line 245 : case( 1 ): // IICがなにかエラーでも知らない。00かFFな 969 969 ; らエラーの可能性が高い 970 970 00168 ?L0053: 971 971 ; line 246 : IICA = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VE 972 972 ; R ); 973 973 $DGL 0,30 974 974 00168 F6 clrw ax ;[INF] 1, 1 975 975 00169 C1 push ax ;[INF] 1, 1 976 976 0016A 5084 mov x,#084H ; 132 ;[INF] 2, 1 977 977 0016C RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 978 978 0016F C0 pop ax ;[INF] 1, 1 979 979 00170 62 mov a,c ;[INF] 1, 1 980 980 00171 9F4005 mov !IICA1,a ;[INF] 3, 1 981 981 ; line 247 : break; 982 982 $DGL 0,31 983 983 00174 EF22 br $?L0051 ;[INF] 2, 3 984 984 ; line 248 : 985 985 ; line 249 : case( 2 ): // 電池メーカーの識別 986 986 00176 ?L0054: 987 987 ; line 250 : BT_DET_P = 1; 988 988 $DGL 0,34 989 989 00176 716201 set1 P1.6 ;[INF] 3, 2 990 990 ; line 251 : IICA = ( u8 ) ( get_adc( ADC_SEL_BATT_DET ) >> 5 ); 991 991 $DGL 0,35 992 992 00179 300900 movw ax,#09H ; 9 ;[INF] 3, 1 993 993 0017C RFD0000 call !_get_adc ;[INF] 3, 3 994 994 0017F 62 mov a,c ;[INF] 1, 1 995 995 00180 315A shr a,5 ;[INF] 2, 1 996 996 00182 9F4005 mov !IICA1,a ;[INF] 3, 1 997 997 ; line 252 : BT_DET_P = 0; 998 998 $DGL 0,36 999 999 00185 716301 clr1 P1.6 ;[INF] 3, 2 1000 1000 ; line 253 : break; 1001 1001 $DGL 0,37 1002 1002 00188 EF0E br $?L0051 ;[INF] 2, 3 1003 1003 ; line 254 : 1004 1004 ; line 255 : case( 3 ): // ガスゲージバージョン 1005 1005 0018A ?L0055: 1006 1006 ; line 256 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R 1007 1007 ; EG_VERSION ); 1008 1008 $DGL 0,40 1009 1009 0018A 300800 movw ax,#08H ; 8 ;[INF] 3, 1 1010 1010 0018D RFD0000 call !bs_F0060 ;[INF] 3, 3 1011 1011 ; line 257 : break; 1012 1012 $DGL 0,41 1013 1013 00190 EF06 br $?L0051 ;[INF] 2, 3 1014 1014 ; line 258 : 1015 1015 ; line 259 : case( 4 ): // LSB 1016 1016 00192 ?L0056: 1017 1017 ; line 260 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R 1018 1018 ; EG_VERSION + 1 ); 1019 1019 $DGL 0,44 1020 1020 00192 300900 movw ax,#09H ; 9 ;[INF] 3, 1 1021 1021 00195 RFD0000 call !bs_F0060 ;[INF] 3, 3 1022 1022 ; line 261 : break; 1023 1023 ; line 262 : 1024 1024 ; line 263 : default: 1025 1025 ; line 264 : goto end; 1026 1026 00198 ??eb04_tski_mcu_info_read: 1027 1027 ; line 265 : } 1028 1028 00198 ?L0051: 1029 1029 ; line 266 : return( ERR_CONTINUE ); 1030 1030 $DGL 0,50 1031 1031 00198 E7 onew bc ;[INF] 1, 1 1032 1032 00199 EF0F br $?L0043 ;[INF] 2, 3 1033 1033 ; line 267 : 1034 1034 ; line 268 : end: 1035 1035 0019B ?L0046: 1036 1036 ; line 269 : LREL = 1; 1037 1037 $DGL 0,53 1038 1038 0019B 71605005 set1 !IICCTL01.6 ;[INF] 4, 2 1039 1039 ; line 270 : SPIE = 0; 1040 1040 $DGL 0,54 1041 1041 0019F 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 1042 1042 ; line 271 : IICAMK = 0; 1043 1043 $DGL 0,55 1044 1044 001A3 713BD5 clr1 MK2H.3 ;[INF] 3, 2 1045 1045 ; line 272 : iic_burst_state = 0; 1046 1046 $DGL 0,56 1047 1047 001A6 RF50000 clrb !_iic_burst_state ;[INF] 3, 1 1048 1048 ; line 273 : return( ERR_FINISED ); 1049 1049 $DGL 0,57 1050 1050 001A9 F7 clrw bc ;[INF] 1, 1 1051 1051 ; line 274 : } 1052 1052 001AA ?L0043: 1053 1053 $DGL 0,58 1054 1054 001AA ??ef_tski_mcu_info_read: 1055 1055 001AA C6 pop hl ;[INF] 1, 1 1056 1056 001AB D7 ret ;[INF] 1, 6 1057 1057 001AC ??ee_tski_mcu_info_read: 1058 1058 1059 1059 ----- @@CODEL CSEG 1060 1060 1061 1061 ----- @@BASE CSEG BASE 1062 1062 END 1063 1063 1064 1064 1065 1065 ; *** Code Information *** 1066 1066 ; 1067 1067 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c 1068 1068 ; 1069 1069 ; $FUNC tsk_misc_stat(55) 1070 1070 ; void=(void) 1071 1071 ; CODE SIZE= 173 bytes, CLOCK_SIZE= 145 clocks, STACK_SIZE= 8 bytes 1072 1072 ; 1073 1073 ; $CALL set_irq(94) 1074 1074 ; void=(int:ax, int:[sp+4]) 1075 1075 ; 1076 1076 ; $CALL set_irq(98) 1077 1077 ; void=(int:ax, int:[sp+4]) 1078 1078 ; 1079 1079 ; $CALL set_irq(107) 1080 1080 ; void=(int:ax, int:[sp+4]) 1081 1081 ; 1082 1082 ; $CALL set_irq(111) 1083 1083 ; void=(int:ax, int:[sp+4]) 1084 1084 ; 1085 1085 ; $CALL renge_task_immed_add(130) 1086 1086 ; bc=(pointer:ax) 1087 1087 ; 1088 1088 ; $CALL renge_task_immed_add(139) 1089 1089 ; bc=(pointer:ax) 1090 1090 ; 1091 1091 ; $FUNC do_command0(159) 1092 1092 ; bc=(void) 1093 1093 ; CODE SIZE= 106 bytes, CLOCK_SIZE= 88 clocks, STACK_SIZE= 8 bytes 1094 1094 ; 1095 1095 ; $CALL iic_mcu_write_a_byte(171) 1096 1096 ; bc=(int:ax, int:[sp+4], int:[sp+6]) 1097 1097 ; 1098 1098 ; $CALL wait_ms(183) 1099 1099 ; void=(int:ax) 1100 1100 ; 1101 1101 ; $CALL iic_mcu_write_a_byte(185) 1102 1102 ; bc=(int:ax, int:[sp+4], int:[sp+6]) 1103 1103 ; 1104 1104 ; $FUNC tski_mcu_info_read(217) 1105 1105 ; bc=(void) 1106 1106 ; CODE SIZE= 137 bytes, CLOCK_SIZE= 149 clocks, STACK_SIZE= 12 bytes 1107 1107 ; 1108 1108 ; $CALL iic_mcu_read_a_byte(246) 1109 1109 ; bc=(int:ax, int:[sp+4]) 1110 1110 ; 1111 1111 ; $CALL get_adc(251) 1112 1112 ; bc=(int:ax) 1113 1113 ; 1114 1114 ; $CALL iic_mcu_read_a_byte(256) 1115 1115 ; bc=(int:ax, int:[sp+4]) 1116 1116 ; 1117 1117 ; $CALL iic_mcu_read_a_byte(260) 1118 1118 ; bc=(int:ax, int:[sp+4]) 1119 1119 1120 1120 ; Target chip : uPD79F0104 1121 1121 ; Device file : E1.00b Segment informations: ADRS LEN NAME 00000 00000H.0 @@BITS 00000 00030H @@CNST 00000 00002H @@R_INIT 00000 00002H @@INIT 00000 00002H @@DATA 00000 00000H @@R_INIS 00000 00000H @@INIS 00000 00000H @@DATS 00000 00000H @@CNSTL 00000 00000H @@RLINIT 00000 00000H @@INITL 00000 00000H @@DATAL 00000 00000H @@CALT 00000 001ACH ROM_CODE 00000 00000H @@CODEL 00000 00000H @@BASE Target chip : uPD79F0104 Device file : E1.00b Assembly complete, 0 error(s) and 0 warning(s) found. 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