78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_debug.asm Para-file: In-file: inter_asm\task_debug.asm Obj-file: task_debug.rel Prn-file: task_debug.prn Assemble list ALNO STNO ADRS OBJECT M I SOURCE STATEMENT 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 2 2 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_debug.c 6 6 ; In-file : task_debug.c 7 7 ; Asm-file : inter_asm\task_debug.asm 8 8 ; Para-file : 9 9 10 10 $PROCESSOR(9F0104) 11 11 $DEBUG 12 12 $NODEBUGA 13 13 $KANJICODE SJIS 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H 15 15 16 16 $DGS FIL_NAM, .file, 05CH, 0FFFEH, 03FH, 067H, 01H, 00H 17 17 $DGS AUX_FIL, task_debug.c 18 18 $DGS MOD_NAM, task_debug, 00H, 0FFFEH, 00H, 077H, 00H, 00H 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 36 36 $DGS AUX_TAG, 01H, 01EH 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 45 45 $DGS AUX_EOS, 013H, 01H 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 47 47 $DGS AUX_TAG, 01H, 025H 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 52 52 $DGS AUX_EOS, 01EH, 01H 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 54 54 $DGS AUX_TAG, 01H, 02FH 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 62 62 $DGS AUX_EOS, 025H, 01H 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H 64 64 $DGS AUX_TAG, 04H, 041H 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H 70 70 $DGS AUX_BIT, 00H, 01H 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H 72 72 $DGS AUX_BIT, 00H, 01H 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H 74 74 $DGS AUX_BIT, 00H, 01H 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H 76 76 $DGS AUX_BIT, 00H, 01H 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H 80 80 $DGS AUX_EOS, 02FH, 04H 81 81 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H 82 82 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H 83 83 $DGS GLV_SYM, _tsk_debug, U, U, 01H, 026H, 01H, 02H 84 84 $DGS AUX_FUN, 00H, U, U, 050H, 00H, 00H 85 85 $DGS BEG_FUN, ??bf_tsk_debug, U, U, 00H, 065H, 01H, 00H 86 86 $DGS AUX_BEG, 010H, 02H, 04AH 87 87 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H 88 88 $DGS STA_SYM, _count, ?L0003, U, 0CH, 03H, 00H, 00H 89 89 $DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H 90 90 $DGS BEG_BLK, ??bb00_tsk_debug, U, U, 00H, 064H, 01H, 00H 91 91 $DGS AUX_BEG, 06H, 00H, 00H 92 92 $DGS END_BLK, ??eb00_tsk_debug, U, U, 00H, 064H, 01H, 00H 93 93 $DGS AUX_END, 015H 94 94 $DGS END_FUN, ??ef_tsk_debug, U, U, 00H, 065H, 01H, 00H 95 95 $DGS AUX_END, 017H 96 96 $DGS GLV_SYM, _tsk_debug2, U, U, 01H, 026H, 01H, 02H 97 97 $DGS AUX_FUN, 00H, U, U, 05CH, 00H, 00H 98 98 $DGS BEG_FUN, ??bf_tsk_debug2, U, U, 00H, 065H, 01H, 00H 99 99 $DGS AUX_BEG, 02BH, 04H, 056H 100 100 $DGS AUT_VAR, _str, 00H, 0FFFFH, 0CH, 01H, 01H, 03H 101 101 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H 102 102 $DGS BEG_BLK, ??bb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H 103 103 $DGS AUX_BEG, 05H, 00H, 00H 104 104 $DGS END_BLK, ??eb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H 105 105 $DGS AUX_END, 01CH 106 106 $DGS END_FUN, ??ef_tsk_debug2, U, U, 00H, 065H, 01H, 00H 107 107 $DGS AUX_END, 01EH 108 108 $DGS GLV_SYM, _temp_debug_3, U, U, 0CH, 026H, 00H, 00H 109 109 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H 110 110 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H 111 111 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H 112 112 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H 113 113 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H 114 114 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 115 115 116 116 EXTRN _system_status 117 117 EXTRN _vreg_ctr 118 118 EXTRN _iic_mcu_write 119 119 PUBLIC _tsk_debug 120 120 PUBLIC _temp_debug_3 121 121 PUBLIC _tsk_debug2 122 122 123 123 ----- @@BITS BSEG 124 124 125 125 ----- @@CNST CSEG MIRRORP 126 126 00000 01 _lpf_coeff: DB 01H ; 1 127 127 00001 02 DB 02H ; 2 128 128 00002 02 DB 02H ; 2 129 129 00003 03 DB 03H ; 3 130 130 00004 03 DB 03H ; 3 131 131 00005 02 DB 02H ; 2 132 132 00006 00 DB 00H ; 0 133 133 00007 FE DB 0FEH ; 254 134 134 00008 FB DB 0FBH ; 251 135 135 00009 F7 DB 0F7H ; 247 136 136 0000A F3 DB 0F3H ; 243 137 137 0000B F0 DB 0F0H ; 240 138 138 0000C F0 DB 0F0H ; 240 139 139 0000D F3 DB 0F3H ; 243 140 140 0000E FA DB 0FAH ; 250 141 141 0000F 04 DB 04H ; 4 142 142 00010 12 DB 012H ; 18 143 143 00011 25 DB 025H ; 37 144 144 00012 38 DB 038H ; 56 145 145 00013 4D DB 04DH ; 77 146 146 00014 5F DB 05FH ; 95 147 147 00015 6E DB 06EH ; 110 148 148 00016 77 DB 077H ; 119 149 149 00017 7A DB 07AH ; 122 150 150 00018 77 DB 077H ; 119 151 151 00019 6E DB 06EH ; 110 152 152 0001A 5F DB 05FH ; 95 153 153 0001B 4D DB 04DH ; 77 154 154 0001C 38 DB 038H ; 56 155 155 0001D 25 DB 025H ; 37 156 156 0001E 12 DB 012H ; 18 157 157 0001F 04 DB 04H ; 4 158 158 00020 FA DB 0FAH ; 250 159 159 00021 F3 DB 0F3H ; 243 160 160 00022 F0 DB 0F0H ; 240 161 161 00023 F0 DB 0F0H ; 240 162 162 00024 F3 DB 0F3H ; 243 163 163 00025 F7 DB 0F7H ; 247 164 164 00026 FB DB 0FBH ; 251 165 165 00027 FE DB 0FEH ; 254 166 166 00028 00 DB 00H ; 0 167 167 00029 02 DB 02H ; 2 168 168 0002A 03 DB 03H ; 3 169 169 0002B 03 DB 03H ; 3 170 170 0002C 02 DB 02H ; 2 171 171 0002D 02 DB 02H ; 2 172 172 0002E 01 DB 01H ; 1 173 173 0002F 00 DB (1) 174 174 175 175 ----- @@R_INIT CSEG UNIT64KP 176 176 00000 00 DB 00H ; 0 177 177 00001 00 DB (1) 178 178 179 179 ----- @@INIT DSEG BASEP 180 180 00000 ?L0003: DS (1) 181 181 00001 DS (1) 182 182 183 183 ----- @@DATA DSEG BASEP 184 184 00000 ?L0004: DS (1) 185 185 00001 _temp_debug_3: DS (1) 186 186 187 187 ----- @@R_INIS CSEG UNIT64KP 188 188 189 189 ----- @@INIS DSEG SADDRP 190 190 191 191 ----- @@DATS DSEG SADDRP 192 192 193 193 ----- @@CNSTL CSEG PAGE64KP 194 194 195 195 ----- @@RLINIT CSEG UNIT64KP 196 196 197 197 ----- @@INITL DSEG UNIT64KP 198 198 199 199 ----- @@DATAL DSEG UNIT64KP 200 200 201 201 ----- @@CALT CSEG CALLT0 202 202 203 203 ; line 1 : #pragma SFR 204 204 ; line 2 : #pragma NOP 205 205 ; line 3 : #pragma HALT 206 206 ; line 4 : #pragma STOP 207 207 ; line 5 : 208 208 ; line 6 : #include "incs.h" 209 209 ; line 7 : #include "renge.h" 210 210 ; line 8 : #include "pm.h" 211 211 ; line 9 : 212 212 ; line 10 : #include "accero.h" 213 213 ; line 11 : 214 214 ; line 12 : 215 215 ; line 13 : /* ======================================================== 216 216 ; line 14 : ======================================================== */ 217 217 ; line 15 : void tsk_debug( ) 218 218 ; line 16 : { 219 219 220 220 ----- ROM_CODE CSEG BASE 221 221 00000 _tsk_debug: 222 222 $DGL 1,67 223 223 00000 C7 push hl ;[INF] 1, 1 224 224 00001 ??bf_tsk_debug: 225 225 ; line 17 : u8 temp; 226 226 ; line 18 : static u8 count = 0; 227 227 ; line 19 : static u8 task_interval; 228 228 ; line 20 : 229 229 ; line 21 : if( system_status.pwr_state == ON_TRIG ){ 230 230 $DGL 0,6 231 231 00001 R40000002 cmp !_system_status,#02H ; 2 ;[INF] 4, 1 232 232 00005 ??bb00_tsk_debug: 233 233 00005 ??eb00_tsk_debug: 234 234 ; line 22 : 235 235 ; line 23 : #ifdef _MODEL_WM0_ 236 236 ; line 24 : PM_CHG_TIMEOUT_DISABLE(); // 237 237 ; /WL_RST に配線されています 238 238 ; line 25 : #endif 239 239 ; line 26 : #ifndef _MODEL_CTR_ 240 240 ; line 27 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 ); // 241 241 ; ACR←0x80 揮発モードへ 242 242 ; line 28 : #endif 243 243 ; line 29 : 244 244 ; line 30 : /* 245 245 ; line 31 : temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_ 246 246 ; DO ); 247 247 ; line 32 : count += 1; 248 248 ; line 33 : iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, co 249 249 ; unt ); 250 250 ; line 34 : iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count ); 251 251 ; line 35 : */ 252 252 ; line 36 : } 253 253 ; line 37 : return; 254 254 ; line 38 : } 255 255 $DGL 0,23 256 256 00005 ??ef_tsk_debug: 257 257 00005 C6 pop hl ;[INF] 1, 1 258 258 00006 D7 ret ;[INF] 1, 6 259 259 00007 ??ee_tsk_debug: 260 260 ; line 39 : 261 261 ; line 40 : u8 temp_debug_3; 262 262 ; line 41 : 263 263 ; line 42 : void tsk_debug2( ) 264 264 ; line 43 : { 265 265 00007 _tsk_debug2: 266 266 $DGL 1,80 267 267 00007 C7 push hl ;[INF] 1, 1 268 268 00008 2004 subw sp,#04H ;[INF] 2, 1 269 269 0000A FBF8FF movw hl,sp ;[INF] 3, 1 270 270 0000D ??bf_tsk_debug2: 271 271 ; line 44 : u8 str[4]; 272 272 ; line 45 : 273 273 ; line 46 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr 274 274 ; _state == SLEEP ) ) 275 275 $DGL 0,4 276 276 0000D R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 277 277 00011 DD06 bz $?L0011 ;[INF] 2, 4 278 278 00013 R40000005 cmp !_system_status,#05H ; 5 ;[INF] 4, 1 279 279 00017 DF21 bnz $?L0009 ;[INF] 2, 4 280 280 00019 ?L0011: 281 281 ; line 47 : { 282 282 00019 ??bb00_tsk_debug2: 283 283 ; line 48 : /* 284 284 ; line 49 : str[3] = vreg_ctr[ VREG_C_FREE0 ]; 285 285 ; line 50 : str[2] = vreg_ctr[ VREG_C_FREE1 ]; 286 286 ; line 51 : str[1] = vreg_ctr[ VREG_C_STATUS ]; 287 287 ; line 52 : str[0] = vreg_ctr[ VREG_C_RTC_SEC ]; 288 288 ; line 53 : */ 289 289 ; line 54 : str[3] = vreg_ctr[ VREG_C_SND_VOL ]; 290 290 $DGL 0,12 291 291 00019 R8F0900 mov a,!_vreg_ctr+9 ;[INF] 3, 1 292 292 0001C 9C03 mov [hl+3],a ; str ;[INF] 2, 1 293 293 ; line 55 : str[2] = vreg_ctr[ VREG_C_TUNE ]; 294 294 $DGL 0,13 295 295 0001E R8F0800 mov a,!_vreg_ctr+8 ;[INF] 3, 1 296 296 00021 9C02 mov [hl+2],a ; str ;[INF] 2, 1 297 297 ; line 56 : str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ]; 298 298 $DGL 0,14 299 299 00023 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 300 300 00026 9C01 mov [hl+1],a ; str ;[INF] 2, 1 301 301 ; line 57 : str[0] = SEC; 302 302 $DGL 0,15 303 303 00028 8E92 mov a,SEC ;[INF] 2, 1 304 304 0002A 9B mov [hl],a ; str ;[INF] 1, 1 305 305 ; line 58 : 306 306 ; line 59 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR 307 307 ; EG_C_IRQ1 ] ); 308 308 ; line 60 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura ); 309 309 ; line 61 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR 310 310 ; EG_C_SND_VOL ] ); 311 311 ; line 62 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR 312 312 ; EG_TUNE ] ); 313 313 ; line 63 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR 314 314 ; EG_C_ACC_ZH ] ); 315 315 ; line 64 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VR 316 316 ; EG_C_TUNE ] ); 317 317 ; line 65 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR 318 318 ; EG_C_SND_VOL ] ); 319 319 ; line 66 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR 320 320 ; EG_C_STATUS ] ); 321 321 ; line 67 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR 322 322 ; EG_C_ACC_ZH ] ); 323 323 ; line 68 : 324 324 ; line 69 : iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] ); 325 325 $DGL 0,27 326 326 0002B 17 movw ax,hl ;[INF] 1, 1 327 327 0002C C1 push ax ;[INF] 1, 1 328 328 0002D 300400 movw ax,#04H ; 4 ;[INF] 3, 1 329 329 00030 C1 push ax ;[INF] 1, 1 330 330 00031 F6 clrw ax ;[INF] 1, 1 331 331 00032 C1 push ax ;[INF] 1, 1 332 332 00033 5044 mov x,#044H ; 68 ;[INF] 2, 1 333 333 00035 RFD0000 call !_iic_mcu_write ;[INF] 3, 3 334 334 00038 1006 addw sp,#06H ; 6 ;[INF] 2, 1 335 335 0003A ??eb00_tsk_debug2: 336 336 ; line 70 : } 337 337 0003A ?L0009: 338 338 ; line 71 : return; 339 339 ; line 72 : } 340 340 $DGL 0,30 341 341 0003A ??ef_tsk_debug2: 342 342 0003A 1004 addw sp,#04H ;[INF] 2, 1 343 343 0003C C6 pop hl ;[INF] 1, 1 344 344 0003D D7 ret ;[INF] 1, 6 345 345 0003E ??ee_tsk_debug2: 346 346 347 347 ----- @@CODEL CSEG 348 348 349 349 ----- @@BASE CSEG BASE 350 350 END 351 351 352 352 353 353 ; *** Code Information *** 354 354 ; 355 355 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c 356 356 ; 357 357 ; $FUNC tsk_debug(16) 358 358 ; void=(void) 359 359 ; CODE SIZE= 7 bytes, CLOCK_SIZE= 9 clocks, STACK_SIZE= 2 bytes 360 360 ; 361 361 ; $FUNC tsk_debug2(43) 362 362 ; void=(void) 363 363 ; CODE SIZE= 55 bytes, CLOCK_SIZE= 40 clocks, STACK_SIZE= 16 bytes 364 364 ; 365 365 ; $CALL iic_mcu_write(69) 366 366 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) 367 367 368 368 ; Target chip : uPD79F0104 369 369 ; Device file : E1.00b Segment informations: ADRS LEN NAME 00000 00000H.0 @@BITS 00000 00030H @@CNST 00000 00002H @@R_INIT 00000 00002H @@INIT 00000 00002H @@DATA 00000 00000H @@R_INIS 00000 00000H @@INIS 00000 00000H @@DATS 00000 00000H @@CNSTL 00000 00000H @@RLINIT 00000 00000H @@INITL 00000 00000H @@DATAL 00000 00000H @@CALT 00000 0003EH ROM_CODE 00000 00000H @@CODEL 00000 00000H @@BASE Target chip : uPD79F0104 Device file : E1.00b Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)