78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\sw.asm Para-file: In-file: inter_asm\sw.asm Obj-file: sw.rel Prn-file: sw.prn Assemble list ALNO STNO ADRS OBJECT M I SOURCE STATEMENT 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 2 2 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no sw.c 6 6 ; In-file : sw.c 7 7 ; Asm-file : inter_asm\sw.asm 8 8 ; Para-file : 9 9 10 10 $PROCESSOR(9F0104) 11 11 $DEBUG 12 12 $NODEBUGA 13 13 $KANJICODE SJIS 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H 15 15 16 16 $DGS FIL_NAM, .file, 0CDH, 0FFFEH, 03FH, 067H, 01H, 00H 17 17 $DGS AUX_FIL, sw.c 18 18 $DGS MOD_NAM, sw, 00H, 0FFFEH, 00H, 077H, 00H, 00H 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 36 36 $DGS AUX_TAG, 01H, 01EH 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 45 45 $DGS AUX_EOS, 013H, 01H 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 47 47 $DGS AUX_TAG, 01H, 025H 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 52 52 $DGS AUX_EOS, 01EH, 01H 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H 54 54 $DGS AUX_TAG, 01H, 02FH 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H 62 62 $DGS AUX_EOS, 025H, 01H 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H 64 64 $DGS AUX_TAG, 04H, 041H 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H 70 70 $DGS AUX_BIT, 00H, 01H 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H 72 72 $DGS AUX_BIT, 00H, 01H 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H 74 74 $DGS AUX_BIT, 00H, 01H 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H 76 76 $DGS AUX_BIT, 00H, 01H 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H 80 80 $DGS AUX_EOS, 02FH, 04H 81 81 $DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H 82 82 $DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H 83 83 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H 84 84 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H 85 85 $DGS GLV_SYM, _tsk_sw, U, U, 01H, 026H, 01H, 02H 86 86 $DGS AUX_FUN, 00H, U, U, 0CDH, 00H, 00H 87 87 $DGS BEG_FUN, ??bf_tsk_sw, U, U, 00H, 065H, 01H, 00H 88 88 $DGS AUX_BEG, 038H, 02H, 04BH 89 89 $DGS STA_SYM, _cnt_force_off, ?L0003, U, 0CH, 03H, 00H, 00H 90 90 $DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H 91 91 $DGS BEG_BLK, ??bb00_tsk_sw, U, U, 00H, 064H, 01H, 00H 92 92 $DGS AUX_BEG, 06H, 00H, 04FH 93 93 $DGS END_BLK, ??eb00_tsk_sw, U, U, 00H, 064H, 01H, 00H 94 94 $DGS AUX_END, 014H 95 95 $DGS BEG_BLK, ??bb01_tsk_sw, U, U, 00H, 064H, 01H, 00H 96 96 $DGS AUX_BEG, 017H, 00H, 053H 97 97 $DGS END_BLK, ??eb01_tsk_sw, U, U, 00H, 064H, 01H, 00H 98 98 $DGS AUX_END, 019H 99 99 $DGS BEG_BLK, ??bb02_tsk_sw, U, U, 00H, 064H, 01H, 00H 100 100 $DGS AUX_BEG, 01BH, 00H, 057H 101 101 $DGS END_BLK, ??eb02_tsk_sw, U, U, 00H, 064H, 01H, 00H 102 102 $DGS AUX_END, 01DH 103 103 $DGS BEG_BLK, ??bb03_tsk_sw, U, U, 00H, 064H, 01H, 00H 104 104 $DGS AUX_BEG, 021H, 00H, 059H 105 105 $DGS BEG_BLK, ??bb04_tsk_sw, U, U, 00H, 064H, 01H, 00H 106 106 $DGS AUX_BEG, 028H, 00H, 05BH 107 107 $DGS BEG_BLK, ??bb05_tsk_sw, U, U, 00H, 064H, 01H, 00H 108 108 $DGS AUX_BEG, 02AH, 00H, 061H 109 109 $DGS END_BLK, ??eb05_tsk_sw, U, U, 00H, 064H, 01H, 00H 110 110 $DGS AUX_END, 030H 111 111 $DGS END_BLK, ??eb04_tsk_sw, U, U, 00H, 064H, 01H, 00H 112 112 $DGS AUX_END, 031H 113 113 $DGS BEG_BLK, ??bb06_tsk_sw, U, U, 00H, 064H, 01H, 00H 114 114 $DGS AUX_BEG, 033H, 00H, 065H 115 115 $DGS END_BLK, ??eb06_tsk_sw, U, U, 00H, 064H, 01H, 00H 116 116 $DGS AUX_END, 039H 117 117 $DGS BEG_BLK, ??bb07_tsk_sw, U, U, 00H, 064H, 01H, 00H 118 118 $DGS AUX_BEG, 03BH, 00H, 069H 119 119 $DGS END_BLK, ??eb07_tsk_sw, U, U, 00H, 064H, 01H, 00H 120 120 $DGS AUX_END, 03FH 121 121 $DGS BEG_BLK, ??bb08_tsk_sw, U, U, 00H, 064H, 01H, 00H 122 122 $DGS AUX_BEG, 043H, 00H, 06BH 123 123 $DGS BEG_BLK, ??bb09_tsk_sw, U, U, 00H, 064H, 01H, 00H 124 124 $DGS AUX_BEG, 046H, 00H, 071H 125 125 $DGS END_BLK, ??eb09_tsk_sw, U, U, 00H, 064H, 01H, 00H 126 126 $DGS AUX_END, 04AH 127 127 $DGS END_BLK, ??eb08_tsk_sw, U, U, 00H, 064H, 01H, 00H 128 128 $DGS AUX_END, 04BH 129 129 $DGS BEG_BLK, ??bb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H 130 130 $DGS AUX_BEG, 04DH, 00H, 075H 131 131 $DGS END_BLK, ??eb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H 132 132 $DGS AUX_END, 04FH 133 133 $DGS BEG_BLK, ??bb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H 134 134 $DGS AUX_BEG, 053H, 00H, 079H 135 135 $DGS END_BLK, ??eb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H 136 136 $DGS AUX_END, 05FH 137 137 $DGS BEG_BLK, ??bb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H 138 138 $DGS AUX_BEG, 062H, 00H, 07BH 139 139 $DGS BEG_BLK, ??bb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H 140 140 $DGS AUX_BEG, 064H, 00H, 081H 141 141 $DGS END_BLK, ??eb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H 142 142 $DGS AUX_END, 066H 143 143 $DGS END_BLK, ??eb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H 144 144 $DGS AUX_END, 067H 145 145 $DGS BEG_BLK, ??bb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H 146 146 $DGS AUX_BEG, 069H, 00H, 085H 147 147 $DGS END_BLK, ??eb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H 148 148 $DGS AUX_END, 06BH 149 149 $DGS BEG_BLK, ??bb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H 150 150 $DGS AUX_BEG, 06FH, 00H, 08BH 151 151 $DGS END_BLK, ??eb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H 152 152 $DGS AUX_END, 071H 153 153 $DGS END_BLK, ??eb03_tsk_sw, U, U, 00H, 064H, 01H, 00H 154 154 $DGS AUX_END, 074H 155 155 $DGS BEG_BLK, ??bb10_tsk_sw, U, U, 00H, 064H, 01H, 00H 156 156 $DGS AUX_BEG, 07DH, 00H, 08DH 157 157 $DGS BEG_BLK, ??bb11_tsk_sw, U, U, 00H, 064H, 01H, 00H 158 158 $DGS AUX_BEG, 07EH, 00H, 08FH 159 159 $DGS BEG_BLK, ??bb12_tsk_sw, U, U, 00H, 064H, 01H, 00H 160 160 $DGS AUX_BEG, 07EH, 00H, 093H 161 161 $DGS END_BLK, ??eb12_tsk_sw, U, U, 00H, 064H, 01H, 00H 162 162 $DGS AUX_END, 07EH 163 163 $DGS BEG_BLK, ??bb13_tsk_sw, U, U, 00H, 064H, 01H, 00H 164 164 $DGS AUX_BEG, 07EH, 00H, 095H 165 165 $DGS BEG_BLK, ??bb14_tsk_sw, U, U, 00H, 064H, 01H, 00H 166 166 $DGS AUX_BEG, 07EH, 00H, 099H 167 167 $DGS END_BLK, ??eb14_tsk_sw, U, U, 00H, 064H, 01H, 00H 168 168 $DGS AUX_END, 07EH 169 169 $DGS BEG_BLK, ??bb15_tsk_sw, U, U, 00H, 064H, 01H, 00H 170 170 $DGS AUX_BEG, 07EH, 00H, 0A1H 171 171 $DGS END_BLK, ??eb15_tsk_sw, U, U, 00H, 064H, 01H, 00H 172 172 $DGS AUX_END, 07EH 173 173 $DGS END_BLK, ??eb13_tsk_sw, U, U, 00H, 064H, 01H, 00H 174 174 $DGS AUX_END, 07EH 175 175 $DGS END_BLK, ??eb11_tsk_sw, U, U, 00H, 064H, 01H, 00H 176 176 $DGS AUX_END, 07EH 177 177 $DGS BEG_BLK, ??bb16_tsk_sw, U, U, 00H, 064H, 01H, 00H 178 178 $DGS AUX_BEG, 080H, 00H, 0A3H 179 179 $DGS BEG_BLK, ??bb17_tsk_sw, U, U, 00H, 064H, 01H, 00H 180 180 $DGS AUX_BEG, 080H, 00H, 0A7H 181 181 $DGS END_BLK, ??eb17_tsk_sw, U, U, 00H, 064H, 01H, 00H 182 182 $DGS AUX_END, 080H 183 183 $DGS BEG_BLK, ??bb18_tsk_sw, U, U, 00H, 064H, 01H, 00H 184 184 $DGS AUX_BEG, 080H, 00H, 0A9H 185 185 $DGS BEG_BLK, ??bb19_tsk_sw, U, U, 00H, 064H, 01H, 00H 186 186 $DGS AUX_BEG, 080H, 00H, 0ADH 187 187 $DGS END_BLK, ??eb19_tsk_sw, U, U, 00H, 064H, 01H, 00H 188 188 $DGS AUX_END, 080H 189 189 $DGS BEG_BLK, ??bb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H 190 190 $DGS AUX_BEG, 080H, 00H, 0B5H 191 191 $DGS END_BLK, ??eb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H 192 192 $DGS AUX_END, 080H 193 193 $DGS END_BLK, ??eb18_tsk_sw, U, U, 00H, 064H, 01H, 00H 194 194 $DGS AUX_END, 080H 195 195 $DGS END_BLK, ??eb16_tsk_sw, U, U, 00H, 064H, 01H, 00H 196 196 $DGS AUX_END, 080H 197 197 $DGS BEG_BLK, ??bb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H 198 198 $DGS AUX_BEG, 082H, 00H, 0B7H 199 199 $DGS BEG_BLK, ??bb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H 200 200 $DGS AUX_BEG, 082H, 00H, 0BBH 201 201 $DGS END_BLK, ??eb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H 202 202 $DGS AUX_END, 082H 203 203 $DGS BEG_BLK, ??bb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H 204 204 $DGS AUX_BEG, 082H, 00H, 0BDH 205 205 $DGS BEG_BLK, ??bb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H 206 206 $DGS AUX_BEG, 082H, 00H, 0C1H 207 207 $DGS END_BLK, ??eb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H 208 208 $DGS AUX_END, 082H 209 209 $DGS BEG_BLK, ??bb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H 210 210 $DGS AUX_BEG, 082H, 00H, 00H 211 211 $DGS END_BLK, ??eb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H 212 212 $DGS AUX_END, 082H 213 213 $DGS END_BLK, ??eb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H 214 214 $DGS AUX_END, 082H 215 215 $DGS END_BLK, ??eb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H 216 216 $DGS AUX_END, 082H 217 217 $DGS END_BLK, ??eb10_tsk_sw, U, U, 00H, 064H, 01H, 00H 218 218 $DGS AUX_END, 083H 219 219 $DGS END_FUN, ??ef_tsk_sw, U, U, 00H, 065H, 01H, 00H 220 220 $DGS AUX_END, 086H 221 221 $DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 026H, 00H, 00H 222 222 $DGS GLV_SYM, _SW_home_count, U, U, 0CH, 026H, 00H, 00H 223 223 $DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 026H, 00H, 00H 224 224 $DGS GLV_SYM, _SW_pow_mask, U, U, 034CH, 027H, 00H, 00H 225 225 $DGS GLV_SYM, _SW_home_mask, U, U, 034CH, 027H, 00H, 00H 226 226 $DGS GLV_SYM, _SW_wifi_mask, U, U, 034CH, 027H, 00H, 00H 227 227 $DGS GLV_SYM, _SW_HOME_n, U, U, 034CH, 027H, 00H, 00H 228 228 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H 229 229 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H 230 230 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H 231 231 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H 232 232 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H 233 233 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H 234 234 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H 235 235 236 236 EXTRN _set_irq 237 237 EXTRN _system_status 238 238 EXTRN _vreg_ctr 239 239 EXTBIT _renge_task_interval_run_force 240 240 PUBLIC _SW_pow_count 241 241 PUBLIC _SW_home_count 242 242 PUBLIC _SW_wifi_count 243 243 PUBLIC _SW_pow_mask 244 244 PUBLIC _SW_home_mask 245 245 PUBLIC _SW_wifi_mask 246 246 PUBLIC _SW_HOME_n 247 247 PUBLIC _tsk_sw 248 248 249 249 ----- @@BITS BSEG 250 250 00000.0 _SW_pow_mask DBIT 251 251 00000.1 _SW_home_mask DBIT 252 252 00000.2 _SW_wifi_mask DBIT 253 253 00000.3 _SW_HOME_n DBIT 254 254 255 255 ----- @@CNST CSEG MIRRORP 256 256 00000 01 _lpf_coeff: DB 01H ; 1 257 257 00001 02 DB 02H ; 2 258 258 00002 02 DB 02H ; 2 259 259 00003 03 DB 03H ; 3 260 260 00004 03 DB 03H ; 3 261 261 00005 02 DB 02H ; 2 262 262 00006 00 DB 00H ; 0 263 263 00007 FE DB 0FEH ; 254 264 264 00008 FB DB 0FBH ; 251 265 265 00009 F7 DB 0F7H ; 247 266 266 0000A F3 DB 0F3H ; 243 267 267 0000B F0 DB 0F0H ; 240 268 268 0000C F0 DB 0F0H ; 240 269 269 0000D F3 DB 0F3H ; 243 270 270 0000E FA DB 0FAH ; 250 271 271 0000F 04 DB 04H ; 4 272 272 00010 12 DB 012H ; 18 273 273 00011 25 DB 025H ; 37 274 274 00012 38 DB 038H ; 56 275 275 00013 4D DB 04DH ; 77 276 276 00014 5F DB 05FH ; 95 277 277 00015 6E DB 06EH ; 110 278 278 00016 77 DB 077H ; 119 279 279 00017 7A DB 07AH ; 122 280 280 00018 77 DB 077H ; 119 281 281 00019 6E DB 06EH ; 110 282 282 0001A 5F DB 05FH ; 95 283 283 0001B 4D DB 04DH ; 77 284 284 0001C 38 DB 038H ; 56 285 285 0001D 25 DB 025H ; 37 286 286 0001E 12 DB 012H ; 18 287 287 0001F 04 DB 04H ; 4 288 288 00020 FA DB 0FAH ; 250 289 289 00021 F3 DB 0F3H ; 243 290 290 00022 F0 DB 0F0H ; 240 291 291 00023 F0 DB 0F0H ; 240 292 292 00024 F3 DB 0F3H ; 243 293 293 00025 F7 DB 0F7H ; 247 294 294 00026 FB DB 0FBH ; 251 295 295 00027 FE DB 0FEH ; 254 296 296 00028 00 DB 00H ; 0 297 297 00029 02 DB 02H ; 2 298 298 0002A 03 DB 03H ; 3 299 299 0002B 03 DB 03H ; 3 300 300 0002C 02 DB 02H ; 2 301 301 0002D 02 DB 02H ; 2 302 302 0002E 01 DB 01H ; 1 303 303 0002F 00 DB (1) 304 304 305 305 ----- @@R_INIT CSEG UNIT64KP 306 306 00000 00 DB 00H ; 0 307 307 00001 00 DB 00H ; 0 308 308 309 309 ----- @@INIT DSEG BASEP 310 310 00000 ?L0003: DS (1) 311 311 00001 ?L0004: DS (1) 312 312 313 313 ----- @@DATA DSEG BASEP 314 314 00000 _SW_pow_count: DS (1) 315 315 00001 _SW_home_count: DS (1) 316 316 00002 _SW_wifi_count: DS (1) 317 317 00003 DS (1) 318 318 319 319 ----- @@R_INIS CSEG UNIT64KP 320 320 321 321 ----- @@INIS DSEG SADDRP 322 322 323 323 ----- @@DATS DSEG SADDRP 324 324 325 325 ----- @@CNSTL CSEG PAGE64KP 326 326 327 327 ----- @@RLINIT CSEG UNIT64KP 328 328 329 329 ----- @@INITL DSEG UNIT64KP 330 330 331 331 ----- @@DATAL DSEG UNIT64KP 332 332 333 333 ----- @@CALT CSEG CALLT0 334 334 335 335 ; Sub-Routines created by CC78K0R 336 336 337 337 ----- ROM_CODE CSEG BASE 338 338 00000 bs_F0060: 339 339 00000 C1 push ax ;[INF] 1, 1 340 340 00001 5010 mov x,#010H ; 16 ;[INF] 2, 1 341 341 00003 RFD0000 call !_set_irq ;[INF] 3, 3 342 342 00006 C0 pop ax ;[INF] 1, 1 343 343 00007 D7 ret ;[INF] 1, 6 344 344 00008 es_F0060: 345 345 346 346 ; *** Sub-Routine Information *** 347 347 ; 348 348 ; $SUB bs_F0060 349 349 ; CODE SIZE= 8 bytes 350 350 351 351 ; End of Sub-Routines 352 352 353 353 ; line 1 : #pragma SFR 354 354 ; line 2 : #pragma NOP 355 355 ; line 3 : #pragma HALT 356 356 ; line 4 : #pragma STOP 357 357 ; line 5 : 358 358 ; line 6 : #include "incs.h" 359 359 ; line 7 : 360 360 ; line 8 : #include "i2c_twl.h" 361 361 ; line 9 : #include "i2c_ctr.h" 362 362 ; line 10 : #include "led.h" 363 363 ; line 11 : #include "accero.h" 364 364 ; line 12 : #include "pm.h" 365 365 ; line 13 : #include "rtc.h" 366 366 ; line 14 : 367 367 ; line 15 : 368 368 ; line 16 : 369 369 ; line 17 : //========================================================= 370 370 ; line 18 : #define INTERVAL_TSK_SW 16 371 371 ; line 19 : #define CLICK_THRESHOLD 1 372 372 ; line 20 : #define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW ) 373 373 ; line 21 : 374 374 ; line 22 : 375 375 ; line 23 : 376 376 ; line 24 : //========================================================= 377 377 ; line 25 : u8 SW_pow_count, SW_home_count, SW_wifi_count; 378 378 ; line 26 : bit SW_pow_mask, SW_home_mask, SW_wifi_mask; 379 379 ; line 27 : 380 380 ; line 28 : bit SW_HOME_n; 381 381 ; line 29 : 382 382 ; line 30 : 383 383 ; line 31 : //========================================================= 384 384 ; line 32 : // 押した時間を数える。押しっぱなしでも0に戻らない 385 385 ; line 33 : // maskが非0の時は、一度離すまで無視する 386 386 ; line 34 : #define count_sw_n( sw, counter, mask ) \ 387 387 ; line 35 : { \ 388 388 ; line 36 : if( sw ){ \ 389 389 ; line 37 : mask = 0; \ 390 390 ; line 38 : counter = 0; \ 391 391 ; line 39 : }else{ \ 392 392 ; line 40 : if( mask != 0 ){ \ 393 393 ; line 41 : counter = 0; \ 394 394 ; line 42 : }else{ \ 395 395 ; line 43 : counter += 1; \ 396 396 ; line 44 : if( counter == 0 ) counter = 255; \ 397 397 ; line 45 : } \ 398 398 ; line 46 : } \ 399 399 ; line 47 : } 400 400 ; line 48 : 401 401 ; line 49 : 402 402 ; line 50 : 403 403 ; line 51 : /* ======================================================== 404 404 ; line 52 : スイッチの監視 405 405 ; line 53 : 　チャタリングをはねたり、長押しや、押したトリガなどの検出など 406 406 ; line 54 : ======================================================== */ 407 407 ; line 55 : void tsk_sw( ) 408 408 ; line 56 : { 409 409 410 410 ----- ROM_CODE CSEG BASE 411 411 00008 _tsk_sw: 412 412 $DGL 1,69 413 413 00008 C7 push hl ;[INF] 1, 1 414 414 00009 ??bf_tsk_sw: 415 415 ; line 57 : static u8 cnt_force_off = 0; 416 416 ; line 58 : static u8 task_interval = 0; 417 417 ; line 59 : 418 418 ; line 60 : switch ( system_status.pwr_state ) 419 419 $DGL 0,5 420 420 00009 R8F0000 mov a,!_system_status ;[INF] 3, 1 421 421 0000C 318F sarw ax,8 ;[INF] 2, 1 422 422 0000E F7 clrw bc ;[INF] 1, 1 423 423 0000F 23 subw ax,bc ;[INF] 1, 1 424 424 00010 DD07 bz $?L0006 ;[INF] 2, 4 425 425 00012 240200 subw ax,#02H ; 2 ;[INF] 3, 1 426 426 00015 DD10 bz $?L0007 ;[INF] 2, 4 427 427 00017 EF17 br $?L0005 ;[INF] 2, 3 428 428 ; line 61 : { 429 429 00019 ??bb00_tsk_sw: 430 430 ; line 62 : case ( OFF_TRIG ): 431 431 00019 ?L0006: 432 432 ; line 63 : SW_pow_count = 0; 433 433 $DGL 0,8 434 434 00019 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 435 435 ; line 64 : SW_wifi_count = 0; 436 436 $DGL 0,9 437 437 0001C RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 438 438 ; line 65 : SW_home_count = 0; 439 439 $DGL 0,10 440 440 0001F RF50100 clrb !_SW_home_count ;[INF] 3, 1 441 441 ; line 66 : cnt_force_off = 0; 442 442 $DGL 0,11 443 443 00022 RF50000 clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 444 444 ; line 67 : break; 445 445 $DGL 0,12 446 446 00025 EF09 br $?L0005 ;[INF] 2, 3 447 447 ; line 68 : 448 448 ; line 69 : case ( ON_TRIG ): 449 449 00027 ?L0007: 450 450 ; line 70 : // 電源投入 451 451 ; line 71 : SW_pow_mask = 1; 452 452 $DGL 0,16 453 453 00027 R710200 set1 _SW_pow_mask ;[INF] 3, 2 454 454 ; line 72 : SW_home_mask = 1; 455 455 $DGL 0,17 456 456 0002A R711200 set1 _SW_home_mask ;[INF] 3, 2 457 457 ; line 73 : SW_wifi_mask = 1; 458 458 $DGL 0,18 459 459 0002D R712200 set1 _SW_wifi_mask ;[INF] 3, 2 460 460 ; line 74 : break; 461 461 00030 ??eb00_tsk_sw: 462 462 ; line 75 : } 463 463 00030 ?L0005: 464 464 ; line 76 : 465 465 ; line 77 : if( task_interval-- != 0 ) 466 466 $DGL 0,22 467 467 00030 R8F0100 mov a,!?L0004 ; task_interval ;[INF] 3, 1 468 468 00033 RB00100 dec !?L0004 ; task_interval ;[INF] 3, 2 469 469 00036 D1 cmp0 a ;[INF] 1, 1 470 470 00037 61E8 skz ;[INF] 2, 1 471 471 00039 RED6501 br !?L0058 ;[INF] 3, 3 472 472 ; line 78 : { 473 473 0003C ??bb01_tsk_sw: 474 474 ; line 79 : return; 475 475 0003C ??eb01_tsk_sw: 476 476 ; line 80 : } 477 477 ; line 81 : else 478 478 ; line 82 : { 479 479 0003C ??bb02_tsk_sw: 480 480 ; line 83 : task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TIC 481 481 ; K ); 482 482 $DGL 0,28 483 483 0003C RCF010008 mov !?L0004,#08H ; task_interval,8 ;[INF] 4, 1 484 484 00040 ??eb02_tsk_sw: 485 485 ; line 84 : } 486 486 ; line 85 : 487 487 ; line 86 : 488 488 ; line 87 : switch ( system_status.pwr_state ) 489 489 $DGL 0,32 490 490 00040 R8F0000 mov a,!_system_status ;[INF] 3, 1 491 491 00043 318F sarw ax,8 ;[INF] 2, 1 492 492 00045 E7 onew bc ;[INF] 1, 1 493 493 00046 340200 movw de,#02H ; 2 ;[INF] 3, 1 494 494 00049 23 subw ax,bc ;[INF] 1, 1 495 495 0004A DD0A bz $?L0013 ;[INF] 2, 4 496 496 0004C 25 subw ax,de ;[INF] 1, 1 497 497 0004D DD07 bz $?L0013 ;[INF] 2, 4 498 498 0004F 25 subw ax,de ;[INF] 1, 1 499 499 00050 23 subw ax,bc ;[INF] 1, 1 500 500 00051 61F3 sknh ;[INF] 2, 1 501 501 00053 RED0201 br !?L0012 ;[INF] 3, 3 502 502 ; line 88 : { 503 503 00056 ??bb03_tsk_sw: 504 504 ; line 89 : case ( ON ): 505 505 00056 ?L0013: 506 506 ; line 90 : case ( SLEEP ): 507 507 ; line 91 : case ( BT_CHARGE ): 508 508 ; line 92 : case ( OFF ): 509 509 ; line 93 : // 電源スイッチの監視 // 510 510 ; line 94 : if( SW_POW_n ) 511 511 $DGL 0,39 512 512 00056 31340712 bf P7.3,$?L0016 ;[INF] 4, 5 513 513 ; line 95 : { 514 514 0005A ??bb04_tsk_sw: 515 515 ; line 96 : if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_c 516 516 ; ount <= HOLD_THREASHOLD ) ) 517 517 $DGL 0,41 518 518 0005A R40000002 cmp !_SW_pow_count,#02H ; 2 ;[INF] 4, 1 519 519 0005E DC29 bc $?L0022 ;[INF] 2, 4 520 520 00060 R40000026 cmp !_SW_pow_count,#026H ; 38 ;[INF] 4, 1 521 521 00064 DE23 bnc $?L0022 ;[INF] 2, 4 522 522 ; line 97 : { 523 523 00066 ??bb05_tsk_sw: 524 524 ; line 98 : #ifdef _SW_HOME_ENABLE_ 525 525 ; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK ); 526 526 $DGL 0,44 527 527 00066 E6 onew ax ;[INF] 1, 1 528 528 00067 RFD0000 call !bs_F0060 ;[INF] 3, 3 529 529 0006A ??eb05_tsk_sw: 530 530 ; line 100 : #else 531 531 ; line 101 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); 532 532 ; line 102 : #endif 533 533 ; line 103 : } 534 534 ; line 104 : } 535 535 $DGL 0,49 536 536 0006A ??eb04_tsk_sw: 537 537 0006A EF1D br $?L0022 ;[INF] 2, 3 538 538 0006C ?L0016: 539 539 ; line 105 : else if( SW_pow_count == HOLD_THREASHOLD ) 540 540 $DGL 0,50 541 541 0006C R40000025 cmp !_SW_pow_count,#025H ; 37 ;[INF] 4, 1 542 542 00070 DF07 bnz $?L0020 ;[INF] 2, 4 543 543 ; line 106 : { 544 544 00072 ??bb06_tsk_sw: 545 545 ; line 107 : #ifdef _SW_HOME_ENABLE_ 546 546 ; line 108 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD ); 547 547 $DGL 0,53 548 548 00072 E6 onew ax ;[INF] 1, 1 549 549 00073 A1 incw ax ;[INF] 1, 1 550 550 00074 RFD0000 call !bs_F0060 ;[INF] 3, 3 551 551 00077 ??eb06_tsk_sw: 552 552 ; line 109 : #else 553 553 ; line 110 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); 554 554 ; line 111 : #endif 555 555 ; line 112 : } 556 556 $DGL 0,57 557 557 00077 EF10 br $?L0022 ;[INF] 2, 3 558 558 00079 ?L0020: 559 559 ; line 113 : else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) ) 560 560 $DGL 0,58 561 561 00079 R40000094 cmp !_SW_pow_count,#094H ; 148 ;[INF] 4, 1 562 562 0007D DF0A bnz $?L0022 ;[INF] 2, 4 563 563 ; line 114 : { // todo 564 564 0007F ??bb07_tsk_sw: 565 565 ; line 115 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED; 566 566 $DGL 0,60 567 567 0007F RCF290004 mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 568 568 ; line 116 : system_status.pwr_state = OFF_TRIG; 569 569 $DGL 0,61 570 570 00083 RF50000 clrb !_system_status ;[INF] 3, 1 571 571 ; line 117 : renge_task_interval_run_force = 1; 572 572 $DGL 0,62 573 573 00086 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 574 574 00089 ??eb07_tsk_sw: 575 575 ; line 118 : } 576 576 00089 ?L0022: 577 577 ; line 119 : 578 578 ; line 120 : // 電源OFF割り込みを入れたが… 579 579 ; line 121 : if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0 580 580 ; ) 581 581 $DGL 0,66 582 582 00089 R8F1000 mov a,!_vreg_ctr+16 ;[INF] 3, 1 583 583 0008C 5C02 and a,#02H ; 2 ;[INF] 2, 1 584 584 0008E D1 cmp0 a ;[INF] 1, 1 585 585 0008F DD15 bz $?L0024 ;[INF] 2, 4 586 586 ; line 122 : { 587 587 00091 ??bb08_tsk_sw: 588 588 ; line 123 : cnt_force_off += 1; 589 589 $DGL 0,68 590 590 00091 RA00000 inc !?L0003 ; cnt_force_off ;[INF] 3, 2 591 591 ; line 124 : if( cnt_force_off >= 13 ) 592 592 $DGL 0,69 593 593 00094 R4000000D cmp !?L0003,#0DH ; cnt_force_off,13 ;[INF] 4, 1 594 594 00098 DC0F bc $?L0025 ;[INF] 2, 4 595 595 ; line 125 : { // …返事がない。強制的に切る。 596 596 0009A ??bb09_tsk_sw: 597 597 ; line 126 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RE 598 598 ; D; 599 599 $DGL 0,71 600 600 0009A RCF290004 mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 601 601 ; line 127 : system_status.pwr_state = OFF_TRIG; 602 602 $DGL 0,72 603 603 0009E RF50000 clrb !_system_status ;[INF] 3, 1 604 604 ; line 128 : renge_task_interval_run_force = 1; 605 605 $DGL 0,73 606 606 000A1 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 607 607 000A4 ??eb09_tsk_sw: 608 608 ; line 129 : } 609 609 ; line 130 : } 610 610 $DGL 0,75 611 611 000A4 ??eb08_tsk_sw: 612 612 000A4 EF03 br $?L0025 ;[INF] 2, 3 613 613 000A6 ?L0024: 614 614 ; line 131 : else 615 615 ; line 132 : { 616 616 000A6 ??bb0A_tsk_sw: 617 617 ; line 133 : cnt_force_off = 0; 618 618 $DGL 0,78 619 619 000A6 RF50000 clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 620 620 000A9 ??eb0A_tsk_sw: 621 621 ; line 134 : } 622 622 000A9 ?L0025: 623 623 ; line 135 : 624 624 ; line 136 : // HOME スイッチ // 625 625 ; line 137 : switch( system_status.model ) 626 626 $DGL 0,82 627 627 000A9 R8F0300 mov a,!_system_status+3 ;[INF] 3, 1 628 628 000AC 318F sarw ax,8 ;[INF] 2, 1 629 629 000AE E7 onew bc ;[INF] 1, 1 630 630 000AF 240000 subw ax,#00H ; 0 ;[INF] 3, 1 631 631 000B2 DD07 bz $?L0029 ;[INF] 2, 4 632 632 000B4 B1 decw ax ;[INF] 1, 1 633 633 000B5 23 subw ax,bc ;[INF] 1, 1 634 634 000B6 61D30C bnh $?L0030 ;[INF] 3, 4 635 635 000B9 EF12 br $?L0031 ;[INF] 2, 3 636 636 ; line 138 : { 637 637 000BB ??bb0B_tsk_sw: 638 638 ; line 139 : #ifdef _MODEL_CTR_ 639 639 ; line 140 : case( MODEL_JIKKI ): 640 640 000BB ?L0029: 641 641 ; line 141 : SW_HOME_n = SW_HOME_n_JIKKI; 642 642 $DGL 0,86 643 643 000BB 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 644 644 000BE 71C4 mov1 CY,[hl].4 ;[INF] 2, 1 645 645 000C0 R713100 mov1 _SW_HOME_n,CY ;[INF] 3, 2 646 646 ; line 142 : break; 647 647 $DGL 0,87 648 648 000C3 EF0B br $?L0028 ;[INF] 2, 3 649 649 ; line 143 : #endif 650 650 ; line 144 : case( MODEL_TS_BOARD ): 651 651 000C5 ?L0030: 652 652 ; line 145 : case( MODEL_SHIROBAKO ): 653 653 ; line 146 : SW_HOME_n = SW_HOME_n_TSBOARD; 654 654 $DGL 0,91 655 655 000C5 710402 mov1 CY,P2.0 ;[INF] 3, 1 656 656 000C8 R713100 mov1 _SW_HOME_n,CY ;[INF] 3, 2 657 657 ; line 147 : break; 658 658 $DGL 0,92 659 659 000CB EF03 br $?L0028 ;[INF] 2, 3 660 660 ; line 148 : default: 661 661 000CD ?L0031: 662 662 ; line 149 : SW_HOME_n = 1; 663 663 $DGL 0,94 664 664 000CD R713200 set1 _SW_HOME_n ;[INF] 3, 2 665 665 000D0 ??eb0B_tsk_sw: 666 666 ; line 150 : } 667 667 000D0 ?L0028: 668 668 ; line 151 : 669 669 ; line 152 : if( SW_HOME_n ) 670 670 $DGL 0,97 671 671 000D0 R31340014 bf _SW_HOME_n,$?L0034 ;[INF] 4, 5 672 672 ; line 153 : { 673 673 000D4 ??bb0C_tsk_sw: 674 674 ; line 154 : if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home 675 675 ; _count <= HOLD_THREASHOLD ) ) 676 676 $DGL 0,99 677 677 000D4 R40010002 cmp !_SW_home_count,#02H ; 2 ;[INF] 4, 1 678 678 000D8 DC1A bc $?L0038 ;[INF] 2, 4 679 679 000DA R40010026 cmp !_SW_home_count,#026H ; 38 ;[INF] 4, 1 680 680 000DE DE14 bnc $?L0038 ;[INF] 2, 4 681 681 ; line 155 : { 682 682 000E0 ??bb0D_tsk_sw: 683 683 ; line 156 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); 684 684 $DGL 0,101 685 685 000E0 300400 movw ax,#04H ; 4 ;[INF] 3, 1 686 686 000E3 RFD0000 call !bs_F0060 ;[INF] 3, 3 687 687 000E6 ??eb0D_tsk_sw: 688 688 ; line 157 : } 689 689 ; line 158 : } 690 690 $DGL 0,103 691 691 000E6 ??eb0C_tsk_sw: 692 692 000E6 EF0C br $?L0038 ;[INF] 2, 3 693 693 000E8 ?L0034: 694 694 ; line 159 : else if( SW_home_count == HOLD_THREASHOLD ) 695 695 $DGL 0,104 696 696 000E8 R40010025 cmp !_SW_home_count,#025H ; 37 ;[INF] 4, 1 697 697 000EC DF06 bnz $?L0038 ;[INF] 2, 4 698 698 ; line 160 : { 699 699 000EE ??bb0E_tsk_sw: 700 700 ; line 161 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); 701 701 $DGL 0,106 702 702 000EE 300800 movw ax,#08H ; 8 ;[INF] 3, 1 703 703 000F1 RFD0000 call !bs_F0060 ;[INF] 3, 3 704 704 000F4 ??eb0E_tsk_sw: 705 705 ; line 162 : } 706 706 000F4 ?L0038: 707 707 ; line 163 : 708 708 ; line 164 : // wifi sw // 709 709 ; line 165 : if( SW_wifi_count == CLICK_THRESHOLD ) 710 710 $DGL 0,110 711 711 000F4 R40020001 cmp !_SW_wifi_count,#01H ; 1 ;[INF] 4, 1 712 712 000F8 DF08 bnz $?L0012 ;[INF] 2, 4 713 713 ; line 166 : { 714 714 000FA ??bb0F_tsk_sw: 715 715 ; line 167 : set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK ); 716 716 $DGL 0,112 717 717 000FA 301000 movw ax,#010H ; 16 ;[INF] 3, 1 718 718 000FD C1 push ax ;[INF] 1, 1 719 719 000FE RFD0000 call !_set_irq ;[INF] 3, 3 720 720 00101 C0 pop ax ;[INF] 1, 1 721 721 00102 ??eb0F_tsk_sw: 722 722 ; line 168 : } 723 723 ; line 169 : 724 724 ; line 170 : break; 725 725 00102 ??eb03_tsk_sw: 726 726 ; line 171 : } 727 727 00102 ?L0012: 728 728 ; line 172 : 729 729 ; line 173 : // ボタン押し時間のカウント 730 730 ; line 174 : /* 731 731 ; line 175 : if( ( system_status.pwr_state == ON ) 732 732 ; line 176 : || ( system_status.pwr_state == OFF ) 733 733 ; line 177 : || ( system_status.pwr_state == BT_CHARGE ) ) 734 734 ; line 178 : */ 735 735 ; line 179 : 736 736 ; line 180 : { 737 737 00102 ??bb10_tsk_sw: 738 738 ; line 181 : count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask ); 739 739 $DGL 0,126 740 740 00102 ??bb11_tsk_sw: 741 741 00102 31340708 bf P7.3,$?L0042 ;[INF] 4, 5 742 742 00106 ??bb12_tsk_sw: 743 743 00106 R710300 clr1 _SW_pow_mask ;[INF] 3, 2 744 744 00109 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 745 745 0010C ??eb12_tsk_sw: 746 746 0010C EF15 br $?L0046 ;[INF] 2, 3 747 747 0010E ?L0042: 748 748 0010E ??bb13_tsk_sw: 749 749 0010E R31040005 bf _SW_pow_mask,$?L0044 ;[INF] 4, 5 750 750 00112 ??bb14_tsk_sw: 751 751 00112 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 752 752 00115 ??eb14_tsk_sw: 753 753 00115 EF0C br $?L0046 ;[INF] 2, 3 754 754 00117 ?L0044: 755 755 00117 ??bb15_tsk_sw: 756 756 00117 RA00000 inc !_SW_pow_count ;[INF] 3, 2 757 757 0011A RD50000 cmp0 !_SW_pow_count ;[INF] 3, 1 758 758 0011D 61F8 sknz ;[INF] 2, 1 759 759 0011F RCF0000FF mov !_SW_pow_count,#0FFH ; 255 ;[INF] 4, 1 760 760 00123 ?L0046: 761 761 00123 ??eb15_tsk_sw: 762 762 00123 ??eb13_tsk_sw: 763 763 00123 ??eb11_tsk_sw: 764 764 ; line 182 : #ifdef _SW_HOME_ENABLE_ 765 765 ; line 183 : count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask ); 766 766 $DGL 0,128 767 767 00123 ??bb16_tsk_sw: 768 768 00123 R31340008 bf _SW_HOME_n,$?L0048 ;[INF] 4, 5 769 769 00127 ??bb17_tsk_sw: 770 770 00127 R711300 clr1 _SW_home_mask ;[INF] 3, 2 771 771 0012A RF50100 clrb !_SW_home_count ;[INF] 3, 1 772 772 0012D ??eb17_tsk_sw: 773 773 0012D EF15 br $?L0052 ;[INF] 2, 3 774 774 0012F ?L0048: 775 775 0012F ??bb18_tsk_sw: 776 776 0012F R31140005 bf _SW_home_mask,$?L0050 ;[INF] 4, 5 777 777 00133 ??bb19_tsk_sw: 778 778 00133 RF50100 clrb !_SW_home_count ;[INF] 3, 1 779 779 00136 ??eb19_tsk_sw: 780 780 00136 EF0C br $?L0052 ;[INF] 2, 3 781 781 00138 ?L0050: 782 782 00138 ??bb1A_tsk_sw: 783 783 00138 RA00100 inc !_SW_home_count ;[INF] 3, 2 784 784 0013B RD50100 cmp0 !_SW_home_count ;[INF] 3, 1 785 785 0013E 61F8 sknz ;[INF] 2, 1 786 786 00140 RCF0100FF mov !_SW_home_count,#0FFH ; 255 ;[INF] 4, 1 787 787 00144 ?L0052: 788 788 00144 ??eb1A_tsk_sw: 789 789 00144 ??eb18_tsk_sw: 790 790 00144 ??eb16_tsk_sw: 791 791 ; line 184 : #endif 792 792 ; line 185 : count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask ); 793 793 $DGL 0,130 794 794 00144 ??bb1B_tsk_sw: 795 795 00144 31440708 bf P7.4,$?L0054 ;[INF] 4, 5 796 796 00148 ??bb1C_tsk_sw: 797 797 00148 R712300 clr1 _SW_wifi_mask ;[INF] 3, 2 798 798 0014B RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 799 799 0014E ??eb1C_tsk_sw: 800 800 0014E EF15 br $?L0058 ;[INF] 2, 3 801 801 00150 ?L0054: 802 802 00150 ??bb1D_tsk_sw: 803 803 00150 R31240005 bf _SW_wifi_mask,$?L0056 ;[INF] 4, 5 804 804 00154 ??bb1E_tsk_sw: 805 805 00154 RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 806 806 00157 ??eb1E_tsk_sw: 807 807 00157 EF0C br $?L0058 ;[INF] 2, 3 808 808 00159 ?L0056: 809 809 00159 ??bb1F_tsk_sw: 810 810 00159 RA00200 inc !_SW_wifi_count ;[INF] 3, 2 811 811 0015C RD50200 cmp0 !_SW_wifi_count ;[INF] 3, 1 812 812 0015F 61F8 sknz ;[INF] 2, 1 813 813 00161 RCF0200FF mov !_SW_wifi_count,#0FFH ; 255 ;[INF] 4, 1 814 814 00165 ?L0058: 815 815 00165 ??eb1F_tsk_sw: 816 816 00165 ??eb1D_tsk_sw: 817 817 00165 ??eb1B_tsk_sw: 818 818 00165 ??eb10_tsk_sw: 819 819 ; line 186 : } 820 820 ; line 187 : 821 821 ; line 188 : return; 822 822 ; line 189 : } 823 823 $DGL 0,134 824 824 00165 ??ef_tsk_sw: 825 825 00165 C6 pop hl ;[INF] 1, 1 826 826 00166 D7 ret ;[INF] 1, 6 827 827 00167 ??ee_tsk_sw: 828 828 829 829 ----- @@CODEL CSEG 830 830 831 831 ----- @@BASE CSEG BASE 832 832 END 833 833 834 834 835 835 ; *** Code Information *** 836 836 ; 837 837 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c 838 838 ; 839 839 ; $FUNC tsk_sw(56) 840 840 ; void=(void) 841 841 ; CODE SIZE= 351 bytes, CLOCK_SIZE= 329 clocks, STACK_SIZE= 12 bytes 842 842 ; 843 843 ; $CALL set_irq(99) 844 844 ; void=(int:ax, int:[sp+4]) 845 845 ; 846 846 ; $CALL set_irq(108) 847 847 ; void=(int:ax, int:[sp+4]) 848 848 ; 849 849 ; $CALL set_irq(156) 850 850 ; void=(int:ax, int:[sp+4]) 851 851 ; 852 852 ; $CALL set_irq(161) 853 853 ; void=(int:ax, int:[sp+4]) 854 854 ; 855 855 ; $CALL set_irq(167) 856 856 ; void=(int:ax, int:[sp+4]) 857 857 858 858 ; Target chip : uPD79F0104 859 859 ; Device file : E1.00b Segment informations: ADRS LEN NAME 00000 00000H.4 @@BITS 00000 00030H @@CNST 00000 00002H @@R_INIT 00000 00002H @@INIT 00000 00004H @@DATA 00000 00000H @@R_INIS 00000 00000H @@INIS 00000 00000H @@DATS 00000 00000H @@CNSTL 00000 00000H @@RLINIT 00000 00000H @@INITL 00000 00000H @@DATAL 00000 00000H @@CALT 00000 00167H ROM_CODE 00000 00000H @@CODEL 00000 00000H @@BASE Target chip : uPD79F0104 Device file : E1.00b Assembly complete, 0 error(s) and 0 warning(s) found. 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