; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24

; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c
; In-file   : vreg_twl.c
; Asm-file  : inter_asm\vreg_twl.asm
; Para-file : 

$PROCESSOR(9F0104)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF	03FH, 0210H, 02H, 00H, 00H, 00H, 00H

$DGS	FIL_NAM, .file,		062H,	0FFFEH,	03FH,	067H,	01H,	00H
$DGS	AUX_FIL, vreg_twl.c
$DGS	MOD_NAM, vreg_twl,	00H,	0FFFEH,	00H,	077H,	00H,	00H
$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
$DGS	LAB_SYM, bs_S0051,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_S0051,	U,	U,	00H,	06H,	00H,	00H
$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
$DGS	STA_SYM, _tasks,	U,	U,	01H,	03H,	01H,	027H
$DGS	AUX_STR, 00H,		00H,	016H,	0BH,	00H,	00H,	00H,	04H
$DGS	GLV_SYM, _vreg_twl_init,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	01FH,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_twl_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 019H,		00H,	01FH
$DGS	END_FUN, ??ef_vreg_twl_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 03H
$DGS	GLV_SYM, _vreg_twl_write,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	033H,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_twl_write,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 023H,		02H,	025H
$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	REG_PAR, _data,		07H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	BEG_BLK, ??bb00_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 03H,		00H,	027H
$DGS	BEG_BLK, ??bb01_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 05H,		00H,	02BH
$DGS	END_BLK, ??eb01_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 08H
$DGS	BEG_BLK, ??bb02_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 027H,		00H,	00H
$DGS	END_BLK, ??eb02_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02AH
$DGS	END_BLK, ??eb00_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02BH
$DGS	END_FUN, ??ef_vreg_twl_write,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 02DH
$DGS	GLV_SYM, _vreg_twl_read,	U,	U,	0CH,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	057H,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_twl_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 059H,		02H,	039H
$DGS	REG_PAR, _phy_adrs,	06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	REG_VAR, _temp,		07H,	0FFFFH,	010CH,	04H,	00H,	00H
$DGS	BEG_BLK, ??bb00_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 04H,		00H,	03BH
$DGS	BEG_BLK, ??bb01_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 09H,		00H,	03FH
$DGS	END_BLK, ??eb01_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0BH
$DGS	BEG_BLK, ??bb02_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0BH,		00H,	043H
$DGS	END_BLK, ??eb02_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0DH
$DGS	BEG_BLK, ??bb03_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0DH,		00H,	047H
$DGS	END_BLK, ??eb03_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0FH
$DGS	BEG_BLK, ??bb04_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0FH,		00H,	04BH
$DGS	END_BLK, ??eb04_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	BEG_BLK, ??bb05_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 011H,		00H,	04FH
$DGS	END_BLK, ??eb05_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 013H
$DGS	BEG_BLK, ??bb06_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 013H,		00H,	00H
$DGS	END_BLK, ??eb06_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 015H
$DGS	END_BLK, ??eb00_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 023H
$DGS	END_FUN, ??ef_vreg_twl_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 024H
$DGS	GLV_SYM, _adrs_table_twl_ext2int,	U,	U,	0CH,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	062H,	00H,	00H
$DGS	BEG_FUN, ??bf_adrs_table_twl_ext2int,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 084H,		02H,	05CH
$DGS	REG_PAR, _img,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	BEG_BLK, ??bb00_adrs_table_twl_ext2int,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02H,		00H,	00H
$DGS	END_BLK, ??eb00_adrs_table_twl_ext2int,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0EH
$DGS	END_FUN, ??ef_adrs_table_twl_ext2int,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 0FH
$DGS	GLV_SYM, _vreg_twl,	U,	U,	0CH,	026H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	0FH,	0FH,	00H,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_sw,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_adc,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_batt,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_led_pow,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_led_wifi,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_led_notify,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_led_cam,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_misc_stat,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_debug,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_debug2,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tsk_sys,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _set_irq,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H

	EXTRN	_tsk_sw
	EXTRN	_tsk_adc
	EXTRN	_tsk_batt
	EXTRN	_tsk_led_pow
	EXTRN	_tsk_led_wifi
	EXTRN	_tsk_led_notify
	EXTRN	_tsk_led_cam
	EXTRN	_tsk_misc_stat
	EXTRN	_tsk_debug
	EXTRN	_tsk_debug2
	EXTRN	_tsk_sys
	EXTRN	_set_irq
	EXTRN	_vreg_ctr
	PUBLIC	_vreg_twl
	PUBLIC	_vreg_twl_init
	PUBLIC	_vreg_twl_write
	PUBLIC	_vreg_twl_read
	PUBLIC	_adrs_table_twl_ext2int

@@BITS	BSEG

@@CNST	CSEG	MIRRORP
_lpf_coeff:	DB	01H	; 1
	DB	02H	; 2
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	00H	; 0
	DB	0FEH	; 254
	DB	0FBH	; 251
	DB	0F7H	; 247
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0FAH	; 250
	DB	04H	; 4
	DB	012H	; 18
	DB	025H	; 37
	DB	038H	; 56
	DB	04DH	; 77
	DB	05FH	; 95
	DB	06EH	; 110
	DB	077H	; 119
	DB	07AH	; 122
	DB	077H	; 119
	DB	06EH	; 110
	DB	05FH	; 95
	DB	04DH	; 77
	DB	038H	; 56
	DB	025H	; 37
	DB	012H	; 18
	DB	04H	; 4
	DB	0FAH	; 250
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0F7H	; 247
	DB	0FBH	; 251
	DB	0FEH	; 254
	DB	00H	; 0
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	02H	; 2
	DB	01H	; 1
	DB	(1)

@@R_INIT	CSEG	UNIT64KP
	DW	loww (_tsk_sw)
	DW	loww (_tsk_adc)
	DW	loww (_tsk_batt)
	DW	loww (_tsk_led_pow)
	DW	loww (_tsk_led_wifi)
	DW	loww (_tsk_led_notify)
	DW	loww (_tsk_led_cam)
	DW	loww (_tsk_misc_stat)
	DW	loww (_tsk_debug)
	DW	loww (_tsk_debug2)
	DW	loww (_tsk_sys)

@@INIT	DSEG	BASEP
_tasks:	DS	(22)

@@DATA	DSEG	BASEP
_vreg_twl:	DS	(15)
	DS	(1)

@@R_INIS	CSEG	UNIT64KP

@@INIS	DSEG	SADDRP

@@DATS	DSEG	SADDRP

@@CNSTL	CSEG	PAGE64KP

@@RLINIT	CSEG	UNIT64KP

@@INITL	DSEG	UNIT64KP

@@DATAL	DSEG	UNIT64KP

@@CALT	CSEG	CALLT0

; Sub-Routines created by CC78K0R

ROM_CODE	CSEG	BASE
bs_S0051:
	mov	a,h						;[INF] 1, 1
	and	a,#03H	; 3 					;[INF] 2, 1
	mov	c,a						;[INF] 1, 1
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,c						;[INF] 1, 1
	mov	_vreg_twl[b],a					;[INF] 3, 1
	ret							;[INF] 1, 6
es_S0051:

; *** Sub-Routine Information ***
;
; $SUB bs_S0051
;      CODE SIZE= 11 bytes

; End of Sub-Routines

; line     1 : /* ========================================================
; line     2 : 
; line     3 : TWL互換側のI2Cレジスタ
; line     4 : 
; line     5 :  ======================================================== */
; line     6 : #include "incs.h"
; line     7 : #include "jhl_defs.h"
; line     8 : #include "vreg_twl.h"
; line     9 : 
; line    10 : #include "vreg_ctr.h"
; line    11 : #include "renge\renge_task_intval.h"
; line    12 : 
; line    13 : // ========================================================
; line    14 : #define TWL_REG_VER_INFO               0x35
; line    15 : #define NON_EXIST_REG                  0xFF
; line    16 : 
; line    17 : // ========================================================
; line    18 : u8      vreg_twl[_REG_TWL_INT_ADRS_ENDMARK];
; line    19 : 
; line    20 : 
; line    21 : /* ========================================================
; line    22 :   仮想レジスタの初期化
; line    23 :  ======================================================== */
; line    24 : void vreg_twl_init(  )
; line    25 : {

ROM_CODE	CSEG	BASE
_vreg_twl_init:
$DGL	1,25
??bf_vreg_twl_init:
; line    26 :     vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03;
$DGL	0,2
	mov	!_vreg_twl+3,#03H	; 3 			;[INF] 4, 1
; line    27 : }
$DGL	0,3
??ef_vreg_twl_init:
	ret							;[INF] 1, 6
??ee_vreg_twl_init:
; line    28 : 
; line    29 : 
; line    30 : // ========================================================
; line    31 : // I2C仮想レジスタに書く・何かアクションする
; line    32 : //　引数 adrs は内部アドレス
; line    33 : //  　存在しないアドレスにアクセスした場合、何もしません。
; line    34 : void vreg_twl_write( u8 adrs, u8 data )
; line    35 : {
_vreg_twl_write:
$DGL	1,31
	push	hl						;[INF] 1, 1
	mov	a,[sp+6]					;[INF] 2, 1
	movw	hl,ax						;[INF] 1, 1
??bf_vreg_twl_write:
; line    36 :     switch ( adrs )
$DGL	0,2
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	onew	bc						;[INF] 1, 1
	movw	de,#02H	; 2 					;[INF] 3, 1
	subw	ax,de						;[INF] 1, 1
	bz	$?L0010						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0007						;[INF] 2, 4
	subw	ax,de						;[INF] 1, 1
	bz	$?L0008						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0006						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0009						;[INF] 2, 4
	br	$?L0013						;[INF] 2, 3
; line    37 :     {
??bb00_vreg_twl_write:
; line    38 :       case ( REG_TWL_INT_ADRS_VOL ):
?L0006:
; line    39 :         {
??bb01_vreg_twl_write:
; line    40 :             set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE );
$DGL	0,6
	movw	ax,#040H	; 64 				;[INF] 3, 1
	push	ax						;[INF] 1, 1
	mov	x,#012H	; 18 					;[INF] 2, 1
	call	!_set_irq					;[INF] 3, 3
	pop	ax						;[INF] 1, 1
; line    41 :             break;
$DGL	0,7
	br	$?L0013						;[INF] 2, 3
??eb01_vreg_twl_write:
; line    42 :         }
; line    43 : 
; line    44 :       case ( REG_TWL_INT_ADRS_MODE ):
?L0007:
; line    45 :         vreg_twl[adrs] = ( data & 0x03 );
$DGL	0,11
	call	!bs_S0051					;[INF] 3, 3
; line    46 :         break;
$DGL	0,12
	br	$?L0013						;[INF] 2, 3
; line    47 : 
; line    48 :       case ( REG_TWL_INT_ADRS_CAM ):
?L0008:
; line    49 :         vreg_twl[adrs] = ( data & 0x03 );
$DGL	0,15
	call	!bs_S0051					;[INF] 3, 3
; line    50 :         tsk_led_cam();  // todo 大丈夫？
$DGL	0,16
	call	!_tsk_led_cam					;[INF] 3, 3
; line    51 :         break;
$DGL	0,17
	br	$?L0013						;[INF] 2, 3
; line    52 : 
; line    53 :       case ( REG_TWL_INT_ADRS_TEMP0 ):
?L0009:
; line    54 :         vreg_twl[adrs] = data;
$DGL	0,20
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,h						;[INF] 1, 1
	mov	_vreg_twl[b],a					;[INF] 3, 1
; line    55 :         break;
$DGL	0,21
	br	$?L0013						;[INF] 2, 3
; line    56 : 
; line    57 :       case ( REG_TWL_INT_ADRS_COMMAND ):
?L0010:
; line    58 : /*
; line    59 :         if( data <= 2 ){
; line    60 :             if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 )
; line    61 :             {
; line    62 :                 set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );    
;                // OFFも実装していたらしい。
; line    63 :                 break;
; line    64 :             }
; line    65 :             else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 )
; line    66 :             {
; line    67 :                 set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );  
;                  //リセットしかない。他のは、SPIから来ます。
; line    68 :                 break;
; line    69 :             }
; line    70 :           }
; line    71 : */
; line    72 :         if( data == REG_BIT_TWL_RESET_REQ )
$DGL	0,38
	mov	a,h						;[INF] 1, 1
	dec	a						;[INF] 1, 1
	bnz	$?L0013						;[INF] 2, 4
; line    73 :         {
??bb02_vreg_twl_write:
; line    74 :             set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );      
;              //リセットしかない。他のは、SPIから来ます。
$DGL	0,40
	onew	ax						;[INF] 1, 1
	push	ax						;[INF] 1, 1
	mov	x,#012H	; 18 					;[INF] 2, 1
	call	!_set_irq					;[INF] 3, 3
	pop	ax						;[INF] 1, 1
; line    75 :             break;
??eb02_vreg_twl_write:
; line    76 :         }
?L0013:
??eb00_vreg_twl_write:
; line    77 :     }
; line    78 :     return;
; line    79 : }
$DGL	0,45
??ef_vreg_twl_write:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_vreg_twl_write:
; line    80 : 
; line    81 : 
; line    82 : 
; line    83 : // ========================================================
; line    84 : // I2C仮想レジスタから読みます。
; line    85 : //　引数 adrs 外から見たときの、アドレス
; line    86 : //　戻り   xx データ
; line    87 : //  　存在しないアドレスにアクセスした場合、戻り値は0x5A
; line    88 : u8 vreg_twl_read( u8 phy_adrs )
; line    89 : {
_vreg_twl_read:
$DGL	1,51
	push	hl						;[INF] 1, 1
	movw	hl,ax						;[INF] 1, 1
??bf_vreg_twl_read:
; line    90 :     u8 temp;
; line    91 : 
; line    92 :     switch( phy_adrs ){
$DGL	0,4
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	onew	bc						;[INF] 1, 1
	subw	ax,#00H	; 0 					;[INF] 3, 1
	bz	$?L0018						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0020						;[INF] 2, 4
	subw	ax,#03H	; 3 					;[INF] 3, 1
	bz	$?L0019						;[INF] 2, 4
	subw	ax,#0FBH	; 251 				;[INF] 3, 1
	bz	$?L0022						;[INF] 2, 4
	br	$?L0021						;[INF] 2, 3
??bb00_vreg_twl_read:
; line    93 :       case( REG_TWL_INT_ADRS_VER_INFO ):
?L0018:
; line    94 :           return( TWL_REG_VER_INFO );
$DGL	0,6
	movw	bc,#035H	; 53 				;[INF] 3, 1
	br	$?L0017						;[INF] 2, 3
; line    95 : 
; line    96 :       case( REG_TWL_INT_ADRS_POWER_INFO ):
?L0019:
; line    97 :           if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){
$DGL	0,9
	cmp	!_vreg_ctr+11,#05BH	; 91 			;[INF] 4, 1
	bc	$?L0025						;[INF] 2, 4
??bb01_vreg_twl_read:
; line    98 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F;
$DGL	0,10
	mov	!_vreg_twl+4,#0FH	; 15 			;[INF] 4, 1
??eb01_vreg_twl_read:
; line    99 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){
$DGL	0,11
	br	$?L0034						;[INF] 2, 3
?L0025:
	cmp	!_vreg_ctr+11,#04CH	; 76 			;[INF] 4, 1
	bc	$?L0027						;[INF] 2, 4
??bb02_vreg_twl_read:
; line   100 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B;
$DGL	0,12
	mov	!_vreg_twl+4,#0BH	; 11 			;[INF] 4, 1
??eb02_vreg_twl_read:
; line   101 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){
$DGL	0,13
	br	$?L0034						;[INF] 2, 3
?L0027:
	cmp	!_vreg_ctr+11,#033H	; 51 			;[INF] 4, 1
	bc	$?L0029						;[INF] 2, 4
??bb03_vreg_twl_read:
; line   102 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07;
$DGL	0,14
	mov	!_vreg_twl+4,#07H	; 7 			;[INF] 4, 1
??eb03_vreg_twl_read:
; line   103 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){
$DGL	0,15
	br	$?L0034						;[INF] 2, 3
?L0029:
	cmp	!_vreg_ctr+11,#01AH	; 26 			;[INF] 4, 1
	bc	$?L0031						;[INF] 2, 4
??bb04_vreg_twl_read:
; line   104 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03;
$DGL	0,16
	mov	!_vreg_twl+4,#03H	; 3 			;[INF] 4, 1
??eb04_vreg_twl_read:
; line   105 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] >  5 ){
$DGL	0,17
	br	$?L0034						;[INF] 2, 3
?L0031:
	cmp	!_vreg_ctr+11,#06H	; 6 			;[INF] 4, 1
	bc	$?L0033						;[INF] 2, 4
??bb05_vreg_twl_read:
; line   106 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01;
$DGL	0,18
	oneb	!_vreg_twl+4					;[INF] 3, 1
??eb05_vreg_twl_read:
; line   107 :           }else{
$DGL	0,19
	br	$?L0034						;[INF] 2, 3
?L0033:
??bb06_vreg_twl_read:
; line   108 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00;
$DGL	0,20
	clrb	!_vreg_twl+4					;[INF] 3, 1
??eb06_vreg_twl_read:
; line   109 :           }
?L0034:
; line   110 : 
; line   111 :           return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !B
;              T_CHG_n ? 0x80: 0x00 ) );  // アダプタbit
$DGL	0,23
	bt	P5.1,$?L0035					;[INF] 4, 5
	movw	ax,#080H	; 128 				;[INF] 3, 1
	br	$?L0036						;[INF] 2, 3
?L0035:
	clrw	ax						;[INF] 1, 1
?L0036:
	xch	a,x						;[INF] 1, 1
	or	a,!_vreg_twl+4					;[INF] 3, 1
	xch	a,x						;[INF] 1, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0017						;[INF] 2, 3
; line   112 : 
; line   113 :       case( REG_TWL_INT_ADRS_IRQ ):
?L0020:
; line   114 :           temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ];
$DGL	0,26
	mov	a,!_vreg_twl+1					;[INF] 3, 1
; line   115 :           vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;
$DGL	0,27
	clrb	!_vreg_twl+1					;[INF] 3, 1
; line   116 :           return( temp );
$DGL	0,28
	shrw	ax,8						;[INF] 2, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0017						;[INF] 2, 3
; line   117 : 
; line   118 :       default:
?L0021:
; line   119 :           return( vreg_twl[ phy_adrs ] );
$DGL	0,31
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,_vreg_twl[b]					;[INF] 3, 1
	shrw	ax,8						;[INF] 2, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0017						;[INF] 2, 3
; line   120 : 
; line   121 :       case( REG_TWL_ADRS_NON_EXIST ):
?L0022:
; line   122 :           return( 0x00 );
$DGL	0,34
	clrw	bc						;[INF] 1, 1
??eb00_vreg_twl_read:
; line   123 :     }
?L0017:
; line   124 : }
$DGL	0,36
??ef_vreg_twl_read:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_vreg_twl_read:
; line   125 : 
; line   126 : 
; line   127 : 
; line   128 : // ========================================================
; line   129 : // 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える
; line   130 : // 0xFFは存在しないアドレス。
; line   131 : u8 adrs_table_twl_ext2int( u8 img )
; line   132 : {
_adrs_table_twl_ext2int:
$DGL	1,87
	push	hl						;[INF] 1, 1
	movw	hl,ax						;[INF] 1, 1
??bf_adrs_table_twl_ext2int:
; line   133 :     switch( img ){
$DGL	0,2
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	onew	bc						;[INF] 1, 1
	subw	ax,#00H	; 0 					;[INF] 3, 1
	bz	$?L0046						;[INF] 2, 4
	subw	ax,#010H	; 16 				;[INF] 3, 1
	bz	$?L0040						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0041						;[INF] 2, 4
	subw	ax,bc						;[INF] 1, 1
	bz	$?L0047						;[INF] 2, 4
	subw	ax,#0EH	; 14 					;[INF] 3, 1
	bz	$?L0042						;[INF] 2, 4
	subw	ax,#011H	; 17 				;[INF] 3, 1
	bz	$?L0043						;[INF] 2, 4
	subw	ax,#0FH	; 15 					;[INF] 3, 1
	bz	$?L0044						;[INF] 2, 4
	subw	ax,#030H	; 48 				;[INF] 3, 1
	bz	$?L0045						;[INF] 2, 4
	br	$?L0048						;[INF] 2, 3
??bb00_adrs_table_twl_ext2int:
; line   134 :       case( REG_TWL_ADRS_IRQ ):        return( REG_TWL_INT_ADRS_
;              IRQ );
$DGL	0,3
?L0040:
	onew	bc						;[INF] 1, 1
	br	$?L0039						;[INF] 2, 3
; line   135 :       case( REG_TWL_ADRS_COMMAND ):    return( REG_TWL_INT_ADRS_
;              COMMAND );
$DGL	0,4
?L0041:
	onew	bc						;[INF] 1, 1
	incw	bc						;[INF] 1, 1
	br	$?L0039						;[INF] 2, 3
; line   136 :       case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_
;              POWER_INFO );
$DGL	0,5
?L0042:
	movw	bc,#04H	; 4 					;[INF] 3, 1
	br	$?L0039						;[INF] 2, 3
; line   137 :       case( REG_TWL_ADRS_CAM ):        return( REG_TWL_INT_ADRS_
;              CAM );
$DGL	0,6
?L0043:
	movw	bc,#05H	; 5 					;[INF] 3, 1
	br	$?L0039						;[INF] 2, 3
; line   138 :       case( REG_TWL_ADRS_VOL ):        return( REG_TWL_INT_ADRS_
;              VOL );
$DGL	0,7
?L0044:
	movw	bc,#06H	; 6 					;[INF] 3, 1
	br	$?L0039						;[INF] 2, 3
; line   139 :       case( REG_TWL_ADRS_TEMP0 ):      return( REG_TWL_INT_ADRS_
;              TEMP0 );
$DGL	0,8
?L0045:
	movw	bc,#07H	; 7 					;[INF] 3, 1
	br	$?L0039						;[INF] 2, 3
; line   140 :       case( REG_TWL_ADRS_VER_INFO ):   return( REG_TWL_INT_ADRS_
;              VER_INFO );
$DGL	0,9
?L0046:
	clrw	bc						;[INF] 1, 1
	br	$?L0039						;[INF] 2, 3
; line   141 :       case( REG_TWL_ADRS_MODE ):       return( REG_TWL_INT_ADRS_
;              MODE );
$DGL	0,10
?L0047:
	movw	bc,#03H	; 3 					;[INF] 3, 1
	br	$?L0039						;[INF] 2, 3
; line   142 :       default:                         return( REG_TWL_ADRS_NON_
;              EXIST );
$DGL	0,11
?L0048:
	clrw	bc						;[INF] 1, 1
	dec	c						;[INF] 1, 1
??eb00_adrs_table_twl_ext2int:
; line   143 : //      0が読めればよい、書けなくて良い
; line   144 : //      case( REG_TWL_ADRS_WIFI ):       return( REG_TWL_INT_ADR
;              S_WIFI );
; line   145 :     }
?L0039:
; line   146 : }
$DGL	0,15
??ef_adrs_table_twl_ext2int:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_adrs_table_twl_ext2int:

@@CODEL	CSEG

@@BASE	CSEG	BASE
	END


; *** Code Information ***
;
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c
;
; $FUNC vreg_twl_init(25)
;	void=(void)
;	CODE SIZE= 5 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
;
; $FUNC vreg_twl_write(35)
;	void=(unsigned char adrs:x, unsigned char data:[sp+6])
;	CODE SIZE= 74 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 8 bytes
;
; $CALL set_irq(40)
;	void=(int:ax, int:[sp+4])
;
; $CALL tsk_led_cam(50)
;	void=(void)
;
; $CALL set_irq(74)
;	void=(int:ax, int:[sp+4])
;
; $FUNC vreg_twl_read(89)
;	bc=(unsigned char phy_adrs:x)
;	CODE SIZE= 134 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 2 bytes
;
; $FUNC adrs_table_twl_ext2int(132)
;	bc=(unsigned char img:x)
;	CODE SIZE= 82 bytes, CLOCK_SIZE= 90 clocks, STACK_SIZE= 2 bytes

; Target chip : uPD79F0104
; Device file : E1.00b