78K0R Assembler W1.31 Date:13 May 2010 Page: 1 Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\ini_VECT.asm Para-file: In-file: inter_asm\ini_VECT.asm Obj-file: ini_VECT.rel Prn-file: ini_VECT.prn Assemble list ALNO STNO ADRS OBJECT M I SOURCE STATEMENT 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 May 2010 Time:20:03:34 2 2 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no ini_VECT.c 6 6 ; In-file : ini_VECT.c 7 7 ; Asm-file : inter_asm\ini_VECT.asm 8 8 ; Para-file : 9 9 10 10 $PROCESSOR(9F0104) 11 11 $DEBUG 12 12 $NODEBUGA 13 13 $KANJICODE SJIS 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H 15 15 16 16 $DGS FIL_NAM, .file, 0115H, 0FFFEH, 03FH, 067H, 01H, 00H 17 17 $DGS AUX_FIL, ini_VECT.c 18 18 $DGS MOD_NAM, ini_VECT, 00H, 0FFFEH, 00H, 077H, 00H, 00H 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H 32 32 $DGS SEC_NAM, @@CODE, U, U, 00H, 078H, 00H, 00H 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H 35 35 $DGS SEC_NAM, @@VECT10, U, U, 00H, 078H, 00H, 00H 36 36 $DGS SEC_NAM, @@VECT1C, U, U, 00H, 078H, 00H, 00H 37 37 $DGS SEC_NAM, @@VECT24, U, U, 00H, 078H, 00H, 00H 38 38 $DGS SEC_NAM, @@VECT2A, U, U, 00H, 078H, 00H, 00H 39 39 $DGS SEC_NAM, @@VECT34, U, U, 00H, 078H, 00H, 00H 40 40 $DGS SEC_NAM, @@VECT4A, U, U, 00H, 078H, 00H, 00H 41 41 $DGS SEC_NAM, @@VECT5A, U, U, 00H, 078H, 00H, 00H 42 42 $DGS SEC_NAM, @@VECT62, U, U, 00H, 078H, 00H, 00H 43 43 $DGS GLV_SYM, _fn_intwdti, U, U, 0E001H, 026H, 01H, 02H 44 44 $DGS AUX_FUN, 00H, U, U, 025H, 00H, 00H 45 45 $DGS BEG_FUN, ??bf_fn_intwdti, U, U, 00H, 065H, 01H, 00H 46 46 $DGS AUX_BEG, 04BH, 00H, 01FH 47 47 $DGS BEG_BLK, ??bb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H 48 48 $DGS AUX_BEG, 03H, 00H, 00H 49 49 $DGS END_BLK, ??eb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H 50 50 $DGS AUX_END, 05H 51 51 $DGS END_FUN, ??ef_fn_intwdti, U, U, 00H, 065H, 01H, 00H 52 52 $DGS AUX_END, 06H 53 53 $DGS GLV_SYM, _fn_intlvi, U, U, 0E001H, 026H, 01H, 02H 54 54 $DGS AUX_FUN, 00H, U, U, 02FH, 00H, 00H 55 55 $DGS BEG_FUN, ??bf_fn_intlvi, U, U, 00H, 065H, 01H, 00H 56 56 $DGS AUX_BEG, 052H, 00H, 029H 57 57 $DGS BEG_BLK, ??bb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H 58 58 $DGS AUX_BEG, 03H, 00H, 00H 59 59 $DGS END_BLK, ??eb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H 60 60 $DGS AUX_END, 05H 61 61 $DGS END_FUN, ??ef_fn_intlvi, U, U, 00H, 065H, 01H, 00H 62 62 $DGS AUX_END, 06H 63 63 $DGS GLV_SYM, _fn_intp0, U, U, 0E001H, 026H, 01H, 02H 64 64 $DGS AUX_FUN, 00H, U, U, 039H, 00H, 00H 65 65 $DGS BEG_FUN, ??bf_fn_intp0, U, U, 00H, 065H, 01H, 00H 66 66 $DGS AUX_BEG, 059H, 00H, 033H 67 67 $DGS BEG_BLK, ??bb00_fn_intp0, U, U, 00H, 064H, 01H, 00H 68 68 $DGS AUX_BEG, 03H, 00H, 00H 69 69 $DGS END_BLK, ??eb00_fn_intp0, U, U, 00H, 064H, 01H, 00H 70 70 $DGS AUX_END, 05H 71 71 $DGS END_FUN, ??ef_fn_intp0, U, U, 00H, 065H, 01H, 00H 72 72 $DGS AUX_END, 06H 73 73 $DGS GLV_SYM, _fn_intp1, U, U, 0E001H, 026H, 01H, 02H 74 74 $DGS AUX_FUN, 00H, U, U, 043H, 00H, 00H 75 75 $DGS BEG_FUN, ??bf_fn_intp1, U, U, 00H, 065H, 01H, 00H 76 76 $DGS AUX_BEG, 061H, 00H, 03DH 77 77 $DGS BEG_BLK, ??bb00_fn_intp1, U, U, 00H, 064H, 01H, 00H 78 78 $DGS AUX_BEG, 03H, 00H, 00H 79 79 $DGS END_BLK, ??eb00_fn_intp1, U, U, 00H, 064H, 01H, 00H 80 80 $DGS AUX_END, 05H 81 81 $DGS END_FUN, ??ef_fn_intp1, U, U, 00H, 065H, 01H, 00H 82 82 $DGS AUX_END, 06H 83 83 $DGS GLV_SYM, _fn_intp2, U, U, 0E001H, 026H, 01H, 02H 84 84 $DGS AUX_FUN, 00H, U, U, 04DH, 00H, 00H 85 85 $DGS BEG_FUN, ??bf_fn_intp2, U, U, 00H, 065H, 01H, 00H 86 86 $DGS AUX_BEG, 068H, 00H, 047H 87 87 $DGS BEG_BLK, ??bb00_fn_intp2, U, U, 00H, 064H, 01H, 00H 88 88 $DGS AUX_BEG, 03H, 00H, 00H 89 89 $DGS END_BLK, ??eb00_fn_intp2, U, U, 00H, 064H, 01H, 00H 90 90 $DGS AUX_END, 05H 91 91 $DGS END_FUN, ??ef_fn_intp2, U, U, 00H, 065H, 01H, 00H 92 92 $DGS AUX_END, 06H 93 93 $DGS GLV_SYM, _fn_intp3, U, U, 0E001H, 026H, 01H, 02H 94 94 $DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H 95 95 $DGS BEG_FUN, ??bf_fn_intp3, U, U, 00H, 065H, 01H, 00H 96 96 $DGS AUX_BEG, 06FH, 00H, 051H 97 97 $DGS BEG_BLK, ??bb00_fn_intp3, U, U, 00H, 064H, 01H, 00H 98 98 $DGS AUX_BEG, 03H, 00H, 00H 99 99 $DGS END_BLK, ??eb00_fn_intp3, U, U, 00H, 064H, 01H, 00H 100 100 $DGS AUX_END, 05H 101 101 $DGS END_FUN, ??ef_fn_intp3, U, U, 00H, 065H, 01H, 00H 102 102 $DGS AUX_END, 06H 103 103 $DGS GLV_SYM, _intp21_RFTx, U, U, 0E001H, 026H, 01H, 02H 104 104 $DGS AUX_FUN, 00H, U, U, 061H, 00H, 00H 105 105 $DGS BEG_FUN, ??bf_intp21_RFTx, U, U, 00H, 065H, 01H, 00H 106 106 $DGS AUX_BEG, 078H, 00H, 05BH 107 107 $DGS BEG_BLK, ??bb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H 108 108 $DGS AUX_BEG, 03H, 00H, 00H 109 109 $DGS END_BLK, ??eb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H 110 110 $DGS AUX_END, 05H 111 111 $DGS END_FUN, ??ef_intp21_RFTx, U, U, 00H, 065H, 01H, 00H 112 112 $DGS AUX_END, 06H 113 113 $DGS GLV_SYM, _fn_intcmp0, U, U, 0E001H, 026H, 01H, 02H 114 114 $DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H 115 115 $DGS BEG_FUN, ??bf_fn_intcmp0, U, U, 00H, 065H, 01H, 00H 116 116 $DGS AUX_BEG, 087H, 00H, 065H 117 117 $DGS BEG_BLK, ??bb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H 118 118 $DGS AUX_BEG, 03H, 00H, 00H 119 119 $DGS END_BLK, ??eb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H 120 120 $DGS AUX_END, 05H 121 121 $DGS END_FUN, ??ef_fn_intcmp0, U, U, 00H, 065H, 01H, 00H 122 122 $DGS AUX_END, 06H 123 123 $DGS GLV_SYM, _fn_intcmp1, U, U, 0E001H, 026H, 01H, 02H 124 124 $DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H 125 125 $DGS BEG_FUN, ??bf_fn_intcmp1, U, U, 00H, 065H, 01H, 00H 126 126 $DGS AUX_BEG, 08EH, 00H, 06FH 127 127 $DGS BEG_BLK, ??bb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H 128 128 $DGS AUX_BEG, 03H, 00H, 00H 129 129 $DGS END_BLK, ??eb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H 130 130 $DGS AUX_END, 05H 131 131 $DGS END_FUN, ??ef_fn_intcmp1, U, U, 00H, 065H, 01H, 00H 132 132 $DGS AUX_END, 06H 133 133 $DGS GLV_SYM, _fn_intdma0, U, U, 0E001H, 026H, 01H, 02H 134 134 $DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H 135 135 $DGS BEG_FUN, ??bf_fn_intdma0, U, U, 00H, 065H, 01H, 00H 136 136 $DGS AUX_BEG, 095H, 00H, 079H 137 137 $DGS BEG_BLK, ??bb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H 138 138 $DGS AUX_BEG, 03H, 00H, 00H 139 139 $DGS END_BLK, ??eb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H 140 140 $DGS AUX_END, 05H 141 141 $DGS END_FUN, ??ef_fn_intdma0, U, U, 00H, 065H, 01H, 00H 142 142 $DGS AUX_END, 06H 143 143 $DGS GLV_SYM, _fn_intst0, U, U, 0E001H, 026H, 01H, 02H 144 144 $DGS AUX_FUN, 00H, U, U, 089H, 00H, 00H 145 145 $DGS BEG_FUN, ??bf_fn_intst0, U, U, 00H, 065H, 01H, 00H 146 146 $DGS AUX_BEG, 09FH, 00H, 083H 147 147 $DGS BEG_BLK, ??bb00_fn_intst0, U, U, 00H, 064H, 01H, 00H 148 148 $DGS AUX_BEG, 03H, 00H, 00H 149 149 $DGS END_BLK, ??eb00_fn_intst0, U, U, 00H, 064H, 01H, 00H 150 150 $DGS AUX_END, 05H 151 151 $DGS END_FUN, ??ef_fn_intst0, U, U, 00H, 065H, 01H, 00H 152 152 $DGS AUX_END, 06H 153 153 $DGS GLV_SYM, _fn_intsr0, U, U, 0E001H, 026H, 01H, 02H 154 154 $DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H 155 155 $DGS BEG_FUN, ??bf_fn_intsr0, U, U, 00H, 065H, 01H, 00H 156 156 $DGS AUX_BEG, 0A8H, 00H, 08DH 157 157 $DGS BEG_BLK, ??bb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H 158 158 $DGS AUX_BEG, 03H, 00H, 00H 159 159 $DGS END_BLK, ??eb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H 160 160 $DGS AUX_END, 05H 161 161 $DGS END_FUN, ??ef_fn_intsr0, U, U, 00H, 065H, 01H, 00H 162 162 $DGS AUX_END, 06H 163 163 $DGS GLV_SYM, _fn_intsre0, U, U, 0E001H, 026H, 01H, 02H 164 164 $DGS AUX_FUN, 00H, U, U, 09DH, 00H, 00H 165 165 $DGS BEG_FUN, ??bf_fn_intsre0, U, U, 00H, 065H, 01H, 00H 166 166 $DGS AUX_BEG, 0B1H, 00H, 097H 167 167 $DGS BEG_BLK, ??bb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H 168 168 $DGS AUX_BEG, 03H, 00H, 00H 169 169 $DGS END_BLK, ??eb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H 170 170 $DGS AUX_END, 05H 171 171 $DGS END_FUN, ??ef_fn_intsre0, U, U, 00H, 065H, 01H, 00H 172 172 $DGS AUX_END, 06H 173 173 $DGS GLV_SYM, _fn_intst1, U, U, 0E001H, 026H, 01H, 02H 174 174 $DGS AUX_FUN, 00H, U, U, 0A7H, 00H, 00H 175 175 $DGS BEG_FUN, ??bf_fn_intst1, U, U, 00H, 065H, 01H, 00H 176 176 $DGS AUX_BEG, 0B9H, 00H, 0A1H 177 177 $DGS BEG_BLK, ??bb00_fn_intst1, U, U, 00H, 064H, 01H, 00H 178 178 $DGS AUX_BEG, 03H, 00H, 00H 179 179 $DGS END_BLK, ??eb00_fn_intst1, U, U, 00H, 064H, 01H, 00H 180 180 $DGS AUX_END, 05H 181 181 $DGS END_FUN, ??ef_fn_intst1, U, U, 00H, 065H, 01H, 00H 182 182 $DGS AUX_END, 06H 183 183 $DGS GLV_SYM, _fn_intsr1, U, U, 0E001H, 026H, 01H, 02H 184 184 $DGS AUX_FUN, 00H, U, U, 0B1H, 00H, 00H 185 185 $DGS BEG_FUN, ??bf_fn_intsr1, U, U, 00H, 065H, 01H, 00H 186 186 $DGS AUX_BEG, 0C3H, 00H, 0ABH 187 187 $DGS BEG_BLK, ??bb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H 188 188 $DGS AUX_BEG, 03H, 00H, 00H 189 189 $DGS END_BLK, ??eb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H 190 190 $DGS AUX_END, 05H 191 191 $DGS END_FUN, ??ef_fn_intsr1, U, U, 00H, 065H, 01H, 00H 192 192 $DGS AUX_END, 06H 193 193 $DGS GLV_SYM, _fn_intsre1, U, U, 0E001H, 026H, 01H, 02H 194 194 $DGS AUX_FUN, 00H, U, U, 0BBH, 00H, 00H 195 195 $DGS BEG_FUN, ??bf_fn_intsre1, U, U, 00H, 065H, 01H, 00H 196 196 $DGS AUX_BEG, 0CAH, 00H, 0B5H 197 197 $DGS BEG_BLK, ??bb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H 198 198 $DGS AUX_BEG, 03H, 00H, 00H 199 199 $DGS END_BLK, ??eb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H 200 200 $DGS AUX_END, 05H 201 201 $DGS END_FUN, ??ef_fn_intsre1, U, U, 00H, 065H, 01H, 00H 202 202 $DGS AUX_END, 06H 203 203 $DGS GLV_SYM, _fn_inttm01, U, U, 0E001H, 026H, 01H, 02H 204 204 $DGS AUX_FUN, 00H, U, U, 0C5H, 00H, 00H 205 205 $DGS BEG_FUN, ??bf_fn_inttm01, U, U, 00H, 065H, 01H, 00H 206 206 $DGS AUX_BEG, 0D4H, 00H, 0BFH 207 207 $DGS BEG_BLK, ??bb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H 208 208 $DGS AUX_BEG, 03H, 00H, 00H 209 209 $DGS END_BLK, ??eb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H 210 210 $DGS AUX_END, 05H 211 211 $DGS END_FUN, ??ef_fn_inttm01, U, U, 00H, 065H, 01H, 00H 212 212 $DGS AUX_END, 06H 213 213 $DGS GLV_SYM, _fn_inttm02, U, U, 0E001H, 026H, 01H, 02H 214 214 $DGS AUX_FUN, 00H, U, U, 0CFH, 00H, 00H 215 215 $DGS BEG_FUN, ??bf_fn_inttm02, U, U, 00H, 065H, 01H, 00H 216 216 $DGS AUX_BEG, 0DCH, 00H, 0C9H 217 217 $DGS BEG_BLK, ??bb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H 218 218 $DGS AUX_BEG, 03H, 00H, 00H 219 219 $DGS END_BLK, ??eb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H 220 220 $DGS AUX_END, 05H 221 221 $DGS END_FUN, ??ef_fn_inttm02, U, U, 00H, 065H, 01H, 00H 222 222 $DGS AUX_END, 06H 223 223 $DGS GLV_SYM, _fn_inttm03, U, U, 0E001H, 026H, 01H, 02H 224 224 $DGS AUX_FUN, 00H, U, U, 0D9H, 00H, 00H 225 225 $DGS BEG_FUN, ??bf_fn_inttm03, U, U, 00H, 065H, 01H, 00H 226 226 $DGS AUX_BEG, 0E3H, 00H, 0D3H 227 227 $DGS BEG_BLK, ??bb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H 228 228 $DGS AUX_BEG, 03H, 00H, 00H 229 229 $DGS END_BLK, ??eb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H 230 230 $DGS AUX_END, 05H 231 231 $DGS END_FUN, ??ef_fn_inttm03, U, U, 00H, 065H, 01H, 00H 232 232 $DGS AUX_END, 06H 233 233 $DGS GLV_SYM, _fn_intrtc, U, U, 0E001H, 026H, 01H, 02H 234 234 $DGS AUX_FUN, 00H, U, U, 0E3H, 00H, 00H 235 235 $DGS BEG_FUN, ??bf_fn_intrtc, U, U, 00H, 065H, 01H, 00H 236 236 $DGS AUX_BEG, 0ECH, 00H, 0DDH 237 237 $DGS BEG_BLK, ??bb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H 238 238 $DGS AUX_BEG, 03H, 00H, 00H 239 239 $DGS END_BLK, ??eb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H 240 240 $DGS AUX_END, 05H 241 241 $DGS END_FUN, ??ef_fn_intrtc, U, U, 00H, 065H, 01H, 00H 242 242 $DGS AUX_END, 06H 243 243 $DGS GLV_SYM, _fn_intmd, U, U, 0E001H, 026H, 01H, 02H 244 244 $DGS AUX_FUN, 00H, U, U, 0EDH, 00H, 00H 245 245 $DGS BEG_FUN, ??bf_fn_intmd, U, U, 00H, 065H, 01H, 00H 246 246 $DGS AUX_BEG, 0F6H, 00H, 0E7H 247 247 $DGS BEG_BLK, ??bb00_fn_intmd, U, U, 00H, 064H, 01H, 00H 248 248 $DGS AUX_BEG, 03H, 00H, 00H 249 249 $DGS END_BLK, ??eb00_fn_intmd, U, U, 00H, 064H, 01H, 00H 250 250 $DGS AUX_END, 05H 251 251 $DGS END_FUN, ??ef_fn_intmd, U, U, 00H, 065H, 01H, 00H 252 252 $DGS AUX_END, 06H 253 253 $DGS GLV_SYM, _fn_inttm04, U, U, 0E001H, 026H, 01H, 02H 254 254 $DGS AUX_FUN, 00H, U, U, 0F7H, 00H, 00H 255 255 $DGS BEG_FUN, ??bf_fn_inttm04, U, U, 00H, 065H, 01H, 00H 256 256 $DGS AUX_BEG, 0FEH, 00H, 0F1H 257 257 $DGS BEG_BLK, ??bb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H 258 258 $DGS AUX_BEG, 03H, 00H, 00H 259 259 $DGS END_BLK, ??eb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H 260 260 $DGS AUX_END, 05H 261 261 $DGS END_FUN, ??ef_fn_inttm04, U, U, 00H, 065H, 01H, 00H 262 262 $DGS AUX_END, 06H 263 263 $DGS GLV_SYM, _fn_inttm05, U, U, 0E001H, 026H, 01H, 02H 264 264 $DGS AUX_FUN, 00H, U, U, 0101H, 00H, 00H 265 265 $DGS BEG_FUN, ??bf_fn_inttm05, U, U, 00H, 065H, 01H, 00H 266 266 $DGS AUX_BEG, 0106H, 00H, 0FBH 267 267 $DGS BEG_BLK, ??bb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H 268 268 $DGS AUX_BEG, 03H, 00H, 00H 269 269 $DGS END_BLK, ??eb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H 270 270 $DGS AUX_END, 05H 271 271 $DGS END_FUN, ??ef_fn_inttm05, U, U, 00H, 065H, 01H, 00H 272 272 $DGS AUX_END, 06H 273 273 $DGS GLV_SYM, _fn_inttm06, U, U, 0E001H, 026H, 01H, 02H 274 274 $DGS AUX_FUN, 00H, U, U, 010BH, 00H, 00H 275 275 $DGS BEG_FUN, ??bf_fn_inttm06, U, U, 00H, 065H, 01H, 00H 276 276 $DGS AUX_BEG, 010EH, 00H, 0105H 277 277 $DGS BEG_BLK, ??bb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H 278 278 $DGS AUX_BEG, 03H, 00H, 00H 279 279 $DGS END_BLK, ??eb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H 280 280 $DGS AUX_END, 05H 281 281 $DGS END_FUN, ??ef_fn_inttm06, U, U, 00H, 065H, 01H, 00H 282 282 $DGS AUX_END, 06H 283 283 $DGS GLV_SYM, _fn_inttm07, U, U, 0E001H, 026H, 01H, 02H 284 284 $DGS AUX_FUN, 00H, U, U, 0115H, 00H, 00H 285 285 $DGS BEG_FUN, ??bf_fn_inttm07, U, U, 00H, 065H, 01H, 00H 286 286 $DGS AUX_BEG, 0116H, 00H, 010FH 287 287 $DGS BEG_BLK, ??bb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H 288 288 $DGS AUX_BEG, 03H, 00H, 00H 289 289 $DGS END_BLK, ??eb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H 290 290 $DGS AUX_END, 05H 291 291 $DGS END_FUN, ??ef_fn_inttm07, U, U, 00H, 065H, 01H, 00H 292 292 $DGS AUX_END, 06H 293 293 $DGS GLV_SYM, _@vect10, U, U, 00H, 026H, 00H, 00H 294 294 $DGS GLV_SYM, _@vect12, U, U, 00H, 026H, 00H, 00H 295 295 $DGS GLV_SYM, _@vect1c, U, U, 00H, 026H, 00H, 00H 296 296 $DGS GLV_SYM, _@vect24, U, U, 00H, 026H, 00H, 00H 297 297 $DGS GLV_SYM, _@vect2a, U, U, 00H, 026H, 00H, 00H 298 298 $DGS GLV_SYM, _@vect34, U, U, 00H, 026H, 00H, 00H 299 299 $DGS GLV_SYM, _@vect36, U, U, 00H, 026H, 00H, 00H 300 300 $DGS GLV_SYM, _@vect38, U, U, 00H, 026H, 00H, 00H 301 301 $DGS GLV_SYM, _@vect3a, U, U, 00H, 026H, 00H, 00H 302 302 $DGS GLV_SYM, _@vect4a, U, U, 00H, 026H, 00H, 00H 303 303 $DGS GLV_SYM, _@vect5a, U, U, 00H, 026H, 00H, 00H 304 304 $DGS GLV_SYM, _@vect62, U, U, 00H, 026H, 00H, 00H 305 305 306 306 EXTRN _intp4_extdc 307 307 EXTRN _intp5_shell 308 308 EXTRN _int_dma1 309 309 EXTRN _int_iic10 310 310 EXTRN _int_iic_twl 311 311 EXTRN _int_adc 312 312 EXTRN _int_rtc 313 313 EXTRN _int_rtc_int 314 314 EXTRN _int_kr 315 315 EXTRN _intp6_PM_irq 316 316 EXTRN _int_iic_ctr 317 317 EXTRN _intp23_ACC_ready 318 318 PUBLIC _fn_intwdti 319 319 PUBLIC _fn_intlvi 320 320 PUBLIC _fn_intp0 321 321 PUBLIC _fn_intp1 322 322 PUBLIC _fn_intp2 323 323 PUBLIC _fn_intp3 324 324 PUBLIC _intp21_RFTx 325 325 PUBLIC _fn_intcmp0 326 326 PUBLIC _fn_intcmp1 327 327 PUBLIC _fn_intdma0 328 328 PUBLIC _fn_intst0 329 329 PUBLIC _fn_intsr0 330 330 PUBLIC _fn_intsre0 331 331 PUBLIC _fn_intst1 332 332 PUBLIC _fn_intsr1 333 333 PUBLIC _fn_intsre1 334 334 PUBLIC _fn_inttm01 335 335 PUBLIC _fn_inttm02 336 336 PUBLIC _fn_inttm03 337 337 PUBLIC _fn_intrtc 338 338 PUBLIC _fn_intmd 339 339 PUBLIC _fn_inttm04 340 340 PUBLIC _fn_inttm05 341 341 PUBLIC _fn_inttm06 342 342 PUBLIC _fn_inttm07 343 343 PUBLIC _@vect10 344 344 PUBLIC _@vect12 345 345 PUBLIC _@vect1c 346 346 PUBLIC _@vect24 347 347 PUBLIC _@vect2a 348 348 PUBLIC _@vect34 349 349 PUBLIC _@vect36 350 350 PUBLIC _@vect38 351 351 PUBLIC _@vect3a 352 352 PUBLIC _@vect4a 353 353 PUBLIC _@vect5a 354 354 PUBLIC _@vect62 355 355 356 356 ----- @@BITS BSEG 357 357 358 358 ----- @@CNST CSEG MIRRORP 359 359 360 360 ----- @@R_INIT CSEG UNIT64KP 361 361 362 362 ----- @@INIT DSEG BASEP 363 363 364 364 ----- @@DATA DSEG BASEP 365 365 366 366 ----- @@R_INIS CSEG UNIT64KP 367 367 368 368 ----- @@INIS DSEG SADDRP 369 369 370 370 ----- @@DATS DSEG SADDRP 371 371 372 372 ----- @@CNSTL CSEG PAGE64KP 373 373 374 374 ----- @@RLINIT CSEG UNIT64KP 375 375 376 376 ----- @@INITL DSEG UNIT64KP 377 377 378 378 ----- @@DATAL DSEG UNIT64KP 379 379 380 380 ----- @@CALT CSEG CALLT0 381 381 382 382 ; line 1 : #pragma nop 383 383 ; line 2 : 384 384 ; line 3 : 385 385 ; line 4 : #include "config.h" 386 386 ; line 5 : 387 387 ; line 6 : //#pragma interrupt INTWDTI fn_intwdti // 未使用 388 388 ; line 7 : //#pragma interrupt INTLVI fn_intlvi // 未使用 389 389 ; line 8 : 390 390 ; line 9 : //#pragma interrupt INTP0 intp0_slp // SLP (CPUより、要求 391 391 ; ) ポーリング 392 392 ; line 10 : //#pragma interrupt INTP1 fn_intp1 // (I2C) 393 393 ; line 11 : //#pragma interrupt INTP2 fn_intp2 // (I2C) 394 394 ; line 12 : //#pragma interrupt INTP3 fn_intp3 // 未搭載 395 395 ; line 13 : #pragma interrupt INTP4 intp4_extdc // EXTDC, ただし電源off 396 396 ; から起こすのみ。通常はポーリング 397 397 ; line 14 : #pragma interrupt INTP5 intp5_shell // SHELL_CLOSE, ただし電 398 398 ; 源offから起こすのみ。通常はポーリング 399 399 ; line 15 : #pragma interrupt INTP6 intp6_PM_irq // CODEC経由で旧PMICへの 400 400 ; コマンド書き込み 401 401 ; line 16 : 402 402 ; line 17 : //#ifdef _MCU_BSR_ // 割り込みそのものは 403 403 ; 使いません 404 404 ; line 18 : //#pragma interrupt INTP21 intp21_RFTx // 電波送信パルス 405 405 ; line 19 : //#else 406 406 ; line 20 : //#pragma interrupt INTP7 intp21_RFTx 407 407 ; line 21 : //#endif 408 408 ; line 22 : 409 409 ; line 23 : #ifdef _MCU_BSR_ 410 410 ; line 24 : #pragma interrupt INTP23 intp23_ACC_ready // 加速度センサ 411 411 ; 、データ準備完了 412 412 ; line 25 : #endif 413 413 ; line 26 : 414 414 ; line 27 : //#pragma interrupt INTCMP0 fn_intcmp0 415 415 ; line 28 : //#pragma interrupt INTCMP1 fn_intcmp1 416 416 ; line 29 : //#pragma interrupt INTDMA0 fn_intdma0 417 417 ; line 30 : #pragma interrupt INTDMA1 int_dma1 418 418 ; line 31 : 419 419 ; line 32 : //#pragma interrupt INTST0 fn_intst0 420 420 ; line 33 : /* #pragma interrupt INTCSI00 fn_intcsi00 */ 421 421 ; line 34 : //#pragma interrupt INTSR0 fn_intsr0 422 422 ; line 35 : /* #pragma interrupt INTCSI01 fn_intcsi01 */ 423 423 ; line 36 : //#pragma interrupt INTSRE0 fn_intsre0 424 424 ; line 37 : 425 425 ; line 38 : //#pragma interrupt INTST1 fn_intst1 426 426 ; line 39 : /* #pragma interrupt INTCSI10 fn_intcsi10 */ 427 427 ; line 40 : #pragma interrupt INTIIC10 int_iic10 428 428 ; line 41 : //#pragma interrupt INTSR1 fn_intsr1 429 429 ; line 42 : //#pragma interrupt INTSRE1 fn_intsre1 430 430 ; line 43 : 431 431 ; line 44 : 432 432 ; line 45 : #ifdef _MCU_KE3_ 433 433 ; line 46 : #pragma interrupt INTIICA int_iic_ctr // CTR側 434 434 ; line 47 : #else 435 435 ; line 48 : 436 436 ; line 49 : // TSはマザボでテレコ、WMは回路図がテレコで結局一致… 437 437 ; line 50 : #pragma interrupt INTIICA0 int_iic_twl 438 438 ; line 51 : #pragma interrupt INTIICA1 int_iic_ctr 439 439 ; line 52 : #endif 440 440 ; line 53 : 441 441 ; line 54 : //#pragma interrupt INTTM00 fn_inttm00 442 442 ; line 55 : //#pragma interrupt INTTM01 fn_inttm01 443 443 ; line 56 : //#pragma interrupt INTTM02 fn_inttm02 444 444 ; line 57 : //#pragma interrupt INTTM03 fn_inttm03 445 445 ; line 58 : 446 446 ; line 59 : #pragma interrupt INTAD int_adc 447 447 ; line 60 : #pragma interrupt INTRTC int_rtc 448 448 ; line 61 : #pragma interrupt INTRTCI int_rtc_int 449 449 ; line 62 : #pragma interrupt INTKR int_kr 450 450 ; line 63 : //#pragma interrupt INTMD fn_intmd 451 451 ; line 64 : 452 452 ; line 65 : //#pragma interrupt INTTM04 fn_inttm04 453 453 ; line 66 : //#pragma interrupt INTTM05 fn_inttm05 454 454 ; line 67 : //#pragma interrupt INTTM06 fn_inttm06 455 455 ; line 68 : //#pragma interrupt INTTM07 fn_inttm07 456 456 ; line 69 : 457 457 ; line 70 : 458 458 ; line 71 : /****************************************************/ 459 459 ; line 72 : /* 未使用時のダミー関数定義 */ 460 460 ; line 73 : /****************************************************/ 461 461 ; line 74 : __interrupt void fn_intwdti( ) 462 462 ; line 75 : { 463 463 464 464 ----- @@BASE CSEG BASE 465 465 00000 _fn_intwdti: 466 466 $DGL 1,27 467 467 00000 ??bf_fn_intwdti: 468 468 ; line 76 : while( 1 ) 469 469 00000 ?L0003: 470 470 ; line 77 : { 471 471 00000 ??bb00_fn_intwdti: 472 472 ; line 78 : NOP(); 473 473 $DGL 0,4 474 474 00000 00 nop ;[INF] 1, 1 475 475 00001 ??eb00_fn_intwdti: 476 476 ; line 79 : } 477 477 $DGL 0,5 478 478 00001 EFFD br $?L0003 ;[INF] 2, 3 479 479 ; line 80 : } 480 480 $DGL 0,6 481 481 00003 ??ef_fn_intwdti: 482 482 00003 61FC reti ;[INF] 2, 6 483 483 00005 ??ee_fn_intwdti: 484 484 ; line 81 : __interrupt void fn_intlvi( ) 485 485 ; line 82 : { 486 486 00005 _fn_intlvi: 487 487 $DGL 1,37 488 488 00005 ??bf_fn_intlvi: 489 489 ; line 83 : while( 1 ) 490 490 00005 ?L0007: 491 491 ; line 84 : { 492 492 00005 ??bb00_fn_intlvi: 493 493 ; line 85 : NOP(); 494 494 $DGL 0,4 495 495 00005 00 nop ;[INF] 1, 1 496 496 00006 ??eb00_fn_intlvi: 497 497 ; line 86 : } 498 498 $DGL 0,5 499 499 00006 EFFD br $?L0007 ;[INF] 2, 3 500 500 ; line 87 : } 501 501 $DGL 0,6 502 502 00008 ??ef_fn_intlvi: 503 503 00008 61FC reti ;[INF] 2, 6 504 504 0000A ??ee_fn_intlvi: 505 505 ; line 88 : 506 506 ; line 89 : __interrupt void fn_intp0(){ 507 507 0000A _fn_intp0: 508 508 $DGL 1,47 509 509 0000A ??bf_fn_intp0: 510 510 ; line 90 : while( 1 ) 511 511 0000A ?L0011: 512 512 ; line 91 : { 513 513 0000A ??bb00_fn_intp0: 514 514 ; line 92 : NOP(); 515 515 $DGL 0,4 516 516 0000A 00 nop ;[INF] 1, 1 517 517 0000B ??eb00_fn_intp0: 518 518 ; line 93 : } 519 519 $DGL 0,5 520 520 0000B EFFD br $?L0011 ;[INF] 2, 3 521 521 ; line 94 : } 522 522 $DGL 0,6 523 523 0000D ??ef_fn_intp0: 524 524 0000D 61FC reti ;[INF] 2, 6 525 525 0000F ??ee_fn_intp0: 526 526 ; line 95 : 527 527 ; line 96 : __interrupt void fn_intp1( ) 528 528 ; line 97 : { 529 529 0000F _fn_intp1: 530 530 $DGL 1,57 531 531 0000F ??bf_fn_intp1: 532 532 ; line 98 : while( 1 ) 533 533 0000F ?L0015: 534 534 ; line 99 : { 535 535 0000F ??bb00_fn_intp1: 536 536 ; line 100 : NOP(); 537 537 $DGL 0,4 538 538 0000F 00 nop ;[INF] 1, 1 539 539 00010 ??eb00_fn_intp1: 540 540 ; line 101 : } 541 541 $DGL 0,5 542 542 00010 EFFD br $?L0015 ;[INF] 2, 3 543 543 ; line 102 : } // 544 544 $DGL 0,6 545 545 00012 ??ef_fn_intp1: 546 546 00012 61FC reti ;[INF] 2, 6 547 547 00014 ??ee_fn_intp1: 548 548 ; line 103 : __interrupt void fn_intp2( ) 549 549 ; line 104 : { 550 550 00014 _fn_intp2: 551 551 $DGL 1,67 552 552 00014 ??bf_fn_intp2: 553 553 ; line 105 : while( 1 ) 554 554 00014 ?L0019: 555 555 ; line 106 : { 556 556 00014 ??bb00_fn_intp2: 557 557 ; line 107 : NOP(); 558 558 $DGL 0,4 559 559 00014 00 nop ;[INF] 1, 1 560 560 00015 ??eb00_fn_intp2: 561 561 ; line 108 : } 562 562 $DGL 0,5 563 563 00015 EFFD br $?L0019 ;[INF] 2, 3 564 564 ; line 109 : } 565 565 $DGL 0,6 566 566 00017 ??ef_fn_intp2: 567 567 00017 61FC reti ;[INF] 2, 6 568 568 00019 ??ee_fn_intp2: 569 569 ; line 110 : __interrupt void fn_intp3( ) 570 570 ; line 111 : { 571 571 00019 _fn_intp3: 572 572 $DGL 1,77 573 573 00019 ??bf_fn_intp3: 574 574 ; line 112 : while( 1 ) 575 575 00019 ?L0023: 576 576 ; line 113 : { 577 577 00019 ??bb00_fn_intp3: 578 578 ; line 114 : NOP(); 579 579 $DGL 0,4 580 580 00019 00 nop ;[INF] 1, 1 581 581 0001A ??eb00_fn_intp3: 582 582 ; line 115 : } 583 583 $DGL 0,5 584 584 0001A EFFD br $?L0023 ;[INF] 2, 3 585 585 ; line 116 : } 586 586 $DGL 0,6 587 587 0001C ??ef_fn_intp3: 588 588 0001C 61FC reti ;[INF] 2, 6 589 589 0001E ??ee_fn_intp3: 590 590 ; line 117 : 591 591 ; line 118 : 592 592 ; line 119 : __interrupt void intp21_RFTx( ) 593 593 ; line 120 : { 594 594 0001E _intp21_RFTx: 595 595 $DGL 1,87 596 596 0001E ??bf_intp21_RFTx: 597 597 ; line 121 : while( 1 ) 598 598 0001E ?L0027: 599 599 ; line 122 : { 600 600 0001E ??bb00_intp21_RFTx: 601 601 ; line 123 : NOP(); 602 602 $DGL 0,4 603 603 0001E 00 nop ;[INF] 1, 1 604 604 0001F ??eb00_intp21_RFTx: 605 605 ; line 124 : } 606 606 $DGL 0,5 607 607 0001F EFFD br $?L0027 ;[INF] 2, 3 608 608 ; line 125 : } 609 609 $DGL 0,6 610 610 00021 ??ef_intp21_RFTx: 611 611 00021 61FC reti ;[INF] 2, 6 612 612 00023 ??ee_intp21_RFTx: 613 613 ; line 126 : 614 614 ; line 127 : 615 615 ; line 128 : //__interrupt void fn_intp4(){ while(1){} } // pm.c 616 616 ; line 129 : //__interrupt void fn_intp5(){ while(1){} } // pm.c 617 617 ; line 130 : //__interrupt void fn_intp6(){ while(1){} } // pm.c 618 618 ; line 131 : //__interrupt void fn_intp7(){ while(1){} } // led.c 619 619 ; line 132 : //__interrupt void fn_intp21(){ while(1){} } // led.c 620 620 ; line 133 : 621 621 ; line 134 : __interrupt void fn_intcmp0( ) 622 622 ; line 135 : { 623 623 00023 _fn_intcmp0: 624 624 $DGL 1,97 625 625 00023 ??bf_fn_intcmp0: 626 626 ; line 136 : while( 1 ) 627 627 00023 ?L0031: 628 628 ; line 137 : { 629 629 00023 ??bb00_fn_intcmp0: 630 630 ; line 138 : NOP(); 631 631 $DGL 0,4 632 632 00023 00 nop ;[INF] 1, 1 633 633 00024 ??eb00_fn_intcmp0: 634 634 ; line 139 : } 635 635 $DGL 0,5 636 636 00024 EFFD br $?L0031 ;[INF] 2, 3 637 637 ; line 140 : } 638 638 $DGL 0,6 639 639 00026 ??ef_fn_intcmp0: 640 640 00026 61FC reti ;[INF] 2, 6 641 641 00028 ??ee_fn_intcmp0: 642 642 ; line 141 : __interrupt void fn_intcmp1( ) 643 643 ; line 142 : { 644 644 00028 _fn_intcmp1: 645 645 $DGL 1,107 646 646 00028 ??bf_fn_intcmp1: 647 647 ; line 143 : while( 1 ) 648 648 00028 ?L0035: 649 649 ; line 144 : { 650 650 00028 ??bb00_fn_intcmp1: 651 651 ; line 145 : NOP(); 652 652 $DGL 0,4 653 653 00028 00 nop ;[INF] 1, 1 654 654 00029 ??eb00_fn_intcmp1: 655 655 ; line 146 : } 656 656 $DGL 0,5 657 657 00029 EFFD br $?L0035 ;[INF] 2, 3 658 658 ; line 147 : } 659 659 $DGL 0,6 660 660 0002B ??ef_fn_intcmp1: 661 661 0002B 61FC reti ;[INF] 2, 6 662 662 0002D ??ee_fn_intcmp1: 663 663 ; line 148 : __interrupt void fn_intdma0( ) 664 664 ; line 149 : { 665 665 0002D _fn_intdma0: 666 666 $DGL 1,117 667 667 0002D ??bf_fn_intdma0: 668 668 ; line 150 : while( 1 ) 669 669 0002D ?L0039: 670 670 ; line 151 : { 671 671 0002D ??bb00_fn_intdma0: 672 672 ; line 152 : NOP(); 673 673 $DGL 0,4 674 674 0002D 00 nop ;[INF] 1, 1 675 675 0002E ??eb00_fn_intdma0: 676 676 ; line 153 : } 677 677 $DGL 0,5 678 678 0002E EFFD br $?L0039 ;[INF] 2, 3 679 679 ; line 154 : } 680 680 $DGL 0,6 681 681 00030 ??ef_fn_intdma0: 682 682 00030 61FC reti ;[INF] 2, 6 683 683 00032 ??ee_fn_intdma0: 684 684 ; line 155 : 685 685 ; line 156 : //__interrupt void fn_intdma1(){} // i2c_mcu.cにある 686 686 ; line 157 : 687 687 ; line 158 : __interrupt void fn_intst0( ) 688 688 ; line 159 : { 689 689 00032 _fn_intst0: 690 690 $DGL 1,127 691 691 00032 ??bf_fn_intst0: 692 692 ; line 160 : while( 1 ) 693 693 00032 ?L0043: 694 694 ; line 161 : { 695 695 00032 ??bb00_fn_intst0: 696 696 ; line 162 : NOP(); 697 697 $DGL 0,4 698 698 00032 00 nop ;[INF] 1, 1 699 699 00033 ??eb00_fn_intst0: 700 700 ; line 163 : } 701 701 $DGL 0,5 702 702 00033 EFFD br $?L0043 ;[INF] 2, 3 703 703 ; line 164 : } 704 704 $DGL 0,6 705 705 00035 ??ef_fn_intst0: 706 706 00035 61FC reti ;[INF] 2, 6 707 707 00037 ??ee_fn_intst0: 708 708 ; line 165 : 709 709 ; line 166 : /* __interrupt void fn_intcsi00(){} */ 710 710 ; line 167 : __interrupt void fn_intsr0( ) 711 711 ; line 168 : { 712 712 00037 _fn_intsr0: 713 713 $DGL 1,137 714 714 00037 ??bf_fn_intsr0: 715 715 ; line 169 : while( 1 ) 716 716 00037 ?L0047: 717 717 ; line 170 : { 718 718 00037 ??bb00_fn_intsr0: 719 719 ; line 171 : NOP(); 720 720 $DGL 0,4 721 721 00037 00 nop ;[INF] 1, 1 722 722 00038 ??eb00_fn_intsr0: 723 723 ; line 172 : } 724 724 $DGL 0,5 725 725 00038 EFFD br $?L0047 ;[INF] 2, 3 726 726 ; line 173 : } 727 727 $DGL 0,6 728 728 0003A ??ef_fn_intsr0: 729 729 0003A 61FC reti ;[INF] 2, 6 730 730 0003C ??ee_fn_intsr0: 731 731 ; line 174 : 732 732 ; line 175 : /* __interrupt void fn_intcsi01(){} */ 733 733 ; line 176 : __interrupt void fn_intsre0( ) 734 734 ; line 177 : { 735 735 0003C _fn_intsre0: 736 736 $DGL 1,147 737 737 0003C ??bf_fn_intsre0: 738 738 ; line 178 : while( 1 ) 739 739 0003C ?L0051: 740 740 ; line 179 : { 741 741 0003C ??bb00_fn_intsre0: 742 742 ; line 180 : NOP(); 743 743 $DGL 0,4 744 744 0003C 00 nop ;[INF] 1, 1 745 745 0003D ??eb00_fn_intsre0: 746 746 ; line 181 : } 747 747 $DGL 0,5 748 748 0003D EFFD br $?L0051 ;[INF] 2, 3 749 749 ; line 182 : } 750 750 $DGL 0,6 751 751 0003F ??ef_fn_intsre0: 752 752 0003F 61FC reti ;[INF] 2, 6 753 753 00041 ??ee_fn_intsre0: 754 754 ; line 183 : 755 755 ; line 184 : __interrupt void fn_intst1( ) 756 756 ; line 185 : { 757 757 00041 _fn_intst1: 758 758 $DGL 1,157 759 759 00041 ??bf_fn_intst1: 760 760 ; line 186 : while( 1 ) 761 761 00041 ?L0055: 762 762 ; line 187 : { 763 763 00041 ??bb00_fn_intst1: 764 764 ; line 188 : NOP(); 765 765 $DGL 0,4 766 766 00041 00 nop ;[INF] 1, 1 767 767 00042 ??eb00_fn_intst1: 768 768 ; line 189 : } 769 769 $DGL 0,5 770 770 00042 EFFD br $?L0055 ;[INF] 2, 3 771 771 ; line 190 : } 772 772 $DGL 0,6 773 773 00044 ??ef_fn_intst1: 774 774 00044 61FC reti ;[INF] 2, 6 775 775 00046 ??ee_fn_intst1: 776 776 ; line 191 : 777 777 ; line 192 : /* __interrupt void fn_intcsi10(){} */ 778 778 ; line 193 : //__interrupt void fn_intiic10(){ while(1){} } 779 779 ; line 194 : __interrupt void fn_intsr1( ) 780 780 ; line 195 : { 781 781 00046 _fn_intsr1: 782 782 $DGL 1,167 783 783 00046 ??bf_fn_intsr1: 784 784 ; line 196 : while( 1 ) 785 785 00046 ?L0059: 786 786 ; line 197 : { 787 787 00046 ??bb00_fn_intsr1: 788 788 ; line 198 : NOP(); 789 789 $DGL 0,4 790 790 00046 00 nop ;[INF] 1, 1 791 791 00047 ??eb00_fn_intsr1: 792 792 ; line 199 : } 793 793 $DGL 0,5 794 794 00047 EFFD br $?L0059 ;[INF] 2, 3 795 795 ; line 200 : } 796 796 $DGL 0,6 797 797 00049 ??ef_fn_intsr1: 798 798 00049 61FC reti ;[INF] 2, 6 799 799 0004B ??ee_fn_intsr1: 800 800 ; line 201 : __interrupt void fn_intsre1( ) 801 801 ; line 202 : { 802 802 0004B _fn_intsre1: 803 803 $DGL 1,177 804 804 0004B ??bf_fn_intsre1: 805 805 ; line 203 : while( 1 ) 806 806 0004B ?L0063: 807 807 ; line 204 : { 808 808 0004B ??bb00_fn_intsre1: 809 809 ; line 205 : NOP(); 810 810 $DGL 0,4 811 811 0004B 00 nop ;[INF] 1, 1 812 812 0004C ??eb00_fn_intsre1: 813 813 ; line 206 : } 814 814 $DGL 0,5 815 815 0004C EFFD br $?L0063 ;[INF] 2, 3 816 816 ; line 207 : } 817 817 $DGL 0,6 818 818 0004E ??ef_fn_intsre1: 819 819 0004E 61FC reti ;[INF] 2, 6 820 820 00050 ??ee_fn_intsre1: 821 821 ; line 208 : 822 822 ; line 209 : //__interrupt void fn_intiica(){} // i2c.cにある 823 823 ; line 210 : /* __interrupt void fn_inttm00(){} *//* sub.cにて定義 */ 824 824 ; line 211 : __interrupt void fn_inttm01( ) 825 825 ; line 212 : { 826 826 00050 _fn_inttm01: 827 827 $DGL 1,187 828 828 00050 ??bf_fn_inttm01: 829 829 ; line 213 : while( 1 ) 830 830 00050 ?L0067: 831 831 ; line 214 : { 832 832 00050 ??bb00_fn_inttm01: 833 833 ; line 215 : NOP(); 834 834 $DGL 0,4 835 835 00050 00 nop ;[INF] 1, 1 836 836 00051 ??eb00_fn_inttm01: 837 837 ; line 216 : } 838 838 $DGL 0,5 839 839 00051 EFFD br $?L0067 ;[INF] 2, 3 840 840 ; line 217 : } 841 841 $DGL 0,6 842 842 00053 ??ef_fn_inttm01: 843 843 00053 61FC reti ;[INF] 2, 6 844 844 00055 ??ee_fn_inttm01: 845 845 ; line 218 : 846 846 ; line 219 : __interrupt void fn_inttm02( ) 847 847 ; line 220 : { 848 848 00055 _fn_inttm02: 849 849 $DGL 1,197 850 850 00055 ??bf_fn_inttm02: 851 851 ; line 221 : while( 1 ) 852 852 00055 ?L0071: 853 853 ; line 222 : { 854 854 00055 ??bb00_fn_inttm02: 855 855 ; line 223 : NOP(); 856 856 $DGL 0,4 857 857 00055 00 nop ;[INF] 1, 1 858 858 00056 ??eb00_fn_inttm02: 859 859 ; line 224 : } 860 860 $DGL 0,5 861 861 00056 EFFD br $?L0071 ;[INF] 2, 3 862 862 ; line 225 : } 863 863 $DGL 0,6 864 864 00058 ??ef_fn_inttm02: 865 865 00058 61FC reti ;[INF] 2, 6 866 866 0005A ??ee_fn_inttm02: 867 867 ; line 226 : __interrupt void fn_inttm03( ) 868 868 ; line 227 : { 869 869 0005A _fn_inttm03: 870 870 $DGL 1,207 871 871 0005A ??bf_fn_inttm03: 872 872 ; line 228 : while( 1 ) 873 873 0005A ?L0075: 874 874 ; line 229 : { 875 875 0005A ??bb00_fn_inttm03: 876 876 ; line 230 : NOP(); 877 877 $DGL 0,4 878 878 0005A 00 nop ;[INF] 1, 1 879 879 0005B ??eb00_fn_inttm03: 880 880 ; line 231 : } 881 881 $DGL 0,5 882 882 0005B EFFD br $?L0075 ;[INF] 2, 3 883 883 ; line 232 : } 884 884 $DGL 0,6 885 885 0005D ??ef_fn_inttm03: 886 886 0005D 61FC reti ;[INF] 2, 6 887 887 0005F ??ee_fn_inttm03: 888 888 ; line 233 : 889 889 ; line 234 : //__interrupt void fn_intad(){ while(1){} } // adc.c 890 890 ; line 235 : __interrupt void fn_intrtc( ) 891 891 ; line 236 : { 892 892 0005F _fn_intrtc: 893 893 $DGL 1,217 894 894 0005F ??bf_fn_intrtc: 895 895 ; line 237 : while( 1 ) 896 896 0005F ?L0079: 897 897 ; line 238 : { 898 898 0005F ??bb00_fn_intrtc: 899 899 ; line 239 : NOP(); 900 900 $DGL 0,4 901 901 0005F 00 nop ;[INF] 1, 1 902 902 00060 ??eb00_fn_intrtc: 903 903 ; line 240 : } 904 904 $DGL 0,5 905 905 00060 EFFD br $?L0079 ;[INF] 2, 3 906 906 ; line 241 : } 907 907 $DGL 0,6 908 908 00062 ??ef_fn_intrtc: 909 909 00062 61FC reti ;[INF] 2, 6 910 910 00064 ??ee_fn_intrtc: 911 911 ; line 242 : 912 912 ; line 243 : //__interrupt void int_rtcint(){} // rtc.cにある 913 913 ; line 244 : //__interrupt void fn_intkr(){} // main.c 914 914 ; line 245 : __interrupt void fn_intmd( ) 915 915 ; line 246 : { 916 916 00064 _fn_intmd: 917 917 $DGL 1,227 918 918 00064 ??bf_fn_intmd: 919 919 ; line 247 : while( 1 ) 920 920 00064 ?L0083: 921 921 ; line 248 : { 922 922 00064 ??bb00_fn_intmd: 923 923 ; line 249 : NOP(); 924 924 $DGL 0,4 925 925 00064 00 nop ;[INF] 1, 1 926 926 00065 ??eb00_fn_intmd: 927 927 ; line 250 : } 928 928 $DGL 0,5 929 929 00065 EFFD br $?L0083 ;[INF] 2, 3 930 930 ; line 251 : } 931 931 $DGL 0,6 932 932 00067 ??ef_fn_intmd: 933 933 00067 61FC reti ;[INF] 2, 6 934 934 00069 ??ee_fn_intmd: 935 935 ; line 252 : 936 936 ; line 253 : __interrupt void fn_inttm04( ) 937 937 ; line 254 : { 938 938 00069 _fn_inttm04: 939 939 $DGL 1,237 940 940 00069 ??bf_fn_inttm04: 941 941 ; line 255 : while( 1 ) 942 942 00069 ?L0087: 943 943 ; line 256 : { 944 944 00069 ??bb00_fn_inttm04: 945 945 ; line 257 : NOP(); 946 946 $DGL 0,4 947 947 00069 00 nop ;[INF] 1, 1 948 948 0006A ??eb00_fn_inttm04: 949 949 ; line 258 : } 950 950 $DGL 0,5 951 951 0006A EFFD br $?L0087 ;[INF] 2, 3 952 952 ; line 259 : } 953 953 $DGL 0,6 954 954 0006C ??ef_fn_inttm04: 955 955 0006C 61FC reti ;[INF] 2, 6 956 956 0006E ??ee_fn_inttm04: 957 957 ; line 260 : 958 958 ; line 261 : __interrupt void fn_inttm05( ) 959 959 ; line 262 : { 960 960 0006E _fn_inttm05: 961 961 $DGL 1,247 962 962 0006E ??bf_fn_inttm05: 963 963 ; line 263 : while( 1 ) 964 964 0006E ?L0091: 965 965 ; line 264 : { 966 966 0006E ??bb00_fn_inttm05: 967 967 ; line 265 : NOP(); 968 968 $DGL 0,4 969 969 0006E 00 nop ;[INF] 1, 1 970 970 0006F ??eb00_fn_inttm05: 971 971 ; line 266 : } 972 972 $DGL 0,5 973 973 0006F EFFD br $?L0091 ;[INF] 2, 3 974 974 ; line 267 : } 975 975 $DGL 0,6 976 976 00071 ??ef_fn_inttm05: 977 977 00071 61FC reti ;[INF] 2, 6 978 978 00073 ??ee_fn_inttm05: 979 979 ; line 268 : 980 980 ; line 269 : __interrupt void fn_inttm06( ) 981 981 ; line 270 : { 982 982 00073 _fn_inttm06: 983 983 $DGL 1,257 984 984 00073 ??bf_fn_inttm06: 985 985 ; line 271 : while( 1 ) 986 986 00073 ?L0095: 987 987 ; line 272 : { 988 988 00073 ??bb00_fn_inttm06: 989 989 ; line 273 : NOP(); 990 990 $DGL 0,4 991 991 00073 00 nop ;[INF] 1, 1 992 992 00074 ??eb00_fn_inttm06: 993 993 ; line 274 : } 994 994 $DGL 0,5 995 995 00074 EFFD br $?L0095 ;[INF] 2, 3 996 996 ; line 275 : } 997 997 $DGL 0,6 998 998 00076 ??ef_fn_inttm06: 999 999 00076 61FC reti ;[INF] 2, 6 1000 1000 00078 ??ee_fn_inttm06: 1001 1001 ; line 276 : 1002 1002 ; line 277 : __interrupt void fn_inttm07( ) 1003 1003 ; line 278 : { 1004 1004 00078 _fn_inttm07: 1005 1005 $DGL 1,267 1006 1006 00078 ??bf_fn_inttm07: 1007 1007 ; line 279 : while( 1 ) 1008 1008 00078 ?L0099: 1009 1009 ; line 280 : { 1010 1010 00078 ??bb00_fn_inttm07: 1011 1011 ; line 281 : NOP(); 1012 1012 $DGL 0,4 1013 1013 00078 00 nop ;[INF] 1, 1 1014 1014 00079 ??eb00_fn_inttm07: 1015 1015 ; line 282 : } 1016 1016 $DGL 0,5 1017 1017 00079 EFFD br $?L0099 ;[INF] 2, 3 1018 1018 ; line 283 : } 1019 1019 $DGL 0,6 1020 1020 0007B ??ef_fn_inttm07: 1021 1021 0007B 61FC reti ;[INF] 2, 6 1022 1022 0007D ??ee_fn_inttm07: 1023 1023 1024 1024 ----- @@VECT10 CSEG AT 0010H 1025 1025 00010 _@vect10: 1026 1026 00010 R0000 DW _intp4_extdc 1027 1027 00012 _@vect12: 1028 1028 00012 R0000 DW _intp5_shell 1029 1029 1030 1030 ----- @@VECT1C CSEG AT 001CH 1031 1031 0001C _@vect1c: 1032 1032 0001C R0000 DW _int_dma1 1033 1033 1034 1034 ----- @@VECT24 CSEG AT 0024H 1035 1035 00024 _@vect24: 1036 1036 00024 R0000 DW _int_iic10 1037 1037 1038 1038 ----- @@VECT2A CSEG AT 002AH 1039 1039 0002A _@vect2a: 1040 1040 0002A R0000 DW _int_iic_twl 1041 1041 1042 1042 ----- @@VECT34 CSEG AT 0034H 1043 1043 00034 _@vect34: 1044 1044 00034 R0000 DW _int_adc 1045 1045 00036 _@vect36: 1046 1046 00036 R0000 DW _int_rtc 1047 1047 00038 _@vect38: 1048 1048 00038 R0000 DW _int_rtc_int 1049 1049 0003A _@vect3a: 1050 1050 0003A R0000 DW _int_kr 1051 1051 1052 1052 ----- @@VECT4A CSEG AT 004AH 1053 1053 0004A _@vect4a: 1054 1054 0004A R0000 DW _intp6_PM_irq 1055 1055 1056 1056 ----- @@VECT5A CSEG AT 005AH 1057 1057 0005A _@vect5a: 1058 1058 0005A R0000 DW _int_iic_ctr 1059 1059 1060 1060 ----- @@VECT62 CSEG AT 0062H 1061 1061 00062 _@vect62: 1062 1062 00062 R0000 DW _intp23_ACC_ready 1063 1063 1064 1064 ----- @@CODE CSEG BASE 1065 1065 1066 1066 ----- @@CODEL CSEG 1067 1067 END 1068 1068 1069 1069 1070 1070 ; *** Code Information *** 1071 1071 ; 1072 1072 ; $FILE C:\78k_data\yav-mcu-basara_0.10\ini_VECT.c 1073 1073 ; 1074 1074 ; $FUNC fn_intwdti(75) 1075 1075 ; void=(void) 1076 1076 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1077 1077 ; 1078 1078 ; $FUNC fn_intlvi(82) 1079 1079 ; void=(void) 1080 1080 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1081 1081 ; 1082 1082 ; $FUNC fn_intp0(89) 1083 1083 ; void=(void) 1084 1084 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1085 1085 ; 1086 1086 ; $FUNC fn_intp1(97) 1087 1087 ; void=(void) 1088 1088 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1089 1089 ; 1090 1090 ; $FUNC fn_intp2(104) 1091 1091 ; void=(void) 1092 1092 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1093 1093 ; 1094 1094 ; $FUNC fn_intp3(111) 1095 1095 ; void=(void) 1096 1096 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1097 1097 ; 1098 1098 ; $FUNC intp21_RFTx(120) 1099 1099 ; void=(void) 1100 1100 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1101 1101 ; 1102 1102 ; $FUNC fn_intcmp0(135) 1103 1103 ; void=(void) 1104 1104 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1105 1105 ; 1106 1106 ; $FUNC fn_intcmp1(142) 1107 1107 ; void=(void) 1108 1108 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1109 1109 ; 1110 1110 ; $FUNC fn_intdma0(149) 1111 1111 ; void=(void) 1112 1112 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1113 1113 ; 1114 1114 ; $FUNC fn_intst0(159) 1115 1115 ; void=(void) 1116 1116 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1117 1117 ; 1118 1118 ; $FUNC fn_intsr0(168) 1119 1119 ; void=(void) 1120 1120 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1121 1121 ; 1122 1122 ; $FUNC fn_intsre0(177) 1123 1123 ; void=(void) 1124 1124 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1125 1125 ; 1126 1126 ; $FUNC fn_intst1(185) 1127 1127 ; void=(void) 1128 1128 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1129 1129 ; 1130 1130 ; $FUNC fn_intsr1(195) 1131 1131 ; void=(void) 1132 1132 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1133 1133 ; 1134 1134 ; $FUNC fn_intsre1(202) 1135 1135 ; void=(void) 1136 1136 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1137 1137 ; 1138 1138 ; $FUNC fn_inttm01(212) 1139 1139 ; void=(void) 1140 1140 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1141 1141 ; 1142 1142 ; $FUNC fn_inttm02(220) 1143 1143 ; void=(void) 1144 1144 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1145 1145 ; 1146 1146 ; $FUNC fn_inttm03(227) 1147 1147 ; void=(void) 1148 1148 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1149 1149 ; 1150 1150 ; $FUNC fn_intrtc(236) 1151 1151 ; void=(void) 1152 1152 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1153 1153 ; 1154 1154 ; $FUNC fn_intmd(246) 1155 1155 ; void=(void) 1156 1156 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1157 1157 ; 1158 1158 ; $FUNC fn_inttm04(254) 1159 1159 ; void=(void) 1160 1160 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1161 1161 ; 1162 1162 ; $FUNC fn_inttm05(262) 1163 1163 ; void=(void) 1164 1164 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1165 1165 ; 1166 1166 ; $FUNC fn_inttm06(270) 1167 1167 ; void=(void) 1168 1168 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1169 1169 ; 1170 1170 ; $FUNC fn_inttm07(278) 1171 1171 ; void=(void) 1172 1172 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes 1173 1173 1174 1174 ; Target chip : uPD79F0104 1175 1175 ; Device file : E1.00b Segment informations: ADRS LEN NAME 00000 00000H.0 @@BITS 00000 00000H @@CNST 00000 00000H @@R_INIT 00000 00000H @@INIT 00000 00000H @@DATA 00000 00000H @@R_INIS 00000 00000H @@INIS 00000 00000H @@DATS 00000 00000H @@CNSTL 00000 00000H @@RLINIT 00000 00000H @@INITL 00000 00000H @@DATAL 00000 00000H @@CALT 00000 0007DH @@BASE 00010 00004H @@VECT10 0001C 00002H @@VECT1C 00024 00002H @@VECT24 0002A 00002H @@VECT2A 00034 00008H @@VECT34 0004A 00002H @@VECT4A 0005A 00002H @@VECT5A 00062 00002H @@VECT62 00000 00000H @@CODE 00000 00000H @@CODEL Target chip : uPD79F0104 Device file : E1.00b Assembly complete, 0 error(s) and 0 warning(s) found. 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