; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24

; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_ctr.c
; In-file   : vreg_ctr.c
; Asm-file  : inter_asm\vreg_ctr.asm
; Para-file : 

$PROCESSOR(9F0104)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF	03FH, 0210H, 02H, 00H, 00H, 00H, 00H

$DGS	FIL_NAM, .file,		0A1H,	0FFFEH,	03FH,	067H,	01H,	00H
$DGS	AUX_FIL, vreg_ctr.c
$DGS	MOD_NAM, vreg_ctr,	00H,	0FFFEH,	00H,	077H,	00H,	00H
$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
$DGS	ENM_TAG, .2fake,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
$DGS	AUX_TAG, 01H,		019H
$DGS	MEB_ENM, _ERR_FINISED,	00H,	0FFFFH,	04H,	010H,	00H,	00H
$DGS	MEB_ENM, _ERR_CONTINUE,	01H,	0FFFFH,	04H,	010H,	00H,	00H
$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
$DGS	AUX_EOS, 013H,		01H
$DGS	LAB_SYM, bs_S0105,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_S0105,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, bs_S0106,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_S0106,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, bs_S0104,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_S0104,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, bs_F0102,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_F0102,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, bs_S0103,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_S0103,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, bs_F0101,	U,	U,	00H,	06H,	00H,	00H
$DGS	LAB_SYM, es_F0101,	U,	U,	00H,	06H,	00H,	00H
$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
$DGS	GLV_SYM, _vreg_ctr_init,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	02DH,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_ctr_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 02AH,		00H,	02DH
$DGS	END_FUN, ??ef_vreg_ctr_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 0DH
$DGS	GLV_SYM, _vreg_ctr_write,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	059H,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_ctr_write,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 042H,		02H,	033H
$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	REG_PAR, _data,		07H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	BEG_BLK, ??bb00_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 06H,		00H,	035H
$DGS	BEG_BLK, ??bb01_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 01CH,		00H,	039H
$DGS	END_BLK, ??eb01_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 01FH
$DGS	BEG_BLK, ??bb02_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02DH,		00H,	03DH
$DGS	END_BLK, ??eb02_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02FH
$DGS	BEG_BLK, ??bb03_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 036H,		00H,	041H
$DGS	END_BLK, ??eb03_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 038H
$DGS	BEG_BLK, ??bb04_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 03AH,		00H,	045H
$DGS	END_BLK, ??eb04_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 03CH
$DGS	BEG_BLK, ??bb05_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 041H,		00H,	049H
$DGS	END_BLK, ??eb05_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 044H
$DGS	BEG_BLK, ??bb06_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 049H,		00H,	04DH
$DGS	END_BLK, ??eb06_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 055H
$DGS	BEG_BLK, ??bb07_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0D1H,		00H,	051H
$DGS	END_BLK, ??eb07_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0D3H
$DGS	BEG_BLK, ??bb08_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0D9H,		00H,	00H
$DGS	END_BLK, ??eb08_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0E3H
$DGS	END_BLK, ??eb00_vreg_ctr_write,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0E4H
$DGS	END_FUN, ??ef_vreg_ctr_write,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 0E6H
$DGS	GLV_SYM, _vreg_ctr_read,	U,	U,	0CH,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	07DH,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_ctr_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 0131H,		02H,	05FH
$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	STA_SYM, _rsub_temp,	?L0073,	U,	0DH,	03H,	00H,	00H
$DGS	BEG_BLK, ??bb00_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 06H,		00H,	063H
$DGS	END_BLK, ??eb00_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 08H
$DGS	BEG_BLK, ??bb01_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0AH,		00H,	067H
$DGS	END_BLK, ??eb01_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0CH
$DGS	BEG_BLK, ??bb02_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0EH,		00H,	06BH
$DGS	END_BLK, ??eb02_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 010H
$DGS	BEG_BLK, ??bb03_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 012H,		00H,	06FH
$DGS	END_BLK, ??eb03_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 015H
$DGS	BEG_BLK, ??bb04_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 017H,		00H,	073H
$DGS	END_BLK, ??eb04_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 019H
$DGS	BEG_BLK, ??bb05_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 01BH,		00H,	077H
$DGS	END_BLK, ??eb05_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 01FH
$DGS	BEG_BLK, ??bb06_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 023H,		00H,	00H
$DGS	END_BLK, ??eb06_vreg_ctr_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 027H
$DGS	END_FUN, ??ef_vreg_ctr_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 02AH
$DGS	GLV_SYM, _vreg_ctr_after_read,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	088H,	00H,	00H
$DGS	BEG_FUN, ??bf_vreg_ctr_after_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 0161H,		02H,	082H
$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
$DGS	BEG_BLK, ??bb00_vreg_ctr_after_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 05H,		00H,	00H
$DGS	END_BLK, ??eb00_vreg_ctr_after_read,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	END_FUN, ??ef_vreg_ctr_after_read,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 012H
$DGS	GLV_SYM, _set_irq,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	0A1H,	00H,	00H
$DGS	BEG_FUN, ??bf_set_irq,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 018AH,		04H,	08FH
$DGS	FUN_ARG, _irqreg,	02H,	0FFFFH,	0CH,	09H,	00H,	00H
$DGS	FUN_ARG, _irq_flg,	0AH,	0FFFFH,	0CH,	09H,	00H,	00H
$DGS	AUT_VAR, _tot,		01H,	0FFFFH,	0CH,	01H,	00H,	00H
$DGS	BEG_BLK, ??bb00_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 05H,		00H,	091H
$DGS	BEG_BLK, ??bb01_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 07H,		00H,	095H
$DGS	END_BLK, ??eb01_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 07H
$DGS	BEG_BLK, ??bb02_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0AH,		00H,	099H
$DGS	END_BLK, ??eb02_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0AH
$DGS	BEG_BLK, ??bb03_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0BH,		00H,	00H
$DGS	END_BLK, ??eb03_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0BH
$DGS	END_BLK, ??eb00_set_irq,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0CH
$DGS	END_FUN, ??ef_set_irq,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 0EH
$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	026H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	060H,	060H,	00H,	00H,	00H,	00H
$DGS	GLV_SYM, _irq_readed,	U,	U,	034CH,	027H,	00H,	00H
$DGS	GLV_SYM, _vreg_twl,	U,	U,	0CH,	02H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
$DGS	GLV_SYM, _set_rtc,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_vcom_set,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _renge_task_immed_add,	U,	U,	0CH,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_firm_update,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _do_command0,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_PM_LCD_on,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_PM_LCD_off,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_PM_BL_set,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _rtc_alarm_dirty,	U,	U,	034CH,	02H,	00H,	00H
$DGS	GLV_SYM, _acc_hosu_set,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _acc_read,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _acc_write,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _clear_hosu_hist,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _rtc_buf_reflesh,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _hosu_read,	U,	U,	0CH,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _tski_mcu_info_read,	U,	U,	0AH,	02H,	01H,	02H
$DGS	AUX_FUN, 013H,		U,	U,	00H,	00H,	00H

	EXTRN	_vreg_twl
	EXTRN	_set_rtc
	EXTRN	_tski_vcom_set
	EXTRN	_renge_task_immed_add
	EXTRN	_tski_firm_update
	EXTRN	_do_command0
	EXTRN	_tski_PM_LCD_on
	EXTRN	_tski_PM_LCD_off
	EXTRN	_tski_PM_BL_set
	EXTRN	_acc_hosu_set
	EXTRN	_acc_read
	EXTRN	_acc_write
	EXTRN	_clear_hosu_hist
	EXTRN	_rtc_buf_reflesh
	EXTRN	_hosu_read
	EXTRN	_tski_mcu_info_read
	EXTBIT	_rtc_alarm_dirty
	PUBLIC	_vreg_ctr
	PUBLIC	_irq_readed
	PUBLIC	_vreg_ctr_init
	PUBLIC	_vreg_ctr_write
	PUBLIC	_vreg_ctr_read
	PUBLIC	_vreg_ctr_after_read
	PUBLIC	_set_irq

@@BITS	BSEG
_irq_readed	DBIT

@@CNST	CSEG	MIRRORP
_lpf_coeff:	DB	01H	; 1
	DB	02H	; 2
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	00H	; 0
	DB	0FEH	; 254
	DB	0FBH	; 251
	DB	0F7H	; 247
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0FAH	; 250
	DB	04H	; 4
	DB	012H	; 18
	DB	025H	; 37
	DB	038H	; 56
	DB	04DH	; 77
	DB	05FH	; 95
	DB	06EH	; 110
	DB	077H	; 119
	DB	07AH	; 122
	DB	077H	; 119
	DB	06EH	; 110
	DB	05FH	; 95
	DB	04DH	; 77
	DB	038H	; 56
	DB	025H	; 37
	DB	012H	; 18
	DB	04H	; 4
	DB	0FAH	; 250
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0F7H	; 247
	DB	0FBH	; 251
	DB	0FEH	; 254
	DB	00H	; 0
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	02H	; 2
	DB	01H	; 1
	DB	(1)

@@R_INIT	CSEG	UNIT64KP

@@INIT	DSEG	BASEP

@@DATA	DSEG	BASEP
_vreg_ctr:	DS	(96)
?L0073:	DS	(2)

@@R_INIS	CSEG	UNIT64KP

@@INIS	DSEG	SADDRP

@@DATS	DSEG	SADDRP

@@CNSTL	CSEG	PAGE64KP

@@RLINIT	CSEG	UNIT64KP

@@INITL	DSEG	UNIT64KP

@@DATAL	DSEG	UNIT64KP

@@CALT	CSEG	CALLT0

; Sub-Routines created by CC78K0R

ROM_CODE	CSEG	BASE
bs_S0105:
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,h						;[INF] 1, 1
	mov	_vreg_ctr[b],a					;[INF] 3, 1
	ret							;[INF] 1, 6
es_S0105:

ROM_CODE	CSEG	BASE
bs_S0106:
	movw	de,#loww (_vreg_twl+1)				;[INF] 3, 1
	mov	a,[de]						;[INF] 1, 1
	or	a,x						;[INF] 2, 1
	mov	[de],a						;[INF] 1, 1
	ret							;[INF] 1, 6
es_S0106:

ROM_CODE	CSEG	BASE
bs_S0104:
	mov	c,a						;[INF] 1, 1
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,c						;[INF] 1, 1
	mov	_vreg_ctr[b],a					;[INF] 3, 1
	ret							;[INF] 1, 6
es_S0104:

ROM_CODE	CSEG	BASE
bs_F0102:
	shrw	ax,8						;[INF] 2, 1
	push	ax						;[INF] 1, 1
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	subw	ax,#030H	; 48 				;[INF] 3, 1
	call	!_set_rtc					;[INF] 3, 3
	pop	ax						;[INF] 1, 1
	ret							;[INF] 1, 6
es_F0102:

ROM_CODE	CSEG	BASE
bs_S0103:
	mov	a,h						;[INF] 1, 1
	and	a,#03FH	; 63 					;[INF] 2, 1
	mov	c,a						;[INF] 1, 1
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,c						;[INF] 1, 1
	mov	_vreg_ctr[b],a					;[INF] 3, 1
	ret							;[INF] 1, 6
es_S0103:

ROM_CODE	CSEG	BASE
bs_F0101:
	and	a,#03FH	; 63 					;[INF] 2, 1
	shrw	ax,8						;[INF] 2, 1
	push	ax						;[INF] 1, 1
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	subw	ax,#030H	; 48 				;[INF] 3, 1
	call	!_set_rtc					;[INF] 3, 3
	pop	ax						;[INF] 1, 1
	ret							;[INF] 1, 6
es_F0101:

; *** Sub-Routine Information ***
;
; $SUB bs_F0101
;      CODE SIZE= 15 bytes
;
; $SUB bs_F0102
;      CODE SIZE= 13 bytes
;
; $SUB bs_S0103
;      CODE SIZE= 11 bytes
;
; $SUB bs_S0104
;      CODE SIZE= 8 bytes
;
; $SUB bs_S0105
;      CODE SIZE= 7 bytes
;
; $SUB bs_S0106
;      CODE SIZE= 8 bytes

; End of Sub-Routines

; line     1 : /* ========================================================
; line     2 : 
; line     3 : CTR MCU I2Cレジスタ
; line     4 : 
; line     5 :   ====================================================== */
; line     6 : #include "incs.h"
; line     7 : #include "vreg_ctr.h"
; line     8 : #include "rtc.h"
; line     9 : #include "led.h"
; line    10 : #include "accero.h"
; line    11 : #include "pm.h"
; line    12 : 
; line    13 : #include <fsl.h>
; line    14 : #include "fsl_user.h"
; line    15 : 
; line    16 : extern u8 mcu_info_read();  // task_misc.c
; line    17 : 
; line    18 : 
; line    19 : 
; line    20 : // ********************************************************
; line    21 : u8      vreg_ctr[VREG_C_ENDMARK_];
; line    22 : 
; line    23 : bit     irq_readed;  // AAA型のため。
; line    24 : 
; line    25 : extern bit update;
; line    26 : extern u16 pool[];
; line    27 : 
; line    28 : 
; line    29 : // ********************************************************
; line    30 : extern task_status_immed tski_firm_update();
; line    31 : extern task_status_immed tski_mcu_info_read();
; line    32 : 
; line    33 : // ********************************************************
; line    34 : #ifdef _MCU_BSR_
; line    35 : #define IICAMK     IICAMK1
; line    36 : #endif
; line    37 : 
; line    38 : 
; line    39 : // ********************************************************
; line    40 : // 非ゼロの初期値の指定が必要なアドレス
; line    41 : void vreg_ctr_init(  )
; line    42 : {

ROM_CODE	CSEG	BASE
_vreg_ctr_init:
$DGL	1,39
??bf_vreg_ctr_init:
; line    43 :     vreg_ctr[VREG_C_LED_BRIGHT] = 0xFF;
$DGL	0,2
	mov	!_vreg_ctr+40,#0FFH	; 255 			;[INF] 4, 1
; line    44 : 
; line    45 : #ifdef _PMIC_TWL_
; line    46 :     vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR;
; line    47 : #else
; line    48 :     vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR | 0x10;
$DGL	0,7
	mov	!_vreg_ctr,#010H	; 16 			;[INF] 4, 1
; line    49 : #endif
; line    50 :     vreg_ctr[VREG_C_MCU_VER_MINOR] = MCU_VER_MINOR;
$DGL	0,9
	mov	!_vreg_ctr+1,#010H	; 16 			;[INF] 4, 1
; line    51 : 
; line    52 :     vreg_ctr[VREG_C_VCOM_T] = VCOM_DEFAULT_T;
$DGL	0,11
	mov	!_vreg_ctr+3,#05CH	; 92 			;[INF] 4, 1
; line    53 :     vreg_ctr[VREG_C_VCOM_B] = VCOM_DEFAULT_B;
$DGL	0,12
	mov	!_vreg_ctr+4,#05FH	; 95 			;[INF] 4, 1
; line    54 : }
$DGL	0,13
??ef_vreg_ctr_init:
	ret							;[INF] 1, 6
??ee_vreg_ctr_init:
; line    55 : 
; line    56 : 
; line    57 : 
; line    58 : 
; line    59 : // ********************************************************
; line    60 : // I2C仮想レジスタに書きます。
; line    61 : //　引数 adrs は内部アドレス
; line    62 : //  　書けないアドレスにアクセスした場合、何もしません。
; line    63 : // ●書き込んだ結果、I2C_mcu通信が発生する場合、renge_task_immed
;              _add()
; line    64 : //  を使用しないと、I2C_mcu使用中でエラー終了した場合にリトライし
;              ません。
; line    65 : void vreg_ctr_write( u8 adrs, u8 data )
; line    66 : {
_vreg_ctr_write:
$DGL	1,45
	push	hl						;[INF] 1, 1
	mov	a,[sp+6]					;[INF] 2, 1
	movw	hl,ax						;[INF] 1, 1
??bf_vreg_ctr_write:
; line    67 :     if( adrs >= VREG_C_ENDMARK_ )
$DGL	0,2
	mov	a,l						;[INF] 1, 1
	cmp	a,#060H	; 96 					;[INF] 2, 1
	skc							;[INF] 2, 1
	br	!?L0067						;[INF] 3, 3
; line    68 :         return;
; line    69 : 
; line    70 :     switch ( adrs )
$DGL	0,5
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	onew	bc						;[INF] 1, 1
	movw	de,#02H	; 2 					;[INF] 3, 1
	subw	ax,de						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0008						;[INF] 3, 3
	decw	ax						;[INF] 1, 1
	subw	ax,bc						;[INF] 1, 1
	skh							;[INF] 2, 1
	br	!?L0009						;[INF] 3, 3
	decw	ax						;[INF] 1, 1
	subw	ax,bc						;[INF] 1, 1
	skh							;[INF] 2, 1
	br	!?L0010						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0011						;[INF] 3, 3
	subw	ax,#011H	; 17 				;[INF] 3, 1
	subw	ax,#05H	; 5 					;[INF] 3, 1
	sknc							;[INF] 2, 1
	br	!?L0012						;[INF] 3, 3
	subw	ax,#03H	; 3 					;[INF] 3, 1
	sknz							;[INF] 2, 1
	br	!?L0013						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0015						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0014						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0038						;[INF] 3, 3
	decw	ax						;[INF] 1, 1
	subw	ax,#04H	; 4 					;[INF] 3, 1
	sknc							;[INF] 2, 1
	br	!?L0016						;[INF] 3, 3
	subw	ax,#00H	; 0 					;[INF] 3, 1
	sknz							;[INF] 2, 1
	br	!?L0018						;[INF] 3, 3
	decw	ax						;[INF] 1, 1
	subw	ax,#05H	; 5 					;[INF] 3, 1
	sknc							;[INF] 2, 1
	br	!?L0019						;[INF] 3, 3
	subw	ax,de						;[INF] 1, 1
	subw	ax,bc						;[INF] 1, 1
	skh							;[INF] 2, 1
	br	!?L0020						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0021						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0022						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0023						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0024						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0025						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0026						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0027						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0028						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0029						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0030						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0031						;[INF] 3, 3
	subw	ax,#04H	; 4 					;[INF] 3, 1
	sknz							;[INF] 2, 1
	br	!?L0032						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0033						;[INF] 3, 3
	subw	ax,de						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0034						;[INF] 3, 3
	subw	ax,bc						;[INF] 1, 1
	sknz							;[INF] 2, 1
	br	!?L0035						;[INF] 3, 3
	subw	ax,#07H	; 7 					;[INF] 3, 1
	subw	ax,#03H	; 3 					;[INF] 3, 1
	sknc							;[INF] 2, 1
	br	!?L0036						;[INF] 3, 3
	subw	ax,#00H	; 0 					;[INF] 3, 1
	sknz							;[INF] 2, 1
	br	!?L0037						;[INF] 3, 3
	subw	ax,de						;[INF] 1, 1
	subw	ax,#010H	; 16 				;[INF] 3, 1
	sknc							;[INF] 2, 1
	br	!?L0017						;[INF] 3, 3
	br	!?L0067						;[INF] 3, 3
; line    71 :     {
??bb00_vreg_ctr_write:
; line    72 : 
; line    73 :     case ( VREG_C_MCU_STATUS ):
?L0008:
; line    74 :         vreg_ctr[adrs] = data;
$DGL	0,9
	call	!bs_S0105					;[INF] 3, 3
; line    75 :         vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( ( data & 0xC0 ) >>
;               6 );
$DGL	0,10
	and	a,#0C0H	; 192 					;[INF] 2, 1
	shr	a,6						;[INF] 2, 1
	mov	!_vreg_twl+3,a					;[INF] 3, 1
; line    76 :         break;
$DGL	0,11
	br	!?L0067						;[INF] 3, 3
; line    77 : 
; line    78 :     case ( VREG_C_VCOM_T ):
?L0009:
; line    79 :     case ( VREG_C_VCOM_B ):
; line    80 :         renge_task_immed_add( tski_vcom_set );
$DGL	0,15
	movw	ax,#loww (_tski_vcom_set)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line    81 :         vreg_ctr[adrs] = data;
$DGL	0,16
	call	!bs_S0105					;[INF] 3, 3
; line    82 :         break;
$DGL	0,17
	br	!?L0067						;[INF] 3, 3
; line    83 : 
; line    84 :     case ( VREG_C_DBG1 ):
?L0010:
; line    85 :     case ( VREG_C_DBG2 ):
; line    86 :         vreg_ctr[adrs] = data;
$DGL	0,21
	call	!bs_S0105					;[INF] 3, 3
; line    87 :         break;
$DGL	0,22
	br	!?L0067						;[INF] 3, 3
; line    88 :     case ( VREG_C_DBG3 ):
?L0011:
; line    89 :         vreg_ctr[adrs] = data;
$DGL	0,24
	call	!bs_S0105					;[INF] 3, 3
; line    90 :         if( ( vreg_ctr[VREG_C_DBG1] == 'j' )
; line    91 :             && ( vreg_ctr[VREG_C_DBG2] == 'h' )
; line    92 :             && ( data == 'l' ) )
$DGL	0,27
	cmp	!_vreg_ctr+5,#06AH	; 106 			;[INF] 4, 1
	bnz	$?L0041						;[INF] 2, 4
	cmp	!_vreg_ctr+6,#068H	; 104 			;[INF] 4, 1
	bnz	$?L0041						;[INF] 2, 4
	cmp	a,#06CH	; 108 					;[INF] 2, 1
	bnz	$?L0041						;[INF] 2, 4
; line    93 :         {
??bb01_vreg_ctr_write:
; line    94 :             renge_task_immed_add( tski_firm_update );
$DGL	0,29
	movw	ax,#loww (_tski_firm_update)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line    95 :             IICAMK = 1;
$DGL	0,30
	set1	MK2H.3						;[INF] 3, 2
??eb01_vreg_ctr_write:
; line    96 :         }
?L0041:
; line    97 :         break;
$DGL	0,32
	br	!?L0067						;[INF] 3, 3
; line    98 : 
; line    99 :     case ( VREG_C_IRQ_MASK0 ):
?L0012:
; line   100 :     case ( VREG_C_IRQ_MASK1 ):
; line   101 :     case ( VREG_C_IRQ_MASK2 ):
; line   102 :     case ( VREG_C_IRQ_MASK3 ):
; line   103 :     case ( VREG_C_IRQ_MASK4 ):
; line   104 :         vreg_ctr[adrs] = data;
$DGL	0,39
	call	!bs_S0105					;[INF] 3, 3
; line   105 :         break;
$DGL	0,40
	br	!?L0067						;[INF] 3, 3
; line   106 : 
; line   107 :     case ( VREG_C_COMMAND0 ):
?L0013:
; line   108 :         vreg_ctr[adrs] |= data;
$DGL	0,43
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	addw	ax,#loww (_vreg_ctr)				;[INF] 3, 1
	movw	de,ax						;[INF] 1, 1
	mov	a,[de]						;[INF] 1, 1
	or	a,h						;[INF] 2, 1
	mov	[de],a						;[INF] 1, 1
; line   109 :         if( data != 0 )
$DGL	0,44
	mov	a,h						;[INF] 1, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0043						;[INF] 2, 4
; line   110 :         {
??bb02_vreg_ctr_write:
; line   111 :             renge_task_immed_add( do_command0 );
$DGL	0,46
	movw	ax,#loww (_do_command0)				;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
??eb02_vreg_ctr_write:
; line   112 :         }
?L0043:
; line   113 :         break;
$DGL	0,48
	br	!?L0067						;[INF] 3, 3
; line   114 : 
; line   115 :     case ( VREG_C_COMMAND2 ):
?L0014:
; line   116 :         // こちらからの完了割り込みを待ってくれないそうです。 #-
;              ω-) 何のための割り込みだ
; line   117 :         // 液晶電源
; line   118 :         if(( data & REG_BIT_CMD_LCD_ON ) != 0 )
$DGL	0,53
	mov	a,h						;[INF] 1, 1
	and	a,#02H	; 2 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0045						;[INF] 2, 4
; line   119 :         {
??bb03_vreg_ctr_write:
; line   120 :             renge_task_immed_add( tski_PM_LCD_on );
$DGL	0,55
	movw	ax,#loww (_tski_PM_LCD_on)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
??eb03_vreg_ctr_write:
; line   121 :         }
$DGL	0,56
	br	$?L0047						;[INF] 2, 3
?L0045:
; line   122 :         else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 )
$DGL	0,57
	mov	a,h						;[INF] 1, 1
	and	a,#01H	; 1 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0047						;[INF] 2, 4
; line   123 :         {
??bb04_vreg_ctr_write:
; line   124 :             renge_task_immed_add( tski_PM_LCD_off );
$DGL	0,59
	movw	ax,#loww (_tski_PM_LCD_off)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
??eb04_vreg_ctr_write:
; line   125 :         }
?L0047:
; line   126 : 
; line   127 :         // バックライト設定
; line   128 :         /// 今のところさらに細かくは分けないけど…
; line   129 :         if(( data & REG_BITS_CMD_BL ) != 0 )
$DGL	0,64
	mov	a,h						;[INF] 1, 1
	and	a,#03CH	; 60 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0049						;[INF] 2, 4
; line   130 :         {
??bb05_vreg_ctr_write:
; line   131 :             vreg_ctr[adrs] = ( data & REG_BITS_CMD_BL );
$DGL	0,66
	mov	a,h						;[INF] 1, 1
	and	a,#03CH	; 60 					;[INF] 2, 1
	call	!bs_S0104					;[INF] 3, 3
; line   132 :             renge_task_immed_add( tski_PM_BL_set );
$DGL	0,67
	movw	ax,#loww (_tski_PM_BL_set)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
??eb05_vreg_ctr_write:
; line   133 :         }
?L0049:
; line   134 :         break;
$DGL	0,69
	br	!?L0067						;[INF] 3, 3
; line   135 : 
; line   136 :     case ( VREG_C_COMMAND1 ):
?L0015:
; line   137 :         if( data != 0 )
$DGL	0,72
	mov	a,h						;[INF] 1, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0051						;[INF] 2, 4
; line   138 :         {
??bb06_vreg_ctr_write:
; line   139 :             // TWLに割り込みを入れる
; line   140 :             /// 実際に割り込みを入れるのはSoC
; line   141 :             vreg_twl[REG_TWL_INT_ADRS_IRQ]  = ( ( data & REG_BIT
;              _SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00;  
;               //pwsw_det
$DGL	0,76
	and	a,#01H	; 1 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0053						;[INF] 2, 4
	movw	ax,#08H	; 8 					;[INF] 3, 1
	br	$?L0054						;[INF] 2, 3
?L0053:
	clrw	ax						;[INF] 1, 1
?L0054:
	mov	a,x						;[INF] 1, 1
	mov	!_vreg_twl+1,a					;[INF] 3, 1
; line   142 :             vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT
;              _SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00;    
;                  //reset_req
$DGL	0,77
	mov	a,h						;[INF] 1, 1
	and	a,#02H	; 2 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0055						;[INF] 2, 4
	onew	ax						;[INF] 1, 1
	br	$?L0056						;[INF] 2, 3
?L0055:
	clrw	ax						;[INF] 1, 1
?L0056:
	call	!bs_S0106					;[INF] 3, 3
; line   143 : 
; line   144 :             vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT
;              _SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00;    //of
;              f_req
$DGL	0,79
	mov	a,h						;[INF] 1, 1
	and	a,#04H	; 4 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0057						;[INF] 2, 4
	onew	ax						;[INF] 1, 1
	incw	ax						;[INF] 1, 1
	br	$?L0058						;[INF] 2, 3
?L0057:
	clrw	ax						;[INF] 1, 1
?L0058:
	call	!bs_S0106					;[INF] 3, 3
; line   145 : 
; line   146 :             vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT
;              _SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00;    
;                //batt_low
$DGL	0,81
	mov	a,h						;[INF] 1, 1
	and	a,#08H	; 8 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0059						;[INF] 2, 4
	movw	ax,#020H	; 32 				;[INF] 3, 1
	br	$?L0060						;[INF] 2, 3
?L0059:
	clrw	ax						;[INF] 1, 1
?L0060:
	call	!bs_S0106					;[INF] 3, 3
; line   147 :             vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT
;              _SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00;
;                //batt_empty
$DGL	0,82
	mov	a,h						;[INF] 1, 1
	and	a,#010H	; 16 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0061						;[INF] 2, 4
	movw	ax,#010H	; 16 				;[INF] 3, 1
	br	$?L0062						;[INF] 2, 3
?L0061:
	clrw	ax						;[INF] 1, 1
?L0062:
	call	!bs_S0106					;[INF] 3, 3
; line   148 : 
; line   149 :             vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT
;              _SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00
;              ;      //vol_changed
$DGL	0,84
	mov	a,h						;[INF] 1, 1
	and	a,#020H	; 32 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0063						;[INF] 2, 4
	movw	ax,#040H	; 64 				;[INF] 3, 1
	br	$?L0064						;[INF] 2, 3
?L0063:
	clrw	ax						;[INF] 1, 1
?L0064:
	call	!bs_S0106					;[INF] 3, 3
??eb06_vreg_ctr_write:
; line   150 :         }
?L0051:
; line   151 :         break;
$DGL	0,86
	br	!?L0067						;[INF] 3, 3
; line   152 : 
; line   153 :     case ( VREG_C_DBG20 ):
?L0016:
; line   154 :     case ( VREG_C_DBG21 ):
; line   155 :     case ( VREG_C_DBG22 ):
; line   156 :     case ( VREG_C_DBG23 ):
; line   157 :         vreg_ctr[adrs] = data;
$DGL	0,92
	call	!bs_S0105					;[INF] 3, 3
; line   158 :         break;
$DGL	0,93
	br	!?L0067						;[INF] 3, 3
; line   159 : 
; line   160 :     case ( VREG_C_FREE_0 ):
?L0017:
; line   161 :     case ( VREG_C_FREE_1 ):
; line   162 :     case ( VREG_C_FREE_2 ):
; line   163 :     case ( VREG_C_FREE_3 ):
; line   164 :     case ( VREG_C_FREE_4 ):
; line   165 :     case ( VREG_C_FREE_5 ):
; line   166 :     case ( VREG_C_FREE_6 ):
; line   167 :     case ( VREG_C_FREE_7 ):
; line   168 :     case ( VREG_C_FREE_8 ):
; line   169 :     case ( VREG_C_FREE_9 ):
; line   170 :     case ( VREG_C_FREE_A ):
; line   171 :     case ( VREG_C_FREE_B ):
; line   172 :     case ( VREG_C_FREE_C ):
; line   173 :     case ( VREG_C_FREE_D ):
; line   174 :     case ( VREG_C_FREE_E ):
; line   175 :     case ( VREG_C_FREE_F ):
; line   176 :         vreg_ctr[adrs] = data;
$DGL	0,111
	call	!bs_S0105					;[INF] 3, 3
; line   177 :         break;
$DGL	0,112
	br	!?L0067						;[INF] 3, 3
; line   178 : 
; line   179 :     case ( VREG_C_LED_BRIGHT ):
?L0018:
; line   180 :         vreg_ctr[adrs] = data;
$DGL	0,115
	call	!bs_S0105					;[INF] 3, 3
; line   181 :         break;
$DGL	0,116
	br	!?L0067						;[INF] 3, 3
; line   182 : 
; line   183 :     case ( VREG_C_LED_POW ):
?L0019:
; line   184 :     case ( VREG_C_LED_WIFI ):
; line   185 :     case ( VREG_C_LED_CAM ):
; line   186 :     case ( VREG_C_LED_TUNE ):
; line   187 :     case ( VREG_C_LED_NOTIFY ):
; line   188 :         vreg_ctr[adrs] = data & 0x0F;
$DGL	0,123
	mov	a,h						;[INF] 1, 1
	and	a,#0FH	; 15 					;[INF] 2, 1
	call	!bs_S0104					;[INF] 3, 3
; line   189 :         break;
$DGL	0,124
	br	!?L0067						;[INF] 3, 3
; line   190 : 
; line   191 :     /// 非同期で動いているためここでは書かない。
; line   192 :     // 予約するだけでstopで書く
; line   193 :     case ( VREG_C_RTC_SEC ):
?L0020:
; line   194 :     case ( VREG_C_RTC_MIN ):
; line   195 :         set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F );
$DGL	0,130
	mov	a,h						;[INF] 1, 1
	and	a,#07FH	; 127 					;[INF] 2, 1
	call	!bs_F0102					;[INF] 3, 3
; line   196 :         break;
$DGL	0,131
	br	!?L0067						;[INF] 3, 3
; line   197 : 
; line   198 :     case ( VREG_C_RTC_HOUR ):
?L0021:
; line   199 :         set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F );
$DGL	0,134
	mov	a,h						;[INF] 1, 1
	call	!bs_F0101					;[INF] 3, 3
; line   200 :         break;
$DGL	0,135
	br	!?L0067						;[INF] 3, 3
; line   201 : 
; line   202 :     case ( VREG_C_RTC_YOBI ):
?L0022:
; line   203 :         set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 );
$DGL	0,138
	mov	a,h						;[INF] 1, 1
	and	a,#07H	; 7 					;[INF] 2, 1
	call	!bs_F0102					;[INF] 3, 3
; line   204 :         break;
$DGL	0,139
	br	!?L0067						;[INF] 3, 3
; line   205 : 
; line   206 :     case ( VREG_C_RTC_DAY ):
?L0023:
; line   207 :         set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F );
$DGL	0,142
	mov	a,h						;[INF] 1, 1
	call	!bs_F0101					;[INF] 3, 3
; line   208 :         break;
$DGL	0,143
	br	!?L0067						;[INF] 3, 3
; line   209 : 
; line   210 :     case ( VREG_C_RTC_MONTH ):
?L0024:
; line   211 :         set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F );
$DGL	0,146
	mov	a,h						;[INF] 1, 1
	and	a,#01FH	; 31 					;[INF] 2, 1
	call	!bs_F0102					;[INF] 3, 3
; line   212 :         break;
$DGL	0,147
	br	$?L0067						;[INF] 2, 3
; line   213 : 
; line   214 :     case ( VREG_C_RTC_YEAR ):
?L0025:
; line   215 :         set_rtc( adrs - VREG_C_RTC_SEC, data );
$DGL	0,150
	mov	a,h						;[INF] 1, 1
	call	!bs_F0102					;[INF] 3, 3
; line   216 :         break;
$DGL	0,151
	br	$?L0067						;[INF] 2, 3
; line   217 : 
; line   218 :     case ( VREG_C_RTC_COMP ):
?L0026:
; line   219 :         vreg_ctr[adrs] = data;
$DGL	0,154
	call	!bs_S0105					;[INF] 3, 3
; line   220 :         SUBCUD = data;
$DGL	0,155
	mov	SUBCUD,a					;[INF] 2, 1
; line   221 :         break;
$DGL	0,156
	br	$?L0067						;[INF] 2, 3
; line   222 : 
; line   223 :     case ( VREG_C_RTC_ALARM_MIN ):
?L0027:
; line   224 :         vreg_ctr[adrs] = ( data & 0x7F );
$DGL	0,159
	mov	a,h						;[INF] 1, 1
	and	a,#07FH	; 127 					;[INF] 2, 1
	call	!bs_S0104					;[INF] 3, 3
; line   225 :         rtc_alarm_dirty = 1;
$DGL	0,160
	set1	_rtc_alarm_dirty				;[INF] 3, 2
; line   226 :         break;
$DGL	0,161
	br	$?L0067						;[INF] 2, 3
; line   227 : 
; line   228 :     case ( VREG_C_RTC_ALARM_HOUR ):
?L0028:
; line   229 :         vreg_ctr[adrs] = ( data & 0x3F );
$DGL	0,164
	call	!bs_S0103					;[INF] 3, 3
; line   230 :         rtc_alarm_dirty = 1;
$DGL	0,165
	set1	_rtc_alarm_dirty				;[INF] 3, 2
; line   231 :         break;
$DGL	0,166
	br	$?L0067						;[INF] 2, 3
; line   232 : 
; line   233 :         // 書くだけでよい
; line   234 :     case ( VREG_C_RTC_ALARM_DAY ):
?L0029:
; line   235 :         vreg_ctr[adrs] = ( data & 0x3F );
$DGL	0,170
	call	!bs_S0103					;[INF] 3, 3
; line   236 :         break;
$DGL	0,171
	br	$?L0067						;[INF] 2, 3
; line   237 : 
; line   238 :     case ( VREG_C_RTC_ALARM_MONTH ):
?L0030:
; line   239 :         vreg_ctr[adrs] = ( data & 0x1F );
$DGL	0,174
	mov	a,h						;[INF] 1, 1
	and	a,#01FH	; 31 					;[INF] 2, 1
	call	!bs_S0104					;[INF] 3, 3
; line   240 :         break;
$DGL	0,175
	br	$?L0067						;[INF] 2, 3
; line   241 : 
; line   242 :     case ( VREG_C_RTC_ALARM_YEAR ):
?L0031:
; line   243 :         vreg_ctr[adrs] = data;
$DGL	0,178
	call	!bs_S0105					;[INF] 3, 3
; line   244 :         break;
$DGL	0,179
	br	$?L0067						;[INF] 2, 3
; line   245 : 
; line   246 : 
; line   247 :     case ( VREG_C_ACC_CONFIG ):
?L0032:
; line   248 :         vreg_ctr[adrs] = data;
$DGL	0,183
	call	!bs_S0105					;[INF] 3, 3
; line   249 :         renge_task_immed_add( acc_hosu_set );
$DGL	0,184
	movw	ax,#loww (_acc_hosu_set)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line   250 :         break;
$DGL	0,185
	br	$?L0067						;[INF] 2, 3
; line   251 : 
; line   252 :     case ( VREG_C_ACC_R_ADRS ):
?L0033:
; line   253 :         vreg_ctr[adrs] = data;
$DGL	0,188
	call	!bs_S0105					;[INF] 3, 3
; line   254 :         renge_task_immed_add( acc_read );
$DGL	0,189
	movw	ax,#loww (_acc_read)				;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line   255 :         break;
$DGL	0,190
	br	$?L0067						;[INF] 2, 3
; line   256 : 
; line   257 :     case ( VREG_C_ACC_W_ADRS ):
?L0034:
; line   258 :         vreg_ctr[adrs] = data;
$DGL	0,193
	call	!bs_S0105					;[INF] 3, 3
; line   259 :         break;
$DGL	0,194
	br	$?L0067						;[INF] 2, 3
; line   260 : 
; line   261 :     case ( VREG_C_ACC_W_BUF ):
?L0035:
; line   262 :         vreg_ctr[adrs] = data;
$DGL	0,197
	call	!bs_S0105					;[INF] 3, 3
; line   263 :         renge_task_immed_add( acc_write );
$DGL	0,198
	movw	ax,#loww (_acc_write)				;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line   264 :         break;
$DGL	0,199
	br	$?L0067						;[INF] 2, 3
; line   265 : 
; line   266 :     case ( VREG_C_ACC_HOSU_L ):
?L0036:
; line   267 :     case ( VREG_C_ACC_HOSU_M ):
; line   268 :     case ( VREG_C_ACC_HOSU_H ):
; line   269 :         vreg_ctr[adrs] = data;
$DGL	0,204
	call	!bs_S0105					;[INF] 3, 3
; line   270 :         break;
$DGL	0,205
	br	$?L0067						;[INF] 2, 3
; line   271 : 
; line   272 :     case ( VREG_C_ACC_HOSU_SETTING ):
?L0037:
; line   273 :         if( ( data & 0x01 ) != 0 )
$DGL	0,208
	mov	a,h						;[INF] 1, 1
	and	a,#01H	; 1 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0067						;[INF] 2, 4
; line   274 :         {
??bb07_vreg_ctr_write:
; line   275 :             clear_hosu_hist(); // 履歴クリア
$DGL	0,210
	call	!_clear_hosu_hist				;[INF] 3, 3
??eb07_vreg_ctr_write:
; line   276 :         }
; line   277 :         break;
$DGL	0,212
	br	$?L0067						;[INF] 2, 3
; line   278 : 
; line   279 :     case ( VREG_C_COMMAND3 ):
?L0038:
; line   280 :         vreg_ctr[adrs] = data;
$DGL	0,215
	call	!bs_S0105					;[INF] 3, 3
; line   281 :         switch ( data )
$DGL	0,216
	shrw	ax,8						;[INF] 2, 1
	subw	ax,#072H	; 114 				;[INF] 3, 1
	bz	$?L0068						;[INF] 2, 4
	subw	ax,#05H	; 5 					;[INF] 3, 1
	sknz							;[INF] 2, 1
; line   282 :         {
??bb08_vreg_ctr_write:
; line   283 :         case ( 'r' ):
?L0068:
; line   284 :             // 割り込みルーチンからFSLライブラリを呼ぶのは禁止の
;              ため
; line   285 : //            renge_task_immed_add( tski_mcu_reset );
; line   286 : //            break;
; line   287 : 
; line   288 :         case ( 'w' ):
; line   289 :             // WDTで再起動（テスト向け）
; line   290 :             WDTE = 0xAA;
$DGL	0,225
	mov	WDTE,#0AAH	; 170 				;[INF] 3, 1
; line   291 :             break;
??eb08_vreg_ctr_write:
; line   292 :         }
?L0067:
??eb00_vreg_ctr_write:
; line   293 :     }
; line   294 :     return;
; line   295 : }
$DGL	0,230
??ef_vreg_ctr_write:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_vreg_ctr_write:
; line   296 : 
; line   297 : 
; line   298 : 
; line   299 : // ********************************************************
; line   300 : // I2C仮想レジスタから読みます。
; line   301 : // 戻り： xx データ
; line   302 : // 注意：次のアドレスの準備で呼ばれる ので、
; line   303 : //       リードされたらクリアなどは気をつける
; line   304 : u8 vreg_ctr_read( u8 adrs )
; line   305 : {
_vreg_ctr_read:
$DGL	1,89
	push	hl						;[INF] 1, 1
	movw	hl,ax						;[INF] 1, 1
??bf_vreg_ctr_read:
; line   306 :     static u16 rsub_temp;
; line   307 : 
; line   308 :     // RTCは読み出し途中に繰り上がるのを避けるため
; line   309 :     if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR 
;              ) )
$DGL	0,5
	mov	a,l						;[INF] 1, 1
	cmp	a,#030H	; 48 					;[INF] 2, 1
	bc	$?L0074						;[INF] 2, 4
	cmp	a,#037H	; 55 					;[INF] 2, 1
	bnc	$?L0074						;[INF] 2, 4
; line   310 :     {
??bb00_vreg_ctr_read:
; line   311 :         rtc_buf_reflesh(  );
$DGL	0,7
	call	!_rtc_buf_reflesh				;[INF] 3, 3
??eb00_vreg_ctr_read:
; line   312 :     }
$DGL	0,8
	br	$?L0084						;[INF] 2, 3
?L0074:
; line   313 :     else if( adrs == VREG_C_MCU_STATUS )
$DGL	0,9
	mov	a,l						;[INF] 1, 1
	cmp	a,#02H	; 2 					;[INF] 2, 1
	bnz	$?L0076						;[INF] 2, 4
; line   314 :     {
??bb01_vreg_ctr_read:
; line   315 :         return( vreg_ctr[ VREG_C_MCU_STATUS ] | ( ( vreg_twl[ RE
;              G_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) );
$DGL	0,11
	mov	a,!_vreg_twl+3					;[INF] 3, 1
	and	a,#03H	; 3 					;[INF] 2, 1
	shrw	ax,8						;[INF] 2, 1
	shlw	ax,6						;[INF] 2, 1
	xch	a,x						;[INF] 1, 1
	or	a,!_vreg_ctr+2					;[INF] 3, 1
	xch	a,x						;[INF] 1, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0072						;[INF] 2, 3
??eb01_vreg_ctr_read:
; line   316 :     }
?L0076:
; line   317 :     else if( adrs == VREG_C_ACC_HOSU_HIST )
$DGL	0,13
	mov	a,l						;[INF] 1, 1
	cmp	a,#04FH	; 79 					;[INF] 2, 1
	bnz	$?L0078						;[INF] 2, 4
; line   318 :     {
??bb02_vreg_ctr_read:
; line   319 :         return( hosu_read() );
$DGL	0,15
	call	!_hosu_read					;[INF] 3, 3
	clrb	b						;[INF] 1, 1
	br	$?L0072						;[INF] 2, 3
??eb02_vreg_ctr_read:
; line   320 :     }
?L0078:
; line   321 :     else if( adrs == VREG_C_RTC_SEC_FINE_L )
$DGL	0,17
	mov	a,l						;[INF] 1, 1
	cmp	a,#03DH	; 61 					;[INF] 2, 1
	bnz	$?L0080						;[INF] 2, 4
; line   322 :     {
??bb03_vreg_ctr_read:
; line   323 :         rsub_temp = RSUBC;
$DGL	0,19
	movw	ax,RSUBC					;[INF] 2, 1
	movw	!?L0073,ax	; rsub_temp 			;[INF] 3, 1
; line   324 :         return( (u8)( rsub_temp & 0xFF ) );
$DGL	0,20
	mov	x,!?L0073	; rsub_temp 			;[INF] 3, 1
	clrb	a						;[INF] 1, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0072						;[INF] 2, 3
??eb03_vreg_ctr_read:
; line   325 :     }
?L0080:
; line   326 :     else if( adrs == VREG_C_RTC_SEC_FINE_H )
$DGL	0,22
	mov	a,l						;[INF] 1, 1
	cmp	a,#03EH	; 62 					;[INF] 2, 1
	bnz	$?L0082						;[INF] 2, 4
; line   327 :     {
??bb04_vreg_ctr_read:
; line   328 :         return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) );
$DGL	0,24
	mov	x,!?L0073+1	; rsub_temp 			;[INF] 3, 1
	clrb	a						;[INF] 1, 1
	movw	bc,ax						;[INF] 1, 1
	br	$?L0072						;[INF] 2, 3
??eb04_vreg_ctr_read:
; line   329 :     }
?L0082:
; line   330 :     else if( adrs == VREG_C_INFO )
$DGL	0,26
	mov	a,l						;[INF] 1, 1
	cmp	a,#07FH	; 127 					;[INF] 2, 1
	bnz	$?L0084						;[INF] 2, 4
; line   331 :     {
??bb05_vreg_ctr_read:
; line   332 :         renge_task_immed_add( tski_mcu_info_read );
$DGL	0,28
	movw	ax,#loww (_tski_mcu_info_read)			;[INF] 3, 1
	call	!_renge_task_immed_add				;[INF] 3, 3
; line   333 :         IICAMK = 1;
$DGL	0,29
	set1	MK2H.3						;[INF] 3, 2
; line   334 :         return( 0x4A );
$DGL	0,30
	movw	bc,#04AH	; 74 				;[INF] 3, 1
	br	$?L0072						;[INF] 2, 3
??eb05_vreg_ctr_read:
; line   335 :     }
?L0084:
; line   336 : 
; line   337 : #if 1
; line   338 :     if( adrs >= VREG_C_ENDMARK_ )
$DGL	0,34
	mov	a,l						;[INF] 1, 1
	cmp	a,#060H	; 96 					;[INF] 2, 1
	bc	$?L0086						;[INF] 2, 4
; line   339 :     {
??bb06_vreg_ctr_read:
; line   340 :         // VREG_C_INFO > VREG_C_ENDMARK_ なので
; line   341 :         // いじるときは注意
; line   342 :         return( 0xEE );
$DGL	0,38
	movw	bc,#0EEH	; 238 				;[INF] 3, 1
	br	$?L0072						;[INF] 2, 3
??eb06_vreg_ctr_read:
; line   343 :     }
?L0086:
; line   344 : #endif
; line   345 :     return ( vreg_ctr[adrs] );
$DGL	0,41
	mov	a,l						;[INF] 1, 1
	mov	b,a						;[INF] 1, 1
	mov	a,_vreg_ctr[b]					;[INF] 3, 1
	shrw	ax,8						;[INF] 2, 1
	movw	bc,ax						;[INF] 1, 1
; line   346 : }
?L0072:
$DGL	0,42
??ef_vreg_ctr_read:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_vreg_ctr_read:
; line   347 : 
; line   348 : 
; line   349 : 
; line   350 : // ********************************************************
; line   351 : // I2C仮想レジスタから読まれて何かするレジスタ
; line   352 : void vreg_ctr_after_read( u8 adrs )
; line   353 : {
_vreg_ctr_after_read:
$DGL	1,125
	push	hl						;[INF] 1, 1
	movw	hl,ax						;[INF] 1, 1
??bf_vreg_ctr_after_read:
; line   354 : 
; line   355 :     // 割り込みフラグはリードでクリア
; line   356 :     switch( adrs )
$DGL	0,4
	movw	ax,hl						;[INF] 1, 1
	clrb	a						;[INF] 1, 1
	subw	ax,#010H	; 16 				;[INF] 3, 1
	subw	ax,#05H	; 5 					;[INF] 3, 1
	bnc	$?L0092						;[INF] 2, 4
; line   357 :     {
??bb00_vreg_ctr_after_read:
; line   358 :       case VREG_C_IRQ0:
; line   359 :       case VREG_C_IRQ1:
; line   360 :       case VREG_C_IRQ2:
; line   361 :       case VREG_C_IRQ3:
; line   362 :       case VREG_C_IRQ4:
; line   363 :         vreg_ctr[ adrs ] = 0;
$DGL	0,11
	mov	a,l						;[INF] 1, 1
	mov	c,a						;[INF] 1, 1
	mov	_vreg_ctr[c],#00H	; 0 			;[INF] 4, 1
; line   364 :         irq_readed = 1;
$DGL	0,12
	set1	_irq_readed					;[INF] 3, 2
; line   365 :         break;
; line   366 : 
; line   367 :       default:
?L0092:
; line   368 :         break;
??eb00_vreg_ctr_after_read:
; line   369 :     }
; line   370 : }
$DGL	0,18
??ef_vreg_ctr_after_read:
	pop	hl						;[INF] 1, 1
	ret							;[INF] 1, 6
??ee_vreg_ctr_after_read:
; line   371 : 
; line   372 : 
; line   373 : 
; line   374 : 
; line   375 : 
; line   376 : 
; line   377 : /***************************************************************
;              ***************
; line   378 :   割り込みを入れる
; line   379 :   割り込みマスクが必要と言うことでこんな事をする羽目になりました
; line   380 :  ***************************************************************
;              **************/
; line   381 : #if 0
; line   382 : // マスクされてたら、フラグは立てるが、割り込みは入れない。
; line   383 : #define set_irq( irqreg, bitpos )               \
; line   384 : {                                               \
; line   385 :   vreg_ctr[ irqreg ] |= bitpos;                 \
; line   386 :   if( ( vreg_ctr[ irqreg+8 ] & bitpos ) == 0 ){ \
; line   387 :     IRQ0_ast;                                   \
; line   388 :   }                                             \
; line   389 : }
; line   390 : #endif
; line   391 : 
; line   392 : // マスクされてたら、フラグも立てず、割り込みも入れない。
; line   393 : void set_irq( u8 irqreg, u8 irq_flg )
; line   394 : {
_set_irq:
$DGL	1,136
	di							;[INF] 3, 4
	push	hl						;[INF] 1, 1
	push	ax						;[INF] 1, 1
	push	ax						;[INF] 1, 1
	movw	hl,sp						;[INF] 3, 1
??bf_set_irq:
; line   395 :     u8 tot;
; line   396 : 
; line   397 :     DI();
; line   398 :     if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 ){
$DGL	0,5
	mov	a,[hl+2]	; irqreg 			;[INF] 2, 1
	mov	b,a						;[INF] 1, 1
	mov	a,_vreg_ctr+8[b]				;[INF] 3, 1
	and	a,[hl+10]	; irq_flg 			;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bnz	$?L0097						;[INF] 2, 4
??bb00_set_irq:
; line   399 :         vreg_ctr[ irqreg ] |= irq_flg;
$DGL	0,6
	mov	a,[hl+2]	; irqreg 			;[INF] 2, 1
	shrw	ax,8						;[INF] 2, 1
	addw	ax,#loww (_vreg_ctr)				;[INF] 3, 1
	movw	de,ax						;[INF] 1, 1
	mov	a,[de]						;[INF] 1, 1
	or	a,[hl+10]	; irq_flg 			;[INF] 2, 1
	mov	[de],a						;[INF] 1, 1
; line   400 :         IRQ0_neg;   // 一瞬上げて落とし直す。
$DGL	0,7
??bb01_set_irq:
	set1	PM7.6						;[INF] 3, 2
??eb01_set_irq:
; line   401 : //        EI();
; line   402 :         tot = 0;
$DGL	0,9
	mov	[hl+1],#00H	; tot,0 			;[INF] 3, 1
; line   403 :         while( !IRQ0 && ( ++tot != 0 ) ){;}   // O.D.なのでちゃん
;              とあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良)
$DGL	0,10
?L0099:
	bt	P7.6,$?L0100					;[INF] 4, 5
	inc	[hl+1]	; tot 					;[INF] 3, 2
	mov	a,[hl+1]	; tot 				;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bnz	$?L0099						;[INF] 2, 4
??bb02_set_irq:
??eb02_set_irq:
?L0100:
; line   404 :         IRQ0_ast;
$DGL	0,11
??bb03_set_irq:
	clr1	P7.6						;[INF] 3, 2
	clr1	PM7.6						;[INF] 3, 2
??eb03_set_irq:
??eb00_set_irq:
; line   405 :     }
?L0097:
; line   406 :     EI();
; line   407 : }
$DGL	0,14
??ef_set_irq:
	addw	sp,#04H						;[INF] 2, 1
	pop	hl						;[INF] 1, 1
	ei							;[INF] 3, 4
	ret							;[INF] 1, 6
??ee_set_irq:

@@CODEL	CSEG

@@BASE	CSEG	BASE
	END


; *** Code Information ***
;
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c
;
; $FUNC vreg_ctr_init(42)
;	void=(void)
;	CODE SIZE= 21 bytes, CLOCK_SIZE= 11 clocks, STACK_SIZE= 0 bytes
;
; $FUNC vreg_ctr_write(66)
;	void=(unsigned char adrs:x, unsigned char data:[sp+6])
;	CODE SIZE= 660 bytes, CLOCK_SIZE= 961 clocks, STACK_SIZE= 12 bytes
;
; $CALL renge_task_immed_add(80)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(94)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(111)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(120)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(124)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(132)
;	bc=(pointer:ax)
;
; $CALL set_rtc(195)
;	void=(int:ax, int:[sp+4])
;
; $CALL set_rtc(199)
;	void=(int:ax, int:[sp+4])
;
; $CALL set_rtc(203)
;	void=(int:ax, int:[sp+4])
;
; $CALL set_rtc(207)
;	void=(int:ax, int:[sp+4])
;
; $CALL set_rtc(211)
;	void=(int:ax, int:[sp+4])
;
; $CALL set_rtc(215)
;	void=(int:ax, int:[sp+4])
;
; $CALL renge_task_immed_add(249)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(254)
;	bc=(pointer:ax)
;
; $CALL renge_task_immed_add(263)
;	bc=(pointer:ax)
;
; $CALL clear_hosu_hist(275)
;	void=(void)
;
; $FUNC vreg_ctr_read(305)
;	bc=(unsigned char adrs:x)
;	CODE SIZE= 117 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 6 bytes
;
; $CALL rtc_buf_reflesh(311)
;	void=(void)
;
; $CALL hosu_read(319)
;	bc=(void)
;
; $CALL renge_task_immed_add(332)
;	bc=(pointer:ax)
;
; $FUNC vreg_ctr_after_read(353)
;	void=(unsigned char adrs:x)
;	CODE SIZE= 23 bytes, CLOCK_SIZE= 22 clocks, STACK_SIZE= 2 bytes
;
; $FUNC set_irq(394)
;	void=(unsigned char irqreg:x, unsigned char irq_flg:[sp+4])
;	CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 6 bytes

; Target chip : uPD79F0104
; Device file : E1.00b