diff --git a/branches/0.10(X3)/WDT.c b/branches/0.10(X3)/WDT.c new file mode 100644 index 0000000..c39323c --- /dev/null +++ b/branches/0.10(X3)/WDT.c @@ -0,0 +1,14 @@ +#pragma sfr + + +#include "incs_loader.h" + + + +//========================================================= +// ウォッチドッグタイマのリスタート +// 0xACはマジック +void WDT_Restart( void ) +{ + WDTE = WDT_RESTART_MAGIC; +} diff --git a/branches/0.10(X3)/WDT.h b/branches/0.10(X3)/WDT.h new file mode 100644 index 0000000..6c6e9e4 --- /dev/null +++ b/branches/0.10(X3)/WDT.h @@ -0,0 +1,18 @@ +#ifndef _WDT_ +#define _WDT_ + + + +//========================================================= +#define WDT_RESTART_MAGIC 0xAC + + + +//========================================================= +void WDT_Restart( void ); + +// 規定値以外を書くと例外でリセットがかかる +#define mcu_reset WDTE = 0x5A + + +#endif diff --git a/branches/0.10(X3)/WDT.prn b/branches/0.10(X3)/WDT.prn new file mode 100644 index 0000000..578123e --- /dev/null +++ b/branches/0.10(X3)/WDT.prn @@ -0,0 +1,154 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\WDT.asm +Para-file: +In-file: inter_asm\WDT.asm +Obj-file: WDT.rel +Prn-file: WDT.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no WDT.c + 6 6 ; In-file : WDT.c + 7 7 ; Asm-file : inter_asm\WDT.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, WDT.c + 18 18 $DGS MOD_NAM, WDT, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 026H, 01H, 02H + 36 36 $DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H + 37 37 $DGS BEG_FUN, ??bf_WDT_Restart, U, U, 00H, 065H, 01H, 00H + 38 38 $DGS AUX_BEG, 0CH, 00H, 019H + 39 39 $DGS END_FUN, ??ef_WDT_Restart, U, U, 00H, 065H, 01H, 00H + 40 40 $DGS AUX_END, 03H + 41 41 + 42 42 PUBLIC _WDT_Restart + 43 43 + 44 44 ----- @@BITS BSEG + 45 45 + 46 46 ----- @@CNST CSEG MIRRORP + 47 47 + 48 48 ----- @@R_INIT CSEG UNIT64KP + 49 49 + 50 50 ----- @@INIT DSEG BASEP + 51 51 + 52 52 ----- @@DATA DSEG BASEP + 53 53 + 54 54 ----- @@R_INIS CSEG UNIT64KP + 55 55 + 56 56 ----- @@INIS DSEG SADDRP + 57 57 + 58 58 ----- @@DATS DSEG SADDRP + 59 59 + 60 60 ----- LDR_CNSL CSEG PAGE64KP + 61 61 + 62 62 ----- @@RLINIT CSEG UNIT64KP + 63 63 + 64 64 ----- @@INITL DSEG UNIT64KP + 65 65 + 66 66 ----- @@DATAL DSEG UNIT64KP + 67 67 + 68 68 ----- @@CALT CSEG CALLT0 + 69 69 + 70 70 ; line 1 : #pragma sfr + 71 71 ; line 2 : + 72 72 ; line 3 : + 73 73 ; line 4 : #include "incs_loader.h" + 74 74 ; line 5 : + 75 75 ; line 6 : + 76 76 ; line 7 : + 77 77 ; line 8 : //========================================================= + 78 78 ; line 9 : // ウォッチドッグタイマのリスタート + 79 79 ; line 10 : // 0xACはマジック + 80 80 ; line 11 : void WDT_Restart( void ) + 81 81 ; line 12 : { + 82 82 + 83 83 ----- LDR_CODE CSEG BASE + 84 84 00000 _WDT_Restart: + 85 85 $DGL 1,19 + 86 86 00000 ??bf_WDT_Restart: + 87 87 ; line 13 : WDTE = WDT_RESTART_MAGIC; + 88 88 $DGL 0,2 + 89 89 00000 CEABAC mov WDTE,#0ACH ; 172 ;[INF] 3, 1 + 90 90 ; line 14 : } + 91 91 $DGL 0,3 + 92 92 00003 ??ef_WDT_Restart: + 93 93 00003 D7 ret ;[INF] 1, 6 + 94 94 00004 ??ee_WDT_Restart: + 95 95 + 96 96 ----- LDR_CODL CSEG + 97 97 + 98 98 ----- @@BASE CSEG BASE + 99 99 END + 100 100 + 101 101 + 102 102 ; *** Code Information *** + 103 103 ; + 104 104 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c + 105 105 ; + 106 106 ; $FUNC WDT_Restart(12) + 107 107 ; void=(void) + 108 108 ; CODE SIZE= 4 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes + 109 109 + 110 110 ; Target chip : uPD79F0104 + 111 111 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00000H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00000H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H LDR_CNSL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00004H LDR_CODE +00000 00000H LDR_CODL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/WDT.rel b/branches/0.10(X3)/WDT.rel new file mode 100644 index 0000000..cea6a36 Binary files /dev/null and b/branches/0.10(X3)/WDT.rel differ diff --git a/branches/0.10(X3)/__info.bat b/branches/0.10(X3)/__info.bat new file mode 100644 index 0000000..34a10fb --- /dev/null +++ b/branches/0.10(X3)/__info.bat @@ -0,0 +1,3 @@ +@echo off +set VF="C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\vf78k0r.exe" +%VF% -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -obsr.lmf "..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r\s0rm.rel" -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFFFFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -b"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib" -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i"C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r" -dbsr_mcu.dr -s -w0 loader.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot.rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg_thre_det2.rel -vx diff --git a/branches/0.10(X3)/accero.c b/branches/0.10(X3)/accero.c new file mode 100644 index 0000000..fe850b5 --- /dev/null +++ b/branches/0.10(X3)/accero.c @@ -0,0 +1,250 @@ +/* ======================================================== +　加速度センサ関係 +・データ更新完了でデータを吸い上げ手レジスタを更新、CPUに割り込み +・フラグが立っていれば歩数カウント +・加速度センサ割り込みからタスクを登録して下さい。（I2Cの競合回避などがあるので） + + ======================================================== */ +#pragma SFR +#pragma NOP +#pragma HALT +#pragma STOP +#pragma ROT +// rorb, rolb, rorw, rolw +#pragma MUL +#pragma BCD + +#include "incs.h" +#include + +// ======================================================== +// レジスタ名 +#define ACC_REG_WHOAMI 0x0F +#define ACC_REG_CTRL1 0x20 +#define ACC_REG_CTRL5 0x24 +#define ACC_REG_X 0x28 + +// ビット位置 +#define ACC_bP_PM0 5 +#define ACC_bP_DR0 3 + +// ビット設定値 +#define ACC_BITS_PM_PDN 0 +#define ACC_BITS_PM_NORM 1 +#define ACC_BITS_PM_LP0R5 2 +#define ACC_BITS_PM_LP1 3 +#define ACC_BITS_PM_LP2 4 +#define ACC_BITS_PM_LP5 5 +#define ACC_BITS_PM_LP10 6 + +#define ACC_BITS_DR_50Hz 0 +#define ACC_BITS_DR_100Hz 1 +#define ACC_BITS_DR_400Hz 2 +#define ACC_BITS_DR_1000Hz 3 + +#define ACC_BITS_ALL_AXIS_ON 7 + + +#define VREG_BITMASK_ACC_CONF_ACQ ( 1 << 0 ) +#define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 ) + + + + +// ======================================================== +task_status tsk_soft_int( ); + + + +/* ======================================================== +　・割り込みを確認してデータを吸い上げ、レジスタに書き出します + ・本当であればコールバック関数を登録しておけばいいじゃんとなるのですが、 + I2Cが使用中だったら？とか考えると私ではそこまでできないのです。 + ・自動歩数計とかでも結局 + ======================================================== */ +task_status_immed tsk_cbk_accero( ) +{ // （疑似）isrから登録されます + +/* + if(( system_status.pwr_state == OFF ) || ( system_status.pwr_state == BT_CHARGE ) ) + { + return ( ERR_SUCCESS ); + } + else + { +*/ + // 加速度センサデータレジスタへの反映 + if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, &vreg_ctr[VREG_C_ACC_XL] ) + != ERR_SUCCESS ) + { + // 加速度センサが異常になったので止める + vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ ); +// vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; + acc_hosu_set(); + return ( ERR_SUCCESS ); // タスクの削除は必要 + } + else + { + // 正常時パス // + // 加速度更新＆割り込み + if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_ACQ ) != 0 ) && + ( system_status.pwr_state == ON ) + ) + { + set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY ); + // ゴミデータのカラ読み + if( ACC_VALID == 1 ) + { + u8 temp[6]; + iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, temp ); + } + } + if(( system_status.pwr_state != OFF ) && + ( system_status.pwr_state != BT_CHARGE ) && + ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_HOSU ) != 0 ) + ) + { + DBG_LED_WIFI_2_on; + pedometer(); // 歩数計 + DBG_LED_WIFI_2_off; + } + } + return ( ERR_SUCCESS ); +} + + + + + +/*======================================================= +　加速度センサ透過アクセス　リード + ========================================================*/ +task_status_immed acc_read( ) +{ + vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); +// vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); + vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; + if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) + { + IRQ0_ast; + } + return ( ERR_SUCCESS ); +} + + + +/*========================================================= +　加速度センサ透過アクセス　ライト + ========================================================*/ +task_status_immed acc_write( ) +{ + iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_ADRS], vreg_ctr[VREG_C_ACC_W_BUF] ); + vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; + if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) + { + IRQ0_ast; + } + return ( ERR_SUCCESS ); +} + + + +/*========================================================= +　自動歩数カウントモードにセット + todo 他のモードだったら止めたり、復帰させたり + 割り込みルーチンなどでカウント判定が必要 + ========================================================*/ +task_status_immed acc_hosu_set( ) +{ + u8 str_send_buf[4]; + + iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI ); + if( iic_mcu_bus_status == ERR_NOSLAVE ) + { + vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; +#ifdef _MCU_BSR_ +// PMK23 = 1; +#endif + return ( ERR_SUCCESS ); // とりあえず、タスクは削除しなくてはならない + }else{ + vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR; + } + + + str_send_buf[1] = 0x00; // ctrl2 HPF:normal, filterd, HPF for IRQ : dis/dis, HPF coeff:norm +#ifdef _MODEL_WM0_ +# ifdef _MODEL_WM0_TEG2_CTRC_ + str_send_buf[2] = 0x02; // 回路が一部違う +# else + + str_send_buf[2] = 0x10; // 3 IRQ pol :Active HI, Drive:Pushpull, + /// IRQ2flg latch: auto clear after read, IRQ2 conf: IRQ( fall,shock,...) + /// 1 : auto clear after read, conf: data ready +# endif +#else +# ifdef _MODEL_CTR_JIKKI_ + str_send_buf[2] = 0x10; +# else + str_send_buf[2] = 0x02; // 3 IRQ pol :Active HI, Drive:Pushpull, + /// IRQ2flg latch: auto clear after read, IRQ2 conf: IRQ( fall,shock,...) + /// 1 : auto clear after read, conf: data ready +# endif +#endif + str_send_buf[3] = 0x80; // ctrl3 block update:enable, MSB first, scale: +-2G(default), selftest: dis + + if( ( vreg_ctr[VREG_C_ACC_CONFIG] & + ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ ) ) == 0 ) + { +#ifdef _MCU_BSR_ + PMK23 = 1; +#endif + // 完全停止 + str_send_buf[0] = + ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | ACC_BITS_ALL_AXIS_ON ); + } + else + { +#ifdef _MCU_BSR_ + PMK23 = 0; +#endif + // 100Hz 自動取り込み + str_send_buf[0] = + ( ACC_BITS_PM_NORM << ACC_bP_PM0 + | ACC_BITS_DR_100Hz << ACC_bP_DR0 + | ACC_BITS_ALL_AXIS_ON ); + } + iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, str_send_buf ); + + // カラ読み + if( ACC_VALID == 1 ) + { + if( system_status.pwr_state == ON ) + { + u8 temp[6]; + iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, temp ); + } + } + return ( ERR_SUCCESS ); +} + + + +/* ======================================================== + 加速度センサ割り込み + I2Cが使用中かもしれないので、読み出しタスクの登録を行うのみ + ======================================================== */ +__interrupt void intp23_ACC_ready( ) +{ + EI(); + if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) + { + if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) ) + { + if( ACC_VALID ) + { + renge_task_immed_add( tsk_cbk_accero ); + } + } + } +} + diff --git a/branches/0.10(X3)/accero.h b/branches/0.10(X3)/accero.h new file mode 100644 index 0000000..1fd23eb --- /dev/null +++ b/branches/0.10(X3)/accero.h @@ -0,0 +1,14 @@ +#ifndef _accero_ +#define _accero_ + + +#include "jhl_defs.h" +#include "pedometer.h" + + +/////////////////////////////////////////////////////////// +task_status_immed tsk_cbk_accero( ); +task_status_immed acc_hosu_set( ); + + +#endif diff --git a/branches/0.10(X3)/accero.prn b/branches/0.10(X3)/accero.prn new file mode 100644 index 0000000..e118a6b --- /dev/null +++ b/branches/0.10(X3)/accero.prn @@ -0,0 +1,1027 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\accero.asm +Para-file: +In-file: inter_asm\accero.asm +Obj-file: accero.rel +Prn-file: accero.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no accero.c + 6 6 ; In-file : accero.c + 7 7 ; Asm-file : inter_asm\accero.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0B7H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, accero.c + 18 18 $DGS MOD_NAM, accero, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 82 82 $DGS AUX_TAG, 01H, 047H + 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 86 86 $DGS AUX_EOS, 041H, 01H + 87 87 $DGS LAB_SYM, bs_F0038, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_F0038, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 91 91 $DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 026H, 01H, 02H + 92 92 $DGS AUX_FUN, 041H, U, U, 067H, 00H, 00H + 93 93 $DGS BEG_FUN, ??bf_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H + 94 94 $DGS AUX_BEG, 042H, 06H, 04FH + 95 95 $DGS BEG_BLK, ??bb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_BEG, 0EH, 00H, 053H + 97 97 $DGS END_BLK, ??eb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_END, 014H + 99 99 $DGS BEG_BLK, ??bb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_BEG, 016H, 00H, 055H + 101 101 $DGS BEG_BLK, ??bb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_BEG, 01CH, 00H, 057H + 103 103 $DGS BEG_BLK, ??bb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_BEG, 020H, 00H, 05FH + 105 105 $DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H + 106 106 $DGS AUX_STR, 00H, 021H, 06H, 06H, 00H, 00H, 00H, 00H + 107 107 $DGS END_BLK, ??eb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_END, 023H + 109 109 $DGS END_BLK, ??eb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_END, 024H + 111 111 $DGS BEG_BLK, ??bb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_BEG, 029H, 00H, 00H + 113 113 $DGS END_BLK, ??eb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_END, 02DH + 115 115 $DGS END_BLK, ??eb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_END, 02EH + 117 117 $DGS END_FUN, ??ef_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H + 118 118 $DGS AUX_END, 030H + 119 119 $DGS GLV_SYM, _acc_read, U, U, 0AH, 026H, 01H, 02H + 120 120 $DGS AUX_FUN, 041H, U, U, 075H, 00H, 00H + 121 121 $DGS BEG_FUN, ??bf_acc_read, U, U, 00H, 065H, 01H, 00H + 122 122 $DGS AUX_BEG, 07BH, 00H, 06BH + 123 123 $DGS BEG_BLK, ??bb00_acc_read, U, U, 00H, 064H, 01H, 00H + 124 124 $DGS AUX_BEG, 06H, 00H, 06DH + 125 125 $DGS BEG_BLK, ??bb01_acc_read, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_BEG, 07H, 00H, 00H + 127 127 $DGS END_BLK, ??eb01_acc_read, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_END, 07H + 129 129 $DGS END_BLK, ??eb00_acc_read, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_END, 08H + 131 131 $DGS END_FUN, ??ef_acc_read, U, U, 00H, 065H, 01H, 00H + 132 132 $DGS AUX_END, 0AH + 133 133 $DGS GLV_SYM, _acc_write, U, U, 0AH, 026H, 01H, 02H + 134 134 $DGS AUX_FUN, 041H, U, U, 083H, 00H, 00H + 135 135 $DGS BEG_FUN, ??bf_acc_write, U, U, 00H, 065H, 01H, 00H + 136 136 $DGS AUX_BEG, 08CH, 00H, 079H + 137 137 $DGS BEG_BLK, ??bb00_acc_write, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_BEG, 05H, 00H, 07BH + 139 139 $DGS BEG_BLK, ??bb01_acc_write, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_BEG, 06H, 00H, 00H + 141 141 $DGS END_BLK, ??eb01_acc_write, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_END, 06H + 143 143 $DGS END_BLK, ??eb00_acc_write, U, U, 00H, 064H, 01H, 00H + 144 144 $DGS AUX_END, 07H + 145 145 $DGS END_FUN, ??ef_acc_write, U, U, 00H, 065H, 01H, 00H + 146 146 $DGS AUX_END, 09H + 147 147 $DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 026H, 01H, 02H + 148 148 $DGS AUX_FUN, 041H, U, U, 0A5H, 00H, 00H + 149 149 $DGS BEG_FUN, ??bf_acc_hosu_set, U, U, 00H, 065H, 01H, 00H + 150 150 $DGS AUX_BEG, 09EH, 0AH, 089H + 151 151 $DGS AUT_VAR, _str_send_buf, 06H, 0FFFFH, 0CH, 01H, 01H, 03H + 152 152 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H + 153 153 $DGS BEG_BLK, ??bb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_BEG, 06H, 00H, 08DH + 155 155 $DGS END_BLK, ??eb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_END, 0CH + 157 157 $DGS BEG_BLK, ??bb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_BEG, 0CH, 00H, 091H + 159 159 $DGS END_BLK, ??eb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_END, 0EH + 161 161 $DGS BEG_BLK, ??bb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 162 162 $DGS AUX_BEG, 028H, 00H, 095H + 163 163 $DGS END_BLK, ??eb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 164 164 $DGS AUX_END, 02FH + 165 165 $DGS BEG_BLK, ??bb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 166 166 $DGS AUX_BEG, 031H, 00H, 099H + 167 167 $DGS END_BLK, ??eb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_END, 03AH + 169 169 $DGS BEG_BLK, ??bb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_BEG, 03FH, 00H, 09BH + 171 171 $DGS BEG_BLK, ??bb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 172 172 $DGS AUX_BEG, 041H, 00H, 00H + 173 173 $DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H + 174 174 $DGS AUX_STR, 00H, 042H, 06H, 06H, 00H, 00H, 00H, 00H + 175 175 $DGS END_BLK, ??eb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 176 176 $DGS AUX_END, 044H + 177 177 $DGS END_BLK, ??eb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H + 178 178 $DGS AUX_END, 045H + 179 179 $DGS END_FUN, ??ef_acc_hosu_set, U, U, 00H, 065H, 01H, 00H + 180 180 $DGS AUX_END, 047H + 181 181 $DGS GLV_SYM, _intp23_ACC_ready, U, U, 0E001H, 026H, 01H, 02H + 182 182 $DGS AUX_FUN, 00H, U, U, 0B7H, 00H, 00H + 183 183 $DGS BEG_FUN, ??bf_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H + 184 184 $DGS AUX_BEG, 0EDH, 016H, 0A9H + 185 185 $DGS BEG_BLK, ??bb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 186 186 $DGS AUX_BEG, 04H, 00H, 0ABH + 187 187 $DGS BEG_BLK, ??bb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 188 188 $DGS AUX_BEG, 06H, 00H, 0ADH + 189 189 $DGS BEG_BLK, ??bb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 190 190 $DGS AUX_BEG, 08H, 00H, 00H + 191 191 $DGS END_BLK, ??eb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 192 192 $DGS AUX_END, 0AH + 193 193 $DGS END_BLK, ??eb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 194 194 $DGS AUX_END, 0BH + 195 195 $DGS END_BLK, ??eb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H + 196 196 $DGS AUX_END, 0CH + 197 197 $DGS END_FUN, ??ef_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H + 198 198 $DGS AUX_END, 0DH + 199 199 $DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H + 200 200 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 201 201 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 202 202 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 203 203 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 204 204 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 205 205 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 206 206 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 207 207 $DGS GLV_SYM, _pedometer, U, U, 01H, 02H, 01H, 02H + 208 208 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 209 209 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H + 210 210 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 211 211 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H + 212 212 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 213 213 $DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H + 214 214 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H + 215 215 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 216 216 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 217 217 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 218 218 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 219 219 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 220 220 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 221 221 + 222 222 EXTRN _iic_mcu_read + 223 223 EXTRN _vreg_ctr + 224 224 EXTRN _system_status + 225 225 EXTRN _set_irq + 226 226 EXTRN _pedometer + 227 227 EXTRN _iic_mcu_read_a_byte + 228 228 EXTRN _iic_mcu_write_a_byte + 229 229 EXTRN _iic_mcu_bus_status + 230 230 EXTRN _iic_mcu_write + 231 231 EXTRN _@SEGAX + 232 232 EXTRN _@SEGDE + 233 233 EXTRN _@RTARG0 + 234 234 EXTRN _renge_task_immed_add + 235 235 PUBLIC _tsk_cbk_accero + 236 236 PUBLIC _acc_read + 237 237 PUBLIC _acc_write + 238 238 PUBLIC _acc_hosu_set + 239 239 PUBLIC _intp23_ACC_ready + 240 240 + 241 241 ----- @@BITS BSEG + 242 242 + 243 243 ----- @@CNST CSEG MIRRORP + 244 244 00000 01 _lpf_coeff: DB 01H ; 1 + 245 245 00001 02 DB 02H ; 2 + 246 246 00002 02 DB 02H ; 2 + 247 247 00003 03 DB 03H ; 3 + 248 248 00004 03 DB 03H ; 3 + 249 249 00005 02 DB 02H ; 2 + 250 250 00006 00 DB 00H ; 0 + 251 251 00007 FE DB 0FEH ; 254 + 252 252 00008 FB DB 0FBH ; 251 + 253 253 00009 F7 DB 0F7H ; 247 + 254 254 0000A F3 DB 0F3H ; 243 + 255 255 0000B F0 DB 0F0H ; 240 + 256 256 0000C F0 DB 0F0H ; 240 + 257 257 0000D F3 DB 0F3H ; 243 + 258 258 0000E FA DB 0FAH ; 250 + 259 259 0000F 04 DB 04H ; 4 + 260 260 00010 12 DB 012H ; 18 + 261 261 00011 25 DB 025H ; 37 + 262 262 00012 38 DB 038H ; 56 + 263 263 00013 4D DB 04DH ; 77 + 264 264 00014 5F DB 05FH ; 95 + 265 265 00015 6E DB 06EH ; 110 + 266 266 00016 77 DB 077H ; 119 + 267 267 00017 7A DB 07AH ; 122 + 268 268 00018 77 DB 077H ; 119 + 269 269 00019 6E DB 06EH ; 110 + 270 270 0001A 5F DB 05FH ; 95 + 271 271 0001B 4D DB 04DH ; 77 + 272 272 0001C 38 DB 038H ; 56 + 273 273 0001D 25 DB 025H ; 37 + 274 274 0001E 12 DB 012H ; 18 + 275 275 0001F 04 DB 04H ; 4 + 276 276 00020 FA DB 0FAH ; 250 + 277 277 00021 F3 DB 0F3H ; 243 + 278 278 00022 F0 DB 0F0H ; 240 + 279 279 00023 F0 DB 0F0H ; 240 + 280 280 00024 F3 DB 0F3H ; 243 + 281 281 00025 F7 DB 0F7H ; 247 + 282 282 00026 FB DB 0FBH ; 251 + 283 283 00027 FE DB 0FEH ; 254 + 284 284 00028 00 DB 00H ; 0 + 285 285 00029 02 DB 02H ; 2 + 286 286 0002A 03 DB 03H ; 3 + 287 287 0002B 03 DB 03H ; 3 + 288 288 0002C 02 DB 02H ; 2 + 289 289 0002D 02 DB 02H ; 2 + 290 290 0002E 01 DB 01H ; 1 + 291 291 0002F 00 DB (1) + 292 292 + 293 293 ----- @@R_INIT CSEG UNIT64KP + 294 294 + 295 295 ----- @@INIT DSEG BASEP + 296 296 + 297 297 ----- @@DATA DSEG BASEP + 298 298 + 299 299 ----- @@R_INIS CSEG UNIT64KP + 300 300 + 301 301 ----- @@INIS DSEG SADDRP + 302 302 + 303 303 ----- @@DATS DSEG SADDRP + 304 304 + 305 305 ----- @@CNSTL CSEG PAGE64KP + 306 306 + 307 307 ----- @@RLINIT CSEG UNIT64KP + 308 308 + 309 309 ----- @@INITL DSEG UNIT64KP + 310 310 + 311 311 ----- @@DATAL DSEG UNIT64KP + 312 312 + 313 313 ----- @@CALT CSEG CALLT0 + 314 314 + 315 315 ; Sub-Routines created by CC78K0R + 316 316 + 317 317 ----- ROM_CODE CSEG BASE + 318 318 00000 bs_F0038: + 319 319 00000 C1 push ax ;[INF] 1, 1 + 320 320 00001 300600 movw ax,#06H ; 6 ;[INF] 3, 1 + 321 321 00004 C1 push ax ;[INF] 1, 1 + 322 322 00005 50A8 mov x,#0A8H ; 168 ;[INF] 2, 1 + 323 323 00007 C1 push ax ;[INF] 1, 1 + 324 324 00008 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 325 325 0000A RFD0000 call !_iic_mcu_read ;[INF] 3, 3 + 326 326 0000D 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 327 327 0000F D7 ret ;[INF] 1, 6 + 328 328 00010 es_F0038: + 329 329 + 330 330 ; *** Sub-Routine Information *** + 331 331 ; + 332 332 ; $SUB bs_F0038 + 333 333 ; CODE SIZE= 16 bytes + 334 334 + 335 335 ; End of Sub-Routines + 336 336 + 337 337 ; line 1 : /* ======================================================== + 338 338 ; line 2 : 　加速度センサ関係 + 339 339 ; line 3 : ・データ更新完了でデータを吸い上げ手レジスタを更新、CPUに割り込み + 340 340 ; line 4 : ・フラグが立っていれば歩数カウント + 341 341 ; line 5 : ・加速度センサ割り込みからタスクを登録して下さい。（I2Cの競合回避 + 342 342 ; などがあるので） + 343 343 ; line 6 : + 344 344 ; line 7 : ======================================================== */ + 345 345 ; line 8 : #pragma SFR + 346 346 ; line 9 : #pragma NOP + 347 347 ; line 10 : #pragma HALT + 348 348 ; line 11 : #pragma STOP + 349 349 ; line 12 : #pragma ROT + 350 350 ; line 13 : // rorb, rolb, rorw, rolw + 351 351 ; line 14 : #pragma MUL + 352 352 ; line 15 : #pragma BCD + 353 353 ; line 16 : + 354 354 ; line 17 : #include "incs.h" + 355 355 ; line 18 : #include + 356 356 ; line 19 : + 357 357 ; line 20 : // ======================================================== + 358 358 ; line 21 : // レジスタ名 + 359 359 ; line 22 : #define ACC_REG_WHOAMI 0x0F + 360 360 ; line 23 : #define ACC_REG_CTRL1 0x20 + 361 361 ; line 24 : #define ACC_REG_CTRL5 0x24 + 362 362 ; line 25 : #define ACC_REG_X 0x28 + 363 363 ; line 26 : + 364 364 ; line 27 : // ビット位置 + 365 365 ; line 28 : #define ACC_bP_PM0 5 + 366 366 ; line 29 : #define ACC_bP_DR0 3 + 367 367 ; line 30 : + 368 368 ; line 31 : // ビット設定値 + 369 369 ; line 32 : #define ACC_BITS_PM_PDN 0 + 370 370 ; line 33 : #define ACC_BITS_PM_NORM 1 + 371 371 ; line 34 : #define ACC_BITS_PM_LP0R5 2 + 372 372 ; line 35 : #define ACC_BITS_PM_LP1 3 + 373 373 ; line 36 : #define ACC_BITS_PM_LP2 4 + 374 374 ; line 37 : #define ACC_BITS_PM_LP5 5 + 375 375 ; line 38 : #define ACC_BITS_PM_LP10 6 + 376 376 ; line 39 : + 377 377 ; line 40 : #define ACC_BITS_DR_50Hz 0 + 378 378 ; line 41 : #define ACC_BITS_DR_100Hz 1 + 379 379 ; line 42 : #define ACC_BITS_DR_400Hz 2 + 380 380 ; line 43 : #define ACC_BITS_DR_1000Hz 3 + 381 381 ; line 44 : + 382 382 ; line 45 : #define ACC_BITS_ALL_AXIS_ON 7 + 383 383 ; line 46 : + 384 384 ; line 47 : + 385 385 ; line 48 : #define VREG_BITMASK_ACC_CONF_ACQ ( 1 << 0 ) + 386 386 ; line 49 : #define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 ) + 387 387 ; line 50 : + 388 388 ; line 51 : + 389 389 ; line 52 : + 390 390 ; line 53 : + 391 391 ; line 54 : // ======================================================== + 392 392 ; line 55 : task_status tsk_soft_int( ); + 393 393 ; line 56 : + 394 394 ; line 57 : + 395 395 ; line 58 : + 396 396 ; line 59 : /* ======================================================== + 397 397 ; line 60 : 　・割り込みを確認してデータを吸い上げ、レジスタに書き出します + 398 398 ; line 61 : ・本当であればコールバック関数を登録しておけばいいじゃんとなる + 399 399 ; のですが、 + 400 400 ; line 62 : I2Cが使用中だったら？とか考えると私ではそこまでできないのです。 + 401 401 ; line 63 : ・自動歩数計とかでも結局 + 402 402 ; line 64 : ======================================================== */ + 403 403 ; line 65 : task_status_immed tsk_cbk_accero( ) + 404 404 ; line 66 : { // （疑似）isrから登録されます + 405 405 + 406 406 ----- ROM_CODE CSEG BASE + 407 407 00010 _tsk_cbk_accero: + 408 408 $DGL 1,75 + 409 409 00010 C7 push hl ;[INF] 1, 1 + 410 410 00011 2006 subw sp,#06H ;[INF] 2, 1 + 411 411 00013 FBF8FF movw hl,sp ;[INF] 3, 1 + 412 412 00016 ??bf_tsk_cbk_accero: + 413 413 ; line 67 : + 414 414 ; line 68 : /* + 415 415 ; line 69 : if(( system_status.pwr_state == OFF ) || ( system_status.pwr + 416 416 ; _state == BT_CHARGE ) ) + 417 417 ; line 70 : { + 418 418 ; line 71 : return ( ERR_SUCCESS ); + 419 419 ; line 72 : } + 420 420 ; line 73 : else + 421 421 ; line 74 : { + 422 422 ; line 75 : */ + 423 423 ; line 76 : // 加速度センサデータレジスタへの反映 + 424 424 ; line 77 : if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6 + 425 425 ; , &vreg_ctr[VREG_C_ACC_XL] ) + 426 426 ; line 78 : != ERR_SUCCESS ) + 427 427 $DGL 0,13 + 428 428 00016 R344500 movw de,#loww (_vreg_ctr+69) ;[INF] 3, 1 + 429 429 00019 C5 push de ;[INF] 1, 1 + 430 430 0001A 300600 movw ax,#06H ; 6 ;[INF] 3, 1 + 431 431 0001D C1 push ax ;[INF] 1, 1 + 432 432 0001E 50A8 mov x,#0A8H ; 168 ;[INF] 2, 1 + 433 433 00020 C1 push ax ;[INF] 1, 1 + 434 434 00021 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 435 435 00023 RFD0000 call !_iic_mcu_read ;[INF] 3, 3 + 436 436 00026 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 437 437 00028 D2 cmp0 c ;[INF] 1, 1 + 438 438 00029 DD0D bz $?L0003 ;[INF] 2, 4 + 439 439 ; line 79 : { + 440 440 0002B ??bb00_tsk_cbk_accero: + 441 441 ; line 80 : // 加速度センサが異常になったので止める + 442 442 ; line 81 : vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_ + 443 443 ; HOSU | VREG_BITMASK_ACC_CONF_ACQ ); + 444 444 $DGL 0,16 + 445 445 0002B R344000 movw de,#loww (_vreg_ctr+64) ;[INF] 3, 1 + 446 446 0002E 89 mov a,[de] ;[INF] 1, 1 + 447 447 0002F 5CFC and a,#0FCH ; 252 ;[INF] 2, 1 + 448 448 00031 99 mov [de],a ;[INF] 1, 1 + 449 449 ; line 82 : // vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; + 450 450 ; line 83 : acc_hosu_set(); + 451 451 $DGL 0,18 + 452 452 00032 RFDBF00 call !_acc_hosu_set ;[INF] 3, 3 + 453 453 ; line 84 : return ( ERR_SUCCESS ); // タスクの削除は必要 + 454 454 $DGL 0,19 + 455 455 00035 F7 clrw bc ;[INF] 1, 1 + 456 456 00036 EF3C br $?L0002 ;[INF] 2, 3 + 457 457 00038 ??eb00_tsk_cbk_accero: + 458 458 ; line 85 : } + 459 459 00038 ?L0003: + 460 460 ; line 86 : else + 461 461 ; line 87 : { + 462 462 00038 ??bb01_tsk_cbk_accero: + 463 463 ; line 88 : // 正常時パス // + 464 464 ; line 89 : // 加速度更新＆割り込み + 465 465 ; line 90 : if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO + 466 466 ; NF_ACQ ) != 0 ) && + 467 467 $DGL 0,25 + 468 468 00038 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 469 469 0003B 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 470 470 0003D D1 cmp0 a ;[INF] 1, 1 + 471 471 0003E DD1C bz $?L0007 ;[INF] 2, 4 + 472 472 ; line 91 : ( system_status.pwr_state == ON ) + 473 473 $DGL 0,26 + 474 474 00040 R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 475 475 00044 DF16 bnz $?L0007 ;[INF] 2, 4 + 476 476 ; line 92 : ) + 477 477 ; line 93 : { + 478 478 00046 ??bb02_tsk_cbk_accero: + 479 479 ; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY ); + 480 480 $DGL 0,29 + 481 481 00046 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 482 482 00049 C1 push ax ;[INF] 1, 1 + 483 483 0004A A1 incw ax ;[INF] 1, 1 + 484 484 0004B RFD0000 call !_set_irq ;[INF] 3, 3 + 485 485 0004E C0 pop ax ;[INF] 1, 1 + 486 486 ; line 95 : // ゴミデータのカラ読み + 487 487 ; line 96 : if( ACC_VALID == 1 ) + 488 488 $DGL 0,31 + 489 489 0004F C7 push hl ;[INF] 1, 1 + 490 490 00050 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 + 491 491 00053 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 + 492 492 00055 C6 pop hl ;[INF] 1, 1 + 493 493 00056 DE04 bnc $?L0007 ;[INF] 2, 4 + 494 494 ; line 97 : { + 495 495 00058 ??bb03_tsk_cbk_accero: + 496 496 ; line 98 : u8 temp[6]; + 497 497 ; line 99 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 + 498 498 ; ), 6, temp ); + 499 499 $DGL 0,34 + 500 500 00058 17 movw ax,hl ;[INF] 1, 1 + 501 501 00059 RFD0000 call !bs_F0038 ;[INF] 3, 3 + 502 502 0005C ??eb03_tsk_cbk_accero: + 503 503 ; line 100 : } + 504 504 0005C ?L0007: + 505 505 0005C ??eb02_tsk_cbk_accero: + 506 506 ; line 101 : } + 507 507 ; line 102 : if(( system_status.pwr_state != OFF ) && + 508 508 ; line 103 : ( system_status.pwr_state != BT_CHARGE ) && + 509 509 $DGL 0,38 + 510 510 0005C R40000001 cmp !_system_status,#01H ; 1 ;[INF] 4, 1 + 511 511 00060 DD11 bz $?L0009 ;[INF] 2, 4 + 512 512 00062 R40000006 cmp !_system_status,#06H ; 6 ;[INF] 4, 1 + 513 513 00066 DD0B bz $?L0009 ;[INF] 2, 4 + 514 514 ; line 104 : ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO + 515 515 ; NF_HOSU ) != 0 ) + 516 516 $DGL 0,39 + 517 517 00068 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 518 518 0006B 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 519 519 0006D D1 cmp0 a ;[INF] 1, 1 + 520 520 0006E 61E8 skz ;[INF] 2, 1 + 521 521 ; line 105 : ) + 522 522 ; line 106 : { + 523 523 00070 ??bb04_tsk_cbk_accero: + 524 524 ; line 107 : DBG_LED_WIFI_2_on; + 525 525 ; line 108 : pedometer(); // 歩数計 + 526 526 $DGL 0,43 + 527 527 00070 RFD0000 call !_pedometer ;[INF] 3, 3 + 528 528 ; line 109 : DBG_LED_WIFI_2_off; + 529 529 00073 ??eb04_tsk_cbk_accero: + 530 530 ; line 110 : } + 531 531 00073 ?L0009: + 532 532 00073 ??eb01_tsk_cbk_accero: + 533 533 ; line 111 : } + 534 534 ; line 112 : return ( ERR_SUCCESS ); + 535 535 $DGL 0,47 + 536 536 00073 F7 clrw bc ;[INF] 1, 1 + 537 537 ; line 113 : } + 538 538 00074 ?L0002: + 539 539 $DGL 0,48 + 540 540 00074 ??ef_tsk_cbk_accero: + 541 541 00074 1006 addw sp,#06H ;[INF] 2, 1 + 542 542 00076 C6 pop hl ;[INF] 1, 1 + 543 543 00077 D7 ret ;[INF] 1, 6 + 544 544 00078 ??ee_tsk_cbk_accero: + 545 545 ; line 114 : + 546 546 ; line 115 : + 547 547 ; line 116 : + 548 548 ; line 117 : + 549 549 ; line 118 : + 550 550 ; line 119 : /*======================================================= + 551 551 ; line 120 : 　加速度センサ透過アクセス　リード + 552 552 ; line 121 : ========================================================*/ + 553 553 ; line 122 : task_status_immed acc_read( ) + 554 554 ; line 123 : { + 555 555 00078 _acc_read: + 556 556 $DGL 1,103 + 557 557 00078 ??bf_acc_read: + 558 558 ; line 124 : vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_AC + 559 559 ; CEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); + 560 560 $DGL 0,2 + 561 561 00078 RD94100 mov x,!_vreg_ctr+65 ;[INF] 3, 1 + 562 562 0007B F1 clrb a ;[INF] 1, 1 + 563 563 0007C C1 push ax ;[INF] 1, 1 + 564 564 0007D 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 565 565 0007F RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 566 566 00082 C0 pop ax ;[INF] 1, 1 + 567 567 00083 62 mov a,c ;[INF] 1, 1 + 568 568 00084 R9F4400 mov !_vreg_ctr+68,a ;[INF] 3, 1 + 569 569 ; line 125 : // vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_ + 570 570 ; ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); + 571 571 ; line 126 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; + 572 572 $DGL 0,4 + 573 573 00087 R71301100 set1 !_vreg_ctr+17.3 ;[INF] 4, 2 + 574 574 ; line 127 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) + 575 575 $DGL 0,5 + 576 576 0008B R8F1900 mov a,!_vreg_ctr+25 ;[INF] 3, 1 + 577 577 0008E 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 578 578 00090 D1 cmp0 a ;[INF] 1, 1 + 579 579 00091 DF06 bnz $?L0013 ;[INF] 2, 4 + 580 580 ; line 128 : { + 581 581 00093 ??bb00_acc_read: + 582 582 ; line 129 : IRQ0_ast; + 583 583 $DGL 0,7 + 584 584 00093 ??bb01_acc_read: + 585 585 00093 716307 clr1 P7.6 ;[INF] 3, 2 + 586 586 00096 716B27 clr1 PM7.6 ;[INF] 3, 2 + 587 587 00099 ??eb01_acc_read: + 588 588 00099 ??eb00_acc_read: + 589 589 ; line 130 : } + 590 590 00099 ?L0013: + 591 591 ; line 131 : return ( ERR_SUCCESS ); + 592 592 $DGL 0,9 + 593 593 00099 F7 clrw bc ;[INF] 1, 1 + 594 594 ; line 132 : } + 595 595 $DGL 0,10 + 596 596 0009A ??ef_acc_read: + 597 597 0009A D7 ret ;[INF] 1, 6 + 598 598 0009B ??ee_acc_read: + 599 599 ; line 133 : + 600 600 ; line 134 : + 601 601 ; line 135 : + 602 602 ; line 136 : /*========================================================= + 603 603 ; line 137 : 　加速度センサ透過アクセス　ライト + 604 604 ; line 138 : ========================================================*/ + 605 605 ; line 139 : task_status_immed acc_write( ) + 606 606 ; line 140 : { + 607 607 0009B _acc_write: + 608 608 $DGL 1,117 + 609 609 0009B ??bf_acc_write: + 610 610 ; line 141 : iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_A + 611 611 ; DRS], vreg_ctr[VREG_C_ACC_W_BUF] ); + 612 612 $DGL 0,2 + 613 613 0009B RD94400 mov x,!_vreg_ctr+68 ;[INF] 3, 1 + 614 614 0009E F1 clrb a ;[INF] 1, 1 + 615 615 0009F C1 push ax ;[INF] 1, 1 + 616 616 000A0 RD94300 mov x,!_vreg_ctr+67 ;[INF] 3, 1 + 617 617 000A3 C1 push ax ;[INF] 1, 1 + 618 618 000A4 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 619 619 000A6 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 620 620 000A9 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 621 621 ; line 142 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; + 622 622 $DGL 0,3 + 623 623 000AB R71301100 set1 !_vreg_ctr+17.3 ;[INF] 4, 2 + 624 624 ; line 143 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) + 625 625 $DGL 0,4 + 626 626 000AF R8F1900 mov a,!_vreg_ctr+25 ;[INF] 3, 1 + 627 627 000B2 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 628 628 000B4 D1 cmp0 a ;[INF] 1, 1 + 629 629 000B5 DF06 bnz $?L0017 ;[INF] 2, 4 + 630 630 ; line 144 : { + 631 631 000B7 ??bb00_acc_write: + 632 632 ; line 145 : IRQ0_ast; + 633 633 $DGL 0,6 + 634 634 000B7 ??bb01_acc_write: + 635 635 000B7 716307 clr1 P7.6 ;[INF] 3, 2 + 636 636 000BA 716B27 clr1 PM7.6 ;[INF] 3, 2 + 637 637 000BD ??eb01_acc_write: + 638 638 000BD ??eb00_acc_write: + 639 639 ; line 146 : } + 640 640 000BD ?L0017: + 641 641 ; line 147 : return ( ERR_SUCCESS ); + 642 642 $DGL 0,8 + 643 643 000BD F7 clrw bc ;[INF] 1, 1 + 644 644 ; line 148 : } + 645 645 $DGL 0,9 + 646 646 000BE ??ef_acc_write: + 647 647 000BE D7 ret ;[INF] 1, 6 + 648 648 000BF ??ee_acc_write: + 649 649 ; line 149 : + 650 650 ; line 150 : + 651 651 ; line 151 : + 652 652 ; line 152 : /*========================================================= + 653 653 ; line 153 : 　自動歩数カウントモードにセット + 654 654 ; line 154 : todo 他のモードだったら止めたり、復帰させたり + 655 655 ; line 155 : 割り込みルーチンなどでカウント判定が必要 + 656 656 ; line 156 : ========================================================*/ + 657 657 ; line 157 : task_status_immed acc_hosu_set( ) + 658 658 ; line 158 : { + 659 659 000BF _acc_hosu_set: + 660 660 $DGL 1,131 + 661 661 000BF C7 push hl ;[INF] 1, 1 + 662 662 000C0 200A subw sp,#0AH ;[INF] 2, 1 + 663 663 000C2 FBF8FF movw hl,sp ;[INF] 3, 1 + 664 664 000C5 ??bf_acc_hosu_set: + 665 665 ; line 159 : u8 str_send_buf[4]; + 666 666 ; line 160 : + 667 667 ; line 161 : iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI ); + 668 668 $DGL 0,4 + 669 669 000C5 300F00 movw ax,#0FH ; 15 ;[INF] 3, 1 + 670 670 000C8 C1 push ax ;[INF] 1, 1 + 671 671 000C9 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 672 672 000CB RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 673 673 000CE C0 pop ax ;[INF] 1, 1 + 674 674 ; line 162 : if( iic_mcu_bus_status == ERR_NOSLAVE ) + 675 675 $DGL 0,5 + 676 676 000CF R40000002 cmp !_iic_mcu_bus_status,#02H ; 2 ;[INF] 4, 1 + 677 677 000D3 DF07 bnz $?L0021 ;[INF] 2, 4 + 678 678 ; line 163 : { + 679 679 000D5 ??bb00_acc_hosu_set: + 680 680 ; line 164 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; + 681 681 $DGL 0,7 + 682 682 000D5 R71100E00 set1 !_vreg_ctr+14.1 ;[INF] 4, 2 + 683 683 ; line 165 : #ifdef _MCU_BSR_ + 684 684 ; line 166 : // PMK23 = 1; + 685 685 ; line 167 : #endif + 686 686 ; line 168 : return ( ERR_SUCCESS ); // とりあえず、タスクは削除しなく + 687 687 ; てはならない + 688 688 $DGL 0,11 + 689 689 000D9 F7 clrw bc ;[INF] 1, 1 + 690 690 000DA EF4A br $?L0020 ;[INF] 2, 3 + 691 691 000DC ??eb00_acc_hosu_set: + 692 692 ; line 169 : }else{ + 693 693 000DC ?L0021: + 694 694 000DC ??bb01_acc_hosu_set: + 695 695 ; line 170 : vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR; + 696 696 $DGL 0,13 + 697 697 000DC R71180E00 clr1 !_vreg_ctr+14.1 ;[INF] 4, 2 + 698 698 000E0 ??eb01_acc_hosu_set: + 699 699 ; line 171 : } + 700 700 ; line 172 : + 701 701 ; line 173 : + 702 702 ; line 174 : str_send_buf[1] = 0x00; // ctrl2 HPF:normal, filterd, H + 703 703 ; PF for IRQ : dis/dis, HPF coeff:norm + 704 704 $DGL 0,17 + 705 705 000E0 CC0700 mov [hl+7],#00H ; str_send_buf,0 ;[INF] 3, 1 + 706 706 ; line 175 : #ifdef _MODEL_WM0_ + 707 707 ; line 176 : # ifdef _MODEL_WM0_TEG2_CTRC_ + 708 708 ; line 177 : str_send_buf[2] = 0x02; // 回路が一部違う + 709 709 ; line 178 : # else + 710 710 ; line 179 : + 711 711 ; line 180 : str_send_buf[2] = 0x10; // 3 IRQ pol :Active HI, Dr + 712 712 ; ive:Pushpull, + 713 713 ; line 181 : /// IRQ2flg latch: auto cl + 714 714 ; ear after read, IRQ2 conf: IRQ( fall,shock,...) + 715 715 ; line 182 : /// 1 : auto cl + 716 716 ; ear after read, conf: data ready + 717 717 ; line 183 : # endif + 718 718 ; line 184 : #else + 719 719 ; line 185 : # ifdef _MODEL_CTR_JIKKI_ + 720 720 ; line 186 : str_send_buf[2] = 0x10; + 721 721 ; line 187 : # else + 722 722 ; line 188 : str_send_buf[2] = 0x02; // 3 IRQ pol :Active HI, Dr + 723 723 ; ive:Pushpull, + 724 724 $DGL 0,31 + 725 725 000E3 CC0802 mov [hl+8],#02H ; str_send_buf,2 ;[INF] 3, 1 + 726 726 ; line 189 : /// IRQ2flg latch: auto cl + 727 727 ; ear after read, IRQ2 conf: IRQ( fall,shock,...) + 728 728 ; line 190 : /// 1 : auto cl + 729 729 ; ear after read, conf: data ready + 730 730 ; line 191 : # endif + 731 731 ; line 192 : #endif + 732 732 ; line 193 : str_send_buf[3] = 0x80; // ctrl3 block update:enable, M + 733 733 ; SB first, scale: +-2G(default), selftest: dis + 734 734 $DGL 0,36 + 735 735 000E6 CC0980 mov [hl+9],#080H ; str_send_buf,128 ;[INF] 3, 1 + 736 736 ; line 194 : + 737 737 ; line 195 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & + 738 738 ; line 196 : ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_A + 739 739 ; CQ ) ) == 0 ) + 740 740 $DGL 0,39 + 741 741 000E9 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 742 742 000EC 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 743 743 000EE D1 cmp0 a ;[INF] 1, 1 + 744 744 000EF DF08 bnz $?L0023 ;[INF] 2, 4 + 745 745 ; line 197 : { + 746 746 000F1 ??bb02_acc_hosu_set: + 747 747 ; line 198 : #ifdef _MCU_BSR_ + 748 748 ; line 199 : PMK23 = 1; + 749 749 $DGL 0,42 + 750 750 000F1 717AD5 set1 MK2H.7 ;[INF] 3, 2 + 751 751 ; line 200 : #endif + 752 752 ; line 201 : // 完全停止 + 753 753 ; line 202 : str_send_buf[0] = + 754 754 ; line 203 : ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | + 755 755 ; ACC_BITS_ALL_AXIS_ON ); + 756 756 $DGL 0,46 + 757 757 000F4 CC0607 mov [hl+6],#07H ; str_send_buf,7 ;[INF] 3, 1 + 758 758 000F7 ??eb02_acc_hosu_set: + 759 759 ; line 204 : } + 760 760 $DGL 0,47 + 761 761 000F7 EF06 br $?L0024 ;[INF] 2, 3 + 762 762 000F9 ?L0023: + 763 763 ; line 205 : else + 764 764 ; line 206 : { + 765 765 000F9 ??bb03_acc_hosu_set: + 766 766 ; line 207 : #ifdef _MCU_BSR_ + 767 767 ; line 208 : PMK23 = 0; + 768 768 $DGL 0,51 + 769 769 000F9 717BD5 clr1 MK2H.7 ;[INF] 3, 2 + 770 770 ; line 209 : #endif + 771 771 ; line 210 : // 100Hz 自動取り込み + 772 772 ; line 211 : str_send_buf[0] = + 773 773 ; line 212 : ( ACC_BITS_PM_NORM << ACC_bP_PM0 + 774 774 ; line 213 : | ACC_BITS_DR_100Hz << ACC_bP_DR0 + 775 775 ; line 214 : | ACC_BITS_ALL_AXIS_ON ); + 776 776 $DGL 0,57 + 777 777 000FC CC062F mov [hl+6],#02FH ; str_send_buf,47 ;[INF] 3, 1 + 778 778 000FF ??eb03_acc_hosu_set: + 779 779 ; line 215 : } + 780 780 000FF ?L0024: + 781 781 ; line 216 : iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, s + 782 782 ; tr_send_buf ); + 783 783 $DGL 0,59 + 784 784 000FF 17 movw ax,hl ;[INF] 1, 1 + 785 785 00100 040600 addw ax,#06H ;[INF] 3, 1 + 786 786 00103 C1 push ax ;[INF] 1, 1 + 787 787 00104 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 788 788 00107 C1 push ax ;[INF] 1, 1 + 789 789 00108 50A0 mov x,#0A0H ; 160 ;[INF] 2, 1 + 790 790 0010A C1 push ax ;[INF] 1, 1 + 791 791 0010B 5030 mov x,#030H ; 48 ;[INF] 2, 1 + 792 792 0010D RFD0000 call !_iic_mcu_write ;[INF] 3, 3 + 793 793 00110 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 794 794 ; line 217 : + 795 795 ; line 218 : // カラ読み + 796 796 ; line 219 : if( ACC_VALID == 1 ) + 797 797 $DGL 0,62 + 798 798 00112 C7 push hl ;[INF] 1, 1 + 799 799 00113 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 + 800 800 00116 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 + 801 801 00118 C6 pop hl ;[INF] 1, 1 + 802 802 00119 DE0A bnc $?L0027 ;[INF] 2, 4 + 803 803 ; line 220 : { + 804 804 0011B ??bb04_acc_hosu_set: + 805 805 ; line 221 : if( system_status.pwr_state == ON ) + 806 806 $DGL 0,64 + 807 807 0011B R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 808 808 0011F DF04 bnz $?L0027 ;[INF] 2, 4 + 809 809 ; line 222 : { + 810 810 00121 ??bb05_acc_hosu_set: + 811 811 ; line 223 : u8 temp[6]; + 812 812 ; line 224 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6 + 813 813 ; , temp ); + 814 814 $DGL 0,67 + 815 815 00121 17 movw ax,hl ;[INF] 1, 1 + 816 816 00122 RFD0000 call !bs_F0038 ;[INF] 3, 3 + 817 817 00125 ??eb05_acc_hosu_set: + 818 818 ; line 225 : } + 819 819 00125 ?L0027: + 820 820 00125 ??eb04_acc_hosu_set: + 821 821 ; line 226 : } + 822 822 ; line 227 : return ( ERR_SUCCESS ); + 823 823 $DGL 0,70 + 824 824 00125 F7 clrw bc ;[INF] 1, 1 + 825 825 ; line 228 : } + 826 826 00126 ?L0020: + 827 827 $DGL 0,71 + 828 828 00126 ??ef_acc_hosu_set: + 829 829 00126 100A addw sp,#0AH ;[INF] 2, 1 + 830 830 00128 C6 pop hl ;[INF] 1, 1 + 831 831 00129 D7 ret ;[INF] 1, 6 + 832 832 0012A ??ee_acc_hosu_set: + 833 833 ; line 229 : + 834 834 ; line 230 : + 835 835 ; line 231 : + 836 836 ; line 232 : /* ======================================================== + 837 837 ; line 233 : 加速度センサ割り込み + 838 838 ; line 234 : I2Cが使用中かもしれないので、読み出しタスクの登録を行うのみ + 839 839 ; line 235 : ======================================================== */ + 840 840 ; line 236 : __interrupt void intp23_ACC_ready( ) + 841 841 ; line 237 : { + 842 842 + 843 843 ----- @@BASE CSEG BASE + 844 844 00000 _intp23_ACC_ready: + 845 845 $DGL 1,165 + 846 846 00000 C1 push ax ;[INF] 1, 1 + 847 847 00001 C3 push bc ;[INF] 1, 1 + 848 848 00002 C5 push de ;[INF] 1, 1 + 849 849 00003 C7 push hl ;[INF] 1, 1 + 850 850 00004 520C mov c,#0CH ;[INF] 2, 1 + 851 851 00006 92 dec c ;[INF] 1, 1 + 852 852 00007 92 dec c ;[INF] 1, 1 + 853 853 00008 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 854 854 0000B C1 push ax ;[INF] 1, 1 + 855 855 0000C DFF8 bnz $$-6 ;[INF] 2, 4 + 856 856 0000E 8EFD mov a,ES ;[INF] 2, 1 + 857 857 00010 70 mov x,a ;[INF] 1, 1 + 858 858 00011 8EFC mov a,CS ;[INF] 2, 1 + 859 859 00013 C1 push ax ;[INF] 1, 1 + 860 860 00014 ??bf_intp23_ACC_ready: + 861 861 ; line 238 : EI(); + 862 862 $DGL 0,2 + 863 863 00014 717AFA ei ;[INF] 3, 4 + 864 864 ; line 239 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) + 865 865 $DGL 0,3 + 866 866 00017 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 867 867 0001A 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 868 868 0001C D1 cmp0 a ;[INF] 1, 1 + 869 869 0001D DD19 bz $?L0036 ;[INF] 2, 4 + 870 870 ; line 240 : { + 871 871 0001F ??bb00_intp23_ACC_ready: + 872 872 ; line 241 : if( ( system_status.pwr_state == ON ) || ( system_status + 873 873 ; .pwr_state == SLEEP ) ) + 874 874 $DGL 0,5 + 875 875 0001F R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 876 876 00023 DD06 bz $?L0035 ;[INF] 2, 4 + 877 877 00025 R40000005 cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + 878 878 00029 DF0D bnz $?L0036 ;[INF] 2, 4 + 879 879 0002B ?L0035: + 880 880 ; line 242 : { + 881 881 0002B ??bb01_intp23_ACC_ready: + 882 882 ; line 243 : if( ACC_VALID ) + 883 883 $DGL 0,7 + 884 884 0002B 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 + 885 885 0002E 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 + 886 886 00030 DE06 bnc $?L0036 ;[INF] 2, 4 + 887 887 ; line 244 : { + 888 888 00032 ??bb02_intp23_ACC_ready: + 889 889 ; line 245 : renge_task_immed_add( tsk_cbk_accero ); + 890 890 $DGL 0,9 + 891 891 00032 R301000 movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1 + 892 892 00035 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 893 893 00038 ??eb02_intp23_ACC_ready: + 894 894 ; line 246 : } + 895 895 00038 ?L0036: + 896 896 00038 ??eb01_intp23_ACC_ready: + 897 897 ; line 247 : } + 898 898 00038 ??eb00_intp23_ACC_ready: + 899 899 ; line 248 : } + 900 900 ; line 249 : } + 901 901 $DGL 0,13 + 902 902 00038 ??ef_intp23_ACC_ready: + 903 903 00038 C0 pop ax ;[INF] 1, 1 + 904 904 00039 9EFC mov CS,a ;[INF] 2, 1 + 905 905 0003B 60 mov a,x ;[INF] 1, 1 + 906 906 0003C 9EFD mov ES,a ;[INF] 2, 1 + 907 907 0003E R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 908 908 00041 5206 mov c,#06H ;[INF] 2, 1 + 909 909 00043 C0 pop ax ;[INF] 1, 1 + 910 910 00044 B9 movw [de],ax ;[INF] 1, 1 + 911 911 00045 A5 incw de ;[INF] 1, 1 + 912 912 00046 A5 incw de ;[INF] 1, 1 + 913 913 00047 92 dec c ;[INF] 1, 1 + 914 914 00048 DFF9 bnz $$-5 ;[INF] 2, 4 + 915 915 0004A C6 pop hl ;[INF] 1, 1 + 916 916 0004B C4 pop de ;[INF] 1, 1 + 917 917 0004C C2 pop bc ;[INF] 1, 1 + 918 918 0004D C0 pop ax ;[INF] 1, 1 + 919 919 0004E 61FC reti ;[INF] 2, 6 + 920 920 00050 ??ee_intp23_ACC_ready: + 921 921 + 922 922 ----- @@CODEL CSEG + 923 923 END + 924 924 + 925 925 + 926 926 ; *** Code Information *** + 927 927 ; + 928 928 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c + 929 929 ; + 930 930 ; $FUNC tsk_cbk_accero(66) + 931 931 ; bc=(void) + 932 932 ; CODE SIZE= 104 bytes, CLOCK_SIZE= 103 clocks, STACK_SIZE= 22 bytes + 933 933 ; + 934 934 ; $CALL iic_mcu_read(78) + 935 935 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 936 936 ; + 937 937 ; $CALL acc_hosu_set(83) + 938 938 ; bc=(void) + 939 939 ; + 940 940 ; $CALL set_irq(94) + 941 941 ; void=(int:ax, int:[sp+4]) + 942 942 ; + 943 943 ; $CALL iic_mcu_read(99) + 944 944 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 945 945 ; + 946 946 ; $CALL pedometer(108) + 947 947 ; void=(void) + 948 948 ; + 949 949 ; $FUNC acc_read(123) + 950 950 ; bc=(void) + 951 951 ; CODE SIZE= 35 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes + 952 952 ; + 953 953 ; $CALL iic_mcu_read_a_byte(124) + 954 954 ; bc=(int:ax, int:[sp+4]) + 955 955 ; + 956 956 ; $FUNC acc_write(140) + 957 957 ; bc=(void) + 958 958 ; CODE SIZE= 36 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 8 bytes + 959 959 ; + 960 960 ; $CALL iic_mcu_write_a_byte(141) + 961 961 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 962 962 ; + 963 963 ; $FUNC acc_hosu_set(158) + 964 964 ; bc=(void) + 965 965 ; CODE SIZE= 107 bytes, CLOCK_SIZE= 96 clocks, STACK_SIZE= 26 bytes + 966 966 ; + 967 967 ; $CALL iic_mcu_read_a_byte(161) + 968 968 ; bc=(int:ax, int:[sp+4]) + 969 969 ; + 970 970 ; $CALL iic_mcu_write(216) + 971 971 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 972 972 ; + 973 973 ; $CALL iic_mcu_read(224) + 974 974 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 975 975 ; + 976 976 ; $FUNC intp23_ACC_ready(237) + 977 977 ; void=(void) + 978 978 ; CODE SIZE= 80 bytes, CLOCK_SIZE= 73 clocks, STACK_SIZE= 26 bytes + 979 979 ; + 980 980 ; $CALL renge_task_immed_add(245) + 981 981 ; bc=(pointer:ax) + 982 982 + 983 983 ; Target chip : uPD79F0104 + 984 984 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00000H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0012AH ROM_CODE +00000 00050H @@BASE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/accero.rel b/branches/0.10(X3)/accero.rel new file mode 100644 index 0000000..8079fd1 Binary files /dev/null and b/branches/0.10(X3)/accero.rel differ diff --git a/branches/0.10(X3)/adc.c b/branches/0.10(X3)/adc.c new file mode 100644 index 0000000..16658cc --- /dev/null +++ b/branches/0.10(X3)/adc.c @@ -0,0 +1,356 @@ +/* ======================================================== + 藤田＠開技 + nintendo + '09 Apr + ======================================================== */ +#include "incs.h" +#include "adc.h" +#include "pm.h" + +#include "led.h" + +bit adc_updated; + +u8 adc_raw_vol; +u8 adc_raw_dep; + +#define INTERVAL_TSK_ADC 3 +/* ======================================================== + ADC設定と、開始 + + 以下のピンは主にここで操作・監視されます。 + ・BT_TEMP,_P + ・ADIN1 + ・VOL + + 関係ありそうですが別のところで管理しています + ・PM_BT_DET,_P PM_init + + ・8tics毎に呼ばれ、３チャンネル分取り込むとADCを停止します。 + 　タスク起動時、レジスタには前回の取り込み値が入っています。 + ======================================================== */ +/* +// max -4db +static const u8 slider_to_codec[64] = +{ + 127, 125, 124, 123, 121, 120, 119, 117, + 116, 115, 113, 112, 111, 109, 108, 107, + 105, 104, 103, 101, 100, 99, 98, 96, + 95, 94, 92, 91, 90, 88, 87, 86, + 84, 83, 82, 80, 79, 78, 76, 75, + 74, 72, 71, 70, 69, 67, 66, 65, + 63, 62, 61, 59, 58, 57, 55, 54, + 53, 51, 50, 49, 47, 46, 45, 44 +}; +*/ + +// max -10db +static const u8 slider_to_codec[64] = +{ + 127, 126, 125, 124, 123, 122, 121, 120, + 119, 118, 117, 116, 115, 114, 113, 112, + 111, 110, 109, 109, 108, 107, 106, 105, + 104, 103, 102, 101, 100, 99, 98, 97, + 96, 95, 94, 93, 92, 91, 90, 89, + 88, 87, 86, 85, 84, 83, 82, 81, + 81, 80, 79, 78, 77, 76, 75, 74, + 73, 72, 71, 70, 69, 68, 67, 66 +}; + +void tsk_adc( ) +{ + static u8 task_interval = 0; + static u8 old_tune; + static u8 sndvol_codec; + static u8 bt_temp_old; + + if( task_interval-- != 0 ) + { + return; + } + else + { + task_interval = (u8)( INTERVAL_TSK_ADC / SYS_INTERVAL_TICK ); + } + + + if( adc_updated ) + { + if( system_status.pwr_state == ON ) + { + // Tune /////////////////////////////////////// + { + // 似非ヒステリシス V2 + // ガリオームには適さない +#define KIKAN 32 + static u8 old_value; + static s8 diffs; + u8 temp; + + if( abs( adc_raw_dep - old_value ) >= 2 ) + { + // 大きく離れた + vreg_ctr[ VREG_C_TUNE ] = adc_raw_dep; + old_value = adc_raw_dep; +#if 0 + 割り込み入れない; + 割り込みを入れるようであれば、ちゃんと変化チェックする; + + set_irq( VREG_C_IRQ0, REG_BIT_VR_TUNE_CHANGE ); +#endif + diffs = 0; + } + else + { + // 近所の値でも、ある期間でいっぱい偏っていたらそっちに寄せる + static u8 kikan_count = KIKAN; + if( old_value < adc_raw_dep ) + { + diffs += 1; + } + else if( old_value > adc_raw_dep ) + { + diffs -= 1; + } + + if( --kikan_count == 0 ) + { + if( diffs >= KIKAN && ( diffs < 64 )) + { + old_value += 1; + } + else if( ( diffs <= ( 256 - KIKAN )) && ( diffs > ( 128 + 64 ) )) // あらー？ + { + old_value -= 1; + } + vreg_ctr[ VREG_C_TUNE ] = old_value; + kikan_count = KIKAN; + diffs = 0; + } + } + } + vreg_ctr[ VREG_C_DBG1 ] = vreg_ctr[ VREG_C_TUNE ]; + vreg_ctr[ VREG_C_DBG2 ] = adc_raw_dep; // dbg + + // Volume ///////////////////////////////////// + { + // 似非ヒステリシスを付けて64段 + u8 temp; + static u8 vol_old; + static u8 force_update_vol; + + if( abs( adc_raw_vol - vol_old ) >= 2 ) // 生値でこれくらいずれたら更新 + { +// if( vreg_ctr[ VREG_C_SND_VOL ] != ( adc_raw_vol / 4 ) ) + { + vol_old = adc_raw_vol; + // レジスタ更新 + vreg_ctr[ VREG_C_SND_VOL ] = ( adc_raw_vol / 4 ); + vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_raw_vol / ( 256 / 32 ); // ←adc値でよい + + // codecに伝える + iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); +#ifndef _MODEL_CTR_ + iic_mcu_write_a_byte( IIC_SLA_DCP, 0, slider_to_codec[ ( 255 - adc_raw_vol ) / 4 ] ); // todo +#endif +// set_irq( VREG_C_IRQ0, REG_BIT_VR_SNDVOL_CHANGE ); // 割り込み廃止 + force_update_vol = 100; + } + } + + { + // ポーリング + if( --force_update_vol == 0 ) + { + vol_old = adc_raw_vol; + // レジスタ更新 +// vreg_ctr[ VREG_C_SND_VOL ] = temp; +// vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_raw_vol / ( 256 / 32 ); // ←adc値でよい + // codecに伝える + iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); + force_update_vol = 100; + } + } + } + + + // TUNE_LED /////////////////////////////////// + // ここで？仕様？ + { + switch ( vreg_ctr[VREG_C_LED_TUNE] ) + { + case LED_TUNE_ILM_ON: + LED_duty_TUNE = vreg_ctr[VREG_C_LED_BRIGHT]; + break; + + case LED_TUNE_ILM_SVR: + LED_duty_TUNE = vreg_ctr[VREG_C_TUNE] / 16; + break; + + case LED_TUNE_ILM_OFF: + default: + LED_duty_TUNE = 0; + break; + } + } + adc_updated = 0; + } + } + + + ADCEN = 1; + ADM = 0b00011011; // セレクトモード、章圧、fCLK/6 ///ここから ↓ + + ADPC = 0x06; // ADCポートのセレクト + ADS = ADC_SEL_TUNE; + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + ADCS = 1; // AD開始。 /// ここまで　↑　までに1us=8clk以上開ける + + ADIF = 0; + ADMK = 0; + +} + + +/* ======================================================== +　過去３つのminでもMAXでもない値を返す + 　突発的なノイズを除く。 + 　根本対策ではないが、これはこれで使い道がある。 +======================================================== */ +static u8 getmean3( u8 * hist ) +{ + if( *hist > *( hist + 1 ) ) + { + if( *hist > *( hist + 2 ) ) + { + return( ( *( hist + 1 ) > *( hist + 2 ) ) ? *( hist + 1 ) : *( hist + 2 ) ); + } + else + { + return( *hist ); + } + }else{ + if( *hist > *( hist + 2 ) ) + { + return( *hist ); + } + else + { + return( ( *( hist + 1 ) < *( hist + 2 ) ) ? *( hist + 1 ) : *( hist + 2 ) ); + } + } +} + + + +/* ======================================================== +　自前で次のチャンネル +　　一通り終わったら止める + ======================================================== */ +__interrupt void int_adc( ) +{ + static u8 hist_tune[3]; + static u8 hist_snd_vol[3]; + static u8 hist_bt_temp[3]; + static u8 index; + + EI( ); + switch ( ADS ) + { +/* +case ( ADC_SEL_AMB_BRIT ): + vreg_ctr[ VREG_C_AMBIENT_BRIGHTNESS ] = ADCRH; + break; +*/ + + case ( ADC_SEL_TUNE ): + hist_tune[index] = ADCRH; +#ifdef _MODEL_WM0_ + adc_raw_dep = 255 - getmean3( hist_tune ); +#else + adc_raw_dep = getmean3( hist_tune ); +#endif + break; + + case ( ADC_SEL_VOL ): + hist_snd_vol[index] = ADCRH; +#ifdef _MODEL_CTR_JIKKI_ + adc_raw_vol = ( 255 - getmean3( hist_snd_vol )); +#else + adc_raw_vol = getmean3( hist_snd_vol ); +#endif + // TWL用レジスタ(32段)の更新。アトミックな処理として扱わないと不都合が。 + /// 割り込みはHorizonを通してコマンドを発行されるのを待てばよい + break; + + case ( ADC_SEL_BATT_TEMP ): + hist_bt_temp[index] = ADCRH; + raw_adc_temperature = getmean3( hist_bt_temp ); + renge_task_immed_add( PM_bt_temp_update ); + break; + + case ( ADC_SEL_BATT_DET ): +// vreg_ctr[ VREG_C_DBG_BATT_DET ] = ADCRH; + // todo + break; + } + + +// もっとまともな書き方がありそうだ +// if( ADS == ADC_SEL_BATT_DET ){ + if( ADS != ADC_SEL_BATT_TEMP ) + { // 電池判別は電源投入の一回のみ + ADS += 1; // 次のチャンネル + BT_TEMP_P = 1; // 電池温度監視スタート + } + else + { + ADCEN = 0; // 止めてしまう + BT_TEMP_P = 0; // 電池温度監視スタート + adc_updated = 1; + index = ( index == 2 ) ? 0 : ( index + 1 ); + } +} + + + +/* ======================================================== + tsk_adcと競合することを考慮していません。 + ======================================================== */ +u8 get_adc( u8 ch ) +{ + u8 temp; + + ADMK = 1; + ADIF = 0; + + ADCEN = 1; + ADCS = 0; + ADM = 0b00100011; // セレクトモード、昇圧、fCLK/6 ///ここから↓ + + ADPC = 0x06; // ADCポートのセレクト + ADS = ch; + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + NOP(); + ADCS = 1; // AD開始。 /// ここまで↑　に、1us以上開ける + + ADMK = 0; + while( ADIF == 0 ){;} + temp = ADCRH; + ADCEN = 0; + + return ( temp ); +} diff --git a/branches/0.10(X3)/adc.h b/branches/0.10(X3)/adc.h new file mode 100644 index 0000000..e18bf83 --- /dev/null +++ b/branches/0.10(X3)/adc.h @@ -0,0 +1,43 @@ +#ifndef __adc__ +#define __adc__ + +#include "jhl_defs.h" + +/////////////////////////////////////// +// ANI2 P22 +#define ADC_SEL_AMB_BRIT 0x02 + +/* +// ANI3 P23 +#define ADC_SEL_GYRO_YAW 0x03 +// ANI4 P24 +#define ADC_SEL_GYRO_PITCH 0x04 +// ANI5 P25 +#define ADC_SEL_GYRO_ROLL 0x05 +*/ + +// ANI6 P26 +#define ADC_SEL_TUNE 0x06 +// ANI7 P27 +#define ADC_SEL_VOL 0x07 + +// ANI8 P150 +#define ADC_SEL_BATT_TEMP 0x08 +// ANI9 P151 +#define ADC_SEL_BATT_DET 0x09 + + + +/////////////////////////////////////// +#define CODEC_REG_VOL 0x13 + + + +/////////////////////////////////////// + + +/////////////////////////////////////// +u8 get_adc( u8 ch ); + + +#endif diff --git a/branches/0.10(X3)/adc.prn b/branches/0.10(X3)/adc.prn new file mode 100644 index 0000000..712d1de --- /dev/null +++ b/branches/0.10(X3)/adc.prn @@ -0,0 +1,1506 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\adc.asm +Para-file: +In-file: inter_asm\adc.asm +Obj-file: adc.rel +Prn-file: adc.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no adc.c + 6 6 ; In-file : adc.c + 7 7 ; Asm-file : inter_asm\adc.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0FAH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, adc.c + 18 18 $DGS MOD_NAM, adc, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 82 82 $DGS AUX_TAG, 01H, 047H + 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 86 86 $DGS AUX_EOS, 041H, 01H + 87 87 $DGS LAB_SYM, bs_S0076, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_S0076, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS LAB_SYM, bs_F0075, U, U, 00H, 06H, 00H, 00H + 90 90 $DGS LAB_SYM, es_F0075, U, U, 00H, 06H, 00H, 00H + 91 91 $DGS LAB_SYM, bs_F0074, U, U, 00H, 06H, 00H, 00H + 92 92 $DGS LAB_SYM, es_F0074, U, U, 00H, 06H, 00H, 00H + 93 93 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 94 94 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 95 95 $DGS STA_SYM, _slider_to_codec, U, U, 0500CH, 03H, 01H, 03H + 96 96 $DGS AUX_STR, 00H, 00H, 040H, 040H, 00H, 00H, 00H, 00H + 97 97 $DGS GLV_SYM, _tsk_adc, U, U, 01H, 026H, 01H, 02H + 98 98 $DGS AUX_FUN, 00H, U, U, 0B5H, 00H, 00H + 99 99 $DGS BEG_FUN, ??bf_tsk_adc, U, U, 00H, 065H, 01H, 00H + 100 100 $DGS AUX_BEG, 03DH, 02H, 059H + 101 101 $DGS STA_SYM, _task_interval, ?L0003, U, 0CH, 03H, 00H, 00H + 102 102 $DGS STA_SYM, _old_tune, ?L0004, U, 0CH, 03H, 00H, 00H + 103 103 $DGS STA_SYM, _sndvol_codec, ?L0005, U, 0CH, 03H, 00H, 00H + 104 104 $DGS STA_SYM, _bt_temp_old, ?L0006, U, 0CH, 03H, 00H, 00H + 105 105 $DGS BEG_BLK, ??bb00_tsk_adc, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_BEG, 08H, 00H, 05DH + 107 107 $DGS END_BLK, ??eb00_tsk_adc, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_END, 0AH + 109 109 $DGS BEG_BLK, ??bb01_tsk_adc, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_BEG, 0CH, 00H, 061H + 111 111 $DGS END_BLK, ??eb01_tsk_adc, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_END, 0EH + 113 113 $DGS BEG_BLK, ??bb02_tsk_adc, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_BEG, 012H, 00H, 063H + 115 115 $DGS BEG_BLK, ??bb03_tsk_adc, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_BEG, 014H, 00H, 065H + 117 117 $DGS BEG_BLK, ??bb04_tsk_adc, U, U, 00H, 064H, 01H, 00H + 118 118 $DGS AUX_BEG, 016H, 00H, 06DH + 119 119 $DGS STA_SYM, _old_value, ?L0007, U, 0CH, 03H, 01H, 00H + 120 120 $DGS AUX_STR, 00H, 01AH, 01H, 00H, 00H, 00H, 00H, 00H + 121 121 $DGS STA_SYM, _diffs, ?L0008, U, 02H, 03H, 01H, 00H + 122 122 $DGS AUX_STR, 00H, 01BH, 01H, 00H, 00H, 00H, 00H, 00H + 123 123 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 01H, 00H + 124 124 $DGS AUX_STR, 00H, 01CH, 01H, 00H, 00H, 00H, 00H, 00H + 125 125 $DGS BEG_BLK, ??bb05_tsk_adc, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_BEG, 01FH, 00H, 071H + 127 127 $DGS END_BLK, ??eb05_tsk_adc, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_END, 02AH + 129 129 $DGS BEG_BLK, ??bb06_tsk_adc, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_BEG, 02CH, 00H, 075H + 131 131 $DGS STA_SYM, _kikan_count, ?L0009, U, 0CH, 03H, 01H, 00H + 132 132 $DGS AUX_STR, 00H, 02EH, 01H, 00H, 00H, 00H, 00H, 00H + 133 133 $DGS BEG_BLK, ??bb07_tsk_adc, U, U, 00H, 064H, 01H, 00H + 134 134 $DGS AUX_BEG, 030H, 00H, 079H + 135 135 $DGS END_BLK, ??eb07_tsk_adc, U, U, 00H, 064H, 01H, 00H + 136 136 $DGS AUX_END, 032H + 137 137 $DGS BEG_BLK, ??bb08_tsk_adc, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_BEG, 034H, 00H, 07DH + 139 139 $DGS END_BLK, ??eb08_tsk_adc, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_END, 036H + 141 141 $DGS BEG_BLK, ??bb09_tsk_adc, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_BEG, 039H, 00H, 07FH + 143 143 $DGS BEG_BLK, ??bb0A_tsk_adc, U, U, 00H, 064H, 01H, 00H + 144 144 $DGS AUX_BEG, 03BH, 00H, 083H + 145 145 $DGS END_BLK, ??eb0A_tsk_adc, U, U, 00H, 064H, 01H, 00H + 146 146 $DGS AUX_END, 03DH + 147 147 $DGS BEG_BLK, ??bb0B_tsk_adc, U, U, 00H, 064H, 01H, 00H + 148 148 $DGS AUX_BEG, 03FH, 00H, 08DH + 149 149 $DGS END_BLK, ??eb0B_tsk_adc, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_END, 041H + 151 151 $DGS END_BLK, ??eb09_tsk_adc, U, U, 00H, 064H, 01H, 00H + 152 152 $DGS AUX_END, 045H + 153 153 $DGS END_BLK, ??eb06_tsk_adc, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_END, 046H + 155 155 $DGS END_BLK, ??eb04_tsk_adc, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_END, 047H + 157 157 $DGS BEG_BLK, ??bb0C_tsk_adc, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_BEG, 04CH, 00H, 095H + 159 159 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 01H, 00H + 160 160 $DGS AUX_STR, 00H, 04EH, 01H, 00H, 00H, 00H, 00H, 00H + 161 161 $DGS STA_SYM, _vol_old, ?L0010, U, 0CH, 03H, 01H, 00H + 162 162 $DGS AUX_STR, 00H, 04FH, 01H, 00H, 00H, 00H, 00H, 00H + 163 163 $DGS STA_SYM, _force_update_vol, ?L0011, U, 0CH, 03H, 01H, 00H + 164 164 $DGS AUX_STR, 00H, 050H, 01H, 00H, 00H, 00H, 00H, 00H + 165 165 $DGS BEG_BLK, ??bb0D_tsk_adc, U, U, 00H, 064H, 01H, 00H + 166 166 $DGS AUX_BEG, 053H, 00H, 097H + 167 167 $DGS BEG_BLK, ??bb0E_tsk_adc, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_BEG, 055H, 00H, 09DH + 169 169 $DGS END_BLK, ??eb0E_tsk_adc, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_END, 062H + 171 171 $DGS END_BLK, ??eb0D_tsk_adc, U, U, 00H, 064H, 01H, 00H + 172 172 $DGS AUX_END, 063H + 173 173 $DGS BEG_BLK, ??bb0F_tsk_adc, U, U, 00H, 064H, 01H, 00H + 174 174 $DGS AUX_BEG, 065H, 00H, 09FH + 175 175 $DGS BEG_BLK, ??bb10_tsk_adc, U, U, 00H, 064H, 01H, 00H + 176 176 $DGS AUX_BEG, 068H, 00H, 0A7H + 177 177 $DGS END_BLK, ??eb10_tsk_adc, U, U, 00H, 064H, 01H, 00H + 178 178 $DGS AUX_END, 070H + 179 179 $DGS END_BLK, ??eb0F_tsk_adc, U, U, 00H, 064H, 01H, 00H + 180 180 $DGS AUX_END, 071H + 181 181 $DGS END_BLK, ??eb0C_tsk_adc, U, U, 00H, 064H, 01H, 00H + 182 182 $DGS AUX_END, 072H + 183 183 $DGS BEG_BLK, ??bb11_tsk_adc, U, U, 00H, 064H, 01H, 00H + 184 184 $DGS AUX_BEG, 077H, 00H, 0A9H + 185 185 $DGS BEG_BLK, ??bb12_tsk_adc, U, U, 00H, 064H, 01H, 00H + 186 186 $DGS AUX_BEG, 079H, 00H, 00H + 187 187 $DGS END_BLK, ??eb12_tsk_adc, U, U, 00H, 064H, 01H, 00H + 188 188 $DGS AUX_END, 086H + 189 189 $DGS END_BLK, ??eb11_tsk_adc, U, U, 00H, 064H, 01H, 00H + 190 190 $DGS AUX_END, 087H + 191 191 $DGS END_BLK, ??eb03_tsk_adc, U, U, 00H, 064H, 01H, 00H + 192 192 $DGS AUX_END, 089H + 193 193 $DGS END_BLK, ??eb02_tsk_adc, U, U, 00H, 064H, 01H, 00H + 194 194 $DGS AUX_END, 08AH + 195 195 $DGS END_FUN, ??ef_tsk_adc, U, U, 00H, 065H, 01H, 00H + 196 196 $DGS AUX_END, 09FH + 197 197 $DGS STA_SYM, _getmean3, U, U, 0CH, 03H, 01H, 02H + 198 198 $DGS AUX_FUN, 00H, U, U, 0D5H, 00H, 00H + 199 199 $DGS BEG_FUN, ??bf_getmean3, U, U, 00H, 065H, 01H, 00H + 200 200 $DGS AUX_BEG, 0E4H, 02H, 0BBH + 201 201 $DGS REG_PAR, _hist, 0103H, 0FFFFH, 010CH, 011H, 01H, 01H + 202 202 $DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H + 203 203 $DGS BEG_BLK, ??bb00_getmean3, U, U, 00H, 064H, 01H, 00H + 204 204 $DGS AUX_BEG, 03H, 00H, 0BDH + 205 205 $DGS BEG_BLK, ??bb01_getmean3, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_BEG, 05H, 00H, 0C1H + 207 207 $DGS END_BLK, ??eb01_getmean3, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_END, 07H + 209 209 $DGS BEG_BLK, ??bb02_getmean3, U, U, 00H, 064H, 01H, 00H + 210 210 $DGS AUX_BEG, 09H, 00H, 0C7H + 211 211 $DGS END_BLK, ??eb02_getmean3, U, U, 00H, 064H, 01H, 00H + 212 212 $DGS AUX_END, 0BH + 213 213 $DGS END_BLK, ??eb00_getmean3, U, U, 00H, 064H, 01H, 00H + 214 214 $DGS AUX_END, 0CH + 215 215 $DGS BEG_BLK, ??bb03_getmean3, U, U, 00H, 064H, 01H, 00H + 216 216 $DGS AUX_BEG, 0CH, 00H, 0C9H + 217 217 $DGS BEG_BLK, ??bb04_getmean3, U, U, 00H, 064H, 01H, 00H + 218 218 $DGS AUX_BEG, 0EH, 00H, 0CDH + 219 219 $DGS END_BLK, ??eb04_getmean3, U, U, 00H, 064H, 01H, 00H + 220 220 $DGS AUX_END, 010H + 221 221 $DGS BEG_BLK, ??bb05_getmean3, U, U, 00H, 064H, 01H, 00H + 222 222 $DGS AUX_BEG, 012H, 00H, 00H + 223 223 $DGS END_BLK, ??eb05_getmean3, U, U, 00H, 064H, 01H, 00H + 224 224 $DGS AUX_END, 014H + 225 225 $DGS END_BLK, ??eb03_getmean3, U, U, 00H, 064H, 01H, 00H + 226 226 $DGS AUX_END, 015H + 227 227 $DGS END_FUN, ??ef_getmean3, U, U, 00H, 065H, 01H, 00H + 228 228 $DGS AUX_END, 016H + 229 229 $DGS GLV_SYM, _int_adc, U, U, 0E001H, 026H, 01H, 02H + 230 230 $DGS AUX_FUN, 00H, U, U, 0EEH, 00H, 00H + 231 231 $DGS BEG_FUN, ??bf_int_adc, U, U, 00H, 065H, 01H, 00H + 232 232 $DGS AUX_BEG, 0102H, 016H, 0E0H + 233 233 $DGS STA_SYM, _hist_tune, ?L0055, U, 0CH, 03H, 01H, 03H + 234 234 $DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H + 235 235 $DGS STA_SYM, _hist_snd_vol, ?L0056, U, 0CH, 03H, 01H, 03H + 236 236 $DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H + 237 237 $DGS STA_SYM, _hist_bt_temp, ?L0057, U, 0CH, 03H, 01H, 03H + 238 238 $DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H + 239 239 $DGS STA_SYM, _index, ?L0058, U, 0CH, 03H, 00H, 00H + 240 240 $DGS BEG_BLK, ??bb00_int_adc, U, U, 00H, 064H, 01H, 00H + 241 241 $DGS AUX_BEG, 09H, 00H, 0E4H + 242 242 $DGS END_BLK, ??eb00_int_adc, U, U, 00H, 064H, 01H, 00H + 243 243 $DGS AUX_END, 02EH + 244 244 $DGS BEG_BLK, ??bb01_int_adc, U, U, 00H, 064H, 01H, 00H + 245 245 $DGS AUX_BEG, 034H, 00H, 0E8H + 246 246 $DGS END_BLK, ??eb01_int_adc, U, U, 00H, 064H, 01H, 00H + 247 247 $DGS AUX_END, 037H + 248 248 $DGS BEG_BLK, ??bb02_int_adc, U, U, 00H, 064H, 01H, 00H + 249 249 $DGS AUX_BEG, 039H, 00H, 00H + 250 250 $DGS END_BLK, ??eb02_int_adc, U, U, 00H, 064H, 01H, 00H + 251 251 $DGS AUX_END, 03EH + 252 252 $DGS END_FUN, ??ef_int_adc, U, U, 00H, 065H, 01H, 00H + 253 253 $DGS AUX_END, 03FH + 254 254 $DGS GLV_SYM, _get_adc, U, U, 0CH, 026H, 01H, 02H + 255 255 $DGS AUX_FUN, 00H, U, U, 0FAH, 00H, 00H + 256 256 $DGS BEG_FUN, ??bf_get_adc, U, U, 00H, 065H, 01H, 00H + 257 257 $DGS AUX_BEG, 0148H, 02H, 0F4H + 258 258 $DGS REG_PAR, _ch, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 259 259 $DGS REG_VAR, _temp, 07H, 0FFFFH, 010CH, 04H, 00H, 00H + 260 260 $DGS BEG_BLK, ??bb00_get_adc, U, U, 00H, 064H, 01H, 00H + 261 261 $DGS AUX_BEG, 018H, 00H, 00H + 262 262 $DGS END_BLK, ??eb00_get_adc, U, U, 00H, 064H, 01H, 00H + 263 263 $DGS AUX_END, 018H + 264 264 $DGS END_FUN, ??ef_get_adc, U, U, 00H, 065H, 01H, 00H + 265 265 $DGS AUX_END, 01DH + 266 266 $DGS GLV_SYM, _adc_updated, U, U, 034CH, 027H, 00H, 00H + 267 267 $DGS GLV_SYM, _adc_raw_vol, U, U, 0CH, 026H, 00H, 00H + 268 268 $DGS GLV_SYM, _adc_raw_dep, U, U, 0CH, 026H, 00H, 00H + 269 269 $DGS GLV_SYM, _abs, U, U, 04H, 02H, 01H, 02H + 270 270 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 271 271 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H + 272 272 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 273 273 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 274 274 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 275 275 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 276 276 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 277 277 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H + 278 278 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 279 279 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 280 280 $DGS GLV_SYM, _raw_adc_temperature, U, U, 0CH, 02H, 00H, 00H + 281 281 $DGS GLV_SYM, _PM_bt_temp_update, U, U, 0AH, 02H, 01H, 02H + 282 282 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H + 283 283 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 284 284 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 285 285 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 286 286 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 287 287 + 288 288 EXTRN _abs + 289 289 EXTRN _iic_mcu_write_a_byte + 290 290 EXTRN _system_status + 291 291 EXTRN _vreg_ctr + 292 292 EXTRN _vreg_twl + 293 293 EXTRN _@SEGAX + 294 294 EXTRN _@SEGDE + 295 295 EXTRN _@RTARG0 + 296 296 EXTRN _raw_adc_temperature + 297 297 EXTRN _PM_bt_temp_update + 298 298 EXTRN _renge_task_immed_add + 299 299 PUBLIC _adc_updated + 300 300 PUBLIC _adc_raw_vol + 301 301 PUBLIC _adc_raw_dep + 302 302 PUBLIC _tsk_adc + 303 303 PUBLIC _int_adc + 304 304 PUBLIC _get_adc + 305 305 + 306 306 ----- @@BITS BSEG + 307 307 00000.0 _adc_updated DBIT + 308 308 + 309 309 ----- @@CNST CSEG MIRRORP + 310 310 00000 01 _lpf_coeff: DB 01H ; 1 + 311 311 00001 02 DB 02H ; 2 + 312 312 00002 02 DB 02H ; 2 + 313 313 00003 03 DB 03H ; 3 + 314 314 00004 03 DB 03H ; 3 + 315 315 00005 02 DB 02H ; 2 + 316 316 00006 00 DB 00H ; 0 + 317 317 00007 FE DB 0FEH ; 254 + 318 318 00008 FB DB 0FBH ; 251 + 319 319 00009 F7 DB 0F7H ; 247 + 320 320 0000A F3 DB 0F3H ; 243 + 321 321 0000B F0 DB 0F0H ; 240 + 322 322 0000C F0 DB 0F0H ; 240 + 323 323 0000D F3 DB 0F3H ; 243 + 324 324 0000E FA DB 0FAH ; 250 + 325 325 0000F 04 DB 04H ; 4 + 326 326 00010 12 DB 012H ; 18 + 327 327 00011 25 DB 025H ; 37 + 328 328 00012 38 DB 038H ; 56 + 329 329 00013 4D DB 04DH ; 77 + 330 330 00014 5F DB 05FH ; 95 + 331 331 00015 6E DB 06EH ; 110 + 332 332 00016 77 DB 077H ; 119 + 333 333 00017 7A DB 07AH ; 122 + 334 334 00018 77 DB 077H ; 119 + 335 335 00019 6E DB 06EH ; 110 + 336 336 0001A 5F DB 05FH ; 95 + 337 337 0001B 4D DB 04DH ; 77 + 338 338 0001C 38 DB 038H ; 56 + 339 339 0001D 25 DB 025H ; 37 + 340 340 0001E 12 DB 012H ; 18 + 341 341 0001F 04 DB 04H ; 4 + 342 342 00020 FA DB 0FAH ; 250 + 343 343 00021 F3 DB 0F3H ; 243 + 344 344 00022 F0 DB 0F0H ; 240 + 345 345 00023 F0 DB 0F0H ; 240 + 346 346 00024 F3 DB 0F3H ; 243 + 347 347 00025 F7 DB 0F7H ; 247 + 348 348 00026 FB DB 0FBH ; 251 + 349 349 00027 FE DB 0FEH ; 254 + 350 350 00028 00 DB 00H ; 0 + 351 351 00029 02 DB 02H ; 2 + 352 352 0002A 03 DB 03H ; 3 + 353 353 0002B 03 DB 03H ; 3 + 354 354 0002C 02 DB 02H ; 2 + 355 355 0002D 02 DB 02H ; 2 + 356 356 0002E 01 DB 01H ; 1 + 357 357 0002F 7F _slider_to_codec: DB 07FH ; 127 + 358 358 00030 7E DB 07EH ; 126 + 359 359 00031 7D DB 07DH ; 125 + 360 360 00032 7C DB 07CH ; 124 + 361 361 00033 7B DB 07BH ; 123 + 362 362 00034 7A DB 07AH ; 122 + 363 363 00035 79 DB 079H ; 121 + 364 364 00036 78 DB 078H ; 120 + 365 365 00037 77 DB 077H ; 119 + 366 366 00038 76 DB 076H ; 118 + 367 367 00039 75 DB 075H ; 117 + 368 368 0003A 74 DB 074H ; 116 + 369 369 0003B 73 DB 073H ; 115 + 370 370 0003C 72 DB 072H ; 114 + 371 371 0003D 71 DB 071H ; 113 + 372 372 0003E 70 DB 070H ; 112 + 373 373 0003F 6F DB 06FH ; 111 + 374 374 00040 6E DB 06EH ; 110 + 375 375 00041 6D DB 06DH ; 109 + 376 376 00042 6D DB 06DH ; 109 + 377 377 00043 6C DB 06CH ; 108 + 378 378 00044 6B DB 06BH ; 107 + 379 379 00045 6A DB 06AH ; 106 + 380 380 00046 69 DB 069H ; 105 + 381 381 00047 68 DB 068H ; 104 + 382 382 00048 67 DB 067H ; 103 + 383 383 00049 66 DB 066H ; 102 + 384 384 0004A 65 DB 065H ; 101 + 385 385 0004B 64 DB 064H ; 100 + 386 386 0004C 63 DB 063H ; 99 + 387 387 0004D 62 DB 062H ; 98 + 388 388 0004E 61 DB 061H ; 97 + 389 389 0004F 60 DB 060H ; 96 + 390 390 00050 5F DB 05FH ; 95 + 391 391 00051 5E DB 05EH ; 94 + 392 392 00052 5D DB 05DH ; 93 + 393 393 00053 5C DB 05CH ; 92 + 394 394 00054 5B DB 05BH ; 91 + 395 395 00055 5A DB 05AH ; 90 + 396 396 00056 59 DB 059H ; 89 + 397 397 00057 58 DB 058H ; 88 + 398 398 00058 57 DB 057H ; 87 + 399 399 00059 56 DB 056H ; 86 + 400 400 0005A 55 DB 055H ; 85 + 401 401 0005B 54 DB 054H ; 84 + 402 402 0005C 53 DB 053H ; 83 + 403 403 0005D 52 DB 052H ; 82 + 404 404 0005E 51 DB 051H ; 81 + 405 405 0005F 51 DB 051H ; 81 + 406 406 00060 50 DB 050H ; 80 + 407 407 00061 4F DB 04FH ; 79 + 408 408 00062 4E DB 04EH ; 78 + 409 409 00063 4D DB 04DH ; 77 + 410 410 00064 4C DB 04CH ; 76 + 411 411 00065 4B DB 04BH ; 75 + 412 412 00066 4A DB 04AH ; 74 + 413 413 00067 49 DB 049H ; 73 + 414 414 00068 48 DB 048H ; 72 + 415 415 00069 47 DB 047H ; 71 + 416 416 0006A 46 DB 046H ; 70 + 417 417 0006B 45 DB 045H ; 69 + 418 418 0006C 44 DB 044H ; 68 + 419 419 0006D 43 DB 043H ; 67 + 420 420 0006E 42 DB 042H ; 66 + 421 421 0006F 00 DB (1) + 422 422 + 423 423 ----- @@R_INIT CSEG UNIT64KP + 424 424 00000 00 DB 00H ; 0 + 425 425 00001 20 DB 020H ; 32 + 426 426 + 427 427 ----- @@INIT DSEG BASEP + 428 428 00000 ?L0003: DS (1) + 429 429 00001 ?L0009: DS (1) + 430 430 + 431 431 ----- @@DATA DSEG BASEP + 432 432 00000 _adc_raw_vol: DS (1) + 433 433 00001 _adc_raw_dep: DS (1) + 434 434 00002 ?L0004: DS (1) + 435 435 00003 ?L0005: DS (1) + 436 436 00004 ?L0006: DS (1) + 437 437 00005 ?L0007: DS (1) + 438 438 00006 ?L0008: DS (1) + 439 439 00007 ?L0010: DS (1) + 440 440 00008 ?L0011: DS (1) + 441 441 00009 ?L0055: DS (3) + 442 442 0000C ?L0056: DS (3) + 443 443 0000F ?L0057: DS (3) + 444 444 00012 ?L0058: DS (1) + 445 445 00013 DS (1) + 446 446 + 447 447 ----- @@R_INIS CSEG UNIT64KP + 448 448 + 449 449 ----- @@INIS DSEG SADDRP + 450 450 + 451 451 ----- @@DATS DSEG SADDRP + 452 452 + 453 453 ----- @@CNSTL CSEG PAGE64KP + 454 454 + 455 455 ----- @@RLINIT CSEG UNIT64KP + 456 456 + 457 457 ----- @@INITL DSEG UNIT64KP + 458 458 + 459 459 ----- @@DATAL DSEG UNIT64KP + 460 460 + 461 461 ----- @@CALT CSEG CALLT0 + 462 462 + 463 463 ; Sub-Routines created by CC78K0R + 464 464 + 465 465 ----- ROM_CODE CSEG BASE + 466 466 00000 bs_S0076: + 467 467 00000 RD90000 mov x,!_adc_raw_vol ;[INF] 3, 1 + 468 468 00003 F1 clrb a ;[INF] 1, 1 + 469 469 00004 312F sarw ax,2 ;[INF] 2, 1 + 470 470 00006 D7 ret ;[INF] 1, 6 + 471 471 00007 es_S0076: + 472 472 + 473 473 ----- ROM_CODE CSEG BASE + 474 474 00007 bs_F0075: + 475 475 00007 70 mov x,a ;[INF] 1, 1 + 476 476 00008 6131 subc a,a ;[INF] 2, 1 + 477 477 0000A RFD0000 call !_abs ;[INF] 3, 3 + 478 478 0000D 13 movw ax,bc ;[INF] 1, 1 + 479 479 0000E 440200 cmpw ax,#02H ; 2 ;[INF] 3, 1 + 480 480 00011 71FE or1 CY,a.7 ;[INF] 2, 1 + 481 481 00013 D7 ret ;[INF] 1, 6 + 482 482 00014 es_F0075: + 483 483 + 484 484 ----- ROM_CODE CSEG BASE + 485 485 00014 bs_F0074: + 486 486 00014 R492F00 mov a,_slider_to_codec[bc] ;[INF] 3, 1 + 487 487 00017 318E shrw ax,8 ;[INF] 2, 1 + 488 488 00019 C1 push ax ;[INF] 1, 1 + 489 489 0001A 5013 mov x,#013H ; 19 ;[INF] 2, 1 + 490 490 0001C C1 push ax ;[INF] 1, 1 + 491 491 0001D 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1 + 492 492 0001F RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 493 493 00022 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 494 494 00024 D7 ret ;[INF] 1, 6 + 495 495 00025 es_F0074: + 496 496 + 497 497 ; *** Sub-Routine Information *** + 498 498 ; + 499 499 ; $SUB bs_F0074 + 500 500 ; CODE SIZE= 17 bytes + 501 501 ; + 502 502 ; $SUB bs_F0075 + 503 503 ; CODE SIZE= 13 bytes + 504 504 ; + 505 505 ; $SUB bs_S0076 + 506 506 ; CODE SIZE= 7 bytes + 507 507 + 508 508 ; End of Sub-Routines + 509 509 + 510 510 ; line 1 : /* ======================================================== + 511 511 ; line 2 : 藤田＠開技 + 512 512 ; line 3 : nintendo + 513 513 ; line 4 : '09 Apr + 514 514 ; line 5 : ======================================================== */ + 515 515 ; line 6 : #include "incs.h" + 516 516 ; line 7 : #include "adc.h" + 517 517 ; line 8 : #include "pm.h" + 518 518 ; line 9 : + 519 519 ; line 10 : #include "led.h" + 520 520 ; line 11 : + 521 521 ; line 12 : bit adc_updated; + 522 522 ; line 13 : + 523 523 ; line 14 : u8 adc_raw_vol; + 524 524 ; line 15 : u8 adc_raw_dep; + 525 525 ; line 16 : + 526 526 ; line 17 : #define INTERVAL_TSK_ADC 3 + 527 527 ; line 18 : /* ======================================================== + 528 528 ; line 19 : ADC設定と、開始 + 529 529 ; line 20 : + 530 530 ; line 21 : 以下のピンは主にここで操作・監視されます。 + 531 531 ; line 22 : ・BT_TEMP,_P + 532 532 ; line 23 : ・ADIN1 + 533 533 ; line 24 : ・VOL + 534 534 ; line 25 : + 535 535 ; line 26 : 関係ありそうですが別のところで管理しています + 536 536 ; line 27 : ・PM_BT_DET,_P PM_init + 537 537 ; line 28 : + 538 538 ; line 29 : ・8tics毎に呼ばれ、３チャンネル分取り込むとADCを停止します。 + 539 539 ; line 30 : 　タスク起動時、レジスタには前回の取り込み値が入っています。 + 540 540 ; line 31 : ======================================================== */ + 541 541 ; line 32 : /* + 542 542 ; line 33 : // max -4db + 543 543 ; line 34 : static const u8 slider_to_codec[64] = + 544 544 ; line 35 : { + 545 545 ; line 36 : 127, 125, 124, 123, 121, 120, 119, 117, + 546 546 ; line 37 : 116, 115, 113, 112, 111, 109, 108, 107, + 547 547 ; line 38 : 105, 104, 103, 101, 100, 99, 98, 96, + 548 548 ; line 39 : 95, 94, 92, 91, 90, 88, 87, 86, + 549 549 ; line 40 : 84, 83, 82, 80, 79, 78, 76, 75, + 550 550 ; line 41 : 74, 72, 71, 70, 69, 67, 66, 65, + 551 551 ; line 42 : 63, 62, 61, 59, 58, 57, 55, 54, + 552 552 ; line 43 : 53, 51, 50, 49, 47, 46, 45, 44 + 553 553 ; line 44 : }; + 554 554 ; line 45 : */ + 555 555 ; line 46 : + 556 556 ; line 47 : // max -10db + 557 557 ; line 48 : static const u8 slider_to_codec[64] = + 558 558 ; line 49 : { + 559 559 ; line 50 : 127, 126, 125, 124, 123, 122, 121, 120, + 560 560 ; line 51 : 119, 118, 117, 116, 115, 114, 113, 112, + 561 561 ; line 52 : 111, 110, 109, 109, 108, 107, 106, 105, + 562 562 ; line 53 : 104, 103, 102, 101, 100, 99, 98, 97, + 563 563 ; line 54 : 96, 95, 94, 93, 92, 91, 90, 89, + 564 564 ; line 55 : 88, 87, 86, 85, 84, 83, 82, 81, + 565 565 ; line 56 : 81, 80, 79, 78, 77, 76, 75, 74, + 566 566 ; line 57 : 73, 72, 71, 70, 69, 68, 67, 66 + 567 567 ; line 58 : }; + 568 568 ; line 59 : + 569 569 ; line 60 : void tsk_adc( ) + 570 570 ; line 61 : { + 571 571 + 572 572 ----- ROM_CODE CSEG BASE + 573 573 00025 _tsk_adc: + 574 574 $DGL 1,81 + 575 575 00025 C7 push hl ;[INF] 1, 1 + 576 576 00026 ??bf_tsk_adc: + 577 577 ; line 62 : static u8 task_interval = 0; + 578 578 ; line 63 : static u8 old_tune; + 579 579 ; line 64 : static u8 sndvol_codec; + 580 580 ; line 65 : static u8 bt_temp_old; + 581 581 ; line 66 : + 582 582 ; line 67 : if( task_interval-- != 0 ) + 583 583 $DGL 0,7 + 584 584 00026 R8F0000 mov a,!?L0003 ; task_interval ;[INF] 3, 1 + 585 585 00029 RB00000 dec !?L0003 ; task_interval ;[INF] 3, 2 + 586 586 0002C D1 cmp0 a ;[INF] 1, 1 + 587 587 0002D 61E8 skz ;[INF] 2, 1 + 588 588 0002F RED5B01 br !?L0002 ;[INF] 3, 3 + 589 589 ; line 68 : { + 590 590 00032 ??bb00_tsk_adc: + 591 591 ; line 69 : return; + 592 592 00032 ??eb00_tsk_adc: + 593 593 ; line 70 : } + 594 594 ; line 71 : else + 595 595 ; line 72 : { + 596 596 00032 ??bb01_tsk_adc: + 597 597 ; line 73 : task_interval = (u8)( INTERVAL_TSK_ADC / SYS_INTERVAL_TI + 598 598 ; CK ); + 599 599 $DGL 0,13 + 600 600 00032 RE50000 oneb !?L0003 ; task_interval ;[INF] 3, 1 + 601 601 00035 ??eb01_tsk_adc: + 602 602 ; line 74 : } + 603 603 ; line 75 : + 604 604 ; line 76 : + 605 605 ; line 77 : if( adc_updated ) + 606 606 $DGL 0,17 + 607 607 00035 R31020003 bt _adc_updated,$$+7 ;[INF] 4, 5 + 608 608 00039 RED3C01 br !?L0016 ;[INF] 3, 3 + 609 609 ; line 78 : { + 610 610 0003C ??bb02_tsk_adc: + 611 611 ; line 79 : if( system_status.pwr_state == ON ) + 612 612 $DGL 0,19 + 613 613 0003C R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 614 614 00040 61E8 skz ;[INF] 2, 1 + 615 615 00042 RED3C01 br !?L0016 ;[INF] 3, 3 + 616 616 ; line 80 : { + 617 617 00045 ??bb03_tsk_adc: + 618 618 ; line 81 : // Tune /////////////////////////////////////// + 619 619 ; line 82 : { + 620 620 00045 ??bb04_tsk_adc: + 621 621 ; line 83 : // 似非ヒステリシス V2 + 622 622 ; line 84 : // ガリオームには適さない + 623 623 ; line 85 : #define KIKAN 32 + 624 624 ; line 86 : static u8 old_value; + 625 625 ; line 87 : static s8 diffs; + 626 626 ; line 88 : u8 temp; + 627 627 ; line 89 : + 628 628 ; line 90 : if( abs( adc_raw_dep - old_value ) >= 2 ) + 629 629 $DGL 0,30 + 630 630 00045 R8F0100 mov a,!_adc_raw_dep ;[INF] 3, 1 + 631 631 00048 R2F0500 sub a,!?L0007 ; old_value ;[INF] 3, 1 + 632 632 0004B RFD0700 call !bs_F0075 ;[INF] 3, 3 + 633 633 0004E DC11 bc $?L0018 ;[INF] 2, 4 + 634 634 ; line 91 : { + 635 635 00050 ??bb05_tsk_adc: + 636 636 ; line 92 : // 大きく離れた + 637 637 ; line 93 : vreg_ctr[ VREG_C_TUNE ] = adc_raw_dep; + 638 638 $DGL 0,33 + 639 639 00050 R8F0100 mov a,!_adc_raw_dep ;[INF] 3, 1 + 640 640 00053 R9F0800 mov !_vreg_ctr+8,a ;[INF] 3, 1 + 641 641 ; line 94 : old_value = adc_raw_dep; + 642 642 $DGL 0,34 + 643 643 00056 R8F0100 mov a,!_adc_raw_dep ;[INF] 3, 1 + 644 644 00059 R9F0500 mov !?L0007,a ; old_value ;[INF] 3, 1 + 645 645 ; line 95 : #if 0 + 646 646 ; line 96 : 割り込み入れない; + 647 647 ; line 97 : 割り込みを入れるようであれば、ちゃんと変化チ + 648 648 ; ェックする; + 649 649 ; line 98 : + 650 650 ; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_VR_TUNE_CHANGE + 651 651 ; ); + 652 652 ; line 100 : #endif + 653 653 ; line 101 : diffs = 0; + 654 654 $DGL 0,41 + 655 655 0005C RF50600 clrb !?L0008 ; diffs ;[INF] 3, 1 + 656 656 0005F ??eb05_tsk_adc: + 657 657 ; line 102 : } + 658 658 $DGL 0,42 + 659 659 0005F EF5F br $?L0024 ;[INF] 2, 3 + 660 660 00061 ?L0018: + 661 661 ; line 103 : else + 662 662 ; line 104 : { + 663 663 00061 ??bb06_tsk_adc: + 664 664 ; line 105 : // 近所の値でも、ある期間でいっぱい偏っていた + 665 665 ; らそっちに寄せる + 666 666 ; line 106 : static u8 kikan_count = KIKAN; + 667 667 ; line 107 : if( old_value < adc_raw_dep ) + 668 668 $DGL 0,47 + 669 669 00061 R8F0500 mov a,!?L0007 ; old_value ;[INF] 3, 1 + 670 670 00064 R4F0100 cmp a,!_adc_raw_dep ;[INF] 3, 1 + 671 671 00067 DE05 bnc $?L0020 ;[INF] 2, 4 + 672 672 ; line 108 : { + 673 673 00069 ??bb07_tsk_adc: + 674 674 ; line 109 : diffs += 1; + 675 675 $DGL 0,49 + 676 676 00069 RA00600 inc !?L0008 ; diffs ;[INF] 3, 2 + 677 677 0006C ??eb07_tsk_adc: + 678 678 ; line 110 : } + 679 679 $DGL 0,50 + 680 680 0006C EF0B br $?L0022 ;[INF] 2, 3 + 681 681 0006E ?L0020: + 682 682 ; line 111 : else if( old_value > adc_raw_dep ) + 683 683 $DGL 0,51 + 684 684 0006E R8F0100 mov a,!_adc_raw_dep ;[INF] 3, 1 + 685 685 00071 R4F0500 cmp a,!?L0007 ; old_value ;[INF] 3, 1 + 686 686 00074 61D8 sknc ;[INF] 2, 1 + 687 687 ; line 112 : { + 688 688 00076 ??bb08_tsk_adc: + 689 689 ; line 113 : diffs -= 1; + 690 690 $DGL 0,53 + 691 691 00076 RB00600 dec !?L0008 ; diffs ;[INF] 3, 2 + 692 692 00079 ??eb08_tsk_adc: + 693 693 ; line 114 : } + 694 694 00079 ?L0022: + 695 695 ; line 115 : + 696 696 ; line 116 : if( --kikan_count == 0 ) + 697 697 $DGL 0,56 + 698 698 00079 RB00100 dec !?L0009 ; kikan_count ;[INF] 3, 2 + 699 699 0007C RD50100 cmp0 !?L0009 ; kikan_count ;[INF] 3, 1 + 700 700 0007F DF3F bnz $?L0024 ;[INF] 2, 4 + 701 701 ; line 117 : { + 702 702 00081 ??bb09_tsk_adc: + 703 703 ; line 118 : if( diffs >= KIKAN && ( diffs < 64 )) + 704 704 $DGL 0,58 + 705 705 00081 R8F0600 mov a,!?L0008 ; diffs ;[INF] 3, 1 + 706 706 00084 7C80 xor a,#080H ; 128 ;[INF] 2, 1 + 707 707 00086 4CA0 cmp a,#0A0H ; 160 ;[INF] 2, 1 + 708 708 00088 DC0E bc $?L0026 ;[INF] 2, 4 + 709 709 0008A R8F0600 mov a,!?L0008 ; diffs ;[INF] 3, 1 + 710 710 0008D 7C80 xor a,#080H ; 128 ;[INF] 2, 1 + 711 711 0008F 4CC0 cmp a,#0C0H ; 192 ;[INF] 2, 1 + 712 712 00091 DE05 bnc $?L0026 ;[INF] 2, 4 + 713 713 ; line 119 : { + 714 714 00093 ??bb0A_tsk_adc: + 715 715 ; line 120 : old_value += 1; + 716 716 $DGL 0,60 + 717 717 00093 RA00500 inc !?L0007 ; old_value ;[INF] 3, 2 + 718 718 00096 ??eb0A_tsk_adc: + 719 719 ; line 121 : } + 720 720 $DGL 0,61 + 721 721 00096 EF1B br $?L0028 ;[INF] 2, 3 + 722 722 00098 ?L0026: + 723 723 ; line 122 : else if( ( diffs <= ( 256 - KIKAN )) && + 724 724 ; ( diffs > ( 128 + 64 ) )) // あらー？ + 725 725 $DGL 0,62 + 726 726 00098 R8F0600 mov a,!?L0008 ; diffs ;[INF] 3, 1 + 727 727 0009B 318F sarw ax,8 ;[INF] 2, 1 + 728 728 0009D 44E100 cmpw ax,#0E1H ; 225 ;[INF] 3, 1 + 729 729 000A0 71FE or1 CY,a.7 ;[INF] 2, 1 + 730 730 000A2 DE0F bnc $?L0028 ;[INF] 2, 4 + 731 731 000A4 R8F0600 mov a,!?L0008 ; diffs ;[INF] 3, 1 + 732 732 000A7 318F sarw ax,8 ;[INF] 2, 1 + 733 733 000A9 44C100 cmpw ax,#0C1H ; 193 ;[INF] 3, 1 + 734 734 000AC 71FE or1 CY,a.7 ;[INF] 2, 1 + 735 735 000AE 61C8 skc ;[INF] 2, 1 + 736 736 ; line 123 : { + 737 737 000B0 ??bb0B_tsk_adc: + 738 738 ; line 124 : old_value -= 1; + 739 739 $DGL 0,64 + 740 740 000B0 RB00500 dec !?L0007 ; old_value ;[INF] 3, 2 + 741 741 000B3 ??eb0B_tsk_adc: + 742 742 ; line 125 : } + 743 743 000B3 ?L0028: + 744 744 ; line 126 : vreg_ctr[ VREG_C_TUNE ] = old_value; + 745 745 $DGL 0,66 + 746 746 000B3 R8F0500 mov a,!?L0007 ; old_value ;[INF] 3, 1 + 747 747 000B6 R9F0800 mov !_vreg_ctr+8,a ;[INF] 3, 1 + 748 748 ; line 127 : kikan_count = KIKAN; + 749 749 $DGL 0,67 + 750 750 000B9 RCF010020 mov !?L0009,#020H ; kikan_count,32 ;[INF] 4, 1 + 751 751 ; line 128 : diffs = 0; + 752 752 $DGL 0,68 + 753 753 000BD RF50600 clrb !?L0008 ; diffs ;[INF] 3, 1 + 754 754 000C0 ??eb09_tsk_adc: + 755 755 ; line 129 : } + 756 756 000C0 ?L0024: + 757 757 000C0 ??eb06_tsk_adc: + 758 758 ; line 130 : } + 759 759 000C0 ??eb04_tsk_adc: + 760 760 ; line 131 : } + 761 761 ; line 132 : vreg_ctr[ VREG_C_DBG1 ] = vreg_ctr[ VREG_C_TUNE ]; + 762 762 $DGL 0,72 + 763 763 000C0 R8F0800 mov a,!_vreg_ctr+8 ;[INF] 3, 1 + 764 764 000C3 R9F0500 mov !_vreg_ctr+5,a ;[INF] 3, 1 + 765 765 ; line 133 : vreg_ctr[ VREG_C_DBG2 ] = adc_raw_dep; // dbg + 766 766 $DGL 0,73 + 767 767 000C6 R8F0100 mov a,!_adc_raw_dep ;[INF] 3, 1 + 768 768 000C9 R9F0600 mov !_vreg_ctr+6,a ;[INF] 3, 1 + 769 769 ; line 134 : + 770 770 ; line 135 : // Volume ///////////////////////////////////// + 771 771 ; line 136 : { + 772 772 000CC ??bb0C_tsk_adc: + 773 773 ; line 137 : // 似非ヒステリシスを付けて64段 + 774 774 ; line 138 : u8 temp; + 775 775 ; line 139 : static u8 vol_old; + 776 776 ; line 140 : static u8 force_update_vol; + 777 777 ; line 141 : + 778 778 ; line 142 : if( abs( adc_raw_vol - vol_old ) >= 2 ) // + 779 779 ; 生値でこれくらいずれたら更新 + 780 780 $DGL 0,82 + 781 781 000CC R8F0000 mov a,!_adc_raw_vol ;[INF] 3, 1 + 782 782 000CF R2F0700 sub a,!?L0010 ; vol_old ;[INF] 3, 1 + 783 783 000D2 RFD0700 call !bs_F0075 ;[INF] 3, 3 + 784 784 000D5 DC22 bc $?L0030 ;[INF] 2, 4 + 785 785 ; line 143 : { + 786 786 000D7 ??bb0D_tsk_adc: + 787 787 ; line 144 : // if( vreg_ctr[ VREG_C_SND_VOL ] != ( adc_ra + 788 788 ; w_vol / 4 ) ) + 789 789 ; line 145 : { + 790 790 000D7 ??bb0E_tsk_adc: + 791 791 ; line 146 : vol_old = adc_raw_vol; + 792 792 $DGL 0,86 + 793 793 000D7 R8F0000 mov a,!_adc_raw_vol ;[INF] 3, 1 + 794 794 000DA R9F0700 mov !?L0010,a ; vol_old ;[INF] 3, 1 + 795 795 ; line 147 : // レジスタ更新 + 796 796 ; line 148 : vreg_ctr[ VREG_C_SND_VOL ] = ( adc_raw_v + 797 797 ; ol / 4 ); + 798 798 $DGL 0,88 + 799 799 000DD RFD0000 call !bs_S0076 ;[INF] 3, 3 + 800 800 000E0 60 mov a,x ;[INF] 1, 1 + 801 801 000E1 R9F0900 mov !_vreg_ctr+9,a ;[INF] 3, 1 + 802 802 ; line 149 : vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_r + 803 803 ; aw_vol / ( 256 / 32 ); // ←adc値でよい + 804 804 $DGL 0,89 + 805 805 000E4 RD90000 mov x,!_adc_raw_vol ;[INF] 3, 1 + 806 806 000E7 F1 clrb a ;[INF] 1, 1 + 807 807 000E8 313F sarw ax,3 ;[INF] 2, 1 + 808 808 000EA 60 mov a,x ;[INF] 1, 1 + 809 809 000EB R9F0600 mov !_vreg_twl+6,a ;[INF] 3, 1 + 810 810 ; line 150 : + 811 811 ; line 151 : // codecに伝える + 812 812 ; line 152 : iic_mcu_write_a_byte( IIC_SLA_CODEC, COD + 813 813 ; EC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); + 814 814 $DGL 0,92 + 815 815 000EE RFD0000 call !bs_S0076 ;[INF] 3, 3 + 816 816 000F1 12 movw bc,ax ;[INF] 1, 1 + 817 817 000F2 RFD1400 call !bs_F0074 ;[INF] 3, 3 + 818 818 ; line 153 : #ifndef _MODEL_CTR_ + 819 819 ; line 154 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0, sl + 820 820 ; ider_to_codec[ ( 255 - adc_raw_vol ) / 4 ] ); // todo + 821 821 ; line 155 : #endif + 822 822 ; line 156 : // set_irq( VREG_C_IRQ0, REG_BIT_VR_SNDVO + 823 823 ; L_CHANGE ); // 割り込み廃止 + 824 824 ; line 157 : force_update_vol = 100; + 825 825 $DGL 0,97 + 826 826 000F5 RCF080064 mov !?L0011,#064H ; force_update_vol,100 ;[INF] 4, 1 + 827 827 000F9 ??eb0E_tsk_adc: + 828 828 ; line 158 : } + 829 829 000F9 ??eb0D_tsk_adc: + 830 830 ; line 159 : } + 831 831 000F9 ?L0030: + 832 832 ; line 160 : + 833 833 ; line 161 : { + 834 834 000F9 ??bb0F_tsk_adc: + 835 835 ; line 162 : // ポーリング + 836 836 ; line 163 : if( --force_update_vol == 0 ) + 837 837 $DGL 0,103 + 838 838 000F9 RB00800 dec !?L0011 ; force_update_vol ;[INF] 3, 2 + 839 839 000FC RD50800 cmp0 !?L0011 ; force_update_vol ;[INF] 3, 1 + 840 840 000FF DF11 bnz $?L0032 ;[INF] 2, 4 + 841 841 ; line 164 : { + 842 842 00101 ??bb10_tsk_adc: + 843 843 ; line 165 : vol_old = adc_raw_vol; + 844 844 $DGL 0,105 + 845 845 00101 R8F0000 mov a,!_adc_raw_vol ;[INF] 3, 1 + 846 846 00104 R9F0700 mov !?L0010,a ; vol_old ;[INF] 3, 1 + 847 847 ; line 166 : // レジスタ更新 + 848 848 ; line 167 : // vreg_ctr[ VREG_C_SND_VOL ] = temp; + 849 849 ; line 168 : // vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc + 850 850 ; _raw_vol / ( 256 / 32 ); // ←adc値でよい + 851 851 ; line 169 : // codecに伝える + 852 852 ; line 170 : iic_mcu_write_a_byte( IIC_SLA_CODEC, COD + 853 853 ; EC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); + 854 854 $DGL 0,110 + 855 855 00107 RFD0000 call !bs_S0076 ;[INF] 3, 3 + 856 856 0010A 12 movw bc,ax ;[INF] 1, 1 + 857 857 0010B RFD1400 call !bs_F0074 ;[INF] 3, 3 + 858 858 ; line 171 : force_update_vol = 100; + 859 859 $DGL 0,111 + 860 860 0010E RCF080064 mov !?L0011,#064H ; force_update_vol,100 ;[INF] 4, 1 + 861 861 00112 ??eb10_tsk_adc: + 862 862 ; line 172 : } + 863 863 00112 ?L0032: + 864 864 00112 ??eb0F_tsk_adc: + 865 865 ; line 173 : } + 866 866 00112 ??eb0C_tsk_adc: + 867 867 ; line 174 : } + 868 868 ; line 175 : + 869 869 ; line 176 : + 870 870 ; line 177 : // TUNE_LED /////////////////////////////////// + 871 871 ; line 178 : // ここで？仕様？ + 872 872 ; line 179 : { + 873 873 00112 ??bb11_tsk_adc: + 874 874 ; line 180 : switch ( vreg_ctr[VREG_C_LED_TUNE] ) + 875 875 $DGL 0,120 + 876 876 00112 RD92C00 mov x,!_vreg_ctr+44 ;[INF] 3, 1 + 877 877 00115 F1 clrb a ;[INF] 1, 1 + 878 878 00116 E7 onew bc ;[INF] 1, 1 + 879 879 00117 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 880 880 0011A DD1A bz $?L0037 ;[INF] 2, 4 + 881 881 0011C 23 subw ax,bc ;[INF] 1, 1 + 882 882 0011D DD05 bz $?L0035 ;[INF] 2, 4 + 883 883 0011F 23 subw ax,bc ;[INF] 1, 1 + 884 884 00120 DD0A bz $?L0036 ;[INF] 2, 4 + 885 885 00122 EF12 br $?L0037 ;[INF] 2, 3 + 886 886 ; line 181 : { + 887 887 00124 ??bb12_tsk_adc: + 888 888 ; line 182 : case LED_TUNE_ILM_ON: + 889 889 00124 ?L0035: + 890 890 ; line 183 : LED_duty_TUNE = vreg_ctr[VREG_C_LED_BRIGHT]; + 891 891 $DGL 0,123 + 892 892 00124 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 893 893 00127 F1 clrb a ;[INF] 1, 1 + 894 894 00128 BD1A movw TDR01,ax ;[INF] 2, 1 + 895 895 ; line 184 : break; + 896 896 $DGL 0,124 + 897 897 0012A EF0D br $?L0034 ;[INF] 2, 3 + 898 898 ; line 185 : + 899 899 ; line 186 : case LED_TUNE_ILM_SVR: + 900 900 0012C ?L0036: + 901 901 ; line 187 : LED_duty_TUNE = vreg_ctr[VREG_C_TUNE] / 16; + 902 902 $DGL 0,127 + 903 903 0012C RD90800 mov x,!_vreg_ctr+8 ;[INF] 3, 1 + 904 904 0012F F1 clrb a ;[INF] 1, 1 + 905 905 00130 314F sarw ax,4 ;[INF] 2, 1 + 906 906 00132 BD1A movw TDR01,ax ;[INF] 2, 1 + 907 907 ; line 188 : break; + 908 908 $DGL 0,128 + 909 909 00134 EF03 br $?L0034 ;[INF] 2, 3 + 910 910 ; line 189 : + 911 911 ; line 190 : case LED_TUNE_ILM_OFF: + 912 912 00136 ?L0037: + 913 913 ; line 191 : default: + 914 914 ; line 192 : LED_duty_TUNE = 0; + 915 915 $DGL 0,132 + 916 916 00136 F6 clrw ax ;[INF] 1, 1 + 917 917 00137 BD1A movw TDR01,ax ;[INF] 2, 1 + 918 918 ; line 193 : break; + 919 919 00139 ??eb12_tsk_adc: + 920 920 ; line 194 : } + 921 921 00139 ?L0034: + 922 922 00139 ??eb11_tsk_adc: + 923 923 ; line 195 : } + 924 924 ; line 196 : adc_updated = 0; + 925 925 $DGL 0,136 + 926 926 00139 R710300 clr1 _adc_updated ;[INF] 3, 2 + 927 927 0013C ??eb03_tsk_adc: + 928 928 ; line 197 : } + 929 929 0013C ?L0016: + 930 930 0013C ??eb02_tsk_adc: + 931 931 ; line 198 : } + 932 932 ; line 199 : + 933 933 ; line 200 : + 934 934 ; line 201 : ADCEN = 1; + 935 935 $DGL 0,141 + 936 936 0013C 7150F000 set1 !PER0.5 ;[INF] 4, 2 + 937 937 ; line 202 : ADM = 0b00011011; // セレクトモード、章圧、fCLK/6 ///こ + 938 938 ; こから ↓ + 939 939 $DGL 0,142 + 940 940 00140 CE301B mov ADM,#01BH ; 27 ;[INF] 3, 1 + 941 941 ; line 203 : + 942 942 ; line 204 : ADPC = 0x06; // ADCポートのセレクト + 943 943 $DGL 0,144 + 944 944 00143 CF170006 mov !ADPC,#06H ; 6 ;[INF] 4, 1 + 945 945 ; line 205 : ADS = ADC_SEL_TUNE; + 946 946 $DGL 0,145 + 947 947 00147 CE3106 mov ADS,#06H ; 6 ;[INF] 3, 1 + 948 948 ; line 206 : NOP(); + 949 949 $DGL 0,146 + 950 950 0014A 00 nop ;[INF] 1, 1 + 951 951 ; line 207 : NOP(); + 952 952 $DGL 0,147 + 953 953 0014B 00 nop ;[INF] 1, 1 + 954 954 ; line 208 : NOP(); + 955 955 $DGL 0,148 + 956 956 0014C 00 nop ;[INF] 1, 1 + 957 957 ; line 209 : NOP(); + 958 958 $DGL 0,149 + 959 959 0014D 00 nop ;[INF] 1, 1 + 960 960 ; line 210 : NOP(); + 961 961 $DGL 0,150 + 962 962 0014E 00 nop ;[INF] 1, 1 + 963 963 ; line 211 : NOP(); + 964 964 $DGL 0,151 + 965 965 0014F 00 nop ;[INF] 1, 1 + 966 966 ; line 212 : NOP(); + 967 967 $DGL 0,152 + 968 968 00150 00 nop ;[INF] 1, 1 + 969 969 ; line 213 : NOP(); + 970 970 $DGL 0,153 + 971 971 00151 00 nop ;[INF] 1, 1 + 972 972 ; line 214 : ADCS = 1; // AD開始。 /// + 973 973 ; ここまで　↑　までに1us=8clk以上開ける + 974 974 $DGL 0,154 + 975 975 00152 717A30 set1 ADM.7 ;[INF] 3, 2 + 976 976 ; line 215 : + 977 977 ; line 216 : ADIF = 0; + 978 978 $DGL 0,156 + 979 979 00155 710BE3 clr1 IF1H.0 ;[INF] 3, 2 + 980 980 ; line 217 : ADMK = 0; + 981 981 $DGL 0,157 + 982 982 00158 710BE7 clr1 MK1H.0 ;[INF] 3, 2 + 983 983 ; line 218 : + 984 984 ; line 219 : } + 985 985 0015B ?L0002: + 986 986 $DGL 0,159 + 987 987 0015B ??ef_tsk_adc: + 988 988 0015B C6 pop hl ;[INF] 1, 1 + 989 989 0015C D7 ret ;[INF] 1, 6 + 990 990 0015D ??ee_tsk_adc: + 991 991 ; line 220 : + 992 992 ; line 221 : + 993 993 ; line 222 : /* ======================================================== + 994 994 ; line 223 : 　過去３つのminでもMAXでもない値を返す + 995 995 ; line 224 : 　突発的なノイズを除く。 + 996 996 ; line 225 : 　根本対策ではないが、これはこれで使い道がある。 + 997 997 ; line 226 : ======================================================== */ + 998 998 ; line 227 : static u8 getmean3( u8 * hist ) + 999 999 ; line 228 : { + 1000 1000 0015D _getmean3: + 1001 1001 $DGL 1,181 + 1002 1002 0015D C7 push hl ;[INF] 1, 1 + 1003 1003 0015E 16 movw hl,ax ;[INF] 1, 1 + 1004 1004 0015F ??bf_getmean3: + 1005 1005 ; line 229 : if( *hist > *( hist + 1 ) ) + 1006 1006 $DGL 0,2 + 1007 1007 0015F 8B mov a,[hl] ;[INF] 1, 1 + 1008 1008 00160 72 mov c,a ;[INF] 1, 1 + 1009 1009 00161 8C01 mov a,[hl+1] ;[INF] 2, 1 + 1010 1010 00163 614A cmp a,c ;[INF] 2, 1 + 1011 1011 00165 DE24 bnc $?L0043 ;[INF] 2, 4 + 1012 1012 ; line 230 : { + 1013 1013 00167 ??bb00_getmean3: + 1014 1014 ; line 231 : if( *hist > *( hist + 2 ) ) + 1015 1015 $DGL 0,4 + 1016 1016 00167 8B mov a,[hl] ;[INF] 1, 1 + 1017 1017 00168 72 mov c,a ;[INF] 1, 1 + 1018 1018 00169 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1019 1019 0016B 614A cmp a,c ;[INF] 2, 1 + 1020 1020 0016D DE16 bnc $?L0045 ;[INF] 2, 4 + 1021 1021 ; line 232 : { + 1022 1022 0016F ??bb01_getmean3: + 1023 1023 ; line 233 : return( ( *( hist + 1 ) > *( hist + 2 ) ) ? *( hist + 1024 1024 ; + 1 ) : *( hist + 2 ) ); + 1025 1025 $DGL 0,6 + 1026 1026 0016F 8C01 mov a,[hl+1] ;[INF] 2, 1 + 1027 1027 00171 72 mov c,a ;[INF] 1, 1 + 1028 1028 00172 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1029 1029 00174 614A cmp a,c ;[INF] 2, 1 + 1030 1030 00176 DE06 bnc $?L0047 ;[INF] 2, 4 + 1031 1031 00178 8C01 mov a,[hl+1] ;[INF] 2, 1 + 1032 1032 0017A 318E shrw ax,8 ;[INF] 2, 1 + 1033 1033 0017C EF04 br $?L0048 ;[INF] 2, 3 + 1034 1034 0017E ?L0047: + 1035 1035 0017E 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1036 1036 00180 318E shrw ax,8 ;[INF] 2, 1 + 1037 1037 00182 ?L0048: + 1038 1038 00182 12 movw bc,ax ;[INF] 1, 1 + 1039 1039 00183 EF28 br $?L0050 ;[INF] 2, 3 + 1040 1040 00185 ??eb01_getmean3: + 1041 1041 ; line 234 : } + 1042 1042 00185 ?L0045: + 1043 1043 ; line 235 : else + 1044 1044 ; line 236 : { + 1045 1045 00185 ??bb02_getmean3: + 1046 1046 ; line 237 : return( *hist ); + 1047 1047 $DGL 0,10 + 1048 1048 00185 8B mov a,[hl] ;[INF] 1, 1 + 1049 1049 00186 318E shrw ax,8 ;[INF] 2, 1 + 1050 1050 00188 12 movw bc,ax ;[INF] 1, 1 + 1051 1051 00189 EF22 br $?L0050 ;[INF] 2, 3 + 1052 1052 0018B ??eb02_getmean3: + 1053 1053 ; line 238 : } + 1054 1054 ; line 239 : }else{ + 1055 1055 0018B ??eb00_getmean3: + 1056 1056 0018B ?L0043: + 1057 1057 0018B ??bb03_getmean3: + 1058 1058 ; line 240 : if( *hist > *( hist + 2 ) ) + 1059 1059 $DGL 0,13 + 1060 1060 0018B 8B mov a,[hl] ;[INF] 1, 1 + 1061 1061 0018C 72 mov c,a ;[INF] 1, 1 + 1062 1062 0018D 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1063 1063 0018F 614A cmp a,c ;[INF] 2, 1 + 1064 1064 00191 DE06 bnc $?L0049 ;[INF] 2, 4 + 1065 1065 ; line 241 : { + 1066 1066 00193 ??bb04_getmean3: + 1067 1067 ; line 242 : return( *hist ); + 1068 1068 $DGL 0,15 + 1069 1069 00193 8B mov a,[hl] ;[INF] 1, 1 + 1070 1070 00194 318E shrw ax,8 ;[INF] 2, 1 + 1071 1071 00196 12 movw bc,ax ;[INF] 1, 1 + 1072 1072 00197 EF14 br $?L0050 ;[INF] 2, 3 + 1073 1073 00199 ??eb04_getmean3: + 1074 1074 ; line 243 : } + 1075 1075 00199 ?L0049: + 1076 1076 ; line 244 : else + 1077 1077 ; line 245 : { + 1078 1078 00199 ??bb05_getmean3: + 1079 1079 ; line 246 : return( ( *( hist + 1 ) < *( hist + 2 ) ) ? *( hist + 1080 1080 ; + 1 ) : *( hist + 2 ) ); + 1081 1081 $DGL 0,19 + 1082 1082 00199 8C01 mov a,[hl+1] ;[INF] 2, 1 + 1083 1083 0019B 72 mov c,a ;[INF] 1, 1 + 1084 1084 0019C 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1085 1085 0019E 6142 cmp c,a ;[INF] 2, 1 + 1086 1086 001A0 DE06 bnc $?L0051 ;[INF] 2, 4 + 1087 1087 001A2 8C01 mov a,[hl+1] ;[INF] 2, 1 + 1088 1088 001A4 318E shrw ax,8 ;[INF] 2, 1 + 1089 1089 001A6 EF04 br $?L0052 ;[INF] 2, 3 + 1090 1090 001A8 ?L0051: + 1091 1091 001A8 8C02 mov a,[hl+2] ;[INF] 2, 1 + 1092 1092 001AA 318E shrw ax,8 ;[INF] 2, 1 + 1093 1093 001AC ?L0052: + 1094 1094 001AC 12 movw bc,ax ;[INF] 1, 1 + 1095 1095 001AD ??eb05_getmean3: + 1096 1096 ; line 247 : } + 1097 1097 001AD ?L0050: + 1098 1098 001AD ??eb03_getmean3: + 1099 1099 ; line 248 : } + 1100 1100 ; line 249 : } + 1101 1101 $DGL 0,22 + 1102 1102 001AD ??ef_getmean3: + 1103 1103 001AD C6 pop hl ;[INF] 1, 1 + 1104 1104 001AE D7 ret ;[INF] 1, 6 + 1105 1105 001AF ??ee_getmean3: + 1106 1106 ; line 250 : + 1107 1107 ; line 251 : + 1108 1108 ; line 252 : + 1109 1109 ; line 253 : /* ======================================================== + 1110 1110 ; line 254 : 　自前で次のチャンネル + 1111 1111 ; line 255 : 　　一通り終わったら止める + 1112 1112 ; line 256 : ======================================================== */ + 1113 1113 ; line 257 : __interrupt void int_adc( ) + 1114 1114 ; line 258 : { + 1115 1115 + 1116 1116 ----- @@BASE CSEG BASE + 1117 1117 00000 _int_adc: + 1118 1118 $DGL 1,213 + 1119 1119 00000 C1 push ax ;[INF] 1, 1 + 1120 1120 00001 C3 push bc ;[INF] 1, 1 + 1121 1121 00002 C5 push de ;[INF] 1, 1 + 1122 1122 00003 C7 push hl ;[INF] 1, 1 + 1123 1123 00004 520C mov c,#0CH ;[INF] 2, 1 + 1124 1124 00006 92 dec c ;[INF] 1, 1 + 1125 1125 00007 92 dec c ;[INF] 1, 1 + 1126 1126 00008 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 1127 1127 0000B C1 push ax ;[INF] 1, 1 + 1128 1128 0000C DFF8 bnz $$-6 ;[INF] 2, 4 + 1129 1129 0000E 8EFD mov a,ES ;[INF] 2, 1 + 1130 1130 00010 70 mov x,a ;[INF] 1, 1 + 1131 1131 00011 8EFC mov a,CS ;[INF] 2, 1 + 1132 1132 00013 C1 push ax ;[INF] 1, 1 + 1133 1133 00014 ??bf_int_adc: + 1134 1134 ; line 259 : static u8 hist_tune[3]; + 1135 1135 ; line 260 : static u8 hist_snd_vol[3]; + 1136 1136 ; line 261 : static u8 hist_bt_temp[3]; + 1137 1137 ; line 262 : static u8 index; + 1138 1138 ; line 263 : + 1139 1139 ; line 264 : EI( ); + 1140 1140 $DGL 0,7 + 1141 1141 00014 717AFA ei ;[INF] 3, 4 + 1142 1142 ; line 265 : switch ( ADS ) + 1143 1143 $DGL 0,8 + 1144 1144 00017 8E31 mov a,ADS ;[INF] 2, 1 + 1145 1145 00019 318E shrw ax,8 ;[INF] 2, 1 + 1146 1146 0001B E7 onew bc ;[INF] 1, 1 + 1147 1147 0001C 240600 subw ax,#06H ; 6 ;[INF] 3, 1 + 1148 1148 0001F DD09 bz $?L0060 ;[INF] 2, 4 + 1149 1149 00021 23 subw ax,bc ;[INF] 1, 1 + 1150 1150 00022 DD1D bz $?L0061 ;[INF] 2, 4 + 1151 1151 00024 23 subw ax,bc ;[INF] 1, 1 + 1152 1152 00025 DD31 bz $?L0062 ;[INF] 2, 4 + 1153 1153 00027 23 subw ax,bc ;[INF] 1, 1 + 1154 1154 00028 EF49 br $?L0059 ;[INF] 2, 3 + 1155 1155 ; line 266 : { + 1156 1156 0002A ??bb00_int_adc: + 1157 1157 ; line 267 : /* + 1158 1158 ; line 268 : case ( ADC_SEL_AMB_BRIT ): + 1159 1159 ; line 269 : vreg_ctr[ VREG_C_AMBIENT_BRIGHTNESS ] = ADCRH; + 1160 1160 ; line 270 : break; + 1161 1161 ; line 271 : */ + 1162 1162 ; line 272 : + 1163 1163 ; line 273 : case ( ADC_SEL_TUNE ): + 1164 1164 0002A ?L0060: + 1165 1165 ; line 274 : hist_tune[index] = ADCRH; + 1166 1166 $DGL 0,17 + 1167 1167 0002A RD91200 mov x,!?L0058 ; index ;[INF] 3, 1 + 1168 1168 0002D F1 clrb a ;[INF] 1, 1 + 1169 1169 0002E R040900 addw ax,#loww (?L0055) ; hist_tune ;[INF] 3, 1 + 1170 1170 00031 14 movw de,ax ;[INF] 1, 1 + 1171 1171 00032 8D1F mov a,ADCRH ;[INF] 2, 1 + 1172 1172 00034 99 mov [de],a ;[INF] 1, 1 + 1173 1173 ; line 275 : #ifdef _MODEL_WM0_ + 1174 1174 ; line 276 : adc_raw_dep = 255 - getmean3( hist_tune ); + 1175 1175 ; line 277 : #else + 1176 1176 ; line 278 : adc_raw_dep = getmean3( hist_tune ); + 1177 1177 $DGL 0,21 + 1178 1178 00035 R300900 movw ax,#loww (?L0055) ; hist_tune ;[INF] 3, 1 + 1179 1179 00038 RFD5D01 call !_getmean3 ;[INF] 3, 3 + 1180 1180 0003B 62 mov a,c ;[INF] 1, 1 + 1181 1181 0003C R9F0100 mov !_adc_raw_dep,a ;[INF] 3, 1 + 1182 1182 ; line 279 : #endif + 1183 1183 ; line 280 : break; + 1184 1184 $DGL 0,23 + 1185 1185 0003F EF32 br $?L0059 ;[INF] 2, 3 + 1186 1186 ; line 281 : + 1187 1187 ; line 282 : case ( ADC_SEL_VOL ): + 1188 1188 00041 ?L0061: + 1189 1189 ; line 283 : hist_snd_vol[index] = ADCRH; + 1190 1190 $DGL 0,26 + 1191 1191 00041 RD91200 mov x,!?L0058 ; index ;[INF] 3, 1 + 1192 1192 00044 F1 clrb a ;[INF] 1, 1 + 1193 1193 00045 R040C00 addw ax,#loww (?L0056) ; hist_snd_vol ;[INF] 3, 1 + 1194 1194 00048 14 movw de,ax ;[INF] 1, 1 + 1195 1195 00049 8D1F mov a,ADCRH ;[INF] 2, 1 + 1196 1196 0004B 99 mov [de],a ;[INF] 1, 1 + 1197 1197 ; line 284 : #ifdef _MODEL_CTR_JIKKI_ + 1198 1198 ; line 285 : adc_raw_vol = ( 255 - getmean3( hist_snd_vol )); + 1199 1199 ; line 286 : #else + 1200 1200 ; line 287 : adc_raw_vol = getmean3( hist_snd_vol ); + 1201 1201 $DGL 0,30 + 1202 1202 0004C R300C00 movw ax,#loww (?L0056) ; hist_snd_vol ;[INF] 3, 1 + 1203 1203 0004F RFD5D01 call !_getmean3 ;[INF] 3, 3 + 1204 1204 00052 62 mov a,c ;[INF] 1, 1 + 1205 1205 00053 R9F0000 mov !_adc_raw_vol,a ;[INF] 3, 1 + 1206 1206 ; line 288 : #endif + 1207 1207 ; line 289 : // TWL用レジスタ(32段)の更新。アトミックな処理として扱わ + 1208 1208 ; ないと不都合が。 + 1209 1209 ; line 290 : /// 割り込みはHorizonを通してコマンドを発行されるのを待て + 1210 1210 ; ばよい + 1211 1211 ; line 291 : break; + 1212 1212 $DGL 0,34 + 1213 1213 00056 EF1B br $?L0059 ;[INF] 2, 3 + 1214 1214 ; line 292 : + 1215 1215 ; line 293 : case ( ADC_SEL_BATT_TEMP ): + 1216 1216 00058 ?L0062: + 1217 1217 ; line 294 : hist_bt_temp[index] = ADCRH; + 1218 1218 $DGL 0,37 + 1219 1219 00058 RD91200 mov x,!?L0058 ; index ;[INF] 3, 1 + 1220 1220 0005B F1 clrb a ;[INF] 1, 1 + 1221 1221 0005C R040F00 addw ax,#loww (?L0057) ; hist_bt_temp ;[INF] 3, 1 + 1222 1222 0005F 14 movw de,ax ;[INF] 1, 1 + 1223 1223 00060 8D1F mov a,ADCRH ;[INF] 2, 1 + 1224 1224 00062 99 mov [de],a ;[INF] 1, 1 + 1225 1225 ; line 295 : raw_adc_temperature = getmean3( hist_bt_temp ); + 1226 1226 $DGL 0,38 + 1227 1227 00063 R300F00 movw ax,#loww (?L0057) ; hist_bt_temp ;[INF] 3, 1 + 1228 1228 00066 RFD5D01 call !_getmean3 ;[INF] 3, 3 + 1229 1229 00069 62 mov a,c ;[INF] 1, 1 + 1230 1230 0006A R9F0000 mov !_raw_adc_temperature,a ;[INF] 3, 1 + 1231 1231 ; line 296 : renge_task_immed_add( PM_bt_temp_update ); + 1232 1232 $DGL 0,39 + 1233 1233 0006D R300000 movw ax,#loww (_PM_bt_temp_update) ;[INF] 3, 1 + 1234 1234 00070 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1235 1235 ; line 297 : break; + 1236 1236 ; line 298 : + 1237 1237 ; line 299 : case ( ADC_SEL_BATT_DET ): + 1238 1238 ; line 300 : // vreg_ctr[ VREG_C_DBG_BATT_DET ] = ADCRH; + 1239 1239 ; line 301 : // todo + 1240 1240 ; line 302 : break; + 1241 1241 00073 ??eb00_int_adc: + 1242 1242 ; line 303 : } + 1243 1243 00073 ?L0059: + 1244 1244 ; line 304 : + 1245 1245 ; line 305 : + 1246 1246 ; line 306 : // もっとまともな書き方がありそうだ + 1247 1247 ; line 307 : // if( ADS == ADC_SEL_BATT_DET ){ + 1248 1248 ; line 308 : if( ADS != ADC_SEL_BATT_TEMP ) + 1249 1249 $DGL 0,51 + 1250 1250 00073 4031FF08 cmp !ADS,#08H ; 8 ;[INF] 4, 1 + 1251 1251 00077 DD08 bz $?L0066 ;[INF] 2, 4 + 1252 1252 ; line 309 : { // 電池判別は電源投入の一回のみ + 1253 1253 00079 ??bb01_int_adc: + 1254 1254 ; line 310 : ADS += 1; // 次のチャンネル + 1255 1255 $DGL 0,53 + 1256 1256 00079 A031FF inc !ADS ;[INF] 3, 2 + 1257 1257 ; line 311 : BT_TEMP_P = 1; // 電池温度監視スタート + 1258 1258 $DGL 0,54 + 1259 1259 0007C 717201 set1 P1.7 ;[INF] 3, 2 + 1260 1260 0007F ??eb01_int_adc: + 1261 1261 ; line 312 : } + 1262 1262 $DGL 0,55 + 1263 1263 0007F EF1C br $?L0067 ;[INF] 2, 3 + 1264 1264 00081 ?L0066: + 1265 1265 ; line 313 : else + 1266 1266 ; line 314 : { + 1267 1267 00081 ??bb02_int_adc: + 1268 1268 ; line 315 : ADCEN = 0; // 止めてしまう + 1269 1269 $DGL 0,58 + 1270 1270 00081 7158F000 clr1 !PER0.5 ;[INF] 4, 2 + 1271 1271 ; line 316 : BT_TEMP_P = 0; // 電池温度監視スタート + 1272 1272 $DGL 0,59 + 1273 1273 00085 717301 clr1 P1.7 ;[INF] 3, 2 + 1274 1274 ; line 317 : adc_updated = 1; + 1275 1275 $DGL 0,60 + 1276 1276 00088 R710200 set1 _adc_updated ;[INF] 3, 2 + 1277 1277 ; line 318 : index = ( index == 2 ) ? 0 : ( index + 1 ); + 1278 1278 $DGL 0,61 + 1279 1279 0008B R40120002 cmp !?L0058,#02H ; index,2 ;[INF] 4, 1 + 1280 1280 0008F DF03 bnz $?L0068 ;[INF] 2, 4 + 1281 1281 00091 F6 clrw ax ;[INF] 1, 1 + 1282 1282 00092 EF05 br $?L0069 ;[INF] 2, 3 + 1283 1283 00094 ?L0068: + 1284 1284 00094 RD91200 mov x,!?L0058 ; index ;[INF] 3, 1 + 1285 1285 00097 F1 clrb a ;[INF] 1, 1 + 1286 1286 00098 A1 incw ax ;[INF] 1, 1 + 1287 1287 00099 ?L0069: + 1288 1288 00099 60 mov a,x ;[INF] 1, 1 + 1289 1289 0009A R9F1200 mov !?L0058,a ; index ;[INF] 3, 1 + 1290 1290 0009D ??eb02_int_adc: + 1291 1291 ; line 319 : } + 1292 1292 0009D ?L0067: + 1293 1293 ; line 320 : } + 1294 1294 $DGL 0,63 + 1295 1295 0009D ??ef_int_adc: + 1296 1296 0009D C0 pop ax ;[INF] 1, 1 + 1297 1297 0009E 9EFC mov CS,a ;[INF] 2, 1 + 1298 1298 000A0 60 mov a,x ;[INF] 1, 1 + 1299 1299 000A1 9EFD mov ES,a ;[INF] 2, 1 + 1300 1300 000A3 R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 1301 1301 000A6 5206 mov c,#06H ;[INF] 2, 1 + 1302 1302 000A8 C0 pop ax ;[INF] 1, 1 + 1303 1303 000A9 B9 movw [de],ax ;[INF] 1, 1 + 1304 1304 000AA A5 incw de ;[INF] 1, 1 + 1305 1305 000AB A5 incw de ;[INF] 1, 1 + 1306 1306 000AC 92 dec c ;[INF] 1, 1 + 1307 1307 000AD DFF9 bnz $$-5 ;[INF] 2, 4 + 1308 1308 000AF C6 pop hl ;[INF] 1, 1 + 1309 1309 000B0 C4 pop de ;[INF] 1, 1 + 1310 1310 000B1 C2 pop bc ;[INF] 1, 1 + 1311 1311 000B2 C0 pop ax ;[INF] 1, 1 + 1312 1312 000B3 61FC reti ;[INF] 2, 6 + 1313 1313 000B5 ??ee_int_adc: + 1314 1314 ; line 321 : + 1315 1315 ; line 322 : + 1316 1316 ; line 323 : + 1317 1317 ; line 324 : /* ======================================================== + 1318 1318 ; line 325 : tsk_adcと競合することを考慮していません。 + 1319 1319 ; line 326 : ======================================================== */ + 1320 1320 ; line 327 : u8 get_adc( u8 ch ) + 1321 1321 ; line 328 : { + 1322 1322 + 1323 1323 ----- ROM_CODE CSEG BASE + 1324 1324 001AF _get_adc: + 1325 1325 $DGL 1,238 + 1326 1326 001AF C7 push hl ;[INF] 1, 1 + 1327 1327 001B0 16 movw hl,ax ;[INF] 1, 1 + 1328 1328 001B1 ??bf_get_adc: + 1329 1329 ; line 329 : u8 temp; + 1330 1330 ; line 330 : + 1331 1331 ; line 331 : ADMK = 1; + 1332 1332 $DGL 0,4 + 1333 1333 001B1 710AE7 set1 MK1H.0 ;[INF] 3, 2 + 1334 1334 ; line 332 : ADIF = 0; + 1335 1335 $DGL 0,5 + 1336 1336 001B4 710BE3 clr1 IF1H.0 ;[INF] 3, 2 + 1337 1337 ; line 333 : + 1338 1338 ; line 334 : ADCEN = 1; + 1339 1339 $DGL 0,7 + 1340 1340 001B7 7150F000 set1 !PER0.5 ;[INF] 4, 2 + 1341 1341 ; line 335 : ADCS = 0; + 1342 1342 $DGL 0,8 + 1343 1343 001BB 717B30 clr1 ADM.7 ;[INF] 3, 2 + 1344 1344 ; line 336 : ADM = 0b00100011; // セレクトモード、昇圧、fCLK/6 + 1345 1345 ; ///ここから↓ + 1346 1346 $DGL 0,9 + 1347 1347 001BE CE3023 mov ADM,#023H ; 35 ;[INF] 3, 1 + 1348 1348 ; line 337 : + 1349 1349 ; line 338 : ADPC = 0x06; // ADCポートのセレクト + 1350 1350 $DGL 0,11 + 1351 1351 001C1 CF170006 mov !ADPC,#06H ; 6 ;[INF] 4, 1 + 1352 1352 ; line 339 : ADS = ch; + 1353 1353 $DGL 0,12 + 1354 1354 001C5 66 mov a,l ;[INF] 1, 1 + 1355 1355 001C6 9E31 mov ADS,a ;[INF] 2, 1 + 1356 1356 ; line 340 : NOP(); + 1357 1357 $DGL 0,13 + 1358 1358 001C8 00 nop ;[INF] 1, 1 + 1359 1359 ; line 341 : NOP(); + 1360 1360 $DGL 0,14 + 1361 1361 001C9 00 nop ;[INF] 1, 1 + 1362 1362 ; line 342 : NOP(); + 1363 1363 $DGL 0,15 + 1364 1364 001CA 00 nop ;[INF] 1, 1 + 1365 1365 ; line 343 : NOP(); + 1366 1366 $DGL 0,16 + 1367 1367 001CB 00 nop ;[INF] 1, 1 + 1368 1368 ; line 344 : NOP(); + 1369 1369 $DGL 0,17 + 1370 1370 001CC 00 nop ;[INF] 1, 1 + 1371 1371 ; line 345 : NOP(); + 1372 1372 $DGL 0,18 + 1373 1373 001CD 00 nop ;[INF] 1, 1 + 1374 1374 ; line 346 : NOP(); + 1375 1375 $DGL 0,19 + 1376 1376 001CE 00 nop ;[INF] 1, 1 + 1377 1377 ; line 347 : NOP(); + 1378 1378 $DGL 0,20 + 1379 1379 001CF 00 nop ;[INF] 1, 1 + 1380 1380 ; line 348 : ADCS = 1; // AD開始。 + 1381 1381 ; /// ここまで↑　に、1us以上開ける + 1382 1382 $DGL 0,21 + 1383 1383 001D0 717A30 set1 ADM.7 ;[INF] 3, 2 + 1384 1384 ; line 349 : + 1385 1385 ; line 350 : ADMK = 0; + 1386 1386 $DGL 0,23 + 1387 1387 001D3 710BE7 clr1 MK1H.0 ;[INF] 3, 2 + 1388 1388 ; line 351 : while( ADIF == 0 ){;} + 1389 1389 $DGL 0,24 + 1390 1390 001D6 ?L0072: + 1391 1391 001D6 3182E302 bt IF1H.0,$?L0073 ;[INF] 4, 5 + 1392 1392 001DA ??bb00_get_adc: + 1393 1393 001DA ??eb00_get_adc: + 1394 1394 001DA EFFA br $?L0072 ;[INF] 2, 3 + 1395 1395 001DC ?L0073: + 1396 1396 ; line 352 : temp = ADCRH; + 1397 1397 $DGL 0,25 + 1398 1398 001DC 8D1F mov a,ADCRH ;[INF] 2, 1 + 1399 1399 ; line 353 : ADCEN = 0; + 1400 1400 $DGL 0,26 + 1401 1401 001DE 7158F000 clr1 !PER0.5 ;[INF] 4, 2 + 1402 1402 ; line 354 : + 1403 1403 ; line 355 : return ( temp ); + 1404 1404 $DGL 0,28 + 1405 1405 001E2 318E shrw ax,8 ;[INF] 2, 1 + 1406 1406 001E4 12 movw bc,ax ;[INF] 1, 1 + 1407 1407 ; line 356 : } + 1408 1408 $DGL 0,29 + 1409 1409 001E5 ??ef_get_adc: + 1410 1410 001E5 C6 pop hl ;[INF] 1, 1 + 1411 1411 001E6 D7 ret ;[INF] 1, 6 + 1412 1412 001E7 ??ee_get_adc: + 1413 1413 + 1414 1414 ----- @@CODEL CSEG + 1415 1415 END + 1416 1416 + 1417 1417 + 1418 1418 ; *** Code Information *** + 1419 1419 ; + 1420 1420 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c + 1421 1421 ; + 1422 1422 ; $FUNC tsk_adc(61) + 1423 1423 ; void=(void) + 1424 1424 ; CODE SIZE= 312 bytes, CLOCK_SIZE= 302 clocks, STACK_SIZE= 14 bytes + 1425 1425 ; + 1426 1426 ; $CALL abs(90) + 1427 1427 ; bc=(int:ax) + 1428 1428 ; + 1429 1429 ; $CALL abs(142) + 1430 1430 ; bc=(int:ax) + 1431 1431 ; + 1432 1432 ; $CALL iic_mcu_write_a_byte(152) + 1433 1433 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1434 1434 ; + 1435 1435 ; $CALL iic_mcu_write_a_byte(170) + 1436 1436 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1437 1437 ; + 1438 1438 ; $FUNC getmean3(228) + 1439 1439 ; bc=(pointer hist:ax) + 1440 1440 ; CODE SIZE= 82 bytes, CLOCK_SIZE= 80 clocks, STACK_SIZE= 2 bytes + 1441 1441 ; + 1442 1442 ; $FUNC int_adc(258) + 1443 1443 ; void=(void) + 1444 1444 ; CODE SIZE= 181 bytes, CLOCK_SIZE= 146 clocks, STACK_SIZE= 26 bytes + 1445 1445 ; + 1446 1446 ; $CALL getmean3(278) + 1447 1447 ; bc=(pointer:ax) + 1448 1448 ; + 1449 1449 ; $CALL getmean3(287) + 1450 1450 ; bc=(pointer:ax) + 1451 1451 ; + 1452 1452 ; $CALL getmean3(295) + 1453 1453 ; bc=(pointer:ax) + 1454 1454 ; + 1455 1455 ; $CALL renge_task_immed_add(296) + 1456 1456 ; bc=(pointer:ax) + 1457 1457 ; + 1458 1458 ; $FUNC get_adc(328) + 1459 1459 ; bc=(unsigned char ch:x) + 1460 1460 ; CODE SIZE= 56 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 2 bytes + 1461 1461 + 1462 1462 ; Target chip : uPD79F0104 + 1463 1463 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.1 @@BITS +00000 00070H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00014H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 001E7H ROM_CODE +00000 000B5H @@BASE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/adc.rel b/branches/0.10(X3)/adc.rel new file mode 100644 index 0000000..f447bcd Binary files /dev/null and b/branches/0.10(X3)/adc.rel differ diff --git a/branches/0.10(X3)/batt_params.h b/branches/0.10(X3)/batt_params.h new file mode 100644 index 0000000..b18a6c4 --- /dev/null +++ b/branches/0.10(X3)/batt_params.h @@ -0,0 +1,80 @@ +/* ======================================================== + 各社バッテリーパラメータ + ======================================================== */ +enum BATT_VENDER { + BT_PANASONIC, // open + BT_UNKNOWN1, + BT_UNKNOWN2, + BT_UNKNOWN3, + BT_UNKNOWN4, + BT_UNKNOWN5, + BT_UNKNOWN6, // gnd + BT_MAXELL + }; + + +static const u8 BT_PARAM[][64] = { + // ID = 0 GND 白箱 + /// パラメータ無し + { // ID = 1 120 ohm + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + }, + { // ID = 2 360 hom + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + }, + { // ID = 3 750 ohm + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + }, + { // ID = 4 1.3kohm + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + }, + { // ID = 5 2.7kohm パナ + 0xAD, 0x30, 0xAE, 0x70, 0xB0, 0x00, 0xB3, 0x00, + 0xB4, 0x70, 0xB5, 0xA0, 0xB7, 0x80, 0xBA, 0x00, + + 0xBB, 0x90, 0xBD, 0x00, 0xBE, 0x00, 0xBF, 0xF0, + 0xC3, 0x00, 0xC5, 0xC0, 0xC8, 0x00, 0xCA, 0xC0, + + 0x04, 0x00, 0x12, 0x00, 0x0C, 0x10, 0x24, 0x00, + 0x10, 0xD0, 0x1B, 0xF0, 0x0A, 0xF0, 0x08, 0xE0, + + 0x0C, 0xF0, 0x08, 0xC0, 0x08, 0xB0, 0x07, 0xF0, + 0x0B, 0x00, 0x05, 0xD0, 0x02, 0x00, 0x09, 0x00 + }, + { // ID = 6 8.2kohm + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + }, + { // ID = 7 マクセル + 0xAD, 0x30, 0xAE, 0x70, 0xB0, 0x00, 0xB3, 0x00, + 0xB4, 0x70, 0xB5, 0xA0, 0xB7, 0x80, 0xBA, 0x00, + + 0xBB, 0x90, 0xBD, 0x00, 0xBE, 0x00, 0xBF, 0xF0, + 0xC3, 0x00, 0xC5, 0xC0, 0xC8, 0x00, 0xCA, 0xC0, + + 0x04, 0x00, 0x12, 0x00, 0x0C, 0x10, 0x24, 0x00, + 0x10, 0xD0, 0x1B, 0xF0, 0x0A, 0xF0, 0x08, 0xE0, + + 0x0C, 0xF0, 0x08, 0xC0, 0x08, 0xB0, 0x07, 0xF0, + 0x0B, 0x00, 0x05, 0xD0, 0x02, 0x00, 0x09, 0x00 + } +}; + +static const unsigned char BT_PANA_RCOMP = 135; +static const float BT_PANA_TEMPCOUP = 0.3; +static const float BT_PANA_TEMPCODN = 0.5; + diff --git a/branches/0.10(X3)/bin/mcu_C2_0B_1215.bin b/branches/0.10(X3)/bin/mcu_C2_0B_1215.bin new file mode 100644 index 0000000..95154e4 Binary files /dev/null and b/branches/0.10(X3)/bin/mcu_C2_0B_1215.bin differ diff --git a/branches/0.10(X3)/bin/mcu_C2_0B_1215_2.bin b/branches/0.10(X3)/bin/mcu_C2_0B_1215_2.bin new file mode 100644 index 0000000..0ec2fe8 Binary files /dev/null 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+:104E9200DCC1410011ABBDD811AC02BDDA118C08E6 +:104EA2009DDDC7FDB706C611AC04BDD811AC06BD69 +:104EB200DA118C099DDDFD340920046ADF03FC74DC +:104EC2004F00FC004F00FDB706FC554F00FDB70632 +:104ED200C9DAC03FC9D80000F4DD51806175FD34E4 +:104EE20009FC3D4F00FDB706B4DF4ADF80DFCFFC8F +:104EF200554F00FDB706100AC0317D0514D715BD08 +:104F0200DA13BDD88DDC9DDDD7C9DA803FC9D80060 +:104F120000F4DDD7118C019DDD11AC02BDD811ACBE +:104F220004BDDA1704060016D78C019DDDAC02BD64 +:104F3200D8AC04BDDA1704060016D7A806BDDAA855 +:104F420004BDD888089DDDD7A80C14A80A128809C8 +:104F52009DDCD7A80CBDDAA80ABDD888099DDDD78B +:104F6200A80635B806A80433B804880861A8DC98F6 +:0D4F720008D715B80613B8048DDC9808D7D1 +:0A4FF60031353A32373A3433000007 +:00000001FF + \ No newline at end of file diff --git a/branches/0.10(X3)/bsr_k0r.map b/branches/0.10(X3)/bsr_k0r.map new file mode 100644 index 0000000..f41b0a4 --- /dev/null +++ b/branches/0.10(X3)/bsr_k0r.map @@ -0,0 +1,656 @@ + + + +78K0R Linker W1.31 Date:13 Jun 2010 Page: 1 + +Command: -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -obsr.l + mf ..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2 + .10\lib78k0r\s0rm.rel -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFF + FFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -bC:\Program Files\NEC El + ectronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib -bcl + 0rdm.lib -bcl0rm.lib -bcl0rmf.lib -iC:\Program Files\NEC Elec + tronics Tools\CC78K0R\W2.10\lib78k0r -dbsr_mcu.dr -s -w0 load + er.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu. + rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vre + g_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot. + rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg + _thre_det2.rel +Para-file: +Out-file: bsr.lmf +Map-file: bsr_k0r.map +Direc-file:bsr_mcu.dr + + +*** Link information *** + + 68 output segment(s) + 3ED6H byte(s) real data + 4631 symbol(s) defined + + +*** Memory map *** + + + SPACE=REGULAR + + MEMORY=BCL0 + BASE ADDRESS=00000H SIZE=01000H + OUTPUT INPUT INPUT BASE SIZE + SEGMENT SEGMENT MODULE ADDRESS + @@VECT00 00000H 00002H CSEG AT + @@VECT00 @cstart 00000H 00002H + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL loader 00002H 00000H + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL main 00002H 00000H + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL WDT 00002H 00000H + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL self_flash + 00002H 00000H + LDR_CNSL 00002H 00000H CSEG PAGE64KP + LDR_CNSL reboot 00002H 00000H + ??NMIROM 00002H 00002H CSEG +* gap * 00004H 0000CH + @@VECT10 00010H 00004H CSEG AT + @@VECT10 ini_VECT 00010H 00004H +* gap * 00014H 00008H + @@VECT1C 0001CH 00002H CSEG AT + @@VECT1C ini_VECT 0001CH 00002H +* gap * 0001EH 00006H + @@VECT24 00024H 00002H CSEG AT + @@VECT24 ini_VECT 00024H 00002H +* gap * 00026H 00004H + @@VECT2A 0002AH 00002H CSEG AT + @@VECT2A ini_VECT 0002AH 00002H +* gap * 0002CH 00008H + @@VECT34 00034H 00008H CSEG AT + @@VECT34 ini_VECT 00034H 00008H +* gap * 0003CH 0000EH + @@VECT4A 0004AH 00002H CSEG AT + @@VECT4A ini_VECT 0004AH 00002H +* gap * 0004CH 0000EH + @@VECT5A 0005AH 00002H CSEG AT + @@VECT5A ini_VECT 0005AH 00002H +* gap * 0005CH 00006H + @@VECT62 00062H 00002H CSEG AT + @@VECT62 ini_VECT 00062H 00002H +* gap * 00064H 0005CH + ?CSEGOB0 000C0H 00004H CSEG OPT_BYTE + @@CODE 000C4H 00000H CSEG BASE + @@CODE magic 000C4H 00000H + @@CODE ini_VECT 000C4H 00000H + LDR_CODL 000C4H 00000H CSEG + LDR_CODL loader 000C4H 00000H + LDR_CODL main 000C4H 00000H + LDR_CODL WDT 000C4H 00000H + LDR_CODL self_flash + 000C4H 00000H + LDR_CODL reboot 000C4H 00000H + ?CSEGSI 000C4H 0000AH CSEG + ?OCDSTAD 000CEH 0000AH CSEG + LDR_CODE 000D8H 00402H CSEG + LDR_CODE loader 000D8H 0017EH + LDR_CODE main 00256H 00082H + LDR_CODE WDT 002D8H 00004H + LDR_CODE self_flash + 002DCH 001F2H + LDR_CODE reboot 004CEH 0000CH + @@LCODE 004DAH 007BDH CSEG + @@LCODE @cstart 004DAH 0006DH + @@LCODE @lumul 00547H 0002BH + @@LCODE @isrem 00572H 00021H + @@LCODE @iurem 00593H 0002FH + @@LCODE @lsdiv 005C2H 00039H + @@LCODE @ludiv 005FBH 0003FH + @@LCODE @ladd 0063AH 0000FH + @@LCODE @iscmp 00649H 0000CH + @@LCODE @lband 00655H 00014H + @@LCODE @bcdtob 00669H 0001AH + @@LCODE @bbcd 00683H 00024H + @@LCODE m_fmul 006A7H 00151H + @@LCODE m_fcom1 007F8H 000CFH + @@LCODE m_fcom5 008C7H 0002AH + @@LCODE m_fcom6 008F1H 0001FH + @@LCODE m_fsub 00910H 00014H + @@LCODE m_fadd 00924H 0013AH + @@LCODE m_fdiv 00A5EH 0012FH + @@LCODE m_frev 00B8DH 00004H + @@LCODE m_ftols 00B91H 00078H + @@LCODE m_ftolu 00C09H 0002BH + @@LCODE m_lstof 00C34H 00016H + @@LCODE m_lutof 00C4AH 0004DH + FSL_CODE 00C97H 00322H CSEG + FSL_CODE fsl_block_cmd + 00C97H 0002BH + FSL_CODE fsl_block_check + 00CC2H 00013H + FSL_CODE fsl_common + 00CD5H 0014FH + FSL_CODE fsl_reset + 00E24H 00001H + FSL_CODE fsl_si_ibf + 00E25H 00064H + FSL_CODE fsl_phySwap + 00E89H 0004DH + FSL_CODE fsl_si_common + 00ED6H 00061H + FSL_CODE fsl_swap 00F37H 00030H + FSL_CODE fsl_write + 00F67H 00052H +* gap * 00FB9H 0003DH + MGC_LOAD 00FF6H 0000AH CSEG AT + MGC_LOAD magic 00FF6H 0000AH + + MEMORY=ROM + BASE ADDRESS=02000H SIZE=03000H + OUTPUT INPUT INPUT BASE SIZE + SEGMENT SEGMENT MODULE ADDRESS + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL @cstart 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL pm 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL i2c_ctr 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL i2c_mcu 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL i2c_twl 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL ini_VECT 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL led 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL rtc 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL vreg_ctr 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL vreg_twl 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL adc 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL renge 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL accero 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL sw 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL task_debug + 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL task_misc + 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL task_sys 02000H 00000H + @@CNSTL 02000H 00000H CSEG PAGE64KP + @@CNSTL pedo_alg_thre_det2 + 02000H 00000H + @@CNSTL 02000H 0000AH CSEG PAGE64KP + @@CNSTL @bcdtob 02000H 0000AH + @@CNSTL 0200AH 00010H CSEG PAGE64KP + @@CNSTL @bbcd 0200AH 00010H + @@CNSTL 0201AH 000CEH CSEG PAGE64KP + @@CNSTL m_fcom5 0201AH 000CEH + @@CNSTL 020E8H 00014H CSEG PAGE64KP + @@CNSTL m_fsqrtx 020E8H 00014H + @@R_INIS 020FCH 00000H CSEG UNIT64KP + @@R_INIS @cstart 020FCH 00000H + @@R_INIS loader 020FCH 00000H + @@R_INIS pm 020FCH 00000H + @@R_INIS i2c_ctr 020FCH 00000H + @@R_INIS main 020FCH 00000H + @@R_INIS magic 020FCH 00000H + @@R_INIS WDT 020FCH 00000H + @@R_INIS i2c_mcu 020FCH 00000H + @@R_INIS i2c_twl 020FCH 00000H + @@R_INIS ini_VECT 020FCH 00000H + @@R_INIS led 020FCH 00000H + @@R_INIS rtc 020FCH 00000H + @@R_INIS vreg_ctr 020FCH 00000H + @@R_INIS vreg_twl 020FCH 00000H + @@R_INIS adc 020FCH 00000H + @@R_INIS renge 020FCH 00000H + @@R_INIS accero 020FCH 00000H + @@R_INIS self_flash + 020FCH 00000H + @@R_INIS reboot 020FCH 00000H + @@R_INIS sw 020FCH 00000H + @@R_INIS task_debug + 020FCH 00000H + @@R_INIS task_misc + 020FCH 00000H + @@R_INIS task_sys 020FCH 00000H + @@R_INIS pedo_alg_thre_det2 + 020FCH 00000H + @@R_INIS @rom 020FCH 00000H + @@CALT 020FCH 00000H CSEG + @@CALT @cstart 020FCH 00000H + @@CALT loader 020FCH 00000H + @@CALT pm 020FCH 00000H + @@CALT i2c_ctr 020FCH 00000H + @@CALT main 020FCH 00000H + @@CALT magic 020FCH 00000H + @@CALT WDT 020FCH 00000H + @@CALT i2c_mcu 020FCH 00000H + @@CALT i2c_twl 020FCH 00000H + @@CALT ini_VECT 020FCH 00000H + @@CALT led 020FCH 00000H + @@CALT rtc 020FCH 00000H + @@CALT vreg_ctr 020FCH 00000H + @@CALT vreg_twl 020FCH 00000H + @@CALT adc 020FCH 00000H + @@CALT renge 020FCH 00000H + @@CALT accero 020FCH 00000H + @@CALT self_flash + 020FCH 00000H + @@CALT reboot 020FCH 00000H + @@CALT sw 020FCH 00000H + @@CALT task_debug + 020FCH 00000H + @@CALT task_misc + 020FCH 00000H + @@CALT task_sys 020FCH 00000H + @@CALT pedo_alg_thre_det2 + 020FCH 00000H + @@RLINIT 020FCH 00000H CSEG UNIT64KP + @@RLINIT loader 020FCH 00000H + @@RLINIT pm 020FCH 00000H + @@RLINIT i2c_ctr 020FCH 00000H + @@RLINIT main 020FCH 00000H + @@RLINIT magic 020FCH 00000H + @@RLINIT WDT 020FCH 00000H + @@RLINIT i2c_mcu 020FCH 00000H + @@RLINIT i2c_twl 020FCH 00000H + @@RLINIT ini_VECT 020FCH 00000H + @@RLINIT led 020FCH 00000H + @@RLINIT rtc 020FCH 00000H + @@RLINIT vreg_ctr 020FCH 00000H + @@RLINIT vreg_twl 020FCH 00000H + @@RLINIT adc 020FCH 00000H + @@RLINIT renge 020FCH 00000H + @@RLINIT accero 020FCH 00000H + @@RLINIT self_flash + 020FCH 00000H + @@RLINIT reboot 020FCH 00000H + @@RLINIT sw 020FCH 00000H + @@RLINIT task_debug + 020FCH 00000H + @@RLINIT task_misc + 020FCH 00000H + @@RLINIT task_sys 020FCH 00000H + @@RLINIT pedo_alg_thre_det2 + 020FCH 00000H + @@RLINIT @rom 020FCH 00000H + @@CODEL 020FCH 00000H CSEG + @@CODEL pm 020FCH 00000H + @@CODEL i2c_ctr 020FCH 00000H + @@CODEL magic 020FCH 00000H + @@CODEL i2c_mcu 020FCH 00000H + @@CODEL i2c_twl 020FCH 00000H + @@CODEL ini_VECT 020FCH 00000H + @@CODEL led 020FCH 00000H + @@CODEL rtc 020FCH 00000H + @@CODEL vreg_ctr 020FCH 00000H + @@CODEL vreg_twl 020FCH 00000H + @@CODEL adc 020FCH 00000H + @@CODEL renge 020FCH 00000H + @@CODEL accero 020FCH 00000H + @@CODEL sw 020FCH 00000H + @@CODEL task_debug + 020FCH 00000H + @@CODEL task_misc + 020FCH 00000H + @@CODEL task_sys 020FCH 00000H + @@CODEL pedo_alg_thre_det2 + 020FCH 00000H +* gap * 020FCH 00004H + MGC_MIMI 02100H 0000AH CSEG AT + MGC_MIMI magic 02100H 0000AH + @@CNST 0210AH 00528H CSEG + @@CNST @cstart 0210AH 00000H + @@CNST loader 0210AH 00000H + @@CNST pm 0210AH 001F8H + @@CNST i2c_ctr 02302H 00030H + @@CNST main 02332H 00030H + @@CNST magic 02362H 00000H + @@CNST WDT 02362H 00000H + @@CNST i2c_mcu 02362H 00030H + @@CNST i2c_twl 02392H 00030H + @@CNST ini_VECT 023C2H 00000H + @@CNST led 023C2H 00034H + @@CNST rtc 023F6H 00030H + @@CNST vreg_ctr 02426H 00030H + @@CNST vreg_twl 02456H 00030H + @@CNST adc 02486H 00070H + @@CNST renge 024F6H 00000H + @@CNST accero 024F6H 00030H + @@CNST self_flash + 02526H 00002H + @@CNST reboot 02528H 00000H + @@CNST sw 02528H 00030H + @@CNST task_debug + 02558H 00030H + @@CNST task_misc + 02588H 00030H + @@CNST task_sys 025B8H 00030H + @@CNST pedo_alg_thre_det2 + 025E8H 0004AH + ROM_CODE 02632H 0223FH CSEG + ROM_CODE pm 02632H 0068DH + ROM_CODE i2c_ctr 02CBFH 00060H + ROM_CODE i2c_mcu 02D1FH 002DBH + ROM_CODE i2c_twl 02FFAH 0005EH + ROM_CODE led 03058H 003CFH + ROM_CODE rtc 03427H 000E0H + ROM_CODE vreg_ctr 03507H 003B2H + ROM_CODE vreg_twl 038B9H 00132H + ROM_CODE adc 039EBH 001E7H + ROM_CODE renge 03BD2H 00221H + ROM_CODE accero 03DF3H 0012AH + ROM_CODE sw 03F1DH 00167H + ROM_CODE task_debug + 04084H 0003EH + ROM_CODE task_misc + 040C2H 001ACH + ROM_CODE task_sys 0426EH 0020BH + ROM_CODE pedo_alg_thre_det2 + 04479H 003F8H + @@BASE 04871H 0055DH CSEG BASE + @@BASE loader 04871H 00006H + @@BASE pm 04877H 0003FH + @@BASE i2c_ctr 048B6H 00163H + @@BASE main 04A19H 00000H + @@BASE magic 04A19H 00000H + @@BASE WDT 04A19H 00000H + @@BASE i2c_mcu 04A19H 000D9H + @@BASE i2c_twl 04AF2H 00117H + @@BASE ini_VECT 04C09H 0007DH + @@BASE led 04C86H 00000H + @@BASE rtc 04C86H 00043H + @@BASE vreg_ctr 04CC9H 00000H + @@BASE vreg_twl 04CC9H 00000H + @@BASE adc 04CC9H 000B5H + @@BASE renge 04D7EH 00000H + @@BASE accero 04D7EH 00050H + @@BASE self_flash + 04DCEH 00000H + @@BASE reboot 04DCEH 00000H + @@BASE sw 04DCEH 00000H + @@BASE task_debug + 04DCEH 00000H + @@BASE task_misc + 04DCEH 00000H + @@BASE task_sys 04DCEH 00000H + @@BASE pedo_alg_thre_det2 + 04DCEH 00000H + @@R_INIT 04DCEH 00046H CSEG UNIT64KP + @@R_INIT @cstart 04DCEH 00000H + @@R_INIT loader 04DCEH 00000H + @@R_INIT pm 04DCEH 00004H + @@R_INIT i2c_ctr 04DD2H 00002H + @@R_INIT main 04DD4H 00000H + @@R_INIT magic 04DD4H 00000H + @@R_INIT WDT 04DD4H 00000H + @@R_INIT i2c_mcu 04DD4H 00000H + @@R_INIT i2c_twl 04DD4H 00000H + @@R_INIT ini_VECT 04DD4H 00000H + @@R_INIT led 04DD4H 00002H + @@R_INIT rtc 04DD6H 00000H + @@R_INIT vreg_ctr 04DD6H 00000H + @@R_INIT vreg_twl 04DD6H 00016H + @@R_INIT adc 04DECH 00002H + @@R_INIT renge 04DEEH 00016H + @@R_INIT accero 04E04H 00000H + @@R_INIT self_flash + 04E04H 00000H + @@R_INIT reboot 04E04H 00000H + @@R_INIT sw 04E04H 00002H + @@R_INIT task_debug + 04E06H 00002H + @@R_INIT task_misc + 04E08H 00002H + @@R_INIT task_sys 04E0AH 00002H + @@R_INIT pedo_alg_thre_det2 + 04E0CH 00008H + @@R_INIT @rom 04E14H 00000H + @@LCODEL 04E14H 0019DH CSEG + @@LCODEL abs 04E14H 00008H + @@LCODEL m_sqrt 04E1CH 00013H + @@LCODEL m_fcom4 04E2FH 00041H + @@LCODEL m_fsqrtx 04E70H 000C2H + @@LCODEL m_fcom3 04F32H 0007FH +* gap * 04FB1H 00045H + MGC_TAIL 04FF6H 0000AH CSEG AT + MGC_TAIL magic 04FF6H 0000AH + + MEMORY=RAM + BASE ADDRESS=FF900H SIZE=00500H + OUTPUT INPUT INPUT BASE SIZE + SEGMENT SEGMENT MODULE ADDRESS + @@DATA FF900H 00378H DSEG BASEP + @@DATA @cstart FF900H 00002H + @@DATA loader FF902H 00000H + @@DATA pm FF902H 00010H + @@DATA i2c_ctr FF912H 00004H + @@DATA main FF916H 00204H + @@DATA magic FFB1AH 00000H + @@DATA WDT FFB1AH 00000H + @@DATA i2c_mcu FFB1AH 00008H + @@DATA i2c_twl FFB22H 00004H + @@DATA ini_VECT FFB26H 00000H + @@DATA led FFB26H 00012H + @@DATA rtc FFB38H 00008H + @@DATA vreg_ctr FFB40H 00062H + @@DATA vreg_twl FFBA2H 00010H + @@DATA adc FFBB2H 00014H + @@DATA renge FFBC6H 00012H + @@DATA accero FFBD8H 00000H + @@DATA self_flash + FFBD8H 00000H + @@DATA reboot FFBD8H 00000H + @@DATA sw FFBD8H 00004H + @@DATA task_debug + FFBDCH 00002H + @@DATA task_misc + FFBDEH 00002H + @@DATA task_sys FFBE0H 00002H + @@DATA pedo_alg_thre_det2 + FFBE2H 00096H + @@DATA @rom FFC78H 00000H + @@INIT FFC78H 00046H DSEG BASEP + @@INIT @cstart FFC78H 00000H + @@INIT loader FFC78H 00000H + @@INIT pm FFC78H 00004H + @@INIT i2c_ctr FFC7CH 00002H + @@INIT main FFC7EH 00000H + @@INIT magic FFC7EH 00000H + @@INIT WDT FFC7EH 00000H + @@INIT i2c_mcu FFC7EH 00000H + @@INIT i2c_twl FFC7EH 00000H + @@INIT ini_VECT FFC7EH 00000H + @@INIT led FFC7EH 00002H + @@INIT rtc FFC80H 00000H + @@INIT vreg_ctr FFC80H 00000H + @@INIT vreg_twl FFC80H 00016H + @@INIT adc FFC96H 00002H + @@INIT renge FFC98H 00016H + @@INIT accero FFCAEH 00000H + @@INIT self_flash + FFCAEH 00000H + @@INIT reboot FFCAEH 00000H + @@INIT sw FFCAEH 00002H + @@INIT task_debug + FFCB0H 00002H + @@INIT task_misc + FFCB2H 00002H + @@INIT task_sys FFCB4H 00002H + @@INIT pedo_alg_thre_det2 + FFCB6H 00008H + @@INIT @rom FFCBEH 00000H + @@INIS FFCBEH 00000H DSEG UNITP + @@INIS @cstart FFCBEH 00000H + @@INIS loader FFCBEH 00000H + @@INIS pm FFCBEH 00000H + @@INIS i2c_ctr FFCBEH 00000H + @@INIS main FFCBEH 00000H + @@INIS magic FFCBEH 00000H + @@INIS WDT FFCBEH 00000H + @@INIS i2c_mcu FFCBEH 00000H + @@INIS i2c_twl FFCBEH 00000H + @@INIS ini_VECT FFCBEH 00000H + @@INIS led FFCBEH 00000H + @@INIS rtc FFCBEH 00000H + @@INIS vreg_ctr FFCBEH 00000H + @@INIS vreg_twl FFCBEH 00000H + @@INIS adc FFCBEH 00000H + @@INIS renge FFCBEH 00000H + @@INIS accero FFCBEH 00000H + @@INIS self_flash + FFCBEH 00000H + @@INIS reboot FFCBEH 00000H + @@INIS sw FFCBEH 00000H + @@INIS task_debug + FFCBEH 00000H + @@INIS task_misc + FFCBEH 00000H + @@INIS task_sys FFCBEH 00000H + @@INIS pedo_alg_thre_det2 + FFCBEH 00000H + @@INIS @rom FFCBEH 00000H + @@DATS FFCBEH 00000H DSEG UNITP + @@DATS @cstart FFCBEH 00000H + @@DATS loader FFCBEH 00000H + @@DATS pm FFCBEH 00000H + @@DATS i2c_ctr FFCBEH 00000H + @@DATS main FFCBEH 00000H + @@DATS magic FFCBEH 00000H + @@DATS WDT FFCBEH 00000H + @@DATS i2c_mcu FFCBEH 00000H + @@DATS i2c_twl FFCBEH 00000H + @@DATS ini_VECT FFCBEH 00000H + @@DATS led FFCBEH 00000H + @@DATS rtc FFCBEH 00000H + @@DATS vreg_ctr FFCBEH 00000H + @@DATS vreg_twl FFCBEH 00000H + @@DATS adc FFCBEH 00000H + @@DATS renge FFCBEH 00000H + @@DATS accero FFCBEH 00000H + @@DATS self_flash + FFCBEH 00000H + @@DATS reboot FFCBEH 00000H + @@DATS sw FFCBEH 00000H + @@DATS task_debug + FFCBEH 00000H + @@DATS task_misc + FFCBEH 00000H + @@DATS task_sys FFCBEH 00000H + @@DATS pedo_alg_thre_det2 + FFCBEH 00000H + @@DATS @rom FFCBEH 00000H + FSL_DATA FFCBEH 00010H DSEG UNITP + FSL_DATA fsl_common + FFCBEH 00010H + @@INITL FFCCEH 00000H DSEG UNIT64KP + @@INITL loader FFCCEH 00000H + @@INITL pm FFCCEH 00000H + @@INITL i2c_ctr FFCCEH 00000H + @@INITL main FFCCEH 00000H + @@INITL magic FFCCEH 00000H + @@INITL WDT FFCCEH 00000H + @@INITL i2c_mcu FFCCEH 00000H + @@INITL i2c_twl FFCCEH 00000H + @@INITL ini_VECT FFCCEH 00000H + @@INITL led FFCCEH 00000H + @@INITL rtc FFCCEH 00000H + @@INITL vreg_ctr FFCCEH 00000H + @@INITL vreg_twl FFCCEH 00000H + @@INITL adc FFCCEH 00000H + @@INITL renge FFCCEH 00000H + @@INITL accero FFCCEH 00000H + @@INITL self_flash + FFCCEH 00000H + @@INITL reboot FFCCEH 00000H + @@INITL sw FFCCEH 00000H + @@INITL task_debug + FFCCEH 00000H + @@INITL task_misc + FFCCEH 00000H + @@INITL task_sys FFCCEH 00000H + @@INITL pedo_alg_thre_det2 + FFCCEH 00000H + @@INITL @rom FFCCEH 00000H + @@DATAL FFCCEH 00000H DSEG UNIT64KP + @@DATAL loader FFCCEH 00000H + @@DATAL pm FFCCEH 00000H + @@DATAL i2c_ctr FFCCEH 00000H + @@DATAL main FFCCEH 00000H + @@DATAL magic FFCCEH 00000H + @@DATAL WDT FFCCEH 00000H + @@DATAL i2c_mcu FFCCEH 00000H + @@DATAL i2c_twl FFCCEH 00000H + @@DATAL ini_VECT FFCCEH 00000H + @@DATAL led FFCCEH 00000H + @@DATAL rtc FFCCEH 00000H + @@DATAL vreg_ctr FFCCEH 00000H + @@DATAL vreg_twl FFCCEH 00000H + @@DATAL adc FFCCEH 00000H + @@DATAL renge FFCCEH 00000H + @@DATAL accero FFCCEH 00000H + @@DATAL self_flash + FFCCEH 00000H + @@DATAL reboot FFCCEH 00000H + @@DATAL sw FFCCEH 00000H + @@DATAL task_debug + FFCCEH 00000H + @@DATAL task_misc + FFCCEH 00000H + @@DATAL task_sys FFCCEH 00000H + @@DATAL pedo_alg_thre_det2 + FFCCEH 00000H + @@DATAL @rom FFCCEH 00000H +* gap * FFCCEH 00132H + + MEMORY=RAM2 + BASE ADDRESS=FFE20H SIZE=000C0H + OUTPUT INPUT INPUT BASE SIZE + SEGMENT SEGMENT MODULE ADDRESS + @@BITS FFE20H 00003H BSEG + @@BITS @cstart FFE20H.0 00000H.0 + @@BITS loader FFE20H.0 00000H.0 + @@BITS pm FFE20H.0 00000H.1 + @@BITS i2c_ctr FFE20H.1 00000H.0 + @@BITS main FFE20H.1 00000H.1 + @@BITS magic FFE20H.2 00000H.0 + @@BITS WDT FFE20H.2 00000H.0 + @@BITS i2c_mcu FFE20H.2 00000H.3 + @@BITS i2c_twl FFE20H.5 00000H.0 + @@BITS ini_VECT FFE20H.5 00000H.0 + @@BITS led FFE20H.5 00000H.0 + @@BITS rtc FFE20H.5 00000H.3 + @@BITS vreg_ctr FFE21H.0 00000H.1 + @@BITS vreg_twl FFE21H.1 00000H.0 + @@BITS adc FFE21H.1 00000H.1 + @@BITS renge FFE21H.2 00000H.3 + @@BITS accero FFE21H.5 00000H.0 + @@BITS self_flash + FFE21H.5 00000H.0 + @@BITS reboot FFE21H.5 00000H.0 + @@BITS sw FFE21H.5 00000H.4 + @@BITS task_debug + FFE22H.1 00000H.0 + @@BITS task_misc + FFE22H.1 00000H.0 + @@BITS task_sys FFE22H.1 00000H.0 + @@BITS pedo_alg_thre_det2 + FFE22H.1 00000H.1 +* gap * FFE23H 000B1H + @@SEGREG FFED4H 00004H DSEG AT + @@SEGREG @SEGREG FFED4H 00004H + @@RTARG0 FFED8H 00008H DSEG AT + @@RTARG0 @RTARG0 FFED8H 00008H + + + Target chip : uPD79F0104 + Device file : E1.00b + \ No newline at end of file diff --git a/branches/0.10(X3)/bsr_mcu.dr b/branches/0.10(X3)/bsr_mcu.dr new file mode 100644 index 0000000..12fcfd0 --- /dev/null +++ b/branches/0.10(X3)/bsr_mcu.dr @@ -0,0 +1,52 @@ +;;; 領域の定義 +;32kB = 0x7FFF +MEMORY BCL0: (00000H, 01000H ) +;MEMORY BCL1: (01000H, 01000H ) ; バックアップ領域 +MEMORY ROM : (02000H, 03000H ) +;MEMORY ROM_BKUP:(05000H, 03000H ) ; バックアップ領域 +;MEMORY OCD :(0FC00H, 00400H ) ; OCDが使っているらしい + + +;;; セグメントの割当先設定 +; ブートブロック0に割り当てる +MERGE LDR_CODE: =BCL0 +MERGE LDR_CODL: =BCL0 +;MERGE @@LCODE : AT( 0E00H ) =BCL0 ; スタートアップルーチン +MERGE @@LCODE : =BCL0 ; スタートアップルーチン + +;MERGE LDR_RINT:=BCL0 +;MERGE LDR_CNST:=BCL0 +MERGE LDR_CNSL:=BCL0 + + +; 通常領域にあてる物達 +MERGE ROM_CODE:=ROM +;MERGE ROM_CNST:=ROM + + +; ちょっと、困るんですが、こうしないと初期値がセットされない +MERGE @@CNST: =ROM +MERGE @@R_INIT: =ROM + + + +; 謹製フラッシュライブラリ +; MERGE FSL_CODE:=FSL +MERGE FSL_CODE:=BCL0 + + +; マジックナンバー +;; magic.cの中で指定 + + +;--- RAM領域 ------------------------------------------------------- +; +; RAM1,RAM2領域はユーザープログラムで使用しても良いですが、セルフプログラム時は +; セルフプログラムのライブラリが使用するため、値は破壊されます。 +; +memory RAM2 : (0FFE20H, 00C0H) ; セルフプログラム時、使用禁止領域 +;memory SLF_RAM : (0FFE00H, 0020H) ; Slef Program予約領域[使用禁止] +memory RAM : (0FF900H, 0500H) ; ユーザーＲＡＭ領域 +;memory SLF_RAM : (0FF900H, 0020H) ; Slef Program予約領域[使用禁止] + + diff --git a/branches/0.10(X3)/bsr_system.h b/branches/0.10(X3)/bsr_system.h new file mode 100644 index 0000000..9332094 --- /dev/null +++ b/branches/0.10(X3)/bsr_system.h @@ -0,0 +1,56 @@ +#ifndef __bsr_system__ +#define __bsr_system__ + +// イベントループのステート +enum pwr_state_ +{ + OFF_TRIG = 0, + OFF, + ON_TRIG, + ON, + SLEEP_TRIG, + SLEEP, +// WAKE, + BT_CHARGE, +}; + +enum poweron_reason_ +{ + NONE = 0, + PWSW, + RTC_ALARM, +}; + + +enum model_ +{ + MODEL_JIKKI = 0, + MODEL_TS_BOARD, + MODEL_SHIROBAKO, + MODEL_RESERVED1, + MODEL_RESERVED2, + MODEL_RESERVED3, +}; + + + +// タスクシステムの状態情報など +typedef struct +{ + enum pwr_state_ pwr_state; + enum poweron_reason_ poweron_reason; + unsigned char dipsw0:1; + unsigned char dipsw1:1; + unsigned char dipsw2:1; + unsigned char reboot:1; + enum model_ model; +} +system_status_; + + + +extern system_status_ system_status; + + + +#endif diff --git a/branches/0.10(X3)/config.h b/branches/0.10(X3)/config.h new file mode 100644 index 0000000..c918dbd --- /dev/null +++ b/branches/0.10(X3)/config.h @@ -0,0 +1,76 @@ +#ifndef __config__ +#define __config__ + +#define _debug_ +//#define _debug_led_ + + +#define MCU_VER_MAJOR 0x00 +#define MCU_VER_MINOR 0x10 + +#define _OVERCLOCK_ + +//#define PM_CCIC_TIM + +// 古い(C)電源ボード +//#define _PM_BUG_ + +//#define _PARRADIUM_ +//#define _MODEL_TEG2_ + // ↑TEG2 CPU ＋ Type-T +//#define _MODEL_WM0_ +//#define _MODEL_WM0_TEG2_CTRC_ + +//#define _MODEL_TS0_ + // ↑TEG2 CPU ＋ Type-C + +#define _MODEL_CTR_TS_ + // ↑FINAL SoC ＋ Type-C + +//#define _MODEL_CTR_JIKKI_ + + +//#define _SW_HOME_ENABLE_ + +// ---------------------------------- // +#ifdef _MODEL_CTR_TS_ +#ifdef _MODEL_CTR_JIKKI_ +どちらか一方だけセットして下さい。 +#endif +#endif + +#ifdef _MODEL_CTR_TS_ +#define _MODEL_CTR_ +#endif + +#ifdef _MODEL_CTR_JIKKI_ +#define _MODEL_CTR_ +#endif + + +// ---------------------------------- // +#ifdef _MODEL_TEG2_ +#define _PMIC_TWL_ +#define _MCU_KE3_ +#endif + + +#ifdef _MODEL_WM0_ +#define _PMIC_TWL_ +#define _MCU_BSR_ +#define _SW_HOME_ENABLE_ +#endif + + +#ifdef _MODEL_TS0_ +#define _PMIC_CTR_ +#define _MCU_BSR_ +#endif + +#ifdef _MODEL_CTR_ +#define _PMIC_CTR_ +#define _MCU_BSR_ +#define _SW_HOME_ENABLE_ +#endif + +#endif diff --git a/branches/0.10(X3)/fsl.h b/branches/0.10(X3)/fsl.h new file mode 100644 index 0000000..0e806b5 --- /dev/null +++ b/branches/0.10(X3)/fsl.h @@ -0,0 +1,362 @@ +/*==============================================================================================*/ +/* Project = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash */ +/* Module = fsl.h */ +/* Version = V1.01 */ +/* Date = 28.03.2008 11:45:42 */ +/*==============================================================================================*/ +/* COPYRIGHT */ +/*==============================================================================================*/ +/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH, */ +/* a company of the NEC Electronics Corporation */ +/*==============================================================================================*/ +/* Purpose: */ +/* constant, type and function prototype definitions used by the FSL */ +/* */ +/*==============================================================================================*/ +/* */ +/* Warranty Disclaimer */ +/* */ +/* Because the Product(s) is licensed free of charge, there is no warranty of any kind */ +/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied, */ +/* including but not limited to those for non-infringement of intellectual property, */ +/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */ +/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/ +/* */ +/* Each User is solely responsible for determining the appropriateness of using the Product(s) */ +/* and assumes all risks associated with its exercise of rights under this Agreement, */ +/* including, but not limited to the risks and costs of program errors, compliance with */ +/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall NEC be liable to the User for any incidental, consequential, indirect, */ +/* or punitive damage (including but not limited to lost profits) regardless of whether */ +/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */ +/* failure of essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. NEC shall not be liable for any services or products provided by third party */ +/* vendors, developers or consultants identified or referred to the User by NEC in connection */ +/* with the Product(s) and/or the Application. */ +/* */ +/*==============================================================================================*/ +/* Environment: PM plus (V6.30) */ +/* RA78K0(V1.20) */ +/* CC78K0(V2.00) */ +/*==============================================================================================*/ + +#ifndef __FSL_H_INCLUDED +#define __FSL_H_INCLUDED + + +/*==============================================================================================*/ +/* FSL type definitions */ +/*==============================================================================================*/ +typedef unsigned char fsl_u08; +typedef unsigned int fsl_u16; +typedef unsigned long int fsl_u32; + + +/*==============================================================================================*/ +/* constant definitions */ +/*==============================================================================================*/ + +/*status code definitions returned by the FSL functions */ +#define FSL_OK 0x00 +#define FSL_ERR_FLMD0 0x01 +#define FSL_ERR_PARAMETER 0x05 +#define FSL_ERR_PROTECTION 0x10 +#define FSL_ERR_ERASE 0x1A +#define FSL_ERR_BLANKCHECK 0x1B +#define FSL_ERR_IVERIFY 0x1B +#define FSL_ERR_WRITE 0x1C +#define FSL_ERR_EEP_IVERIFY 0x1D +#define FSL_ERR_EEP_BLANKCHECK 0x1E +#define FSL_ERR_INTERRUPTION 0x1F + + +/*==============================================================================================*/ +/* global function prototypes */ +/*==============================================================================================*/ + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: initialization of selfprogramming environment */ +/* After initialization: */ +/* - the pointer to the data-buffer is stored */ +/* - all timing data are re-calculated according to the used system clock */ +/* */ +/* CAUTION: */ +/* The FSL_Init(&data_buffer) function is interruptible. Please use the */ +/* FSL_Init_cont(&data_buffer) to recall it as long return status is 0x1F. */ +/* */ +/* Input: data_buffer_pu08 - pointer to a data buffer of N...256 bytes */ +/* (used for data exchange between firmware and application) */ +/* Output: - */ +/* Returned: u08, status_code */ +/* = 0x00(FSL_OK), normal and means initialization OK */ +/* = 0x1F(FSL_ERR_INTERRUPTION), initialization interrupted by user interrupt*/ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_Init( fsl_u08 * data_buffer_pu08 ); +extern fsl_u08 FSL_Init_cont( fsl_u08 * data_buffer_pu08 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: checks the voltage level (high or low) at FLMD0 pin */ +/* Input: - */ +/* Output: - */ +/* Returned: fsl_u08, status_code */ +/* = 0x00(FSL_OK), normal and means FLMD0=HIGH */ +/* = 0x01(FSL_ERR_FLMD0), error, FLMD0=LOW */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_ModeCheck( void ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: checks if specified block is blank */ +/* Input: block_u16 - block number has to be checked */ +/* Output: - */ +/* Returned: fsl_u08, status_code */ +/* = 0x00(FSL_OK), normal and means "block is blank" */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x1B(FSL_ERR_BLANKCHECK), blank-check error, means "block not blank" */ +/* = 0x1F(FSL_ERR_INTERRUPTION), blank-check interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_BlankCheck( fsl_u16 block_u16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: erase specified block */ +/* Input: block_u16 - block number has to be erase */ +/* Output: - */ +/* Returned: fsl_u08, status_code */ +/* = 0x00(FSL_OK), normal and means "block erased successfully" */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), tried to erase protected area */ +/* = 0x1A(FSL_ERR_ERASE), erase error, retry up to max. 255 times */ +/* = 0x1F(FSL_ERR_INTERRUPTION), erasing interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_Erase( fsl_u16 block_u16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: performs internal verify on specified block */ +/* Input: block_u16 - block number has to be verified */ +/* Output: - */ +/* Returned: fsl_u08, status_code */ +/* = 0x00(FSL_OK), normal and means "block is verified" */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x1B(FSL_ERR_IVERIFY), internal verify error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), verify interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_IVerify( fsl_u16 block_u16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: writes N words from the data buffer into flash */ +/* Input: s_address_u32 - starting flash address the data has to be written */ +/* See Condition 2) please. */ +/* my_wordcount_u08 - number of words (4 bytes) has to be written */ +/* Output: - */ +/* Condition: 1) (s_address_u32 MOD 4 == 0) */ +/* 2) most significant byte (MSB) of s_address_u32 has to be 0x00. */ +/* Means: 0x00abcdef 24 bit flash address allowed */ +/* 3) (word_count_u08 <= sizeof(data buffer)) NOT CHECKED BY LIBRARY !!!!! */ +/* Changed: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), protection error */ +/* = 0x1C(FSL_ERR_WRITE), write error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_Write( fsl_u32 s_address_u32, fsl_u08 word_count_u08 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: writes N words from the data buffer into flash */ +/* Before "writing" a N-word blankcheck is performed. */ +/* After "writing" a N-Word internal verify is performed. */ +/* Input: s_address_u32 - starting destination address has to be written */ +/* my_wordcount_u08 - number of words (4 bytes) has to be written */ +/* Output: - */ +/* Condition: 1) (s_address_u32 MOD 4 == 0) */ +/* 2) (word_count_u08 <= sizeof(data buffer)) NOT CHECKED BY FIRMWARE !!!!! */ +/* Changed: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), protection error */ +/* = 0x1C(FSL_ERR_WRITE), write error */ +/* = 0x1D(FSL_ERR_EEP_IVERIFY), verify error */ +/* = 0x1E(FSL_ERR_EEP_BLANKCHECK), blankcheck error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_EEPROMWrite( fsl_u32 s_address_u32, + fsl_u08 word_count_u08 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: reads the security information */ +/* Input: destination_pu16 - destination address of the security info */ +/* The format of the security info is: "unsigned short int" */ +/* */ +/* Format of the security info: */ +/* bit_0 = 0 -> chip erase command disabled, otherwise enabled */ +/* bit_1 = 0 -> block erase command disabled, otherwise enabled */ +/* bit_2 = 0 -> write command disabled, otherwise enabled */ +/* bit_4 = 0 -> boot-area re-programming disabled, otherwise enabled */ +/* bit_8...bit_15 = 03H -> last block of the boot-area */ +/* other bits = 1 */ +/* Output: - */ +/* Changed: content of the data_buffer */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_GetSecurityFlags( fsl_u16 * destination_pu16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: read the boot flag i */ +/* Input: destination_pu08 - destination address of the bootflag info */ +/* The format of the boot-flag info is: "unsigned char" */ +/* The value of the boot info is 0x00 for cluster 0 and 0x01 for cluster 1. */ +/* Output: - */ +/* Changed: content of the data_buffer */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_GetActiveBootCluster( fsl_u08 * destination_pu08 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: puts the last address of the specified block into *destination_pu32 */ +/* Input: *destination_pu32 - destination where the last-block-address */ +/* should be stored */ +/* block_u16 - block number of the last address is needed */ +/* Changed: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_GetBlockEndAddr( fsl_u32 * destination_pu32, + fsl_u16 block_u16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: puts the information about the protected flash area into the function parameter */ +/* Input: *start_block_pu16 - destination where the FSW start block should be stored */ +/* *end_block_pu16 - destination where the FSW end block should be stored */ +/* Changed: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_GetFlashShieldWindow( fsl_u16 * start_block_pu16, + fsl_u16 * end_block_pu16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: defines a new Flash-Shield-Window area inside the flash memory */ +/* Input: start_block_u16 - starting block of the Flash-Shield-Window (FSW) */ +/* end_block_u16 - ending block of the flash-Shield-Window (FSW) */ +/* Changed: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), protection error */ +/* = 0x1A(FSL_ERR_ERASE), erase error */ +/* = 0x1B(FSL_ERR_IVERIFY), internal verify error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_SetFlashShieldWindow( fsl_u16 start_block_u16, + fsl_u16 end_block_u16 ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: Swapping of bootcluster 0 and 1 */ +/* */ +/* CAUTION !!!! */ +/* After this function the boot cluster are immediately swapped */ +/* Input: - */ +/* Output: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), protection error */ +/* = 0x1A(FSL_ERR_ERASE), erase error */ +/* = 0x1B(FSL_ERR_IVERIFY), internal verify error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_SwapBootCluster( void ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL command function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: sets specified security flag by dedicated command-function. */ +/* */ +/* There are following security levels: */ +/* a) chip-erase protection (cannot be reset by programmer !!!) */ +/* b) block-erase protection (can be reset by chip-erase on programmer) */ +/* c) write protection (can be reset by chip-erase on programmer) */ +/* d) boot-cluster protection (cannot be reset by programmer !!!) */ +/* */ +/* CAUTION !!!! */ +/* Each security flag can be written by the application only once */ +/* */ +/* Input: - */ +/* Output: - */ +/* Returned: fsl_u08, status code */ +/* = 0x00(FSL_OK), normal */ +/* = 0x05(FSL_ERR_PARAMETER), parameter error */ +/* = 0x10(FSL_ERR_PROTECTION), protection error */ +/* = 0x1A(FSL_ERR_ERASE), erase error */ +/* = 0x1B(FSL_ERR_IVERIFY), internal verify error */ +/* = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt */ +/*----------------------------------------------------------------------------------------------*/ +extern fsl_u08 FSL_SetChipEraseProtectFlag( void ); +extern fsl_u08 FSL_SetBlockEraseProtectFlag( void ); +extern fsl_u08 FSL_SetWriteProtectFlag( void ); +extern fsl_u08 FSL_SetBootClusterProtectFlag( void ); + + +/*----------------------------------------------------------------------------------------------*/ +/* Block type: FSL function */ +/*----------------------------------------------------------------------------------------------*/ +/* Purpose: defines the firmware operation method after interrupt service (ISR) execution. */ +/* Input: mode_u08 = 0x00, after RETI the firmware is continuing the interrupted command.*/ +/* = other, after RETI the firmware is interrupted with status 0x1F. */ +/* Changed: - */ +/* Returned: - */ +/*----------------------------------------------------------------------------------------------*/ +extern void FSL_SetInterruptMode( fsl_u08 mode_u08 ); + +#endif diff --git a/branches/0.10(X3)/fsl_user.h b/branches/0.10(X3)/fsl_user.h new file mode 100644 index 0000000..823eb8d --- /dev/null +++ b/branches/0.10(X3)/fsl_user.h @@ -0,0 +1,108 @@ +/*==============================================================================================*/ +/* Project = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash */ +/* Module = fsl_user.h */ +/* Version = V1.01 */ +/* Date = 28.03.2008 11:45:55 */ +/*==============================================================================================*/ +/* COPYRIGHT */ +/*==============================================================================================*/ +/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH, */ +/* a company of the NEC Electronics Corporation */ +/*==============================================================================================*/ +/* Purpose: */ +/* user configurable constant/macros of the selfprogramming library */ +/* */ +/*==============================================================================================*/ +/* */ +/* Warranty Disclaimer */ +/* */ +/* Because the Product(s) is licensed free of charge, there is no warranty of any kind */ +/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied, */ +/* including but not limited to those for non-infringement of intellectual property, */ +/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */ +/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/ +/* */ +/* Each User is solely responsible for determining the appropriateness of using the Product(s) */ +/* and assumes all risks associated with its exercise of rights under this Agreement, */ +/* including, but not limited to the risks and costs of program errors, compliance with */ +/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall NEC be liable to the User for any incidental, consequential, indirect, */ +/* or punitive damage (including but not limited to lost profits) regardless of whether */ +/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */ +/* failure of essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. NEC shall not be liable for any services or products provided by third party */ +/* vendors, developers or consultants identified or referred to the User by NEC in connection */ +/* with the Product(s) and/or the Application. */ +/* */ +/*==============================================================================================*/ +/* Environment: PM plus (V6.30) */ +/* RA78K0(V1.20) */ +/* CC78K0(V2.00) */ +/*==============================================================================================*/ + + +#ifndef __FSL_USER_H_INCLUDED +#define __FSL_USER_H_INCLUDED + + +/*==============================================================================================*/ +/* constant definitions */ +/*==============================================================================================*/ + + +/* specify the CPU frequency in [Hz], only 2MHz....20MHz allowed */ +#define FSL_SYSTEM_FREQUENCY 4000000 + +/* define whether low-voltage mode is used or not */ +/* #define FSL_LOW_VOLTAGE_MODE */ + +/* size of the common data buffer expressed in [bytes] */ +/* the data buffer is used for data-exchange between the firmware and the selflib. */ +//#define FSL_DATA_BUFFER_SIZE 256 +#define FSL_DATA_BUFFER_SIZE 0 + + +/* customizable interrupt controller configuration during selfprogramming period */ +/* Bit --7-------6-------5-------4-------3-------2-------1-------0---------------------- */ +/* MK0L: PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK */ +/* MK0H: SREMK0 SRMK0* STMK0* DMAMK1 DMAMK0 SREMK3 SRMK3 STMK3 */ +/* MK1L: TMMK03 TMMK02 TMMK01 TMMK00 IICMK0 SREMK1 SRMK1 STMK1* */ +/* MK1H: TMMK04 SREMK2 SRMK2 STMK2* KRMK RTCIMK RTCMK ADMK */ +/* MK2L: PMK10 PMK9 PMK8 PMK7 PMK6 TMMK07 TMMK06 TMMK05 */ +/* MK2H: 1 1 1 1 1 1 1 PMK11 */ +/*------------------------------------------------------------------------------------------ */ +/* */ +/* Examples: */ +/* ========= */ +/*#define FSL_MK0L_MASK 0xF7 -> allow INTP1 interrupt during selfprogramming */ +/*#define FSL_MK0H_MASK 0xEF -> allow DMA1 interrupt during selfprogramming */ +/*#define FSL_MK1L_MASK 0xBF -> allow TM02 interrupt during selfprogramming */ +/*#define FSL_MK1H_MASK 0xFF -> all interrupts disabled during selfprogramming */ +/*#define FSL_MK2L_MASK 0xF7 -> allow INTP6 interrupt during selfprogramming */ +/*#define FSL_MK2H_MASK 0xFF -> all interrupts disabled during selfprogramming */ +/*------------------------------------------------------------------------------------------ */ +#define FSL_MK0L_MASK 0xFF /* all interrupts disabled during selfprogramming */ +#define FSL_MK0H_MASK 0xFF /* all interrupts disabled during selfprogramming */ +#define FSL_MK1L_MASK 0xFF /* all interrupts disabled during selfprogramming */ +#define FSL_MK1H_MASK 0xFF /* all interrupts disabled during selfprogramming */ +#define FSL_MK2L_MASK 0xFF /* all interrupts disabled during selfprogramming */ +#define FSL_MK2H_MASK 0xFF /* all interrupts disabled during selfprogramming */ + + +/* FLMD0 control bit */ +#define FSL_FLMD0_HIGH {BECTL.7 = 1;} +#define FSL_FLMD0_LOW {BECTL.7 = 0;} + + +/*----------------------------------------------------------------------------------------------*/ +/* switch interrupt backu functionality ON/OFF using #define/#undef */ +/*----------------------------------------------------------------------------------------------*/ +/* #define FSL_INT_BACKUP */ +#undef FSL_INT_BACKUP + + +#endif diff --git a/branches/0.10(X3)/hex/bsr_V0.1_090819.hex b/branches/0.10(X3)/hex/bsr_V0.1_090819.hex new file mode 100644 index 0000000..2914c20 --- /dev/null +++ b/branches/0.10(X3)/hex/bsr_V0.1_090819.hex @@ -0,0 +1,4163 @@ +:0400000300000000F9 +:020000020000FC +:02000000D80026 +:020000020000FC +:02000200FFFFFE +:020000020000FC +:04000400FFFFFFFFFC +:020000020000FC +:02000800B62D13 +:020000020000FC +:06000A00FFFFFFFFFFFFF6 +:020000020000FC +:04001000E72BE92BC6 +:020000020000FC +:08001400FFFFFFFFFFFFFFFFEC +:020000020000FC +:02001C00F82CBE +:020000020000FC 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Binary files /dev/null and b/branches/0.10(X3)/hoge.0_10.TS.bin differ diff --git a/branches/0.10(X3)/hoge.0_10_T3.bin b/branches/0.10(X3)/hoge.0_10_T3.bin new file mode 100644 index 0000000..1a5c1b1 Binary files /dev/null and b/branches/0.10(X3)/hoge.0_10_T3.bin differ diff --git a/branches/0.10(X3)/hoge.0_10_T3_CodecRevA.bin b/branches/0.10(X3)/hoge.0_10_T3_CodecRevA.bin new file mode 100644 index 0000000..47f1bee Binary files /dev/null and b/branches/0.10(X3)/hoge.0_10_T3_CodecRevA.bin differ diff --git a/branches/0.10(X3)/hoge.bin b/branches/0.10(X3)/hoge.bin new file mode 100644 index 0000000..5720045 Binary files /dev/null and b/branches/0.10(X3)/hoge.bin differ diff --git a/branches/0.10(X3)/i2c_ctr.c b/branches/0.10(X3)/i2c_ctr.c new file mode 100644 index 0000000..15fde2a --- /dev/null +++ b/branches/0.10(X3)/i2c_ctr.c @@ -0,0 +1,261 @@ +/* ======================================================== + 対SoC 新規チャンネル I2C通信 + 藤田＠開技.nintendo + '09 Apr + ======================================================== */ +#include "incs.h" +#include "accero.h" + +#ifdef _MCU_BSR_ +// #ifdef _MODEL_TS0_ || _MODEL_WM0_ + +// ワーキングモデルはI2Cが逆 +// TEGは回路図でテレコ +#define ACKD ACKD1 +#define ACKE ACKE1 +#define COI COI1 +#define IICAEN IICA1EN +#define IICRSV IICRSV1 +#define IICA IICA1 +#define IICAIF IICAIF1 +#define IICAMK IICAMK1 +#define IICAPR0 IICAPR11 +#define IICAPR1 IICAPR01 +#define IICCTL0 IICCTL10 +#define IICE IICE1 +#define IICF IICF1 +#define IICS IICS1 +#define IICWH IICWH1 +#define IICWL IICWL1 +#define LREL LREL1 +#define SPD SPD1 +#define SPIE SPIE1 +#define STCEN STCEN1 +#define STD STD1 +#define SVA SVA1 +#define WREL WREL1 +#define WTIM WTIM1 +#define TRC TRC1 +#define SMC SMC1 +#define DFC DFC1 + + +#endif + +// ============================================== +extern bit irq_readed; // いずれかのIRQレジスタが読まれた + +u8 iic_burst_state; + + +/* ======================================================== + ======================================================== */ +enum +{ + IIC_IDLE = 0, + IIC_RCV_REG_ADRS, + IIC_TX_OR_RX, + IIC_TX, + IIC_RX +}; + + +// 1バイト送受の度に割り込みが発生するバージョン +__interrupt void int_iic_ctr( ) +{ + static u8 state = IIC_IDLE; + static u8 reg_adrs; + static u8 reg_adrs_internal; + static u8 tx_buf; + u8 rx_buf; + + EI(); + + // 読み出し終了 + if( !ACKD ) // 割り込み要因はNAK（データ送信の最後） + { + state = IIC_IDLE; + SPIE = 0; + LREL = 1; + + // レジスタリードで、割り込みピンをネゲート + // まだ読まれてない割り込みがあれば、再度アサート + if( irq_readed ) + { + IRQ0_neg; + irq_readed = 0; + if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 ) + && ( vreg_ctr[VREG_C_IRQ1] == 0 ) + && ( vreg_ctr[VREG_C_IRQ2] == 0 ) + && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) ) + { + while( !IRQ0 ){;} // 時間稼ぎ不要かも + IRQ0_ast; + } + } + + // 歩数計読み出し終了 + hosu_read_end( ); + rtc_unlock( ); + iic_burst_state = 0; + return; + } + + if( SPD ) // 割り込み要因はストップコンディション + // 通信の最後。↑の !ACKD に来たときは割り込み来ない (SPIE = 0 のため ) + { + state = IIC_IDLE; + SPIE = 0; + // I2C終了時に何かする物 // + rtc_unlock( ); + return; + } + + if( STD ) // 割り込み要因：スタートコンディション + { + if( ( state == IIC_TX ) || ( state == IIC_RX ) + || ( state == IIC_RCV_REG_ADRS ) + ) + { + state = IIC_IDLE; + // no break // + } + } + + switch ( state ) + { + case ( IIC_IDLE ): + // 自局呼び出しに応答。 + // 初期化など + SPIE = 1; + state = IIC_RCV_REG_ADRS; + WREL = 1; // ウェイト解除 + break; + + case ( IIC_RCV_REG_ADRS ): // ２バイト目（レジスタアドレス）受信後に来る + // レジスタアドレス受信 + reg_adrs = IICA; + tx_buf = vreg_ctr_read( reg_adrs ); // データの準備をしておく + if( reg_adrs != VREG_C_INFO ) + { + state = IIC_TX_OR_RX; + } + else + { + state = IIC_IDLE; + } + WREL = 1; + break; + + case ( IIC_TX_OR_RX ): // ↑の次に来る割り込み。STなら送信準備、データが来たら書き込まれ +// if( TRC ){ // 送信方向フラグ で区別するのは、割り込み遅延時に不具合が起こりえる + if( STD ) + { // スタートコンディション検出フラグ + // リードされる + if( COI ) + { // アドレス一致フラグ + state = IIC_TX; + // no break, no return // + } + else + { + // リスタートで違うデバイスが呼ばれた！ + state = IIC_IDLE; // 終了処理 + SPIE = 0; + LREL = 1; // ウェイト解除? + return; + } + } + else + { + state = IIC_RX; // データ1バイト受信の割り込みだった + // no break, no return // + } + + default: // バースト R/W でここが何回も呼ばれることになる + if( state == IIC_TX ) + { // 送信 + IICA = tx_buf; + vreg_ctr_after_read( reg_adrs ); // 読んだらクリアなどの処理 + } + else + { // 受信 + rx_buf = IICA; + vreg_ctr_write( reg_adrs, rx_buf ); + WREL = 1; + } + // + if( ( reg_adrs != VREG_C_ACC_HOSU_HIST ) + && ( reg_adrs != VREG_C_INFO ) ) + { // この二つのレジスタは特殊なアクセス方法をする。アクセスポインタを進めない。 + reg_adrs += 1; + } + + if( state == IIC_TX ) + { // さらにつぎに送るデータの準備だけシテオク。SPが来て使われないかもしれない + tx_buf = vreg_ctr_read( reg_adrs ); + } + break; + } +} + + + +// ======================================================== +void IIC_ctr_Init( void ) +{ + + IICAEN = 1; + + IICE = 0; /* IICA disable */ + + IICAMK = 1; /* INTIICA disable */ + IICAIF = 0; /* clear INTIICA interrupt flag */ + + IICAPR0 = 1; /* set INTIICA high priority */ + IICAPR1 = 0; /* set INTIICA high priority */ + +#ifdef _MODEL_TEG2_ + P6 &= ~0x3; +#else + P20 &= ~0x3; +#endif + + SVA = IIC_C_SLAVEADDRESS; + IICF = 0x01; + + STCEN = 1; // リスタートの許可 + IICRSV = 1; // 通信予約をさせない:スレーブに徹する + + SPIE = 0; // ストップコンディションでの割り込みを禁止 + WTIM = 1; // 自動でACKを返した後clkをLに固定する + ACKE = 1; // ダメCPUは無視して次の通信をはじめるかもしれないんで早くclkを開放しないといけない + + IICWH = 5; + IICWL = 10; // L期間の長さ + + SMC = 1; // 高速モード + DFC = 1; // デジタルフィルタon (@fast mode) + + IICAMK = 0; // 割り込みを許可 + + IICE = 1; + +#ifdef _MODEL_TEG2_ + PM6 &= ~0x3; /* set clock pin for IICA */ +#else + PM20 &= ~0x3; /* set clock pin for IICA */ +#endif +} + + + +// ======================================================== +void IIC_ctr_Stop( void ) +{ + IICE = 0; /* IICA disable */ + IICAEN = 0; +} + + + diff --git a/branches/0.10(X3)/i2c_ctr.h b/branches/0.10(X3)/i2c_ctr.h new file mode 100644 index 0000000..16234ff --- /dev/null +++ b/branches/0.10(X3)/i2c_ctr.h @@ -0,0 +1,210 @@ +#ifndef _MDSERIAL_A_ +#define _MDSERIAL_A_ + + +/* IIC operation enable (IICE0) */ +#define IIC0_OPERATION 0x80 +#define IIC0_OPERATION_DISABLE 0x00 /* stop operation */ +#define IIC0_OPERATION_ENABLE 0x80 /* enable operation */ + +/* Exit from communications (LREL0) */ +#define IIC0_COMMUNICATION 0x40 +#define IIC0_COMMUNICATION_NORMAL 0x00 /* normal operation */ +#define IIC0_COMMUNICATION_EXIT 0x40 /* exit from current communication */ + +/* Wait cancellation (WREL0) */ +#define IIC0_WAITCANCEL 0x20 +#define IIC0_WAIT_NOTCANCEL 0x00 /* do not cancel wait */ +#define IIC0_WAIT_CANCEL 0x20 /* cancel wait */ + +/* Generation of interrupt when stop condition (SPIE0) */ +#define IIC0_STOPINT 0x10 +#define IIC0_STOPINT_DISABLE 0x00 /* disable */ +#define IIC0_STOPINT_ENABLE 0x10 /* enable */ + +/* Wait and interrupt generation (WTIM0) */ +#define IIC0_WAITINT 0x08 +#define IIC0_WAITINT_CLK8FALLING 0x00 /* generate at the eighth clocks falling edge */ +#define IIC0_WAITINT_CLK9FALLING 0x08 /* generated at the ninth clocks falling edge */ + +/* Acknowledgement control (ACKE0) */ +#define IIC0_ACK 0x04 +#define IIC0_ACK_DISABLE 0x00 /* enable acknowledgement */ +#define IIC0_ACK_ENABLE 0x04 /* disable acknowledgement */ + +/* Start condition trigger (STT0) */ +#define IIC0_STARTCONDITION 0x02 +#define IIC0_START_NOTGENERATE 0x00 /* do not generate start condition */ +#define IIC0_START_GENERATE 0x02 /* generate start condition */ + +/* Stop condition trigger (SPT0) */ +#define IIC0_STOPCONDITION 0x01 +#define IIC0_STOP_NOTGENERATE 0x00 /* do not generate stop condition */ +#define IIC0_STOP_GENERATE 0x01 /* generate stop condition */ + +/* + IIC Status Register 0 (IICS0) +*/ +/* Master device status (MSTS0) */ +#define IIC0_MASTERSTATUS 0x80 +#define IIC0_STATUS_NOTMASTER 0x00 /* slave device status or communication standby status */ +#define IIC0_STATUS_MASTER 0x80 /* master device communication status */ + +/* Detection of arbitration loss (ALD0) */ +#define IIC0_ARBITRATION 0x40 +#define IIC0_ARBITRATION_NO 0x00 /* arbitration win or no arbitration */ +#define IIC0_ARBITRATION_LOSS 0x40 /* arbitration loss */ + +/* Detection of extension code reception (EXC0) */ +#define IIC0_EXTENSIONCODE 0x20 +#define IIC0_EXTCODE_NOT 0x00 /* extension code not received */ +#define IIC0_EXTCODE_RECEIVED 0x20 /* extension code received */ + +/* Detection of matching addresses (COI0) */ +#define IIC0_ADDRESSMATCH 0x10 +#define IIC0_ADDRESS_NOTMATCH 0x00 /* addresses do not match */ +#define IIC0_ADDRESS_MATCH 0x10 /* addresses match */ + +/* Detection of transmit/receive status (TRC0) */ +#define IIC0_STATUS 0x08 +#define IIC0_STATUS_RECEIVE 0x00 /* receive status */ +#define IIC0_STATUS_TRANSMIT 0x08 /* transmit status */ + +/* Detection of acknowledge signal (ACKD0) */ +#define IIC0_ACKDETECTION 0x04 +#define IIC0_ACK_NOTDETECTED 0x00 /* ACK signal was not detected */ +#define IIC0_ACK_DETECTED 0x04 /* ACK signal was detected */ + +/* Detection of start condition (STD0) */ +#define IIC0_STARTDETECTION 0x02 +#define IIC0_START_NOTDETECTED 0x00 /* start condition not detected */ +#define IIC0_START_DETECTED 0x02 /* start condition detected */ + +/* Detection of stop condition (SPD0) */ +#define IIC0_STOPDETECTION 0x01 +#define IIC0_STOP_NOTDETECTED 0x00 /* stop condition not detected */ +#define IIC0_STOP_DETECTED 0x01 /* stop condition detected */ + +/* + IIC Flag Register 0 (IICF0) +*/ +/* STT0 clear flag (STCF) */ +#define IIC0_STARTFLAG 0x80 +#define IIC0_STARTFLAG_GENERATE 0x00 /* generate start condition */ +#define IIC0_STARTFLAG_UNSUCCESSFUL 0x80 /* start condition generation unsuccessful */ + +/* IIC bus status flag (IICBSY) */ +#define IIC0_BUSSTATUS 0x40 +#define IIC0_BUS_RELEASE 0x00 /* bus release status */ +#define IIC0_BUS_COMMUNICATION 0x40 /* bus communication status */ + +/* Initial start enable trigger (STCEN) */ +#define IIC0_STARTWITHSTOP 0x02 +#define IIC0_START_WITHSTOP 0x00 /* generation of a start condition without detecting a stop condition */ +#define IIC0_START_WITHOUTSTOP 0x02 /* generation of a start condition upon detection of a stop condition */ + +/* Communication reservation function disable bit (IICRSV) */ +#define IIC0_RESERVATION 0x01 +#define IIC0_RESERVATION_ENABLE 0x00 /* enable communication reservation */ +#define IIC0_RESERVATION_DISABLE 0x01 /* disable communication reservation */ + +/* + IIC clock selection register 0 (IICCL0) +*/ +#define IICCL0_INITIALVALUE 0x00 +/* Detection of SCL0 pin level (CLD0) */ +#define IIC0_SCLLEVEL 0x20 +#define IIC0_SCL_LOW 0x00 /* clock line at low level */ +#define IIC0_SCL_HIGH 0x20 /* clock line at high level */ + +/* Detection of SDA0 pin level (DAD0) */ +#define IIC0_SDALEVEL 0x10 +#define IIC0_SDA_LOW 0x00 /* data line at low level */ +#define IIC0_SDA_HIGH 0x10 /* data line at high level */ + +/* Operation mode switching (SMC0) */ +#define IIC0_OPERATIONMODE 0x08 +#define IIC0_MODE_STANDARD 0x00 /* operates in standard mode */ +#define IIC0_MODE_HIGHSPEED 0x08 /* operates in high-speed mode */ + +/* Digital filter operation control (DFC0) */ +#define IIC0_DIGITALFILTER 0x04 +#define IIC0_FILTER_OFF 0x00 /* digital filter off */ +#define IIC0_FILTER_ON 0x04 /* digital filter on */ + +/* Operation mode switching (CL01, CL00) */ +#define IIC0_CLOCKSELECTION 0x03 + +/* Combine of (SMC0, CL01, CL00)*/ +#define IIC0_CLOCK0 0x00 +#define IIC0_CLOCK1 0x01 +#define IIC0_CLOCK2 0x02 +#define IIC0_CLOCK3 0x03 +#define IIC0_CLOCK4 0x08 +#define IIC0_CLOCK5 0x09 +#define IIC0_CLOCK6 0x0a +#define IIC0_CLOCK7 0x0b + +/* + IIC function expansion register 0 (IICX0) +*/ +/* IIC clock expension (CLX0) */ +#define IIC0_CLOCKEXPENSION 0x01 +#define IIC0_EXPENSION0 0x00 +#define IIC0_EXPENSION1 0x01 + +/* Operation clock (CLX0, SMC0, CL01, CL00) + | IIC0_EXPENSION0 | IIC0_EXPENSION1 | +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK0 | fprs/2 | prohibited | selection clock(fw) + | fprs/88 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK1 | fprs/2 | prohibited | selection clock(fw) + | fprs/172 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK2 | fprs/2 | prohibited | selection clock(fw) + | fprs/344 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK3 |prohibited/fexscl0 | prohibited | selection clock(fw) + | fw/66 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK4 | fprs/2 | fprs/2 | selection clock(fw) + | fprs/48 | fprs/24 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK5 | fprs/2 | fprs/2 | selection clock(fw) + | fprs/48 | fprs/24 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK6 | fprs/4 | fprs/4 | selection clock(fw) + | fprs/96 | fprs/48 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK7 |prohibited/fexscl0 | prohibited | selection clock(fw) + | fw/18 | | transfer clock + | high speed | | mode +------------|-------------------|-------------------|---------------------- +*/ + +#define ADDRESS_COMPLETE 0x80 +#define IIC_MASTER_FLAG_CLEAR 0x00 + +/****************************************************************************** + * Macro define + ******************************************************************************/ + + + +/****************************************************************************** + * Function define + ******************************************************************************/ + +void IIC_ctr_Init( void ); +void IIC_ctr_Stop( void ); + + +#endif diff --git a/branches/0.10(X3)/i2c_ctr.prn b/branches/0.10(X3)/i2c_ctr.prn new file mode 100644 index 0000000..a3d4ed0 --- /dev/null +++ b/branches/0.10(X3)/i2c_ctr.prn @@ -0,0 +1,963 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\i2c_ctr.asm +Para-file: +In-file: inter_asm\i2c_ctr.asm +Obj-file: i2c_ctr.rel +Prn-file: i2c_ctr.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c + 6 6 ; In-file : i2c_ctr.c + 7 7 ; Asm-file : inter_asm\i2c_ctr.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 07CH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, i2c_ctr.c + 18 18 $DGS MOD_NAM, i2c_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 36 36 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 37 37 $DGS GLV_SYM, _int_iic_ctr, U, U, 0E001H, 026H, 01H, 02H + 38 38 $DGS AUX_FUN, 00H, U, U, 070H, 00H, 00H + 39 39 $DGS BEG_FUN, ??bf_int_iic_ctr, U, U, 00H, 065H, 01H, 00H + 40 40 $DGS AUX_BEG, 041H, 016H, 01EH + 41 41 $DGS STA_SYM, _state, ?L0003, U, 0CH, 03H, 00H, 00H + 42 42 $DGS STA_SYM, _reg_adrs, ?L0004, U, 0CH, 03H, 00H, 00H + 43 43 $DGS STA_SYM, _reg_adrs_internal, ?L0005, U, 0CH, 03H, 00H, 00H + 44 44 $DGS STA_SYM, _tx_buf, ?L0006, U, 0CH, 03H, 00H, 00H + 45 45 $DGS REG_VAR, _rx_buf, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 46 46 $DGS BEG_BLK, ??bb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 47 47 $DGS AUX_BEG, 0CH, 00H, 020H + 48 48 $DGS BEG_BLK, ??bb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 49 49 $DGS AUX_BEG, 014H, 00H, 022H + 50 50 $DGS BEG_BLK, ??bb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 51 51 $DGS AUX_BEG, 015H, 00H, 026H + 52 52 $DGS END_BLK, ??eb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 53 53 $DGS AUX_END, 015H + 54 54 $DGS BEG_BLK, ??bb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 55 55 $DGS AUX_BEG, 01BH, 00H, 028H + 56 56 $DGS BEG_BLK, ??bb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 57 57 $DGS AUX_BEG, 01CH, 00H, 02CH + 58 58 $DGS END_BLK, ??eb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 59 59 $DGS AUX_END, 01CH + 60 60 $DGS BEG_BLK, ??bb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 61 61 $DGS AUX_BEG, 01DH, 00H, 036H + 62 62 $DGS END_BLK, ??eb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 63 63 $DGS AUX_END, 01DH + 64 64 $DGS END_BLK, ??eb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 65 65 $DGS AUX_END, 01EH + 66 66 $DGS END_BLK, ??eb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 67 67 $DGS AUX_END, 01FH + 68 68 $DGS END_BLK, ??eb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 69 69 $DGS AUX_END, 026H + 70 70 $DGS BEG_BLK, ??bb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 71 71 $DGS AUX_BEG, 02AH, 00H, 03AH + 72 72 $DGS END_BLK, ??eb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 73 73 $DGS AUX_END, 030H + 74 74 $DGS BEG_BLK, ??bb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 75 75 $DGS AUX_BEG, 033H, 00H, 03CH + 76 76 $DGS BEG_BLK, ??bb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 77 77 $DGS AUX_BEG, 037H, 00H, 042H + 78 78 $DGS END_BLK, ??eb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 79 79 $DGS AUX_END, 03AH + 80 80 $DGS END_BLK, ??eb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 81 81 $DGS AUX_END, 03BH + 82 82 $DGS BEG_BLK, ??bb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 83 83 $DGS AUX_BEG, 03EH, 00H, 044H + 84 84 $DGS BEG_BLK, ??bb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 85 85 $DGS AUX_BEG, 04CH, 00H, 048H + 86 86 $DGS END_BLK, ??eb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 87 87 $DGS AUX_END, 04EH + 88 88 $DGS BEG_BLK, ??bb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 89 89 $DGS AUX_BEG, 050H, 00H, 04CH + 90 90 $DGS END_BLK, ??eb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 91 91 $DGS AUX_END, 052H + 92 92 $DGS BEG_BLK, ??bb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 93 93 $DGS AUX_BEG, 059H, 00H, 04EH + 94 94 $DGS BEG_BLK, ??bb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 95 95 $DGS AUX_BEG, 05CH, 00H, 052H + 96 96 $DGS END_BLK, ??eb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 97 97 $DGS AUX_END, 05FH + 98 98 $DGS BEG_BLK, ??bb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 99 99 $DGS AUX_BEG, 061H, 00H, 058H + 100 100 $DGS END_BLK, ??eb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 101 101 $DGS AUX_END, 067H + 102 102 $DGS END_BLK, ??eb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_END, 068H + 104 104 $DGS BEG_BLK, ??bb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_BEG, 06AH, 00H, 05CH + 106 106 $DGS END_BLK, ??eb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 107 107 $DGS AUX_END, 06DH + 108 108 $DGS BEG_BLK, ??bb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_BEG, 071H, 00H, 060H + 110 110 $DGS END_BLK, ??eb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_END, 074H + 112 112 $DGS BEG_BLK, ??bb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 113 113 $DGS AUX_BEG, 076H, 00H, 064H + 114 114 $DGS END_BLK, ??eb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 115 115 $DGS AUX_END, 07AH + 116 116 $DGS BEG_BLK, ??bb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 117 117 $DGS AUX_BEG, 07EH, 00H, 068H + 118 118 $DGS END_BLK, ??eb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 119 119 $DGS AUX_END, 080H + 120 120 $DGS BEG_BLK, ??bb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_BEG, 083H, 00H, 00H + 122 122 $DGS END_BLK, ??eb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 123 123 $DGS AUX_END, 085H + 124 124 $DGS END_BLK, ??eb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H + 125 125 $DGS AUX_END, 087H + 126 126 $DGS END_FUN, ??ef_int_iic_ctr, U, U, 00H, 065H, 01H, 00H + 127 127 $DGS AUX_END, 088H + 128 128 $DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 026H, 01H, 02H + 129 129 $DGS AUX_FUN, 00H, U, U, 076H, 00H, 00H + 130 130 $DGS BEG_FUN, ??bf_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H + 131 131 $DGS AUX_BEG, 0CEH, 00H, 076H + 132 132 $DGS END_FUN, ??ef_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H + 133 133 $DGS AUX_END, 02CH + 134 134 $DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 026H, 01H, 02H + 135 135 $DGS AUX_FUN, 00H, U, U, 07CH, 00H, 00H + 136 136 $DGS BEG_FUN, ??bf_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H + 137 137 $DGS AUX_BEG, 0FFH, 00H, 07CH + 138 138 $DGS END_FUN, ??ef_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H + 139 139 $DGS AUX_END, 04H + 140 140 $DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 026H, 00H, 00H + 141 141 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 142 142 $DGS GLV_SYM, _irq_readed, U, U, 034CH, 02H, 00H, 00H + 143 143 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 144 144 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 145 145 $DGS GLV_SYM, _hosu_read_end, U, U, 01H, 02H, 01H, 02H + 146 146 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 147 147 $DGS GLV_SYM, _rtc_unlock, U, U, 01H, 02H, 01H, 02H + 148 148 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 149 149 $DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 02H, 01H, 02H + 150 150 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 151 151 $DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 02H, 01H, 02H + 152 152 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 153 153 $DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 02H, 01H, 02H + 154 154 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 155 155 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 156 156 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 157 157 + 158 158 EXTRN _@SEGAX + 159 159 EXTRN _@SEGDE + 160 160 EXTRN _@RTARG0 + 161 161 EXTRN _vreg_ctr + 162 162 EXTRN _hosu_read_end + 163 163 EXTRN _rtc_unlock + 164 164 EXTRN _vreg_ctr_read + 165 165 EXTRN _vreg_ctr_after_read + 166 166 EXTRN _vreg_ctr_write + 167 167 EXTBIT _irq_readed + 168 168 PUBLIC _iic_burst_state + 169 169 PUBLIC _int_iic_ctr + 170 170 PUBLIC _IIC_ctr_Init + 171 171 PUBLIC _IIC_ctr_Stop + 172 172 + 173 173 ----- @@BITS BSEG + 174 174 + 175 175 ----- @@CNST CSEG MIRRORP + 176 176 00000 01 _lpf_coeff: DB 01H ; 1 + 177 177 00001 02 DB 02H ; 2 + 178 178 00002 02 DB 02H ; 2 + 179 179 00003 03 DB 03H ; 3 + 180 180 00004 03 DB 03H ; 3 + 181 181 00005 02 DB 02H ; 2 + 182 182 00006 00 DB 00H ; 0 + 183 183 00007 FE DB 0FEH ; 254 + 184 184 00008 FB DB 0FBH ; 251 + 185 185 00009 F7 DB 0F7H ; 247 + 186 186 0000A F3 DB 0F3H ; 243 + 187 187 0000B F0 DB 0F0H ; 240 + 188 188 0000C F0 DB 0F0H ; 240 + 189 189 0000D F3 DB 0F3H ; 243 + 190 190 0000E FA DB 0FAH ; 250 + 191 191 0000F 04 DB 04H ; 4 + 192 192 00010 12 DB 012H ; 18 + 193 193 00011 25 DB 025H ; 37 + 194 194 00012 38 DB 038H ; 56 + 195 195 00013 4D DB 04DH ; 77 + 196 196 00014 5F DB 05FH ; 95 + 197 197 00015 6E DB 06EH ; 110 + 198 198 00016 77 DB 077H ; 119 + 199 199 00017 7A DB 07AH ; 122 + 200 200 00018 77 DB 077H ; 119 + 201 201 00019 6E DB 06EH ; 110 + 202 202 0001A 5F DB 05FH ; 95 + 203 203 0001B 4D DB 04DH ; 77 + 204 204 0001C 38 DB 038H ; 56 + 205 205 0001D 25 DB 025H ; 37 + 206 206 0001E 12 DB 012H ; 18 + 207 207 0001F 04 DB 04H ; 4 + 208 208 00020 FA DB 0FAH ; 250 + 209 209 00021 F3 DB 0F3H ; 243 + 210 210 00022 F0 DB 0F0H ; 240 + 211 211 00023 F0 DB 0F0H ; 240 + 212 212 00024 F3 DB 0F3H ; 243 + 213 213 00025 F7 DB 0F7H ; 247 + 214 214 00026 FB DB 0FBH ; 251 + 215 215 00027 FE DB 0FEH ; 254 + 216 216 00028 00 DB 00H ; 0 + 217 217 00029 02 DB 02H ; 2 + 218 218 0002A 03 DB 03H ; 3 + 219 219 0002B 03 DB 03H ; 3 + 220 220 0002C 02 DB 02H ; 2 + 221 221 0002D 02 DB 02H ; 2 + 222 222 0002E 01 DB 01H ; 1 + 223 223 0002F 00 DB (1) + 224 224 + 225 225 ----- @@R_INIT CSEG UNIT64KP + 226 226 00000 00 DB 00H ; 0 + 227 227 00001 00 DB (1) + 228 228 + 229 229 ----- @@INIT DSEG BASEP + 230 230 00000 ?L0003: DS (1) + 231 231 00001 DS (1) + 232 232 + 233 233 ----- @@DATA DSEG BASEP + 234 234 00000 _iic_burst_state: DS (1) + 235 235 00001 ?L0004: DS (1) + 236 236 00002 ?L0005: DS (1) + 237 237 00003 ?L0006: DS (1) + 238 238 + 239 239 ----- @@R_INIS CSEG UNIT64KP + 240 240 + 241 241 ----- @@INIS DSEG SADDRP + 242 242 + 243 243 ----- @@DATS DSEG SADDRP + 244 244 + 245 245 ----- @@CNSTL CSEG PAGE64KP + 246 246 + 247 247 ----- @@RLINIT CSEG UNIT64KP + 248 248 + 249 249 ----- @@INITL DSEG UNIT64KP + 250 250 + 251 251 ----- @@DATAL DSEG UNIT64KP + 252 252 + 253 253 ----- @@CALT CSEG CALLT0 + 254 254 + 255 255 ; line 1 : /* ======================================================== + 256 256 ; line 2 : 対SoC 新規チャンネル I2C通信 + 257 257 ; line 3 : 藤田＠開技.nintendo + 258 258 ; line 4 : '09 Apr + 259 259 ; line 5 : ======================================================== */ + 260 260 ; line 6 : #include "incs.h" + 261 261 ; line 7 : #include "accero.h" + 262 262 ; line 8 : + 263 263 ; line 9 : #ifdef _MCU_BSR_ + 264 264 ; line 10 : // #ifdef _MODEL_TS0_ || _MODEL_WM0_ + 265 265 ; line 11 : + 266 266 ; line 12 : // ワーキングモデルはI2Cが逆 + 267 267 ; line 13 : // TEGは回路図でテレコ + 268 268 ; line 14 : #define ACKD ACKD1 + 269 269 ; line 15 : #define ACKE ACKE1 + 270 270 ; line 16 : #define COI COI1 + 271 271 ; line 17 : #define IICAEN IICA1EN + 272 272 ; line 18 : #define IICRSV IICRSV1 + 273 273 ; line 19 : #define IICA IICA1 + 274 274 ; line 20 : #define IICAIF IICAIF1 + 275 275 ; line 21 : #define IICAMK IICAMK1 + 276 276 ; line 22 : #define IICAPR0 IICAPR11 + 277 277 ; line 23 : #define IICAPR1 IICAPR01 + 278 278 ; line 24 : #define IICCTL0 IICCTL10 + 279 279 ; line 25 : #define IICE IICE1 + 280 280 ; line 26 : #define IICF IICF1 + 281 281 ; line 27 : #define IICS IICS1 + 282 282 ; line 28 : #define IICWH IICWH1 + 283 283 ; line 29 : #define IICWL IICWL1 + 284 284 ; line 30 : #define LREL LREL1 + 285 285 ; line 31 : #define SPD SPD1 + 286 286 ; line 32 : #define SPIE SPIE1 + 287 287 ; line 33 : #define STCEN STCEN1 + 288 288 ; line 34 : #define STD STD1 + 289 289 ; line 35 : #define SVA SVA1 + 290 290 ; line 36 : #define WREL WREL1 + 291 291 ; line 37 : #define WTIM WTIM1 + 292 292 ; line 38 : #define TRC TRC1 + 293 293 ; line 39 : #define SMC SMC1 + 294 294 ; line 40 : #define DFC DFC1 + 295 295 ; line 41 : + 296 296 ; line 42 : + 297 297 ; line 43 : #endif + 298 298 ; line 44 : + 299 299 ; line 45 : // ============================================== + 300 300 ; line 46 : extern bit irq_readed; // いずれかのIRQレジスタが + 301 301 ; 読まれた + 302 302 ; line 47 : + 303 303 ; line 48 : u8 iic_burst_state; + 304 304 ; line 49 : + 305 305 ; line 50 : + 306 306 ; line 51 : /* ======================================================== + 307 307 ; line 52 : ======================================================== */ + 308 308 ; line 53 : enum + 309 309 ; line 54 : { + 310 310 ; line 55 : IIC_IDLE = 0, + 311 311 ; line 56 : IIC_RCV_REG_ADRS, + 312 312 ; line 57 : IIC_TX_OR_RX, + 313 313 ; line 58 : IIC_TX, + 314 314 ; line 59 : IIC_RX + 315 315 ; line 60 : }; + 316 316 ; line 61 : + 317 317 ; line 62 : + 318 318 ; line 63 : // 1バイト送受の度に割り込みが発生するバージョン + 319 319 ; line 64 : __interrupt void int_iic_ctr( ) + 320 320 ; line 65 : { + 321 321 + 322 322 ----- @@BASE CSEG BASE + 323 323 00000 _int_iic_ctr: + 324 324 $DGL 1,21 + 325 325 00000 C1 push ax ;[INF] 1, 1 + 326 326 00001 C3 push bc ;[INF] 1, 1 + 327 327 00002 C5 push de ;[INF] 1, 1 + 328 328 00003 C7 push hl ;[INF] 1, 1 + 329 329 00004 520C mov c,#0CH ;[INF] 2, 1 + 330 330 00006 92 dec c ;[INF] 1, 1 + 331 331 00007 92 dec c ;[INF] 1, 1 + 332 332 00008 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 333 333 0000B C1 push ax ;[INF] 1, 1 + 334 334 0000C DFF8 bnz $$-6 ;[INF] 2, 4 + 335 335 0000E 8EFD mov a,ES ;[INF] 2, 1 + 336 336 00010 70 mov x,a ;[INF] 1, 1 + 337 337 00011 8EFC mov a,CS ;[INF] 2, 1 + 338 338 00013 C1 push ax ;[INF] 1, 1 + 339 339 00014 ??bf_int_iic_ctr: + 340 340 ; line 66 : static u8 state = IIC_IDLE; + 341 341 ; line 67 : static u8 reg_adrs; + 342 342 ; line 68 : static u8 reg_adrs_internal; + 343 343 ; line 69 : static u8 tx_buf; + 344 344 ; line 70 : u8 rx_buf; + 345 345 ; line 71 : + 346 346 ; line 72 : EI(); + 347 347 $DGL 0,8 + 348 348 00014 717AFA ei ;[INF] 3, 4 + 349 349 ; line 73 : + 350 350 ; line 74 : // 読み出し終了 + 351 351 ; line 75 : if( !ACKD ) // 割り込み要因はNAK（データ送信 + 352 352 ; の最後） + 353 353 $DGL 0,11 + 354 354 00017 C7 push hl ;[INF] 1, 1 + 355 355 00018 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 356 356 0001B 71A4 mov1 CY,[hl].2 ;[INF] 2, 1 + 357 357 0001D C6 pop hl ;[INF] 1, 1 + 358 358 0001E DC41 bc $?L0007 ;[INF] 2, 4 + 359 359 ; line 76 : { + 360 360 00020 ??bb00_int_iic_ctr: + 361 361 ; line 77 : state = IIC_IDLE; + 362 362 $DGL 0,13 + 363 363 00020 RF50000 clrb !?L0003 ; state ;[INF] 3, 1 + 364 364 ; line 78 : SPIE = 0; + 365 365 $DGL 0,14 + 366 366 00023 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 + 367 367 ; line 79 : LREL = 1; + 368 368 $DGL 0,15 + 369 369 00027 71605005 set1 !IICCTL01.6 ;[INF] 4, 2 + 370 370 ; line 80 : + 371 371 ; line 81 : // レジスタリードで、割り込みピンをネゲート + 372 372 ; line 82 : // まだ読まれてない割り込みがあれば、再度アサート + 373 373 ; line 83 : if( irq_readed ) + 374 374 $DGL 0,19 + 375 375 0002B R31040026 bf _irq_readed,$?L0011 ;[INF] 4, 5 + 376 376 ; line 84 : { + 377 377 0002F ??bb01_int_iic_ctr: + 378 378 ; line 85 : IRQ0_neg; + 379 379 $DGL 0,21 + 380 380 0002F ??bb02_int_iic_ctr: + 381 381 0002F 716A27 set1 PM7.6 ;[INF] 3, 2 + 382 382 00032 ??eb02_int_iic_ctr: + 383 383 ; line 86 : irq_readed = 0; + 384 384 $DGL 0,22 + 385 385 00032 R710300 clr1 _irq_readed ;[INF] 3, 2 + 386 386 ; line 87 : if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 ) + 387 387 ; line 88 : && ( vreg_ctr[VREG_C_IRQ1] == 0 ) + 388 388 ; line 89 : && ( vreg_ctr[VREG_C_IRQ2] == 0 ) + 389 389 ; line 90 : && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) ) + 390 390 $DGL 0,26 + 391 391 00035 RD51000 cmp0 !_vreg_ctr+16 ;[INF] 3, 1 + 392 392 00038 DF0F bnz $?L0013 ;[INF] 2, 4 + 393 393 0003A RD51100 cmp0 !_vreg_ctr+17 ;[INF] 3, 1 + 394 394 0003D DF0A bnz $?L0013 ;[INF] 2, 4 + 395 395 0003F RD51200 cmp0 !_vreg_ctr+18 ;[INF] 3, 1 + 396 396 00042 DF05 bnz $?L0013 ;[INF] 2, 4 + 397 397 00044 RD51300 cmp0 !_vreg_ctr+19 ;[INF] 3, 1 + 398 398 00047 DD0C bz $?L0011 ;[INF] 2, 4 + 399 399 00049 ?L0013: + 400 400 ; line 91 : { + 401 401 00049 ??bb03_int_iic_ctr: + 402 402 ; line 92 : while( !IRQ0 ){;} // 時間稼ぎ不要かも + 403 403 $DGL 0,28 + 404 404 00049 31620702 bt P7.6,$?L0015 ;[INF] 4, 5 + 405 405 0004D ??bb04_int_iic_ctr: + 406 406 0004D ??eb04_int_iic_ctr: + 407 407 0004D EFFA br $?L0013 ;[INF] 2, 3 + 408 408 0004F ?L0015: + 409 409 ; line 93 : IRQ0_ast; + 410 410 $DGL 0,29 + 411 411 0004F ??bb05_int_iic_ctr: + 412 412 0004F 716307 clr1 P7.6 ;[INF] 3, 2 + 413 413 00052 716B27 clr1 PM7.6 ;[INF] 3, 2 + 414 414 00055 ??eb05_int_iic_ctr: + 415 415 00055 ??eb03_int_iic_ctr: + 416 416 ; line 94 : } + 417 417 00055 ?L0011: + 418 418 00055 ??eb01_int_iic_ctr: + 419 419 ; line 95 : } + 420 420 ; line 96 : + 421 421 ; line 97 : // 歩数計読み出し終了 + 422 422 ; line 98 : hosu_read_end( ); + 423 423 $DGL 0,34 + 424 424 00055 RFD0000 call !_hosu_read_end ;[INF] 3, 3 + 425 425 ; line 99 : rtc_unlock( ); + 426 426 $DGL 0,35 + 427 427 00058 RFD0000 call !_rtc_unlock ;[INF] 3, 3 + 428 428 ; line 100 : iic_burst_state = 0; + 429 429 $DGL 0,36 + 430 430 0005B RF50000 clrb !_iic_burst_state ;[INF] 3, 1 + 431 431 ; line 101 : return; + 432 432 $DGL 0,37 + 433 433 0005E RED4B01 br !?L0023 ;[INF] 3, 3 + 434 434 00061 ??eb00_int_iic_ctr: + 435 435 ; line 102 : } + 436 436 00061 ?L0007: + 437 437 ; line 103 : + 438 438 ; line 104 : if( SPD ) // 割り込み要因はストップコンディ + 439 439 ; ション + 440 440 $DGL 0,40 + 441 441 00061 C7 push hl ;[INF] 1, 1 + 442 442 00062 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 443 443 00065 7184 mov1 CY,[hl].0 ;[INF] 2, 1 + 444 444 00067 C6 pop hl ;[INF] 1, 1 + 445 445 00068 DE0D bnc $?L0016 ;[INF] 2, 4 + 446 446 ; line 105 : // 通信の最後。↑の !ACKD に来た + 447 447 ; ときは割り込み来ない (SPIE = 0 のため ) + 448 448 ; line 106 : { + 449 449 0006A ??bb06_int_iic_ctr: + 450 450 ; line 107 : state = IIC_IDLE; + 451 451 $DGL 0,43 + 452 452 0006A RF50000 clrb !?L0003 ; state ;[INF] 3, 1 + 453 453 ; line 108 : SPIE = 0; + 454 454 $DGL 0,44 + 455 455 0006D 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 + 456 456 ; line 109 : // I2C終了時に何かする物 // + 457 457 ; line 110 : rtc_unlock( ); + 458 458 $DGL 0,46 + 459 459 00071 RFD0000 call !_rtc_unlock ;[INF] 3, 3 + 460 460 ; line 111 : return; + 461 461 $DGL 0,47 + 462 462 00074 RED4B01 br !?L0023 ;[INF] 3, 3 + 463 463 00077 ??eb06_int_iic_ctr: + 464 464 ; line 112 : } + 465 465 00077 ?L0016: + 466 466 ; line 113 : + 467 467 ; line 114 : if( STD ) // 割り込み要因：スタートコンディ + 468 468 ; ション + 469 469 $DGL 0,50 + 470 470 00077 C7 push hl ;[INF] 1, 1 + 471 471 00078 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 472 472 0007B 7194 mov1 CY,[hl].1 ;[INF] 2, 1 + 473 473 0007D C6 pop hl ;[INF] 1, 1 + 474 474 0007E DE15 bnc $?L0020 ;[INF] 2, 4 + 475 475 ; line 115 : { + 476 476 00080 ??bb07_int_iic_ctr: + 477 477 ; line 116 : if( ( state == IIC_TX ) || ( state == IIC_RX ) + 478 478 ; line 117 : || ( state == IIC_RCV_REG_ADRS ) + 479 479 $DGL 0,53 + 480 480 00080 R40000003 cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + 481 481 00084 DD0C bz $?L0022 ;[INF] 2, 4 + 482 482 00086 R40000004 cmp !?L0003,#04H ; state,4 ;[INF] 4, 1 + 483 483 0008A DD06 bz $?L0022 ;[INF] 2, 4 + 484 484 0008C R40000001 cmp !?L0003,#01H ; state,1 ;[INF] 4, 1 + 485 485 00090 61F8 sknz ;[INF] 2, 1 + 486 486 00092 ?L0022: + 487 487 ; line 118 : ) + 488 488 ; line 119 : { + 489 489 00092 ??bb08_int_iic_ctr: + 490 490 ; line 120 : state = IIC_IDLE; + 491 491 $DGL 0,56 + 492 492 00092 RF50000 clrb !?L0003 ; state ;[INF] 3, 1 + 493 493 00095 ??eb08_int_iic_ctr: + 494 494 ; line 121 : // no break // + 495 495 ; line 122 : } + 496 496 00095 ?L0020: + 497 497 00095 ??eb07_int_iic_ctr: + 498 498 ; line 123 : } + 499 499 ; line 124 : + 500 500 ; line 125 : switch ( state ) + 501 501 $DGL 0,61 + 502 502 00095 RD90000 mov x,!?L0003 ; state ;[INF] 3, 1 + 503 503 00098 F1 clrb a ;[INF] 1, 1 + 504 504 00099 E7 onew bc ;[INF] 1, 1 + 505 505 0009A 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 506 506 0009D DD08 bz $?L0024 ;[INF] 2, 4 + 507 507 0009F 23 subw ax,bc ;[INF] 1, 1 + 508 508 000A0 DD13 bz $?L0025 ;[INF] 2, 4 + 509 509 000A2 23 subw ax,bc ;[INF] 1, 1 + 510 510 000A3 DD36 bz $?L0026 ;[INF] 2, 4 + 511 511 000A5 EF5D br $?L0033 ;[INF] 2, 3 + 512 512 ; line 126 : { + 513 513 000A7 ??bb09_int_iic_ctr: + 514 514 ; line 127 : case ( IIC_IDLE ): + 515 515 000A7 ?L0024: + 516 516 ; line 128 : // 自局呼び出しに応答。 + 517 517 ; line 129 : // 初期化など + 518 518 ; line 130 : SPIE = 1; + 519 519 $DGL 0,66 + 520 520 000A7 71405005 set1 !IICCTL01.4 ;[INF] 4, 2 + 521 521 ; line 131 : state = IIC_RCV_REG_ADRS; + 522 522 $DGL 0,67 + 523 523 000AB RE50000 oneb !?L0003 ; state ;[INF] 3, 1 + 524 524 ; line 132 : WREL = 1; // ウェイト解除 + 525 525 $DGL 0,68 + 526 526 000AE 71505005 set1 !IICCTL01.5 ;[INF] 4, 2 + 527 527 ; line 133 : break; + 528 528 $DGL 0,69 + 529 529 000B2 RED4B01 br !?L0023 ;[INF] 3, 3 + 530 530 ; line 134 : + 531 531 ; line 135 : case ( IIC_RCV_REG_ADRS ): // ２バイト目（レジスタアドレス） + 532 532 ; 受信後に来る + 533 533 000B5 ?L0025: + 534 534 ; line 136 : // レジスタアドレス受信 + 535 535 ; line 137 : reg_adrs = IICA; + 536 536 $DGL 0,73 + 537 537 000B5 8F4005 mov a,!IICA1 ;[INF] 3, 1 + 538 538 000B8 R9F0100 mov !?L0004,a ; reg_adrs ;[INF] 3, 1 + 539 539 ; line 138 : tx_buf = vreg_ctr_read( reg_adrs ); // データの準備を + 540 540 ; しておく + 541 541 $DGL 0,74 + 542 542 000BB RD90100 mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + 543 543 000BE F1 clrb a ;[INF] 1, 1 + 544 544 000BF RFD0000 call !_vreg_ctr_read ;[INF] 3, 3 + 545 545 000C2 62 mov a,c ;[INF] 1, 1 + 546 546 000C3 R9F0300 mov !?L0006,a ; tx_buf ;[INF] 3, 1 + 547 547 ; line 139 : if( reg_adrs != VREG_C_INFO ) + 548 548 $DGL 0,75 + 549 549 000C6 R4001007F cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1 + 550 550 000CA DD06 bz $?L0030 ;[INF] 2, 4 + 551 551 ; line 140 : { + 552 552 000CC ??bb0A_int_iic_ctr: + 553 553 ; line 141 : state = IIC_TX_OR_RX; + 554 554 $DGL 0,77 + 555 555 000CC RCF000002 mov !?L0003,#02H ; state,2 ;[INF] 4, 1 + 556 556 000D0 ??eb0A_int_iic_ctr: + 557 557 ; line 142 : } + 558 558 $DGL 0,78 + 559 559 000D0 EF03 br $?L0031 ;[INF] 2, 3 + 560 560 000D2 ?L0030: + 561 561 ; line 143 : else + 562 562 ; line 144 : { + 563 563 000D2 ??bb0B_int_iic_ctr: + 564 564 ; line 145 : state = IIC_IDLE; + 565 565 $DGL 0,81 + 566 566 000D2 RF50000 clrb !?L0003 ; state ;[INF] 3, 1 + 567 567 000D5 ??eb0B_int_iic_ctr: + 568 568 ; line 146 : } + 569 569 000D5 ?L0031: + 570 570 ; line 147 : WREL = 1; + 571 571 $DGL 0,83 + 572 572 000D5 71505005 set1 !IICCTL01.5 ;[INF] 4, 2 + 573 573 ; line 148 : break; + 574 574 $DGL 0,84 + 575 575 000D9 EF70 br $?L0023 ;[INF] 2, 3 + 576 576 ; line 149 : + 577 577 ; line 150 : case ( IIC_TX_OR_RX ): // ↑の次に来る割り込み。STなら送 + 578 578 ; 信準備、データが来たら書き込まれ + 579 579 000DB ?L0026: + 580 580 ; line 151 : // if( TRC ){ // 送信方向フラグ で区別するのは、割り + 581 581 ; 込み遅延時に不具合が起こりえる + 582 582 ; line 152 : if( STD ) + 583 583 $DGL 0,88 + 584 584 000DB C7 push hl ;[INF] 1, 1 + 585 585 000DC 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 586 586 000DF 7194 mov1 CY,[hl].1 ;[INF] 2, 1 + 587 587 000E1 C6 pop hl ;[INF] 1, 1 + 588 588 000E2 DE1C bnc $?L0032 ;[INF] 2, 4 + 589 589 ; line 153 : { // スタートコンディション検出フラ + 590 590 ; グ + 591 591 000E4 ??bb0C_int_iic_ctr: + 592 592 ; line 154 : // リードされる + 593 593 ; line 155 : if( COI ) + 594 594 $DGL 0,91 + 595 595 000E4 C7 push hl ;[INF] 1, 1 + 596 596 000E5 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 597 597 000E8 71C4 mov1 CY,[hl].4 ;[INF] 2, 1 + 598 598 000EA C6 pop hl ;[INF] 1, 1 + 599 599 000EB DE06 bnc $?L0034 ;[INF] 2, 4 + 600 600 ; line 156 : { // アドレス一致フラグ + 601 601 000ED ??bb0D_int_iic_ctr: + 602 602 ; line 157 : state = IIC_TX; + 603 603 $DGL 0,93 + 604 604 000ED RCF000003 mov !?L0003,#03H ; state,3 ;[INF] 4, 1 + 605 605 000F1 ??eb0D_int_iic_ctr: + 606 606 ; line 158 : // no break, no return // + 607 607 ; line 159 : } + 608 608 $DGL 0,95 + 609 609 000F1 EF11 br $?L0033 ;[INF] 2, 3 + 610 610 000F3 ?L0034: + 611 611 ; line 160 : else + 612 612 ; line 161 : { + 613 613 000F3 ??bb0E_int_iic_ctr: + 614 614 ; line 162 : // リスタートで違うデバイスが呼ばれた！ + 615 615 ; line 163 : state = IIC_IDLE; // 終了処理 + 616 616 $DGL 0,99 + 617 617 000F3 RF50000 clrb !?L0003 ; state ;[INF] 3, 1 + 618 618 ; line 164 : SPIE = 0; + 619 619 $DGL 0,100 + 620 620 000F6 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 + 621 621 ; line 165 : LREL = 1; // ウェイト解除? + 622 622 $DGL 0,101 + 623 623 000FA 71605005 set1 !IICCTL01.6 ;[INF] 4, 2 + 624 624 ; line 166 : return; + 625 625 $DGL 0,102 + 626 626 000FE EF4B br $?L0023 ;[INF] 2, 3 + 627 627 00100 ??eb0E_int_iic_ctr: + 628 628 ; line 167 : } + 629 629 ; line 168 : } + 630 630 00100 ??eb0C_int_iic_ctr: + 631 631 00100 ?L0032: + 632 632 ; line 169 : else + 633 633 ; line 170 : { + 634 634 00100 ??bb0F_int_iic_ctr: + 635 635 ; line 171 : state = IIC_RX; // データ1バイト受信の割り込みだ + 636 636 ; った + 637 637 $DGL 0,107 + 638 638 00100 RCF000004 mov !?L0003,#04H ; state,4 ;[INF] 4, 1 + 639 639 00104 ??eb0F_int_iic_ctr: + 640 640 ; line 172 : // no break, no return // + 641 641 ; line 173 : } + 642 642 00104 ?L0033: + 643 643 ; line 174 : + 644 644 ; line 175 : default: // バースト R/W でここが何回も呼 + 645 645 ; ばれることになる + 646 646 ; line 176 : if( state == IIC_TX ) + 647 647 $DGL 0,112 + 648 648 00104 R40000003 cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + 649 649 00108 DF0F bnz $?L0036 ;[INF] 2, 4 + 650 650 ; line 177 : { // 送信 + 651 651 0010A ??bb10_int_iic_ctr: + 652 652 ; line 178 : IICA = tx_buf; + 653 653 $DGL 0,114 + 654 654 0010A R8F0300 mov a,!?L0006 ; tx_buf ;[INF] 3, 1 + 655 655 0010D 9F4005 mov !IICA1,a ;[INF] 3, 1 + 656 656 ; line 179 : vreg_ctr_after_read( reg_adrs ); // 読んだらクリア + 657 657 ; などの処理 + 658 658 $DGL 0,115 + 659 659 00110 RD90100 mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + 660 660 00113 F1 clrb a ;[INF] 1, 1 + 661 661 00114 RFD0000 call !_vreg_ctr_after_read ;[INF] 3, 3 + 662 662 00117 ??eb10_int_iic_ctr: + 663 663 ; line 180 : } + 664 664 $DGL 0,116 + 665 665 00117 EF12 br $?L0037 ;[INF] 2, 3 + 666 666 00119 ?L0036: + 667 667 ; line 181 : else + 668 668 ; line 182 : { // 受信 + 669 669 00119 ??bb11_int_iic_ctr: + 670 670 ; line 183 : rx_buf = IICA; + 671 671 $DGL 0,119 + 672 672 00119 8F4005 mov a,!IICA1 ;[INF] 3, 1 + 673 673 0011C 76 mov l,a ;[INF] 1, 1 + 674 674 ; line 184 : vreg_ctr_write( reg_adrs, rx_buf ); + 675 675 $DGL 0,120 + 676 676 0011D 17 movw ax,hl ;[INF] 1, 1 + 677 677 0011E F1 clrb a ;[INF] 1, 1 + 678 678 0011F C1 push ax ;[INF] 1, 1 + 679 679 00120 RD90100 mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + 680 680 00123 RFD0000 call !_vreg_ctr_write ;[INF] 3, 3 + 681 681 00126 C0 pop ax ;[INF] 1, 1 + 682 682 ; line 185 : WREL = 1; + 683 683 $DGL 0,121 + 684 684 00127 71505005 set1 !IICCTL01.5 ;[INF] 4, 2 + 685 685 0012B ??eb11_int_iic_ctr: + 686 686 ; line 186 : } + 687 687 0012B ?L0037: + 688 688 ; line 187 : // + 689 689 ; line 188 : if( ( reg_adrs != VREG_C_ACC_HOSU_HIST ) + 690 690 ; line 189 : && ( reg_adrs != VREG_C_INFO ) ) + 691 691 $DGL 0,125 + 692 692 0012B R4001004F cmp !?L0004,#04FH ; reg_adrs,79 ;[INF] 4, 1 + 693 693 0012F DD09 bz $?L0038 ;[INF] 2, 4 + 694 694 00131 R4001007F cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1 + 695 695 00135 61E8 skz ;[INF] 2, 1 + 696 696 ; line 190 : { // この二つのレジスタは特殊なアクセス方法をする。アク + 697 697 ; セスポインタを進めない。 + 698 698 00137 ??bb12_int_iic_ctr: + 699 699 ; line 191 : reg_adrs += 1; + 700 700 $DGL 0,127 + 701 701 00137 RA00100 inc !?L0004 ; reg_adrs ;[INF] 3, 2 + 702 702 0013A ??eb12_int_iic_ctr: + 703 703 ; line 192 : } + 704 704 0013A ?L0038: + 705 705 ; line 193 : + 706 706 ; line 194 : if( state == IIC_TX ) + 707 707 $DGL 0,130 + 708 708 0013A R40000003 cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + 709 709 0013E DF0B bnz $?L0023 ;[INF] 2, 4 + 710 710 ; line 195 : { // さらにつぎに送るデータの準備だ + 711 711 ; けシテオク。SPが来て使われないかもしれない + 712 712 00140 ??bb13_int_iic_ctr: + 713 713 ; line 196 : tx_buf = vreg_ctr_read( reg_adrs ); + 714 714 $DGL 0,132 + 715 715 00140 RD90100 mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + 716 716 00143 F1 clrb a ;[INF] 1, 1 + 717 717 00144 RFD0000 call !_vreg_ctr_read ;[INF] 3, 3 + 718 718 00147 62 mov a,c ;[INF] 1, 1 + 719 719 00148 R9F0300 mov !?L0006,a ; tx_buf ;[INF] 3, 1 + 720 720 0014B ??eb13_int_iic_ctr: + 721 721 ; line 197 : } + 722 722 ; line 198 : break; + 723 723 0014B ??eb09_int_iic_ctr: + 724 724 ; line 199 : } + 725 725 0014B ?L0023: + 726 726 ; line 200 : } + 727 727 $DGL 0,136 + 728 728 0014B ??ef_int_iic_ctr: + 729 729 0014B C0 pop ax ;[INF] 1, 1 + 730 730 0014C 9EFC mov CS,a ;[INF] 2, 1 + 731 731 0014E 60 mov a,x ;[INF] 1, 1 + 732 732 0014F 9EFD mov ES,a ;[INF] 2, 1 + 733 733 00151 R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 734 734 00154 5206 mov c,#06H ;[INF] 2, 1 + 735 735 00156 C0 pop ax ;[INF] 1, 1 + 736 736 00157 B9 movw [de],ax ;[INF] 1, 1 + 737 737 00158 A5 incw de ;[INF] 1, 1 + 738 738 00159 A5 incw de ;[INF] 1, 1 + 739 739 0015A 92 dec c ;[INF] 1, 1 + 740 740 0015B DFF9 bnz $$-5 ;[INF] 2, 4 + 741 741 0015D C6 pop hl ;[INF] 1, 1 + 742 742 0015E C4 pop de ;[INF] 1, 1 + 743 743 0015F C2 pop bc ;[INF] 1, 1 + 744 744 00160 C0 pop ax ;[INF] 1, 1 + 745 745 00161 61FC reti ;[INF] 2, 6 + 746 746 00163 ??ee_int_iic_ctr: + 747 747 ; line 201 : + 748 748 ; line 202 : + 749 749 ; line 203 : + 750 750 ; line 204 : // ======================================================== + 751 751 ; line 205 : void IIC_ctr_Init( void ) + 752 752 ; line 206 : { + 753 753 + 754 754 ----- ROM_CODE CSEG BASE + 755 755 00000 _IIC_ctr_Init: + 756 756 $DGL 1,112 + 757 757 00000 ??bf_IIC_ctr_Init: + 758 758 ; line 207 : + 759 759 ; line 208 : IICAEN = 1; + 760 760 $DGL 0,3 + 761 761 00000 71000105 set1 !PER3.0 ;[INF] 4, 2 + 762 762 ; line 209 : + 763 763 ; line 210 : IICE = 0; /* IICA disable */ + 764 764 $DGL 0,5 + 765 765 00004 71785005 clr1 !IICCTL01.7 ;[INF] 4, 2 + 766 766 ; line 211 : + 767 767 ; line 212 : IICAMK = 1; /* INTIICA disable */ + 768 768 $DGL 0,7 + 769 769 00008 713AD5 set1 MK2H.3 ;[INF] 3, 2 + 770 770 ; line 213 : IICAIF = 0; /* clear INTIICA interrupt flag + 771 771 ; */ + 772 772 $DGL 0,8 + 773 773 0000B 713BD1 clr1 IF2H.3 ;[INF] 3, 2 + 774 774 ; line 214 : + 775 775 ; line 215 : IICAPR0 = 1; /* set INTIICA high priority */ + 776 776 $DGL 0,10 + 777 777 0000E 713ADD set1 PR12H.3 ;[INF] 3, 2 + 778 778 ; line 216 : IICAPR1 = 0; /* set INTIICA high priority */ + 779 779 $DGL 0,11 + 780 780 00011 713BD9 clr1 PR02H.3 ;[INF] 3, 2 + 781 781 ; line 217 : + 782 782 ; line 218 : #ifdef _MODEL_TEG2_ + 783 783 ; line 219 : P6 &= ~0x3; + 784 784 ; line 220 : #else + 785 785 ; line 221 : P20 &= ~0x3; + 786 786 $DGL 0,16 + 787 787 00014 8F1005 mov a,!P20 ;[INF] 3, 1 + 788 788 00017 5CFC and a,#0FCH ; 252 ;[INF] 2, 1 + 789 789 00019 9F1005 mov !P20,a ;[INF] 3, 1 + 790 790 ; line 222 : #endif + 791 791 ; line 223 : + 792 792 ; line 224 : SVA = IIC_C_SLAVEADDRESS; + 793 793 $DGL 0,19 + 794 794 0001C CF54054A mov !SVA1,#04AH ; 74 ;[INF] 4, 1 + 795 795 ; line 225 : IICF = 0x01; + 796 796 $DGL 0,20 + 797 797 00020 E54205 oneb !IICF1 ;[INF] 3, 1 + 798 798 ; line 226 : + 799 799 ; line 227 : STCEN = 1; // リスタートの許可 + 800 800 $DGL 0,22 + 801 801 00023 71104205 set1 !IICF1.1 ;[INF] 4, 2 + 802 802 ; line 228 : IICRSV = 1; // 通信予約をさせない:スレーブに + 803 803 ; 徹する + 804 804 $DGL 0,23 + 805 805 00027 71004205 set1 !IICF1.0 ;[INF] 4, 2 + 806 806 ; line 229 : + 807 807 ; line 230 : SPIE = 0; // ストップコンディションでの割り + 808 808 ; 込みを禁止 + 809 809 $DGL 0,25 + 810 810 0002B 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 + 811 811 ; line 231 : WTIM = 1; // 自動でACKを返した後clkをLに固 + 812 812 ; 定する + 813 813 $DGL 0,26 + 814 814 0002F 71305005 set1 !IICCTL01.3 ;[INF] 4, 2 + 815 815 ; line 232 : ACKE = 1; // ダメCPUは無視して次の通信をは + 816 816 ; じめるかもしれないんで早くclkを開放しないといけない + 817 817 $DGL 0,27 + 818 818 00033 71205005 set1 !IICCTL01.2 ;[INF] 4, 2 + 819 819 ; line 233 : + 820 820 ; line 234 : IICWH = 5; + 821 821 $DGL 0,29 + 822 822 00037 CF530505 mov !IICWH1,#05H ; 5 ;[INF] 4, 1 + 823 823 ; line 235 : IICWL = 10; // L期間の長さ + 824 824 $DGL 0,30 + 825 825 0003B CF52050A mov !IICWL1,#0AH ; 10 ;[INF] 4, 1 + 826 826 ; line 236 : + 827 827 ; line 237 : SMC = 1; // 高速モード + 828 828 $DGL 0,32 + 829 829 0003F 71305105 set1 !IICCTL11.3 ;[INF] 4, 2 + 830 830 ; line 238 : DFC = 1; // デジタルフィルタon (@fast mod + 831 831 ; e) + 832 832 $DGL 0,33 + 833 833 00043 71205105 set1 !IICCTL11.2 ;[INF] 4, 2 + 834 834 ; line 239 : + 835 835 ; line 240 : IICAMK = 0; // 割り込みを許可 + 836 836 $DGL 0,35 + 837 837 00047 713BD5 clr1 MK2H.3 ;[INF] 3, 2 + 838 838 ; line 241 : + 839 839 ; line 242 : IICE = 1; + 840 840 $DGL 0,37 + 841 841 0004A 71705005 set1 !IICCTL01.7 ;[INF] 4, 2 + 842 842 ; line 243 : + 843 843 ; line 244 : #ifdef _MODEL_TEG2_ + 844 844 ; line 245 : PM6 &= ~0x3; /* set clock pin for IICA */ + 845 845 ; line 246 : #else + 846 846 ; line 247 : PM20 &= ~0x3; /* set clock pin for IICA */ + 847 847 $DGL 0,42 + 848 848 0004E 8F1105 mov a,!PM20 ;[INF] 3, 1 + 849 849 00051 5CFC and a,#0FCH ; 252 ;[INF] 2, 1 + 850 850 00053 9F1105 mov !PM20,a ;[INF] 3, 1 + 851 851 ; line 248 : #endif + 852 852 ; line 249 : } + 853 853 $DGL 0,44 + 854 854 00056 ??ef_IIC_ctr_Init: + 855 855 00056 D7 ret ;[INF] 1, 6 + 856 856 00057 ??ee_IIC_ctr_Init: + 857 857 ; line 250 : + 858 858 ; line 251 : + 859 859 ; line 252 : + 860 860 ; line 253 : // ======================================================== + 861 861 ; line 254 : void IIC_ctr_Stop( void ) + 862 862 ; line 255 : { + 863 863 00057 _IIC_ctr_Stop: + 864 864 $DGL 1,118 + 865 865 00057 ??bf_IIC_ctr_Stop: + 866 866 ; line 256 : IICE = 0; /* IICA disable */ + 867 867 $DGL 0,2 + 868 868 00057 71785005 clr1 !IICCTL01.7 ;[INF] 4, 2 + 869 869 ; line 257 : IICAEN = 0; + 870 870 $DGL 0,3 + 871 871 0005B 71080105 clr1 !PER3.0 ;[INF] 4, 2 + 872 872 ; line 258 : } + 873 873 $DGL 0,4 + 874 874 0005F ??ef_IIC_ctr_Stop: + 875 875 0005F D7 ret ;[INF] 1, 6 + 876 876 00060 ??ee_IIC_ctr_Stop: + 877 877 + 878 878 ----- @@CODEL CSEG + 879 879 END + 880 880 + 881 881 + 882 882 ; *** Code Information *** + 883 883 ; + 884 884 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c + 885 885 ; + 886 886 ; $FUNC int_iic_ctr(65) + 887 887 ; void=(void) + 888 888 ; CODE SIZE= 355 bytes, CLOCK_SIZE= 278 clocks, STACK_SIZE= 28 bytes + 889 889 ; + 890 890 ; $CALL hosu_read_end(98) + 891 891 ; void=(void) + 892 892 ; + 893 893 ; $CALL rtc_unlock(99) + 894 894 ; void=(void) + 895 895 ; + 896 896 ; $CALL rtc_unlock(110) + 897 897 ; void=(void) + 898 898 ; + 899 899 ; $CALL vreg_ctr_read(138) + 900 900 ; bc=(int:ax) + 901 901 ; + 902 902 ; $CALL vreg_ctr_after_read(179) + 903 903 ; void=(int:ax) + 904 904 ; + 905 905 ; $CALL vreg_ctr_write(184) + 906 906 ; void=(int:ax, int:[sp+4]) + 907 907 ; + 908 908 ; $CALL vreg_ctr_read(196) + 909 909 ; bc=(int:ax) + 910 910 ; + 911 911 ; $FUNC IIC_ctr_Init(206) + 912 912 ; void=(void) + 913 913 ; CODE SIZE= 87 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes + 914 914 ; + 915 915 ; $FUNC IIC_ctr_Stop(255) + 916 916 ; void=(void) + 917 917 ; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 918 918 + 919 919 ; Target chip : uPD79F0104 + 920 920 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00004H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00163H @@BASE +00000 00060H ROM_CODE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/i2c_ctr.rel b/branches/0.10(X3)/i2c_ctr.rel new file mode 100644 index 0000000..889a834 Binary files /dev/null and b/branches/0.10(X3)/i2c_ctr.rel differ diff --git a/branches/0.10(X3)/i2c_mcu.c b/branches/0.10(X3)/i2c_mcu.c new file mode 100644 index 0000000..d78cd9b --- /dev/null +++ b/branches/0.10(X3)/i2c_mcu.c @@ -0,0 +1,734 @@ +/* ======================================================== + 簡易I2C（内蔵ペリフェラル使用）通信 + de JHL 藤田＠開技 + '09 Feb - + ======================================================== */ +#pragma sfr +#pragma di +#pragma ei +#pragma nop +#pragma inline // memcpy()をインライン展開する + +#include "incs.h" +#include "i2c_mcu.h" + + + +// ======================================================== +// レジスタのビット名 +// プリフィックスbだが、一部のビット名がレジスタ名にかぶるため... +// SMR0n +#define bCKS0 ( 1 << 15 ) +#define bCCS0 ( 1 << 14 ) +#define bSTS0 ( 1 << 8 ) +#define bSIS0 ( 1 << 6 ) +#define bMD0n2 ( 1 << 2 ) +#define bMD0n1 ( 1 << 1 ) +#define bMD0n0 ( 1 << 0 ) +#define bSMR0n_FIXEDBIT ( 1 << 5 ) + +// SSR0n +#define bit_TSF0 6 +#define PEF0 ( 1 << 1 ) + +// SIR0n +#define PECT0 ( 1 << 1 ) + +// SCR0n +#define TXE0 ( 1 << 15 ) +#define RXE0 ( 1 << 14 ) +#define SLC02 4 +#define DLS02 0 +#define TSF0 ( 1 << 6 ) + +// SOn +#define TAUS_MASK 0b0000101100001011; + +// DMCn +#define DRS ( 1 << 6 ) + + + + +// ======================================================== +static void iic_mcu_send_st( ); +static void iic_mcu_send_re_st( ); +static void iic_mcu_send_sp( ); +static err iic_mcu_send_a_byte( u8 ); +static err iic_mcu_call_slave( u8 slave ); + + + +// ======================================================== +bit iic_mcu_wo_dma; +volatile bit iic_mcu_busy; +volatile bit iic_mcu_initialized; + + +u8 iic_send_work[4]; +u8 *p_iic_send_wo_dma_dat; +u8 iic_send_wo_dma_len; + +u8 iic_mcu_bus_status; // 一文字リードの時はデータを返す。 + // ステータスが必要ならこっちを呼んで + +void nop8() +{ +} + + + +/* ======================================================== + スレーブからの 『1文字』 リード + 返値がデータそのものです。 + エラー判定ができません。 + ======================================================== */ +u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs ) +{ + u8 dat; + + if( iic_mcu_initialized == 0 ) + { +#ifdef _debug_ + iic_mcu_start( ); +#else + while( 1 ) + { + } +#endif + } + + while( iic_mcu_busy ) + { + NOP( ); + } + iic_mcu_busy = 1; + + iic_mcu_bus_status = ERR_OK; + + // スタートコンディションとスレーブの呼び出し、レジスタアドレスの送信 + if( iic_mcu_call_slave( SLA ) != 0 ) + { + iic_mcu_bus_status = ERR_NOSLAVE; + iic_mcu_busy = 0; + return ( 0 ); + } + + // レジスタアドレスの送信 + iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない + // if( err != ERR_SUCCESS )〜 + + // データ受信 // + iic_mcu_send_re_st( ); // リスタートコンディション + iic_mcu_send_a_byte( SLA | 0x01 ); // 送信完了まで戻ってきません。 + + ST0 = 0x0004; // 受信モードに設定を変えるのでロジック停止 + SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 + SS0 = 0x0004; // 通信待機 + + SOE0 = 0x0000; // 1バイト送信なので、最後のNAKを送る + IICIF10 = 0; + SIO10 = 0xFF; // ダミーデータを書くと受信開始 + + while( IICIF10 == 0 ) + { // 受信完了待ち + ; + } + dat = SIO10; + + iic_mcu_send_sp( ); + IICIF10 = 0; // 後を濁さないこと + iic_mcu_busy = 0; + return ( dat ); +} + + + +/* ======================================================== + スレーブからのリード + 0 正常終了 + 1 スレーブが応答しない + 2 バスが誰かに占有されていてタイムアウト + 3 意味不明エラー + 【注】 + スレーブがウェイトコンディションを出すことは禁止です。 + その場合でもエラー検出などできません + ======================================================== */ +err iic_mcu_read( u8 slave, u8 adrs, u8 len, u8 * dest ) +{ + +//* + // 使用中なら待つ + if( iic_mcu_initialized == 0 ) + { +#ifdef _debug_ + iic_mcu_start( ); +#else + while( 1 ) + { + } +#endif + } + while( iic_mcu_busy ) + { + NOP( ); + } +/*/ + // 使用中なら帰る + if( iic_mcu_initialized == 0 ){ + return(0x80); + } + if( iic_mcu_busy != 0 ){ + return( 3 ); + } +//*/ + + iic_mcu_busy = 1; + // スタートコンディションとスレーブの呼び出し、レジスタアドレスの送信 + if( iic_mcu_call_slave( slave ) != 0 ) + { + iic_mcu_busy = 0; + return ( ERR_NOSLAVE ); + } + + // レジスタアドレスの送信 + iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない + // if( err != ERR_SUCCESS )〜 + + // データ受信 // + iic_mcu_send_re_st( ); // リスタートコンディション + iic_mcu_send_a_byte( slave | 0x01 ); // 送信完了まで戻ってきません。 + + // データ受信 + ST0 = 0x0004; // 受信モードに設定を変えるのでロジック停止 + SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 + SS0 = 0x0004; // 通信待機 + + do + { + if( len == 1 ) + { + SOE0 = 0x0000; // 最後のNAK + } + IICIF10 = 0; + SIO10 = 0xFF; // ダミーデータを書くと受信開始 + while( IICIF10 == 0 ) + { // 受信完了待ち + ; + } + *dest = SIO10; + dest++; + len--; + } + while( len != 0 ); + + iic_mcu_send_sp( ); + + IICIF10 = 0; + iic_mcu_busy = 0; + return ( ERR_SUCCESS ); +} + + + + +/* ======================================================== + スレーブへ 『１バイト』 ライト + 前の転送が終わるのを待って、ライトします。 + 返値　iic_mcu_write　に同じ + + ======================================================== */ +err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat ) +{ + + if( iic_mcu_initialized == 0 ) + { +#ifdef _debug_ + iic_mcu_start( ); +#else + while( 1 ) + { + } +#endif + } + while( iic_mcu_busy ) + { + NOP( ); + } + iic_mcu_busy = 1; +#if 0 + temp = dat; + return ( iic_mcu_write( SLA, adrs, 1, &temp ) ); +} +#else + // スタートコンディションとスレーブの呼び出し... + IICMK10 = 1; + if( iic_mcu_call_slave( SLA ) != 0 ) + { + iic_mcu_busy = 0; + return ( ERR_NAK ); + } + iic_mcu_send_a_byte( adrs ); + iic_mcu_send_a_byte( dat ); + iic_mcu_send_sp( ); + iic_mcu_busy = 0; + return ( ERR_SUCCESS ); +#endif +} + + + +/* ======================================================== + スレーブへライト + レジスタ adrs を先頭に、 + *strから + len文字書きます。 + + 0 正常終了 + 1 スレーブが応答しない + 2 バスが誰かに占有されていてタイムアウト + 3 前に指示された通信がまだ終わってない + 【注】 + スレーブがウェイトコンディションを出すことは禁止です。 + その場合でもエラー検出などできません + DMA1を使用します。 + ******************************************************************************/ +err iic_mcu_write( u8 slave, u8 adrs, u8 len, void * src ) +{ +//* + // 使用中なら待つ + if( iic_mcu_initialized == 0 ) + { +#ifdef _debug_ + iic_mcu_start( ); +#else + while( 1 ) + { + } +#endif + } + while( iic_mcu_busy ) + { + NOP( ); + } +/*/ + // 使用中なら帰る + if( iic_mcu_initialized == 0 ){ + return(0x80); + } + if( iic_mcu_busy != 0 ){ + return( 3 ); + } +//*/ + iic_mcu_busy = 1; + // スタートコンディションとスレーブの呼び出し... + IICMK10 = 1; + IICIF10 = 0; + if( iic_mcu_call_slave( slave ) != 0 ) + { + iic_mcu_busy = 0; + EI( ); + return ( ERR_NAK ); + } + + IICIF10 = 0; + if( !iic_mcu_wo_dma ) + { + // DMAを使用する（通常） + + // レジスタアドレスを送り、データの準備 + memcpy( iic_send_work, src, 4 ); //バッファとして4バイトしか用意して無いため。 + // DMAセット + while( DST1 ) + {; + } + + DEN1 = 1; + DSA1 = ( u8 ) ( &SIO10 ); + DRA1 = ( u16 ) iic_send_work; + DBC1 = len; + DMC1 = DRS | 8; // RAM -> SFR, 8bit, IRQ, IIC10 + + DMAIF1 = 0; + DMAMK1 = 0; + DST1 = 1; + + SIO10 = adrs; // 書きっぱなし！ 割り込みが発生してDMAスタート + // 残りは割り込みルーチン内で + } + else + { + // DMAを使用しない // + + // レジスタアドレスの送信 + SIO10 = adrs; + + IICMK10 = 0; + iic_send_wo_dma_len = len; + p_iic_send_wo_dma_dat = src; + // 残りは割り込みルーチン内で + } + return ( ERR_SUCCESS ); +} + + + + +/* ======================================================== + DMA１転送終了割り込み + IIC_mcu の送信完了コールバック関数のようなもの + 注：DMA転送が終わっただけで、I2Cの転送は終わってません +　 割り込み中などで、DMA1の処理が遅延した場合、 + IIC10の割り込みの準備ができずに、割り込みを発生させられなくなる + 恐れがあります。また、回避方法も特にありません。 + 　そのため、DMA仕様の差異は、最後のバイトは送信完了を + フラグのポーリングで確認します。 + ======================================================== */ +__interrupt void int_dma1( ) +{ + u16 i = 0; + + EI(); + + DMAMK1 = 1; + DEN1 = 0; + while( ( SSR02L & TSF0 ) != 0 ) + { + if( ++i == 0 ) // タイムアウト？ + { + break; + } + } + +// iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪いので展開 + { + ST0 = 0x0004; + SOE0 = 0; // 受信の時はもっと前に「も」設定してる。(NACK出力) + SO0 = 0x0000 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0400 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0404 | TAUS_MASK; + } + IICMK10 = 1; + iic_mcu_busy = 0; +} + + + +/* ======================================================== + IIC MCUのバイト送出完了割り込み + ※DMA使用時は使用されません。 + 　他の割り込み処理中でDMAの割り込みにすぐ飛ばない場合、 + 　IIC割り込みのセットが間に合わず困ることがあります。 + ======================================================== */ +__interrupt void int_iic10( ) +{ + EI(); + if( iic_send_wo_dma_len != 0 ) + { + SIO10 = *p_iic_send_wo_dma_dat; + p_iic_send_wo_dma_dat++; + iic_send_wo_dma_len--; + return; + } + + // 最後のバイト送信完了 + IICMK10 = 1; +// iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪いので展開 + { + ST0 = 0x0004; + SOE0 = 0; // 受信の時はもっと前に「も」設定してる。(NACK出力) + SO0 = 0x0000 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0400 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0404 | TAUS_MASK; + } + iic_mcu_wo_dma = 0; + iic_mcu_busy = 0; +} + + + +/* ======================================================== + スレーブの呼び出し +　スレーブアドレスを呼んで、ACKの確認。 + ACK　→　　　　　　　　　　　　　　　　　返：0 +　NACK →　ストップコンディションを出す。　返：1 + ======================================================== */ +static err iic_mcu_call_slave( u8 slave ) +{ + iic_mcu_send_st( ); + +// SIR02 = SSR02; // NAKエラーのフラグクリア + if( iic_mcu_send_a_byte( slave ) != ERR_SUCCESS ) + { + iic_mcu_send_sp( ); + return ( ERR_NAK ); // 指定のスレーブがいない / busy + } + + return ( ERR_SUCCESS ); +} + + + +/* ======================================================== + ほんとに１バイト書くのみ + 書き終わるまで帰りません + ======================================================== */ +static err iic_mcu_send_a_byte( u8 dat ) +{ + IICMK10 = 1; + IICIF10 = 0; + SIO10 = dat; + while( IICIF10 == 0 ) + { + NOP( ); + } // 通信中 + if( SSR02 != 0 ) + { + SIR02 = SSR02; + return ( ERR_NAK ); + } + return ( ERR_SUCCESS ); +} + + + +/* ======================================================== + スタートコンディションを発行 + ソフトウェア制御 + ======================================================== */ +static void iic_mcu_send_st( ) +{ + SO0 &= ~0x0004; // SDA + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 &= ~0x0400; // SCL + SOE0 = 0x0004; // ハード制御へ + + SCR02 = TXE0 | 1 << SLC02 | 7 << DLS02; // 送信許可、データは８ビット単位 + SS0 = 0x0004; // 通信待機 +} + + + +/* ======================================================== + リスタート発行 + ======================================================== */ +static void iic_mcu_send_re_st( ) +{ + ST0 |= 0x0004; + SO0 |= 0x0400 | TAUS_MASK; // ( SDA = H ), SCL -> H + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SOE0 &= ~0x0004; // ( SCL = H ), SDA -> L + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + iic_mcu_send_st( ); +} + + + +/* ======================================================== + ストップコンディション発行 + この前に、「最後のバイトの送受信」の時に前準備が必要です。 + ======================================================== */ +static void iic_mcu_send_sp( ) +{ + ST0 = 0x0004; + SOE0 = 0; // 受信の時はもっと前に「も」設定してる。(NACK出力) + SO0 = 0x0000 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0400 | TAUS_MASK; // SCL + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SO0 = 0x0404 | TAUS_MASK; +} + + + + +/* ======================================================== + ペリフェラルモジュールの初期化 + ======================================================== */ +void iic_mcu_start( ) +{ + DST1 = 0; + NOP( ); // 2clkもしくは、DSTn==0をポーリング + NOP( ); + DEN1 = 0; + I2C_PU_on(); + SAU0EN = 1; + nop8(); +/* + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#ifdef _OVERCLOCK_ + NOP( ); + NOP( ); + NOP( ); + NOP( ); + NOP( ); +#endif +*/ + SPS0 = 0x0000; // シリアルユニットのクロック０。(8M/2)/1 + SMR02 = bSMR0n_FIXEDBIT | bMD0n2; // 簡易I2Cに設定 +#ifdef _OVERCLOCK_ + SDR02 = 12 << 9; // ボーレート設定 (8M/2)/1/(x+1)/2 +#else + SDR02 = 5 << 9; // ボーレート設定 (8M/2)/1/(x+1)/2 +#endif + + SO0 = 0x0404 | TAUS_MASK; // 最初はHH + iic_mcu_busy = 0; + iic_mcu_wo_dma = 0; + + + // バスのリセット + IICIF10 = 0; + IICMK10 = 1; + + iic_mcu_send_st(); + + SIO10 = 0xFF; + while( IICIF10 == 0 ){} // 通信中 + iic_mcu_send_sp(); + + SIR02 = SSR02; + + iic_mcu_initialized = 1; +} + + + +/* ======================================================== + モジュールの停止 + 再度使うときは初期化が必要 + ======================================================== */ +void iic_mcu_stop( ) +{ + while( iic_mcu_busy ) + {; + } // DMA動作中はもう少し待つ + iic_mcu_send_re_st( ); // SCL,SDAをLLにする + I2C_PU_off(); + SAU0EN = 0; + iic_mcu_initialized = 0; +} diff --git a/branches/0.10(X3)/i2c_mcu.h b/branches/0.10(X3)/i2c_mcu.h new file mode 100644 index 0000000..6cd1072 --- /dev/null +++ b/branches/0.10(X3)/i2c_mcu.h @@ -0,0 +1,34 @@ +#ifndef __ic2_mcu__ +#define __ic2_mcu__ + + +// ======================================================== +#define ERR_OK 0 +#define ERR_NAK 1 +#define ERR_NOSLAVE 2 + + + +// ======================================================== +extern volatile bit iic_mcu_busy; +extern bit iic_mcu_wo_dma; + +extern u8 iic_mcu_bus_status; + + + +// ======================================================== +err iic_mcu_read( u8 SLA, u8 adrs, u8 len, u8 * dest ); +u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs ); + +err iic_mcu_write( u8 SLA, u8 adrs, u8 len, void * src ); +err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat ); + +// ↓その通信が完了したら解除されます。 +#define iic_mcu_set_wo_dma() { while( iic_mcu_busy ){;} iic_mcu_wo_dma = 1; } + +void iic_mcu_start( ); +void iic_mcu_stop( ); + + +#endif diff --git a/branches/0.10(X3)/i2c_mcu.prn b/branches/0.10(X3)/i2c_mcu.prn new file mode 100644 index 0000000..61bbdda --- /dev/null +++ b/branches/0.10(X3)/i2c_mcu.prn @@ -0,0 +1,2215 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\i2c_mcu.asm +Para-file: +In-file: inter_asm\i2c_mcu.asm +Obj-file: i2c_mcu.rel +Prn-file: i2c_mcu.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_mcu.c + 6 6 ; In-file : i2c_mcu.c + 7 7 ; Asm-file : inter_asm\i2c_mcu.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0100H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, i2c_mcu.c + 18 18 $DGS MOD_NAM, i2c_mcu, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS LAB_SYM, bs_F0085, U, U, 00H, 06H, 00H, 00H + 36 36 $DGS LAB_SYM, es_F0085, U, U, 00H, 06H, 00H, 00H + 37 37 $DGS LAB_SYM, bs_S0086, U, U, 00H, 06H, 00H, 00H + 38 38 $DGS LAB_SYM, es_S0086, U, U, 00H, 06H, 00H, 00H + 39 39 $DGS LAB_SYM, bs_S0087, U, U, 00H, 06H, 00H, 00H + 40 40 $DGS LAB_SYM, es_S0087, U, U, 00H, 06H, 00H, 00H + 41 41 $DGS LAB_SYM, bs_F0084, U, U, 00H, 06H, 00H, 00H + 42 42 $DGS LAB_SYM, es_F0084, U, U, 00H, 06H, 00H, 00H + 43 43 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 44 44 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 45 45 $DGS GLV_SYM, _nop8, U, U, 01H, 026H, 01H, 02H + 46 46 $DGS AUX_FUN, 00H, U, U, 023H, 00H, 00H + 47 47 $DGS BEG_FUN, ??bf_nop8, U, U, 00H, 065H, 01H, 00H + 48 48 $DGS AUX_BEG, 04CH, 00H, 023H + 49 49 $DGS END_FUN, ??ef_nop8, U, U, 00H, 065H, 01H, 00H + 50 50 $DGS AUX_END, 02H + 51 51 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 026H, 01H, 02H + 52 52 $DGS AUX_FUN, 00H, U, U, 03CH, 00H, 00H + 53 53 $DGS BEG_FUN, ??bf_iic_mcu_read_a_byte, U, U, 00H, 065H, 01H, 00H + 54 54 $DGS AUX_BEG, 057H, 04H, 02AH + 55 55 $DGS FUN_ARG, _SLA, 02H, 0FFFFH, 0CH, 09H, 00H, 00H + 56 56 $DGS FUN_ARG, _adrs, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H + 57 57 $DGS AUT_VAR, _dat, 01H, 0FFFFH, 0CH, 01H, 00H, 00H + 58 58 $DGS BEG_BLK, ??bb00_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 59 59 $DGS AUX_BEG, 05H, 00H, 02EH + 60 60 $DGS END_BLK, ??eb00_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 61 61 $DGS AUX_END, 0DH + 62 62 $DGS BEG_BLK, ??bb01_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 63 63 $DGS AUX_BEG, 010H, 00H, 032H + 64 64 $DGS END_BLK, ??eb01_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 65 65 $DGS AUX_END, 012H + 66 66 $DGS BEG_BLK, ??bb02_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 67 67 $DGS AUX_BEG, 019H, 00H, 036H + 68 68 $DGS END_BLK, ??eb02_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 69 69 $DGS AUX_END, 01DH + 70 70 $DGS BEG_BLK, ??bb03_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 71 71 $DGS AUX_BEG, 030H, 00H, 00H + 72 72 $DGS END_BLK, ??eb03_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H + 73 73 $DGS AUX_END, 032H + 74 74 $DGS END_FUN, ??ef_iic_mcu_read_a_byte, U, U, 00H, 065H, 01H, 00H + 75 75 $DGS AUX_END, 039H + 76 76 $DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 026H, 01H, 02H + 77 77 $DGS AUX_FUN, 00H, U, U, 05FH, 00H, 00H + 78 78 $DGS BEG_FUN, ??bf_iic_mcu_read, U, U, 00H, 065H, 01H, 00H + 79 79 $DGS AUX_BEG, 09EH, 02H, 045H + 80 80 $DGS FUN_ARG, _slave, 00H, 0FFFFH, 0CH, 09H, 00H, 00H + 81 81 $DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H + 82 82 $DGS FUN_ARG, _len, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H + 83 83 $DGS FUN_ARG, _dest, 0CH, 0FFFFH, 0CH, 09H, 01H, 01H + 84 84 $DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H + 85 85 $DGS BEG_BLK, ??bb00_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 86 86 $DGS AUX_BEG, 06H, 00H, 049H + 87 87 $DGS END_BLK, ??eb00_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_END, 0EH + 89 89 $DGS BEG_BLK, ??bb01_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_BEG, 010H, 00H, 04DH + 91 91 $DGS END_BLK, ??eb01_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_END, 012H + 93 93 $DGS BEG_BLK, ??bb02_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_BEG, 020H, 00H, 051H + 95 95 $DGS END_BLK, ??eb02_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_END, 023H + 97 97 $DGS BEG_BLK, ??bb03_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_BEG, 033H, 00H, 053H + 99 99 $DGS BEG_BLK, ??bb04_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_BEG, 035H, 00H, 057H + 101 101 $DGS END_BLK, ??eb04_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_END, 037H + 103 103 $DGS BEG_BLK, ??bb05_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_BEG, 03BH, 00H, 00H + 105 105 $DGS END_BLK, ??eb05_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_END, 03DH + 107 107 $DGS END_BLK, ??eb03_iic_mcu_read, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_END, 041H + 109 109 $DGS END_FUN, ??ef_iic_mcu_read, U, U, 00H, 065H, 01H, 00H + 110 110 $DGS AUX_END, 049H + 111 111 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 026H, 01H, 02H + 112 112 $DGS AUX_FUN, 00H, U, U, 074H, 00H, 00H + 113 113 $DGS BEG_FUN, ??bf_iic_mcu_write_a_byte, U, U, 00H, 065H, 01H, 00H + 114 114 $DGS AUX_BEG, 0F2H, 02H, 066H + 115 115 $DGS FUN_ARG, _SLA, 00H, 0FFFFH, 0CH, 09H, 00H, 00H + 116 116 $DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H + 117 117 $DGS FUN_ARG, _dat, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H + 118 118 $DGS BEG_BLK, ??bb00_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 119 119 $DGS AUX_BEG, 04H, 00H, 06AH + 120 120 $DGS END_BLK, ??eb00_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_END, 0CH + 122 122 $DGS BEG_BLK, ??bb01_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 123 123 $DGS AUX_BEG, 0EH, 00H, 06EH + 124 124 $DGS END_BLK, ??eb01_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 125 125 $DGS AUX_END, 010H + 126 126 $DGS BEG_BLK, ??bb02_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 127 127 $DGS AUX_BEG, 01AH, 00H, 00H + 128 128 $DGS END_BLK, ??eb02_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H + 129 129 $DGS AUX_END, 01DH + 130 130 $DGS END_FUN, ??ef_iic_mcu_write_a_byte, U, U, 00H, 065H, 01H, 00H + 131 131 $DGS AUX_END, 024H + 132 132 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 026H, 01H, 02H + 133 133 $DGS AUX_FUN, 00H, U, U, 097H, 00H, 00H + 134 134 $DGS BEG_FUN, ??bf_iic_mcu_write, U, U, 00H, 065H, 01H, 00H + 135 135 $DGS AUX_BEG, 0129H, 02H, 07DH + 136 136 $DGS FUN_ARG, _slave, 00H, 0FFFFH, 0CH, 09H, 00H, 00H + 137 137 $DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H + 138 138 $DGS FUN_ARG, _len, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H + 139 139 $DGS FUN_ARG, _src, 0CH, 0FFFFH, 01H, 09H, 01H, 01H + 140 140 $DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H + 141 141 $DGS BEG_BLK, ??bb00_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_BEG, 05H, 00H, 081H + 143 143 $DGS END_BLK, ??eb00_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 144 144 $DGS AUX_END, 0DH + 145 145 $DGS BEG_BLK, ??bb01_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 146 146 $DGS AUX_BEG, 0FH, 00H, 085H + 147 147 $DGS END_BLK, ??eb01_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 148 148 $DGS AUX_END, 011H + 149 149 $DGS BEG_BLK, ??bb02_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_BEG, 020H, 00H, 089H + 151 151 $DGS END_BLK, ??eb02_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 152 152 $DGS AUX_END, 024H + 153 153 $DGS BEG_BLK, ??bb03_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_BEG, 028H, 00H, 08BH + 155 155 $DGS BEG_BLK, ??bb04_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_BEG, 02FH, 00H, 091H + 157 157 $DGS END_BLK, ??eb04_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_END, 030H + 159 159 $DGS END_BLK, ??eb03_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_END, 03EH + 161 161 $DGS BEG_BLK, ??bb05_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 162 162 $DGS AUX_BEG, 040H, 00H, 00H + 163 163 $DGS END_BLK, ??eb05_iic_mcu_write, U, U, 00H, 064H, 01H, 00H + 164 164 $DGS AUX_END, 04AH + 165 165 $DGS END_FUN, ??ef_iic_mcu_write, U, U, 00H, 065H, 01H, 00H + 166 166 $DGS AUX_END, 04CH + 167 167 $DGS GLV_SYM, _int_dma1, U, U, 0E001H, 026H, 01H, 02H + 168 168 $DGS AUX_FUN, 00H, U, U, 0AAH, 00H, 00H + 169 169 $DGS BEG_FUN, ??bf_int_dma1, U, U, 00H, 065H, 01H, 00H + 170 170 $DGS AUX_BEG, 0184H, 016H, 09CH + 171 171 $DGS REG_VAR, _i, 0103H, 0FFFFH, 010DH, 04H, 00H, 00H + 172 172 $DGS BEG_BLK, ??bb00_int_dma1, U, U, 00H, 064H, 01H, 00H + 173 173 $DGS AUX_BEG, 09H, 00H, 09EH + 174 174 $DGS BEG_BLK, ??bb01_int_dma1, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_BEG, 0BH, 00H, 0A4H + 176 176 $DGS END_BLK, ??eb01_int_dma1, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_END, 0DH + 178 178 $DGS END_BLK, ??eb00_int_dma1, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_END, 0EH + 180 180 $DGS BEG_BLK, ??bb02_int_dma1, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_BEG, 011H, 00H, 00H + 182 182 $DGS END_BLK, ??eb02_int_dma1, U, U, 00H, 064H, 01H, 00H + 183 183 $DGS AUX_END, 033H + 184 184 $DGS END_FUN, ??ef_int_dma1, U, U, 00H, 065H, 01H, 00H + 185 185 $DGS AUX_END, 036H + 186 186 $DGS GLV_SYM, _int_iic10, U, U, 0E001H, 026H, 01H, 02H + 187 187 $DGS AUX_FUN, 00H, U, U, 0B8H, 00H, 00H + 188 188 $DGS BEG_FUN, ??bf_int_iic10, U, U, 00H, 065H, 01H, 00H + 189 189 $DGS AUX_BEG, 01C4H, 016H, 0AEH + 190 190 $DGS BEG_BLK, ??bb00_int_iic10, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_BEG, 04H, 00H, 0B2H + 192 192 $DGS END_BLK, ??eb00_int_iic10, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_END, 09H + 194 194 $DGS BEG_BLK, ??bb01_int_iic10, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_BEG, 0EH, 00H, 00H + 196 196 $DGS END_BLK, ??eb01_int_iic10, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_END, 030H + 198 198 $DGS END_FUN, ??ef_int_iic10, U, U, 00H, 065H, 01H, 00H + 199 199 $DGS AUX_END, 033H + 200 200 $DGS STA_SYM, _iic_mcu_call_slave, U, U, 0CH, 03H, 01H, 02H + 201 201 $DGS AUX_FUN, 00H, U, U, 0C3H, 00H, 00H + 202 202 $DGS BEG_FUN, ??bf_iic_mcu_call_slave, U, U, 00H, 065H, 01H, 00H + 203 203 $DGS AUX_BEG, 0201H, 02H, 0BDH + 204 204 $DGS REG_PAR, _slave, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 205 205 $DGS BEG_BLK, ??bb00_iic_mcu_call_slave, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_BEG, 06H, 00H, 00H + 207 207 $DGS END_BLK, ??eb00_iic_mcu_call_slave, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_END, 09H + 209 209 $DGS END_FUN, ??ef_iic_mcu_call_slave, U, U, 00H, 065H, 01H, 00H + 210 210 $DGS AUX_END, 0CH + 211 211 $DGS STA_SYM, _iic_mcu_send_a_byte, U, U, 0CH, 03H, 01H, 02H + 212 212 $DGS AUX_FUN, 00H, U, U, 0D2H, 00H, 00H + 213 213 $DGS BEG_FUN, ??bf_iic_mcu_send_a_byte, U, U, 00H, 065H, 01H, 00H + 214 214 $DGS AUX_BEG, 0215H, 02H, 0C8H + 215 215 $DGS REG_PAR, _dat, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 216 216 $DGS BEG_BLK, ??bb00_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H + 217 217 $DGS AUX_BEG, 06H, 00H, 0CCH + 218 218 $DGS END_BLK, ??eb00_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H + 219 219 $DGS AUX_END, 08H + 220 220 $DGS BEG_BLK, ??bb01_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H + 221 221 $DGS AUX_BEG, 0AH, 00H, 00H + 222 222 $DGS END_BLK, ??eb01_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H + 223 223 $DGS AUX_END, 0DH + 224 224 $DGS END_FUN, ??ef_iic_mcu_send_a_byte, U, U, 00H, 065H, 01H, 00H + 225 225 $DGS AUX_END, 0FH + 226 226 $DGS STA_SYM, _iic_mcu_send_st, U, U, 01H, 03H, 01H, 02H + 227 227 $DGS AUX_FUN, 00H, U, U, 0D8H, 00H, 00H + 228 228 $DGS BEG_FUN, ??bf_iic_mcu_send_st, U, U, 00H, 065H, 01H, 00H + 229 229 $DGS AUX_BEG, 022CH, 00H, 0D8H + 230 230 $DGS END_FUN, ??ef_iic_mcu_send_st, U, U, 00H, 065H, 01H, 00H + 231 231 $DGS AUX_END, 016H + 232 232 $DGS STA_SYM, _iic_mcu_send_re_st, U, U, 01H, 03H, 01H, 02H + 233 233 $DGS AUX_FUN, 00H, U, U, 0DEH, 00H, 00H + 234 234 $DGS BEG_FUN, ??bf_iic_mcu_send_re_st, U, U, 00H, 065H, 01H, 00H + 235 235 $DGS AUX_BEG, 0249H, 00H, 0DEH + 236 236 $DGS END_FUN, ??ef_iic_mcu_send_re_st, U, U, 00H, 065H, 01H, 00H + 237 237 $DGS AUX_END, 022H + 238 238 $DGS STA_SYM, _iic_mcu_send_sp, U, U, 01H, 03H, 01H, 02H + 239 239 $DGS AUX_FUN, 00H, U, U, 0E4H, 00H, 00H + 240 240 $DGS BEG_FUN, ??bf_iic_mcu_send_sp, U, U, 00H, 065H, 01H, 00H + 241 241 $DGS AUX_BEG, 0273H, 00H, 0E4H + 242 242 $DGS END_FUN, ??ef_iic_mcu_send_sp, U, U, 00H, 065H, 01H, 00H + 243 243 $DGS AUX_END, 023H + 244 244 $DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 026H, 01H, 02H + 245 245 $DGS AUX_FUN, 00H, U, U, 0F2H, 00H, 00H + 246 246 $DGS BEG_FUN, ??bf_iic_mcu_start, U, U, 00H, 065H, 01H, 00H + 247 247 $DGS AUX_BEG, 029EH, 00H, 0E8H + 248 248 $DGS BEG_BLK, ??bb00_iic_mcu_start, U, U, 00H, 064H, 01H, 00H + 249 249 $DGS AUX_BEG, 06H, 00H, 0ECH + 250 250 $DGS END_BLK, ??eb00_iic_mcu_start, U, U, 00H, 064H, 01H, 00H + 251 251 $DGS AUX_END, 06H + 252 252 $DGS BEG_BLK, ??bb01_iic_mcu_start, U, U, 00H, 064H, 01H, 00H + 253 253 $DGS AUX_BEG, 02AH, 00H, 00H + 254 254 $DGS END_BLK, ??eb01_iic_mcu_start, U, U, 00H, 064H, 01H, 00H + 255 255 $DGS AUX_END, 02AH + 256 256 $DGS END_FUN, ??ef_iic_mcu_start, U, U, 00H, 065H, 01H, 00H + 257 257 $DGS AUX_END, 030H + 258 258 $DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 026H, 01H, 02H + 259 259 $DGS AUX_FUN, 00H, U, U, 0100H, 00H, 00H + 260 260 $DGS BEG_FUN, ??bf_iic_mcu_stop, U, U, 00H, 065H, 01H, 00H + 261 261 $DGS AUX_BEG, 02D6H, 00H, 0F6H + 262 262 $DGS BEG_BLK, ??bb00_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H + 263 263 $DGS AUX_BEG, 03H, 00H, 0FAH + 264 264 $DGS END_BLK, ??eb00_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H + 265 265 $DGS AUX_END, 04H + 266 266 $DGS BEG_BLK, ??bb01_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H + 267 267 $DGS AUX_BEG, 06H, 00H, 00H + 268 268 $DGS END_BLK, ??eb01_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H + 269 269 $DGS AUX_END, 06H + 270 270 $DGS END_FUN, ??ef_iic_mcu_stop, U, U, 00H, 065H, 01H, 00H + 271 271 $DGS AUX_END, 09H + 272 272 $DGS GLV_SYM, _iic_mcu_wo_dma, U, U, 034CH, 027H, 00H, 00H + 273 273 $DGS GLV_SYM, _iic_mcu_busy, U, U, 0134CH, 027H, 00H, 00H + 274 274 $DGS GLV_SYM, _iic_mcu_initialized, U, U, 0134CH, 027H, 00H, 00H + 275 275 $DGS GLV_SYM, _iic_send_work, U, U, 0CH, 026H, 01H, 03H + 276 276 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H + 277 277 $DGS GLV_SYM, _p_iic_send_wo_dma_dat, U, U, 0CH, 026H, 01H, 01H + 278 278 $DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H + 279 279 $DGS GLV_SYM, _iic_send_wo_dma_len, U, U, 0CH, 026H, 00H, 00H + 280 280 $DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 026H, 00H, 00H + 281 281 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 282 282 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 283 283 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 284 284 + 285 285 EXTRN _@SEGAX + 286 286 EXTRN _@SEGDE + 287 287 EXTRN _@RTARG0 + 288 288 PUBLIC _iic_mcu_wo_dma + 289 289 PUBLIC _iic_mcu_busy + 290 290 PUBLIC _iic_mcu_initialized + 291 291 PUBLIC _iic_send_work + 292 292 PUBLIC _p_iic_send_wo_dma_dat + 293 293 PUBLIC _iic_send_wo_dma_len + 294 294 PUBLIC _iic_mcu_bus_status + 295 295 PUBLIC _nop8 + 296 296 PUBLIC _iic_mcu_read_a_byte + 297 297 PUBLIC _iic_mcu_read + 298 298 PUBLIC _iic_mcu_write_a_byte + 299 299 PUBLIC _iic_mcu_write + 300 300 PUBLIC _int_dma1 + 301 301 PUBLIC _int_iic10 + 302 302 PUBLIC _iic_mcu_start + 303 303 PUBLIC _iic_mcu_stop + 304 304 + 305 305 ----- @@BITS BSEG + 306 306 00000.0 _iic_mcu_wo_dma DBIT + 307 307 00000.1 _iic_mcu_busy DBIT + 308 308 00000.2 _iic_mcu_initialized DBIT + 309 309 + 310 310 ----- @@CNST CSEG MIRRORP + 311 311 00000 01 _lpf_coeff: DB 01H ; 1 + 312 312 00001 02 DB 02H ; 2 + 313 313 00002 02 DB 02H ; 2 + 314 314 00003 03 DB 03H ; 3 + 315 315 00004 03 DB 03H ; 3 + 316 316 00005 02 DB 02H ; 2 + 317 317 00006 00 DB 00H ; 0 + 318 318 00007 FE DB 0FEH ; 254 + 319 319 00008 FB DB 0FBH ; 251 + 320 320 00009 F7 DB 0F7H ; 247 + 321 321 0000A F3 DB 0F3H ; 243 + 322 322 0000B F0 DB 0F0H ; 240 + 323 323 0000C F0 DB 0F0H ; 240 + 324 324 0000D F3 DB 0F3H ; 243 + 325 325 0000E FA DB 0FAH ; 250 + 326 326 0000F 04 DB 04H ; 4 + 327 327 00010 12 DB 012H ; 18 + 328 328 00011 25 DB 025H ; 37 + 329 329 00012 38 DB 038H ; 56 + 330 330 00013 4D DB 04DH ; 77 + 331 331 00014 5F DB 05FH ; 95 + 332 332 00015 6E DB 06EH ; 110 + 333 333 00016 77 DB 077H ; 119 + 334 334 00017 7A DB 07AH ; 122 + 335 335 00018 77 DB 077H ; 119 + 336 336 00019 6E DB 06EH ; 110 + 337 337 0001A 5F DB 05FH ; 95 + 338 338 0001B 4D DB 04DH ; 77 + 339 339 0001C 38 DB 038H ; 56 + 340 340 0001D 25 DB 025H ; 37 + 341 341 0001E 12 DB 012H ; 18 + 342 342 0001F 04 DB 04H ; 4 + 343 343 00020 FA DB 0FAH ; 250 + 344 344 00021 F3 DB 0F3H ; 243 + 345 345 00022 F0 DB 0F0H ; 240 + 346 346 00023 F0 DB 0F0H ; 240 + 347 347 00024 F3 DB 0F3H ; 243 + 348 348 00025 F7 DB 0F7H ; 247 + 349 349 00026 FB DB 0FBH ; 251 + 350 350 00027 FE DB 0FEH ; 254 + 351 351 00028 00 DB 00H ; 0 + 352 352 00029 02 DB 02H ; 2 + 353 353 0002A 03 DB 03H ; 3 + 354 354 0002B 03 DB 03H ; 3 + 355 355 0002C 02 DB 02H ; 2 + 356 356 0002D 02 DB 02H ; 2 + 357 357 0002E 01 DB 01H ; 1 + 358 358 0002F 00 DB (1) + 359 359 + 360 360 ----- @@R_INIT CSEG UNIT64KP + 361 361 + 362 362 ----- @@INIT DSEG BASEP + 363 363 + 364 364 ----- @@DATA DSEG BASEP + 365 365 00000 _iic_send_work: DS (4) + 366 366 00004 _p_iic_send_wo_dma_dat: DS (2) + 367 367 00006 _iic_send_wo_dma_len: DS (1) + 368 368 00007 _iic_mcu_bus_status: DS (1) + 369 369 + 370 370 ----- @@R_INIS CSEG UNIT64KP + 371 371 + 372 372 ----- @@INIS DSEG SADDRP + 373 373 + 374 374 ----- @@DATS DSEG SADDRP + 375 375 + 376 376 ----- @@CNSTL CSEG PAGE64KP + 377 377 + 378 378 ----- @@RLINIT CSEG UNIT64KP + 379 379 + 380 380 ----- @@INITL DSEG UNIT64KP + 381 381 + 382 382 ----- @@DATAL DSEG UNIT64KP + 383 383 + 384 384 ----- @@CALT CSEG CALLT0 + 385 385 + 386 386 ; Sub-Routines created by CC78K0R + 387 387 + 388 388 ----- ROM_CODE CSEG BASE + 389 389 00000 bs_F0085: + 390 390 00000 318E shrw ax,8 ;[INF] 2, 1 + 391 391 00002 REDC701 br !_iic_mcu_send_a_byte ;[INF] 3, 3 + 392 392 00005 es_F0085: + 393 393 + 394 394 ----- ROM_CODE CSEG BASE + 395 395 00005 bs_S0086: + 396 396 00005 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 397 397 00008 BF2401 movw !ST0,ax ;[INF] 3, 1 + 398 398 0000B D7 ret ;[INF] 1, 6 + 399 399 0000C es_S0086: + 400 400 + 401 401 ----- ROM_CODE CSEG BASE + 402 402 0000C bs_S0087: + 403 403 0000C 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 404 404 0000F BF2201 movw !SS0,ax ;[INF] 3, 1 + 405 405 00012 D7 ret ;[INF] 1, 6 + 406 406 00013 es_S0087: + 407 407 + 408 408 ----- ROM_CODE CSEG BASE + 409 409 00013 bs_F0084: + 410 410 00013 8B mov a,[hl] ;[INF] 1, 1 + 411 411 00014 318E shrw ax,8 ;[INF] 2, 1 + 412 412 00016 RFDB101 call !_iic_mcu_call_slave ;[INF] 3, 3 + 413 413 00019 D2 cmp0 c ;[INF] 1, 1 + 414 414 0001A D7 ret ;[INF] 1, 6 + 415 415 0001B es_F0084: + 416 416 + 417 417 ; *** Sub-Routine Information *** + 418 418 ; + 419 419 ; $SUB bs_F0084 + 420 420 ; CODE SIZE= 8 bytes + 421 421 ; + 422 422 ; $SUB bs_F0085 + 423 423 ; CODE SIZE= 5 bytes + 424 424 ; + 425 425 ; $SUB bs_S0086 + 426 426 ; CODE SIZE= 7 bytes + 427 427 ; + 428 428 ; $SUB bs_S0087 + 429 429 ; CODE SIZE= 7 bytes + 430 430 + 431 431 ; End of Sub-Routines + 432 432 + 433 433 ; line 1 : /* ======================================================== + 434 434 ; line 2 : 簡易I2C（内蔵ペリフェラル使用）通信 + 435 435 ; line 3 : de JHL 藤田＠開技 + 436 436 ; line 4 : '09 Feb - + 437 437 ; line 5 : ======================================================== */ + 438 438 ; line 6 : #pragma sfr + 439 439 ; line 7 : #pragma di + 440 440 ; line 8 : #pragma ei + 441 441 ; line 9 : #pragma nop + 442 442 ; line 10 : #pragma inline // memcpy()をインライン展開する + 443 443 ; line 11 : + 444 444 ; line 12 : #include "incs.h" + 445 445 ; line 13 : #include "i2c_mcu.h" + 446 446 ; line 14 : + 447 447 ; line 15 : + 448 448 ; line 16 : + 449 449 ; line 17 : // ======================================================== + 450 450 ; line 18 : // レジスタのビット名 + 451 451 ; line 19 : // プリフィックスbだが、一部のビット名がレジスタ名にかぶるため.. + 452 452 ; . + 453 453 ; line 20 : // SMR0n + 454 454 ; line 21 : #define bCKS0 ( 1 << 15 ) + 455 455 ; line 22 : #define bCCS0 ( 1 << 14 ) + 456 456 ; line 23 : #define bSTS0 ( 1 << 8 ) + 457 457 ; line 24 : #define bSIS0 ( 1 << 6 ) + 458 458 ; line 25 : #define bMD0n2 ( 1 << 2 ) + 459 459 ; line 26 : #define bMD0n1 ( 1 << 1 ) + 460 460 ; line 27 : #define bMD0n0 ( 1 << 0 ) + 461 461 ; line 28 : #define bSMR0n_FIXEDBIT ( 1 << 5 ) + 462 462 ; line 29 : + 463 463 ; line 30 : // SSR0n + 464 464 ; line 31 : #define bit_TSF0 6 + 465 465 ; line 32 : #define PEF0 ( 1 << 1 ) + 466 466 ; line 33 : + 467 467 ; line 34 : // SIR0n + 468 468 ; line 35 : #define PECT0 ( 1 << 1 ) + 469 469 ; line 36 : + 470 470 ; line 37 : // SCR0n + 471 471 ; line 38 : #define TXE0 ( 1 << 15 ) + 472 472 ; line 39 : #define RXE0 ( 1 << 14 ) + 473 473 ; line 40 : #define SLC02 4 + 474 474 ; line 41 : #define DLS02 0 + 475 475 ; line 42 : #define TSF0 ( 1 << 6 ) + 476 476 ; line 43 : + 477 477 ; line 44 : // SOn + 478 478 ; line 45 : #define TAUS_MASK 0b0000101100001011; + 479 479 ; line 46 : + 480 480 ; line 47 : // DMCn + 481 481 ; line 48 : #define DRS ( 1 << 6 ) + 482 482 ; line 49 : + 483 483 ; line 50 : + 484 484 ; line 51 : + 485 485 ; line 52 : + 486 486 ; line 53 : // ======================================================== + 487 487 ; line 54 : static void iic_mcu_send_st( ); + 488 488 ; line 55 : static void iic_mcu_send_re_st( ); + 489 489 ; line 56 : static void iic_mcu_send_sp( ); + 490 490 ; line 57 : static err iic_mcu_send_a_byte( u8 ); + 491 491 ; line 58 : static err iic_mcu_call_slave( u8 slave ); + 492 492 ; line 59 : + 493 493 ; line 60 : + 494 494 ; line 61 : + 495 495 ; line 62 : // ======================================================== + 496 496 ; line 63 : bit iic_mcu_wo_dma; + 497 497 ; line 64 : volatile bit iic_mcu_busy; + 498 498 ; line 65 : volatile bit iic_mcu_initialized; + 499 499 ; line 66 : + 500 500 ; line 67 : + 501 501 ; line 68 : u8 iic_send_work[4]; + 502 502 ; line 69 : u8 *p_iic_send_wo_dma_dat; + 503 503 ; line 70 : u8 iic_send_wo_dma_len; + 504 504 ; line 71 : + 505 505 ; line 72 : u8 iic_mcu_bus_status; // 一文字リードの時はデータを返す + 506 506 ; 。 + 507 507 ; line 73 : // ステータスが必要ならこっちを呼 + 508 508 ; んで + 509 509 ; line 74 : + 510 510 ; line 75 : void nop8() + 511 511 ; line 76 : { + 512 512 + 513 513 ----- ROM_CODE CSEG BASE + 514 514 0001B _nop8: + 515 515 $DGL 1,29 + 516 516 0001B ??bf_nop8: + 517 517 ; line 77 : } + 518 518 $DGL 0,2 + 519 519 0001B ??ef_nop8: + 520 520 0001B D7 ret ;[INF] 1, 6 + 521 521 0001C ??ee_nop8: + 522 522 ; line 78 : + 523 523 ; line 79 : + 524 524 ; line 80 : + 525 525 ; line 81 : /* ======================================================== + 526 526 ; line 82 : スレーブからの 『1文字』 リード + 527 527 ; line 83 : 返値がデータそのものです。 + 528 528 ; line 84 : エラー判定ができません。 + 529 529 ; line 85 : ======================================================== */ + 530 530 ; line 86 : u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs ) + 531 531 ; line 87 : { + 532 532 0001C _iic_mcu_read_a_byte: + 533 533 $DGL 1,35 + 534 534 0001C C7 push hl ;[INF] 1, 1 + 535 535 0001D C1 push ax ;[INF] 1, 1 + 536 536 0001E C1 push ax ;[INF] 1, 1 + 537 537 0001F FBF8FF movw hl,sp ;[INF] 3, 1 + 538 538 00022 ??bf_iic_mcu_read_a_byte: + 539 539 ; line 88 : u8 dat; + 540 540 ; line 89 : + 541 541 ; line 90 : if( iic_mcu_initialized == 0 ) + 542 542 $DGL 0,4 + 543 543 00022 R31220003 bt _iic_mcu_initialized,$?L0005 ;[INF] 4, 5 + 544 544 ; line 91 : { + 545 545 00026 ??bb00_iic_mcu_read_a_byte: + 546 546 ; line 92 : #ifdef _debug_ + 547 547 ; line 93 : iic_mcu_start( ); + 548 548 $DGL 0,7 + 549 549 00026 RFD5902 call !_iic_mcu_start ;[INF] 3, 3 + 550 550 00029 ??eb00_iic_mcu_read_a_byte: + 551 551 ; line 94 : #else + 552 552 ; line 95 : while( 1 ) + 553 553 ; line 96 : { + 554 554 ; line 97 : } + 555 555 ; line 98 : #endif + 556 556 ; line 99 : } + 557 557 00029 ?L0005: + 558 558 ; line 100 : + 559 559 ; line 101 : while( iic_mcu_busy ) + 560 560 $DGL 0,15 + 561 561 00029 R31140003 bf _iic_mcu_busy,$?L0008 ;[INF] 4, 5 + 562 562 ; line 102 : { + 563 563 0002D ??bb01_iic_mcu_read_a_byte: + 564 564 ; line 103 : NOP( ); + 565 565 $DGL 0,17 + 566 566 0002D 00 nop ;[INF] 1, 1 + 567 567 0002E ??eb01_iic_mcu_read_a_byte: + 568 568 ; line 104 : } + 569 569 $DGL 0,18 + 570 570 0002E EFF9 br $?L0005 ;[INF] 2, 3 + 571 571 00030 ?L0008: + 572 572 ; line 105 : iic_mcu_busy = 1; + 573 573 $DGL 0,19 + 574 574 00030 R711200 set1 _iic_mcu_busy ;[INF] 3, 2 + 575 575 ; line 106 : + 576 576 ; line 107 : iic_mcu_bus_status = ERR_OK; + 577 577 $DGL 0,21 + 578 578 00033 RF50700 clrb !_iic_mcu_bus_status ;[INF] 3, 1 + 579 579 ; line 108 : + 580 580 ; line 109 : // スタートコンディションとスレーブの呼び出し、レジスタアドレ + 581 581 ; スの送信 + 582 582 ; line 110 : if( iic_mcu_call_slave( SLA ) != 0 ) + 583 583 $DGL 0,24 + 584 584 00036 8C02 mov a,[hl+2] ; SLA ;[INF] 2, 1 + 585 585 00038 318E shrw ax,8 ;[INF] 2, 1 + 586 586 0003A RFDB101 call !_iic_mcu_call_slave ;[INF] 3, 3 + 587 587 0003D D2 cmp0 c ;[INF] 1, 1 + 588 588 0003E DD0A bz $?L0009 ;[INF] 2, 4 + 589 589 ; line 111 : { + 590 590 00040 ??bb02_iic_mcu_read_a_byte: + 591 591 ; line 112 : iic_mcu_bus_status = ERR_NOSLAVE; + 592 592 $DGL 0,26 + 593 593 00040 RCF070002 mov !_iic_mcu_bus_status,#02H ; 2 ;[INF] 4, 1 + 594 594 ; line 113 : iic_mcu_busy = 0; + 595 595 $DGL 0,27 + 596 596 00044 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 597 597 ; line 114 : return ( 0 ); + 598 598 $DGL 0,28 + 599 599 00047 F7 clrw bc ;[INF] 1, 1 + 600 600 00048 EF3D br $?L0004 ;[INF] 2, 3 + 601 601 0004A ??eb02_iic_mcu_read_a_byte: + 602 602 ; line 115 : } + 603 603 0004A ?L0009: + 604 604 ; line 116 : + 605 605 ; line 117 : // レジスタアドレスの送信 + 606 606 ; line 118 : iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない + 607 607 $DGL 0,32 + 608 608 0004A 8C0A mov a,[hl+10] ; adrs ;[INF] 2, 1 + 609 609 0004C RFD0000 call !bs_F0085 ;[INF] 3, 3 + 610 610 ; line 119 : // if( err != ERR_SUCCESS )〜 + 611 611 ; line 120 : + 612 612 ; line 121 : // データ受信 // + 613 613 ; line 122 : iic_mcu_send_re_st( ); // リスタートコンディション + 614 614 $DGL 0,36 + 615 615 0004F RFD1002 call !_iic_mcu_send_re_st ;[INF] 3, 3 + 616 616 ; line 123 : iic_mcu_send_a_byte( SLA | 0x01 ); // 送信完了まで戻ってきま + 617 617 ; せん。 + 618 618 $DGL 0,37 + 619 619 00052 8C02 mov a,[hl+2] ; SLA ;[INF] 2, 1 + 620 620 00054 6C01 or a,#01H ; 1 ;[INF] 2, 1 + 621 621 00056 RFD0000 call !bs_F0085 ;[INF] 3, 3 + 622 622 ; line 124 : + 623 623 ; line 125 : ST0 = 0x0004; // 受信モードに設定を変えるのでロ + 624 624 ; ジック停止 + 625 625 $DGL 0,39 + 626 626 00059 RFD0500 call !bs_S0086 ;[INF] 3, 3 + 627 627 ; line 126 : SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 + 628 628 $DGL 0,40 + 629 629 0005C 301740 movw ax,#04017H ; 16407 ;[INF] 3, 1 + 630 630 0005F BF1C01 movw !SCR02,ax ;[INF] 3, 1 + 631 631 ; line 127 : SS0 = 0x0004; // 通信待機 + 632 632 $DGL 0,41 + 633 633 00062 RFD0C00 call !bs_S0087 ;[INF] 3, 3 + 634 634 ; line 128 : + 635 635 ; line 129 : SOE0 = 0x0000; // 1バイト送信なので、最後のNAKを + 636 636 ; 送る + 637 637 $DGL 0,43 + 638 638 00065 F6 clrw ax ;[INF] 1, 1 + 639 639 00066 BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 640 640 ; line 130 : IICIF10 = 0; + 641 641 $DGL 0,44 + 642 642 00069 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 643 643 ; line 131 : SIO10 = 0xFF; // ダミーデータを書くと受信開始 + 644 644 $DGL 0,45 + 645 645 0006C CE44FF mov SIO10,#0FFH ; 255 ;[INF] 3, 1 + 646 646 ; line 132 : + 647 647 ; line 133 : while( IICIF10 == 0 ) + 648 648 $DGL 0,47 + 649 649 0006F ?L0011: + 650 650 0006F 3182E202 bt IF1L.0,$?L0012 ;[INF] 4, 5 + 651 651 ; line 134 : { // 受信完了待ち + 652 652 00073 ??bb03_iic_mcu_read_a_byte: + 653 653 ; line 135 : ; + 654 654 00073 ??eb03_iic_mcu_read_a_byte: + 655 655 ; line 136 : } + 656 656 $DGL 0,50 + 657 657 00073 EFFA br $?L0011 ;[INF] 2, 3 + 658 658 00075 ?L0012: + 659 659 ; line 137 : dat = SIO10; + 660 660 $DGL 0,51 + 661 661 00075 8E44 mov a,SIO10 ;[INF] 2, 1 + 662 662 00077 9C01 mov [hl+1],a ; dat ;[INF] 2, 1 + 663 663 ; line 138 : + 664 664 ; line 139 : iic_mcu_send_sp( ); + 665 665 $DGL 0,53 + 666 666 00079 RFD3902 call !_iic_mcu_send_sp ;[INF] 3, 3 + 667 667 ; line 140 : IICIF10 = 0; // 後を濁さないこと + 668 668 $DGL 0,54 + 669 669 0007C 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 670 670 ; line 141 : iic_mcu_busy = 0; + 671 671 $DGL 0,55 + 672 672 0007F R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 673 673 ; line 142 : return ( dat ); + 674 674 $DGL 0,56 + 675 675 00082 8C01 mov a,[hl+1] ; dat ;[INF] 2, 1 + 676 676 00084 318E shrw ax,8 ;[INF] 2, 1 + 677 677 00086 12 movw bc,ax ;[INF] 1, 1 + 678 678 ; line 143 : } + 679 679 00087 ?L0004: + 680 680 $DGL 0,57 + 681 681 00087 ??ef_iic_mcu_read_a_byte: + 682 682 00087 1004 addw sp,#04H ;[INF] 2, 1 + 683 683 00089 C6 pop hl ;[INF] 1, 1 + 684 684 0008A D7 ret ;[INF] 1, 6 + 685 685 0008B ??ee_iic_mcu_read_a_byte: + 686 686 ; line 144 : + 687 687 ; line 145 : + 688 688 ; line 146 : + 689 689 ; line 147 : /* ======================================================== + 690 690 ; line 148 : スレーブからのリード + 691 691 ; line 149 : 0 正常終了 + 692 692 ; line 150 : 1 スレーブが応答しない + 693 693 ; line 151 : 2 バスが誰かに占有されていてタイムアウト + 694 694 ; line 152 : 3 意味不明エラー + 695 695 ; line 153 : 【注】 + 696 696 ; line 154 : スレーブがウェイトコンディションを出すことは禁止です。 + 697 697 ; line 155 : その場合でもエラー検出などできません + 698 698 ; line 156 : ======================================================== */ + 699 699 ; line 157 : err iic_mcu_read( u8 slave, u8 adrs, u8 len, u8 * dest ) + 700 700 ; line 158 : { + 701 701 0008B _iic_mcu_read: + 702 702 $DGL 1,60 + 703 703 0008B C7 push hl ;[INF] 1, 1 + 704 704 0008C C1 push ax ;[INF] 1, 1 + 705 705 0008D FBF8FF movw hl,sp ;[INF] 3, 1 + 706 706 00090 ??bf_iic_mcu_read: + 707 707 ; line 159 : + 708 708 ; line 160 : //* + 709 709 ; line 161 : // 使用中なら待つ + 710 710 ; line 162 : if( iic_mcu_initialized == 0 ) + 711 711 $DGL 0,5 + 712 712 00090 R31220003 bt _iic_mcu_initialized,$?L0015 ;[INF] 4, 5 + 713 713 ; line 163 : { + 714 714 00094 ??bb00_iic_mcu_read: + 715 715 ; line 164 : #ifdef _debug_ + 716 716 ; line 165 : iic_mcu_start( ); + 717 717 $DGL 0,8 + 718 718 00094 RFD5902 call !_iic_mcu_start ;[INF] 3, 3 + 719 719 00097 ??eb00_iic_mcu_read: + 720 720 ; line 166 : #else + 721 721 ; line 167 : while( 1 ) + 722 722 ; line 168 : { + 723 723 ; line 169 : } + 724 724 ; line 170 : #endif + 725 725 ; line 171 : } + 726 726 00097 ?L0015: + 727 727 ; line 172 : while( iic_mcu_busy ) + 728 728 $DGL 0,15 + 729 729 00097 R31140003 bf _iic_mcu_busy,$?L0018 ;[INF] 4, 5 + 730 730 ; line 173 : { + 731 731 0009B ??bb01_iic_mcu_read: + 732 732 ; line 174 : NOP( ); + 733 733 $DGL 0,17 + 734 734 0009B 00 nop ;[INF] 1, 1 + 735 735 0009C ??eb01_iic_mcu_read: + 736 736 ; line 175 : } + 737 737 $DGL 0,18 + 738 738 0009C EFF9 br $?L0015 ;[INF] 2, 3 + 739 739 0009E ?L0018: + 740 740 ; line 176 : /*/ + 741 741 ; line 177 : // 使用中なら帰る + 742 742 ; line 178 : if( iic_mcu_initialized == 0 ){ + 743 743 ; line 179 : return(0x80); + 744 744 ; line 180 : } + 745 745 ; line 181 : if( iic_mcu_busy != 0 ){ + 746 746 ; line 182 : return( 3 ); + 747 747 ; line 183 : } + 748 748 ; line 184 : //*/ + 749 749 ; line 185 : + 750 750 ; line 186 : iic_mcu_busy = 1; + 751 751 $DGL 0,29 + 752 752 0009E R711200 set1 _iic_mcu_busy ;[INF] 3, 2 + 753 753 ; line 187 : // スタートコンディションとスレーブの呼び出し、レジスタアドレ + 754 754 ; スの送信 + 755 755 ; line 188 : if( iic_mcu_call_slave( slave ) != 0 ) + 756 756 $DGL 0,31 + 757 757 000A1 RFD1300 call !bs_F0084 ;[INF] 3, 3 + 758 758 000A4 DD07 bz $?L0019 ;[INF] 2, 4 + 759 759 ; line 189 : { + 760 760 000A6 ??bb02_iic_mcu_read: + 761 761 ; line 190 : iic_mcu_busy = 0; + 762 762 $DGL 0,33 + 763 763 000A6 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 764 764 ; line 191 : return ( ERR_NOSLAVE ); + 765 765 $DGL 0,34 + 766 766 000A9 E7 onew bc ;[INF] 1, 1 + 767 767 000AA A3 incw bc ;[INF] 1, 1 + 768 768 000AB EF4A br $?L0014 ;[INF] 2, 3 + 769 769 000AD ??eb02_iic_mcu_read: + 770 770 ; line 192 : } + 771 771 000AD ?L0019: + 772 772 ; line 193 : + 773 773 ; line 194 : // レジスタアドレスの送信 + 774 774 ; line 195 : iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない + 775 775 $DGL 0,38 + 776 776 000AD 8C08 mov a,[hl+8] ; adrs ;[INF] 2, 1 + 777 777 000AF RFD0000 call !bs_F0085 ;[INF] 3, 3 + 778 778 ; line 196 : // if( err != ERR_SUCCESS )〜 + 779 779 ; line 197 : + 780 780 ; line 198 : // データ受信 // + 781 781 ; line 199 : iic_mcu_send_re_st( ); // リスタートコンディション + 782 782 $DGL 0,42 + 783 783 000B2 RFD1002 call !_iic_mcu_send_re_st ;[INF] 3, 3 + 784 784 ; line 200 : iic_mcu_send_a_byte( slave | 0x01 ); // 送信完了まで戻 + 785 785 ; ってきません。 + 786 786 $DGL 0,43 + 787 787 000B5 8B mov a,[hl] ; slave ;[INF] 1, 1 + 788 788 000B6 6C01 or a,#01H ; 1 ;[INF] 2, 1 + 789 789 000B8 RFD0000 call !bs_F0085 ;[INF] 3, 3 + 790 790 ; line 201 : + 791 791 ; line 202 : // データ受信 + 792 792 ; line 203 : ST0 = 0x0004; // 受信モードに設定を変えるのでロ + 793 793 ; ジック停止 + 794 794 $DGL 0,46 + 795 795 000BB RFD0500 call !bs_S0086 ;[INF] 3, 3 + 796 796 ; line 204 : SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 + 797 797 $DGL 0,47 + 798 798 000BE 301740 movw ax,#04017H ; 16407 ;[INF] 3, 1 + 799 799 000C1 BF1C01 movw !SCR02,ax ;[INF] 3, 1 + 800 800 ; line 205 : SS0 = 0x0004; // 通信待機 + 801 801 $DGL 0,48 + 802 802 000C4 RFD0C00 call !bs_S0087 ;[INF] 3, 3 + 803 803 ; line 206 : + 804 804 ; line 207 : do + 805 805 000C7 ?L0021: + 806 806 ; line 208 : { + 807 807 000C7 ??bb03_iic_mcu_read: + 808 808 ; line 209 : if( len == 1 ) + 809 809 $DGL 0,52 + 810 810 000C7 8C0A mov a,[hl+10] ; len ;[INF] 2, 1 + 811 811 000C9 91 dec a ;[INF] 1, 1 + 812 812 000CA DF04 bnz $?L0024 ;[INF] 2, 4 + 813 813 ; line 210 : { + 814 814 000CC ??bb04_iic_mcu_read: + 815 815 ; line 211 : SOE0 = 0x0000; // 最後のNAK + 816 816 $DGL 0,54 + 817 817 000CC F6 clrw ax ;[INF] 1, 1 + 818 818 000CD BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 819 819 000D0 ??eb04_iic_mcu_read: + 820 820 ; line 212 : } + 821 821 000D0 ?L0024: + 822 822 ; line 213 : IICIF10 = 0; + 823 823 $DGL 0,56 + 824 824 000D0 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 825 825 ; line 214 : SIO10 = 0xFF; // ダミーデータを書くと受信開始 + 826 826 $DGL 0,57 + 827 827 000D3 CE44FF mov SIO10,#0FFH ; 255 ;[INF] 3, 1 + 828 828 ; line 215 : while( IICIF10 == 0 ) + 829 829 $DGL 0,58 + 830 830 000D6 ?L0026: + 831 831 000D6 3182E202 bt IF1L.0,$?L0027 ;[INF] 4, 5 + 832 832 ; line 216 : { // 受信完了待ち + 833 833 000DA ??bb05_iic_mcu_read: + 834 834 ; line 217 : ; + 835 835 000DA ??eb05_iic_mcu_read: + 836 836 ; line 218 : } + 837 837 $DGL 0,61 + 838 838 000DA EFFA br $?L0026 ;[INF] 2, 3 + 839 839 000DC ?L0027: + 840 840 ; line 219 : *dest = SIO10; + 841 841 $DGL 0,62 + 842 842 000DC AC0C movw ax,[hl+12] ; dest ;[INF] 2, 1 + 843 843 000DE 14 movw de,ax ;[INF] 1, 1 + 844 844 000DF 8E44 mov a,SIO10 ;[INF] 2, 1 + 845 845 000E1 99 mov [de],a ;[INF] 1, 1 + 846 846 ; line 220 : dest++; + 847 847 $DGL 0,63 + 848 848 000E2 61790C incw [hl+12] ; dest ;[INF] 3, 2 + 849 849 ; line 221 : len--; + 850 850 $DGL 0,64 + 851 851 000E5 61690A dec [hl+10] ; len ;[INF] 3, 2 + 852 852 000E8 ??eb03_iic_mcu_read: + 853 853 ; line 222 : } + 854 854 ; line 223 : while( len != 0 ); + 855 855 $DGL 0,66 + 856 856 000E8 8C0A mov a,[hl+10] ; len ;[INF] 2, 1 + 857 857 000EA D1 cmp0 a ;[INF] 1, 1 + 858 858 000EB DFDA bnz $?L0021 ;[INF] 2, 4 + 859 859 ; line 224 : + 860 860 ; line 225 : iic_mcu_send_sp( ); + 861 861 $DGL 0,68 + 862 862 000ED RFD3902 call !_iic_mcu_send_sp ;[INF] 3, 3 + 863 863 ; line 226 : + 864 864 ; line 227 : IICIF10 = 0; + 865 865 $DGL 0,70 + 866 866 000F0 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 867 867 ; line 228 : iic_mcu_busy = 0; + 868 868 $DGL 0,71 + 869 869 000F3 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 870 870 ; line 229 : return ( ERR_SUCCESS ); + 871 871 $DGL 0,72 + 872 872 000F6 F7 clrw bc ;[INF] 1, 1 + 873 873 ; line 230 : } + 874 874 000F7 ?L0014: + 875 875 $DGL 0,73 + 876 876 000F7 ??ef_iic_mcu_read: + 877 877 000F7 C0 pop ax ;[INF] 1, 1 + 878 878 000F8 C6 pop hl ;[INF] 1, 1 + 879 879 000F9 D7 ret ;[INF] 1, 6 + 880 880 000FA ??ee_iic_mcu_read: + 881 881 ; line 231 : + 882 882 ; line 232 : + 883 883 ; line 233 : + 884 884 ; line 234 : + 885 885 ; line 235 : /* ======================================================== + 886 886 ; line 236 : スレーブへ 『１バイト』 ライト + 887 887 ; line 237 : 前の転送が終わるのを待って、ライトします。 + 888 888 ; line 238 : 返値　iic_mcu_write　に同じ + 889 889 ; line 239 : + 890 890 ; line 240 : ======================================================== */ + 891 891 ; line 241 : err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat ) + 892 892 ; line 242 : { + 893 893 000FA _iic_mcu_write_a_byte: + 894 894 $DGL 1,95 + 895 895 000FA C7 push hl ;[INF] 1, 1 + 896 896 000FB C1 push ax ;[INF] 1, 1 + 897 897 000FC FBF8FF movw hl,sp ;[INF] 3, 1 + 898 898 000FF ??bf_iic_mcu_write_a_byte: + 899 899 ; line 243 : + 900 900 ; line 244 : if( iic_mcu_initialized == 0 ) + 901 901 $DGL 0,3 + 902 902 000FF R31220003 bt _iic_mcu_initialized,$?L0030 ;[INF] 4, 5 + 903 903 ; line 245 : { + 904 904 00103 ??bb00_iic_mcu_write_a_byte: + 905 905 ; line 246 : #ifdef _debug_ + 906 906 ; line 247 : iic_mcu_start( ); + 907 907 $DGL 0,6 + 908 908 00103 RFD5902 call !_iic_mcu_start ;[INF] 3, 3 + 909 909 00106 ??eb00_iic_mcu_write_a_byte: + 910 910 ; line 248 : #else + 911 911 ; line 249 : while( 1 ) + 912 912 ; line 250 : { + 913 913 ; line 251 : } + 914 914 ; line 252 : #endif + 915 915 ; line 253 : } + 916 916 00106 ?L0030: + 917 917 ; line 254 : while( iic_mcu_busy ) + 918 918 $DGL 0,13 + 919 919 00106 R31140003 bf _iic_mcu_busy,$?L0033 ;[INF] 4, 5 + 920 920 ; line 255 : { + 921 921 0010A ??bb01_iic_mcu_write_a_byte: + 922 922 ; line 256 : NOP( ); + 923 923 $DGL 0,15 + 924 924 0010A 00 nop ;[INF] 1, 1 + 925 925 0010B ??eb01_iic_mcu_write_a_byte: + 926 926 ; line 257 : } + 927 927 $DGL 0,16 + 928 928 0010B EFF9 br $?L0030 ;[INF] 2, 3 + 929 929 0010D ?L0033: + 930 930 ; line 258 : iic_mcu_busy = 1; + 931 931 $DGL 0,17 + 932 932 0010D R711200 set1 _iic_mcu_busy ;[INF] 3, 2 + 933 933 ; line 259 : #if 0 + 934 934 ; line 260 : temp = dat; + 935 935 ; line 261 : return ( iic_mcu_write( SLA, adrs, 1, &temp ) ); + 936 936 ; line 262 : } + 937 937 ; line 263 : #else + 938 938 ; line 264 : // スタートコンディションとスレーブの呼び出し... + 939 939 ; line 265 : IICMK10 = 1; + 940 940 $DGL 0,24 + 941 941 00110 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 942 942 ; line 266 : if( iic_mcu_call_slave( SLA ) != 0 ) + 943 943 $DGL 0,25 + 944 944 00113 RFD1300 call !bs_F0084 ;[INF] 3, 3 + 945 945 00116 DD06 bz $?L0034 ;[INF] 2, 4 + 946 946 ; line 267 : { + 947 947 00118 ??bb02_iic_mcu_write_a_byte: + 948 948 ; line 268 : iic_mcu_busy = 0; + 949 949 $DGL 0,27 + 950 950 00118 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 951 951 ; line 269 : return ( ERR_NAK ); + 952 952 $DGL 0,28 + 953 953 0011B E7 onew bc ;[INF] 1, 1 + 954 954 0011C EF11 br $?L0029 ;[INF] 2, 3 + 955 955 0011E ??eb02_iic_mcu_write_a_byte: + 956 956 ; line 270 : } + 957 957 0011E ?L0034: + 958 958 ; line 271 : iic_mcu_send_a_byte( adrs ); + 959 959 $DGL 0,30 + 960 960 0011E 8C08 mov a,[hl+8] ; adrs ;[INF] 2, 1 + 961 961 00120 RFD0000 call !bs_F0085 ;[INF] 3, 3 + 962 962 ; line 272 : iic_mcu_send_a_byte( dat ); + 963 963 $DGL 0,31 + 964 964 00123 8C0A mov a,[hl+10] ; dat ;[INF] 2, 1 + 965 965 00125 RFD0000 call !bs_F0085 ;[INF] 3, 3 + 966 966 ; line 273 : iic_mcu_send_sp( ); + 967 967 $DGL 0,32 + 968 968 00128 RFD3902 call !_iic_mcu_send_sp ;[INF] 3, 3 + 969 969 ; line 274 : iic_mcu_busy = 0; + 970 970 $DGL 0,33 + 971 971 0012B R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 972 972 ; line 275 : return ( ERR_SUCCESS ); + 973 973 $DGL 0,34 + 974 974 0012E F7 clrw bc ;[INF] 1, 1 + 975 975 ; line 276 : #endif + 976 976 ; line 277 : } + 977 977 0012F ?L0029: + 978 978 $DGL 0,36 + 979 979 0012F ??ef_iic_mcu_write_a_byte: + 980 980 0012F C0 pop ax ;[INF] 1, 1 + 981 981 00130 C6 pop hl ;[INF] 1, 1 + 982 982 00131 D7 ret ;[INF] 1, 6 + 983 983 00132 ??ee_iic_mcu_write_a_byte: + 984 984 ; line 278 : + 985 985 ; line 279 : + 986 986 ; line 280 : + 987 987 ; line 281 : /* ======================================================== + 988 988 ; line 282 : スレーブへライト + 989 989 ; line 283 : レジスタ adrs を先頭に、 + 990 990 ; line 284 : *strから + 991 991 ; line 285 : len文字書きます。 + 992 992 ; line 286 : + 993 993 ; line 287 : 0 正常終了 + 994 994 ; line 288 : 1 スレーブが応答しない + 995 995 ; line 289 : 2 バスが誰かに占有されていてタイムアウト + 996 996 ; line 290 : 3 前に指示された通信がまだ終わってない + 997 997 ; line 291 : 【注】 + 998 998 ; line 292 : スレーブがウェイトコンディションを出すことは禁止です。 + 999 999 ; line 293 : その場合でもエラー検出などできません + 1000 1000 ; line 294 : DMA1を使用します。 + 1001 1001 ; line 295 : *************************************************************** + 1002 1002 ; ***************/ + 1003 1003 ; line 296 : err iic_mcu_write( u8 slave, u8 adrs, u8 len, void * src ) + 1004 1004 ; line 297 : { + 1005 1005 00132 _iic_mcu_write: + 1006 1006 $DGL 1,116 + 1007 1007 00132 C7 push hl ;[INF] 1, 1 + 1008 1008 00133 C1 push ax ;[INF] 1, 1 + 1009 1009 00134 FBF8FF movw hl,sp ;[INF] 3, 1 + 1010 1010 00137 ??bf_iic_mcu_write: + 1011 1011 ; line 298 : //* + 1012 1012 ; line 299 : // 使用中なら待つ + 1013 1013 ; line 300 : if( iic_mcu_initialized == 0 ) + 1014 1014 $DGL 0,4 + 1015 1015 00137 R31220003 bt _iic_mcu_initialized,$?L0038 ;[INF] 4, 5 + 1016 1016 ; line 301 : { + 1017 1017 0013B ??bb00_iic_mcu_write: + 1018 1018 ; line 302 : #ifdef _debug_ + 1019 1019 ; line 303 : iic_mcu_start( ); + 1020 1020 $DGL 0,7 + 1021 1021 0013B RFD5902 call !_iic_mcu_start ;[INF] 3, 3 + 1022 1022 0013E ??eb00_iic_mcu_write: + 1023 1023 ; line 304 : #else + 1024 1024 ; line 305 : while( 1 ) + 1025 1025 ; line 306 : { + 1026 1026 ; line 307 : } + 1027 1027 ; line 308 : #endif + 1028 1028 ; line 309 : } + 1029 1029 0013E ?L0038: + 1030 1030 ; line 310 : while( iic_mcu_busy ) + 1031 1031 $DGL 0,14 + 1032 1032 0013E R31140003 bf _iic_mcu_busy,$?L0041 ;[INF] 4, 5 + 1033 1033 ; line 311 : { + 1034 1034 00142 ??bb01_iic_mcu_write: + 1035 1035 ; line 312 : NOP( ); + 1036 1036 $DGL 0,16 + 1037 1037 00142 00 nop ;[INF] 1, 1 + 1038 1038 00143 ??eb01_iic_mcu_write: + 1039 1039 ; line 313 : } + 1040 1040 $DGL 0,17 + 1041 1041 00143 EFF9 br $?L0038 ;[INF] 2, 3 + 1042 1042 00145 ?L0041: + 1043 1043 ; line 314 : /*/ + 1044 1044 ; line 315 : // 使用中なら帰る + 1045 1045 ; line 316 : if( iic_mcu_initialized == 0 ){ + 1046 1046 ; line 317 : return(0x80); + 1047 1047 ; line 318 : } + 1048 1048 ; line 319 : if( iic_mcu_busy != 0 ){ + 1049 1049 ; line 320 : return( 3 ); + 1050 1050 ; line 321 : } + 1051 1051 ; line 322 : //*/ + 1052 1052 ; line 323 : iic_mcu_busy = 1; + 1053 1053 $DGL 0,27 + 1054 1054 00145 R711200 set1 _iic_mcu_busy ;[INF] 3, 2 + 1055 1055 ; line 324 : // スタートコンディションとスレーブの呼び出し... + 1056 1056 ; line 325 : IICMK10 = 1; + 1057 1057 $DGL 0,29 + 1058 1058 00148 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 1059 1059 ; line 326 : IICIF10 = 0; + 1060 1060 $DGL 0,30 + 1061 1061 0014B 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 1062 1062 ; line 327 : if( iic_mcu_call_slave( slave ) != 0 ) + 1063 1063 $DGL 0,31 + 1064 1064 0014E RFD1300 call !bs_F0084 ;[INF] 3, 3 + 1065 1065 00151 DD09 bz $?L0042 ;[INF] 2, 4 + 1066 1066 ; line 328 : { + 1067 1067 00153 ??bb02_iic_mcu_write: + 1068 1068 ; line 329 : iic_mcu_busy = 0; + 1069 1069 $DGL 0,33 + 1070 1070 00153 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 1071 1071 ; line 330 : EI( ); + 1072 1072 $DGL 0,34 + 1073 1073 00156 717AFA ei ;[INF] 3, 4 + 1074 1074 ; line 331 : return ( ERR_NAK ); + 1075 1075 $DGL 0,35 + 1076 1076 00159 E7 onew bc ;[INF] 1, 1 + 1077 1077 0015A EF52 br $?L0037 ;[INF] 2, 3 + 1078 1078 0015C ??eb02_iic_mcu_write: + 1079 1079 ; line 332 : } + 1080 1080 0015C ?L0042: + 1081 1081 ; line 333 : + 1082 1082 ; line 334 : IICIF10 = 0; + 1083 1083 $DGL 0,38 + 1084 1084 0015C 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 1085 1085 ; line 335 : if( !iic_mcu_wo_dma ) + 1086 1086 $DGL 0,39 + 1087 1087 0015F R31020039 bt _iic_mcu_wo_dma,$?L0044 ;[INF] 4, 5 + 1088 1088 ; line 336 : { + 1089 1089 00163 ??bb03_iic_mcu_write: + 1090 1090 ; line 337 : // DMAを使用する（通常） + 1091 1091 ; line 338 : + 1092 1092 ; line 339 : // レジスタアドレスを送り、データの準備 + 1093 1093 ; line 340 : memcpy( iic_send_work, src, 4 ); //バッファとして + 1094 1094 ; 4バイトしか用意して無いため。 + 1095 1095 $DGL 0,44 + 1096 1096 00163 C7 push hl ;[INF] 1, 1 + 1097 1097 00164 R340000 movw de,#loww (_iic_send_work) ;[INF] 3, 1 + 1098 1098 00167 AC0C movw ax,[hl+12] ; src ;[INF] 2, 1 + 1099 1099 00169 16 movw hl,ax ;[INF] 1, 1 + 1100 1100 0016A 5204 mov c,#04H ; 4 ;[INF] 2, 1 + 1101 1101 0016C ?L0046: + 1102 1102 0016C 8B mov a,[hl] ;[INF] 1, 1 + 1103 1103 0016D 99 mov [de],a ;[INF] 1, 1 + 1104 1104 0016E A5 incw de ;[INF] 1, 1 + 1105 1105 0016F A7 incw hl ;[INF] 1, 1 + 1106 1106 00170 92 dec c ;[INF] 1, 1 + 1107 1107 00171 DFF9 bnz $?L0046 ;[INF] 2, 4 + 1108 1108 00173 C6 pop hl ;[INF] 1, 1 + 1109 1109 ; line 341 : // DMAセット + 1110 1110 ; line 342 : while( DST1 ) + 1111 1111 $DGL 0,46 + 1112 1112 00174 ?L0048: + 1113 1113 00174 3184BD02 bf DRC1.0,$?L0049 ;[INF] 4, 5 + 1114 1114 ; line 343 : {; + 1115 1115 00178 ??bb04_iic_mcu_write: + 1116 1116 00178 ??eb04_iic_mcu_write: + 1117 1117 ; line 344 : } + 1118 1118 $DGL 0,48 + 1119 1119 00178 EFFA br $?L0048 ;[INF] 2, 3 + 1120 1120 0017A ?L0049: + 1121 1121 ; line 345 : + 1122 1122 ; line 346 : DEN1 = 1; + 1123 1123 $DGL 0,50 + 1124 1124 0017A 717ABD set1 DRC1.7 ;[INF] 3, 2 + 1125 1125 ; line 347 : DSA1 = ( u8 ) ( &SIO10 ); + 1126 1126 $DGL 0,51 + 1127 1127 0017D CEB144 mov DSA1,#044H ; 68 ;[INF] 3, 1 + 1128 1128 ; line 348 : DRA1 = ( u16 ) iic_send_work; + 1129 1129 $DGL 0,52 + 1130 1130 00180 RCBB40000 movw DRA1,#loww (_iic_send_work) ;[INF] 4, 1 + 1131 1131 ; line 349 : DBC1 = len; + 1132 1132 $DGL 0,53 + 1133 1133 00184 8C0A mov a,[hl+10] ; len ;[INF] 2, 1 + 1134 1134 00186 318E shrw ax,8 ;[INF] 2, 1 + 1135 1135 00188 BEB8 movw DBC1,ax ;[INF] 2, 1 + 1136 1136 ; line 350 : DMC1 = DRS | 8; // RAM -> SFR, 8bit, IRQ, IIC10 + 1137 1137 $DGL 0,54 + 1138 1138 0018A CEBB48 mov DMC1,#048H ; 72 ;[INF] 3, 1 + 1139 1139 ; line 351 : + 1140 1140 ; line 352 : DMAIF1 = 0; + 1141 1141 $DGL 0,56 + 1142 1142 0018D 714BE1 clr1 IF0H.4 ;[INF] 3, 2 + 1143 1143 ; line 353 : DMAMK1 = 0; + 1144 1144 $DGL 0,57 + 1145 1145 00190 714BE5 clr1 MK0H.4 ;[INF] 3, 2 + 1146 1146 ; line 354 : DST1 = 1; + 1147 1147 $DGL 0,58 + 1148 1148 00193 710ABD set1 DRC1.0 ;[INF] 3, 2 + 1149 1149 ; line 355 : + 1150 1150 ; line 356 : SIO10 = adrs; // 書きっぱなし！ 割り込みが発生 + 1151 1151 ; してDMAスタート + 1152 1152 $DGL 0,60 + 1153 1153 00196 8C08 mov a,[hl+8] ; adrs ;[INF] 2, 1 + 1154 1154 00198 9E44 mov SIO10,a ;[INF] 2, 1 + 1155 1155 0019A ??eb03_iic_mcu_write: + 1156 1156 ; line 357 : // 残りは割り込みルーチン内で + 1157 1157 ; line 358 : } + 1158 1158 $DGL 0,62 + 1159 1159 0019A EF11 br $?L0045 ;[INF] 2, 3 + 1160 1160 0019C ?L0044: + 1161 1161 ; line 359 : else + 1162 1162 ; line 360 : { + 1163 1163 0019C ??bb05_iic_mcu_write: + 1164 1164 ; line 361 : // DMAを使用しない // + 1165 1165 ; line 362 : + 1166 1166 ; line 363 : // レジスタアドレスの送信 + 1167 1167 ; line 364 : SIO10 = adrs; + 1168 1168 $DGL 0,68 + 1169 1169 0019C 8C08 mov a,[hl+8] ; adrs ;[INF] 2, 1 + 1170 1170 0019E 9E44 mov SIO10,a ;[INF] 2, 1 + 1171 1171 ; line 365 : + 1172 1172 ; line 366 : IICMK10 = 0; + 1173 1173 $DGL 0,70 + 1174 1174 001A0 710BE6 clr1 MK1L.0 ;[INF] 3, 2 + 1175 1175 ; line 367 : iic_send_wo_dma_len = len; + 1176 1176 $DGL 0,71 + 1177 1177 001A3 8C0A mov a,[hl+10] ; len ;[INF] 2, 1 + 1178 1178 001A5 R9F0600 mov !_iic_send_wo_dma_len,a ;[INF] 3, 1 + 1179 1179 ; line 368 : p_iic_send_wo_dma_dat = src; + 1180 1180 $DGL 0,72 + 1181 1181 001A8 AC0C movw ax,[hl+12] ; src ;[INF] 2, 1 + 1182 1182 001AA RBF0400 movw !_p_iic_send_wo_dma_dat,ax ;[INF] 3, 1 + 1183 1183 001AD ??eb05_iic_mcu_write: + 1184 1184 ; line 369 : // 残りは割り込みルーチン内で + 1185 1185 ; line 370 : } + 1186 1186 001AD ?L0045: + 1187 1187 ; line 371 : return ( ERR_SUCCESS ); + 1188 1188 $DGL 0,75 + 1189 1189 001AD F7 clrw bc ;[INF] 1, 1 + 1190 1190 ; line 372 : } + 1191 1191 001AE ?L0037: + 1192 1192 $DGL 0,76 + 1193 1193 001AE ??ef_iic_mcu_write: + 1194 1194 001AE C0 pop ax ;[INF] 1, 1 + 1195 1195 001AF C6 pop hl ;[INF] 1, 1 + 1196 1196 001B0 D7 ret ;[INF] 1, 6 + 1197 1197 001B1 ??ee_iic_mcu_write: + 1198 1198 ; line 373 : + 1199 1199 ; line 374 : + 1200 1200 ; line 375 : + 1201 1201 ; line 376 : + 1202 1202 ; line 377 : /* ======================================================== + 1203 1203 ; line 378 : DMA１転送終了割り込み + 1204 1204 ; line 379 : IIC_mcu の送信完了コールバック関数のようなもの + 1205 1205 ; line 380 : 注：DMA転送が終わっただけで、I2Cの転送は終わってません + 1206 1206 ; line 381 : 　 割り込み中などで、DMA1の処理が遅延した場合、 + 1207 1207 ; line 382 : IIC10の割り込みの準備ができずに、割り込みを発生させられなくなる + 1208 1208 ; line 383 : 恐れがあります。また、回避方法も特にありません。 + 1209 1209 ; line 384 : 　そのため、DMA仕様の差異は、最後のバイトは送信完了を + 1210 1210 ; line 385 : フラグのポーリングで確認します。 + 1211 1211 ; line 386 : ======================================================== */ + 1212 1212 ; line 387 : __interrupt void int_dma1( ) + 1213 1213 ; line 388 : { + 1214 1214 + 1215 1215 ----- @@BASE CSEG BASE + 1216 1216 00000 _int_dma1: + 1217 1217 $DGL 1,151 + 1218 1218 00000 C1 push ax ;[INF] 1, 1 + 1219 1219 00001 C3 push bc ;[INF] 1, 1 + 1220 1220 00002 C5 push de ;[INF] 1, 1 + 1221 1221 00003 C7 push hl ;[INF] 1, 1 + 1222 1222 00004 520C mov c,#0CH ;[INF] 2, 1 + 1223 1223 00006 92 dec c ;[INF] 1, 1 + 1224 1224 00007 92 dec c ;[INF] 1, 1 + 1225 1225 00008 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 1226 1226 0000B C1 push ax ;[INF] 1, 1 + 1227 1227 0000C DFF8 bnz $$-6 ;[INF] 2, 4 + 1228 1228 0000E 8EFD mov a,ES ;[INF] 2, 1 + 1229 1229 00010 70 mov x,a ;[INF] 1, 1 + 1230 1230 00011 8EFC mov a,CS ;[INF] 2, 1 + 1231 1231 00013 C1 push ax ;[INF] 1, 1 + 1232 1232 00014 ??bf_int_dma1: + 1233 1233 ; line 389 : u16 i = 0; + 1234 1234 $DGL 0,2 + 1235 1235 00014 F6 clrw ax ;[INF] 1, 1 + 1236 1236 00015 16 movw hl,ax ;[INF] 1, 1 + 1237 1237 ; line 390 : + 1238 1238 ; line 391 : EI(); + 1239 1239 $DGL 0,4 + 1240 1240 00016 717AFA ei ;[INF] 3, 4 + 1241 1241 ; line 392 : + 1242 1242 ; line 393 : DMAMK1 = 1; + 1243 1243 $DGL 0,6 + 1244 1244 00019 714AE5 set1 MK0H.4 ;[INF] 3, 2 + 1245 1245 ; line 394 : DEN1 = 0; + 1246 1246 $DGL 0,7 + 1247 1247 0001C 717BBD clr1 DRC1.7 ;[INF] 3, 2 + 1248 1248 ; line 395 : while( ( SSR02L & TSF0 ) != 0 ) + 1249 1249 $DGL 0,8 + 1250 1250 0001F ?L0052: + 1251 1251 0001F 5140 mov a,#040H ; 64 ;[INF] 2, 1 + 1252 1252 00021 5F0401 and a,!SSR02L ;[INF] 3, 1 + 1253 1253 00024 D1 cmp0 a ;[INF] 1, 1 + 1254 1254 00025 DD05 bz $?L0053 ;[INF] 2, 4 + 1255 1255 ; line 396 : { + 1256 1256 00027 ??bb00_int_dma1: + 1257 1257 ; line 397 : if( ++i == 0 ) // タイムアウト？ + 1258 1258 $DGL 0,10 + 1259 1259 00027 A7 incw hl ;[INF] 1, 1 + 1260 1260 00028 F6 clrw ax ;[INF] 1, 1 + 1261 1261 00029 47 cmpw ax,hl ;[INF] 1, 1 + 1262 1262 0002A DFF3 bnz $?L0052 ;[INF] 2, 4 + 1263 1263 ; line 398 : { + 1264 1264 0002C ??bb01_int_dma1: + 1265 1265 ; line 399 : break; + 1266 1266 0002C ??eb01_int_dma1: + 1267 1267 ; line 400 : } + 1268 1268 0002C ??eb00_int_dma1: + 1269 1269 ; line 401 : } + 1270 1270 0002C ?L0053: + 1271 1271 ; line 402 : + 1272 1272 ; line 403 : // iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪いの + 1273 1273 ; で展開 + 1274 1274 ; line 404 : { + 1275 1275 0002C ??bb02_int_dma1: + 1276 1276 ; line 405 : ST0 = 0x0004; + 1277 1277 $DGL 0,18 + 1278 1278 0002C 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1279 1279 0002F BF2401 movw !ST0,ax ;[INF] 3, 1 + 1280 1280 ; line 406 : SOE0 = 0; // 受信の時はもっと前に「も」設定 + 1281 1281 ; してる。(NACK出力) + 1282 1282 $DGL 0,19 + 1283 1283 00032 F6 clrw ax ;[INF] 1, 1 + 1284 1284 00033 BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 1285 1285 ; line 407 : SO0 = 0x0000 | TAUS_MASK; // SCL + 1286 1286 $DGL 0,20 + 1287 1287 00036 300B0B movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + 1288 1288 00039 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1289 1289 ; line 408 : nop8(); + 1290 1290 $DGL 0,21 + 1291 1291 0003C RFD1B00 call !_nop8 ;[INF] 3, 3 + 1292 1292 ; line 409 : /* + 1293 1293 ; line 410 : NOP( ); + 1294 1294 ; line 411 : NOP( ); + 1295 1295 ; line 412 : NOP( ); + 1296 1296 ; line 413 : NOP( ); + 1297 1297 ; line 414 : #ifdef _OVERCLOCK_ + 1298 1298 ; line 415 : NOP( ); + 1299 1299 ; line 416 : NOP( ); + 1300 1300 ; line 417 : NOP( ); + 1301 1301 ; line 418 : NOP( ); + 1302 1302 ; line 419 : NOP( ); + 1303 1303 ; line 420 : #endif + 1304 1304 ; line 421 : */ + 1305 1305 ; line 422 : SO0 = 0x0400 | TAUS_MASK; // SCL + 1306 1306 $DGL 0,35 + 1307 1307 0003F 300B0F movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + 1308 1308 00042 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1309 1309 ; line 423 : nop8(); + 1310 1310 $DGL 0,36 + 1311 1311 00045 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1312 1312 ; line 424 : /* + 1313 1313 ; line 425 : NOP( ); + 1314 1314 ; line 426 : NOP( ); + 1315 1315 ; line 427 : NOP( ); + 1316 1316 ; line 428 : NOP( ); + 1317 1317 ; line 429 : #ifdef _OVERCLOCK_ + 1318 1318 ; line 430 : NOP( ); + 1319 1319 ; line 431 : NOP( ); + 1320 1320 ; line 432 : NOP( ); + 1321 1321 ; line 433 : NOP( ); + 1322 1322 ; line 434 : NOP( ); + 1323 1323 ; line 435 : #endif + 1324 1324 ; line 436 : */ + 1325 1325 ; line 437 : SO0 = 0x0404 | TAUS_MASK; + 1326 1326 $DGL 0,50 + 1327 1327 00048 300F0F movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + 1328 1328 0004B BF2801 movw !SO0,ax ;[INF] 3, 1 + 1329 1329 0004E ??eb02_int_dma1: + 1330 1330 ; line 438 : } + 1331 1331 ; line 439 : IICMK10 = 1; + 1332 1332 $DGL 0,52 + 1333 1333 0004E 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 1334 1334 ; line 440 : iic_mcu_busy = 0; + 1335 1335 $DGL 0,53 + 1336 1336 00051 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 1337 1337 ; line 441 : } + 1338 1338 $DGL 0,54 + 1339 1339 00054 ??ef_int_dma1: + 1340 1340 00054 C0 pop ax ;[INF] 1, 1 + 1341 1341 00055 9EFC mov CS,a ;[INF] 2, 1 + 1342 1342 00057 60 mov a,x ;[INF] 1, 1 + 1343 1343 00058 9EFD mov ES,a ;[INF] 2, 1 + 1344 1344 0005A R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 1345 1345 0005D 5206 mov c,#06H ;[INF] 2, 1 + 1346 1346 0005F C0 pop ax ;[INF] 1, 1 + 1347 1347 00060 B9 movw [de],ax ;[INF] 1, 1 + 1348 1348 00061 A5 incw de ;[INF] 1, 1 + 1349 1349 00062 A5 incw de ;[INF] 1, 1 + 1350 1350 00063 92 dec c ;[INF] 1, 1 + 1351 1351 00064 DFF9 bnz $$-5 ;[INF] 2, 4 + 1352 1352 00066 C6 pop hl ;[INF] 1, 1 + 1353 1353 00067 C4 pop de ;[INF] 1, 1 + 1354 1354 00068 C2 pop bc ;[INF] 1, 1 + 1355 1355 00069 C0 pop ax ;[INF] 1, 1 + 1356 1356 0006A 61FC reti ;[INF] 2, 6 + 1357 1357 0006C ??ee_int_dma1: + 1358 1358 ; line 442 : + 1359 1359 ; line 443 : + 1360 1360 ; line 444 : + 1361 1361 ; line 445 : /* ======================================================== + 1362 1362 ; line 446 : IIC MCUのバイト送出完了割り込み + 1363 1363 ; line 447 : ※DMA使用時は使用されません。 + 1364 1364 ; line 448 : 　他の割り込み処理中でDMAの割り込みにすぐ飛ばない場合、 + 1365 1365 ; line 449 : 　IIC割り込みのセットが間に合わず困ることがあります。 + 1366 1366 ; line 450 : ======================================================== */ + 1367 1367 ; line 451 : __interrupt void int_iic10( ) + 1368 1368 ; line 452 : { + 1369 1369 0006C _int_iic10: + 1370 1370 $DGL 1,170 + 1371 1371 0006C C1 push ax ;[INF] 1, 1 + 1372 1372 0006D C3 push bc ;[INF] 1, 1 + 1373 1373 0006E C5 push de ;[INF] 1, 1 + 1374 1374 0006F C7 push hl ;[INF] 1, 1 + 1375 1375 00070 520C mov c,#0CH ;[INF] 2, 1 + 1376 1376 00072 92 dec c ;[INF] 1, 1 + 1377 1377 00073 92 dec c ;[INF] 1, 1 + 1378 1378 00074 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 1379 1379 00077 C1 push ax ;[INF] 1, 1 + 1380 1380 00078 DFF8 bnz $$-6 ;[INF] 2, 4 + 1381 1381 0007A 8EFD mov a,ES ;[INF] 2, 1 + 1382 1382 0007C 70 mov x,a ;[INF] 1, 1 + 1383 1383 0007D 8EFC mov a,CS ;[INF] 2, 1 + 1384 1384 0007F C1 push ax ;[INF] 1, 1 + 1385 1385 00080 ??bf_int_iic10: + 1386 1386 ; line 453 : EI(); + 1387 1387 $DGL 0,2 + 1388 1388 00080 717AFA ei ;[INF] 3, 4 + 1389 1389 ; line 454 : if( iic_send_wo_dma_len != 0 ) + 1390 1390 $DGL 0,3 + 1391 1391 00083 RD50600 cmp0 !_iic_send_wo_dma_len ;[INF] 3, 1 + 1392 1392 00086 DD0E bz $?L0058 ;[INF] 2, 4 + 1393 1393 ; line 455 : { + 1394 1394 00088 ??bb00_int_iic10: + 1395 1395 ; line 456 : SIO10 = *p_iic_send_wo_dma_dat; + 1396 1396 $DGL 0,5 + 1397 1397 00088 REB0400 movw de,!_p_iic_send_wo_dma_dat ;[INF] 3, 1 + 1398 1398 0008B 89 mov a,[de] ;[INF] 1, 1 + 1399 1399 0008C 9E44 mov SIO10,a ;[INF] 2, 1 + 1400 1400 ; line 457 : p_iic_send_wo_dma_dat++; + 1401 1401 $DGL 0,6 + 1402 1402 0008E RA20400 incw !_p_iic_send_wo_dma_dat ;[INF] 3, 2 + 1403 1403 ; line 458 : iic_send_wo_dma_len--; + 1404 1404 $DGL 0,7 + 1405 1405 00091 RB00600 dec !_iic_send_wo_dma_len ;[INF] 3, 2 + 1406 1406 ; line 459 : return; + 1407 1407 $DGL 0,8 + 1408 1408 00094 EF2B br $?L0057 ;[INF] 2, 3 + 1409 1409 00096 ??eb00_int_iic10: + 1410 1410 ; line 460 : } + 1411 1411 00096 ?L0058: + 1412 1412 ; line 461 : + 1413 1413 ; line 462 : // 最後のバイト送信完了 + 1414 1414 ; line 463 : IICMK10 = 1; + 1415 1415 $DGL 0,12 + 1416 1416 00096 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 1417 1417 ; line 464 : // iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪い + 1418 1418 ; ので展開 + 1419 1419 ; line 465 : { + 1420 1420 00099 ??bb01_int_iic10: + 1421 1421 ; line 466 : ST0 = 0x0004; + 1422 1422 $DGL 0,15 + 1423 1423 00099 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1424 1424 0009C BF2401 movw !ST0,ax ;[INF] 3, 1 + 1425 1425 ; line 467 : SOE0 = 0; // 受信の時はもっと前に「も」設定 + 1426 1426 ; してる。(NACK出力) + 1427 1427 $DGL 0,16 + 1428 1428 0009F F6 clrw ax ;[INF] 1, 1 + 1429 1429 000A0 BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 1430 1430 ; line 468 : SO0 = 0x0000 | TAUS_MASK; // SCL + 1431 1431 $DGL 0,17 + 1432 1432 000A3 300B0B movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + 1433 1433 000A6 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1434 1434 ; line 469 : nop8(); + 1435 1435 $DGL 0,18 + 1436 1436 000A9 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1437 1437 ; line 470 : /* + 1438 1438 ; line 471 : NOP( ); + 1439 1439 ; line 472 : NOP( ); + 1440 1440 ; line 473 : NOP( ); + 1441 1441 ; line 474 : NOP( ); + 1442 1442 ; line 475 : #ifdef _OVERCLOCK_ + 1443 1443 ; line 476 : NOP( ); + 1444 1444 ; line 477 : NOP( ); + 1445 1445 ; line 478 : NOP( ); + 1446 1446 ; line 479 : NOP( ); + 1447 1447 ; line 480 : NOP( ); + 1448 1448 ; line 481 : #endif + 1449 1449 ; line 482 : */ + 1450 1450 ; line 483 : SO0 = 0x0400 | TAUS_MASK; // SCL + 1451 1451 $DGL 0,32 + 1452 1452 000AC 300B0F movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + 1453 1453 000AF BF2801 movw !SO0,ax ;[INF] 3, 1 + 1454 1454 ; line 484 : nop8(); + 1455 1455 $DGL 0,33 + 1456 1456 000B2 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1457 1457 ; line 485 : /* + 1458 1458 ; line 486 : NOP( ); + 1459 1459 ; line 487 : NOP( ); + 1460 1460 ; line 488 : NOP( ); + 1461 1461 ; line 489 : NOP( ); + 1462 1462 ; line 490 : #ifdef _OVERCLOCK_ + 1463 1463 ; line 491 : NOP( ); + 1464 1464 ; line 492 : NOP( ); + 1465 1465 ; line 493 : NOP( ); + 1466 1466 ; line 494 : NOP( ); + 1467 1467 ; line 495 : NOP( ); + 1468 1468 ; line 496 : #endif + 1469 1469 ; line 497 : */ + 1470 1470 ; line 498 : SO0 = 0x0404 | TAUS_MASK; + 1471 1471 $DGL 0,47 + 1472 1472 000B5 300F0F movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + 1473 1473 000B8 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1474 1474 000BB ??eb01_int_iic10: + 1475 1475 ; line 499 : } + 1476 1476 ; line 500 : iic_mcu_wo_dma = 0; + 1477 1477 $DGL 0,49 + 1478 1478 000BB R710300 clr1 _iic_mcu_wo_dma ;[INF] 3, 2 + 1479 1479 ; line 501 : iic_mcu_busy = 0; + 1480 1480 $DGL 0,50 + 1481 1481 000BE R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 1482 1482 ; line 502 : } + 1483 1483 000C1 ?L0057: + 1484 1484 $DGL 0,51 + 1485 1485 000C1 ??ef_int_iic10: + 1486 1486 000C1 C0 pop ax ;[INF] 1, 1 + 1487 1487 000C2 9EFC mov CS,a ;[INF] 2, 1 + 1488 1488 000C4 60 mov a,x ;[INF] 1, 1 + 1489 1489 000C5 9EFD mov ES,a ;[INF] 2, 1 + 1490 1490 000C7 R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 1491 1491 000CA 5206 mov c,#06H ;[INF] 2, 1 + 1492 1492 000CC C0 pop ax ;[INF] 1, 1 + 1493 1493 000CD B9 movw [de],ax ;[INF] 1, 1 + 1494 1494 000CE A5 incw de ;[INF] 1, 1 + 1495 1495 000CF A5 incw de ;[INF] 1, 1 + 1496 1496 000D0 92 dec c ;[INF] 1, 1 + 1497 1497 000D1 DFF9 bnz $$-5 ;[INF] 2, 4 + 1498 1498 000D3 C6 pop hl ;[INF] 1, 1 + 1499 1499 000D4 C4 pop de ;[INF] 1, 1 + 1500 1500 000D5 C2 pop bc ;[INF] 1, 1 + 1501 1501 000D6 C0 pop ax ;[INF] 1, 1 + 1502 1502 000D7 61FC reti ;[INF] 2, 6 + 1503 1503 000D9 ??ee_int_iic10: + 1504 1504 ; line 503 : + 1505 1505 ; line 504 : + 1506 1506 ; line 505 : + 1507 1507 ; line 506 : /* ======================================================== + 1508 1508 ; line 507 : スレーブの呼び出し + 1509 1509 ; line 508 : 　スレーブアドレスを呼んで、ACKの確認。 + 1510 1510 ; line 509 : ACK　→　　　　　　　　　　　　　　　　　返：0 + 1511 1511 ; line 510 : 　NACK →　ストップコンディションを出す。　返：1 + 1512 1512 ; line 511 : ======================================================== */ + 1513 1513 ; line 512 : static err iic_mcu_call_slave( u8 slave ) + 1514 1514 ; line 513 : { + 1515 1515 + 1516 1516 ----- ROM_CODE CSEG BASE + 1517 1517 001B1 _iic_mcu_call_slave: + 1518 1518 $DGL 1,184 + 1519 1519 001B1 C7 push hl ;[INF] 1, 1 + 1520 1520 001B2 16 movw hl,ax ;[INF] 1, 1 + 1521 1521 001B3 ??bf_iic_mcu_call_slave: + 1522 1522 ; line 514 : iic_mcu_send_st( ); + 1523 1523 $DGL 0,2 + 1524 1524 001B3 RFDEB01 call !_iic_mcu_send_st ;[INF] 3, 3 + 1525 1525 ; line 515 : + 1526 1526 ; line 516 : // SIR02 = SSR02; // NAKエラーのフラグクリア + 1527 1527 ; line 517 : if( iic_mcu_send_a_byte( slave ) != ERR_SUCCESS ) + 1528 1528 $DGL 0,5 + 1529 1529 001B6 17 movw ax,hl ;[INF] 1, 1 + 1530 1530 001B7 F1 clrb a ;[INF] 1, 1 + 1531 1531 001B8 RFDC701 call !_iic_mcu_send_a_byte ;[INF] 3, 3 + 1532 1532 001BB D2 cmp0 c ;[INF] 1, 1 + 1533 1533 001BC DD06 bz $?L0062 ;[INF] 2, 4 + 1534 1534 ; line 518 : { + 1535 1535 001BE ??bb00_iic_mcu_call_slave: + 1536 1536 ; line 519 : iic_mcu_send_sp( ); + 1537 1537 $DGL 0,7 + 1538 1538 001BE RFD3902 call !_iic_mcu_send_sp ;[INF] 3, 3 + 1539 1539 ; line 520 : return ( ERR_NAK ); // 指定のスレーブがいない / busy + 1540 1540 $DGL 0,8 + 1541 1541 001C1 E7 onew bc ;[INF] 1, 1 + 1542 1542 001C2 EF01 br $?L0061 ;[INF] 2, 3 + 1543 1543 001C4 ??eb00_iic_mcu_call_slave: + 1544 1544 ; line 521 : } + 1545 1545 001C4 ?L0062: + 1546 1546 ; line 522 : + 1547 1547 ; line 523 : return ( ERR_SUCCESS ); + 1548 1548 $DGL 0,11 + 1549 1549 001C4 F7 clrw bc ;[INF] 1, 1 + 1550 1550 ; line 524 : } + 1551 1551 001C5 ?L0061: + 1552 1552 $DGL 0,12 + 1553 1553 001C5 ??ef_iic_mcu_call_slave: + 1554 1554 001C5 C6 pop hl ;[INF] 1, 1 + 1555 1555 001C6 D7 ret ;[INF] 1, 6 + 1556 1556 001C7 ??ee_iic_mcu_call_slave: + 1557 1557 ; line 525 : + 1558 1558 ; line 526 : + 1559 1559 ; line 527 : + 1560 1560 ; line 528 : /* ======================================================== + 1561 1561 ; line 529 : ほんとに１バイト書くのみ + 1562 1562 ; line 530 : 書き終わるまで帰りません + 1563 1563 ; line 531 : ======================================================== */ + 1564 1564 ; line 532 : static err iic_mcu_send_a_byte( u8 dat ) + 1565 1565 ; line 533 : { + 1566 1566 001C7 _iic_mcu_send_a_byte: + 1567 1567 $DGL 1,195 + 1568 1568 001C7 C7 push hl ;[INF] 1, 1 + 1569 1569 001C8 16 movw hl,ax ;[INF] 1, 1 + 1570 1570 001C9 ??bf_iic_mcu_send_a_byte: + 1571 1571 ; line 534 : IICMK10 = 1; + 1572 1572 $DGL 0,2 + 1573 1573 001C9 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 1574 1574 ; line 535 : IICIF10 = 0; + 1575 1575 $DGL 0,3 + 1576 1576 001CC 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 1577 1577 ; line 536 : SIO10 = dat; + 1578 1578 $DGL 0,4 + 1579 1579 001CF 66 mov a,l ;[INF] 1, 1 + 1580 1580 001D0 9E44 mov SIO10,a ;[INF] 2, 1 + 1581 1581 ; line 537 : while( IICIF10 == 0 ) + 1582 1582 $DGL 0,5 + 1583 1583 001D2 ?L0066: + 1584 1584 001D2 3182E203 bt IF1L.0,$?L0067 ;[INF] 4, 5 + 1585 1585 ; line 538 : { + 1586 1586 001D6 ??bb00_iic_mcu_send_a_byte: + 1587 1587 ; line 539 : NOP( ); + 1588 1588 $DGL 0,7 + 1589 1589 001D6 00 nop ;[INF] 1, 1 + 1590 1590 001D7 ??eb00_iic_mcu_send_a_byte: + 1591 1591 ; line 540 : } // 通信中 + 1592 1592 $DGL 0,8 + 1593 1593 001D7 EFF9 br $?L0066 ;[INF] 2, 3 + 1594 1594 001D9 ?L0067: + 1595 1595 ; line 541 : if( SSR02 != 0 ) + 1596 1596 $DGL 0,9 + 1597 1597 001D9 F6 clrw ax ;[INF] 1, 1 + 1598 1598 001DA 420401 cmpw ax,!SSR02 ;[INF] 3, 1 + 1599 1599 001DD DD09 bz $?L0068 ;[INF] 2, 4 + 1600 1600 ; line 542 : { + 1601 1601 001DF ??bb01_iic_mcu_send_a_byte: + 1602 1602 ; line 543 : SIR02 = SSR02; + 1603 1603 $DGL 0,11 + 1604 1604 001DF AF0401 movw ax,!SSR02 ;[INF] 3, 1 + 1605 1605 001E2 BF0C01 movw !SIR02,ax ;[INF] 3, 1 + 1606 1606 ; line 544 : return ( ERR_NAK ); + 1607 1607 $DGL 0,12 + 1608 1608 001E5 E7 onew bc ;[INF] 1, 1 + 1609 1609 001E6 EF01 br $?L0065 ;[INF] 2, 3 + 1610 1610 001E8 ??eb01_iic_mcu_send_a_byte: + 1611 1611 ; line 545 : } + 1612 1612 001E8 ?L0068: + 1613 1613 ; line 546 : return ( ERR_SUCCESS ); + 1614 1614 $DGL 0,14 + 1615 1615 001E8 F7 clrw bc ;[INF] 1, 1 + 1616 1616 ; line 547 : } + 1617 1617 001E9 ?L0065: + 1618 1618 $DGL 0,15 + 1619 1619 001E9 ??ef_iic_mcu_send_a_byte: + 1620 1620 001E9 C6 pop hl ;[INF] 1, 1 + 1621 1621 001EA D7 ret ;[INF] 1, 6 + 1622 1622 001EB ??ee_iic_mcu_send_a_byte: + 1623 1623 ; line 548 : + 1624 1624 ; line 549 : + 1625 1625 ; line 550 : + 1626 1626 ; line 551 : /* ======================================================== + 1627 1627 ; line 552 : スタートコンディションを発行 + 1628 1628 ; line 553 : ソフトウェア制御 + 1629 1629 ; line 554 : ======================================================== */ + 1630 1630 ; line 555 : static void iic_mcu_send_st( ) + 1631 1631 ; line 556 : { + 1632 1632 001EB _iic_mcu_send_st: + 1633 1633 $DGL 1,210 + 1634 1634 001EB ??bf_iic_mcu_send_st: + 1635 1635 ; line 557 : SO0 &= ~0x0004; // SDA + 1636 1636 $DGL 0,2 + 1637 1637 001EB AF2801 movw ax,!SO0 ;[INF] 3, 1 + 1638 1638 001EE 08 xch a,x ;[INF] 1, 1 + 1639 1639 001EF 5CFB and a,#0FBH ; 251 ;[INF] 2, 1 + 1640 1640 001F1 08 xch a,x ;[INF] 1, 1 + 1641 1641 001F2 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1642 1642 ; line 558 : nop8(); + 1643 1643 $DGL 0,3 + 1644 1644 001F5 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1645 1645 ; line 559 : /* + 1646 1646 ; line 560 : NOP( ); + 1647 1647 ; line 561 : NOP( ); + 1648 1648 ; line 562 : NOP( ); + 1649 1649 ; line 563 : NOP( ); + 1650 1650 ; line 564 : #ifdef _OVERCLOCK_ + 1651 1651 ; line 565 : NOP( ); + 1652 1652 ; line 566 : NOP( ); + 1653 1653 ; line 567 : NOP( ); + 1654 1654 ; line 568 : NOP( ); + 1655 1655 ; line 569 : NOP( ); + 1656 1656 ; line 570 : #endif + 1657 1657 ; line 571 : */ + 1658 1658 ; line 572 : SO0 &= ~0x0400; // SCL + 1659 1659 $DGL 0,17 + 1660 1660 001F8 AF2801 movw ax,!SO0 ;[INF] 3, 1 + 1661 1661 001FB 5CFB and a,#0FBH ; 251 ;[INF] 2, 1 + 1662 1662 001FD BF2801 movw !SO0,ax ;[INF] 3, 1 + 1663 1663 ; line 573 : SOE0 = 0x0004; // ハード制御へ + 1664 1664 $DGL 0,18 + 1665 1665 00200 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1666 1666 00203 BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 1667 1667 ; line 574 : + 1668 1668 ; line 575 : SCR02 = TXE0 | 1 << SLC02 | 7 << DLS02; // 送信許可、デー + 1669 1669 ; タは８ビット単位 + 1670 1670 $DGL 0,20 + 1671 1671 00206 301780 movw ax,#08017H ; -32745 ;[INF] 3, 1 + 1672 1672 00209 BF1C01 movw !SCR02,ax ;[INF] 3, 1 + 1673 1673 ; line 576 : SS0 = 0x0004; // 通信待機 + 1674 1674 $DGL 0,21 + 1675 1675 0020C RFD0C00 call !bs_S0087 ;[INF] 3, 3 + 1676 1676 ; line 577 : } + 1677 1677 $DGL 0,22 + 1678 1678 0020F ??ef_iic_mcu_send_st: + 1679 1679 0020F D7 ret ;[INF] 1, 6 + 1680 1680 00210 ??ee_iic_mcu_send_st: + 1681 1681 ; line 578 : + 1682 1682 ; line 579 : + 1683 1683 ; line 580 : + 1684 1684 ; line 581 : /* ======================================================== + 1685 1685 ; line 582 : リスタート発行 + 1686 1686 ; line 583 : ======================================================== */ + 1687 1687 ; line 584 : static void iic_mcu_send_re_st( ) + 1688 1688 ; line 585 : { + 1689 1689 00210 _iic_mcu_send_re_st: + 1690 1690 $DGL 1,216 + 1691 1691 00210 ??bf_iic_mcu_send_re_st: + 1692 1692 ; line 586 : ST0 |= 0x0004; + 1693 1693 $DGL 0,2 + 1694 1694 00210 AF2401 movw ax,!ST0 ;[INF] 3, 1 + 1695 1695 00213 08 xch a,x ;[INF] 1, 1 + 1696 1696 00214 6C04 or a,#04H ; 4 ;[INF] 2, 1 + 1697 1697 00216 08 xch a,x ;[INF] 1, 1 + 1698 1698 00217 BF2401 movw !ST0,ax ;[INF] 3, 1 + 1699 1699 ; line 587 : SO0 |= 0x0400 | TAUS_MASK; // ( SDA = H ), SCL -> H + 1700 1700 $DGL 0,3 + 1701 1701 0021A AF2801 movw ax,!SO0 ;[INF] 3, 1 + 1702 1702 0021D 6C0F or a,#0FH ; 15 ;[INF] 2, 1 + 1703 1703 0021F 08 xch a,x ;[INF] 1, 1 + 1704 1704 00220 6C0B or a,#0BH ; 11 ;[INF] 2, 1 + 1705 1705 00222 08 xch a,x ;[INF] 1, 1 + 1706 1706 00223 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1707 1707 ; line 588 : nop8(); + 1708 1708 $DGL 0,4 + 1709 1709 00226 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1710 1710 ; line 589 : /* + 1711 1711 ; line 590 : NOP( ); + 1712 1712 ; line 591 : NOP( ); + 1713 1713 ; line 592 : NOP( ); + 1714 1714 ; line 593 : NOP( ); + 1715 1715 ; line 594 : #ifdef _OVERCLOCK_ + 1716 1716 ; line 595 : NOP( ); + 1717 1717 ; line 596 : NOP( ); + 1718 1718 ; line 597 : NOP( ); + 1719 1719 ; line 598 : NOP( ); + 1720 1720 ; line 599 : NOP( ); + 1721 1721 ; line 600 : #endif + 1722 1722 ; line 601 : */ + 1723 1723 ; line 602 : SOE0 &= ~0x0004; // ( SCL = H ), SDA -> L + 1724 1724 $DGL 0,18 + 1725 1725 00229 AF2A01 movw ax,!SOE0 ;[INF] 3, 1 + 1726 1726 0022C 08 xch a,x ;[INF] 1, 1 + 1727 1727 0022D 5CFB and a,#0FBH ; 251 ;[INF] 2, 1 + 1728 1728 0022F 08 xch a,x ;[INF] 1, 1 + 1729 1729 00230 BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 1730 1730 ; line 603 : nop8(); + 1731 1731 $DGL 0,19 + 1732 1732 00233 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1733 1733 ; line 604 : /* + 1734 1734 ; line 605 : NOP( ); + 1735 1735 ; line 606 : NOP( ); + 1736 1736 ; line 607 : NOP( ); + 1737 1737 ; line 608 : NOP( ); + 1738 1738 ; line 609 : #ifdef _OVERCLOCK_ + 1739 1739 ; line 610 : NOP( ); + 1740 1740 ; line 611 : NOP( ); + 1741 1741 ; line 612 : NOP( ); + 1742 1742 ; line 613 : NOP( ); + 1743 1743 ; line 614 : NOP( ); + 1744 1744 ; line 615 : #endif + 1745 1745 ; line 616 : */ + 1746 1746 ; line 617 : iic_mcu_send_st( ); + 1747 1747 $DGL 0,33 + 1748 1748 00236 REDEB01 br !_iic_mcu_send_st ;[INF] 3, 3 + 1749 1749 00239 ??ef_iic_mcu_send_re_st: + 1750 1750 00239 ??ee_iic_mcu_send_re_st: + 1751 1751 ; line 618 : } + 1752 1752 ; line 619 : + 1753 1753 ; line 620 : + 1754 1754 ; line 621 : + 1755 1755 ; line 622 : /* ======================================================== + 1756 1756 ; line 623 : ストップコンディション発行 + 1757 1757 ; line 624 : この前に、「最後のバイトの送受信」の時に前準備が必要です。 + 1758 1758 ; line 625 : ======================================================== */ + 1759 1759 ; line 626 : static void iic_mcu_send_sp( ) + 1760 1760 ; line 627 : { + 1761 1761 00239 _iic_mcu_send_sp: + 1762 1762 $DGL 1,222 + 1763 1763 00239 ??bf_iic_mcu_send_sp: + 1764 1764 ; line 628 : ST0 = 0x0004; + 1765 1765 $DGL 0,2 + 1766 1766 00239 RFD0500 call !bs_S0086 ;[INF] 3, 3 + 1767 1767 ; line 629 : SOE0 = 0; // 受信の時はもっと前に「も」設定 + 1768 1768 ; してる。(NACK出力) + 1769 1769 $DGL 0,3 + 1770 1770 0023C F6 clrw ax ;[INF] 1, 1 + 1771 1771 0023D BF2A01 movw !SOE0,ax ;[INF] 3, 1 + 1772 1772 ; line 630 : SO0 = 0x0000 | TAUS_MASK; // SCL + 1773 1773 $DGL 0,4 + 1774 1774 00240 300B0B movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + 1775 1775 00243 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1776 1776 ; line 631 : nop8(); + 1777 1777 $DGL 0,5 + 1778 1778 00246 RFD1B00 call !_nop8 ;[INF] 3, 3 + 1779 1779 ; line 632 : /* + 1780 1780 ; line 633 : NOP( ); + 1781 1781 ; line 634 : NOP( ); + 1782 1782 ; line 635 : NOP( ); + 1783 1783 ; line 636 : NOP( ); + 1784 1784 ; line 637 : #ifdef _OVERCLOCK_ + 1785 1785 ; line 638 : NOP( ); + 1786 1786 ; line 639 : NOP( ); + 1787 1787 ; line 640 : NOP( ); + 1788 1788 ; line 641 : NOP( ); + 1789 1789 ; line 642 : NOP( ); + 1790 1790 ; line 643 : #endif + 1791 1791 ; line 644 : */ + 1792 1792 ; line 645 : SO0 = 0x0400 | TAUS_MASK; // SCL + 1793 1793 $DGL 0,19 + 1794 1794 00249 300B0F movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + 1795 1795 0024C BF2801 movw !SO0,ax ;[INF] 3, 1 + 1796 1796 ; line 646 : nop8(); + 1797 1797 $DGL 0,20 + 1798 1798 0024F RFD1B00 call !_nop8 ;[INF] 3, 3 + 1799 1799 ; line 647 : /* + 1800 1800 ; line 648 : NOP( ); + 1801 1801 ; line 649 : NOP( ); + 1802 1802 ; line 650 : NOP( ); + 1803 1803 ; line 651 : NOP( ); + 1804 1804 ; line 652 : #ifdef _OVERCLOCK_ + 1805 1805 ; line 653 : NOP( ); + 1806 1806 ; line 654 : NOP( ); + 1807 1807 ; line 655 : NOP( ); + 1808 1808 ; line 656 : NOP( ); + 1809 1809 ; line 657 : NOP( ); + 1810 1810 ; line 658 : #endif + 1811 1811 ; line 659 : */ + 1812 1812 ; line 660 : SO0 = 0x0404 | TAUS_MASK; + 1813 1813 $DGL 0,34 + 1814 1814 00252 300F0F movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + 1815 1815 00255 BF2801 movw !SO0,ax ;[INF] 3, 1 + 1816 1816 ; line 661 : } + 1817 1817 $DGL 0,35 + 1818 1818 00258 ??ef_iic_mcu_send_sp: + 1819 1819 00258 D7 ret ;[INF] 1, 6 + 1820 1820 00259 ??ee_iic_mcu_send_sp: + 1821 1821 ; line 662 : + 1822 1822 ; line 663 : + 1823 1823 ; line 664 : + 1824 1824 ; line 665 : + 1825 1825 ; line 666 : /* ======================================================== + 1826 1826 ; line 667 : ペリフェラルモジュールの初期化 + 1827 1827 ; line 668 : ======================================================== */ + 1828 1828 ; line 669 : void iic_mcu_start( ) + 1829 1829 ; line 670 : { + 1830 1830 00259 _iic_mcu_start: + 1831 1831 $DGL 1,228 + 1832 1832 00259 ??bf_iic_mcu_start: + 1833 1833 ; line 671 : DST1 = 0; + 1834 1834 $DGL 0,2 + 1835 1835 00259 710BBD clr1 DRC1.0 ;[INF] 3, 2 + 1836 1836 ; line 672 : NOP( ); // 2clkもしくは、DSTn==0をポーリ + 1837 1837 ; ング + 1838 1838 $DGL 0,3 + 1839 1839 0025C 00 nop ;[INF] 1, 1 + 1840 1840 ; line 673 : NOP( ); + 1841 1841 $DGL 0,4 + 1842 1842 0025D 00 nop ;[INF] 1, 1 + 1843 1843 ; line 674 : DEN1 = 0; + 1844 1844 $DGL 0,5 + 1845 1845 0025E 717BBD clr1 DRC1.7 ;[INF] 3, 2 + 1846 1846 ; line 675 : I2C_PU_on(); + 1847 1847 $DGL 0,6 + 1848 1848 00261 ??bb00_iic_mcu_start: + 1849 1849 00261 713A25 set1 PM5.3 ;[INF] 3, 2 + 1850 1850 00264 713A23 set1 PM3.3 ;[INF] 3, 2 + 1851 1851 00267 6A0E03 or P14,#03H ; 3 ;[INF] 3, 2 + 1852 1852 0026A 713205 set1 P5.3 ;[INF] 3, 2 + 1853 1853 0026D 713B25 clr1 PM5.3 ;[INF] 3, 2 + 1854 1854 00270 713203 set1 P3.3 ;[INF] 3, 2 + 1855 1855 00273 713B23 clr1 PM3.3 ;[INF] 3, 2 + 1856 1856 00276 ??eb00_iic_mcu_start: + 1857 1857 ; line 676 : SAU0EN = 1; + 1858 1858 $DGL 0,7 + 1859 1859 00276 7120F000 set1 !PER0.2 ;[INF] 4, 2 + 1860 1860 ; line 677 : nop8(); + 1861 1861 $DGL 0,8 + 1862 1862 0027A RFD1B00 call !_nop8 ;[INF] 3, 3 + 1863 1863 ; line 678 : /* + 1864 1864 ; line 679 : NOP( ); + 1865 1865 ; line 680 : NOP( ); + 1866 1866 ; line 681 : NOP( ); + 1867 1867 ; line 682 : NOP( ); + 1868 1868 ; line 683 : #ifdef _OVERCLOCK_ + 1869 1869 ; line 684 : NOP( ); + 1870 1870 ; line 685 : NOP( ); + 1871 1871 ; line 686 : NOP( ); + 1872 1872 ; line 687 : NOP( ); + 1873 1873 ; line 688 : NOP( ); + 1874 1874 ; line 689 : #endif + 1875 1875 ; line 690 : */ + 1876 1876 ; line 691 : SPS0 = 0x0000; // シリアルユニットのクロック０。 + 1877 1877 ; (8M/2)/1 + 1878 1878 $DGL 0,22 + 1879 1879 0027D F6 clrw ax ;[INF] 1, 1 + 1880 1880 0027E BF2601 movw !SPS0,ax ;[INF] 3, 1 + 1881 1881 ; line 692 : SMR02 = bSMR0n_FIXEDBIT | bMD0n2; // 簡易I2Cに設定 + 1882 1882 $DGL 0,23 + 1883 1883 00281 5024 mov x,#024H ; 36 ;[INF] 2, 1 + 1884 1884 00283 BF1401 movw !SMR02,ax ;[INF] 3, 1 + 1885 1885 ; line 693 : #ifdef _OVERCLOCK_ + 1886 1886 ; line 694 : SDR02 = 12 << 9; // ボーレート設定 (8M/2)/1/(x+1 + 1887 1887 ; )/2 + 1888 1888 $DGL 0,25 + 1889 1889 00286 CB440018 movw SDR02,#01800H ; 6144 ;[INF] 4, 1 + 1890 1890 ; line 695 : #else + 1891 1891 ; line 696 : SDR02 = 5 << 9; // ボーレート設定 (8M/2)/1/(x+1) + 1892 1892 ; /2 + 1893 1893 ; line 697 : #endif + 1894 1894 ; line 698 : + 1895 1895 ; line 699 : SO0 = 0x0404 | TAUS_MASK; // 最初はHH + 1896 1896 $DGL 0,30 + 1897 1897 0028A 300F0F movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + 1898 1898 0028D BF2801 movw !SO0,ax ;[INF] 3, 1 + 1899 1899 ; line 700 : iic_mcu_busy = 0; + 1900 1900 $DGL 0,31 + 1901 1901 00290 R711300 clr1 _iic_mcu_busy ;[INF] 3, 2 + 1902 1902 ; line 701 : iic_mcu_wo_dma = 0; + 1903 1903 $DGL 0,32 + 1904 1904 00293 R710300 clr1 _iic_mcu_wo_dma ;[INF] 3, 2 + 1905 1905 ; line 702 : + 1906 1906 ; line 703 : + 1907 1907 ; line 704 : // バスのリセット + 1908 1908 ; line 705 : IICIF10 = 0; + 1909 1909 $DGL 0,36 + 1910 1910 00296 710BE2 clr1 IF1L.0 ;[INF] 3, 2 + 1911 1911 ; line 706 : IICMK10 = 1; + 1912 1912 $DGL 0,37 + 1913 1913 00299 710AE6 set1 MK1L.0 ;[INF] 3, 2 + 1914 1914 ; line 707 : + 1915 1915 ; line 708 : iic_mcu_send_st(); + 1916 1916 $DGL 0,39 + 1917 1917 0029C RFDEB01 call !_iic_mcu_send_st ;[INF] 3, 3 + 1918 1918 ; line 709 : + 1919 1919 ; line 710 : SIO10 = 0xFF; + 1920 1920 $DGL 0,41 + 1921 1921 0029F CE44FF mov SIO10,#0FFH ; 255 ;[INF] 3, 1 + 1922 1922 ; line 711 : while( IICIF10 == 0 ){} // 通信中 + 1923 1923 $DGL 0,42 + 1924 1924 002A2 ?L0078: + 1925 1925 002A2 3182E202 bt IF1L.0,$?L0079 ;[INF] 4, 5 + 1926 1926 002A6 ??bb01_iic_mcu_start: + 1927 1927 002A6 ??eb01_iic_mcu_start: + 1928 1928 002A6 EFFA br $?L0078 ;[INF] 2, 3 + 1929 1929 002A8 ?L0079: + 1930 1930 ; line 712 : iic_mcu_send_sp(); + 1931 1931 $DGL 0,43 + 1932 1932 002A8 RFD3902 call !_iic_mcu_send_sp ;[INF] 3, 3 + 1933 1933 ; line 713 : + 1934 1934 ; line 714 : SIR02 = SSR02; + 1935 1935 $DGL 0,45 + 1936 1936 002AB AF0401 movw ax,!SSR02 ;[INF] 3, 1 + 1937 1937 002AE BF0C01 movw !SIR02,ax ;[INF] 3, 1 + 1938 1938 ; line 715 : + 1939 1939 ; line 716 : iic_mcu_initialized = 1; + 1940 1940 $DGL 0,47 + 1941 1941 002B1 R712200 set1 _iic_mcu_initialized ;[INF] 3, 2 + 1942 1942 ; line 717 : } + 1943 1943 $DGL 0,48 + 1944 1944 002B4 ??ef_iic_mcu_start: + 1945 1945 002B4 D7 ret ;[INF] 1, 6 + 1946 1946 002B5 ??ee_iic_mcu_start: + 1947 1947 ; line 718 : + 1948 1948 ; line 719 : + 1949 1949 ; line 720 : + 1950 1950 ; line 721 : /* ======================================================== + 1951 1951 ; line 722 : モジュールの停止 + 1952 1952 ; line 723 : 再度使うときは初期化が必要 + 1953 1953 ; line 724 : ======================================================== */ + 1954 1954 ; line 725 : void iic_mcu_stop( ) + 1955 1955 ; line 726 : { + 1956 1956 002B5 _iic_mcu_stop: + 1957 1957 $DGL 1,242 + 1958 1958 002B5 ??bf_iic_mcu_stop: + 1959 1959 ; line 727 : while( iic_mcu_busy ) + 1960 1960 $DGL 0,2 + 1961 1961 002B5 ?L0082: + 1962 1962 002B5 R31140002 bf _iic_mcu_busy,$?L0083 ;[INF] 4, 5 + 1963 1963 ; line 728 : {; + 1964 1964 002B9 ??bb00_iic_mcu_stop: + 1965 1965 002B9 ??eb00_iic_mcu_stop: + 1966 1966 ; line 729 : } // DMA動作中はもう少し待つ + 1967 1967 $DGL 0,4 + 1968 1968 002B9 EFFA br $?L0082 ;[INF] 2, 3 + 1969 1969 002BB ?L0083: + 1970 1970 ; line 730 : iic_mcu_send_re_st( ); // SCL,SDAをLLにする + 1971 1971 $DGL 0,5 + 1972 1972 002BB RFD1002 call !_iic_mcu_send_re_st ;[INF] 3, 3 + 1973 1973 ; line 731 : I2C_PU_off(); + 1974 1974 $DGL 0,6 + 1975 1975 002BE ??bb01_iic_mcu_stop: + 1976 1976 002BE 713A25 set1 PM5.3 ;[INF] 3, 2 + 1977 1977 002C1 713A23 set1 PM3.3 ;[INF] 3, 2 + 1978 1978 002C4 5A0EFC and P14,#0FCH ; 252 ;[INF] 3, 2 + 1979 1979 002C7 713305 clr1 P5.3 ;[INF] 3, 2 + 1980 1980 002CA 713B25 clr1 PM5.3 ;[INF] 3, 2 + 1981 1981 002CD 713303 clr1 P3.3 ;[INF] 3, 2 + 1982 1982 002D0 713B23 clr1 PM3.3 ;[INF] 3, 2 + 1983 1983 002D3 ??eb01_iic_mcu_stop: + 1984 1984 ; line 732 : SAU0EN = 0; + 1985 1985 $DGL 0,7 + 1986 1986 002D3 7128F000 clr1 !PER0.2 ;[INF] 4, 2 + 1987 1987 ; line 733 : iic_mcu_initialized = 0; + 1988 1988 $DGL 0,8 + 1989 1989 002D7 R712300 clr1 _iic_mcu_initialized ;[INF] 3, 2 + 1990 1990 ; line 734 : } + 1991 1991 $DGL 0,9 + 1992 1992 002DA ??ef_iic_mcu_stop: + 1993 1993 002DA D7 ret ;[INF] 1, 6 + 1994 1994 002DB ??ee_iic_mcu_stop: + 1995 1995 + 1996 1996 ----- @@CODEL CSEG + 1997 1997 END + 1998 1998 + 1999 1999 + 2000 2000 ; *** Code Information *** + 2001 2001 ; + 2002 2002 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c + 2003 2003 ; + 2004 2004 ; $FUNC nop8(76) + 2005 2005 ; void=(void) + 2006 2006 ; CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes + 2007 2007 ; + 2008 2008 ; $FUNC iic_mcu_read_a_byte(87) + 2009 2009 ; bc=(unsigned char SLA:x, unsigned char adrs:[sp+4]) + 2010 2010 ; CODE SIZE= 111 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 10 bytes + 2011 2011 ; + 2012 2012 ; $CALL iic_mcu_start(93) + 2013 2013 ; void=(void) + 2014 2014 ; + 2015 2015 ; $CALL iic_mcu_call_slave(110) + 2016 2016 ; bc=(int:ax) + 2017 2017 ; + 2018 2018 ; $CALL iic_mcu_send_a_byte(118) + 2019 2019 ; bc=(int:ax) + 2020 2020 ; + 2021 2021 ; $CALL iic_mcu_send_re_st(122) + 2022 2022 ; void=(void) + 2023 2023 ; + 2024 2024 ; $CALL iic_mcu_send_a_byte(123) + 2025 2025 ; bc=(int:ax) + 2026 2026 ; + 2027 2027 ; $CALL iic_mcu_send_sp(139) + 2028 2028 ; void=(void) + 2029 2029 ; + 2030 2030 ; $FUNC iic_mcu_read(158) + 2031 2031 ; bc=(unsigned char slave:x, unsigned char adrs:[sp+4], + 2032 2032 ; unsigned char len:[sp+6], pointer dest:[sp+8]) + 2033 2033 ; CODE SIZE= 111 bytes, CLOCK_SIZE= 141 clocks, STACK_SIZE= 12 bytes + 2034 2034 ; + 2035 2035 ; $CALL iic_mcu_start(165) + 2036 2036 ; void=(void) + 2037 2037 ; + 2038 2038 ; $CALL iic_mcu_call_slave(188) + 2039 2039 ; bc=(int:ax) + 2040 2040 ; + 2041 2041 ; $CALL iic_mcu_send_a_byte(195) + 2042 2042 ; bc=(int:ax) + 2043 2043 ; + 2044 2044 ; $CALL iic_mcu_send_re_st(199) + 2045 2045 ; void=(void) + 2046 2046 ; + 2047 2047 ; $CALL iic_mcu_send_a_byte(200) + 2048 2048 ; bc=(int:ax) + 2049 2049 ; + 2050 2050 ; $CALL iic_mcu_send_sp(225) + 2051 2051 ; void=(void) + 2052 2052 ; + 2053 2053 ; $FUNC iic_mcu_write_a_byte(242) + 2054 2054 ; bc=(unsigned char SLA:x, unsigned char adrs:[sp+4], + 2055 2055 ; unsigned char dat:[sp+6]) + 2056 2056 ; CODE SIZE= 56 bytes, CLOCK_SIZE= 79 clocks, STACK_SIZE= 12 bytes + 2057 2057 ; + 2058 2058 ; $CALL iic_mcu_start(247) + 2059 2059 ; void=(void) + 2060 2060 ; + 2061 2061 ; $CALL iic_mcu_call_slave(266) + 2062 2062 ; bc=(int:ax) + 2063 2063 ; + 2064 2064 ; $CALL iic_mcu_send_a_byte(271) + 2065 2065 ; bc=(int:ax) + 2066 2066 ; + 2067 2067 ; $CALL iic_mcu_send_a_byte(272) + 2068 2068 ; bc=(int:ax) + 2069 2069 ; + 2070 2070 ; $CALL iic_mcu_send_sp(273) + 2071 2071 ; void=(void) + 2072 2072 ; + 2073 2073 ; $FUNC iic_mcu_write(297) + 2074 2074 ; bc=(unsigned char slave:x, unsigned char adrs:[sp+4], + 2075 2075 ; unsigned char len:[sp+6], pointer src:[sp+8]) + 2076 2076 ; CODE SIZE= 127 bytes, CLOCK_SIZE= 121 clocks, STACK_SIZE= 12 bytes + 2077 2077 ; + 2078 2078 ; $CALL iic_mcu_start(303) + 2079 2079 ; void=(void) + 2080 2080 ; + 2081 2081 ; $CALL iic_mcu_call_slave(327) + 2082 2082 ; bc=(int:ax) + 2083 2083 ; + 2084 2084 ; $FUNC int_dma1(388) + 2085 2085 ; void=(void) + 2086 2086 ; CODE SIZE= 108 bytes, CLOCK_SIZE= 86 clocks, STACK_SIZE= 26 bytes + 2087 2087 ; + 2088 2088 ; $CALL nop8(408) + 2089 2089 ; void=(void) + 2090 2090 ; + 2091 2091 ; $CALL nop8(423) + 2092 2092 ; void=(void) + 2093 2093 ; + 2094 2094 ; $FUNC int_iic10(452) + 2095 2095 ; void=(void) + 2096 2096 ; CODE SIZE= 109 bytes, CLOCK_SIZE= 83 clocks, STACK_SIZE= 26 bytes + 2097 2097 ; + 2098 2098 ; $CALL nop8(469) + 2099 2099 ; void=(void) + 2100 2100 ; + 2101 2101 ; $CALL nop8(484) + 2102 2102 ; void=(void) + 2103 2103 ; + 2104 2104 ; $FUNC iic_mcu_call_slave(513) + 2105 2105 ; bc=(unsigned char slave:x) + 2106 2106 ; CODE SIZE= 22 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes + 2107 2107 ; + 2108 2108 ; $CALL iic_mcu_send_st(514) + 2109 2109 ; void=(void) + 2110 2110 ; + 2111 2111 ; $CALL iic_mcu_send_a_byte(517) + 2112 2112 ; bc=(int:ax) + 2113 2113 ; + 2114 2114 ; $CALL iic_mcu_send_sp(519) + 2115 2115 ; void=(void) + 2116 2116 ; + 2117 2117 ; $FUNC iic_mcu_send_a_byte(533) + 2118 2118 ; bc=(unsigned char dat:x) + 2119 2119 ; CODE SIZE= 36 bytes, CLOCK_SIZE= 37 clocks, STACK_SIZE= 2 bytes + 2120 2120 ; + 2121 2121 ; $FUNC iic_mcu_send_st(556) + 2122 2122 ; void=(void) + 2123 2123 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 32 clocks, STACK_SIZE= 4 bytes + 2124 2124 ; + 2125 2125 ; $CALL nop8(558) + 2126 2126 ; void=(void) + 2127 2127 ; + 2128 2128 ; $FUNC iic_mcu_send_re_st(585) + 2129 2129 ; void=(void) + 2130 2130 ; CODE SIZE= 41 bytes, CLOCK_SIZE= 25 clocks, STACK_SIZE= 4 bytes + 2131 2131 ; + 2132 2132 ; $CALL nop8(588) + 2133 2133 ; void=(void) + 2134 2134 ; + 2135 2135 ; $CALL nop8(603) + 2136 2136 ; void=(void) + 2137 2137 ; + 2138 2138 ; $CALL iic_mcu_send_st(617) + 2139 2139 ; void=(void) + 2140 2140 ; + 2141 2141 ; $FUNC iic_mcu_send_sp(627) + 2142 2142 ; void=(void) + 2143 2143 ; CODE SIZE= 32 bytes, CLOCK_SIZE= 31 clocks, STACK_SIZE= 4 bytes + 2144 2144 ; + 2145 2145 ; $CALL nop8(631) + 2146 2146 ; void=(void) + 2147 2147 ; + 2148 2148 ; $CALL nop8(646) + 2149 2149 ; void=(void) + 2150 2150 ; + 2151 2151 ; $FUNC iic_mcu_start(670) + 2152 2152 ; void=(void) + 2153 2153 ; CODE SIZE= 92 bytes, CLOCK_SIZE= 65 clocks, STACK_SIZE= 4 bytes + 2154 2154 ; + 2155 2155 ; $CALL nop8(677) + 2156 2156 ; void=(void) + 2157 2157 ; + 2158 2158 ; $CALL iic_mcu_send_st(708) + 2159 2159 ; void=(void) + 2160 2160 ; + 2161 2161 ; $CALL iic_mcu_send_sp(712) + 2162 2162 ; void=(void) + 2163 2163 ; + 2164 2164 ; $FUNC iic_mcu_stop(726) + 2165 2165 ; void=(void) + 2166 2166 ; CODE SIZE= 38 bytes, CLOCK_SIZE= 35 clocks, STACK_SIZE= 4 bytes + 2167 2167 ; + 2168 2168 ; $CALL iic_mcu_send_re_st(730) + 2169 2169 ; void=(void) + 2170 2170 + 2171 2171 ; Target chip : uPD79F0104 + 2172 2172 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.3 @@BITS +00000 00030H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00008H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 002DBH ROM_CODE +00000 000D9H @@BASE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/i2c_mcu.rel b/branches/0.10(X3)/i2c_mcu.rel new file mode 100644 index 0000000..38ea88c Binary files /dev/null and b/branches/0.10(X3)/i2c_mcu.rel differ diff --git a/branches/0.10(X3)/i2c_twl.c b/branches/0.10(X3)/i2c_twl.c new file mode 100644 index 0000000..1df2e57 --- /dev/null +++ b/branches/0.10(X3)/i2c_twl.c @@ -0,0 +1,206 @@ +#pragma sfr /* 特殊機能レジスタ使用 */ + + + +/*============================================================================*/ +#include "incs.h" +#include "i2c_twl_defs.h" + + +extern u8 vreg_twl[]; + +#ifdef _MCU_BSR_ +//#ifdef _MODEL_TS0_ || _MODEL_WM0_ + +// ワーキングモデルはI2Cが逆 +#define ACKD ACKD0 +#define ACKE ACKE0 +#define COI COI0 +#define IICAEN IICA0EN +#define IICRSV IICRSV0 +#define IICA IICA0 +#define IICAIF IICAIF0 +#define IICAMK IICAMK0 +#define IICAPR0 IICAPR00 +#define IICAPR1 IICAPR10 +#define IICCTL0 IICCTL00 +#define IICE IICE0 +#define IICF IICF0 +#define IICS IICS0 +#define IICWH IICWH0 +#define IICWL IICWL0 +#define LREL LREL0 +#define SPD SPD0 +#define SPIE SPIE0 +#define STCEN STCEN0 +#define STD STD0 +#define SVA SVA0 +#define WREL WREL0 +#define WTIM WTIM0 +#define SMC SMC0 + +#endif + +#ifndef _MCU_BSR_ + +// ke3の時はダミー関数 +void IIC_twl_Stop( void ) +{ +} +void IIC_twl_Init( void ) +{ +} +#else + + +/*============================================================================*/ +u8 vreg_adrs; +u8 pre_dat; + + +u16 tot; + + +// 注！　↓はマクロなので、returnはメインループに戻ります。 +#define wait_next { \ + tot = 0; \ + while( IICAIF != 1 ){ \ + if( SPD ){ \ + LREL = 1; \ + return; \ + } \ + tot++; \ + if( tot == 0 ){ \ + LREL = 1; \ + return; \ + } \ + } \ +} + + +__interrupt void int_iic_twl( ) +{ + u8 temp; + u16 tot; + +// WDT_Restart(); + // フラグ１回目 スレーブアドレス,R/W +/* COI != 1 なら、割り込みはいらない + if( COI != 1 ){ // 被呼び出し？ + LREL = 1; // 呼ばれたのは他のID + return; + }else{ + ACKE0 = 1; // 自動でackを返すようにする + WREL = 1; // ウェイト解除して次のバイトを待つ + } + */ + WREL = 1; // ウェイト解除して次のバイトを待つ + wait_next; // １バイト受信完了を待つ + + // ２回目 R/W レジスタアドレス + temp = IICA; + IICAIF = 0; + WREL = 1; + + vreg_adrs = adrs_table_twl_ext2int( temp ); + + // ３回目 + // スタートコンディションか、データ受信完了フラグ待ち + + while( 1 ) + { + u8 my_iics = IICS; + + if( my_iics & 0x01 ) // SPD + { // 強制終了 + LREL = 1; + return; + } + else if( my_iics & 0x02 ) // ( STD && !SPD ) + { + // 送信 // (スタートコンディション検出) + pre_dat = vreg_twl_read( vreg_adrs ); // mcu内部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除 + + // 自局をRで呼ばれるのを待つ + wait_next; + IICAIF = 0; + if( COI != 1 ) + { // 被呼び出し？ + LREL = 1; // 呼ばれたのは他のID（あれ？） + return; + } + IICA = pre_dat; // データを送る。ウェイトも解除される。 + + wait_next; + // ４回目。(送信データ後の、ACK/NACK後)　どうしても発生してしまう。 + IICAIF = 0; // おしまい + LREL = 1; + return; + } + else if( IICAIF && (( my_iics & 0x03 ) == 0 )) // !STD && !SPD ) + { + // 受信 // + IICAIF = 0; + temp = IICA; + WREL = 1; + + // 通常アクセス(ライト) // + LREL = 1; // スタートコンディション待ちへ(連続書き込み未対応のため) + vreg_twl_write( vreg_adrs, temp ); + return; // 受信おしまい // + } + } +} + + + +/*****************************************************/ +void IIC_twl_Init( void ) +{ + + IICAEN = 1; + + IICE = 0; /* IICA disable */ + + IICAMK = 1; /* INTIICA disable */ + IICAIF = 0; /* clear INTIICA interrupt flag */ + + IICAPR0 = 0; /* set INTIICA high priority */ + IICAPR1 = 0; /* set INTIICA high priority */ + P20 &= ~0x3; + + SVA = IIC_T_SLAVEADDRESS; + IICF = 0x01; + + STCEN = 1; // リスタートの許可 + IICRSV = 1; // 通信予約をさせない:スレーブに徹する + + SPIE = 0; // ストップコンディションでの割り込みを禁止 + WTIM = 1; // 自動でACKを返した後clkをLに固定する + ACKE = 1; // ダメCPUは無視して次の通信をはじめるかもしれないんで早くclkを開放しないといけない + + IICWH = 5; + IICWL = 10; // L期間の長さ（？） + + SMC = 1; + + IICAMK = 0; // 割り込みを許可 + + IICE = 1; + + PM20 &= ~0x3; /* set clock pin for IICA */ + + LREL = 1; +} + + + +//**************************************************************************** +void IIC_twl_Stop( void ) +{ + IICE = 0; /* IICA disable */ + IICAEN = 0; +} + + +#endif diff --git a/branches/0.10(X3)/i2c_twl.h b/branches/0.10(X3)/i2c_twl.h new file mode 100644 index 0000000..0f608b0 --- /dev/null +++ b/branches/0.10(X3)/i2c_twl.h @@ -0,0 +1,7 @@ +#ifndef _iic_twl_ +#define _iic_twl_ + +void IIC_twl_Init( void ); +void IIC_twl_Stop( void ); + +#endif diff --git a/branches/0.10(X3)/i2c_twl.prn b/branches/0.10(X3)/i2c_twl.prn new file mode 100644 index 0000000..619af2f --- /dev/null +++ b/branches/0.10(X3)/i2c_twl.prn @@ -0,0 +1,797 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\i2c_twl.asm +Para-file: +In-file: inter_asm\i2c_twl.asm +Obj-file: i2c_twl.rel +Prn-file: i2c_twl.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c + 6 6 ; In-file : i2c_twl.c + 7 7 ; Asm-file : inter_asm\i2c_twl.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 06FH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, i2c_twl.c + 18 18 $DGS MOD_NAM, i2c_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 36 36 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 37 37 $DGS GLV_SYM, _int_iic_twl, U, U, 0E001H, 026H, 01H, 02H + 38 38 $DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H + 39 39 $DGS BEG_FUN, ??bf_int_iic_twl, U, U, 00H, 065H, 01H, 00H + 40 40 $DGS AUX_BEG, 052H, 01CH, 01BH + 41 41 $DGS AUT_VAR, _temp, 05H, 0FFFFH, 0CH, 01H, 00H, 00H + 42 42 $DGS AUT_VAR, _tot, 02H, 0FFFFH, 0DH, 01H, 00H, 00H + 43 43 $DGS BEG_BLK, ??bb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 44 44 $DGS AUX_BEG, 011H, 00H, 01DH + 45 45 $DGS BEG_BLK, ??bb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 46 46 $DGS AUX_BEG, 011H, 00H, 01FH + 47 47 $DGS BEG_BLK, ??bb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 48 48 $DGS AUX_BEG, 011H, 00H, 023H + 49 49 $DGS END_BLK, ??eb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 50 50 $DGS AUX_END, 011H + 51 51 $DGS BEG_BLK, ??bb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 52 52 $DGS AUX_BEG, 011H, 00H, 02BH + 53 53 $DGS END_BLK, ??eb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 54 54 $DGS AUX_END, 011H + 55 55 $DGS END_BLK, ??eb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 56 56 $DGS AUX_END, 011H + 57 57 $DGS END_BLK, ??eb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 58 58 $DGS AUX_END, 011H + 59 59 $DGS BEG_BLK, ??bb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 60 60 $DGS AUX_BEG, 01EH, 00H, 02FH + 61 61 $DGS AUT_VAR, _my_iics, 01H, 0FFFFH, 0CH, 01H, 01H, 00H + 62 62 $DGS AUX_STR, 00H, 01FH, 01H, 00H, 00H, 00H, 00H, 00H + 63 63 $DGS BEG_BLK, ??bb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 64 64 $DGS AUX_BEG, 022H, 00H, 033H + 65 65 $DGS END_BLK, ??eb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 66 66 $DGS AUX_END, 025H + 67 67 $DGS BEG_BLK, ??bb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 68 68 $DGS AUX_BEG, 027H, 00H, 035H + 69 69 $DGS BEG_BLK, ??bb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 70 70 $DGS AUX_BEG, 02CH, 00H, 037H + 71 71 $DGS BEG_BLK, ??bb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 72 72 $DGS AUX_BEG, 02CH, 00H, 039H + 73 73 $DGS BEG_BLK, ??bb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 74 74 $DGS AUX_BEG, 02CH, 00H, 03DH + 75 75 $DGS END_BLK, ??eb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 76 76 $DGS AUX_END, 02CH + 77 77 $DGS BEG_BLK, ??bb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_BEG, 02CH, 00H, 045H + 79 79 $DGS END_BLK, ??eb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 80 80 $DGS AUX_END, 02CH + 81 81 $DGS END_BLK, ??eb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 82 82 $DGS AUX_END, 02CH + 83 83 $DGS END_BLK, ??eb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 84 84 $DGS AUX_END, 02CH + 85 85 $DGS BEG_BLK, ??bb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 86 86 $DGS AUX_BEG, 02FH, 00H, 049H + 87 87 $DGS END_BLK, ??eb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_END, 032H + 89 89 $DGS BEG_BLK, ??bb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_BEG, 035H, 00H, 04BH + 91 91 $DGS BEG_BLK, ??bb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_BEG, 035H, 00H, 04DH + 93 93 $DGS BEG_BLK, ??bb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_BEG, 035H, 00H, 051H + 95 95 $DGS END_BLK, ??eb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_END, 035H + 97 97 $DGS BEG_BLK, ??bb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_BEG, 035H, 00H, 05BH + 99 99 $DGS END_BLK, ??eb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_END, 035H + 101 101 $DGS END_BLK, ??eb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_END, 035H + 103 103 $DGS END_BLK, ??eb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_END, 035H + 105 105 $DGS END_BLK, ??eb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_END, 03AH + 107 107 $DGS BEG_BLK, ??bb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_BEG, 03CH, 00H, 00H + 109 109 $DGS END_BLK, ??eb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_END, 046H + 111 111 $DGS END_BLK, ??eb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_END, 047H + 113 113 $DGS END_FUN, ??ef_int_iic_twl, U, U, 00H, 065H, 01H, 00H + 114 114 $DGS AUX_END, 048H + 115 115 $DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 026H, 01H, 02H + 116 116 $DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H + 117 117 $DGS BEG_FUN, ??bf_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H + 118 118 $DGS AUX_BEG, 09FH, 00H, 069H + 119 119 $DGS END_FUN, ??ef_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H + 120 120 $DGS AUX_END, 024H + 121 121 $DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 026H, 01H, 02H + 122 122 $DGS AUX_FUN, 00H, U, U, 06FH, 00H, 00H + 123 123 $DGS BEG_FUN, ??bf_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H + 124 124 $DGS AUX_BEG, 0C8H, 00H, 06FH + 125 125 $DGS END_FUN, ??ef_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H + 126 126 $DGS AUX_END, 04H + 127 127 $DGS GLV_SYM, _vreg_adrs, U, U, 0CH, 026H, 00H, 00H + 128 128 $DGS GLV_SYM, _pre_dat, U, U, 0CH, 026H, 00H, 00H + 129 129 $DGS GLV_SYM, _tot, U, U, 0DH, 026H, 00H, 00H + 130 130 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 131 131 $DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 02H, 01H, 02H + 132 132 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 133 133 $DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 02H, 01H, 02H + 134 134 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 135 135 $DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 02H, 01H, 02H + 136 136 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 137 137 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 138 138 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 139 139 + 140 140 EXTRN _@SEGAX + 141 141 EXTRN _@SEGDE + 142 142 EXTRN _@RTARG0 + 143 143 EXTRN _adrs_table_twl_ext2int + 144 144 EXTRN _vreg_twl_read + 145 145 EXTRN _vreg_twl_write + 146 146 PUBLIC _vreg_adrs + 147 147 PUBLIC _pre_dat + 148 148 PUBLIC _tot + 149 149 PUBLIC _int_iic_twl + 150 150 PUBLIC _IIC_twl_Init + 151 151 PUBLIC _IIC_twl_Stop + 152 152 + 153 153 ----- @@BITS BSEG + 154 154 + 155 155 ----- @@CNST CSEG MIRRORP + 156 156 00000 01 _lpf_coeff: DB 01H ; 1 + 157 157 00001 02 DB 02H ; 2 + 158 158 00002 02 DB 02H ; 2 + 159 159 00003 03 DB 03H ; 3 + 160 160 00004 03 DB 03H ; 3 + 161 161 00005 02 DB 02H ; 2 + 162 162 00006 00 DB 00H ; 0 + 163 163 00007 FE DB 0FEH ; 254 + 164 164 00008 FB DB 0FBH ; 251 + 165 165 00009 F7 DB 0F7H ; 247 + 166 166 0000A F3 DB 0F3H ; 243 + 167 167 0000B F0 DB 0F0H ; 240 + 168 168 0000C F0 DB 0F0H ; 240 + 169 169 0000D F3 DB 0F3H ; 243 + 170 170 0000E FA DB 0FAH ; 250 + 171 171 0000F 04 DB 04H ; 4 + 172 172 00010 12 DB 012H ; 18 + 173 173 00011 25 DB 025H ; 37 + 174 174 00012 38 DB 038H ; 56 + 175 175 00013 4D DB 04DH ; 77 + 176 176 00014 5F DB 05FH ; 95 + 177 177 00015 6E DB 06EH ; 110 + 178 178 00016 77 DB 077H ; 119 + 179 179 00017 7A DB 07AH ; 122 + 180 180 00018 77 DB 077H ; 119 + 181 181 00019 6E DB 06EH ; 110 + 182 182 0001A 5F DB 05FH ; 95 + 183 183 0001B 4D DB 04DH ; 77 + 184 184 0001C 38 DB 038H ; 56 + 185 185 0001D 25 DB 025H ; 37 + 186 186 0001E 12 DB 012H ; 18 + 187 187 0001F 04 DB 04H ; 4 + 188 188 00020 FA DB 0FAH ; 250 + 189 189 00021 F3 DB 0F3H ; 243 + 190 190 00022 F0 DB 0F0H ; 240 + 191 191 00023 F0 DB 0F0H ; 240 + 192 192 00024 F3 DB 0F3H ; 243 + 193 193 00025 F7 DB 0F7H ; 247 + 194 194 00026 FB DB 0FBH ; 251 + 195 195 00027 FE DB 0FEH ; 254 + 196 196 00028 00 DB 00H ; 0 + 197 197 00029 02 DB 02H ; 2 + 198 198 0002A 03 DB 03H ; 3 + 199 199 0002B 03 DB 03H ; 3 + 200 200 0002C 02 DB 02H ; 2 + 201 201 0002D 02 DB 02H ; 2 + 202 202 0002E 01 DB 01H ; 1 + 203 203 0002F 00 DB (1) + 204 204 + 205 205 ----- @@R_INIT CSEG UNIT64KP + 206 206 + 207 207 ----- @@INIT DSEG BASEP + 208 208 + 209 209 ----- @@DATA DSEG BASEP + 210 210 00000 _vreg_adrs: DS (1) + 211 211 00001 _pre_dat: DS (1) + 212 212 00002 _tot: DS (2) + 213 213 + 214 214 ----- @@R_INIS CSEG UNIT64KP + 215 215 + 216 216 ----- @@INIS DSEG SADDRP + 217 217 + 218 218 ----- @@DATS DSEG SADDRP + 219 219 + 220 220 ----- @@CNSTL CSEG PAGE64KP + 221 221 + 222 222 ----- @@RLINIT CSEG UNIT64KP + 223 223 + 224 224 ----- @@INITL DSEG UNIT64KP + 225 225 + 226 226 ----- @@DATAL DSEG UNIT64KP + 227 227 + 228 228 ----- @@CALT CSEG CALLT0 + 229 229 + 230 230 ; line 1 : #pragma sfr /* 特殊機能レジスタ使用 */ + 231 231 ; line 2 : + 232 232 ; line 3 : + 233 233 ; line 4 : + 234 234 ; line 5 : /*============================================================== + 235 235 ; ==============*/ + 236 236 ; line 6 : #include "incs.h" + 237 237 ; line 7 : #include "i2c_twl_defs.h" + 238 238 ; line 8 : + 239 239 ; line 9 : + 240 240 ; line 10 : extern u8 vreg_twl[]; + 241 241 ; line 11 : + 242 242 ; line 12 : #ifdef _MCU_BSR_ + 243 243 ; line 13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_ + 244 244 ; line 14 : + 245 245 ; line 15 : // ワーキングモデルはI2Cが逆 + 246 246 ; line 16 : #define ACKD ACKD0 + 247 247 ; line 17 : #define ACKE ACKE0 + 248 248 ; line 18 : #define COI COI0 + 249 249 ; line 19 : #define IICAEN IICA0EN + 250 250 ; line 20 : #define IICRSV IICRSV0 + 251 251 ; line 21 : #define IICA IICA0 + 252 252 ; line 22 : #define IICAIF IICAIF0 + 253 253 ; line 23 : #define IICAMK IICAMK0 + 254 254 ; line 24 : #define IICAPR0 IICAPR00 + 255 255 ; line 25 : #define IICAPR1 IICAPR10 + 256 256 ; line 26 : #define IICCTL0 IICCTL00 + 257 257 ; line 27 : #define IICE IICE0 + 258 258 ; line 28 : #define IICF IICF0 + 259 259 ; line 29 : #define IICS IICS0 + 260 260 ; line 30 : #define IICWH IICWH0 + 261 261 ; line 31 : #define IICWL IICWL0 + 262 262 ; line 32 : #define LREL LREL0 + 263 263 ; line 33 : #define SPD SPD0 + 264 264 ; line 34 : #define SPIE SPIE0 + 265 265 ; line 35 : #define STCEN STCEN0 + 266 266 ; line 36 : #define STD STD0 + 267 267 ; line 37 : #define SVA SVA0 + 268 268 ; line 38 : #define WREL WREL0 + 269 269 ; line 39 : #define WTIM WTIM0 + 270 270 ; line 40 : #define SMC SMC0 + 271 271 ; line 41 : + 272 272 ; line 42 : #endif + 273 273 ; line 43 : + 274 274 ; line 44 : #ifndef _MCU_BSR_ + 275 275 ; line 45 : + 276 276 ; line 46 : // ke3の時はダミー関数 + 277 277 ; line 47 : void IIC_twl_Stop( void ) + 278 278 ; line 48 : { + 279 279 ; line 49 : } + 280 280 ; line 50 : void IIC_twl_Init( void ) + 281 281 ; line 51 : { + 282 282 ; line 52 : } + 283 283 ; line 53 : #else + 284 284 ; line 54 : + 285 285 ; line 55 : + 286 286 ; line 56 : /*============================================================== + 287 287 ; ==============*/ + 288 288 ; line 57 : u8 vreg_adrs; + 289 289 ; line 58 : u8 pre_dat; + 290 290 ; line 59 : + 291 291 ; line 60 : + 292 292 ; line 61 : u16 tot; + 293 293 ; line 62 : + 294 294 ; line 63 : + 295 295 ; line 64 : // 注！　↓はマクロなので、returnはメインループに戻ります。 + 296 296 ; line 65 : #define wait_next { \ + 297 297 ; line 66 : tot = 0; \ + 298 298 ; line 67 : while( IICAIF != 1 ){ \ + 299 299 ; line 68 : if( SPD ){ \ + 300 300 ; line 69 : LREL = 1; \ + 301 301 ; line 70 : return; \ + 302 302 ; line 71 : } \ + 303 303 ; line 72 : tot++; \ + 304 304 ; line 73 : if( tot == 0 ){ \ + 305 305 ; line 74 : LREL = 1; \ + 306 306 ; line 75 : return; \ + 307 307 ; line 76 : } \ + 308 308 ; line 77 : } \ + 309 309 ; line 78 : } + 310 310 ; line 79 : + 311 311 ; line 80 : + 312 312 ; line 81 : __interrupt void int_iic_twl( ) + 313 313 ; line 82 : { + 314 314 + 315 315 ----- @@BASE CSEG BASE + 316 316 00000 _int_iic_twl: + 317 317 $DGL 1,21 + 318 318 00000 C1 push ax ;[INF] 1, 1 + 319 319 00001 C3 push bc ;[INF] 1, 1 + 320 320 00002 C5 push de ;[INF] 1, 1 + 321 321 00003 C7 push hl ;[INF] 1, 1 + 322 322 00004 520C mov c,#0CH ;[INF] 2, 1 + 323 323 00006 92 dec c ;[INF] 1, 1 + 324 324 00007 92 dec c ;[INF] 1, 1 + 325 325 00008 R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 326 326 0000B C1 push ax ;[INF] 1, 1 + 327 327 0000C DFF8 bnz $$-6 ;[INF] 2, 4 + 328 328 0000E 8EFD mov a,ES ;[INF] 2, 1 + 329 329 00010 70 mov x,a ;[INF] 1, 1 + 330 330 00011 8EFC mov a,CS ;[INF] 2, 1 + 331 331 00013 C1 push ax ;[INF] 1, 1 + 332 332 00014 2006 subw sp,#06H ;[INF] 2, 1 + 333 333 00016 FBF8FF movw hl,sp ;[INF] 3, 1 + 334 334 00019 ??bf_int_iic_twl: + 335 335 ; line 83 : u8 temp; + 336 336 ; line 84 : u16 tot; + 337 337 ; line 85 : + 338 338 ; line 86 : // WDT_Restart(); + 339 339 ; line 87 : // フラグ１回目 スレーブアドレス,R/W + 340 340 ; line 88 : /* COI != 1 なら、割り込みはいらない + 341 341 ; line 89 : if( COI != 1 ){ // 被呼び出し？ + 342 342 ; line 90 : LREL = 1; // 呼ばれたのは他のID + 343 343 ; line 91 : return; + 344 344 ; line 92 : }else{ + 345 345 ; line 93 : ACKE0 = 1; // 自動でackを返すようにする + 346 346 ; line 94 : WREL = 1; // ウェイト解除して次のバイトを待つ + 347 347 ; line 95 : } + 348 348 ; line 96 : */ + 349 349 ; line 97 : WREL = 1; // ウェイト解除して次のバイトを待 + 350 350 ; つ + 351 351 $DGL 0,16 + 352 352 00019 71503002 set1 !IICCTL00.5 ;[INF] 4, 2 + 353 353 ; line 98 : wait_next; // １バイト受信完了を待つ + 354 354 $DGL 0,17 + 355 355 0001D ??bb00_int_iic_twl: + 356 356 0001D F6 clrw ax ;[INF] 1, 1 + 357 357 0001E BC02 movw [hl+2],ax ; tot ;[INF] 2, 1 + 358 358 00020 ?L0003: + 359 359 00020 31B2E21B bt IF1L.3,$?L0004 ;[INF] 4, 5 + 360 360 00024 ??bb01_int_iic_twl: + 361 361 00024 31845107 bf IICS0.0,$?L0005 ;[INF] 4, 5 + 362 362 00028 ??bb02_int_iic_twl: + 363 363 00028 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 364 364 0002C REDFD00 br !?L0010 ;[INF] 3, 3 + 365 365 0002F ??eb02_int_iic_twl: + 366 366 0002F ?L0005: + 367 367 0002F 617902 incw [hl+2] ; tot ;[INF] 3, 2 + 368 368 00032 F6 clrw ax ;[INF] 1, 1 + 369 369 00033 614902 cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + 370 370 00036 DFE8 bnz $?L0003 ;[INF] 2, 4 + 371 371 00038 ??bb03_int_iic_twl: + 372 372 00038 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 373 373 0003C REDFD00 br !?L0010 ;[INF] 3, 3 + 374 374 0003F ??eb03_int_iic_twl: + 375 375 0003F ??eb01_int_iic_twl: + 376 376 0003F ?L0004: + 377 377 0003F ??eb00_int_iic_twl: + 378 378 ; line 99 : + 379 379 ; line 100 : // ２回目 R/W レジスタアドレス + 380 380 ; line 101 : temp = IICA; + 381 381 $DGL 0,20 + 382 382 0003F 8E50 mov a,IICA0 ;[INF] 2, 1 + 383 383 00041 9C05 mov [hl+5],a ; temp ;[INF] 2, 1 + 384 384 ; line 102 : IICAIF = 0; + 385 385 $DGL 0,21 + 386 386 00043 713BE2 clr1 IF1L.3 ;[INF] 3, 2 + 387 387 ; line 103 : WREL = 1; + 388 388 $DGL 0,22 + 389 389 00046 71503002 set1 !IICCTL00.5 ;[INF] 4, 2 + 390 390 ; line 104 : + 391 391 ; line 105 : vreg_adrs = adrs_table_twl_ext2int( temp ); + 392 392 $DGL 0,24 + 393 393 0004A 8C05 mov a,[hl+5] ; temp ;[INF] 2, 1 + 394 394 0004C 318E shrw ax,8 ;[INF] 2, 1 + 395 395 0004E RFD0000 call !_adrs_table_twl_ext2int ;[INF] 3, 3 + 396 396 00051 62 mov a,c ;[INF] 1, 1 + 397 397 00052 R9F0000 mov !_vreg_adrs,a ;[INF] 3, 1 + 398 398 ; line 106 : + 399 399 ; line 107 : // ３回目 + 400 400 ; line 108 : // スタートコンディションか、データ受信完了フラグ待ち + 401 401 ; line 109 : + 402 402 ; line 110 : while( 1 ) + 403 403 00055 ?L0009: + 404 404 ; line 111 : { + 405 405 00055 ??bb04_int_iic_twl: + 406 406 ; line 112 : u8 my_iics = IICS; + 407 407 $DGL 0,31 + 408 408 00055 8E51 mov a,IICS0 ;[INF] 2, 1 + 409 409 00057 9C01 mov [hl+1],a ; my_iics ;[INF] 2, 1 + 410 410 ; line 113 : + 411 411 ; line 114 : if( my_iics & 0x01 ) // SPD + 412 412 $DGL 0,33 + 413 413 00059 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 414 414 0005B D1 cmp0 a ;[INF] 1, 1 + 415 415 0005C DD07 bz $?L0011 ;[INF] 2, 4 + 416 416 ; line 115 : { // 強制終了 + 417 417 0005E ??bb05_int_iic_twl: + 418 418 ; line 116 : LREL = 1; + 419 419 $DGL 0,35 + 420 420 0005E 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 421 421 ; line 117 : return; + 422 422 $DGL 0,36 + 423 423 00062 REDFD00 br !?L0010 ;[INF] 3, 3 + 424 424 00065 ??eb05_int_iic_twl: + 425 425 ; line 118 : } + 426 426 00065 ?L0011: + 427 427 ; line 119 : else if( my_iics & 0x02 ) // ( STD && !SPD ) + 428 428 $DGL 0,38 + 429 429 00065 8C01 mov a,[hl+1] ; my_iics ;[INF] 2, 1 + 430 430 00067 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 431 431 00069 D1 cmp0 a ;[INF] 1, 1 + 432 432 0006A DD66 bz $?L0013 ;[INF] 2, 4 + 433 433 ; line 120 : { + 434 434 0006C ??bb06_int_iic_twl: + 435 435 ; line 121 : // 送信 // (スタートコンディション検出) + 436 436 ; line 122 : pre_dat = vreg_twl_read( vreg_adrs ); // mcu内 + 437 437 ; 部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除 + 438 438 $DGL 0,41 + 439 439 0006C RD90000 mov x,!_vreg_adrs ;[INF] 3, 1 + 440 440 0006F F1 clrb a ;[INF] 1, 1 + 441 441 00070 RFD0000 call !_vreg_twl_read ;[INF] 3, 3 + 442 442 00073 62 mov a,c ;[INF] 1, 1 + 443 443 00074 R9F0100 mov !_pre_dat,a ;[INF] 3, 1 + 444 444 ; line 123 : + 445 445 ; line 124 : // 自局をRで呼ばれるのを待つ + 446 446 ; line 125 : wait_next; + 447 447 $DGL 0,44 + 448 448 00077 ??bb07_int_iic_twl: + 449 449 00077 F6 clrw ax ;[INF] 1, 1 + 450 450 00078 BC02 movw [hl+2],ax ; tot ;[INF] 2, 1 + 451 451 0007A ?L0015: + 452 452 0007A 31B2E219 bt IF1L.3,$?L0016 ;[INF] 4, 5 + 453 453 0007E ??bb08_int_iic_twl: + 454 454 0007E 31845106 bf IICS0.0,$?L0017 ;[INF] 4, 5 + 455 455 00082 ??bb09_int_iic_twl: + 456 456 00082 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 457 457 00086 EF75 br $?L0010 ;[INF] 2, 3 + 458 458 00088 ??eb09_int_iic_twl: + 459 459 00088 ?L0017: + 460 460 00088 617902 incw [hl+2] ; tot ;[INF] 3, 2 + 461 461 0008B F6 clrw ax ;[INF] 1, 1 + 462 462 0008C 614902 cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + 463 463 0008F DFE9 bnz $?L0015 ;[INF] 2, 4 + 464 464 00091 ??bb0A_int_iic_twl: + 465 465 00091 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 466 466 00095 EF66 br $?L0010 ;[INF] 2, 3 + 467 467 00097 ??eb0A_int_iic_twl: + 468 468 ; line 126 : IICAIF = 0; + 469 469 $DGL 0,45 + 470 470 00097 ??eb08_int_iic_twl: + 471 471 00097 ?L0016: + 472 472 00097 ??eb07_int_iic_twl: + 473 473 00097 713BE2 clr1 IF1L.3 ;[INF] 3, 2 + 474 474 ; line 127 : if( COI != 1 ) + 475 475 $DGL 0,46 + 476 476 0009A 31C25106 bt IICS0.4,$?L0021 ;[INF] 4, 5 + 477 477 ; line 128 : { // 被呼び出し？ + 478 478 0009E ??bb0B_int_iic_twl: + 479 479 ; line 129 : LREL = 1; // 呼ばれたのは他のID（あれ？） + 480 480 $DGL 0,48 + 481 481 0009E 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 482 482 ; line 130 : return; + 483 483 $DGL 0,49 + 484 484 000A2 EF59 br $?L0010 ;[INF] 2, 3 + 485 485 000A4 ??eb0B_int_iic_twl: + 486 486 ; line 131 : } + 487 487 000A4 ?L0021: + 488 488 ; line 132 : IICA = pre_dat; // データを送る。ウェイトも解除さ + 489 489 ; れる。 + 490 490 $DGL 0,51 + 491 491 000A4 R8F0100 mov a,!_pre_dat ;[INF] 3, 1 + 492 492 000A7 9E50 mov IICA0,a ;[INF] 2, 1 + 493 493 ; line 133 : + 494 494 ; line 134 : wait_next; + 495 495 $DGL 0,53 + 496 496 000A9 ??bb0C_int_iic_twl: + 497 497 000A9 F6 clrw ax ;[INF] 1, 1 + 498 498 000AA BC02 movw [hl+2],ax ; tot ;[INF] 2, 1 + 499 499 000AC ?L0023: + 500 500 000AC 31B2E219 bt IF1L.3,$?L0024 ;[INF] 4, 5 + 501 501 000B0 ??bb0D_int_iic_twl: + 502 502 000B0 31845106 bf IICS0.0,$?L0025 ;[INF] 4, 5 + 503 503 000B4 ??bb0E_int_iic_twl: + 504 504 000B4 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 505 505 000B8 EF43 br $?L0010 ;[INF] 2, 3 + 506 506 000BA ??eb0E_int_iic_twl: + 507 507 000BA ?L0025: + 508 508 000BA 617902 incw [hl+2] ; tot ;[INF] 3, 2 + 509 509 000BD F6 clrw ax ;[INF] 1, 1 + 510 510 000BE 614902 cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + 511 511 000C1 DFE9 bnz $?L0023 ;[INF] 2, 4 + 512 512 000C3 ??bb0F_int_iic_twl: + 513 513 000C3 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 514 514 000C7 EF34 br $?L0010 ;[INF] 2, 3 + 515 515 000C9 ??eb0F_int_iic_twl: + 516 516 ; line 135 : // ４回目。(送信データ後の、ACK/NACK後)　どうしても発 + 517 517 ; 生してしまう。 + 518 518 000C9 ??eb0D_int_iic_twl: + 519 519 000C9 ?L0024: + 520 520 000C9 ??eb0C_int_iic_twl: + 521 521 ; line 136 : IICAIF = 0; // おしまい + 522 522 $DGL 0,55 + 523 523 000C9 713BE2 clr1 IF1L.3 ;[INF] 3, 2 + 524 524 ; line 137 : LREL = 1; + 525 525 $DGL 0,56 + 526 526 000CC 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 527 527 ; line 138 : return; + 528 528 $DGL 0,57 + 529 529 000D0 EF2B br $?L0010 ;[INF] 2, 3 + 530 530 000D2 ??eb06_int_iic_twl: + 531 531 ; line 139 : } + 532 532 000D2 ?L0013: + 533 533 ; line 140 : else if( IICAIF && (( my_iics & 0x03 ) == 0 )) // !STD + 534 534 ; && !SPD ) + 535 535 $DGL 0,59 + 536 536 000D2 31B4E224 bf IF1L.3,$?L0029 ;[INF] 4, 5 + 537 537 000D6 8C01 mov a,[hl+1] ; my_iics ;[INF] 2, 1 + 538 538 000D8 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 539 539 000DA D1 cmp0 a ;[INF] 1, 1 + 540 540 000DB DF1D bnz $?L0029 ;[INF] 2, 4 + 541 541 ; line 141 : { + 542 542 000DD ??bb10_int_iic_twl: + 543 543 ; line 142 : // 受信 // + 544 544 ; line 143 : IICAIF = 0; + 545 545 $DGL 0,62 + 546 546 000DD 713BE2 clr1 IF1L.3 ;[INF] 3, 2 + 547 547 ; line 144 : temp = IICA; + 548 548 $DGL 0,63 + 549 549 000E0 8E50 mov a,IICA0 ;[INF] 2, 1 + 550 550 000E2 9C05 mov [hl+5],a ; temp ;[INF] 2, 1 + 551 551 ; line 145 : WREL = 1; + 552 552 $DGL 0,64 + 553 553 000E4 71503002 set1 !IICCTL00.5 ;[INF] 4, 2 + 554 554 ; line 146 : + 555 555 ; line 147 : // 通常アクセス(ライト) // + 556 556 ; line 148 : LREL = 1; // スタートコンディション待ちへ( + 557 557 ; 連続書き込み未対応のため) + 558 558 $DGL 0,67 + 559 559 000E8 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 560 560 ; line 149 : vreg_twl_write( vreg_adrs, temp ); + 561 561 $DGL 0,68 + 562 562 000EC 8C05 mov a,[hl+5] ; temp ;[INF] 2, 1 + 563 563 000EE 318E shrw ax,8 ;[INF] 2, 1 + 564 564 000F0 C1 push ax ;[INF] 1, 1 + 565 565 000F1 RD90000 mov x,!_vreg_adrs ;[INF] 3, 1 + 566 566 000F4 RFD0000 call !_vreg_twl_write ;[INF] 3, 3 + 567 567 000F7 C0 pop ax ;[INF] 1, 1 + 568 568 ; line 150 : return; // 受信おしまい // + 569 569 $DGL 0,69 + 570 570 000F8 EF03 br $?L0010 ;[INF] 2, 3 + 571 571 000FA ??eb10_int_iic_twl: + 572 572 ; line 151 : } + 573 573 000FA ?L0029: + 574 574 000FA ??eb04_int_iic_twl: + 575 575 ; line 152 : } + 576 576 $DGL 0,71 + 577 577 000FA RED5500 br !?L0009 ;[INF] 3, 3 + 578 578 000FD ?L0010: + 579 579 ; line 153 : } + 580 580 $DGL 0,72 + 581 581 000FD ??ef_int_iic_twl: + 582 582 000FD 1006 addw sp,#06H ;[INF] 2, 1 + 583 583 000FF C0 pop ax ;[INF] 1, 1 + 584 584 00100 9EFC mov CS,a ;[INF] 2, 1 + 585 585 00102 60 mov a,x ;[INF] 1, 1 + 586 586 00103 9EFD mov ES,a ;[INF] 2, 1 + 587 587 00105 R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 588 588 00108 5206 mov c,#06H ;[INF] 2, 1 + 589 589 0010A C0 pop ax ;[INF] 1, 1 + 590 590 0010B B9 movw [de],ax ;[INF] 1, 1 + 591 591 0010C A5 incw de ;[INF] 1, 1 + 592 592 0010D A5 incw de ;[INF] 1, 1 + 593 593 0010E 92 dec c ;[INF] 1, 1 + 594 594 0010F DFF9 bnz $$-5 ;[INF] 2, 4 + 595 595 00111 C6 pop hl ;[INF] 1, 1 + 596 596 00112 C4 pop de ;[INF] 1, 1 + 597 597 00113 C2 pop bc ;[INF] 1, 1 + 598 598 00114 C0 pop ax ;[INF] 1, 1 + 599 599 00115 61FC reti ;[INF] 2, 6 + 600 600 00117 ??ee_int_iic_twl: + 601 601 ; line 154 : + 602 602 ; line 155 : + 603 603 ; line 156 : + 604 604 ; line 157 : /*****************************************************/ + 605 605 ; line 158 : void IIC_twl_Init( void ) + 606 606 ; line 159 : { + 607 607 + 608 608 ----- ROM_CODE CSEG BASE + 609 609 00000 _IIC_twl_Init: + 610 610 $DGL 1,99 + 611 611 00000 ??bf_IIC_twl_Init: + 612 612 ; line 160 : + 613 613 ; line 161 : IICAEN = 1; + 614 614 $DGL 0,3 + 615 615 00000 7140F000 set1 !PER0.4 ;[INF] 4, 2 + 616 616 ; line 162 : + 617 617 ; line 163 : IICE = 0; /* IICA disable */ + 618 618 $DGL 0,5 + 619 619 00004 71783002 clr1 !IICCTL00.7 ;[INF] 4, 2 + 620 620 ; line 164 : + 621 621 ; line 165 : IICAMK = 1; /* INTIICA disable */ + 622 622 $DGL 0,7 + 623 623 00008 713AE6 set1 MK1L.3 ;[INF] 3, 2 + 624 624 ; line 166 : IICAIF = 0; /* clear INTIICA interrupt flag + 625 625 ; */ + 626 626 $DGL 0,8 + 627 627 0000B 713BE2 clr1 IF1L.3 ;[INF] 3, 2 + 628 628 ; line 167 : + 629 629 ; line 168 : IICAPR0 = 0; /* set INTIICA high priority */ + 630 630 $DGL 0,10 + 631 631 0000E 713BEA clr1 PR01L.3 ;[INF] 3, 2 + 632 632 ; line 169 : IICAPR1 = 0; /* set INTIICA high priority */ + 633 633 $DGL 0,11 + 634 634 00011 713BEE clr1 PR11L.3 ;[INF] 3, 2 + 635 635 ; line 170 : P20 &= ~0x3; + 636 636 $DGL 0,12 + 637 637 00014 8F1005 mov a,!P20 ;[INF] 3, 1 + 638 638 00017 5CFC and a,#0FCH ; 252 ;[INF] 2, 1 + 639 639 00019 9F1005 mov !P20,a ;[INF] 3, 1 + 640 640 ; line 171 : + 641 641 ; line 172 : SVA = IIC_T_SLAVEADDRESS; + 642 642 $DGL 0,14 + 643 643 0001C CF34024A mov !SVA0,#04AH ; 74 ;[INF] 4, 1 + 644 644 ; line 173 : IICF = 0x01; + 645 645 $DGL 0,15 + 646 646 00020 E552FF oneb !IICF0 ;[INF] 3, 1 + 647 647 ; line 174 : + 648 648 ; line 175 : STCEN = 1; // リスタートの許可 + 649 649 $DGL 0,17 + 650 650 00023 711A52 set1 IICF0.1 ;[INF] 3, 2 + 651 651 ; line 176 : IICRSV = 1; // 通信予約をさせない:スレーブに + 652 652 ; 徹する + 653 653 $DGL 0,18 + 654 654 00026 710A52 set1 IICF0.0 ;[INF] 3, 2 + 655 655 ; line 177 : + 656 656 ; line 178 : SPIE = 0; // ストップコンディションでの割り + 657 657 ; 込みを禁止 + 658 658 $DGL 0,20 + 659 659 00029 71483002 clr1 !IICCTL00.4 ;[INF] 4, 2 + 660 660 ; line 179 : WTIM = 1; // 自動でACKを返した後clkをLに固 + 661 661 ; 定する + 662 662 $DGL 0,21 + 663 663 0002D 71303002 set1 !IICCTL00.3 ;[INF] 4, 2 + 664 664 ; line 180 : ACKE = 1; // ダメCPUは無視して次の通信をは + 665 665 ; じめるかもしれないんで早くclkを開放しないといけない + 666 666 $DGL 0,22 + 667 667 00031 71203002 set1 !IICCTL00.2 ;[INF] 4, 2 + 668 668 ; line 181 : + 669 669 ; line 182 : IICWH = 5; + 670 670 $DGL 0,24 + 671 671 00035 CF330205 mov !IICWH0,#05H ; 5 ;[INF] 4, 1 + 672 672 ; line 183 : IICWL = 10; // L期間の長さ（？） + 673 673 $DGL 0,25 + 674 674 00039 CF32020A mov !IICWL0,#0AH ; 10 ;[INF] 4, 1 + 675 675 ; line 184 : + 676 676 ; line 185 : SMC = 1; + 677 677 $DGL 0,27 + 678 678 0003D 71303102 set1 !IICCTL10.3 ;[INF] 4, 2 + 679 679 ; line 186 : + 680 680 ; line 187 : IICAMK = 0; // 割り込みを許可 + 681 681 $DGL 0,29 + 682 682 00041 713BE6 clr1 MK1L.3 ;[INF] 3, 2 + 683 683 ; line 188 : + 684 684 ; line 189 : IICE = 1; + 685 685 $DGL 0,31 + 686 686 00044 71703002 set1 !IICCTL00.7 ;[INF] 4, 2 + 687 687 ; line 190 : + 688 688 ; line 191 : PM20 &= ~0x3; /* set clock pin for IICA */ + 689 689 $DGL 0,33 + 690 690 00048 8F1105 mov a,!PM20 ;[INF] 3, 1 + 691 691 0004B 5CFC and a,#0FCH ; 252 ;[INF] 2, 1 + 692 692 0004D 9F1105 mov !PM20,a ;[INF] 3, 1 + 693 693 ; line 192 : + 694 694 ; line 193 : LREL = 1; + 695 695 $DGL 0,35 + 696 696 00050 71603002 set1 !IICCTL00.6 ;[INF] 4, 2 + 697 697 ; line 194 : } + 698 698 $DGL 0,36 + 699 699 00054 ??ef_IIC_twl_Init: + 700 700 00054 D7 ret ;[INF] 1, 6 + 701 701 00055 ??ee_IIC_twl_Init: + 702 702 ; line 195 : + 703 703 ; line 196 : + 704 704 ; line 197 : + 705 705 ; line 198 : //************************************************************** + 706 706 ; ************** + 707 707 ; line 199 : void IIC_twl_Stop( void ) + 708 708 ; line 200 : { + 709 709 00055 _IIC_twl_Stop: + 710 710 $DGL 1,105 + 711 711 00055 ??bf_IIC_twl_Stop: + 712 712 ; line 201 : IICE = 0; /* IICA disable */ + 713 713 $DGL 0,2 + 714 714 00055 71783002 clr1 !IICCTL00.7 ;[INF] 4, 2 + 715 715 ; line 202 : IICAEN = 0; + 716 716 $DGL 0,3 + 717 717 00059 7148F000 clr1 !PER0.4 ;[INF] 4, 2 + 718 718 ; line 203 : } + 719 719 $DGL 0,4 + 720 720 0005D ??ef_IIC_twl_Stop: + 721 721 0005D D7 ret ;[INF] 1, 6 + 722 722 0005E ??ee_IIC_twl_Stop: + 723 723 + 724 724 ----- @@CODEL CSEG + 725 725 END + 726 726 + 727 727 + 728 728 ; *** Code Information *** + 729 729 ; + 730 730 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c + 731 731 ; + 732 732 ; $FUNC int_iic_twl(82) + 733 733 ; void=(void) + 734 734 ; CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes + 735 735 ; + 736 736 ; $CALL adrs_table_twl_ext2int(105) + 737 737 ; bc=(int:ax) + 738 738 ; + 739 739 ; $CALL vreg_twl_read(122) + 740 740 ; bc=(int:ax) + 741 741 ; + 742 742 ; $CALL vreg_twl_write(149) + 743 743 ; void=(int:ax, int:[sp+4]) + 744 744 ; + 745 745 ; $FUNC IIC_twl_Init(159) + 746 746 ; void=(void) + 747 747 ; CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes + 748 748 ; + 749 749 ; $FUNC IIC_twl_Stop(200) + 750 750 ; void=(void) + 751 751 ; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 752 752 + 753 753 ; Target chip : uPD79F0104 + 754 754 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00004H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00117H @@BASE +00000 0005EH ROM_CODE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/i2c_twl.rel b/branches/0.10(X3)/i2c_twl.rel new file mode 100644 index 0000000..32028d8 Binary files /dev/null and b/branches/0.10(X3)/i2c_twl.rel differ diff --git a/branches/0.10(X3)/i2c_twl_defs.h b/branches/0.10(X3)/i2c_twl_defs.h new file mode 100644 index 0000000..be5d566 --- /dev/null +++ b/branches/0.10(X3)/i2c_twl_defs.h @@ -0,0 +1,196 @@ +#ifndef _MDSERIAL_ +#define _MDSERIAL_ + + +/* IIC operation enable (IICE0) */ +#define IIC0_OPERATION 0x80 +#define IIC0_OPERATION_DISABLE 0x00 /* stop operation */ +#define IIC0_OPERATION_ENABLE 0x80 /* enable operation */ + +/* Exit from communications (LREL0) */ +#define IIC0_COMMUNICATION 0x40 +#define IIC0_COMMUNICATION_NORMAL 0x00 /* normal operation */ +#define IIC0_COMMUNICATION_EXIT 0x40 /* exit from current communication */ + +/* Wait cancellation (WREL0) */ +#define IIC0_WAITCANCEL 0x20 +#define IIC0_WAIT_NOTCANCEL 0x00 /* do not cancel wait */ +#define IIC0_WAIT_CANCEL 0x20 /* cancel wait */ + +/* Generation of interrupt when stop condition (SPIE0) */ +#define IIC0_STOPINT 0x10 +#define IIC0_STOPINT_DISABLE 0x00 /* disable */ +#define IIC0_STOPINT_ENABLE 0x10 /* enable */ + +/* Wait and interrupt generation (WTIM0) */ +#define IIC0_WAITINT 0x08 +#define IIC0_WAITINT_CLK8FALLING 0x00 /* generate at the eighth clocks falling edge */ +#define IIC0_WAITINT_CLK9FALLING 0x08 /* generated at the ninth clocks falling edge */ + +/* Acknowledgement control (ACKE0) */ +#define IIC0_ACK 0x04 +#define IIC0_ACK_DISABLE 0x00 /* enable acknowledgement */ +#define IIC0_ACK_ENABLE 0x04 /* disable acknowledgement */ + +/* Start condition trigger (STT0) */ +#define IIC0_STARTCONDITION 0x02 +#define IIC0_START_NOTGENERATE 0x00 /* do not generate start condition */ +#define IIC0_START_GENERATE 0x02 /* generate start condition */ + +/* Stop condition trigger (SPT0) */ +#define IIC0_STOPCONDITION 0x01 +#define IIC0_STOP_NOTGENERATE 0x00 /* do not generate stop condition */ +#define IIC0_STOP_GENERATE 0x01 /* generate stop condition */ + +/* + IIC Status Register 0 (IICS0) +*/ +/* Master device status (MSTS0) */ +#define IIC0_MASTERSTATUS 0x80 +#define IIC0_STATUS_NOTMASTER 0x00 /* slave device status or communication standby status */ +#define IIC0_STATUS_MASTER 0x80 /* master device communication status */ + +/* Detection of arbitration loss (ALD0) */ +#define IIC0_ARBITRATION 0x40 +#define IIC0_ARBITRATION_NO 0x00 /* arbitration win or no arbitration */ +#define IIC0_ARBITRATION_LOSS 0x40 /* arbitration loss */ + +/* Detection of extension code reception (EXC0) */ +#define IIC0_EXTENSIONCODE 0x20 +#define IIC0_EXTCODE_NOT 0x00 /* extension code not received */ +#define IIC0_EXTCODE_RECEIVED 0x20 /* extension code received */ + +/* Detection of matching addresses (COI0) */ +#define IIC0_ADDRESSMATCH 0x10 +#define IIC0_ADDRESS_NOTMATCH 0x00 /* addresses do not match */ +#define IIC0_ADDRESS_MATCH 0x10 /* addresses match */ + +/* Detection of transmit/receive status (TRC0) */ +#define IIC0_STATUS 0x08 +#define IIC0_STATUS_RECEIVE 0x00 /* receive status */ +#define IIC0_STATUS_TRANSMIT 0x08 /* transmit status */ + +/* Detection of acknowledge signal (ACKD0) */ +#define IIC0_ACKDETECTION 0x04 +#define IIC0_ACK_NOTDETECTED 0x00 /* ACK signal was not detected */ +#define IIC0_ACK_DETECTED 0x04 /* ACK signal was detected */ + +/* Detection of start condition (STD0) */ +#define IIC0_STARTDETECTION 0x02 +#define IIC0_START_NOTDETECTED 0x00 /* start condition not detected */ +#define IIC0_START_DETECTED 0x02 /* start condition detected */ + +/* Detection of stop condition (SPD0) */ +#define IIC0_STOPDETECTION 0x01 +#define IIC0_STOP_NOTDETECTED 0x00 /* stop condition not detected */ +#define IIC0_STOP_DETECTED 0x01 /* stop condition detected */ + +/* + IIC Flag Register 0 (IICF0) +*/ +/* STT0 clear flag (STCF) */ +#define IIC0_STARTFLAG 0x80 +#define IIC0_STARTFLAG_GENERATE 0x00 /* generate start condition */ +#define IIC0_STARTFLAG_UNSUCCESSFUL 0x80 /* start condition generation unsuccessful */ + +/* IIC bus status flag (IICBSY) */ +#define IIC0_BUSSTATUS 0x40 +#define IIC0_BUS_RELEASE 0x00 /* bus release status */ +#define IIC0_BUS_COMMUNICATION 0x40 /* bus communication status */ + +/* Initial start enable trigger (STCEN) */ +#define IIC0_STARTWITHSTOP 0x02 +#define IIC0_START_WITHSTOP 0x00 /* generation of a start condition without detecting a stop condition */ +#define IIC0_START_WITHOUTSTOP 0x02 /* generation of a start condition upon detection of a stop condition */ + +/* Communication reservation function disable bit (IICRSV) */ +#define IIC0_RESERVATION 0x01 +#define IIC0_RESERVATION_ENABLE 0x00 /* enable communication reservation */ +#define IIC0_RESERVATION_DISABLE 0x01 /* disable communication reservation */ + +/* + IIC clock selection register 0 (IICCL0) +*/ +#define IICCL0_INITIALVALUE 0x00 +/* Detection of SCL0 pin level (CLD0) */ +#define IIC0_SCLLEVEL 0x20 +#define IIC0_SCL_LOW 0x00 /* clock line at low level */ +#define IIC0_SCL_HIGH 0x20 /* clock line at high level */ + +/* Detection of SDA0 pin level (DAD0) */ +#define IIC0_SDALEVEL 0x10 +#define IIC0_SDA_LOW 0x00 /* data line at low level */ +#define IIC0_SDA_HIGH 0x10 /* data line at high level */ + +/* Operation mode switching (SMC0) */ +#define IIC0_OPERATIONMODE 0x08 +#define IIC0_MODE_STANDARD 0x00 /* operates in standard mode */ +#define IIC0_MODE_HIGHSPEED 0x08 /* operates in high-speed mode */ + +/* Digital filter operation control (DFC0) */ +#define IIC0_DIGITALFILTER 0x04 +#define IIC0_FILTER_OFF 0x00 /* digital filter off */ +#define IIC0_FILTER_ON 0x04 /* digital filter on */ + +/* Operation mode switching (CL01, CL00) */ +#define IIC0_CLOCKSELECTION 0x03 + +/* Combine of (SMC0, CL01, CL00)*/ +#define IIC0_CLOCK0 0x00 +#define IIC0_CLOCK1 0x01 +#define IIC0_CLOCK2 0x02 +#define IIC0_CLOCK3 0x03 +#define IIC0_CLOCK4 0x08 +#define IIC0_CLOCK5 0x09 +#define IIC0_CLOCK6 0x0a +#define IIC0_CLOCK7 0x0b + +/* + IIC function expansion register 0 (IICX0) +*/ +/* IIC clock expension (CLX0) */ +#define IIC0_CLOCKEXPENSION 0x01 +#define IIC0_EXPENSION0 0x00 +#define IIC0_EXPENSION1 0x01 + +/* Operation clock (CLX0, SMC0, CL01, CL00) + | IIC0_EXPENSION0 | IIC0_EXPENSION1 | +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK0 | fprs/2 | prohibited | selection clock(fw) + | fprs/88 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK1 | fprs/2 | prohibited | selection clock(fw) + | fprs/172 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK2 | fprs/2 | prohibited | selection clock(fw) + | fprs/344 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK3 |prohibited/fexscl0 | prohibited | selection clock(fw) + | fw/66 | | transfer clock + | normal | | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK4 | fprs/2 | fprs/2 | selection clock(fw) + | fprs/48 | fprs/24 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK5 | fprs/2 | fprs/2 | selection clock(fw) + | fprs/48 | fprs/24 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK6 | fprs/4 | fprs/4 | selection clock(fw) + | fprs/96 | fprs/48 | transfer clock + | high speed | high speed | mode +------------|-------------------|-------------------|---------------------- +IIC0_CLOCK7 |prohibited/fexscl0 | prohibited | selection clock(fw) + | fw/18 | | transfer clock + | high speed | | mode +------------|-------------------|-------------------|---------------------- +*/ + +#define ADDRESS_COMPLETE 0x80 +#define IIC_MASTER_FLAG_CLEAR 0x00 + +#endif diff --git a/branches/0.10(X3)/incs.h b/branches/0.10(X3)/incs.h new file mode 100644 index 0000000..160ca82 --- /dev/null +++ b/branches/0.10(X3)/incs.h @@ -0,0 +1,36 @@ +#pragma SFR +#pragma di +#pragma ei +#pragma nop +#pragma stop +#pragma halt + +#pragma section @@CODE ROM_CODE +//#pragma section @@CNST ROM_CNST + +//========================================================= +#ifndef _incs_h_ +#define _incs_h_ + +#define _mcu_ + +#include "jhl_defs.h" +#include "user_define.h" + +#include "bsr_system.h" +#include "renge.h" + +#include "vreg_ctr.h" +#include "vreg_twl.h" + +#include "i2c_mcu.h" + +#include "rtc.h" + +#include "accero.h" + + +//========================================================= +err firm_update( ); + +#endif diff --git a/branches/0.10(X3)/incs_loader.h b/branches/0.10(X3)/incs_loader.h new file mode 100644 index 0000000..4df1329 --- /dev/null +++ b/branches/0.10(X3)/incs_loader.h @@ -0,0 +1,38 @@ +#pragma SFR +#pragma di +#pragma ei +#pragma nop +#pragma stop +#pragma halt + + +#pragma section @@CODE LDR_CODE +#pragma section @@CODEL LDR_CODL + +//#pragma section @@R_INIT FSL_RINT // これやるとスタートアップルーチンが初期値を +//#pragma section @@CNST FSL_CNST // セットしてくれない +#pragma section @@CNSTL LDR_CNSL + + + +//========================================================= +#include "jhl_defs.h" +#include "user_define.h" + +#include "bsr_system.h" +#include "renge.h" + +#include "vreg_ctr.h" +#include "vreg_twl.h" + +#include "loader.h" + +#include "i2c_mcu.h" + +#include "WDT.h" + + + +//========================================================= +err firm_update( ); +err firm_restore( ); diff --git a/branches/0.10(X3)/ini_VECT.c b/branches/0.10(X3)/ini_VECT.c new file mode 100644 index 0000000..f992a4c --- /dev/null +++ b/branches/0.10(X3)/ini_VECT.c @@ -0,0 +1,283 @@ +#pragma nop + + +#include "config.h" + +//#pragma interrupt INTWDTI fn_intwdti // 未使用 +//#pragma interrupt INTLVI fn_intlvi // 未使用 + +//#pragma interrupt INTP0 intp0_slp // SLP (CPUより、要求) ポーリング +//#pragma interrupt INTP1 fn_intp1 // (I2C) +//#pragma interrupt INTP2 fn_intp2 // (I2C) +//#pragma interrupt INTP3 fn_intp3 // 未搭載 +#pragma interrupt INTP4 intp4_extdc // EXTDC, ただし電源offから起こすのみ。通常はポーリング +#pragma interrupt INTP5 intp5_shell // SHELL_CLOSE, ただし電源offから起こすのみ。通常はポーリング +#pragma interrupt INTP6 intp6_PM_irq // CODEC経由で旧PMICへのコマンド書き込み + +//#ifdef _MCU_BSR_ // 割り込みそのものは使いません +//#pragma interrupt INTP21 intp21_RFTx // 電波送信パルス +//#else +//#pragma interrupt INTP7 intp21_RFTx +//#endif + +#ifdef _MCU_BSR_ +#pragma interrupt INTP23 intp23_ACC_ready // 加速度センサ、データ準備完了 +#endif + +//#pragma interrupt INTCMP0 fn_intcmp0 +//#pragma interrupt INTCMP1 fn_intcmp1 +//#pragma interrupt INTDMA0 fn_intdma0 +#pragma interrupt INTDMA1 int_dma1 + +//#pragma interrupt INTST0 fn_intst0 +/* #pragma interrupt INTCSI00 fn_intcsi00 */ +//#pragma interrupt INTSR0 fn_intsr0 +/* #pragma interrupt INTCSI01 fn_intcsi01 */ +//#pragma interrupt INTSRE0 fn_intsre0 + +//#pragma interrupt INTST1 fn_intst1 +/* #pragma interrupt INTCSI10 fn_intcsi10 */ +#pragma interrupt INTIIC10 int_iic10 +//#pragma interrupt INTSR1 fn_intsr1 +//#pragma interrupt INTSRE1 fn_intsre1 + + +#ifdef _MCU_KE3_ +#pragma interrupt INTIICA int_iic_ctr // CTR側 +#else + +// TSはマザボでテレコ、WMは回路図がテレコで結局一致… +#pragma interrupt INTIICA0 int_iic_twl +#pragma interrupt INTIICA1 int_iic_ctr +#endif + +//#pragma interrupt INTTM00 fn_inttm00 +//#pragma interrupt INTTM01 fn_inttm01 +//#pragma interrupt INTTM02 fn_inttm02 +//#pragma interrupt INTTM03 fn_inttm03 + +#pragma interrupt INTAD int_adc +#pragma interrupt INTRTC int_rtc +#pragma interrupt INTRTCI int_rtc_int +#pragma interrupt INTKR int_kr +//#pragma interrupt INTMD fn_intmd + +//#pragma interrupt INTTM04 fn_inttm04 +//#pragma interrupt INTTM05 fn_inttm05 +//#pragma interrupt INTTM06 fn_inttm06 +//#pragma interrupt INTTM07 fn_inttm07 + + +/****************************************************/ +/* 未使用時のダミー関数定義 */ +/****************************************************/ +__interrupt void fn_intwdti( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_intlvi( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_intp0(){ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_intp1( ) +{ + while( 1 ) + { + NOP(); + } +} // +__interrupt void fn_intp2( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_intp3( ) +{ + while( 1 ) + { + NOP(); + } +} + + +__interrupt void intp21_RFTx( ) +{ + while( 1 ) + { + NOP(); + } +} + + +//__interrupt void fn_intp4(){ while(1){} } // pm.c +//__interrupt void fn_intp5(){ while(1){} } // pm.c +//__interrupt void fn_intp6(){ while(1){} } // pm.c +//__interrupt void fn_intp7(){ while(1){} } // led.c +//__interrupt void fn_intp21(){ while(1){} } // led.c + +__interrupt void fn_intcmp0( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_intcmp1( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_intdma0( ) +{ + while( 1 ) + { + NOP(); + } +} + +//__interrupt void fn_intdma1(){} // i2c_mcu.cにある + +__interrupt void fn_intst0( ) +{ + while( 1 ) + { + NOP(); + } +} + +/* __interrupt void fn_intcsi00(){} */ +__interrupt void fn_intsr0( ) +{ + while( 1 ) + { + NOP(); + } +} + +/* __interrupt void fn_intcsi01(){} */ +__interrupt void fn_intsre0( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_intst1( ) +{ + while( 1 ) + { + NOP(); + } +} + +/* __interrupt void fn_intcsi10(){} */ +//__interrupt void fn_intiic10(){ while(1){} } +__interrupt void fn_intsr1( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_intsre1( ) +{ + while( 1 ) + { + NOP(); + } +} + +//__interrupt void fn_intiica(){} // i2c.cにある +/* __interrupt void fn_inttm00(){} *//* sub.cにて定義 */ +__interrupt void fn_inttm01( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_inttm02( ) +{ + while( 1 ) + { + NOP(); + } +} +__interrupt void fn_inttm03( ) +{ + while( 1 ) + { + NOP(); + } +} + +//__interrupt void fn_intad(){ while(1){} } // adc.c +__interrupt void fn_intrtc( ) +{ + while( 1 ) + { + NOP(); + } +} + +//__interrupt void int_rtcint(){} // rtc.cにある +//__interrupt void fn_intkr(){} // main.c +__interrupt void fn_intmd( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_inttm04( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_inttm05( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_inttm06( ) +{ + while( 1 ) + { + NOP(); + } +} + +__interrupt void fn_inttm07( ) +{ + while( 1 ) + { + NOP(); + } +} diff --git a/branches/0.10(X3)/ini_VECT.prn b/branches/0.10(X3)/ini_VECT.prn new file mode 100644 index 0000000..f9dc3e2 --- /dev/null +++ b/branches/0.10(X3)/ini_VECT.prn @@ -0,0 +1,1226 @@ + + + +78K0R Assembler W1.31 Date:13 May 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\ini_VECT.asm +Para-file: +In-file: inter_asm\ini_VECT.asm +Obj-file: ini_VECT.rel +Prn-file: ini_VECT.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 May 2010 Time:20:03:34 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no ini_VECT.c + 6 6 ; In-file : ini_VECT.c + 7 7 ; Asm-file : inter_asm\ini_VECT.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0115H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, ini_VECT.c + 18 18 $DGS MOD_NAM, ini_VECT, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, @@CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS SEC_NAM, @@VECT10, U, U, 00H, 078H, 00H, 00H + 36 36 $DGS SEC_NAM, @@VECT1C, U, U, 00H, 078H, 00H, 00H + 37 37 $DGS SEC_NAM, @@VECT24, U, U, 00H, 078H, 00H, 00H + 38 38 $DGS SEC_NAM, @@VECT2A, U, U, 00H, 078H, 00H, 00H + 39 39 $DGS SEC_NAM, @@VECT34, U, U, 00H, 078H, 00H, 00H + 40 40 $DGS SEC_NAM, @@VECT4A, U, U, 00H, 078H, 00H, 00H + 41 41 $DGS SEC_NAM, @@VECT5A, U, U, 00H, 078H, 00H, 00H + 42 42 $DGS SEC_NAM, @@VECT62, U, U, 00H, 078H, 00H, 00H + 43 43 $DGS GLV_SYM, _fn_intwdti, U, U, 0E001H, 026H, 01H, 02H + 44 44 $DGS AUX_FUN, 00H, U, U, 025H, 00H, 00H + 45 45 $DGS BEG_FUN, ??bf_fn_intwdti, U, U, 00H, 065H, 01H, 00H + 46 46 $DGS AUX_BEG, 04BH, 00H, 01FH + 47 47 $DGS BEG_BLK, ??bb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H + 48 48 $DGS AUX_BEG, 03H, 00H, 00H + 49 49 $DGS END_BLK, ??eb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H + 50 50 $DGS AUX_END, 05H + 51 51 $DGS END_FUN, ??ef_fn_intwdti, U, U, 00H, 065H, 01H, 00H + 52 52 $DGS AUX_END, 06H + 53 53 $DGS GLV_SYM, _fn_intlvi, U, U, 0E001H, 026H, 01H, 02H + 54 54 $DGS AUX_FUN, 00H, U, U, 02FH, 00H, 00H + 55 55 $DGS BEG_FUN, ??bf_fn_intlvi, U, U, 00H, 065H, 01H, 00H + 56 56 $DGS AUX_BEG, 052H, 00H, 029H + 57 57 $DGS BEG_BLK, ??bb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H + 58 58 $DGS AUX_BEG, 03H, 00H, 00H + 59 59 $DGS END_BLK, ??eb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H + 60 60 $DGS AUX_END, 05H + 61 61 $DGS END_FUN, ??ef_fn_intlvi, U, U, 00H, 065H, 01H, 00H + 62 62 $DGS AUX_END, 06H + 63 63 $DGS GLV_SYM, _fn_intp0, U, U, 0E001H, 026H, 01H, 02H + 64 64 $DGS AUX_FUN, 00H, U, U, 039H, 00H, 00H + 65 65 $DGS BEG_FUN, ??bf_fn_intp0, U, U, 00H, 065H, 01H, 00H + 66 66 $DGS AUX_BEG, 059H, 00H, 033H + 67 67 $DGS BEG_BLK, ??bb00_fn_intp0, U, U, 00H, 064H, 01H, 00H + 68 68 $DGS AUX_BEG, 03H, 00H, 00H + 69 69 $DGS END_BLK, ??eb00_fn_intp0, U, U, 00H, 064H, 01H, 00H + 70 70 $DGS AUX_END, 05H + 71 71 $DGS END_FUN, ??ef_fn_intp0, U, U, 00H, 065H, 01H, 00H + 72 72 $DGS AUX_END, 06H + 73 73 $DGS GLV_SYM, _fn_intp1, U, U, 0E001H, 026H, 01H, 02H + 74 74 $DGS AUX_FUN, 00H, U, U, 043H, 00H, 00H + 75 75 $DGS BEG_FUN, ??bf_fn_intp1, U, U, 00H, 065H, 01H, 00H + 76 76 $DGS AUX_BEG, 061H, 00H, 03DH + 77 77 $DGS BEG_BLK, ??bb00_fn_intp1, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_BEG, 03H, 00H, 00H + 79 79 $DGS END_BLK, ??eb00_fn_intp1, U, U, 00H, 064H, 01H, 00H + 80 80 $DGS AUX_END, 05H + 81 81 $DGS END_FUN, ??ef_fn_intp1, U, U, 00H, 065H, 01H, 00H + 82 82 $DGS AUX_END, 06H + 83 83 $DGS GLV_SYM, _fn_intp2, U, U, 0E001H, 026H, 01H, 02H + 84 84 $DGS AUX_FUN, 00H, U, U, 04DH, 00H, 00H + 85 85 $DGS BEG_FUN, ??bf_fn_intp2, U, U, 00H, 065H, 01H, 00H + 86 86 $DGS AUX_BEG, 068H, 00H, 047H + 87 87 $DGS BEG_BLK, ??bb00_fn_intp2, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_BEG, 03H, 00H, 00H + 89 89 $DGS END_BLK, ??eb00_fn_intp2, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_END, 05H + 91 91 $DGS END_FUN, ??ef_fn_intp2, U, U, 00H, 065H, 01H, 00H + 92 92 $DGS AUX_END, 06H + 93 93 $DGS GLV_SYM, _fn_intp3, U, U, 0E001H, 026H, 01H, 02H + 94 94 $DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H + 95 95 $DGS BEG_FUN, ??bf_fn_intp3, U, U, 00H, 065H, 01H, 00H + 96 96 $DGS AUX_BEG, 06FH, 00H, 051H + 97 97 $DGS BEG_BLK, ??bb00_fn_intp3, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_BEG, 03H, 00H, 00H + 99 99 $DGS END_BLK, ??eb00_fn_intp3, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_END, 05H + 101 101 $DGS END_FUN, ??ef_fn_intp3, U, U, 00H, 065H, 01H, 00H + 102 102 $DGS AUX_END, 06H + 103 103 $DGS GLV_SYM, _intp21_RFTx, U, U, 0E001H, 026H, 01H, 02H + 104 104 $DGS AUX_FUN, 00H, U, U, 061H, 00H, 00H + 105 105 $DGS BEG_FUN, ??bf_intp21_RFTx, U, U, 00H, 065H, 01H, 00H + 106 106 $DGS AUX_BEG, 078H, 00H, 05BH + 107 107 $DGS BEG_BLK, ??bb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_BEG, 03H, 00H, 00H + 109 109 $DGS END_BLK, ??eb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_END, 05H + 111 111 $DGS END_FUN, ??ef_intp21_RFTx, U, U, 00H, 065H, 01H, 00H + 112 112 $DGS AUX_END, 06H + 113 113 $DGS GLV_SYM, _fn_intcmp0, U, U, 0E001H, 026H, 01H, 02H + 114 114 $DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H + 115 115 $DGS BEG_FUN, ??bf_fn_intcmp0, U, U, 00H, 065H, 01H, 00H + 116 116 $DGS AUX_BEG, 087H, 00H, 065H + 117 117 $DGS BEG_BLK, ??bb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H + 118 118 $DGS AUX_BEG, 03H, 00H, 00H + 119 119 $DGS END_BLK, ??eb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H + 120 120 $DGS AUX_END, 05H + 121 121 $DGS END_FUN, ??ef_fn_intcmp0, U, U, 00H, 065H, 01H, 00H + 122 122 $DGS AUX_END, 06H + 123 123 $DGS GLV_SYM, _fn_intcmp1, U, U, 0E001H, 026H, 01H, 02H + 124 124 $DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H + 125 125 $DGS BEG_FUN, ??bf_fn_intcmp1, U, U, 00H, 065H, 01H, 00H + 126 126 $DGS AUX_BEG, 08EH, 00H, 06FH + 127 127 $DGS BEG_BLK, ??bb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_BEG, 03H, 00H, 00H + 129 129 $DGS END_BLK, ??eb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_END, 05H + 131 131 $DGS END_FUN, ??ef_fn_intcmp1, U, U, 00H, 065H, 01H, 00H + 132 132 $DGS AUX_END, 06H + 133 133 $DGS GLV_SYM, _fn_intdma0, U, U, 0E001H, 026H, 01H, 02H + 134 134 $DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H + 135 135 $DGS BEG_FUN, ??bf_fn_intdma0, U, U, 00H, 065H, 01H, 00H + 136 136 $DGS AUX_BEG, 095H, 00H, 079H + 137 137 $DGS BEG_BLK, ??bb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_BEG, 03H, 00H, 00H + 139 139 $DGS END_BLK, ??eb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_END, 05H + 141 141 $DGS END_FUN, ??ef_fn_intdma0, U, U, 00H, 065H, 01H, 00H + 142 142 $DGS AUX_END, 06H + 143 143 $DGS GLV_SYM, _fn_intst0, U, U, 0E001H, 026H, 01H, 02H + 144 144 $DGS AUX_FUN, 00H, U, U, 089H, 00H, 00H + 145 145 $DGS BEG_FUN, ??bf_fn_intst0, U, U, 00H, 065H, 01H, 00H + 146 146 $DGS AUX_BEG, 09FH, 00H, 083H + 147 147 $DGS BEG_BLK, ??bb00_fn_intst0, U, U, 00H, 064H, 01H, 00H + 148 148 $DGS AUX_BEG, 03H, 00H, 00H + 149 149 $DGS END_BLK, ??eb00_fn_intst0, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_END, 05H + 151 151 $DGS END_FUN, ??ef_fn_intst0, U, U, 00H, 065H, 01H, 00H + 152 152 $DGS AUX_END, 06H + 153 153 $DGS GLV_SYM, _fn_intsr0, U, U, 0E001H, 026H, 01H, 02H + 154 154 $DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H + 155 155 $DGS BEG_FUN, ??bf_fn_intsr0, U, U, 00H, 065H, 01H, 00H + 156 156 $DGS AUX_BEG, 0A8H, 00H, 08DH + 157 157 $DGS BEG_BLK, ??bb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_BEG, 03H, 00H, 00H + 159 159 $DGS END_BLK, ??eb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_END, 05H + 161 161 $DGS END_FUN, ??ef_fn_intsr0, U, U, 00H, 065H, 01H, 00H + 162 162 $DGS AUX_END, 06H + 163 163 $DGS GLV_SYM, _fn_intsre0, U, U, 0E001H, 026H, 01H, 02H + 164 164 $DGS AUX_FUN, 00H, U, U, 09DH, 00H, 00H + 165 165 $DGS BEG_FUN, ??bf_fn_intsre0, U, U, 00H, 065H, 01H, 00H + 166 166 $DGS AUX_BEG, 0B1H, 00H, 097H + 167 167 $DGS BEG_BLK, ??bb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_BEG, 03H, 00H, 00H + 169 169 $DGS END_BLK, ??eb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_END, 05H + 171 171 $DGS END_FUN, ??ef_fn_intsre0, U, U, 00H, 065H, 01H, 00H + 172 172 $DGS AUX_END, 06H + 173 173 $DGS GLV_SYM, _fn_intst1, U, U, 0E001H, 026H, 01H, 02H + 174 174 $DGS AUX_FUN, 00H, U, U, 0A7H, 00H, 00H + 175 175 $DGS BEG_FUN, ??bf_fn_intst1, U, U, 00H, 065H, 01H, 00H + 176 176 $DGS AUX_BEG, 0B9H, 00H, 0A1H + 177 177 $DGS BEG_BLK, ??bb00_fn_intst1, U, U, 00H, 064H, 01H, 00H + 178 178 $DGS AUX_BEG, 03H, 00H, 00H + 179 179 $DGS END_BLK, ??eb00_fn_intst1, U, U, 00H, 064H, 01H, 00H + 180 180 $DGS AUX_END, 05H + 181 181 $DGS END_FUN, ??ef_fn_intst1, U, U, 00H, 065H, 01H, 00H + 182 182 $DGS AUX_END, 06H + 183 183 $DGS GLV_SYM, _fn_intsr1, U, U, 0E001H, 026H, 01H, 02H + 184 184 $DGS AUX_FUN, 00H, U, U, 0B1H, 00H, 00H + 185 185 $DGS BEG_FUN, ??bf_fn_intsr1, U, U, 00H, 065H, 01H, 00H + 186 186 $DGS AUX_BEG, 0C3H, 00H, 0ABH + 187 187 $DGS BEG_BLK, ??bb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H + 188 188 $DGS AUX_BEG, 03H, 00H, 00H + 189 189 $DGS END_BLK, ??eb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H + 190 190 $DGS AUX_END, 05H + 191 191 $DGS END_FUN, ??ef_fn_intsr1, U, U, 00H, 065H, 01H, 00H + 192 192 $DGS AUX_END, 06H + 193 193 $DGS GLV_SYM, _fn_intsre1, U, U, 0E001H, 026H, 01H, 02H + 194 194 $DGS AUX_FUN, 00H, U, U, 0BBH, 00H, 00H + 195 195 $DGS BEG_FUN, ??bf_fn_intsre1, U, U, 00H, 065H, 01H, 00H + 196 196 $DGS AUX_BEG, 0CAH, 00H, 0B5H + 197 197 $DGS BEG_BLK, ??bb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H + 198 198 $DGS AUX_BEG, 03H, 00H, 00H + 199 199 $DGS END_BLK, ??eb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H + 200 200 $DGS AUX_END, 05H + 201 201 $DGS END_FUN, ??ef_fn_intsre1, U, U, 00H, 065H, 01H, 00H + 202 202 $DGS AUX_END, 06H + 203 203 $DGS GLV_SYM, _fn_inttm01, U, U, 0E001H, 026H, 01H, 02H + 204 204 $DGS AUX_FUN, 00H, U, U, 0C5H, 00H, 00H + 205 205 $DGS BEG_FUN, ??bf_fn_inttm01, U, U, 00H, 065H, 01H, 00H + 206 206 $DGS AUX_BEG, 0D4H, 00H, 0BFH + 207 207 $DGS BEG_BLK, ??bb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_BEG, 03H, 00H, 00H + 209 209 $DGS END_BLK, ??eb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H + 210 210 $DGS AUX_END, 05H + 211 211 $DGS END_FUN, ??ef_fn_inttm01, U, U, 00H, 065H, 01H, 00H + 212 212 $DGS AUX_END, 06H + 213 213 $DGS GLV_SYM, _fn_inttm02, U, U, 0E001H, 026H, 01H, 02H + 214 214 $DGS AUX_FUN, 00H, U, U, 0CFH, 00H, 00H + 215 215 $DGS BEG_FUN, ??bf_fn_inttm02, U, U, 00H, 065H, 01H, 00H + 216 216 $DGS AUX_BEG, 0DCH, 00H, 0C9H + 217 217 $DGS BEG_BLK, ??bb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H + 218 218 $DGS AUX_BEG, 03H, 00H, 00H + 219 219 $DGS END_BLK, ??eb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H + 220 220 $DGS AUX_END, 05H + 221 221 $DGS END_FUN, ??ef_fn_inttm02, U, U, 00H, 065H, 01H, 00H + 222 222 $DGS AUX_END, 06H + 223 223 $DGS GLV_SYM, _fn_inttm03, U, U, 0E001H, 026H, 01H, 02H + 224 224 $DGS AUX_FUN, 00H, U, U, 0D9H, 00H, 00H + 225 225 $DGS BEG_FUN, ??bf_fn_inttm03, U, U, 00H, 065H, 01H, 00H + 226 226 $DGS AUX_BEG, 0E3H, 00H, 0D3H + 227 227 $DGS BEG_BLK, ??bb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H + 228 228 $DGS AUX_BEG, 03H, 00H, 00H + 229 229 $DGS END_BLK, ??eb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H + 230 230 $DGS AUX_END, 05H + 231 231 $DGS END_FUN, ??ef_fn_inttm03, U, U, 00H, 065H, 01H, 00H + 232 232 $DGS AUX_END, 06H + 233 233 $DGS GLV_SYM, _fn_intrtc, U, U, 0E001H, 026H, 01H, 02H + 234 234 $DGS AUX_FUN, 00H, U, U, 0E3H, 00H, 00H + 235 235 $DGS BEG_FUN, ??bf_fn_intrtc, U, U, 00H, 065H, 01H, 00H + 236 236 $DGS AUX_BEG, 0ECH, 00H, 0DDH + 237 237 $DGS BEG_BLK, ??bb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H + 238 238 $DGS AUX_BEG, 03H, 00H, 00H + 239 239 $DGS END_BLK, ??eb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H + 240 240 $DGS AUX_END, 05H + 241 241 $DGS END_FUN, ??ef_fn_intrtc, U, U, 00H, 065H, 01H, 00H + 242 242 $DGS AUX_END, 06H + 243 243 $DGS GLV_SYM, _fn_intmd, U, U, 0E001H, 026H, 01H, 02H + 244 244 $DGS AUX_FUN, 00H, U, U, 0EDH, 00H, 00H + 245 245 $DGS BEG_FUN, ??bf_fn_intmd, U, U, 00H, 065H, 01H, 00H + 246 246 $DGS AUX_BEG, 0F6H, 00H, 0E7H + 247 247 $DGS BEG_BLK, ??bb00_fn_intmd, U, U, 00H, 064H, 01H, 00H + 248 248 $DGS AUX_BEG, 03H, 00H, 00H + 249 249 $DGS END_BLK, ??eb00_fn_intmd, U, U, 00H, 064H, 01H, 00H + 250 250 $DGS AUX_END, 05H + 251 251 $DGS END_FUN, ??ef_fn_intmd, U, U, 00H, 065H, 01H, 00H + 252 252 $DGS AUX_END, 06H + 253 253 $DGS GLV_SYM, _fn_inttm04, U, U, 0E001H, 026H, 01H, 02H + 254 254 $DGS AUX_FUN, 00H, U, U, 0F7H, 00H, 00H + 255 255 $DGS BEG_FUN, ??bf_fn_inttm04, U, U, 00H, 065H, 01H, 00H + 256 256 $DGS AUX_BEG, 0FEH, 00H, 0F1H + 257 257 $DGS BEG_BLK, ??bb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H + 258 258 $DGS AUX_BEG, 03H, 00H, 00H + 259 259 $DGS END_BLK, ??eb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H + 260 260 $DGS AUX_END, 05H + 261 261 $DGS END_FUN, ??ef_fn_inttm04, U, U, 00H, 065H, 01H, 00H + 262 262 $DGS AUX_END, 06H + 263 263 $DGS GLV_SYM, _fn_inttm05, U, U, 0E001H, 026H, 01H, 02H + 264 264 $DGS AUX_FUN, 00H, U, U, 0101H, 00H, 00H + 265 265 $DGS BEG_FUN, ??bf_fn_inttm05, U, U, 00H, 065H, 01H, 00H + 266 266 $DGS AUX_BEG, 0106H, 00H, 0FBH + 267 267 $DGS BEG_BLK, ??bb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H + 268 268 $DGS AUX_BEG, 03H, 00H, 00H + 269 269 $DGS END_BLK, ??eb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H + 270 270 $DGS AUX_END, 05H + 271 271 $DGS END_FUN, ??ef_fn_inttm05, U, U, 00H, 065H, 01H, 00H + 272 272 $DGS AUX_END, 06H + 273 273 $DGS GLV_SYM, _fn_inttm06, U, U, 0E001H, 026H, 01H, 02H + 274 274 $DGS AUX_FUN, 00H, U, U, 010BH, 00H, 00H + 275 275 $DGS BEG_FUN, ??bf_fn_inttm06, U, U, 00H, 065H, 01H, 00H + 276 276 $DGS AUX_BEG, 010EH, 00H, 0105H + 277 277 $DGS BEG_BLK, ??bb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H + 278 278 $DGS AUX_BEG, 03H, 00H, 00H + 279 279 $DGS END_BLK, ??eb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H + 280 280 $DGS AUX_END, 05H + 281 281 $DGS END_FUN, ??ef_fn_inttm06, U, U, 00H, 065H, 01H, 00H + 282 282 $DGS AUX_END, 06H + 283 283 $DGS GLV_SYM, _fn_inttm07, U, U, 0E001H, 026H, 01H, 02H + 284 284 $DGS AUX_FUN, 00H, U, U, 0115H, 00H, 00H + 285 285 $DGS BEG_FUN, ??bf_fn_inttm07, U, U, 00H, 065H, 01H, 00H + 286 286 $DGS AUX_BEG, 0116H, 00H, 010FH + 287 287 $DGS BEG_BLK, ??bb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H + 288 288 $DGS AUX_BEG, 03H, 00H, 00H + 289 289 $DGS END_BLK, ??eb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H + 290 290 $DGS AUX_END, 05H + 291 291 $DGS END_FUN, ??ef_fn_inttm07, U, U, 00H, 065H, 01H, 00H + 292 292 $DGS AUX_END, 06H + 293 293 $DGS GLV_SYM, _@vect10, U, U, 00H, 026H, 00H, 00H + 294 294 $DGS GLV_SYM, _@vect12, U, U, 00H, 026H, 00H, 00H + 295 295 $DGS GLV_SYM, _@vect1c, U, U, 00H, 026H, 00H, 00H + 296 296 $DGS GLV_SYM, _@vect24, U, U, 00H, 026H, 00H, 00H + 297 297 $DGS GLV_SYM, _@vect2a, U, U, 00H, 026H, 00H, 00H + 298 298 $DGS GLV_SYM, _@vect34, U, U, 00H, 026H, 00H, 00H + 299 299 $DGS GLV_SYM, _@vect36, U, U, 00H, 026H, 00H, 00H + 300 300 $DGS GLV_SYM, _@vect38, U, U, 00H, 026H, 00H, 00H + 301 301 $DGS GLV_SYM, _@vect3a, U, U, 00H, 026H, 00H, 00H + 302 302 $DGS GLV_SYM, _@vect4a, U, U, 00H, 026H, 00H, 00H + 303 303 $DGS GLV_SYM, _@vect5a, U, U, 00H, 026H, 00H, 00H + 304 304 $DGS GLV_SYM, _@vect62, U, U, 00H, 026H, 00H, 00H + 305 305 + 306 306 EXTRN _intp4_extdc + 307 307 EXTRN _intp5_shell + 308 308 EXTRN _int_dma1 + 309 309 EXTRN _int_iic10 + 310 310 EXTRN _int_iic_twl + 311 311 EXTRN _int_adc + 312 312 EXTRN _int_rtc + 313 313 EXTRN _int_rtc_int + 314 314 EXTRN _int_kr + 315 315 EXTRN _intp6_PM_irq + 316 316 EXTRN _int_iic_ctr + 317 317 EXTRN _intp23_ACC_ready + 318 318 PUBLIC _fn_intwdti + 319 319 PUBLIC _fn_intlvi + 320 320 PUBLIC _fn_intp0 + 321 321 PUBLIC _fn_intp1 + 322 322 PUBLIC _fn_intp2 + 323 323 PUBLIC _fn_intp3 + 324 324 PUBLIC _intp21_RFTx + 325 325 PUBLIC _fn_intcmp0 + 326 326 PUBLIC _fn_intcmp1 + 327 327 PUBLIC _fn_intdma0 + 328 328 PUBLIC _fn_intst0 + 329 329 PUBLIC _fn_intsr0 + 330 330 PUBLIC _fn_intsre0 + 331 331 PUBLIC _fn_intst1 + 332 332 PUBLIC _fn_intsr1 + 333 333 PUBLIC _fn_intsre1 + 334 334 PUBLIC _fn_inttm01 + 335 335 PUBLIC _fn_inttm02 + 336 336 PUBLIC _fn_inttm03 + 337 337 PUBLIC _fn_intrtc + 338 338 PUBLIC _fn_intmd + 339 339 PUBLIC _fn_inttm04 + 340 340 PUBLIC _fn_inttm05 + 341 341 PUBLIC _fn_inttm06 + 342 342 PUBLIC _fn_inttm07 + 343 343 PUBLIC _@vect10 + 344 344 PUBLIC _@vect12 + 345 345 PUBLIC _@vect1c + 346 346 PUBLIC _@vect24 + 347 347 PUBLIC _@vect2a + 348 348 PUBLIC _@vect34 + 349 349 PUBLIC _@vect36 + 350 350 PUBLIC _@vect38 + 351 351 PUBLIC _@vect3a + 352 352 PUBLIC _@vect4a + 353 353 PUBLIC _@vect5a + 354 354 PUBLIC _@vect62 + 355 355 + 356 356 ----- @@BITS BSEG + 357 357 + 358 358 ----- @@CNST CSEG MIRRORP + 359 359 + 360 360 ----- @@R_INIT CSEG UNIT64KP + 361 361 + 362 362 ----- @@INIT DSEG BASEP + 363 363 + 364 364 ----- @@DATA DSEG BASEP + 365 365 + 366 366 ----- @@R_INIS CSEG UNIT64KP + 367 367 + 368 368 ----- @@INIS DSEG SADDRP + 369 369 + 370 370 ----- @@DATS DSEG SADDRP + 371 371 + 372 372 ----- @@CNSTL CSEG PAGE64KP + 373 373 + 374 374 ----- @@RLINIT CSEG UNIT64KP + 375 375 + 376 376 ----- @@INITL DSEG UNIT64KP + 377 377 + 378 378 ----- @@DATAL DSEG UNIT64KP + 379 379 + 380 380 ----- @@CALT CSEG CALLT0 + 381 381 + 382 382 ; line 1 : #pragma nop + 383 383 ; line 2 : + 384 384 ; line 3 : + 385 385 ; line 4 : #include "config.h" + 386 386 ; line 5 : + 387 387 ; line 6 : //#pragma interrupt INTWDTI fn_intwdti // 未使用 + 388 388 ; line 7 : //#pragma interrupt INTLVI fn_intlvi // 未使用 + 389 389 ; line 8 : + 390 390 ; line 9 : //#pragma interrupt INTP0 intp0_slp // SLP (CPUより、要求 + 391 391 ; ) ポーリング + 392 392 ; line 10 : //#pragma interrupt INTP1 fn_intp1 // (I2C) + 393 393 ; line 11 : //#pragma interrupt INTP2 fn_intp2 // (I2C) + 394 394 ; line 12 : //#pragma interrupt INTP3 fn_intp3 // 未搭載 + 395 395 ; line 13 : #pragma interrupt INTP4 intp4_extdc // EXTDC, ただし電源off + 396 396 ; から起こすのみ。通常はポーリング + 397 397 ; line 14 : #pragma interrupt INTP5 intp5_shell // SHELL_CLOSE, ただし電 + 398 398 ; 源offから起こすのみ。通常はポーリング + 399 399 ; line 15 : #pragma interrupt INTP6 intp6_PM_irq // CODEC経由で旧PMICへの + 400 400 ; コマンド書き込み + 401 401 ; line 16 : + 402 402 ; line 17 : //#ifdef _MCU_BSR_ // 割り込みそのものは + 403 403 ; 使いません + 404 404 ; line 18 : //#pragma interrupt INTP21 intp21_RFTx // 電波送信パルス + 405 405 ; line 19 : //#else + 406 406 ; line 20 : //#pragma interrupt INTP7 intp21_RFTx + 407 407 ; line 21 : //#endif + 408 408 ; line 22 : + 409 409 ; line 23 : #ifdef _MCU_BSR_ + 410 410 ; line 24 : #pragma interrupt INTP23 intp23_ACC_ready // 加速度センサ + 411 411 ; 、データ準備完了 + 412 412 ; line 25 : #endif + 413 413 ; line 26 : + 414 414 ; line 27 : //#pragma interrupt INTCMP0 fn_intcmp0 + 415 415 ; line 28 : //#pragma interrupt INTCMP1 fn_intcmp1 + 416 416 ; line 29 : //#pragma interrupt INTDMA0 fn_intdma0 + 417 417 ; line 30 : #pragma interrupt INTDMA1 int_dma1 + 418 418 ; line 31 : + 419 419 ; line 32 : //#pragma interrupt INTST0 fn_intst0 + 420 420 ; line 33 : /* #pragma interrupt INTCSI00 fn_intcsi00 */ + 421 421 ; line 34 : //#pragma interrupt INTSR0 fn_intsr0 + 422 422 ; line 35 : /* #pragma interrupt INTCSI01 fn_intcsi01 */ + 423 423 ; line 36 : //#pragma interrupt INTSRE0 fn_intsre0 + 424 424 ; line 37 : + 425 425 ; line 38 : //#pragma interrupt INTST1 fn_intst1 + 426 426 ; line 39 : /* #pragma interrupt INTCSI10 fn_intcsi10 */ + 427 427 ; line 40 : #pragma interrupt INTIIC10 int_iic10 + 428 428 ; line 41 : //#pragma interrupt INTSR1 fn_intsr1 + 429 429 ; line 42 : //#pragma interrupt INTSRE1 fn_intsre1 + 430 430 ; line 43 : + 431 431 ; line 44 : + 432 432 ; line 45 : #ifdef _MCU_KE3_ + 433 433 ; line 46 : #pragma interrupt INTIICA int_iic_ctr // CTR側 + 434 434 ; line 47 : #else + 435 435 ; line 48 : + 436 436 ; line 49 : // TSはマザボでテレコ、WMは回路図がテレコで結局一致… + 437 437 ; line 50 : #pragma interrupt INTIICA0 int_iic_twl + 438 438 ; line 51 : #pragma interrupt INTIICA1 int_iic_ctr + 439 439 ; line 52 : #endif + 440 440 ; line 53 : + 441 441 ; line 54 : //#pragma interrupt INTTM00 fn_inttm00 + 442 442 ; line 55 : //#pragma interrupt INTTM01 fn_inttm01 + 443 443 ; line 56 : //#pragma interrupt INTTM02 fn_inttm02 + 444 444 ; line 57 : //#pragma interrupt INTTM03 fn_inttm03 + 445 445 ; line 58 : + 446 446 ; line 59 : #pragma interrupt INTAD int_adc + 447 447 ; line 60 : #pragma interrupt INTRTC int_rtc + 448 448 ; line 61 : #pragma interrupt INTRTCI int_rtc_int + 449 449 ; line 62 : #pragma interrupt INTKR int_kr + 450 450 ; line 63 : //#pragma interrupt INTMD fn_intmd + 451 451 ; line 64 : + 452 452 ; line 65 : //#pragma interrupt INTTM04 fn_inttm04 + 453 453 ; line 66 : //#pragma interrupt INTTM05 fn_inttm05 + 454 454 ; line 67 : //#pragma interrupt INTTM06 fn_inttm06 + 455 455 ; line 68 : //#pragma interrupt INTTM07 fn_inttm07 + 456 456 ; line 69 : + 457 457 ; line 70 : + 458 458 ; line 71 : /****************************************************/ + 459 459 ; line 72 : /* 未使用時のダミー関数定義 */ + 460 460 ; line 73 : /****************************************************/ + 461 461 ; line 74 : __interrupt void fn_intwdti( ) + 462 462 ; line 75 : { + 463 463 + 464 464 ----- @@BASE CSEG BASE + 465 465 00000 _fn_intwdti: + 466 466 $DGL 1,27 + 467 467 00000 ??bf_fn_intwdti: + 468 468 ; line 76 : while( 1 ) + 469 469 00000 ?L0003: + 470 470 ; line 77 : { + 471 471 00000 ??bb00_fn_intwdti: + 472 472 ; line 78 : NOP(); + 473 473 $DGL 0,4 + 474 474 00000 00 nop ;[INF] 1, 1 + 475 475 00001 ??eb00_fn_intwdti: + 476 476 ; line 79 : } + 477 477 $DGL 0,5 + 478 478 00001 EFFD br $?L0003 ;[INF] 2, 3 + 479 479 ; line 80 : } + 480 480 $DGL 0,6 + 481 481 00003 ??ef_fn_intwdti: + 482 482 00003 61FC reti ;[INF] 2, 6 + 483 483 00005 ??ee_fn_intwdti: + 484 484 ; line 81 : __interrupt void fn_intlvi( ) + 485 485 ; line 82 : { + 486 486 00005 _fn_intlvi: + 487 487 $DGL 1,37 + 488 488 00005 ??bf_fn_intlvi: + 489 489 ; line 83 : while( 1 ) + 490 490 00005 ?L0007: + 491 491 ; line 84 : { + 492 492 00005 ??bb00_fn_intlvi: + 493 493 ; line 85 : NOP(); + 494 494 $DGL 0,4 + 495 495 00005 00 nop ;[INF] 1, 1 + 496 496 00006 ??eb00_fn_intlvi: + 497 497 ; line 86 : } + 498 498 $DGL 0,5 + 499 499 00006 EFFD br $?L0007 ;[INF] 2, 3 + 500 500 ; line 87 : } + 501 501 $DGL 0,6 + 502 502 00008 ??ef_fn_intlvi: + 503 503 00008 61FC reti ;[INF] 2, 6 + 504 504 0000A ??ee_fn_intlvi: + 505 505 ; line 88 : + 506 506 ; line 89 : __interrupt void fn_intp0(){ + 507 507 0000A _fn_intp0: + 508 508 $DGL 1,47 + 509 509 0000A ??bf_fn_intp0: + 510 510 ; line 90 : while( 1 ) + 511 511 0000A ?L0011: + 512 512 ; line 91 : { + 513 513 0000A ??bb00_fn_intp0: + 514 514 ; line 92 : NOP(); + 515 515 $DGL 0,4 + 516 516 0000A 00 nop ;[INF] 1, 1 + 517 517 0000B ??eb00_fn_intp0: + 518 518 ; line 93 : } + 519 519 $DGL 0,5 + 520 520 0000B EFFD br $?L0011 ;[INF] 2, 3 + 521 521 ; line 94 : } + 522 522 $DGL 0,6 + 523 523 0000D ??ef_fn_intp0: + 524 524 0000D 61FC reti ;[INF] 2, 6 + 525 525 0000F ??ee_fn_intp0: + 526 526 ; line 95 : + 527 527 ; line 96 : __interrupt void fn_intp1( ) + 528 528 ; line 97 : { + 529 529 0000F _fn_intp1: + 530 530 $DGL 1,57 + 531 531 0000F ??bf_fn_intp1: + 532 532 ; line 98 : while( 1 ) + 533 533 0000F ?L0015: + 534 534 ; line 99 : { + 535 535 0000F ??bb00_fn_intp1: + 536 536 ; line 100 : NOP(); + 537 537 $DGL 0,4 + 538 538 0000F 00 nop ;[INF] 1, 1 + 539 539 00010 ??eb00_fn_intp1: + 540 540 ; line 101 : } + 541 541 $DGL 0,5 + 542 542 00010 EFFD br $?L0015 ;[INF] 2, 3 + 543 543 ; line 102 : } // + 544 544 $DGL 0,6 + 545 545 00012 ??ef_fn_intp1: + 546 546 00012 61FC reti ;[INF] 2, 6 + 547 547 00014 ??ee_fn_intp1: + 548 548 ; line 103 : __interrupt void fn_intp2( ) + 549 549 ; line 104 : { + 550 550 00014 _fn_intp2: + 551 551 $DGL 1,67 + 552 552 00014 ??bf_fn_intp2: + 553 553 ; line 105 : while( 1 ) + 554 554 00014 ?L0019: + 555 555 ; line 106 : { + 556 556 00014 ??bb00_fn_intp2: + 557 557 ; line 107 : NOP(); + 558 558 $DGL 0,4 + 559 559 00014 00 nop ;[INF] 1, 1 + 560 560 00015 ??eb00_fn_intp2: + 561 561 ; line 108 : } + 562 562 $DGL 0,5 + 563 563 00015 EFFD br $?L0019 ;[INF] 2, 3 + 564 564 ; line 109 : } + 565 565 $DGL 0,6 + 566 566 00017 ??ef_fn_intp2: + 567 567 00017 61FC reti ;[INF] 2, 6 + 568 568 00019 ??ee_fn_intp2: + 569 569 ; line 110 : __interrupt void fn_intp3( ) + 570 570 ; line 111 : { + 571 571 00019 _fn_intp3: + 572 572 $DGL 1,77 + 573 573 00019 ??bf_fn_intp3: + 574 574 ; line 112 : while( 1 ) + 575 575 00019 ?L0023: + 576 576 ; line 113 : { + 577 577 00019 ??bb00_fn_intp3: + 578 578 ; line 114 : NOP(); + 579 579 $DGL 0,4 + 580 580 00019 00 nop ;[INF] 1, 1 + 581 581 0001A ??eb00_fn_intp3: + 582 582 ; line 115 : } + 583 583 $DGL 0,5 + 584 584 0001A EFFD br $?L0023 ;[INF] 2, 3 + 585 585 ; line 116 : } + 586 586 $DGL 0,6 + 587 587 0001C ??ef_fn_intp3: + 588 588 0001C 61FC reti ;[INF] 2, 6 + 589 589 0001E ??ee_fn_intp3: + 590 590 ; line 117 : + 591 591 ; line 118 : + 592 592 ; line 119 : __interrupt void intp21_RFTx( ) + 593 593 ; line 120 : { + 594 594 0001E _intp21_RFTx: + 595 595 $DGL 1,87 + 596 596 0001E ??bf_intp21_RFTx: + 597 597 ; line 121 : while( 1 ) + 598 598 0001E ?L0027: + 599 599 ; line 122 : { + 600 600 0001E ??bb00_intp21_RFTx: + 601 601 ; line 123 : NOP(); + 602 602 $DGL 0,4 + 603 603 0001E 00 nop ;[INF] 1, 1 + 604 604 0001F ??eb00_intp21_RFTx: + 605 605 ; line 124 : } + 606 606 $DGL 0,5 + 607 607 0001F EFFD br $?L0027 ;[INF] 2, 3 + 608 608 ; line 125 : } + 609 609 $DGL 0,6 + 610 610 00021 ??ef_intp21_RFTx: + 611 611 00021 61FC reti ;[INF] 2, 6 + 612 612 00023 ??ee_intp21_RFTx: + 613 613 ; line 126 : + 614 614 ; line 127 : + 615 615 ; line 128 : //__interrupt void fn_intp4(){ while(1){} } // pm.c + 616 616 ; line 129 : //__interrupt void fn_intp5(){ while(1){} } // pm.c + 617 617 ; line 130 : //__interrupt void fn_intp6(){ while(1){} } // pm.c + 618 618 ; line 131 : //__interrupt void fn_intp7(){ while(1){} } // led.c + 619 619 ; line 132 : //__interrupt void fn_intp21(){ while(1){} } // led.c + 620 620 ; line 133 : + 621 621 ; line 134 : __interrupt void fn_intcmp0( ) + 622 622 ; line 135 : { + 623 623 00023 _fn_intcmp0: + 624 624 $DGL 1,97 + 625 625 00023 ??bf_fn_intcmp0: + 626 626 ; line 136 : while( 1 ) + 627 627 00023 ?L0031: + 628 628 ; line 137 : { + 629 629 00023 ??bb00_fn_intcmp0: + 630 630 ; line 138 : NOP(); + 631 631 $DGL 0,4 + 632 632 00023 00 nop ;[INF] 1, 1 + 633 633 00024 ??eb00_fn_intcmp0: + 634 634 ; line 139 : } + 635 635 $DGL 0,5 + 636 636 00024 EFFD br $?L0031 ;[INF] 2, 3 + 637 637 ; line 140 : } + 638 638 $DGL 0,6 + 639 639 00026 ??ef_fn_intcmp0: + 640 640 00026 61FC reti ;[INF] 2, 6 + 641 641 00028 ??ee_fn_intcmp0: + 642 642 ; line 141 : __interrupt void fn_intcmp1( ) + 643 643 ; line 142 : { + 644 644 00028 _fn_intcmp1: + 645 645 $DGL 1,107 + 646 646 00028 ??bf_fn_intcmp1: + 647 647 ; line 143 : while( 1 ) + 648 648 00028 ?L0035: + 649 649 ; line 144 : { + 650 650 00028 ??bb00_fn_intcmp1: + 651 651 ; line 145 : NOP(); + 652 652 $DGL 0,4 + 653 653 00028 00 nop ;[INF] 1, 1 + 654 654 00029 ??eb00_fn_intcmp1: + 655 655 ; line 146 : } + 656 656 $DGL 0,5 + 657 657 00029 EFFD br $?L0035 ;[INF] 2, 3 + 658 658 ; line 147 : } + 659 659 $DGL 0,6 + 660 660 0002B ??ef_fn_intcmp1: + 661 661 0002B 61FC reti ;[INF] 2, 6 + 662 662 0002D ??ee_fn_intcmp1: + 663 663 ; line 148 : __interrupt void fn_intdma0( ) + 664 664 ; line 149 : { + 665 665 0002D _fn_intdma0: + 666 666 $DGL 1,117 + 667 667 0002D ??bf_fn_intdma0: + 668 668 ; line 150 : while( 1 ) + 669 669 0002D ?L0039: + 670 670 ; line 151 : { + 671 671 0002D ??bb00_fn_intdma0: + 672 672 ; line 152 : NOP(); + 673 673 $DGL 0,4 + 674 674 0002D 00 nop ;[INF] 1, 1 + 675 675 0002E ??eb00_fn_intdma0: + 676 676 ; line 153 : } + 677 677 $DGL 0,5 + 678 678 0002E EFFD br $?L0039 ;[INF] 2, 3 + 679 679 ; line 154 : } + 680 680 $DGL 0,6 + 681 681 00030 ??ef_fn_intdma0: + 682 682 00030 61FC reti ;[INF] 2, 6 + 683 683 00032 ??ee_fn_intdma0: + 684 684 ; line 155 : + 685 685 ; line 156 : //__interrupt void fn_intdma1(){} // i2c_mcu.cにある + 686 686 ; line 157 : + 687 687 ; line 158 : __interrupt void fn_intst0( ) + 688 688 ; line 159 : { + 689 689 00032 _fn_intst0: + 690 690 $DGL 1,127 + 691 691 00032 ??bf_fn_intst0: + 692 692 ; line 160 : while( 1 ) + 693 693 00032 ?L0043: + 694 694 ; line 161 : { + 695 695 00032 ??bb00_fn_intst0: + 696 696 ; line 162 : NOP(); + 697 697 $DGL 0,4 + 698 698 00032 00 nop ;[INF] 1, 1 + 699 699 00033 ??eb00_fn_intst0: + 700 700 ; line 163 : } + 701 701 $DGL 0,5 + 702 702 00033 EFFD br $?L0043 ;[INF] 2, 3 + 703 703 ; line 164 : } + 704 704 $DGL 0,6 + 705 705 00035 ??ef_fn_intst0: + 706 706 00035 61FC reti ;[INF] 2, 6 + 707 707 00037 ??ee_fn_intst0: + 708 708 ; line 165 : + 709 709 ; line 166 : /* __interrupt void fn_intcsi00(){} */ + 710 710 ; line 167 : __interrupt void fn_intsr0( ) + 711 711 ; line 168 : { + 712 712 00037 _fn_intsr0: + 713 713 $DGL 1,137 + 714 714 00037 ??bf_fn_intsr0: + 715 715 ; line 169 : while( 1 ) + 716 716 00037 ?L0047: + 717 717 ; line 170 : { + 718 718 00037 ??bb00_fn_intsr0: + 719 719 ; line 171 : NOP(); + 720 720 $DGL 0,4 + 721 721 00037 00 nop ;[INF] 1, 1 + 722 722 00038 ??eb00_fn_intsr0: + 723 723 ; line 172 : } + 724 724 $DGL 0,5 + 725 725 00038 EFFD br $?L0047 ;[INF] 2, 3 + 726 726 ; line 173 : } + 727 727 $DGL 0,6 + 728 728 0003A ??ef_fn_intsr0: + 729 729 0003A 61FC reti ;[INF] 2, 6 + 730 730 0003C ??ee_fn_intsr0: + 731 731 ; line 174 : + 732 732 ; line 175 : /* __interrupt void fn_intcsi01(){} */ + 733 733 ; line 176 : __interrupt void fn_intsre0( ) + 734 734 ; line 177 : { + 735 735 0003C _fn_intsre0: + 736 736 $DGL 1,147 + 737 737 0003C ??bf_fn_intsre0: + 738 738 ; line 178 : while( 1 ) + 739 739 0003C ?L0051: + 740 740 ; line 179 : { + 741 741 0003C ??bb00_fn_intsre0: + 742 742 ; line 180 : NOP(); + 743 743 $DGL 0,4 + 744 744 0003C 00 nop ;[INF] 1, 1 + 745 745 0003D ??eb00_fn_intsre0: + 746 746 ; line 181 : } + 747 747 $DGL 0,5 + 748 748 0003D EFFD br $?L0051 ;[INF] 2, 3 + 749 749 ; line 182 : } + 750 750 $DGL 0,6 + 751 751 0003F ??ef_fn_intsre0: + 752 752 0003F 61FC reti ;[INF] 2, 6 + 753 753 00041 ??ee_fn_intsre0: + 754 754 ; line 183 : + 755 755 ; line 184 : __interrupt void fn_intst1( ) + 756 756 ; line 185 : { + 757 757 00041 _fn_intst1: + 758 758 $DGL 1,157 + 759 759 00041 ??bf_fn_intst1: + 760 760 ; line 186 : while( 1 ) + 761 761 00041 ?L0055: + 762 762 ; line 187 : { + 763 763 00041 ??bb00_fn_intst1: + 764 764 ; line 188 : NOP(); + 765 765 $DGL 0,4 + 766 766 00041 00 nop ;[INF] 1, 1 + 767 767 00042 ??eb00_fn_intst1: + 768 768 ; line 189 : } + 769 769 $DGL 0,5 + 770 770 00042 EFFD br $?L0055 ;[INF] 2, 3 + 771 771 ; line 190 : } + 772 772 $DGL 0,6 + 773 773 00044 ??ef_fn_intst1: + 774 774 00044 61FC reti ;[INF] 2, 6 + 775 775 00046 ??ee_fn_intst1: + 776 776 ; line 191 : + 777 777 ; line 192 : /* __interrupt void fn_intcsi10(){} */ + 778 778 ; line 193 : //__interrupt void fn_intiic10(){ while(1){} } + 779 779 ; line 194 : __interrupt void fn_intsr1( ) + 780 780 ; line 195 : { + 781 781 00046 _fn_intsr1: + 782 782 $DGL 1,167 + 783 783 00046 ??bf_fn_intsr1: + 784 784 ; line 196 : while( 1 ) + 785 785 00046 ?L0059: + 786 786 ; line 197 : { + 787 787 00046 ??bb00_fn_intsr1: + 788 788 ; line 198 : NOP(); + 789 789 $DGL 0,4 + 790 790 00046 00 nop ;[INF] 1, 1 + 791 791 00047 ??eb00_fn_intsr1: + 792 792 ; line 199 : } + 793 793 $DGL 0,5 + 794 794 00047 EFFD br $?L0059 ;[INF] 2, 3 + 795 795 ; line 200 : } + 796 796 $DGL 0,6 + 797 797 00049 ??ef_fn_intsr1: + 798 798 00049 61FC reti ;[INF] 2, 6 + 799 799 0004B ??ee_fn_intsr1: + 800 800 ; line 201 : __interrupt void fn_intsre1( ) + 801 801 ; line 202 : { + 802 802 0004B _fn_intsre1: + 803 803 $DGL 1,177 + 804 804 0004B ??bf_fn_intsre1: + 805 805 ; line 203 : while( 1 ) + 806 806 0004B ?L0063: + 807 807 ; line 204 : { + 808 808 0004B ??bb00_fn_intsre1: + 809 809 ; line 205 : NOP(); + 810 810 $DGL 0,4 + 811 811 0004B 00 nop ;[INF] 1, 1 + 812 812 0004C ??eb00_fn_intsre1: + 813 813 ; line 206 : } + 814 814 $DGL 0,5 + 815 815 0004C EFFD br $?L0063 ;[INF] 2, 3 + 816 816 ; line 207 : } + 817 817 $DGL 0,6 + 818 818 0004E ??ef_fn_intsre1: + 819 819 0004E 61FC reti ;[INF] 2, 6 + 820 820 00050 ??ee_fn_intsre1: + 821 821 ; line 208 : + 822 822 ; line 209 : //__interrupt void fn_intiica(){} // i2c.cにある + 823 823 ; line 210 : /* __interrupt void fn_inttm00(){} *//* sub.cにて定義 */ + 824 824 ; line 211 : __interrupt void fn_inttm01( ) + 825 825 ; line 212 : { + 826 826 00050 _fn_inttm01: + 827 827 $DGL 1,187 + 828 828 00050 ??bf_fn_inttm01: + 829 829 ; line 213 : while( 1 ) + 830 830 00050 ?L0067: + 831 831 ; line 214 : { + 832 832 00050 ??bb00_fn_inttm01: + 833 833 ; line 215 : NOP(); + 834 834 $DGL 0,4 + 835 835 00050 00 nop ;[INF] 1, 1 + 836 836 00051 ??eb00_fn_inttm01: + 837 837 ; line 216 : } + 838 838 $DGL 0,5 + 839 839 00051 EFFD br $?L0067 ;[INF] 2, 3 + 840 840 ; line 217 : } + 841 841 $DGL 0,6 + 842 842 00053 ??ef_fn_inttm01: + 843 843 00053 61FC reti ;[INF] 2, 6 + 844 844 00055 ??ee_fn_inttm01: + 845 845 ; line 218 : + 846 846 ; line 219 : __interrupt void fn_inttm02( ) + 847 847 ; line 220 : { + 848 848 00055 _fn_inttm02: + 849 849 $DGL 1,197 + 850 850 00055 ??bf_fn_inttm02: + 851 851 ; line 221 : while( 1 ) + 852 852 00055 ?L0071: + 853 853 ; line 222 : { + 854 854 00055 ??bb00_fn_inttm02: + 855 855 ; line 223 : NOP(); + 856 856 $DGL 0,4 + 857 857 00055 00 nop ;[INF] 1, 1 + 858 858 00056 ??eb00_fn_inttm02: + 859 859 ; line 224 : } + 860 860 $DGL 0,5 + 861 861 00056 EFFD br $?L0071 ;[INF] 2, 3 + 862 862 ; line 225 : } + 863 863 $DGL 0,6 + 864 864 00058 ??ef_fn_inttm02: + 865 865 00058 61FC reti ;[INF] 2, 6 + 866 866 0005A ??ee_fn_inttm02: + 867 867 ; line 226 : __interrupt void fn_inttm03( ) + 868 868 ; line 227 : { + 869 869 0005A _fn_inttm03: + 870 870 $DGL 1,207 + 871 871 0005A ??bf_fn_inttm03: + 872 872 ; line 228 : while( 1 ) + 873 873 0005A ?L0075: + 874 874 ; line 229 : { + 875 875 0005A ??bb00_fn_inttm03: + 876 876 ; line 230 : NOP(); + 877 877 $DGL 0,4 + 878 878 0005A 00 nop ;[INF] 1, 1 + 879 879 0005B ??eb00_fn_inttm03: + 880 880 ; line 231 : } + 881 881 $DGL 0,5 + 882 882 0005B EFFD br $?L0075 ;[INF] 2, 3 + 883 883 ; line 232 : } + 884 884 $DGL 0,6 + 885 885 0005D ??ef_fn_inttm03: + 886 886 0005D 61FC reti ;[INF] 2, 6 + 887 887 0005F ??ee_fn_inttm03: + 888 888 ; line 233 : + 889 889 ; line 234 : //__interrupt void fn_intad(){ while(1){} } // adc.c + 890 890 ; line 235 : __interrupt void fn_intrtc( ) + 891 891 ; line 236 : { + 892 892 0005F _fn_intrtc: + 893 893 $DGL 1,217 + 894 894 0005F ??bf_fn_intrtc: + 895 895 ; line 237 : while( 1 ) + 896 896 0005F ?L0079: + 897 897 ; line 238 : { + 898 898 0005F ??bb00_fn_intrtc: + 899 899 ; line 239 : NOP(); + 900 900 $DGL 0,4 + 901 901 0005F 00 nop ;[INF] 1, 1 + 902 902 00060 ??eb00_fn_intrtc: + 903 903 ; line 240 : } + 904 904 $DGL 0,5 + 905 905 00060 EFFD br $?L0079 ;[INF] 2, 3 + 906 906 ; line 241 : } + 907 907 $DGL 0,6 + 908 908 00062 ??ef_fn_intrtc: + 909 909 00062 61FC reti ;[INF] 2, 6 + 910 910 00064 ??ee_fn_intrtc: + 911 911 ; line 242 : + 912 912 ; line 243 : //__interrupt void int_rtcint(){} // rtc.cにある + 913 913 ; line 244 : //__interrupt void fn_intkr(){} // main.c + 914 914 ; line 245 : __interrupt void fn_intmd( ) + 915 915 ; line 246 : { + 916 916 00064 _fn_intmd: + 917 917 $DGL 1,227 + 918 918 00064 ??bf_fn_intmd: + 919 919 ; line 247 : while( 1 ) + 920 920 00064 ?L0083: + 921 921 ; line 248 : { + 922 922 00064 ??bb00_fn_intmd: + 923 923 ; line 249 : NOP(); + 924 924 $DGL 0,4 + 925 925 00064 00 nop ;[INF] 1, 1 + 926 926 00065 ??eb00_fn_intmd: + 927 927 ; line 250 : } + 928 928 $DGL 0,5 + 929 929 00065 EFFD br $?L0083 ;[INF] 2, 3 + 930 930 ; line 251 : } + 931 931 $DGL 0,6 + 932 932 00067 ??ef_fn_intmd: + 933 933 00067 61FC reti ;[INF] 2, 6 + 934 934 00069 ??ee_fn_intmd: + 935 935 ; line 252 : + 936 936 ; line 253 : __interrupt void fn_inttm04( ) + 937 937 ; line 254 : { + 938 938 00069 _fn_inttm04: + 939 939 $DGL 1,237 + 940 940 00069 ??bf_fn_inttm04: + 941 941 ; line 255 : while( 1 ) + 942 942 00069 ?L0087: + 943 943 ; line 256 : { + 944 944 00069 ??bb00_fn_inttm04: + 945 945 ; line 257 : NOP(); + 946 946 $DGL 0,4 + 947 947 00069 00 nop ;[INF] 1, 1 + 948 948 0006A ??eb00_fn_inttm04: + 949 949 ; line 258 : } + 950 950 $DGL 0,5 + 951 951 0006A EFFD br $?L0087 ;[INF] 2, 3 + 952 952 ; line 259 : } + 953 953 $DGL 0,6 + 954 954 0006C ??ef_fn_inttm04: + 955 955 0006C 61FC reti ;[INF] 2, 6 + 956 956 0006E ??ee_fn_inttm04: + 957 957 ; line 260 : + 958 958 ; line 261 : __interrupt void fn_inttm05( ) + 959 959 ; line 262 : { + 960 960 0006E _fn_inttm05: + 961 961 $DGL 1,247 + 962 962 0006E ??bf_fn_inttm05: + 963 963 ; line 263 : while( 1 ) + 964 964 0006E ?L0091: + 965 965 ; line 264 : { + 966 966 0006E ??bb00_fn_inttm05: + 967 967 ; line 265 : NOP(); + 968 968 $DGL 0,4 + 969 969 0006E 00 nop ;[INF] 1, 1 + 970 970 0006F ??eb00_fn_inttm05: + 971 971 ; line 266 : } + 972 972 $DGL 0,5 + 973 973 0006F EFFD br $?L0091 ;[INF] 2, 3 + 974 974 ; line 267 : } + 975 975 $DGL 0,6 + 976 976 00071 ??ef_fn_inttm05: + 977 977 00071 61FC reti ;[INF] 2, 6 + 978 978 00073 ??ee_fn_inttm05: + 979 979 ; line 268 : + 980 980 ; line 269 : __interrupt void fn_inttm06( ) + 981 981 ; line 270 : { + 982 982 00073 _fn_inttm06: + 983 983 $DGL 1,257 + 984 984 00073 ??bf_fn_inttm06: + 985 985 ; line 271 : while( 1 ) + 986 986 00073 ?L0095: + 987 987 ; line 272 : { + 988 988 00073 ??bb00_fn_inttm06: + 989 989 ; line 273 : NOP(); + 990 990 $DGL 0,4 + 991 991 00073 00 nop ;[INF] 1, 1 + 992 992 00074 ??eb00_fn_inttm06: + 993 993 ; line 274 : } + 994 994 $DGL 0,5 + 995 995 00074 EFFD br $?L0095 ;[INF] 2, 3 + 996 996 ; line 275 : } + 997 997 $DGL 0,6 + 998 998 00076 ??ef_fn_inttm06: + 999 999 00076 61FC reti ;[INF] 2, 6 + 1000 1000 00078 ??ee_fn_inttm06: + 1001 1001 ; line 276 : + 1002 1002 ; line 277 : __interrupt void fn_inttm07( ) + 1003 1003 ; line 278 : { + 1004 1004 00078 _fn_inttm07: + 1005 1005 $DGL 1,267 + 1006 1006 00078 ??bf_fn_inttm07: + 1007 1007 ; line 279 : while( 1 ) + 1008 1008 00078 ?L0099: + 1009 1009 ; line 280 : { + 1010 1010 00078 ??bb00_fn_inttm07: + 1011 1011 ; line 281 : NOP(); + 1012 1012 $DGL 0,4 + 1013 1013 00078 00 nop ;[INF] 1, 1 + 1014 1014 00079 ??eb00_fn_inttm07: + 1015 1015 ; line 282 : } + 1016 1016 $DGL 0,5 + 1017 1017 00079 EFFD br $?L0099 ;[INF] 2, 3 + 1018 1018 ; line 283 : } + 1019 1019 $DGL 0,6 + 1020 1020 0007B ??ef_fn_inttm07: + 1021 1021 0007B 61FC reti ;[INF] 2, 6 + 1022 1022 0007D ??ee_fn_inttm07: + 1023 1023 + 1024 1024 ----- @@VECT10 CSEG AT 0010H + 1025 1025 00010 _@vect10: + 1026 1026 00010 R0000 DW _intp4_extdc + 1027 1027 00012 _@vect12: + 1028 1028 00012 R0000 DW _intp5_shell + 1029 1029 + 1030 1030 ----- @@VECT1C CSEG AT 001CH + 1031 1031 0001C _@vect1c: + 1032 1032 0001C R0000 DW _int_dma1 + 1033 1033 + 1034 1034 ----- @@VECT24 CSEG AT 0024H + 1035 1035 00024 _@vect24: + 1036 1036 00024 R0000 DW _int_iic10 + 1037 1037 + 1038 1038 ----- @@VECT2A CSEG AT 002AH + 1039 1039 0002A _@vect2a: + 1040 1040 0002A R0000 DW _int_iic_twl + 1041 1041 + 1042 1042 ----- @@VECT34 CSEG AT 0034H + 1043 1043 00034 _@vect34: + 1044 1044 00034 R0000 DW _int_adc + 1045 1045 00036 _@vect36: + 1046 1046 00036 R0000 DW _int_rtc + 1047 1047 00038 _@vect38: + 1048 1048 00038 R0000 DW _int_rtc_int + 1049 1049 0003A _@vect3a: + 1050 1050 0003A R0000 DW _int_kr + 1051 1051 + 1052 1052 ----- @@VECT4A CSEG AT 004AH + 1053 1053 0004A _@vect4a: + 1054 1054 0004A R0000 DW _intp6_PM_irq + 1055 1055 + 1056 1056 ----- @@VECT5A CSEG AT 005AH + 1057 1057 0005A _@vect5a: + 1058 1058 0005A R0000 DW _int_iic_ctr + 1059 1059 + 1060 1060 ----- @@VECT62 CSEG AT 0062H + 1061 1061 00062 _@vect62: + 1062 1062 00062 R0000 DW _intp23_ACC_ready + 1063 1063 + 1064 1064 ----- @@CODE CSEG BASE + 1065 1065 + 1066 1066 ----- @@CODEL CSEG + 1067 1067 END + 1068 1068 + 1069 1069 + 1070 1070 ; *** Code Information *** + 1071 1071 ; + 1072 1072 ; $FILE C:\78k_data\yav-mcu-basara_0.10\ini_VECT.c + 1073 1073 ; + 1074 1074 ; $FUNC fn_intwdti(75) + 1075 1075 ; void=(void) + 1076 1076 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1077 1077 ; + 1078 1078 ; $FUNC fn_intlvi(82) + 1079 1079 ; void=(void) + 1080 1080 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1081 1081 ; + 1082 1082 ; $FUNC fn_intp0(89) + 1083 1083 ; void=(void) + 1084 1084 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1085 1085 ; + 1086 1086 ; $FUNC fn_intp1(97) + 1087 1087 ; void=(void) + 1088 1088 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1089 1089 ; + 1090 1090 ; $FUNC fn_intp2(104) + 1091 1091 ; void=(void) + 1092 1092 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1093 1093 ; + 1094 1094 ; $FUNC fn_intp3(111) + 1095 1095 ; void=(void) + 1096 1096 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1097 1097 ; + 1098 1098 ; $FUNC intp21_RFTx(120) + 1099 1099 ; void=(void) + 1100 1100 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1101 1101 ; + 1102 1102 ; $FUNC fn_intcmp0(135) + 1103 1103 ; void=(void) + 1104 1104 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1105 1105 ; + 1106 1106 ; $FUNC fn_intcmp1(142) + 1107 1107 ; void=(void) + 1108 1108 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1109 1109 ; + 1110 1110 ; $FUNC fn_intdma0(149) + 1111 1111 ; void=(void) + 1112 1112 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1113 1113 ; + 1114 1114 ; $FUNC fn_intst0(159) + 1115 1115 ; void=(void) + 1116 1116 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1117 1117 ; + 1118 1118 ; $FUNC fn_intsr0(168) + 1119 1119 ; void=(void) + 1120 1120 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1121 1121 ; + 1122 1122 ; $FUNC fn_intsre0(177) + 1123 1123 ; void=(void) + 1124 1124 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1125 1125 ; + 1126 1126 ; $FUNC fn_intst1(185) + 1127 1127 ; void=(void) + 1128 1128 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1129 1129 ; + 1130 1130 ; $FUNC fn_intsr1(195) + 1131 1131 ; void=(void) + 1132 1132 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1133 1133 ; + 1134 1134 ; $FUNC fn_intsre1(202) + 1135 1135 ; void=(void) + 1136 1136 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1137 1137 ; + 1138 1138 ; $FUNC fn_inttm01(212) + 1139 1139 ; void=(void) + 1140 1140 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1141 1141 ; + 1142 1142 ; $FUNC fn_inttm02(220) + 1143 1143 ; void=(void) + 1144 1144 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1145 1145 ; + 1146 1146 ; $FUNC fn_inttm03(227) + 1147 1147 ; void=(void) + 1148 1148 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1149 1149 ; + 1150 1150 ; $FUNC fn_intrtc(236) + 1151 1151 ; void=(void) + 1152 1152 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1153 1153 ; + 1154 1154 ; $FUNC fn_intmd(246) + 1155 1155 ; void=(void) + 1156 1156 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1157 1157 ; + 1158 1158 ; $FUNC fn_inttm04(254) + 1159 1159 ; void=(void) + 1160 1160 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1161 1161 ; + 1162 1162 ; $FUNC fn_inttm05(262) + 1163 1163 ; void=(void) + 1164 1164 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1165 1165 ; + 1166 1166 ; $FUNC fn_inttm06(270) + 1167 1167 ; void=(void) + 1168 1168 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1169 1169 ; + 1170 1170 ; $FUNC fn_inttm07(278) + 1171 1171 ; void=(void) + 1172 1172 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + 1173 1173 + 1174 1174 ; Target chip : uPD79F0104 + 1175 1175 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00000H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00000H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0007DH @@BASE +00010 00004H @@VECT10 +0001C 00002H @@VECT1C +00024 00002H @@VECT24 +0002A 00002H @@VECT2A +00034 00008H @@VECT34 +0004A 00002H @@VECT4A +0005A 00002H @@VECT5A +00062 00002H @@VECT62 +00000 00000H @@CODE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/ini_VECT.rel b/branches/0.10(X3)/ini_VECT.rel new file mode 100644 index 0000000..5ca48ca Binary files /dev/null and b/branches/0.10(X3)/ini_VECT.rel differ diff --git a/branches/0.10(X3)/inter_asm/WDT.asm b/branches/0.10(X3)/inter_asm/WDT.asm new file mode 100644 index 0000000..06ae5d4 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/WDT.asm @@ -0,0 +1,111 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no WDT.c +; In-file : WDT.c +; Asm-file : inter_asm\WDT.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, WDT.c +$DGS MOD_NAM, WDT, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H +$DGS BEG_FUN, ??bf_WDT_Restart, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 019H +$DGS END_FUN, ??ef_WDT_Restart, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03H + + PUBLIC _WDT_Restart + +@@BITS BSEG + +@@CNST CSEG MIRRORP + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +LDR_CNSL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : #pragma sfr +; line 2 : +; line 3 : +; line 4 : #include "incs_loader.h" +; line 5 : +; line 6 : +; line 7 : +; line 8 : //========================================================= +; line 9 : // ウォッチドッグタイマのリスタート +; line 10 : // 0xACはマジック +; line 11 : void WDT_Restart( void ) +; line 12 : { + +LDR_CODE CSEG BASE +_WDT_Restart: +$DGL 1,19 +??bf_WDT_Restart: +; line 13 : WDTE = WDT_RESTART_MAGIC; +$DGL 0,2 + mov WDTE,#0ACH ; 172 ;[INF] 3, 1 +; line 14 : } +$DGL 0,3 +??ef_WDT_Restart: + ret ;[INF] 1, 6 +??ee_WDT_Restart: + +LDR_CODL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c +; +; $FUNC WDT_Restart(12) +; void=(void) +; CODE SIZE= 4 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/accero.asm b/branches/0.10(X3)/inter_asm/accero.asm new file mode 100644 index 0000000..0b769df --- /dev/null +++ b/branches/0.10(X3)/inter_asm/accero.asm @@ -0,0 +1,984 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no accero.c +; In-file : accero.c +; Asm-file : inter_asm\accero.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0B7H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, accero.c +$DGS MOD_NAM, accero, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 047H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 041H, 01H +$DGS LAB_SYM, bs_F0038, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0038, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 067H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 042H, 06H, 04FH +$DGS BEG_BLK, ??bb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 053H +$DGS END_BLK, ??eb00_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS BEG_BLK, ??bb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 055H +$DGS BEG_BLK, ??bb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 057H +$DGS BEG_BLK, ??bb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 05FH +$DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 021H, 06H, 06H, 00H, 00H, 00H, 00H +$DGS END_BLK, ??eb03_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS END_BLK, ??eb02_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 024H +$DGS BEG_BLK, ??bb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 029H, 00H, 00H +$DGS END_BLK, ??eb04_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02DH +$DGS END_BLK, ??eb01_tsk_cbk_accero, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02EH +$DGS END_FUN, ??ef_tsk_cbk_accero, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 030H +$DGS GLV_SYM, _acc_read, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 075H, 00H, 00H +$DGS BEG_FUN, ??bf_acc_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 07BH, 00H, 06BH +$DGS BEG_BLK, ??bb00_acc_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 06DH +$DGS BEG_BLK, ??bb01_acc_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 00H +$DGS END_BLK, ??eb01_acc_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS END_BLK, ??eb00_acc_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS END_FUN, ??ef_acc_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0AH +$DGS GLV_SYM, _acc_write, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 083H, 00H, 00H +$DGS BEG_FUN, ??bf_acc_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 08CH, 00H, 079H +$DGS BEG_BLK, ??bb00_acc_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 07BH +$DGS BEG_BLK, ??bb01_acc_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 00H +$DGS END_BLK, ??eb01_acc_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06H +$DGS END_BLK, ??eb00_acc_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS END_FUN, ??ef_acc_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09H +$DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0A5H, 00H, 00H +$DGS BEG_FUN, ??bf_acc_hosu_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09EH, 0AH, 089H +$DGS AUT_VAR, _str_send_buf, 06H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 08DH +$DGS END_BLK, ??eb00_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 091H +$DGS END_BLK, ??eb01_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS BEG_BLK, ??bb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 095H +$DGS END_BLK, ??eb02_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02FH +$DGS BEG_BLK, ??bb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 031H, 00H, 099H +$DGS END_BLK, ??eb03_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03AH +$DGS BEG_BLK, ??bb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03FH, 00H, 09BH +$DGS BEG_BLK, ??bb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 041H, 00H, 00H +$DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 042H, 06H, 06H, 00H, 00H, 00H, 00H +$DGS END_BLK, ??eb05_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 044H +$DGS END_BLK, ??eb04_acc_hosu_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 045H +$DGS END_FUN, ??ef_acc_hosu_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 047H +$DGS GLV_SYM, _intp23_ACC_ready, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0B7H, 00H, 00H +$DGS BEG_FUN, ??bf_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0EDH, 016H, 0A9H +$DGS BEG_BLK, ??bb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 0ABH +$DGS BEG_BLK, ??bb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0ADH +$DGS BEG_BLK, ??bb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 00H +$DGS END_BLK, ??eb02_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0AH +$DGS END_BLK, ??eb01_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS END_BLK, ??eb00_intp23_ACC_ready, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS END_FUN, ??ef_intp23_ACC_ready, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0DH +$DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _pedometer, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + + EXTRN _iic_mcu_read + EXTRN _vreg_ctr + EXTRN _system_status + EXTRN _set_irq + EXTRN _pedometer + EXTRN _iic_mcu_read_a_byte + EXTRN _iic_mcu_write_a_byte + EXTRN _iic_mcu_bus_status + EXTRN _iic_mcu_write + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _@RTARG0 + EXTRN _renge_task_immed_add + PUBLIC _tsk_cbk_accero + PUBLIC _acc_read + PUBLIC _acc_write + PUBLIC _acc_hosu_set + PUBLIC _intp23_ACC_ready + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0038: + push ax ;[INF] 1, 1 + movw ax,#06H ; 6 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0A8H ; 168 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_read ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0038: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0038 +; CODE SIZE= 16 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : 　加速度センサ関係 +; line 3 : ・データ更新完了でデータを吸い上げ手レジスタを更新、CPUに割り込み +; line 4 : ・フラグが立っていれば歩数カウント +; line 5 : ・加速度センサ割り込みからタスクを登録して下さい。（I2Cの競合回避 +; などがあるので） +; line 6 : +; line 7 : ======================================================== */ +; line 8 : #pragma SFR +; line 9 : #pragma NOP +; line 10 : #pragma HALT +; line 11 : #pragma STOP +; line 12 : #pragma ROT +; line 13 : // rorb, rolb, rorw, rolw +; line 14 : #pragma MUL +; line 15 : #pragma BCD +; line 16 : +; line 17 : #include "incs.h" +; line 18 : #include +; line 19 : +; line 20 : // ======================================================== +; line 21 : // レジスタ名 +; line 22 : #define ACC_REG_WHOAMI 0x0F +; line 23 : #define ACC_REG_CTRL1 0x20 +; line 24 : #define ACC_REG_CTRL5 0x24 +; line 25 : #define ACC_REG_X 0x28 +; line 26 : +; line 27 : // ビット位置 +; line 28 : #define ACC_bP_PM0 5 +; line 29 : #define ACC_bP_DR0 3 +; line 30 : +; line 31 : // ビット設定値 +; line 32 : #define ACC_BITS_PM_PDN 0 +; line 33 : #define ACC_BITS_PM_NORM 1 +; line 34 : #define ACC_BITS_PM_LP0R5 2 +; line 35 : #define ACC_BITS_PM_LP1 3 +; line 36 : #define ACC_BITS_PM_LP2 4 +; line 37 : #define ACC_BITS_PM_LP5 5 +; line 38 : #define ACC_BITS_PM_LP10 6 +; line 39 : +; line 40 : #define ACC_BITS_DR_50Hz 0 +; line 41 : #define ACC_BITS_DR_100Hz 1 +; line 42 : #define ACC_BITS_DR_400Hz 2 +; line 43 : #define ACC_BITS_DR_1000Hz 3 +; line 44 : +; line 45 : #define ACC_BITS_ALL_AXIS_ON 7 +; line 46 : +; line 47 : +; line 48 : #define VREG_BITMASK_ACC_CONF_ACQ ( 1 << 0 ) +; line 49 : #define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 ) +; line 50 : +; line 51 : +; line 52 : +; line 53 : +; line 54 : // ======================================================== +; line 55 : task_status tsk_soft_int( ); +; line 56 : +; line 57 : +; line 58 : +; line 59 : /* ======================================================== +; line 60 : 　・割り込みを確認してデータを吸い上げ、レジスタに書き出します +; line 61 : ・本当であればコールバック関数を登録しておけばいいじゃんとなる +; のですが、 +; line 62 : I2Cが使用中だったら？とか考えると私ではそこまでできないのです。 +; line 63 : ・自動歩数計とかでも結局 +; line 64 : ======================================================== */ +; line 65 : task_status_immed tsk_cbk_accero( ) +; line 66 : { // （疑似）isrから登録されます + +ROM_CODE CSEG BASE +_tsk_cbk_accero: +$DGL 1,75 + push hl ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_tsk_cbk_accero: +; line 67 : +; line 68 : /* +; line 69 : if(( system_status.pwr_state == OFF ) || ( system_status.pwr +; _state == BT_CHARGE ) ) +; line 70 : { +; line 71 : return ( ERR_SUCCESS ); +; line 72 : } +; line 73 : else +; line 74 : { +; line 75 : */ +; line 76 : // 加速度センサデータレジスタへの反映 +; line 77 : if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6 +; , &vreg_ctr[VREG_C_ACC_XL] ) +; line 78 : != ERR_SUCCESS ) +$DGL 0,13 + movw de,#loww (_vreg_ctr+69) ;[INF] 3, 1 + push de ;[INF] 1, 1 + movw ax,#06H ; 6 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0A8H ; 168 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_read ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 + cmp0 c ;[INF] 1, 1 + bz $?L0003 ;[INF] 2, 4 +; line 79 : { +??bb00_tsk_cbk_accero: +; line 80 : // 加速度センサが異常になったので止める +; line 81 : vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_ +; HOSU | VREG_BITMASK_ACC_CONF_ACQ ); +$DGL 0,16 + movw de,#loww (_vreg_ctr+64) ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + and a,#0FCH ; 252 ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 82 : // vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; +; line 83 : acc_hosu_set(); +$DGL 0,18 + call !_acc_hosu_set ;[INF] 3, 3 +; line 84 : return ( ERR_SUCCESS ); // タスクの削除は必要 +$DGL 0,19 + clrw bc ;[INF] 1, 1 + br $?L0002 ;[INF] 2, 3 +??eb00_tsk_cbk_accero: +; line 85 : } +?L0003: +; line 86 : else +; line 87 : { +??bb01_tsk_cbk_accero: +; line 88 : // 正常時パス // +; line 89 : // 加速度更新＆割り込み +; line 90 : if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO +; NF_ACQ ) != 0 ) && +$DGL 0,25 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0007 ;[INF] 2, 4 +; line 91 : ( system_status.pwr_state == ON ) +$DGL 0,26 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bnz $?L0007 ;[INF] 2, 4 +; line 92 : ) +; line 93 : { +??bb02_tsk_cbk_accero: +; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY ); +$DGL 0,29 + movw ax,#010H ; 16 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 95 : // ゴミデータのカラ読み +; line 96 : if( ACC_VALID == 1 ) +$DGL 0,31 + push hl ;[INF] 1, 1 + movw hl,#0510H ; 1296 ;[INF] 3, 1 + mov1 CY,[hl].5 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0007 ;[INF] 2, 4 +; line 97 : { +??bb03_tsk_cbk_accero: +; line 98 : u8 temp[6]; +; line 99 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 +; ), 6, temp ); +$DGL 0,34 + movw ax,hl ;[INF] 1, 1 + call !bs_F0038 ;[INF] 3, 3 +??eb03_tsk_cbk_accero: +; line 100 : } +?L0007: +??eb02_tsk_cbk_accero: +; line 101 : } +; line 102 : if(( system_status.pwr_state != OFF ) && +; line 103 : ( system_status.pwr_state != BT_CHARGE ) && +$DGL 0,38 + cmp !_system_status,#01H ; 1 ;[INF] 4, 1 + bz $?L0009 ;[INF] 2, 4 + cmp !_system_status,#06H ; 6 ;[INF] 4, 1 + bz $?L0009 ;[INF] 2, 4 +; line 104 : ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO +; NF_HOSU ) != 0 ) +$DGL 0,39 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 +; line 105 : ) +; line 106 : { +??bb04_tsk_cbk_accero: +; line 107 : DBG_LED_WIFI_2_on; +; line 108 : pedometer(); // 歩数計 +$DGL 0,43 + call !_pedometer ;[INF] 3, 3 +; line 109 : DBG_LED_WIFI_2_off; +??eb04_tsk_cbk_accero: +; line 110 : } +?L0009: +??eb01_tsk_cbk_accero: +; line 111 : } +; line 112 : return ( ERR_SUCCESS ); +$DGL 0,47 + clrw bc ;[INF] 1, 1 +; line 113 : } +?L0002: +$DGL 0,48 +??ef_tsk_cbk_accero: + addw sp,#06H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_cbk_accero: +; line 114 : +; line 115 : +; line 116 : +; line 117 : +; line 118 : +; line 119 : /*======================================================= +; line 120 : 　加速度センサ透過アクセス　リード +; line 121 : ========================================================*/ +; line 122 : task_status_immed acc_read( ) +; line 123 : { +_acc_read: +$DGL 1,103 +??bf_acc_read: +; line 124 : vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_AC +; CEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); +$DGL 0,2 + mov x,!_vreg_ctr+65 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov !_vreg_ctr+68,a ;[INF] 3, 1 +; line 125 : // vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_ +; ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] ); +; line 126 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; +$DGL 0,4 + set1 !_vreg_ctr+17.3 ;[INF] 4, 2 +; line 127 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) +$DGL 0,5 + mov a,!_vreg_ctr+25 ;[INF] 3, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0013 ;[INF] 2, 4 +; line 128 : { +??bb00_acc_read: +; line 129 : IRQ0_ast; +$DGL 0,7 +??bb01_acc_read: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb01_acc_read: +??eb00_acc_read: +; line 130 : } +?L0013: +; line 131 : return ( ERR_SUCCESS ); +$DGL 0,9 + clrw bc ;[INF] 1, 1 +; line 132 : } +$DGL 0,10 +??ef_acc_read: + ret ;[INF] 1, 6 +??ee_acc_read: +; line 133 : +; line 134 : +; line 135 : +; line 136 : /*========================================================= +; line 137 : 　加速度センサ透過アクセス　ライト +; line 138 : ========================================================*/ +; line 139 : task_status_immed acc_write( ) +; line 140 : { +_acc_write: +$DGL 1,117 +??bf_acc_write: +; line 141 : iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_A +; DRS], vreg_ctr[VREG_C_ACC_W_BUF] ); +$DGL 0,2 + mov x,!_vreg_ctr+68 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,!_vreg_ctr+67 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 142 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK; +$DGL 0,3 + set1 !_vreg_ctr+17.3 ;[INF] 4, 2 +; line 143 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 ) +$DGL 0,4 + mov a,!_vreg_ctr+25 ;[INF] 3, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0017 ;[INF] 2, 4 +; line 144 : { +??bb00_acc_write: +; line 145 : IRQ0_ast; +$DGL 0,6 +??bb01_acc_write: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb01_acc_write: +??eb00_acc_write: +; line 146 : } +?L0017: +; line 147 : return ( ERR_SUCCESS ); +$DGL 0,8 + clrw bc ;[INF] 1, 1 +; line 148 : } +$DGL 0,9 +??ef_acc_write: + ret ;[INF] 1, 6 +??ee_acc_write: +; line 149 : +; line 150 : +; line 151 : +; line 152 : /*========================================================= +; line 153 : 　自動歩数カウントモードにセット +; line 154 : todo 他のモードだったら止めたり、復帰させたり +; line 155 : 割り込みルーチンなどでカウント判定が必要 +; line 156 : ========================================================*/ +; line 157 : task_status_immed acc_hosu_set( ) +; line 158 : { +_acc_hosu_set: +$DGL 1,131 + push hl ;[INF] 1, 1 + subw sp,#0AH ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_acc_hosu_set: +; line 159 : u8 str_send_buf[4]; +; line 160 : +; line 161 : iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI ); +$DGL 0,4 + movw ax,#0FH ; 15 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 162 : if( iic_mcu_bus_status == ERR_NOSLAVE ) +$DGL 0,5 + cmp !_iic_mcu_bus_status,#02H ; 2 ;[INF] 4, 1 + bnz $?L0021 ;[INF] 2, 4 +; line 163 : { +??bb00_acc_hosu_set: +; line 164 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR; +$DGL 0,7 + set1 !_vreg_ctr+14.1 ;[INF] 4, 2 +; line 165 : #ifdef _MCU_BSR_ +; line 166 : // PMK23 = 1; +; line 167 : #endif +; line 168 : return ( ERR_SUCCESS ); // とりあえず、タスクは削除しなく +; てはならない +$DGL 0,11 + clrw bc ;[INF] 1, 1 + br $?L0020 ;[INF] 2, 3 +??eb00_acc_hosu_set: +; line 169 : }else{ +?L0021: +??bb01_acc_hosu_set: +; line 170 : vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR; +$DGL 0,13 + clr1 !_vreg_ctr+14.1 ;[INF] 4, 2 +??eb01_acc_hosu_set: +; line 171 : } +; line 172 : +; line 173 : +; line 174 : str_send_buf[1] = 0x00; // ctrl2 HPF:normal, filterd, H +; PF for IRQ : dis/dis, HPF coeff:norm +$DGL 0,17 + mov [hl+7],#00H ; str_send_buf,0 ;[INF] 3, 1 +; line 175 : #ifdef _MODEL_WM0_ +; line 176 : # ifdef _MODEL_WM0_TEG2_CTRC_ +; line 177 : str_send_buf[2] = 0x02; // 回路が一部違う +; line 178 : # else +; line 179 : +; line 180 : str_send_buf[2] = 0x10; // 3 IRQ pol :Active HI, Dr +; ive:Pushpull, +; line 181 : /// IRQ2flg latch: auto cl +; ear after read, IRQ2 conf: IRQ( fall,shock,...) +; line 182 : /// 1 : auto cl +; ear after read, conf: data ready +; line 183 : # endif +; line 184 : #else +; line 185 : # ifdef _MODEL_CTR_JIKKI_ +; line 186 : str_send_buf[2] = 0x10; +; line 187 : # else +; line 188 : str_send_buf[2] = 0x02; // 3 IRQ pol :Active HI, Dr +; ive:Pushpull, +$DGL 0,31 + mov [hl+8],#02H ; str_send_buf,2 ;[INF] 3, 1 +; line 189 : /// IRQ2flg latch: auto cl +; ear after read, IRQ2 conf: IRQ( fall,shock,...) +; line 190 : /// 1 : auto cl +; ear after read, conf: data ready +; line 191 : # endif +; line 192 : #endif +; line 193 : str_send_buf[3] = 0x80; // ctrl3 block update:enable, M +; SB first, scale: +-2G(default), selftest: dis +$DGL 0,36 + mov [hl+9],#080H ; str_send_buf,128 ;[INF] 3, 1 +; line 194 : +; line 195 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & +; line 196 : ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_A +; CQ ) ) == 0 ) +$DGL 0,39 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0023 ;[INF] 2, 4 +; line 197 : { +??bb02_acc_hosu_set: +; line 198 : #ifdef _MCU_BSR_ +; line 199 : PMK23 = 1; +$DGL 0,42 + set1 MK2H.7 ;[INF] 3, 2 +; line 200 : #endif +; line 201 : // 完全停止 +; line 202 : str_send_buf[0] = +; line 203 : ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | +; ACC_BITS_ALL_AXIS_ON ); +$DGL 0,46 + mov [hl+6],#07H ; str_send_buf,7 ;[INF] 3, 1 +??eb02_acc_hosu_set: +; line 204 : } +$DGL 0,47 + br $?L0024 ;[INF] 2, 3 +?L0023: +; line 205 : else +; line 206 : { +??bb03_acc_hosu_set: +; line 207 : #ifdef _MCU_BSR_ +; line 208 : PMK23 = 0; +$DGL 0,51 + clr1 MK2H.7 ;[INF] 3, 2 +; line 209 : #endif +; line 210 : // 100Hz 自動取り込み +; line 211 : str_send_buf[0] = +; line 212 : ( ACC_BITS_PM_NORM << ACC_bP_PM0 +; line 213 : | ACC_BITS_DR_100Hz << ACC_bP_DR0 +; line 214 : | ACC_BITS_ALL_AXIS_ON ); +$DGL 0,57 + mov [hl+6],#02FH ; str_send_buf,47 ;[INF] 3, 1 +??eb03_acc_hosu_set: +; line 215 : } +?L0024: +; line 216 : iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, s +; tr_send_buf ); +$DGL 0,59 + movw ax,hl ;[INF] 1, 1 + addw ax,#06H ;[INF] 3, 1 + push ax ;[INF] 1, 1 + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0A0H ; 160 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#030H ; 48 ;[INF] 2, 1 + call !_iic_mcu_write ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 217 : +; line 218 : // カラ読み +; line 219 : if( ACC_VALID == 1 ) +$DGL 0,62 + push hl ;[INF] 1, 1 + movw hl,#0510H ; 1296 ;[INF] 3, 1 + mov1 CY,[hl].5 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0027 ;[INF] 2, 4 +; line 220 : { +??bb04_acc_hosu_set: +; line 221 : if( system_status.pwr_state == ON ) +$DGL 0,64 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bnz $?L0027 ;[INF] 2, 4 +; line 222 : { +??bb05_acc_hosu_set: +; line 223 : u8 temp[6]; +; line 224 : iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6 +; , temp ); +$DGL 0,67 + movw ax,hl ;[INF] 1, 1 + call !bs_F0038 ;[INF] 3, 3 +??eb05_acc_hosu_set: +; line 225 : } +?L0027: +??eb04_acc_hosu_set: +; line 226 : } +; line 227 : return ( ERR_SUCCESS ); +$DGL 0,70 + clrw bc ;[INF] 1, 1 +; line 228 : } +?L0020: +$DGL 0,71 +??ef_acc_hosu_set: + addw sp,#0AH ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_acc_hosu_set: +; line 229 : +; line 230 : +; line 231 : +; line 232 : /* ======================================================== +; line 233 : 加速度センサ割り込み +; line 234 : I2Cが使用中かもしれないので、読み出しタスクの登録を行うのみ +; line 235 : ======================================================== */ +; line 236 : __interrupt void intp23_ACC_ready( ) +; line 237 : { + +@@BASE CSEG BASE +_intp23_ACC_ready: +$DGL 1,165 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_intp23_ACC_ready: +; line 238 : EI(); +$DGL 0,2 + ei ;[INF] 3, 4 +; line 239 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) +$DGL 0,3 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0036 ;[INF] 2, 4 +; line 240 : { +??bb00_intp23_ACC_ready: +; line 241 : if( ( system_status.pwr_state == ON ) || ( system_status +; .pwr_state == SLEEP ) ) +$DGL 0,5 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bz $?L0035 ;[INF] 2, 4 + cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + bnz $?L0036 ;[INF] 2, 4 +?L0035: +; line 242 : { +??bb01_intp23_ACC_ready: +; line 243 : if( ACC_VALID ) +$DGL 0,7 + movw hl,#0510H ; 1296 ;[INF] 3, 1 + mov1 CY,[hl].5 ;[INF] 2, 1 + bnc $?L0036 ;[INF] 2, 4 +; line 244 : { +??bb02_intp23_ACC_ready: +; line 245 : renge_task_immed_add( tsk_cbk_accero ); +$DGL 0,9 + movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb02_intp23_ACC_ready: +; line 246 : } +?L0036: +??eb01_intp23_ACC_ready: +; line 247 : } +??eb00_intp23_ACC_ready: +; line 248 : } +; line 249 : } +$DGL 0,13 +??ef_intp23_ACC_ready: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_intp23_ACC_ready: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c +; +; $FUNC tsk_cbk_accero(66) +; bc=(void) +; CODE SIZE= 104 bytes, CLOCK_SIZE= 103 clocks, STACK_SIZE= 22 bytes +; +; $CALL iic_mcu_read(78) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL acc_hosu_set(83) +; bc=(void) +; +; $CALL set_irq(94) +; void=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_read(99) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL pedometer(108) +; void=(void) +; +; $FUNC acc_read(123) +; bc=(void) +; CODE SIZE= 35 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes +; +; $CALL iic_mcu_read_a_byte(124) +; bc=(int:ax, int:[sp+4]) +; +; $FUNC acc_write(140) +; bc=(void) +; CODE SIZE= 36 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 8 bytes +; +; $CALL iic_mcu_write_a_byte(141) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC acc_hosu_set(158) +; bc=(void) +; CODE SIZE= 107 bytes, CLOCK_SIZE= 96 clocks, STACK_SIZE= 26 bytes +; +; $CALL iic_mcu_read_a_byte(161) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write(216) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_read(224) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $FUNC intp23_ACC_ready(237) +; void=(void) +; CODE SIZE= 80 bytes, CLOCK_SIZE= 73 clocks, STACK_SIZE= 26 bytes +; +; $CALL renge_task_immed_add(245) +; bc=(pointer:ax) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/adc.asm b/branches/0.10(X3)/inter_asm/adc.asm new file mode 100644 index 0000000..a05a9ee --- /dev/null +++ b/branches/0.10(X3)/inter_asm/adc.asm @@ -0,0 +1,1463 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no adc.c +; In-file : adc.c +; Asm-file : inter_asm\adc.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0FAH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, adc.c +$DGS MOD_NAM, adc, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 047H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 041H, 01H +$DGS LAB_SYM, bs_S0076, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0076, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0075, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0075, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0074, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0074, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS STA_SYM, _slider_to_codec, U, U, 0500CH, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 040H, 040H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_adc, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0B5H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 03DH, 02H, 059H +$DGS STA_SYM, _task_interval, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _old_tune, ?L0004, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _sndvol_codec, ?L0005, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _bt_temp_old, ?L0006, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 05DH +$DGS END_BLK, ??eb00_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0AH +$DGS BEG_BLK, ??bb01_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 061H +$DGS END_BLK, ??eb01_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS BEG_BLK, ??bb02_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 063H +$DGS BEG_BLK, ??bb03_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 065H +$DGS BEG_BLK, ??bb04_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 06DH +$DGS STA_SYM, _old_value, ?L0007, U, 0CH, 03H, 01H, 00H +$DGS AUX_STR, 00H, 01AH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _diffs, ?L0008, U, 02H, 03H, 01H, 00H +$DGS AUX_STR, 00H, 01BH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 01CH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb05_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01FH, 00H, 071H +$DGS END_BLK, ??eb05_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS BEG_BLK, ??bb06_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 075H +$DGS STA_SYM, _kikan_count, ?L0009, U, 0CH, 03H, 01H, 00H +$DGS AUX_STR, 00H, 02EH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb07_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 079H +$DGS END_BLK, ??eb07_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 032H +$DGS BEG_BLK, ??bb08_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 034H, 00H, 07DH +$DGS END_BLK, ??eb08_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 036H +$DGS BEG_BLK, ??bb09_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 039H, 00H, 07FH +$DGS BEG_BLK, ??bb0A_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03BH, 00H, 083H +$DGS END_BLK, ??eb0A_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03DH +$DGS BEG_BLK, ??bb0B_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03FH, 00H, 08DH +$DGS END_BLK, ??eb0B_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 041H +$DGS END_BLK, ??eb09_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 045H +$DGS END_BLK, ??eb06_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 046H +$DGS END_BLK, ??eb04_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 047H +$DGS BEG_BLK, ??bb0C_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04CH, 00H, 095H +$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 04EH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _vol_old, ?L0010, U, 0CH, 03H, 01H, 00H +$DGS AUX_STR, 00H, 04FH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _force_update_vol, ?L0011, U, 0CH, 03H, 01H, 00H +$DGS AUX_STR, 00H, 050H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb0D_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 053H, 00H, 097H +$DGS BEG_BLK, ??bb0E_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 055H, 00H, 09DH +$DGS END_BLK, ??eb0E_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 062H +$DGS END_BLK, ??eb0D_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 063H +$DGS BEG_BLK, ??bb0F_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 065H, 00H, 09FH +$DGS BEG_BLK, ??bb10_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 068H, 00H, 0A7H +$DGS END_BLK, ??eb10_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 070H +$DGS END_BLK, ??eb0F_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 071H +$DGS END_BLK, ??eb0C_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 072H +$DGS BEG_BLK, ??bb11_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 077H, 00H, 0A9H +$DGS BEG_BLK, ??bb12_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 079H, 00H, 00H +$DGS END_BLK, ??eb12_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 086H +$DGS END_BLK, ??eb11_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 087H +$DGS END_BLK, ??eb03_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 089H +$DGS END_BLK, ??eb02_tsk_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08AH +$DGS END_FUN, ??ef_tsk_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09FH +$DGS STA_SYM, _getmean3, U, U, 0CH, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0D5H, 00H, 00H +$DGS BEG_FUN, ??bf_getmean3, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0E4H, 02H, 0BBH +$DGS REG_PAR, _hist, 0103H, 0FFFFH, 010CH, 011H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS BEG_BLK, ??bb00_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 0BDH +$DGS BEG_BLK, ??bb01_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 0C1H +$DGS END_BLK, ??eb01_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS BEG_BLK, ??bb02_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 0C7H +$DGS END_BLK, ??eb02_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS END_BLK, ??eb00_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb03_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 0C9H +$DGS BEG_BLK, ??bb04_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 0CDH +$DGS END_BLK, ??eb04_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS BEG_BLK, ??bb05_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 00H +$DGS END_BLK, ??eb05_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS END_BLK, ??eb03_getmean3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS END_FUN, ??ef_getmean3, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 016H +$DGS GLV_SYM, _int_adc, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0EEH, 00H, 00H +$DGS BEG_FUN, ??bf_int_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0102H, 016H, 0E0H +$DGS STA_SYM, _hist_tune, ?L0055, U, 0CH, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _hist_snd_vol, ?L0056, U, 0CH, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _hist_bt_temp, ?L0057, U, 0CH, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 03H, 03H, 00H, 00H, 00H, 00H +$DGS STA_SYM, _index, ?L0058, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 0E4H +$DGS END_BLK, ??eb00_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02EH +$DGS BEG_BLK, ??bb01_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 034H, 00H, 0E8H +$DGS END_BLK, ??eb01_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 037H +$DGS BEG_BLK, ??bb02_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 039H, 00H, 00H +$DGS END_BLK, ??eb02_int_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03EH +$DGS END_FUN, ??ef_int_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03FH +$DGS GLV_SYM, _get_adc, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0FAH, 00H, 00H +$DGS BEG_FUN, ??bf_get_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0148H, 02H, 0F4H +$DGS REG_PAR, _ch, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS REG_VAR, _temp, 07H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_get_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 00H +$DGS END_BLK, ??eb00_get_adc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS END_FUN, ??ef_get_adc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01DH +$DGS GLV_SYM, _adc_updated, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _adc_raw_vol, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _adc_raw_dep, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _abs, U, U, 04H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _raw_adc_temperature, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _PM_bt_temp_update, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + + EXTRN _abs + EXTRN _iic_mcu_write_a_byte + EXTRN _system_status + EXTRN _vreg_ctr + EXTRN _vreg_twl + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _@RTARG0 + EXTRN _raw_adc_temperature + EXTRN _PM_bt_temp_update + EXTRN _renge_task_immed_add + PUBLIC _adc_updated + PUBLIC _adc_raw_vol + PUBLIC _adc_raw_dep + PUBLIC _tsk_adc + PUBLIC _int_adc + PUBLIC _get_adc + +@@BITS BSEG +_adc_updated DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 +_slider_to_codec: DB 07FH ; 127 + DB 07EH ; 126 + DB 07DH ; 125 + DB 07CH ; 124 + DB 07BH ; 123 + DB 07AH ; 122 + DB 079H ; 121 + DB 078H ; 120 + DB 077H ; 119 + DB 076H ; 118 + DB 075H ; 117 + DB 074H ; 116 + DB 073H ; 115 + DB 072H ; 114 + DB 071H ; 113 + DB 070H ; 112 + DB 06FH ; 111 + DB 06EH ; 110 + DB 06DH ; 109 + DB 06DH ; 109 + DB 06CH ; 108 + DB 06BH ; 107 + DB 06AH ; 106 + DB 069H ; 105 + DB 068H ; 104 + DB 067H ; 103 + DB 066H ; 102 + DB 065H ; 101 + DB 064H ; 100 + DB 063H ; 99 + DB 062H ; 98 + DB 061H ; 97 + DB 060H ; 96 + DB 05FH ; 95 + DB 05EH ; 94 + DB 05DH ; 93 + DB 05CH ; 92 + DB 05BH ; 91 + DB 05AH ; 90 + DB 059H ; 89 + DB 058H ; 88 + DB 057H ; 87 + DB 056H ; 86 + DB 055H ; 85 + DB 054H ; 84 + DB 053H ; 83 + DB 052H ; 82 + DB 051H ; 81 + DB 051H ; 81 + DB 050H ; 80 + DB 04FH ; 79 + DB 04EH ; 78 + DB 04DH ; 77 + DB 04CH ; 76 + DB 04BH ; 75 + DB 04AH ; 74 + DB 049H ; 73 + DB 048H ; 72 + DB 047H ; 71 + DB 046H ; 70 + DB 045H ; 69 + DB 044H ; 68 + DB 043H ; 67 + DB 042H ; 66 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB 020H ; 32 + +@@INIT DSEG BASEP +?L0003: DS (1) +?L0009: DS (1) + +@@DATA DSEG BASEP +_adc_raw_vol: DS (1) +_adc_raw_dep: DS (1) +?L0004: DS (1) +?L0005: DS (1) +?L0006: DS (1) +?L0007: DS (1) +?L0008: DS (1) +?L0010: DS (1) +?L0011: DS (1) +?L0055: DS (3) +?L0056: DS (3) +?L0057: DS (3) +?L0058: DS (1) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_S0076: + mov x,!_adc_raw_vol ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + sarw ax,2 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0076: + +ROM_CODE CSEG BASE +bs_F0075: + mov x,a ;[INF] 1, 1 + subc a,a ;[INF] 2, 1 + call !_abs ;[INF] 3, 3 + movw ax,bc ;[INF] 1, 1 + cmpw ax,#02H ; 2 ;[INF] 3, 1 + or1 CY,a.7 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0075: + +ROM_CODE CSEG BASE +bs_F0074: + mov a,_slider_to_codec[bc] ;[INF] 3, 1 + shrw ax,8 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#013H ; 19 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#0A4H ; 164 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0074: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0074 +; CODE SIZE= 17 bytes +; +; $SUB bs_F0075 +; CODE SIZE= 13 bytes +; +; $SUB bs_S0076 +; CODE SIZE= 7 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : 藤田＠開技 +; line 3 : nintendo +; line 4 : '09 Apr +; line 5 : ======================================================== */ +; line 6 : #include "incs.h" +; line 7 : #include "adc.h" +; line 8 : #include "pm.h" +; line 9 : +; line 10 : #include "led.h" +; line 11 : +; line 12 : bit adc_updated; +; line 13 : +; line 14 : u8 adc_raw_vol; +; line 15 : u8 adc_raw_dep; +; line 16 : +; line 17 : #define INTERVAL_TSK_ADC 3 +; line 18 : /* ======================================================== +; line 19 : ADC設定と、開始 +; line 20 : +; line 21 : 以下のピンは主にここで操作・監視されます。 +; line 22 : ・BT_TEMP,_P +; line 23 : ・ADIN1 +; line 24 : ・VOL +; line 25 : +; line 26 : 関係ありそうですが別のところで管理しています +; line 27 : ・PM_BT_DET,_P PM_init +; line 28 : +; line 29 : ・8tics毎に呼ばれ、３チャンネル分取り込むとADCを停止します。 +; line 30 : 　タスク起動時、レジスタには前回の取り込み値が入っています。 +; line 31 : ======================================================== */ +; line 32 : /* +; line 33 : // max -4db +; line 34 : static const u8 slider_to_codec[64] = +; line 35 : { +; line 36 : 127, 125, 124, 123, 121, 120, 119, 117, +; line 37 : 116, 115, 113, 112, 111, 109, 108, 107, +; line 38 : 105, 104, 103, 101, 100, 99, 98, 96, +; line 39 : 95, 94, 92, 91, 90, 88, 87, 86, +; line 40 : 84, 83, 82, 80, 79, 78, 76, 75, +; line 41 : 74, 72, 71, 70, 69, 67, 66, 65, +; line 42 : 63, 62, 61, 59, 58, 57, 55, 54, +; line 43 : 53, 51, 50, 49, 47, 46, 45, 44 +; line 44 : }; +; line 45 : */ +; line 46 : +; line 47 : // max -10db +; line 48 : static const u8 slider_to_codec[64] = +; line 49 : { +; line 50 : 127, 126, 125, 124, 123, 122, 121, 120, +; line 51 : 119, 118, 117, 116, 115, 114, 113, 112, +; line 52 : 111, 110, 109, 109, 108, 107, 106, 105, +; line 53 : 104, 103, 102, 101, 100, 99, 98, 97, +; line 54 : 96, 95, 94, 93, 92, 91, 90, 89, +; line 55 : 88, 87, 86, 85, 84, 83, 82, 81, +; line 56 : 81, 80, 79, 78, 77, 76, 75, 74, +; line 57 : 73, 72, 71, 70, 69, 68, 67, 66 +; line 58 : }; +; line 59 : +; line 60 : void tsk_adc( ) +; line 61 : { + +ROM_CODE CSEG BASE +_tsk_adc: +$DGL 1,81 + push hl ;[INF] 1, 1 +??bf_tsk_adc: +; line 62 : static u8 task_interval = 0; +; line 63 : static u8 old_tune; +; line 64 : static u8 sndvol_codec; +; line 65 : static u8 bt_temp_old; +; line 66 : +; line 67 : if( task_interval-- != 0 ) +$DGL 0,7 + mov a,!?L0003 ; task_interval ;[INF] 3, 1 + dec !?L0003 ; task_interval ;[INF] 3, 2 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 + br !?L0002 ;[INF] 3, 3 +; line 68 : { +??bb00_tsk_adc: +; line 69 : return; +??eb00_tsk_adc: +; line 70 : } +; line 71 : else +; line 72 : { +??bb01_tsk_adc: +; line 73 : task_interval = (u8)( INTERVAL_TSK_ADC / SYS_INTERVAL_TI +; CK ); +$DGL 0,13 + oneb !?L0003 ; task_interval ;[INF] 3, 1 +??eb01_tsk_adc: +; line 74 : } +; line 75 : +; line 76 : +; line 77 : if( adc_updated ) +$DGL 0,17 + bt _adc_updated,$$+7 ;[INF] 4, 5 + br !?L0016 ;[INF] 3, 3 +; line 78 : { +??bb02_tsk_adc: +; line 79 : if( system_status.pwr_state == ON ) +$DGL 0,19 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + skz ;[INF] 2, 1 + br !?L0016 ;[INF] 3, 3 +; line 80 : { +??bb03_tsk_adc: +; line 81 : // Tune /////////////////////////////////////// +; line 82 : { +??bb04_tsk_adc: +; line 83 : // 似非ヒステリシス V2 +; line 84 : // ガリオームには適さない +; line 85 : #define KIKAN 32 +; line 86 : static u8 old_value; +; line 87 : static s8 diffs; +; line 88 : u8 temp; +; line 89 : +; line 90 : if( abs( adc_raw_dep - old_value ) >= 2 ) +$DGL 0,30 + mov a,!_adc_raw_dep ;[INF] 3, 1 + sub a,!?L0007 ; old_value ;[INF] 3, 1 + call !bs_F0075 ;[INF] 3, 3 + bc $?L0018 ;[INF] 2, 4 +; line 91 : { +??bb05_tsk_adc: +; line 92 : // 大きく離れた +; line 93 : vreg_ctr[ VREG_C_TUNE ] = adc_raw_dep; +$DGL 0,33 + mov a,!_adc_raw_dep ;[INF] 3, 1 + mov !_vreg_ctr+8,a ;[INF] 3, 1 +; line 94 : old_value = adc_raw_dep; +$DGL 0,34 + mov a,!_adc_raw_dep ;[INF] 3, 1 + mov !?L0007,a ; old_value ;[INF] 3, 1 +; line 95 : #if 0 +; line 96 : 割り込み入れない; +; line 97 : 割り込みを入れるようであれば、ちゃんと変化チ +; ェックする; +; line 98 : +; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_VR_TUNE_CHANGE +; ); +; line 100 : #endif +; line 101 : diffs = 0; +$DGL 0,41 + clrb !?L0008 ; diffs ;[INF] 3, 1 +??eb05_tsk_adc: +; line 102 : } +$DGL 0,42 + br $?L0024 ;[INF] 2, 3 +?L0018: +; line 103 : else +; line 104 : { +??bb06_tsk_adc: +; line 105 : // 近所の値でも、ある期間でいっぱい偏っていた +; らそっちに寄せる +; line 106 : static u8 kikan_count = KIKAN; +; line 107 : if( old_value < adc_raw_dep ) +$DGL 0,47 + mov a,!?L0007 ; old_value ;[INF] 3, 1 + cmp a,!_adc_raw_dep ;[INF] 3, 1 + bnc $?L0020 ;[INF] 2, 4 +; line 108 : { +??bb07_tsk_adc: +; line 109 : diffs += 1; +$DGL 0,49 + inc !?L0008 ; diffs ;[INF] 3, 2 +??eb07_tsk_adc: +; line 110 : } +$DGL 0,50 + br $?L0022 ;[INF] 2, 3 +?L0020: +; line 111 : else if( old_value > adc_raw_dep ) +$DGL 0,51 + mov a,!_adc_raw_dep ;[INF] 3, 1 + cmp a,!?L0007 ; old_value ;[INF] 3, 1 + sknc ;[INF] 2, 1 +; line 112 : { +??bb08_tsk_adc: +; line 113 : diffs -= 1; +$DGL 0,53 + dec !?L0008 ; diffs ;[INF] 3, 2 +??eb08_tsk_adc: +; line 114 : } +?L0022: +; line 115 : +; line 116 : if( --kikan_count == 0 ) +$DGL 0,56 + dec !?L0009 ; kikan_count ;[INF] 3, 2 + cmp0 !?L0009 ; kikan_count ;[INF] 3, 1 + bnz $?L0024 ;[INF] 2, 4 +; line 117 : { +??bb09_tsk_adc: +; line 118 : if( diffs >= KIKAN && ( diffs < 64 )) +$DGL 0,58 + mov a,!?L0008 ; diffs ;[INF] 3, 1 + xor a,#080H ; 128 ;[INF] 2, 1 + cmp a,#0A0H ; 160 ;[INF] 2, 1 + bc $?L0026 ;[INF] 2, 4 + mov a,!?L0008 ; diffs ;[INF] 3, 1 + xor a,#080H ; 128 ;[INF] 2, 1 + cmp a,#0C0H ; 192 ;[INF] 2, 1 + bnc $?L0026 ;[INF] 2, 4 +; line 119 : { +??bb0A_tsk_adc: +; line 120 : old_value += 1; +$DGL 0,60 + inc !?L0007 ; old_value ;[INF] 3, 2 +??eb0A_tsk_adc: +; line 121 : } +$DGL 0,61 + br $?L0028 ;[INF] 2, 3 +?L0026: +; line 122 : else if( ( diffs <= ( 256 - KIKAN )) && +; ( diffs > ( 128 + 64 ) )) // あらー？ +$DGL 0,62 + mov a,!?L0008 ; diffs ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + cmpw ax,#0E1H ; 225 ;[INF] 3, 1 + or1 CY,a.7 ;[INF] 2, 1 + bnc $?L0028 ;[INF] 2, 4 + mov a,!?L0008 ; diffs ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + cmpw ax,#0C1H ; 193 ;[INF] 3, 1 + or1 CY,a.7 ;[INF] 2, 1 + skc ;[INF] 2, 1 +; line 123 : { +??bb0B_tsk_adc: +; line 124 : old_value -= 1; +$DGL 0,64 + dec !?L0007 ; old_value ;[INF] 3, 2 +??eb0B_tsk_adc: +; line 125 : } +?L0028: +; line 126 : vreg_ctr[ VREG_C_TUNE ] = old_value; +$DGL 0,66 + mov a,!?L0007 ; old_value ;[INF] 3, 1 + mov !_vreg_ctr+8,a ;[INF] 3, 1 +; line 127 : kikan_count = KIKAN; +$DGL 0,67 + mov !?L0009,#020H ; kikan_count,32 ;[INF] 4, 1 +; line 128 : diffs = 0; +$DGL 0,68 + clrb !?L0008 ; diffs ;[INF] 3, 1 +??eb09_tsk_adc: +; line 129 : } +?L0024: +??eb06_tsk_adc: +; line 130 : } +??eb04_tsk_adc: +; line 131 : } +; line 132 : vreg_ctr[ VREG_C_DBG1 ] = vreg_ctr[ VREG_C_TUNE ]; +$DGL 0,72 + mov a,!_vreg_ctr+8 ;[INF] 3, 1 + mov !_vreg_ctr+5,a ;[INF] 3, 1 +; line 133 : vreg_ctr[ VREG_C_DBG2 ] = adc_raw_dep; // dbg +$DGL 0,73 + mov a,!_adc_raw_dep ;[INF] 3, 1 + mov !_vreg_ctr+6,a ;[INF] 3, 1 +; line 134 : +; line 135 : // Volume ///////////////////////////////////// +; line 136 : { +??bb0C_tsk_adc: +; line 137 : // 似非ヒステリシスを付けて64段 +; line 138 : u8 temp; +; line 139 : static u8 vol_old; +; line 140 : static u8 force_update_vol; +; line 141 : +; line 142 : if( abs( adc_raw_vol - vol_old ) >= 2 ) // +; 生値でこれくらいずれたら更新 +$DGL 0,82 + mov a,!_adc_raw_vol ;[INF] 3, 1 + sub a,!?L0010 ; vol_old ;[INF] 3, 1 + call !bs_F0075 ;[INF] 3, 3 + bc $?L0030 ;[INF] 2, 4 +; line 143 : { +??bb0D_tsk_adc: +; line 144 : // if( vreg_ctr[ VREG_C_SND_VOL ] != ( adc_ra +; w_vol / 4 ) ) +; line 145 : { +??bb0E_tsk_adc: +; line 146 : vol_old = adc_raw_vol; +$DGL 0,86 + mov a,!_adc_raw_vol ;[INF] 3, 1 + mov !?L0010,a ; vol_old ;[INF] 3, 1 +; line 147 : // レジスタ更新 +; line 148 : vreg_ctr[ VREG_C_SND_VOL ] = ( adc_raw_v +; ol / 4 ); +$DGL 0,88 + call !bs_S0076 ;[INF] 3, 3 + mov a,x ;[INF] 1, 1 + mov !_vreg_ctr+9,a ;[INF] 3, 1 +; line 149 : vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_r +; aw_vol / ( 256 / 32 ); // ←adc値でよい +$DGL 0,89 + mov x,!_adc_raw_vol ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + sarw ax,3 ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov !_vreg_twl+6,a ;[INF] 3, 1 +; line 150 : +; line 151 : // codecに伝える +; line 152 : iic_mcu_write_a_byte( IIC_SLA_CODEC, COD +; EC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); +$DGL 0,92 + call !bs_S0076 ;[INF] 3, 3 + movw bc,ax ;[INF] 1, 1 + call !bs_F0074 ;[INF] 3, 3 +; line 153 : #ifndef _MODEL_CTR_ +; line 154 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0, sl +; ider_to_codec[ ( 255 - adc_raw_vol ) / 4 ] ); // todo +; line 155 : #endif +; line 156 : // set_irq( VREG_C_IRQ0, REG_BIT_VR_SNDVO +; L_CHANGE ); // 割り込み廃止 +; line 157 : force_update_vol = 100; +$DGL 0,97 + mov !?L0011,#064H ; force_update_vol,100 ;[INF] 4, 1 +??eb0E_tsk_adc: +; line 158 : } +??eb0D_tsk_adc: +; line 159 : } +?L0030: +; line 160 : +; line 161 : { +??bb0F_tsk_adc: +; line 162 : // ポーリング +; line 163 : if( --force_update_vol == 0 ) +$DGL 0,103 + dec !?L0011 ; force_update_vol ;[INF] 3, 2 + cmp0 !?L0011 ; force_update_vol ;[INF] 3, 1 + bnz $?L0032 ;[INF] 2, 4 +; line 164 : { +??bb10_tsk_adc: +; line 165 : vol_old = adc_raw_vol; +$DGL 0,105 + mov a,!_adc_raw_vol ;[INF] 3, 1 + mov !?L0010,a ; vol_old ;[INF] 3, 1 +; line 166 : // レジスタ更新 +; line 167 : // vreg_ctr[ VREG_C_SND_VOL ] = temp; +; line 168 : // vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc +; _raw_vol / ( 256 / 32 ); // ←adc値でよい +; line 169 : // codecに伝える +; line 170 : iic_mcu_write_a_byte( IIC_SLA_CODEC, COD +; EC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] ); +$DGL 0,110 + call !bs_S0076 ;[INF] 3, 3 + movw bc,ax ;[INF] 1, 1 + call !bs_F0074 ;[INF] 3, 3 +; line 171 : force_update_vol = 100; +$DGL 0,111 + mov !?L0011,#064H ; force_update_vol,100 ;[INF] 4, 1 +??eb10_tsk_adc: +; line 172 : } +?L0032: +??eb0F_tsk_adc: +; line 173 : } +??eb0C_tsk_adc: +; line 174 : } +; line 175 : +; line 176 : +; line 177 : // TUNE_LED /////////////////////////////////// +; line 178 : // ここで？仕様？ +; line 179 : { +??bb11_tsk_adc: +; line 180 : switch ( vreg_ctr[VREG_C_LED_TUNE] ) +$DGL 0,120 + mov x,!_vreg_ctr+44 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0037 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0035 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0036 ;[INF] 2, 4 + br $?L0037 ;[INF] 2, 3 +; line 181 : { +??bb12_tsk_adc: +; line 182 : case LED_TUNE_ILM_ON: +?L0035: +; line 183 : LED_duty_TUNE = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,123 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw TDR01,ax ;[INF] 2, 1 +; line 184 : break; +$DGL 0,124 + br $?L0034 ;[INF] 2, 3 +; line 185 : +; line 186 : case LED_TUNE_ILM_SVR: +?L0036: +; line 187 : LED_duty_TUNE = vreg_ctr[VREG_C_TUNE] / 16; +$DGL 0,127 + mov x,!_vreg_ctr+8 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + sarw ax,4 ;[INF] 2, 1 + movw TDR01,ax ;[INF] 2, 1 +; line 188 : break; +$DGL 0,128 + br $?L0034 ;[INF] 2, 3 +; line 189 : +; line 190 : case LED_TUNE_ILM_OFF: +?L0037: +; line 191 : default: +; line 192 : LED_duty_TUNE = 0; +$DGL 0,132 + clrw ax ;[INF] 1, 1 + movw TDR01,ax ;[INF] 2, 1 +; line 193 : break; +??eb12_tsk_adc: +; line 194 : } +?L0034: +??eb11_tsk_adc: +; line 195 : } +; line 196 : adc_updated = 0; +$DGL 0,136 + clr1 _adc_updated ;[INF] 3, 2 +??eb03_tsk_adc: +; line 197 : } +?L0016: +??eb02_tsk_adc: +; line 198 : } +; line 199 : +; line 200 : +; line 201 : ADCEN = 1; +$DGL 0,141 + set1 !PER0.5 ;[INF] 4, 2 +; line 202 : ADM = 0b00011011; // セレクトモード、章圧、fCLK/6 ///こ +; こから ↓ +$DGL 0,142 + mov ADM,#01BH ; 27 ;[INF] 3, 1 +; line 203 : +; line 204 : ADPC = 0x06; // ADCポートのセレクト +$DGL 0,144 + mov !ADPC,#06H ; 6 ;[INF] 4, 1 +; line 205 : ADS = ADC_SEL_TUNE; +$DGL 0,145 + mov ADS,#06H ; 6 ;[INF] 3, 1 +; line 206 : NOP(); +$DGL 0,146 + nop ;[INF] 1, 1 +; line 207 : NOP(); +$DGL 0,147 + nop ;[INF] 1, 1 +; line 208 : NOP(); +$DGL 0,148 + nop ;[INF] 1, 1 +; line 209 : NOP(); +$DGL 0,149 + nop ;[INF] 1, 1 +; line 210 : NOP(); +$DGL 0,150 + nop ;[INF] 1, 1 +; line 211 : NOP(); +$DGL 0,151 + nop ;[INF] 1, 1 +; line 212 : NOP(); +$DGL 0,152 + nop ;[INF] 1, 1 +; line 213 : NOP(); +$DGL 0,153 + nop ;[INF] 1, 1 +; line 214 : ADCS = 1; // AD開始。 /// +; ここまで　↑　までに1us=8clk以上開ける +$DGL 0,154 + set1 ADM.7 ;[INF] 3, 2 +; line 215 : +; line 216 : ADIF = 0; +$DGL 0,156 + clr1 IF1H.0 ;[INF] 3, 2 +; line 217 : ADMK = 0; +$DGL 0,157 + clr1 MK1H.0 ;[INF] 3, 2 +; line 218 : +; line 219 : } +?L0002: +$DGL 0,159 +??ef_tsk_adc: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_adc: +; line 220 : +; line 221 : +; line 222 : /* ======================================================== +; line 223 : 　過去３つのminでもMAXでもない値を返す +; line 224 : 　突発的なノイズを除く。 +; line 225 : 　根本対策ではないが、これはこれで使い道がある。 +; line 226 : ======================================================== */ +; line 227 : static u8 getmean3( u8 * hist ) +; line 228 : { +_getmean3: +$DGL 1,181 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_getmean3: +; line 229 : if( *hist > *( hist + 1 ) ) +$DGL 0,2 + mov a,[hl] ;[INF] 1, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+1] ;[INF] 2, 1 + cmp a,c ;[INF] 2, 1 + bnc $?L0043 ;[INF] 2, 4 +; line 230 : { +??bb00_getmean3: +; line 231 : if( *hist > *( hist + 2 ) ) +$DGL 0,4 + mov a,[hl] ;[INF] 1, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+2] ;[INF] 2, 1 + cmp a,c ;[INF] 2, 1 + bnc $?L0045 ;[INF] 2, 4 +; line 232 : { +??bb01_getmean3: +; line 233 : return( ( *( hist + 1 ) > *( hist + 2 ) ) ? *( hist +; + 1 ) : *( hist + 2 ) ); +$DGL 0,6 + mov a,[hl+1] ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+2] ;[INF] 2, 1 + cmp a,c ;[INF] 2, 1 + bnc $?L0047 ;[INF] 2, 4 + mov a,[hl+1] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + br $?L0048 ;[INF] 2, 3 +?L0047: + mov a,[hl+2] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 +?L0048: + movw bc,ax ;[INF] 1, 1 + br $?L0050 ;[INF] 2, 3 +??eb01_getmean3: +; line 234 : } +?L0045: +; line 235 : else +; line 236 : { +??bb02_getmean3: +; line 237 : return( *hist ); +$DGL 0,10 + mov a,[hl] ;[INF] 1, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0050 ;[INF] 2, 3 +??eb02_getmean3: +; line 238 : } +; line 239 : }else{ +??eb00_getmean3: +?L0043: +??bb03_getmean3: +; line 240 : if( *hist > *( hist + 2 ) ) +$DGL 0,13 + mov a,[hl] ;[INF] 1, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+2] ;[INF] 2, 1 + cmp a,c ;[INF] 2, 1 + bnc $?L0049 ;[INF] 2, 4 +; line 241 : { +??bb04_getmean3: +; line 242 : return( *hist ); +$DGL 0,15 + mov a,[hl] ;[INF] 1, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0050 ;[INF] 2, 3 +??eb04_getmean3: +; line 243 : } +?L0049: +; line 244 : else +; line 245 : { +??bb05_getmean3: +; line 246 : return( ( *( hist + 1 ) < *( hist + 2 ) ) ? *( hist +; + 1 ) : *( hist + 2 ) ); +$DGL 0,19 + mov a,[hl+1] ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+2] ;[INF] 2, 1 + cmp c,a ;[INF] 2, 1 + bnc $?L0051 ;[INF] 2, 4 + mov a,[hl+1] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + br $?L0052 ;[INF] 2, 3 +?L0051: + mov a,[hl+2] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 +?L0052: + movw bc,ax ;[INF] 1, 1 +??eb05_getmean3: +; line 247 : } +?L0050: +??eb03_getmean3: +; line 248 : } +; line 249 : } +$DGL 0,22 +??ef_getmean3: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_getmean3: +; line 250 : +; line 251 : +; line 252 : +; line 253 : /* ======================================================== +; line 254 : 　自前で次のチャンネル +; line 255 : 　　一通り終わったら止める +; line 256 : ======================================================== */ +; line 257 : __interrupt void int_adc( ) +; line 258 : { + +@@BASE CSEG BASE +_int_adc: +$DGL 1,213 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_int_adc: +; line 259 : static u8 hist_tune[3]; +; line 260 : static u8 hist_snd_vol[3]; +; line 261 : static u8 hist_bt_temp[3]; +; line 262 : static u8 index; +; line 263 : +; line 264 : EI( ); +$DGL 0,7 + ei ;[INF] 3, 4 +; line 265 : switch ( ADS ) +$DGL 0,8 + mov a,ADS ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + onew bc ;[INF] 1, 1 + subw ax,#06H ; 6 ;[INF] 3, 1 + bz $?L0060 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0061 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0062 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + br $?L0059 ;[INF] 2, 3 +; line 266 : { +??bb00_int_adc: +; line 267 : /* +; line 268 : case ( ADC_SEL_AMB_BRIT ): +; line 269 : vreg_ctr[ VREG_C_AMBIENT_BRIGHTNESS ] = ADCRH; +; line 270 : break; +; line 271 : */ +; line 272 : +; line 273 : case ( ADC_SEL_TUNE ): +?L0060: +; line 274 : hist_tune[index] = ADCRH; +$DGL 0,17 + mov x,!?L0058 ; index ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,#loww (?L0055) ; hist_tune ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,ADCRH ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 275 : #ifdef _MODEL_WM0_ +; line 276 : adc_raw_dep = 255 - getmean3( hist_tune ); +; line 277 : #else +; line 278 : adc_raw_dep = getmean3( hist_tune ); +$DGL 0,21 + movw ax,#loww (?L0055) ; hist_tune ;[INF] 3, 1 + call !_getmean3 ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_adc_raw_dep,a ;[INF] 3, 1 +; line 279 : #endif +; line 280 : break; +$DGL 0,23 + br $?L0059 ;[INF] 2, 3 +; line 281 : +; line 282 : case ( ADC_SEL_VOL ): +?L0061: +; line 283 : hist_snd_vol[index] = ADCRH; +$DGL 0,26 + mov x,!?L0058 ; index ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,#loww (?L0056) ; hist_snd_vol ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,ADCRH ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 284 : #ifdef _MODEL_CTR_JIKKI_ +; line 285 : adc_raw_vol = ( 255 - getmean3( hist_snd_vol )); +; line 286 : #else +; line 287 : adc_raw_vol = getmean3( hist_snd_vol ); +$DGL 0,30 + movw ax,#loww (?L0056) ; hist_snd_vol ;[INF] 3, 1 + call !_getmean3 ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_adc_raw_vol,a ;[INF] 3, 1 +; line 288 : #endif +; line 289 : // TWL用レジスタ(32段)の更新。アトミックな処理として扱わ +; ないと不都合が。 +; line 290 : /// 割り込みはHorizonを通してコマンドを発行されるのを待て +; ばよい +; line 291 : break; +$DGL 0,34 + br $?L0059 ;[INF] 2, 3 +; line 292 : +; line 293 : case ( ADC_SEL_BATT_TEMP ): +?L0062: +; line 294 : hist_bt_temp[index] = ADCRH; +$DGL 0,37 + mov x,!?L0058 ; index ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,#loww (?L0057) ; hist_bt_temp ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,ADCRH ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 295 : raw_adc_temperature = getmean3( hist_bt_temp ); +$DGL 0,38 + movw ax,#loww (?L0057) ; hist_bt_temp ;[INF] 3, 1 + call !_getmean3 ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_raw_adc_temperature,a ;[INF] 3, 1 +; line 296 : renge_task_immed_add( PM_bt_temp_update ); +$DGL 0,39 + movw ax,#loww (_PM_bt_temp_update) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 297 : break; +; line 298 : +; line 299 : case ( ADC_SEL_BATT_DET ): +; line 300 : // vreg_ctr[ VREG_C_DBG_BATT_DET ] = ADCRH; +; line 301 : // todo +; line 302 : break; +??eb00_int_adc: +; line 303 : } +?L0059: +; line 304 : +; line 305 : +; line 306 : // もっとまともな書き方がありそうだ +; line 307 : // if( ADS == ADC_SEL_BATT_DET ){ +; line 308 : if( ADS != ADC_SEL_BATT_TEMP ) +$DGL 0,51 + cmp !ADS,#08H ; 8 ;[INF] 4, 1 + bz $?L0066 ;[INF] 2, 4 +; line 309 : { // 電池判別は電源投入の一回のみ +??bb01_int_adc: +; line 310 : ADS += 1; // 次のチャンネル +$DGL 0,53 + inc !ADS ;[INF] 3, 2 +; line 311 : BT_TEMP_P = 1; // 電池温度監視スタート +$DGL 0,54 + set1 P1.7 ;[INF] 3, 2 +??eb01_int_adc: +; line 312 : } +$DGL 0,55 + br $?L0067 ;[INF] 2, 3 +?L0066: +; line 313 : else +; line 314 : { +??bb02_int_adc: +; line 315 : ADCEN = 0; // 止めてしまう +$DGL 0,58 + clr1 !PER0.5 ;[INF] 4, 2 +; line 316 : BT_TEMP_P = 0; // 電池温度監視スタート +$DGL 0,59 + clr1 P1.7 ;[INF] 3, 2 +; line 317 : adc_updated = 1; +$DGL 0,60 + set1 _adc_updated ;[INF] 3, 2 +; line 318 : index = ( index == 2 ) ? 0 : ( index + 1 ); +$DGL 0,61 + cmp !?L0058,#02H ; index,2 ;[INF] 4, 1 + bnz $?L0068 ;[INF] 2, 4 + clrw ax ;[INF] 1, 1 + br $?L0069 ;[INF] 2, 3 +?L0068: + mov x,!?L0058 ; index ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + incw ax ;[INF] 1, 1 +?L0069: + mov a,x ;[INF] 1, 1 + mov !?L0058,a ; index ;[INF] 3, 1 +??eb02_int_adc: +; line 319 : } +?L0067: +; line 320 : } +$DGL 0,63 +??ef_int_adc: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_adc: +; line 321 : +; line 322 : +; line 323 : +; line 324 : /* ======================================================== +; line 325 : tsk_adcと競合することを考慮していません。 +; line 326 : ======================================================== */ +; line 327 : u8 get_adc( u8 ch ) +; line 328 : { + +ROM_CODE CSEG BASE +_get_adc: +$DGL 1,238 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_get_adc: +; line 329 : u8 temp; +; line 330 : +; line 331 : ADMK = 1; +$DGL 0,4 + set1 MK1H.0 ;[INF] 3, 2 +; line 332 : ADIF = 0; +$DGL 0,5 + clr1 IF1H.0 ;[INF] 3, 2 +; line 333 : +; line 334 : ADCEN = 1; +$DGL 0,7 + set1 !PER0.5 ;[INF] 4, 2 +; line 335 : ADCS = 0; +$DGL 0,8 + clr1 ADM.7 ;[INF] 3, 2 +; line 336 : ADM = 0b00100011; // セレクトモード、昇圧、fCLK/6 +; ///ここから↓ +$DGL 0,9 + mov ADM,#023H ; 35 ;[INF] 3, 1 +; line 337 : +; line 338 : ADPC = 0x06; // ADCポートのセレクト +$DGL 0,11 + mov !ADPC,#06H ; 6 ;[INF] 4, 1 +; line 339 : ADS = ch; +$DGL 0,12 + mov a,l ;[INF] 1, 1 + mov ADS,a ;[INF] 2, 1 +; line 340 : NOP(); +$DGL 0,13 + nop ;[INF] 1, 1 +; line 341 : NOP(); +$DGL 0,14 + nop ;[INF] 1, 1 +; line 342 : NOP(); +$DGL 0,15 + nop ;[INF] 1, 1 +; line 343 : NOP(); +$DGL 0,16 + nop ;[INF] 1, 1 +; line 344 : NOP(); +$DGL 0,17 + nop ;[INF] 1, 1 +; line 345 : NOP(); +$DGL 0,18 + nop ;[INF] 1, 1 +; line 346 : NOP(); +$DGL 0,19 + nop ;[INF] 1, 1 +; line 347 : NOP(); +$DGL 0,20 + nop ;[INF] 1, 1 +; line 348 : ADCS = 1; // AD開始。 +; /// ここまで↑　に、1us以上開ける +$DGL 0,21 + set1 ADM.7 ;[INF] 3, 2 +; line 349 : +; line 350 : ADMK = 0; +$DGL 0,23 + clr1 MK1H.0 ;[INF] 3, 2 +; line 351 : while( ADIF == 0 ){;} +$DGL 0,24 +?L0072: + bt IF1H.0,$?L0073 ;[INF] 4, 5 +??bb00_get_adc: +??eb00_get_adc: + br $?L0072 ;[INF] 2, 3 +?L0073: +; line 352 : temp = ADCRH; +$DGL 0,25 + mov a,ADCRH ;[INF] 2, 1 +; line 353 : ADCEN = 0; +$DGL 0,26 + clr1 !PER0.5 ;[INF] 4, 2 +; line 354 : +; line 355 : return ( temp ); +$DGL 0,28 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 +; line 356 : } +$DGL 0,29 +??ef_get_adc: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_get_adc: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c +; +; $FUNC tsk_adc(61) +; void=(void) +; CODE SIZE= 312 bytes, CLOCK_SIZE= 302 clocks, STACK_SIZE= 14 bytes +; +; $CALL abs(90) +; bc=(int:ax) +; +; $CALL abs(142) +; bc=(int:ax) +; +; $CALL iic_mcu_write_a_byte(152) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL iic_mcu_write_a_byte(170) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC getmean3(228) +; bc=(pointer hist:ax) +; CODE SIZE= 82 bytes, CLOCK_SIZE= 80 clocks, STACK_SIZE= 2 bytes +; +; $FUNC int_adc(258) +; void=(void) +; CODE SIZE= 181 bytes, CLOCK_SIZE= 146 clocks, STACK_SIZE= 26 bytes +; +; $CALL getmean3(278) +; bc=(pointer:ax) +; +; $CALL getmean3(287) +; bc=(pointer:ax) +; +; $CALL getmean3(295) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(296) +; bc=(pointer:ax) +; +; $FUNC get_adc(328) +; bc=(unsigned char ch:x) +; CODE SIZE= 56 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 2 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/i2c_ctr.asm b/branches/0.10(X3)/inter_asm/i2c_ctr.asm new file mode 100644 index 0000000..24fbfd2 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/i2c_ctr.asm @@ -0,0 +1,920 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c +; In-file : i2c_ctr.c +; Asm-file : inter_asm\i2c_ctr.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 07CH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, i2c_ctr.c +$DGS MOD_NAM, i2c_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _int_iic_ctr, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 070H, 00H, 00H +$DGS BEG_FUN, ??bf_int_iic_ctr, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 041H, 016H, 01EH +$DGS STA_SYM, _state, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _reg_adrs, ?L0004, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _reg_adrs_internal, ?L0005, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _tx_buf, ?L0006, U, 0CH, 03H, 00H, 00H +$DGS REG_VAR, _rx_buf, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 020H +$DGS BEG_BLK, ??bb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 022H +$DGS BEG_BLK, ??bb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 026H +$DGS END_BLK, ??eb02_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS BEG_BLK, ??bb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 028H +$DGS BEG_BLK, ??bb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 02CH +$DGS END_BLK, ??eb04_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS BEG_BLK, ??bb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01DH, 00H, 036H +$DGS END_BLK, ??eb05_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS END_BLK, ??eb03_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01EH +$DGS END_BLK, ??eb01_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS END_BLK, ??eb00_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS BEG_BLK, ??bb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 03AH +$DGS END_BLK, ??eb06_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS BEG_BLK, ??bb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 03CH +$DGS BEG_BLK, ??bb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 037H, 00H, 042H +$DGS END_BLK, ??eb08_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03AH +$DGS END_BLK, ??eb07_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03BH +$DGS BEG_BLK, ??bb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03EH, 00H, 044H +$DGS BEG_BLK, ??bb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04CH, 00H, 048H +$DGS END_BLK, ??eb0A_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04EH +$DGS BEG_BLK, ??bb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 050H, 00H, 04CH +$DGS END_BLK, ??eb0B_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 052H +$DGS BEG_BLK, ??bb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 059H, 00H, 04EH +$DGS BEG_BLK, ??bb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05CH, 00H, 052H +$DGS END_BLK, ??eb0D_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05FH +$DGS BEG_BLK, ??bb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 061H, 00H, 058H +$DGS END_BLK, ??eb0E_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 067H +$DGS END_BLK, ??eb0C_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 068H +$DGS BEG_BLK, ??bb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06AH, 00H, 05CH +$DGS END_BLK, ??eb0F_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06DH +$DGS BEG_BLK, ??bb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 071H, 00H, 060H +$DGS END_BLK, ??eb10_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 074H +$DGS BEG_BLK, ??bb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 076H, 00H, 064H +$DGS END_BLK, ??eb11_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07AH +$DGS BEG_BLK, ??bb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 068H +$DGS END_BLK, ??eb12_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS BEG_BLK, ??bb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 083H, 00H, 00H +$DGS END_BLK, ??eb13_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 085H +$DGS END_BLK, ??eb09_int_iic_ctr, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 087H +$DGS END_FUN, ??ef_int_iic_ctr, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 088H +$DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 076H, 00H, 00H +$DGS BEG_FUN, ??bf_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0CEH, 00H, 076H +$DGS END_FUN, ??ef_IIC_ctr_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02CH +$DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 07CH, 00H, 00H +$DGS BEG_FUN, ??bf_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0FFH, 00H, 07CH +$DGS END_FUN, ??ef_IIC_ctr_Stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _irq_readed, U, U, 034CH, 02H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _hosu_read_end, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _rtc_unlock, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _@RTARG0 + EXTRN _vreg_ctr + EXTRN _hosu_read_end + EXTRN _rtc_unlock + EXTRN _vreg_ctr_read + EXTRN _vreg_ctr_after_read + EXTRN _vreg_ctr_write + EXTBIT _irq_readed + PUBLIC _iic_burst_state + PUBLIC _int_iic_ctr + PUBLIC _IIC_ctr_Init + PUBLIC _IIC_ctr_Stop + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0003: DS (1) + DS (1) + +@@DATA DSEG BASEP +_iic_burst_state: DS (1) +?L0004: DS (1) +?L0005: DS (1) +?L0006: DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : /* ======================================================== +; line 2 : 対SoC 新規チャンネル I2C通信 +; line 3 : 藤田＠開技.nintendo +; line 4 : '09 Apr +; line 5 : ======================================================== */ +; line 6 : #include "incs.h" +; line 7 : #include "accero.h" +; line 8 : +; line 9 : #ifdef _MCU_BSR_ +; line 10 : // #ifdef _MODEL_TS0_ || _MODEL_WM0_ +; line 11 : +; line 12 : // ワーキングモデルはI2Cが逆 +; line 13 : // TEGは回路図でテレコ +; line 14 : #define ACKD ACKD1 +; line 15 : #define ACKE ACKE1 +; line 16 : #define COI COI1 +; line 17 : #define IICAEN IICA1EN +; line 18 : #define IICRSV IICRSV1 +; line 19 : #define IICA IICA1 +; line 20 : #define IICAIF IICAIF1 +; line 21 : #define IICAMK IICAMK1 +; line 22 : #define IICAPR0 IICAPR11 +; line 23 : #define IICAPR1 IICAPR01 +; line 24 : #define IICCTL0 IICCTL10 +; line 25 : #define IICE IICE1 +; line 26 : #define IICF IICF1 +; line 27 : #define IICS IICS1 +; line 28 : #define IICWH IICWH1 +; line 29 : #define IICWL IICWL1 +; line 30 : #define LREL LREL1 +; line 31 : #define SPD SPD1 +; line 32 : #define SPIE SPIE1 +; line 33 : #define STCEN STCEN1 +; line 34 : #define STD STD1 +; line 35 : #define SVA SVA1 +; line 36 : #define WREL WREL1 +; line 37 : #define WTIM WTIM1 +; line 38 : #define TRC TRC1 +; line 39 : #define SMC SMC1 +; line 40 : #define DFC DFC1 +; line 41 : +; line 42 : +; line 43 : #endif +; line 44 : +; line 45 : // ============================================== +; line 46 : extern bit irq_readed; // いずれかのIRQレジスタが +; 読まれた +; line 47 : +; line 48 : u8 iic_burst_state; +; line 49 : +; line 50 : +; line 51 : /* ======================================================== +; line 52 : ======================================================== */ +; line 53 : enum +; line 54 : { +; line 55 : IIC_IDLE = 0, +; line 56 : IIC_RCV_REG_ADRS, +; line 57 : IIC_TX_OR_RX, +; line 58 : IIC_TX, +; line 59 : IIC_RX +; line 60 : }; +; line 61 : +; line 62 : +; line 63 : // 1バイト送受の度に割り込みが発生するバージョン +; line 64 : __interrupt void int_iic_ctr( ) +; line 65 : { + +@@BASE CSEG BASE +_int_iic_ctr: +$DGL 1,21 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_int_iic_ctr: +; line 66 : static u8 state = IIC_IDLE; +; line 67 : static u8 reg_adrs; +; line 68 : static u8 reg_adrs_internal; +; line 69 : static u8 tx_buf; +; line 70 : u8 rx_buf; +; line 71 : +; line 72 : EI(); +$DGL 0,8 + ei ;[INF] 3, 4 +; line 73 : +; line 74 : // 読み出し終了 +; line 75 : if( !ACKD ) // 割り込み要因はNAK（データ送信 +; の最後） +$DGL 0,11 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].2 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bc $?L0007 ;[INF] 2, 4 +; line 76 : { +??bb00_int_iic_ctr: +; line 77 : state = IIC_IDLE; +$DGL 0,13 + clrb !?L0003 ; state ;[INF] 3, 1 +; line 78 : SPIE = 0; +$DGL 0,14 + clr1 !IICCTL01.4 ;[INF] 4, 2 +; line 79 : LREL = 1; +$DGL 0,15 + set1 !IICCTL01.6 ;[INF] 4, 2 +; line 80 : +; line 81 : // レジスタリードで、割り込みピンをネゲート +; line 82 : // まだ読まれてない割り込みがあれば、再度アサート +; line 83 : if( irq_readed ) +$DGL 0,19 + bf _irq_readed,$?L0011 ;[INF] 4, 5 +; line 84 : { +??bb01_int_iic_ctr: +; line 85 : IRQ0_neg; +$DGL 0,21 +??bb02_int_iic_ctr: + set1 PM7.6 ;[INF] 3, 2 +??eb02_int_iic_ctr: +; line 86 : irq_readed = 0; +$DGL 0,22 + clr1 _irq_readed ;[INF] 3, 2 +; line 87 : if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 ) +; line 88 : && ( vreg_ctr[VREG_C_IRQ1] == 0 ) +; line 89 : && ( vreg_ctr[VREG_C_IRQ2] == 0 ) +; line 90 : && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) ) +$DGL 0,26 + cmp0 !_vreg_ctr+16 ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 + cmp0 !_vreg_ctr+17 ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 + cmp0 !_vreg_ctr+18 ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 + cmp0 !_vreg_ctr+19 ;[INF] 3, 1 + bz $?L0011 ;[INF] 2, 4 +?L0013: +; line 91 : { +??bb03_int_iic_ctr: +; line 92 : while( !IRQ0 ){;} // 時間稼ぎ不要かも +$DGL 0,28 + bt P7.6,$?L0015 ;[INF] 4, 5 +??bb04_int_iic_ctr: +??eb04_int_iic_ctr: + br $?L0013 ;[INF] 2, 3 +?L0015: +; line 93 : IRQ0_ast; +$DGL 0,29 +??bb05_int_iic_ctr: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb05_int_iic_ctr: +??eb03_int_iic_ctr: +; line 94 : } +?L0011: +??eb01_int_iic_ctr: +; line 95 : } +; line 96 : +; line 97 : // 歩数計読み出し終了 +; line 98 : hosu_read_end( ); +$DGL 0,34 + call !_hosu_read_end ;[INF] 3, 3 +; line 99 : rtc_unlock( ); +$DGL 0,35 + call !_rtc_unlock ;[INF] 3, 3 +; line 100 : iic_burst_state = 0; +$DGL 0,36 + clrb !_iic_burst_state ;[INF] 3, 1 +; line 101 : return; +$DGL 0,37 + br !?L0023 ;[INF] 3, 3 +??eb00_int_iic_ctr: +; line 102 : } +?L0007: +; line 103 : +; line 104 : if( SPD ) // 割り込み要因はストップコンディ +; ション +$DGL 0,40 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].0 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0016 ;[INF] 2, 4 +; line 105 : // 通信の最後。↑の !ACKD に来た +; ときは割り込み来ない (SPIE = 0 のため ) +; line 106 : { +??bb06_int_iic_ctr: +; line 107 : state = IIC_IDLE; +$DGL 0,43 + clrb !?L0003 ; state ;[INF] 3, 1 +; line 108 : SPIE = 0; +$DGL 0,44 + clr1 !IICCTL01.4 ;[INF] 4, 2 +; line 109 : // I2C終了時に何かする物 // +; line 110 : rtc_unlock( ); +$DGL 0,46 + call !_rtc_unlock ;[INF] 3, 3 +; line 111 : return; +$DGL 0,47 + br !?L0023 ;[INF] 3, 3 +??eb06_int_iic_ctr: +; line 112 : } +?L0016: +; line 113 : +; line 114 : if( STD ) // 割り込み要因：スタートコンディ +; ション +$DGL 0,50 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].1 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0020 ;[INF] 2, 4 +; line 115 : { +??bb07_int_iic_ctr: +; line 116 : if( ( state == IIC_TX ) || ( state == IIC_RX ) +; line 117 : || ( state == IIC_RCV_REG_ADRS ) +$DGL 0,53 + cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + bz $?L0022 ;[INF] 2, 4 + cmp !?L0003,#04H ; state,4 ;[INF] 4, 1 + bz $?L0022 ;[INF] 2, 4 + cmp !?L0003,#01H ; state,1 ;[INF] 4, 1 + sknz ;[INF] 2, 1 +?L0022: +; line 118 : ) +; line 119 : { +??bb08_int_iic_ctr: +; line 120 : state = IIC_IDLE; +$DGL 0,56 + clrb !?L0003 ; state ;[INF] 3, 1 +??eb08_int_iic_ctr: +; line 121 : // no break // +; line 122 : } +?L0020: +??eb07_int_iic_ctr: +; line 123 : } +; line 124 : +; line 125 : switch ( state ) +$DGL 0,61 + mov x,!?L0003 ; state ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0024 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0025 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0026 ;[INF] 2, 4 + br $?L0033 ;[INF] 2, 3 +; line 126 : { +??bb09_int_iic_ctr: +; line 127 : case ( IIC_IDLE ): +?L0024: +; line 128 : // 自局呼び出しに応答。 +; line 129 : // 初期化など +; line 130 : SPIE = 1; +$DGL 0,66 + set1 !IICCTL01.4 ;[INF] 4, 2 +; line 131 : state = IIC_RCV_REG_ADRS; +$DGL 0,67 + oneb !?L0003 ; state ;[INF] 3, 1 +; line 132 : WREL = 1; // ウェイト解除 +$DGL 0,68 + set1 !IICCTL01.5 ;[INF] 4, 2 +; line 133 : break; +$DGL 0,69 + br !?L0023 ;[INF] 3, 3 +; line 134 : +; line 135 : case ( IIC_RCV_REG_ADRS ): // ２バイト目（レジスタアドレス） +; 受信後に来る +?L0025: +; line 136 : // レジスタアドレス受信 +; line 137 : reg_adrs = IICA; +$DGL 0,73 + mov a,!IICA1 ;[INF] 3, 1 + mov !?L0004,a ; reg_adrs ;[INF] 3, 1 +; line 138 : tx_buf = vreg_ctr_read( reg_adrs ); // データの準備を +; しておく +$DGL 0,74 + mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + call !_vreg_ctr_read ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !?L0006,a ; tx_buf ;[INF] 3, 1 +; line 139 : if( reg_adrs != VREG_C_INFO ) +$DGL 0,75 + cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1 + bz $?L0030 ;[INF] 2, 4 +; line 140 : { +??bb0A_int_iic_ctr: +; line 141 : state = IIC_TX_OR_RX; +$DGL 0,77 + mov !?L0003,#02H ; state,2 ;[INF] 4, 1 +??eb0A_int_iic_ctr: +; line 142 : } +$DGL 0,78 + br $?L0031 ;[INF] 2, 3 +?L0030: +; line 143 : else +; line 144 : { +??bb0B_int_iic_ctr: +; line 145 : state = IIC_IDLE; +$DGL 0,81 + clrb !?L0003 ; state ;[INF] 3, 1 +??eb0B_int_iic_ctr: +; line 146 : } +?L0031: +; line 147 : WREL = 1; +$DGL 0,83 + set1 !IICCTL01.5 ;[INF] 4, 2 +; line 148 : break; +$DGL 0,84 + br $?L0023 ;[INF] 2, 3 +; line 149 : +; line 150 : case ( IIC_TX_OR_RX ): // ↑の次に来る割り込み。STなら送 +; 信準備、データが来たら書き込まれ +?L0026: +; line 151 : // if( TRC ){ // 送信方向フラグ で区別するのは、割り +; 込み遅延時に不具合が起こりえる +; line 152 : if( STD ) +$DGL 0,88 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].1 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0032 ;[INF] 2, 4 +; line 153 : { // スタートコンディション検出フラ +; グ +??bb0C_int_iic_ctr: +; line 154 : // リードされる +; line 155 : if( COI ) +$DGL 0,91 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].4 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0034 ;[INF] 2, 4 +; line 156 : { // アドレス一致フラグ +??bb0D_int_iic_ctr: +; line 157 : state = IIC_TX; +$DGL 0,93 + mov !?L0003,#03H ; state,3 ;[INF] 4, 1 +??eb0D_int_iic_ctr: +; line 158 : // no break, no return // +; line 159 : } +$DGL 0,95 + br $?L0033 ;[INF] 2, 3 +?L0034: +; line 160 : else +; line 161 : { +??bb0E_int_iic_ctr: +; line 162 : // リスタートで違うデバイスが呼ばれた！ +; line 163 : state = IIC_IDLE; // 終了処理 +$DGL 0,99 + clrb !?L0003 ; state ;[INF] 3, 1 +; line 164 : SPIE = 0; +$DGL 0,100 + clr1 !IICCTL01.4 ;[INF] 4, 2 +; line 165 : LREL = 1; // ウェイト解除? +$DGL 0,101 + set1 !IICCTL01.6 ;[INF] 4, 2 +; line 166 : return; +$DGL 0,102 + br $?L0023 ;[INF] 2, 3 +??eb0E_int_iic_ctr: +; line 167 : } +; line 168 : } +??eb0C_int_iic_ctr: +?L0032: +; line 169 : else +; line 170 : { +??bb0F_int_iic_ctr: +; line 171 : state = IIC_RX; // データ1バイト受信の割り込みだ +; った +$DGL 0,107 + mov !?L0003,#04H ; state,4 ;[INF] 4, 1 +??eb0F_int_iic_ctr: +; line 172 : // no break, no return // +; line 173 : } +?L0033: +; line 174 : +; line 175 : default: // バースト R/W でここが何回も呼 +; ばれることになる +; line 176 : if( state == IIC_TX ) +$DGL 0,112 + cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + bnz $?L0036 ;[INF] 2, 4 +; line 177 : { // 送信 +??bb10_int_iic_ctr: +; line 178 : IICA = tx_buf; +$DGL 0,114 + mov a,!?L0006 ; tx_buf ;[INF] 3, 1 + mov !IICA1,a ;[INF] 3, 1 +; line 179 : vreg_ctr_after_read( reg_adrs ); // 読んだらクリア +; などの処理 +$DGL 0,115 + mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + call !_vreg_ctr_after_read ;[INF] 3, 3 +??eb10_int_iic_ctr: +; line 180 : } +$DGL 0,116 + br $?L0037 ;[INF] 2, 3 +?L0036: +; line 181 : else +; line 182 : { // 受信 +??bb11_int_iic_ctr: +; line 183 : rx_buf = IICA; +$DGL 0,119 + mov a,!IICA1 ;[INF] 3, 1 + mov l,a ;[INF] 1, 1 +; line 184 : vreg_ctr_write( reg_adrs, rx_buf ); +$DGL 0,120 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + call !_vreg_ctr_write ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 185 : WREL = 1; +$DGL 0,121 + set1 !IICCTL01.5 ;[INF] 4, 2 +??eb11_int_iic_ctr: +; line 186 : } +?L0037: +; line 187 : // +; line 188 : if( ( reg_adrs != VREG_C_ACC_HOSU_HIST ) +; line 189 : && ( reg_adrs != VREG_C_INFO ) ) +$DGL 0,125 + cmp !?L0004,#04FH ; reg_adrs,79 ;[INF] 4, 1 + bz $?L0038 ;[INF] 2, 4 + cmp !?L0004,#07FH ; reg_adrs,127 ;[INF] 4, 1 + skz ;[INF] 2, 1 +; line 190 : { // この二つのレジスタは特殊なアクセス方法をする。アク +; セスポインタを進めない。 +??bb12_int_iic_ctr: +; line 191 : reg_adrs += 1; +$DGL 0,127 + inc !?L0004 ; reg_adrs ;[INF] 3, 2 +??eb12_int_iic_ctr: +; line 192 : } +?L0038: +; line 193 : +; line 194 : if( state == IIC_TX ) +$DGL 0,130 + cmp !?L0003,#03H ; state,3 ;[INF] 4, 1 + bnz $?L0023 ;[INF] 2, 4 +; line 195 : { // さらにつぎに送るデータの準備だ +; けシテオク。SPが来て使われないかもしれない +??bb13_int_iic_ctr: +; line 196 : tx_buf = vreg_ctr_read( reg_adrs ); +$DGL 0,132 + mov x,!?L0004 ; reg_adrs ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + call !_vreg_ctr_read ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !?L0006,a ; tx_buf ;[INF] 3, 1 +??eb13_int_iic_ctr: +; line 197 : } +; line 198 : break; +??eb09_int_iic_ctr: +; line 199 : } +?L0023: +; line 200 : } +$DGL 0,136 +??ef_int_iic_ctr: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_iic_ctr: +; line 201 : +; line 202 : +; line 203 : +; line 204 : // ======================================================== +; line 205 : void IIC_ctr_Init( void ) +; line 206 : { + +ROM_CODE CSEG BASE +_IIC_ctr_Init: +$DGL 1,112 +??bf_IIC_ctr_Init: +; line 207 : +; line 208 : IICAEN = 1; +$DGL 0,3 + set1 !PER3.0 ;[INF] 4, 2 +; line 209 : +; line 210 : IICE = 0; /* IICA disable */ +$DGL 0,5 + clr1 !IICCTL01.7 ;[INF] 4, 2 +; line 211 : +; line 212 : IICAMK = 1; /* INTIICA disable */ +$DGL 0,7 + set1 MK2H.3 ;[INF] 3, 2 +; line 213 : IICAIF = 0; /* clear INTIICA interrupt flag +; */ +$DGL 0,8 + clr1 IF2H.3 ;[INF] 3, 2 +; line 214 : +; line 215 : IICAPR0 = 1; /* set INTIICA high priority */ +$DGL 0,10 + set1 PR12H.3 ;[INF] 3, 2 +; line 216 : IICAPR1 = 0; /* set INTIICA high priority */ +$DGL 0,11 + clr1 PR02H.3 ;[INF] 3, 2 +; line 217 : +; line 218 : #ifdef _MODEL_TEG2_ +; line 219 : P6 &= ~0x3; +; line 220 : #else +; line 221 : P20 &= ~0x3; +$DGL 0,16 + mov a,!P20 ;[INF] 3, 1 + and a,#0FCH ; 252 ;[INF] 2, 1 + mov !P20,a ;[INF] 3, 1 +; line 222 : #endif +; line 223 : +; line 224 : SVA = IIC_C_SLAVEADDRESS; +$DGL 0,19 + mov !SVA1,#04AH ; 74 ;[INF] 4, 1 +; line 225 : IICF = 0x01; +$DGL 0,20 + oneb !IICF1 ;[INF] 3, 1 +; line 226 : +; line 227 : STCEN = 1; // リスタートの許可 +$DGL 0,22 + set1 !IICF1.1 ;[INF] 4, 2 +; line 228 : IICRSV = 1; // 通信予約をさせない:スレーブに +; 徹する +$DGL 0,23 + set1 !IICF1.0 ;[INF] 4, 2 +; line 229 : +; line 230 : SPIE = 0; // ストップコンディションでの割り +; 込みを禁止 +$DGL 0,25 + clr1 !IICCTL01.4 ;[INF] 4, 2 +; line 231 : WTIM = 1; // 自動でACKを返した後clkをLに固 +; 定する +$DGL 0,26 + set1 !IICCTL01.3 ;[INF] 4, 2 +; line 232 : ACKE = 1; // ダメCPUは無視して次の通信をは +; じめるかもしれないんで早くclkを開放しないといけない +$DGL 0,27 + set1 !IICCTL01.2 ;[INF] 4, 2 +; line 233 : +; line 234 : IICWH = 5; +$DGL 0,29 + mov !IICWH1,#05H ; 5 ;[INF] 4, 1 +; line 235 : IICWL = 10; // L期間の長さ +$DGL 0,30 + mov !IICWL1,#0AH ; 10 ;[INF] 4, 1 +; line 236 : +; line 237 : SMC = 1; // 高速モード +$DGL 0,32 + set1 !IICCTL11.3 ;[INF] 4, 2 +; line 238 : DFC = 1; // デジタルフィルタon (@fast mod +; e) +$DGL 0,33 + set1 !IICCTL11.2 ;[INF] 4, 2 +; line 239 : +; line 240 : IICAMK = 0; // 割り込みを許可 +$DGL 0,35 + clr1 MK2H.3 ;[INF] 3, 2 +; line 241 : +; line 242 : IICE = 1; +$DGL 0,37 + set1 !IICCTL01.7 ;[INF] 4, 2 +; line 243 : +; line 244 : #ifdef _MODEL_TEG2_ +; line 245 : PM6 &= ~0x3; /* set clock pin for IICA */ +; line 246 : #else +; line 247 : PM20 &= ~0x3; /* set clock pin for IICA */ +$DGL 0,42 + mov a,!PM20 ;[INF] 3, 1 + and a,#0FCH ; 252 ;[INF] 2, 1 + mov !PM20,a ;[INF] 3, 1 +; line 248 : #endif +; line 249 : } +$DGL 0,44 +??ef_IIC_ctr_Init: + ret ;[INF] 1, 6 +??ee_IIC_ctr_Init: +; line 250 : +; line 251 : +; line 252 : +; line 253 : // ======================================================== +; line 254 : void IIC_ctr_Stop( void ) +; line 255 : { +_IIC_ctr_Stop: +$DGL 1,118 +??bf_IIC_ctr_Stop: +; line 256 : IICE = 0; /* IICA disable */ +$DGL 0,2 + clr1 !IICCTL01.7 ;[INF] 4, 2 +; line 257 : IICAEN = 0; +$DGL 0,3 + clr1 !PER3.0 ;[INF] 4, 2 +; line 258 : } +$DGL 0,4 +??ef_IIC_ctr_Stop: + ret ;[INF] 1, 6 +??ee_IIC_ctr_Stop: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c +; +; $FUNC int_iic_ctr(65) +; void=(void) +; CODE SIZE= 355 bytes, CLOCK_SIZE= 278 clocks, STACK_SIZE= 28 bytes +; +; $CALL hosu_read_end(98) +; void=(void) +; +; $CALL rtc_unlock(99) +; void=(void) +; +; $CALL rtc_unlock(110) +; void=(void) +; +; $CALL vreg_ctr_read(138) +; bc=(int:ax) +; +; $CALL vreg_ctr_after_read(179) +; void=(int:ax) +; +; $CALL vreg_ctr_write(184) +; void=(int:ax, int:[sp+4]) +; +; $CALL vreg_ctr_read(196) +; bc=(int:ax) +; +; $FUNC IIC_ctr_Init(206) +; void=(void) +; CODE SIZE= 87 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes +; +; $FUNC IIC_ctr_Stop(255) +; void=(void) +; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/i2c_mcu.asm b/branches/0.10(X3)/inter_asm/i2c_mcu.asm new file mode 100644 index 0000000..8be712c --- /dev/null +++ b/branches/0.10(X3)/inter_asm/i2c_mcu.asm @@ -0,0 +1,2172 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_mcu.c +; In-file : i2c_mcu.c +; Asm-file : inter_asm\i2c_mcu.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0100H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, i2c_mcu.c +$DGS MOD_NAM, i2c_mcu, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS LAB_SYM, bs_F0085, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0085, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0086, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0086, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0087, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0087, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0084, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0084, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _nop8, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 023H, 00H, 00H +$DGS BEG_FUN, ??bf_nop8, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 04CH, 00H, 023H +$DGS END_FUN, ??ef_nop8, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02H +$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 03CH, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_read_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 057H, 04H, 02AH +$DGS FUN_ARG, _SLA, 02H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _adrs, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS AUT_VAR, _dat, 01H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 02EH +$DGS END_BLK, ??eb00_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb01_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 032H +$DGS END_BLK, ??eb01_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS BEG_BLK, ??bb02_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 019H, 00H, 036H +$DGS END_BLK, ??eb02_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS BEG_BLK, ??bb03_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 00H +$DGS END_BLK, ??eb03_iic_mcu_read_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 032H +$DGS END_FUN, ??ef_iic_mcu_read_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 039H +$DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 05FH, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09EH, 02H, 045H +$DGS FUN_ARG, _slave, 00H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _len, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _dest, 0CH, 0FFFFH, 0CH, 09H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS BEG_BLK, ??bb00_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 049H +$DGS END_BLK, ??eb00_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS BEG_BLK, ??bb01_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 04DH +$DGS END_BLK, ??eb01_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS BEG_BLK, ??bb02_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 051H +$DGS END_BLK, ??eb02_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS BEG_BLK, ??bb03_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 053H +$DGS BEG_BLK, ??bb04_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 057H +$DGS END_BLK, ??eb04_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 037H +$DGS BEG_BLK, ??bb05_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03BH, 00H, 00H +$DGS END_BLK, ??eb05_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03DH +$DGS END_BLK, ??eb03_iic_mcu_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 041H +$DGS END_FUN, ??ef_iic_mcu_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 049H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 074H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_write_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0F2H, 02H, 066H +$DGS FUN_ARG, _SLA, 00H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _dat, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS BEG_BLK, ??bb00_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 06AH +$DGS END_BLK, ??eb00_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb01_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 06EH +$DGS END_BLK, ??eb01_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS BEG_BLK, ??bb02_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01AH, 00H, 00H +$DGS END_BLK, ??eb02_iic_mcu_write_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS END_FUN, ??ef_iic_mcu_write_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 024H +$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 097H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0129H, 02H, 07DH +$DGS FUN_ARG, _slave, 00H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _adrs, 08H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _len, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _src, 0CH, 0FFFFH, 01H, 09H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS BEG_BLK, ??bb00_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 081H +$DGS END_BLK, ??eb00_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb01_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0FH, 00H, 085H +$DGS END_BLK, ??eb01_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb02_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 089H +$DGS END_BLK, ??eb02_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 024H +$DGS BEG_BLK, ??bb03_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 08BH +$DGS BEG_BLK, ??bb04_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02FH, 00H, 091H +$DGS END_BLK, ??eb04_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS END_BLK, ??eb03_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03EH +$DGS BEG_BLK, ??bb05_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 040H, 00H, 00H +$DGS END_BLK, ??eb05_iic_mcu_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04AH +$DGS END_FUN, ??ef_iic_mcu_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04CH +$DGS GLV_SYM, _int_dma1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0AAH, 00H, 00H +$DGS BEG_FUN, ??bf_int_dma1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0184H, 016H, 09CH +$DGS REG_VAR, _i, 0103H, 0FFFFH, 010DH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 09EH +$DGS BEG_BLK, ??bb01_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 0A4H +$DGS END_BLK, ??eb01_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS END_BLK, ??eb00_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS BEG_BLK, ??bb02_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 00H +$DGS END_BLK, ??eb02_int_dma1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 033H +$DGS END_FUN, ??ef_int_dma1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 036H +$DGS GLV_SYM, _int_iic10, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0B8H, 00H, 00H +$DGS BEG_FUN, ??bf_int_iic10, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 01C4H, 016H, 0AEH +$DGS BEG_BLK, ??bb00_int_iic10, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 0B2H +$DGS END_BLK, ??eb00_int_iic10, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 09H +$DGS BEG_BLK, ??bb01_int_iic10, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 00H +$DGS END_BLK, ??eb01_int_iic10, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS END_FUN, ??ef_int_iic10, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 033H +$DGS STA_SYM, _iic_mcu_call_slave, U, U, 0CH, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0C3H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_call_slave, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0201H, 02H, 0BDH +$DGS REG_PAR, _slave, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_iic_mcu_call_slave, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 00H +$DGS END_BLK, ??eb00_iic_mcu_call_slave, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 09H +$DGS END_FUN, ??ef_iic_mcu_call_slave, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0CH +$DGS STA_SYM, _iic_mcu_send_a_byte, U, U, 0CH, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0D2H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_send_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0215H, 02H, 0C8H +$DGS REG_PAR, _dat, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0CCH +$DGS END_BLK, ??eb00_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb01_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 00H +$DGS END_BLK, ??eb01_iic_mcu_send_a_byte, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS END_FUN, ??ef_iic_mcu_send_a_byte, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0FH +$DGS STA_SYM, _iic_mcu_send_st, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0D8H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_send_st, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 022CH, 00H, 0D8H +$DGS END_FUN, ??ef_iic_mcu_send_st, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 016H +$DGS STA_SYM, _iic_mcu_send_re_st, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0DEH, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_send_re_st, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0249H, 00H, 0DEH +$DGS END_FUN, ??ef_iic_mcu_send_re_st, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 022H +$DGS STA_SYM, _iic_mcu_send_sp, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0E4H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_send_sp, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0273H, 00H, 0E4H +$DGS END_FUN, ??ef_iic_mcu_send_sp, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 023H +$DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0F2H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_start, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 029EH, 00H, 0E8H +$DGS BEG_BLK, ??bb00_iic_mcu_start, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0ECH +$DGS END_BLK, ??eb00_iic_mcu_start, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06H +$DGS BEG_BLK, ??bb01_iic_mcu_start, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 00H +$DGS END_BLK, ??eb01_iic_mcu_start, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS END_FUN, ??ef_iic_mcu_start, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 030H +$DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0100H, 00H, 00H +$DGS BEG_FUN, ??bf_iic_mcu_stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02D6H, 00H, 0F6H +$DGS BEG_BLK, ??bb00_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 0FAH +$DGS END_BLK, ??eb00_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04H +$DGS BEG_BLK, ??bb01_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 00H +$DGS END_BLK, ??eb01_iic_mcu_stop, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06H +$DGS END_FUN, ??ef_iic_mcu_stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09H +$DGS GLV_SYM, _iic_mcu_wo_dma, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_busy, U, U, 0134CH, 027H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_initialized, U, U, 0134CH, 027H, 00H, 00H +$DGS GLV_SYM, _iic_send_work, U, U, 0CH, 026H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _p_iic_send_wo_dma_dat, U, U, 0CH, 026H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS GLV_SYM, _iic_send_wo_dma_len, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _@RTARG0 + PUBLIC _iic_mcu_wo_dma + PUBLIC _iic_mcu_busy + PUBLIC _iic_mcu_initialized + PUBLIC _iic_send_work + PUBLIC _p_iic_send_wo_dma_dat + PUBLIC _iic_send_wo_dma_len + PUBLIC _iic_mcu_bus_status + PUBLIC _nop8 + PUBLIC _iic_mcu_read_a_byte + PUBLIC _iic_mcu_read + PUBLIC _iic_mcu_write_a_byte + PUBLIC _iic_mcu_write + PUBLIC _int_dma1 + PUBLIC _int_iic10 + PUBLIC _iic_mcu_start + PUBLIC _iic_mcu_stop + +@@BITS BSEG +_iic_mcu_wo_dma DBIT +_iic_mcu_busy DBIT +_iic_mcu_initialized DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP +_iic_send_work: DS (4) +_p_iic_send_wo_dma_dat: DS (2) +_iic_send_wo_dma_len: DS (1) +_iic_mcu_bus_status: DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0085: + shrw ax,8 ;[INF] 2, 1 + br !_iic_mcu_send_a_byte ;[INF] 3, 3 +es_F0085: + +ROM_CODE CSEG BASE +bs_S0086: + movw ax,#04H ; 4 ;[INF] 3, 1 + movw !ST0,ax ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0086: + +ROM_CODE CSEG BASE +bs_S0087: + movw ax,#04H ; 4 ;[INF] 3, 1 + movw !SS0,ax ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0087: + +ROM_CODE CSEG BASE +bs_F0084: + mov a,[hl] ;[INF] 1, 1 + shrw ax,8 ;[INF] 2, 1 + call !_iic_mcu_call_slave ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0084: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0084 +; CODE SIZE= 8 bytes +; +; $SUB bs_F0085 +; CODE SIZE= 5 bytes +; +; $SUB bs_S0086 +; CODE SIZE= 7 bytes +; +; $SUB bs_S0087 +; CODE SIZE= 7 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : 簡易I2C（内蔵ペリフェラル使用）通信 +; line 3 : de JHL 藤田＠開技 +; line 4 : '09 Feb - +; line 5 : ======================================================== */ +; line 6 : #pragma sfr +; line 7 : #pragma di +; line 8 : #pragma ei +; line 9 : #pragma nop +; line 10 : #pragma inline // memcpy()をインライン展開する +; line 11 : +; line 12 : #include "incs.h" +; line 13 : #include "i2c_mcu.h" +; line 14 : +; line 15 : +; line 16 : +; line 17 : // ======================================================== +; line 18 : // レジスタのビット名 +; line 19 : // プリフィックスbだが、一部のビット名がレジスタ名にかぶるため.. +; . +; line 20 : // SMR0n +; line 21 : #define bCKS0 ( 1 << 15 ) +; line 22 : #define bCCS0 ( 1 << 14 ) +; line 23 : #define bSTS0 ( 1 << 8 ) +; line 24 : #define bSIS0 ( 1 << 6 ) +; line 25 : #define bMD0n2 ( 1 << 2 ) +; line 26 : #define bMD0n1 ( 1 << 1 ) +; line 27 : #define bMD0n0 ( 1 << 0 ) +; line 28 : #define bSMR0n_FIXEDBIT ( 1 << 5 ) +; line 29 : +; line 30 : // SSR0n +; line 31 : #define bit_TSF0 6 +; line 32 : #define PEF0 ( 1 << 1 ) +; line 33 : +; line 34 : // SIR0n +; line 35 : #define PECT0 ( 1 << 1 ) +; line 36 : +; line 37 : // SCR0n +; line 38 : #define TXE0 ( 1 << 15 ) +; line 39 : #define RXE0 ( 1 << 14 ) +; line 40 : #define SLC02 4 +; line 41 : #define DLS02 0 +; line 42 : #define TSF0 ( 1 << 6 ) +; line 43 : +; line 44 : // SOn +; line 45 : #define TAUS_MASK 0b0000101100001011; +; line 46 : +; line 47 : // DMCn +; line 48 : #define DRS ( 1 << 6 ) +; line 49 : +; line 50 : +; line 51 : +; line 52 : +; line 53 : // ======================================================== +; line 54 : static void iic_mcu_send_st( ); +; line 55 : static void iic_mcu_send_re_st( ); +; line 56 : static void iic_mcu_send_sp( ); +; line 57 : static err iic_mcu_send_a_byte( u8 ); +; line 58 : static err iic_mcu_call_slave( u8 slave ); +; line 59 : +; line 60 : +; line 61 : +; line 62 : // ======================================================== +; line 63 : bit iic_mcu_wo_dma; +; line 64 : volatile bit iic_mcu_busy; +; line 65 : volatile bit iic_mcu_initialized; +; line 66 : +; line 67 : +; line 68 : u8 iic_send_work[4]; +; line 69 : u8 *p_iic_send_wo_dma_dat; +; line 70 : u8 iic_send_wo_dma_len; +; line 71 : +; line 72 : u8 iic_mcu_bus_status; // 一文字リードの時はデータを返す +; 。 +; line 73 : // ステータスが必要ならこっちを呼 +; んで +; line 74 : +; line 75 : void nop8() +; line 76 : { + +ROM_CODE CSEG BASE +_nop8: +$DGL 1,29 +??bf_nop8: +; line 77 : } +$DGL 0,2 +??ef_nop8: + ret ;[INF] 1, 6 +??ee_nop8: +; line 78 : +; line 79 : +; line 80 : +; line 81 : /* ======================================================== +; line 82 : スレーブからの 『1文字』 リード +; line 83 : 返値がデータそのものです。 +; line 84 : エラー判定ができません。 +; line 85 : ======================================================== */ +; line 86 : u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs ) +; line 87 : { +_iic_mcu_read_a_byte: +$DGL 1,35 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_iic_mcu_read_a_byte: +; line 88 : u8 dat; +; line 89 : +; line 90 : if( iic_mcu_initialized == 0 ) +$DGL 0,4 + bt _iic_mcu_initialized,$?L0005 ;[INF] 4, 5 +; line 91 : { +??bb00_iic_mcu_read_a_byte: +; line 92 : #ifdef _debug_ +; line 93 : iic_mcu_start( ); +$DGL 0,7 + call !_iic_mcu_start ;[INF] 3, 3 +??eb00_iic_mcu_read_a_byte: +; line 94 : #else +; line 95 : while( 1 ) +; line 96 : { +; line 97 : } +; line 98 : #endif +; line 99 : } +?L0005: +; line 100 : +; line 101 : while( iic_mcu_busy ) +$DGL 0,15 + bf _iic_mcu_busy,$?L0008 ;[INF] 4, 5 +; line 102 : { +??bb01_iic_mcu_read_a_byte: +; line 103 : NOP( ); +$DGL 0,17 + nop ;[INF] 1, 1 +??eb01_iic_mcu_read_a_byte: +; line 104 : } +$DGL 0,18 + br $?L0005 ;[INF] 2, 3 +?L0008: +; line 105 : iic_mcu_busy = 1; +$DGL 0,19 + set1 _iic_mcu_busy ;[INF] 3, 2 +; line 106 : +; line 107 : iic_mcu_bus_status = ERR_OK; +$DGL 0,21 + clrb !_iic_mcu_bus_status ;[INF] 3, 1 +; line 108 : +; line 109 : // スタートコンディションとスレーブの呼び出し、レジスタアドレ +; スの送信 +; line 110 : if( iic_mcu_call_slave( SLA ) != 0 ) +$DGL 0,24 + mov a,[hl+2] ; SLA ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + call !_iic_mcu_call_slave ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + bz $?L0009 ;[INF] 2, 4 +; line 111 : { +??bb02_iic_mcu_read_a_byte: +; line 112 : iic_mcu_bus_status = ERR_NOSLAVE; +$DGL 0,26 + mov !_iic_mcu_bus_status,#02H ; 2 ;[INF] 4, 1 +; line 113 : iic_mcu_busy = 0; +$DGL 0,27 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 114 : return ( 0 ); +$DGL 0,28 + clrw bc ;[INF] 1, 1 + br $?L0004 ;[INF] 2, 3 +??eb02_iic_mcu_read_a_byte: +; line 115 : } +?L0009: +; line 116 : +; line 117 : // レジスタアドレスの送信 +; line 118 : iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない +$DGL 0,32 + mov a,[hl+10] ; adrs ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 119 : // if( err != ERR_SUCCESS )〜 +; line 120 : +; line 121 : // データ受信 // +; line 122 : iic_mcu_send_re_st( ); // リスタートコンディション +$DGL 0,36 + call !_iic_mcu_send_re_st ;[INF] 3, 3 +; line 123 : iic_mcu_send_a_byte( SLA | 0x01 ); // 送信完了まで戻ってきま +; せん。 +$DGL 0,37 + mov a,[hl+2] ; SLA ;[INF] 2, 1 + or a,#01H ; 1 ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 124 : +; line 125 : ST0 = 0x0004; // 受信モードに設定を変えるのでロ +; ジック停止 +$DGL 0,39 + call !bs_S0086 ;[INF] 3, 3 +; line 126 : SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 +$DGL 0,40 + movw ax,#04017H ; 16407 ;[INF] 3, 1 + movw !SCR02,ax ;[INF] 3, 1 +; line 127 : SS0 = 0x0004; // 通信待機 +$DGL 0,41 + call !bs_S0087 ;[INF] 3, 3 +; line 128 : +; line 129 : SOE0 = 0x0000; // 1バイト送信なので、最後のNAKを +; 送る +$DGL 0,43 + clrw ax ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 130 : IICIF10 = 0; +$DGL 0,44 + clr1 IF1L.0 ;[INF] 3, 2 +; line 131 : SIO10 = 0xFF; // ダミーデータを書くと受信開始 +$DGL 0,45 + mov SIO10,#0FFH ; 255 ;[INF] 3, 1 +; line 132 : +; line 133 : while( IICIF10 == 0 ) +$DGL 0,47 +?L0011: + bt IF1L.0,$?L0012 ;[INF] 4, 5 +; line 134 : { // 受信完了待ち +??bb03_iic_mcu_read_a_byte: +; line 135 : ; +??eb03_iic_mcu_read_a_byte: +; line 136 : } +$DGL 0,50 + br $?L0011 ;[INF] 2, 3 +?L0012: +; line 137 : dat = SIO10; +$DGL 0,51 + mov a,SIO10 ;[INF] 2, 1 + mov [hl+1],a ; dat ;[INF] 2, 1 +; line 138 : +; line 139 : iic_mcu_send_sp( ); +$DGL 0,53 + call !_iic_mcu_send_sp ;[INF] 3, 3 +; line 140 : IICIF10 = 0; // 後を濁さないこと +$DGL 0,54 + clr1 IF1L.0 ;[INF] 3, 2 +; line 141 : iic_mcu_busy = 0; +$DGL 0,55 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 142 : return ( dat ); +$DGL 0,56 + mov a,[hl+1] ; dat ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 +; line 143 : } +?L0004: +$DGL 0,57 +??ef_iic_mcu_read_a_byte: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_read_a_byte: +; line 144 : +; line 145 : +; line 146 : +; line 147 : /* ======================================================== +; line 148 : スレーブからのリード +; line 149 : 0 正常終了 +; line 150 : 1 スレーブが応答しない +; line 151 : 2 バスが誰かに占有されていてタイムアウト +; line 152 : 3 意味不明エラー +; line 153 : 【注】 +; line 154 : スレーブがウェイトコンディションを出すことは禁止です。 +; line 155 : その場合でもエラー検出などできません +; line 156 : ======================================================== */ +; line 157 : err iic_mcu_read( u8 slave, u8 adrs, u8 len, u8 * dest ) +; line 158 : { +_iic_mcu_read: +$DGL 1,60 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_iic_mcu_read: +; line 159 : +; line 160 : //* +; line 161 : // 使用中なら待つ +; line 162 : if( iic_mcu_initialized == 0 ) +$DGL 0,5 + bt _iic_mcu_initialized,$?L0015 ;[INF] 4, 5 +; line 163 : { +??bb00_iic_mcu_read: +; line 164 : #ifdef _debug_ +; line 165 : iic_mcu_start( ); +$DGL 0,8 + call !_iic_mcu_start ;[INF] 3, 3 +??eb00_iic_mcu_read: +; line 166 : #else +; line 167 : while( 1 ) +; line 168 : { +; line 169 : } +; line 170 : #endif +; line 171 : } +?L0015: +; line 172 : while( iic_mcu_busy ) +$DGL 0,15 + bf _iic_mcu_busy,$?L0018 ;[INF] 4, 5 +; line 173 : { +??bb01_iic_mcu_read: +; line 174 : NOP( ); +$DGL 0,17 + nop ;[INF] 1, 1 +??eb01_iic_mcu_read: +; line 175 : } +$DGL 0,18 + br $?L0015 ;[INF] 2, 3 +?L0018: +; line 176 : /*/ +; line 177 : // 使用中なら帰る +; line 178 : if( iic_mcu_initialized == 0 ){ +; line 179 : return(0x80); +; line 180 : } +; line 181 : if( iic_mcu_busy != 0 ){ +; line 182 : return( 3 ); +; line 183 : } +; line 184 : //*/ +; line 185 : +; line 186 : iic_mcu_busy = 1; +$DGL 0,29 + set1 _iic_mcu_busy ;[INF] 3, 2 +; line 187 : // スタートコンディションとスレーブの呼び出し、レジスタアドレ +; スの送信 +; line 188 : if( iic_mcu_call_slave( slave ) != 0 ) +$DGL 0,31 + call !bs_F0084 ;[INF] 3, 3 + bz $?L0019 ;[INF] 2, 4 +; line 189 : { +??bb02_iic_mcu_read: +; line 190 : iic_mcu_busy = 0; +$DGL 0,33 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 191 : return ( ERR_NOSLAVE ); +$DGL 0,34 + onew bc ;[INF] 1, 1 + incw bc ;[INF] 1, 1 + br $?L0014 ;[INF] 2, 3 +??eb02_iic_mcu_read: +; line 192 : } +?L0019: +; line 193 : +; line 194 : // レジスタアドレスの送信 +; line 195 : iic_mcu_send_a_byte( adrs ); // 終わるまで帰ってこない +$DGL 0,38 + mov a,[hl+8] ; adrs ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 196 : // if( err != ERR_SUCCESS )〜 +; line 197 : +; line 198 : // データ受信 // +; line 199 : iic_mcu_send_re_st( ); // リスタートコンディション +$DGL 0,42 + call !_iic_mcu_send_re_st ;[INF] 3, 3 +; line 200 : iic_mcu_send_a_byte( slave | 0x01 ); // 送信完了まで戻 +; ってきません。 +$DGL 0,43 + mov a,[hl] ; slave ;[INF] 1, 1 + or a,#01H ; 1 ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 201 : +; line 202 : // データ受信 +; line 203 : ST0 = 0x0004; // 受信モードに設定を変えるのでロ +; ジック停止 +$DGL 0,46 + call !bs_S0086 ;[INF] 3, 3 +; line 204 : SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02; // 受信設定 +$DGL 0,47 + movw ax,#04017H ; 16407 ;[INF] 3, 1 + movw !SCR02,ax ;[INF] 3, 1 +; line 205 : SS0 = 0x0004; // 通信待機 +$DGL 0,48 + call !bs_S0087 ;[INF] 3, 3 +; line 206 : +; line 207 : do +?L0021: +; line 208 : { +??bb03_iic_mcu_read: +; line 209 : if( len == 1 ) +$DGL 0,52 + mov a,[hl+10] ; len ;[INF] 2, 1 + dec a ;[INF] 1, 1 + bnz $?L0024 ;[INF] 2, 4 +; line 210 : { +??bb04_iic_mcu_read: +; line 211 : SOE0 = 0x0000; // 最後のNAK +$DGL 0,54 + clrw ax ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +??eb04_iic_mcu_read: +; line 212 : } +?L0024: +; line 213 : IICIF10 = 0; +$DGL 0,56 + clr1 IF1L.0 ;[INF] 3, 2 +; line 214 : SIO10 = 0xFF; // ダミーデータを書くと受信開始 +$DGL 0,57 + mov SIO10,#0FFH ; 255 ;[INF] 3, 1 +; line 215 : while( IICIF10 == 0 ) +$DGL 0,58 +?L0026: + bt IF1L.0,$?L0027 ;[INF] 4, 5 +; line 216 : { // 受信完了待ち +??bb05_iic_mcu_read: +; line 217 : ; +??eb05_iic_mcu_read: +; line 218 : } +$DGL 0,61 + br $?L0026 ;[INF] 2, 3 +?L0027: +; line 219 : *dest = SIO10; +$DGL 0,62 + movw ax,[hl+12] ; dest ;[INF] 2, 1 + movw de,ax ;[INF] 1, 1 + mov a,SIO10 ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 220 : dest++; +$DGL 0,63 + incw [hl+12] ; dest ;[INF] 3, 2 +; line 221 : len--; +$DGL 0,64 + dec [hl+10] ; len ;[INF] 3, 2 +??eb03_iic_mcu_read: +; line 222 : } +; line 223 : while( len != 0 ); +$DGL 0,66 + mov a,[hl+10] ; len ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0021 ;[INF] 2, 4 +; line 224 : +; line 225 : iic_mcu_send_sp( ); +$DGL 0,68 + call !_iic_mcu_send_sp ;[INF] 3, 3 +; line 226 : +; line 227 : IICIF10 = 0; +$DGL 0,70 + clr1 IF1L.0 ;[INF] 3, 2 +; line 228 : iic_mcu_busy = 0; +$DGL 0,71 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 229 : return ( ERR_SUCCESS ); +$DGL 0,72 + clrw bc ;[INF] 1, 1 +; line 230 : } +?L0014: +$DGL 0,73 +??ef_iic_mcu_read: + pop ax ;[INF] 1, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_read: +; line 231 : +; line 232 : +; line 233 : +; line 234 : +; line 235 : /* ======================================================== +; line 236 : スレーブへ 『１バイト』 ライト +; line 237 : 前の転送が終わるのを待って、ライトします。 +; line 238 : 返値　iic_mcu_write　に同じ +; line 239 : +; line 240 : ======================================================== */ +; line 241 : err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat ) +; line 242 : { +_iic_mcu_write_a_byte: +$DGL 1,95 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_iic_mcu_write_a_byte: +; line 243 : +; line 244 : if( iic_mcu_initialized == 0 ) +$DGL 0,3 + bt _iic_mcu_initialized,$?L0030 ;[INF] 4, 5 +; line 245 : { +??bb00_iic_mcu_write_a_byte: +; line 246 : #ifdef _debug_ +; line 247 : iic_mcu_start( ); +$DGL 0,6 + call !_iic_mcu_start ;[INF] 3, 3 +??eb00_iic_mcu_write_a_byte: +; line 248 : #else +; line 249 : while( 1 ) +; line 250 : { +; line 251 : } +; line 252 : #endif +; line 253 : } +?L0030: +; line 254 : while( iic_mcu_busy ) +$DGL 0,13 + bf _iic_mcu_busy,$?L0033 ;[INF] 4, 5 +; line 255 : { +??bb01_iic_mcu_write_a_byte: +; line 256 : NOP( ); +$DGL 0,15 + nop ;[INF] 1, 1 +??eb01_iic_mcu_write_a_byte: +; line 257 : } +$DGL 0,16 + br $?L0030 ;[INF] 2, 3 +?L0033: +; line 258 : iic_mcu_busy = 1; +$DGL 0,17 + set1 _iic_mcu_busy ;[INF] 3, 2 +; line 259 : #if 0 +; line 260 : temp = dat; +; line 261 : return ( iic_mcu_write( SLA, adrs, 1, &temp ) ); +; line 262 : } +; line 263 : #else +; line 264 : // スタートコンディションとスレーブの呼び出し... +; line 265 : IICMK10 = 1; +$DGL 0,24 + set1 MK1L.0 ;[INF] 3, 2 +; line 266 : if( iic_mcu_call_slave( SLA ) != 0 ) +$DGL 0,25 + call !bs_F0084 ;[INF] 3, 3 + bz $?L0034 ;[INF] 2, 4 +; line 267 : { +??bb02_iic_mcu_write_a_byte: +; line 268 : iic_mcu_busy = 0; +$DGL 0,27 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 269 : return ( ERR_NAK ); +$DGL 0,28 + onew bc ;[INF] 1, 1 + br $?L0029 ;[INF] 2, 3 +??eb02_iic_mcu_write_a_byte: +; line 270 : } +?L0034: +; line 271 : iic_mcu_send_a_byte( adrs ); +$DGL 0,30 + mov a,[hl+8] ; adrs ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 272 : iic_mcu_send_a_byte( dat ); +$DGL 0,31 + mov a,[hl+10] ; dat ;[INF] 2, 1 + call !bs_F0085 ;[INF] 3, 3 +; line 273 : iic_mcu_send_sp( ); +$DGL 0,32 + call !_iic_mcu_send_sp ;[INF] 3, 3 +; line 274 : iic_mcu_busy = 0; +$DGL 0,33 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 275 : return ( ERR_SUCCESS ); +$DGL 0,34 + clrw bc ;[INF] 1, 1 +; line 276 : #endif +; line 277 : } +?L0029: +$DGL 0,36 +??ef_iic_mcu_write_a_byte: + pop ax ;[INF] 1, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_write_a_byte: +; line 278 : +; line 279 : +; line 280 : +; line 281 : /* ======================================================== +; line 282 : スレーブへライト +; line 283 : レジスタ adrs を先頭に、 +; line 284 : *strから +; line 285 : len文字書きます。 +; line 286 : +; line 287 : 0 正常終了 +; line 288 : 1 スレーブが応答しない +; line 289 : 2 バスが誰かに占有されていてタイムアウト +; line 290 : 3 前に指示された通信がまだ終わってない +; line 291 : 【注】 +; line 292 : スレーブがウェイトコンディションを出すことは禁止です。 +; line 293 : その場合でもエラー検出などできません +; line 294 : DMA1を使用します。 +; line 295 : *************************************************************** +; ***************/ +; line 296 : err iic_mcu_write( u8 slave, u8 adrs, u8 len, void * src ) +; line 297 : { +_iic_mcu_write: +$DGL 1,116 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_iic_mcu_write: +; line 298 : //* +; line 299 : // 使用中なら待つ +; line 300 : if( iic_mcu_initialized == 0 ) +$DGL 0,4 + bt _iic_mcu_initialized,$?L0038 ;[INF] 4, 5 +; line 301 : { +??bb00_iic_mcu_write: +; line 302 : #ifdef _debug_ +; line 303 : iic_mcu_start( ); +$DGL 0,7 + call !_iic_mcu_start ;[INF] 3, 3 +??eb00_iic_mcu_write: +; line 304 : #else +; line 305 : while( 1 ) +; line 306 : { +; line 307 : } +; line 308 : #endif +; line 309 : } +?L0038: +; line 310 : while( iic_mcu_busy ) +$DGL 0,14 + bf _iic_mcu_busy,$?L0041 ;[INF] 4, 5 +; line 311 : { +??bb01_iic_mcu_write: +; line 312 : NOP( ); +$DGL 0,16 + nop ;[INF] 1, 1 +??eb01_iic_mcu_write: +; line 313 : } +$DGL 0,17 + br $?L0038 ;[INF] 2, 3 +?L0041: +; line 314 : /*/ +; line 315 : // 使用中なら帰る +; line 316 : if( iic_mcu_initialized == 0 ){ +; line 317 : return(0x80); +; line 318 : } +; line 319 : if( iic_mcu_busy != 0 ){ +; line 320 : return( 3 ); +; line 321 : } +; line 322 : //*/ +; line 323 : iic_mcu_busy = 1; +$DGL 0,27 + set1 _iic_mcu_busy ;[INF] 3, 2 +; line 324 : // スタートコンディションとスレーブの呼び出し... +; line 325 : IICMK10 = 1; +$DGL 0,29 + set1 MK1L.0 ;[INF] 3, 2 +; line 326 : IICIF10 = 0; +$DGL 0,30 + clr1 IF1L.0 ;[INF] 3, 2 +; line 327 : if( iic_mcu_call_slave( slave ) != 0 ) +$DGL 0,31 + call !bs_F0084 ;[INF] 3, 3 + bz $?L0042 ;[INF] 2, 4 +; line 328 : { +??bb02_iic_mcu_write: +; line 329 : iic_mcu_busy = 0; +$DGL 0,33 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 330 : EI( ); +$DGL 0,34 + ei ;[INF] 3, 4 +; line 331 : return ( ERR_NAK ); +$DGL 0,35 + onew bc ;[INF] 1, 1 + br $?L0037 ;[INF] 2, 3 +??eb02_iic_mcu_write: +; line 332 : } +?L0042: +; line 333 : +; line 334 : IICIF10 = 0; +$DGL 0,38 + clr1 IF1L.0 ;[INF] 3, 2 +; line 335 : if( !iic_mcu_wo_dma ) +$DGL 0,39 + bt _iic_mcu_wo_dma,$?L0044 ;[INF] 4, 5 +; line 336 : { +??bb03_iic_mcu_write: +; line 337 : // DMAを使用する（通常） +; line 338 : +; line 339 : // レジスタアドレスを送り、データの準備 +; line 340 : memcpy( iic_send_work, src, 4 ); //バッファとして +; 4バイトしか用意して無いため。 +$DGL 0,44 + push hl ;[INF] 1, 1 + movw de,#loww (_iic_send_work) ;[INF] 3, 1 + movw ax,[hl+12] ; src ;[INF] 2, 1 + movw hl,ax ;[INF] 1, 1 + mov c,#04H ; 4 ;[INF] 2, 1 +?L0046: + mov a,[hl] ;[INF] 1, 1 + mov [de],a ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw hl ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $?L0046 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 +; line 341 : // DMAセット +; line 342 : while( DST1 ) +$DGL 0,46 +?L0048: + bf DRC1.0,$?L0049 ;[INF] 4, 5 +; line 343 : {; +??bb04_iic_mcu_write: +??eb04_iic_mcu_write: +; line 344 : } +$DGL 0,48 + br $?L0048 ;[INF] 2, 3 +?L0049: +; line 345 : +; line 346 : DEN1 = 1; +$DGL 0,50 + set1 DRC1.7 ;[INF] 3, 2 +; line 347 : DSA1 = ( u8 ) ( &SIO10 ); +$DGL 0,51 + mov DSA1,#044H ; 68 ;[INF] 3, 1 +; line 348 : DRA1 = ( u16 ) iic_send_work; +$DGL 0,52 + movw DRA1,#loww (_iic_send_work) ;[INF] 4, 1 +; line 349 : DBC1 = len; +$DGL 0,53 + mov a,[hl+10] ; len ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + movw DBC1,ax ;[INF] 2, 1 +; line 350 : DMC1 = DRS | 8; // RAM -> SFR, 8bit, IRQ, IIC10 +$DGL 0,54 + mov DMC1,#048H ; 72 ;[INF] 3, 1 +; line 351 : +; line 352 : DMAIF1 = 0; +$DGL 0,56 + clr1 IF0H.4 ;[INF] 3, 2 +; line 353 : DMAMK1 = 0; +$DGL 0,57 + clr1 MK0H.4 ;[INF] 3, 2 +; line 354 : DST1 = 1; +$DGL 0,58 + set1 DRC1.0 ;[INF] 3, 2 +; line 355 : +; line 356 : SIO10 = adrs; // 書きっぱなし！ 割り込みが発生 +; してDMAスタート +$DGL 0,60 + mov a,[hl+8] ; adrs ;[INF] 2, 1 + mov SIO10,a ;[INF] 2, 1 +??eb03_iic_mcu_write: +; line 357 : // 残りは割り込みルーチン内で +; line 358 : } +$DGL 0,62 + br $?L0045 ;[INF] 2, 3 +?L0044: +; line 359 : else +; line 360 : { +??bb05_iic_mcu_write: +; line 361 : // DMAを使用しない // +; line 362 : +; line 363 : // レジスタアドレスの送信 +; line 364 : SIO10 = adrs; +$DGL 0,68 + mov a,[hl+8] ; adrs ;[INF] 2, 1 + mov SIO10,a ;[INF] 2, 1 +; line 365 : +; line 366 : IICMK10 = 0; +$DGL 0,70 + clr1 MK1L.0 ;[INF] 3, 2 +; line 367 : iic_send_wo_dma_len = len; +$DGL 0,71 + mov a,[hl+10] ; len ;[INF] 2, 1 + mov !_iic_send_wo_dma_len,a ;[INF] 3, 1 +; line 368 : p_iic_send_wo_dma_dat = src; +$DGL 0,72 + movw ax,[hl+12] ; src ;[INF] 2, 1 + movw !_p_iic_send_wo_dma_dat,ax ;[INF] 3, 1 +??eb05_iic_mcu_write: +; line 369 : // 残りは割り込みルーチン内で +; line 370 : } +?L0045: +; line 371 : return ( ERR_SUCCESS ); +$DGL 0,75 + clrw bc ;[INF] 1, 1 +; line 372 : } +?L0037: +$DGL 0,76 +??ef_iic_mcu_write: + pop ax ;[INF] 1, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_write: +; line 373 : +; line 374 : +; line 375 : +; line 376 : +; line 377 : /* ======================================================== +; line 378 : DMA１転送終了割り込み +; line 379 : IIC_mcu の送信完了コールバック関数のようなもの +; line 380 : 注：DMA転送が終わっただけで、I2Cの転送は終わってません +; line 381 : 　 割り込み中などで、DMA1の処理が遅延した場合、 +; line 382 : IIC10の割り込みの準備ができずに、割り込みを発生させられなくなる +; line 383 : 恐れがあります。また、回避方法も特にありません。 +; line 384 : 　そのため、DMA仕様の差異は、最後のバイトは送信完了を +; line 385 : フラグのポーリングで確認します。 +; line 386 : ======================================================== */ +; line 387 : __interrupt void int_dma1( ) +; line 388 : { + +@@BASE CSEG BASE +_int_dma1: +$DGL 1,151 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_int_dma1: +; line 389 : u16 i = 0; +$DGL 0,2 + clrw ax ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +; line 390 : +; line 391 : EI(); +$DGL 0,4 + ei ;[INF] 3, 4 +; line 392 : +; line 393 : DMAMK1 = 1; +$DGL 0,6 + set1 MK0H.4 ;[INF] 3, 2 +; line 394 : DEN1 = 0; +$DGL 0,7 + clr1 DRC1.7 ;[INF] 3, 2 +; line 395 : while( ( SSR02L & TSF0 ) != 0 ) +$DGL 0,8 +?L0052: + mov a,#040H ; 64 ;[INF] 2, 1 + and a,!SSR02L ;[INF] 3, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0053 ;[INF] 2, 4 +; line 396 : { +??bb00_int_dma1: +; line 397 : if( ++i == 0 ) // タイムアウト？ +$DGL 0,10 + incw hl ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + cmpw ax,hl ;[INF] 1, 1 + bnz $?L0052 ;[INF] 2, 4 +; line 398 : { +??bb01_int_dma1: +; line 399 : break; +??eb01_int_dma1: +; line 400 : } +??eb00_int_dma1: +; line 401 : } +?L0053: +; line 402 : +; line 403 : // iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪いの +; で展開 +; line 404 : { +??bb02_int_dma1: +; line 405 : ST0 = 0x0004; +$DGL 0,18 + movw ax,#04H ; 4 ;[INF] 3, 1 + movw !ST0,ax ;[INF] 3, 1 +; line 406 : SOE0 = 0; // 受信の時はもっと前に「も」設定 +; してる。(NACK出力) +$DGL 0,19 + clrw ax ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 407 : SO0 = 0x0000 | TAUS_MASK; // SCL +$DGL 0,20 + movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 408 : nop8(); +$DGL 0,21 + call !_nop8 ;[INF] 3, 3 +; line 409 : /* +; line 410 : NOP( ); +; line 411 : NOP( ); +; line 412 : NOP( ); +; line 413 : NOP( ); +; line 414 : #ifdef _OVERCLOCK_ +; line 415 : NOP( ); +; line 416 : NOP( ); +; line 417 : NOP( ); +; line 418 : NOP( ); +; line 419 : NOP( ); +; line 420 : #endif +; line 421 : */ +; line 422 : SO0 = 0x0400 | TAUS_MASK; // SCL +$DGL 0,35 + movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 423 : nop8(); +$DGL 0,36 + call !_nop8 ;[INF] 3, 3 +; line 424 : /* +; line 425 : NOP( ); +; line 426 : NOP( ); +; line 427 : NOP( ); +; line 428 : NOP( ); +; line 429 : #ifdef _OVERCLOCK_ +; line 430 : NOP( ); +; line 431 : NOP( ); +; line 432 : NOP( ); +; line 433 : NOP( ); +; line 434 : NOP( ); +; line 435 : #endif +; line 436 : */ +; line 437 : SO0 = 0x0404 | TAUS_MASK; +$DGL 0,50 + movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +??eb02_int_dma1: +; line 438 : } +; line 439 : IICMK10 = 1; +$DGL 0,52 + set1 MK1L.0 ;[INF] 3, 2 +; line 440 : iic_mcu_busy = 0; +$DGL 0,53 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 441 : } +$DGL 0,54 +??ef_int_dma1: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_dma1: +; line 442 : +; line 443 : +; line 444 : +; line 445 : /* ======================================================== +; line 446 : IIC MCUのバイト送出完了割り込み +; line 447 : ※DMA使用時は使用されません。 +; line 448 : 　他の割り込み処理中でDMAの割り込みにすぐ飛ばない場合、 +; line 449 : 　IIC割り込みのセットが間に合わず困ることがあります。 +; line 450 : ======================================================== */ +; line 451 : __interrupt void int_iic10( ) +; line 452 : { +_int_iic10: +$DGL 1,170 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_int_iic10: +; line 453 : EI(); +$DGL 0,2 + ei ;[INF] 3, 4 +; line 454 : if( iic_send_wo_dma_len != 0 ) +$DGL 0,3 + cmp0 !_iic_send_wo_dma_len ;[INF] 3, 1 + bz $?L0058 ;[INF] 2, 4 +; line 455 : { +??bb00_int_iic10: +; line 456 : SIO10 = *p_iic_send_wo_dma_dat; +$DGL 0,5 + movw de,!_p_iic_send_wo_dma_dat ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + mov SIO10,a ;[INF] 2, 1 +; line 457 : p_iic_send_wo_dma_dat++; +$DGL 0,6 + incw !_p_iic_send_wo_dma_dat ;[INF] 3, 2 +; line 458 : iic_send_wo_dma_len--; +$DGL 0,7 + dec !_iic_send_wo_dma_len ;[INF] 3, 2 +; line 459 : return; +$DGL 0,8 + br $?L0057 ;[INF] 2, 3 +??eb00_int_iic10: +; line 460 : } +?L0058: +; line 461 : +; line 462 : // 最後のバイト送信完了 +; line 463 : IICMK10 = 1; +$DGL 0,12 + set1 MK1L.0 ;[INF] 3, 2 +; line 464 : // iic_mcu_send_sp(); // ISR中で外の関数を呼ぶのは都合が悪い +; ので展開 +; line 465 : { +??bb01_int_iic10: +; line 466 : ST0 = 0x0004; +$DGL 0,15 + movw ax,#04H ; 4 ;[INF] 3, 1 + movw !ST0,ax ;[INF] 3, 1 +; line 467 : SOE0 = 0; // 受信の時はもっと前に「も」設定 +; してる。(NACK出力) +$DGL 0,16 + clrw ax ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 468 : SO0 = 0x0000 | TAUS_MASK; // SCL +$DGL 0,17 + movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 469 : nop8(); +$DGL 0,18 + call !_nop8 ;[INF] 3, 3 +; line 470 : /* +; line 471 : NOP( ); +; line 472 : NOP( ); +; line 473 : NOP( ); +; line 474 : NOP( ); +; line 475 : #ifdef _OVERCLOCK_ +; line 476 : NOP( ); +; line 477 : NOP( ); +; line 478 : NOP( ); +; line 479 : NOP( ); +; line 480 : NOP( ); +; line 481 : #endif +; line 482 : */ +; line 483 : SO0 = 0x0400 | TAUS_MASK; // SCL +$DGL 0,32 + movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 484 : nop8(); +$DGL 0,33 + call !_nop8 ;[INF] 3, 3 +; line 485 : /* +; line 486 : NOP( ); +; line 487 : NOP( ); +; line 488 : NOP( ); +; line 489 : NOP( ); +; line 490 : #ifdef _OVERCLOCK_ +; line 491 : NOP( ); +; line 492 : NOP( ); +; line 493 : NOP( ); +; line 494 : NOP( ); +; line 495 : NOP( ); +; line 496 : #endif +; line 497 : */ +; line 498 : SO0 = 0x0404 | TAUS_MASK; +$DGL 0,47 + movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +??eb01_int_iic10: +; line 499 : } +; line 500 : iic_mcu_wo_dma = 0; +$DGL 0,49 + clr1 _iic_mcu_wo_dma ;[INF] 3, 2 +; line 501 : iic_mcu_busy = 0; +$DGL 0,50 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 502 : } +?L0057: +$DGL 0,51 +??ef_int_iic10: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_iic10: +; line 503 : +; line 504 : +; line 505 : +; line 506 : /* ======================================================== +; line 507 : スレーブの呼び出し +; line 508 : 　スレーブアドレスを呼んで、ACKの確認。 +; line 509 : ACK　→　　　　　　　　　　　　　　　　　返：0 +; line 510 : 　NACK →　ストップコンディションを出す。　返：1 +; line 511 : ======================================================== */ +; line 512 : static err iic_mcu_call_slave( u8 slave ) +; line 513 : { + +ROM_CODE CSEG BASE +_iic_mcu_call_slave: +$DGL 1,184 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_iic_mcu_call_slave: +; line 514 : iic_mcu_send_st( ); +$DGL 0,2 + call !_iic_mcu_send_st ;[INF] 3, 3 +; line 515 : +; line 516 : // SIR02 = SSR02; // NAKエラーのフラグクリア +; line 517 : if( iic_mcu_send_a_byte( slave ) != ERR_SUCCESS ) +$DGL 0,5 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + call !_iic_mcu_send_a_byte ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + bz $?L0062 ;[INF] 2, 4 +; line 518 : { +??bb00_iic_mcu_call_slave: +; line 519 : iic_mcu_send_sp( ); +$DGL 0,7 + call !_iic_mcu_send_sp ;[INF] 3, 3 +; line 520 : return ( ERR_NAK ); // 指定のスレーブがいない / busy +$DGL 0,8 + onew bc ;[INF] 1, 1 + br $?L0061 ;[INF] 2, 3 +??eb00_iic_mcu_call_slave: +; line 521 : } +?L0062: +; line 522 : +; line 523 : return ( ERR_SUCCESS ); +$DGL 0,11 + clrw bc ;[INF] 1, 1 +; line 524 : } +?L0061: +$DGL 0,12 +??ef_iic_mcu_call_slave: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_call_slave: +; line 525 : +; line 526 : +; line 527 : +; line 528 : /* ======================================================== +; line 529 : ほんとに１バイト書くのみ +; line 530 : 書き終わるまで帰りません +; line 531 : ======================================================== */ +; line 532 : static err iic_mcu_send_a_byte( u8 dat ) +; line 533 : { +_iic_mcu_send_a_byte: +$DGL 1,195 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_iic_mcu_send_a_byte: +; line 534 : IICMK10 = 1; +$DGL 0,2 + set1 MK1L.0 ;[INF] 3, 2 +; line 535 : IICIF10 = 0; +$DGL 0,3 + clr1 IF1L.0 ;[INF] 3, 2 +; line 536 : SIO10 = dat; +$DGL 0,4 + mov a,l ;[INF] 1, 1 + mov SIO10,a ;[INF] 2, 1 +; line 537 : while( IICIF10 == 0 ) +$DGL 0,5 +?L0066: + bt IF1L.0,$?L0067 ;[INF] 4, 5 +; line 538 : { +??bb00_iic_mcu_send_a_byte: +; line 539 : NOP( ); +$DGL 0,7 + nop ;[INF] 1, 1 +??eb00_iic_mcu_send_a_byte: +; line 540 : } // 通信中 +$DGL 0,8 + br $?L0066 ;[INF] 2, 3 +?L0067: +; line 541 : if( SSR02 != 0 ) +$DGL 0,9 + clrw ax ;[INF] 1, 1 + cmpw ax,!SSR02 ;[INF] 3, 1 + bz $?L0068 ;[INF] 2, 4 +; line 542 : { +??bb01_iic_mcu_send_a_byte: +; line 543 : SIR02 = SSR02; +$DGL 0,11 + movw ax,!SSR02 ;[INF] 3, 1 + movw !SIR02,ax ;[INF] 3, 1 +; line 544 : return ( ERR_NAK ); +$DGL 0,12 + onew bc ;[INF] 1, 1 + br $?L0065 ;[INF] 2, 3 +??eb01_iic_mcu_send_a_byte: +; line 545 : } +?L0068: +; line 546 : return ( ERR_SUCCESS ); +$DGL 0,14 + clrw bc ;[INF] 1, 1 +; line 547 : } +?L0065: +$DGL 0,15 +??ef_iic_mcu_send_a_byte: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_iic_mcu_send_a_byte: +; line 548 : +; line 549 : +; line 550 : +; line 551 : /* ======================================================== +; line 552 : スタートコンディションを発行 +; line 553 : ソフトウェア制御 +; line 554 : ======================================================== */ +; line 555 : static void iic_mcu_send_st( ) +; line 556 : { +_iic_mcu_send_st: +$DGL 1,210 +??bf_iic_mcu_send_st: +; line 557 : SO0 &= ~0x0004; // SDA +$DGL 0,2 + movw ax,!SO0 ;[INF] 3, 1 + xch a,x ;[INF] 1, 1 + and a,#0FBH ; 251 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 558 : nop8(); +$DGL 0,3 + call !_nop8 ;[INF] 3, 3 +; line 559 : /* +; line 560 : NOP( ); +; line 561 : NOP( ); +; line 562 : NOP( ); +; line 563 : NOP( ); +; line 564 : #ifdef _OVERCLOCK_ +; line 565 : NOP( ); +; line 566 : NOP( ); +; line 567 : NOP( ); +; line 568 : NOP( ); +; line 569 : NOP( ); +; line 570 : #endif +; line 571 : */ +; line 572 : SO0 &= ~0x0400; // SCL +$DGL 0,17 + movw ax,!SO0 ;[INF] 3, 1 + and a,#0FBH ; 251 ;[INF] 2, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 573 : SOE0 = 0x0004; // ハード制御へ +$DGL 0,18 + movw ax,#04H ; 4 ;[INF] 3, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 574 : +; line 575 : SCR02 = TXE0 | 1 << SLC02 | 7 << DLS02; // 送信許可、デー +; タは８ビット単位 +$DGL 0,20 + movw ax,#08017H ; -32745 ;[INF] 3, 1 + movw !SCR02,ax ;[INF] 3, 1 +; line 576 : SS0 = 0x0004; // 通信待機 +$DGL 0,21 + call !bs_S0087 ;[INF] 3, 3 +; line 577 : } +$DGL 0,22 +??ef_iic_mcu_send_st: + ret ;[INF] 1, 6 +??ee_iic_mcu_send_st: +; line 578 : +; line 579 : +; line 580 : +; line 581 : /* ======================================================== +; line 582 : リスタート発行 +; line 583 : ======================================================== */ +; line 584 : static void iic_mcu_send_re_st( ) +; line 585 : { +_iic_mcu_send_re_st: +$DGL 1,216 +??bf_iic_mcu_send_re_st: +; line 586 : ST0 |= 0x0004; +$DGL 0,2 + movw ax,!ST0 ;[INF] 3, 1 + xch a,x ;[INF] 1, 1 + or a,#04H ; 4 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + movw !ST0,ax ;[INF] 3, 1 +; line 587 : SO0 |= 0x0400 | TAUS_MASK; // ( SDA = H ), SCL -> H +$DGL 0,3 + movw ax,!SO0 ;[INF] 3, 1 + or a,#0FH ; 15 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + or a,#0BH ; 11 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 588 : nop8(); +$DGL 0,4 + call !_nop8 ;[INF] 3, 3 +; line 589 : /* +; line 590 : NOP( ); +; line 591 : NOP( ); +; line 592 : NOP( ); +; line 593 : NOP( ); +; line 594 : #ifdef _OVERCLOCK_ +; line 595 : NOP( ); +; line 596 : NOP( ); +; line 597 : NOP( ); +; line 598 : NOP( ); +; line 599 : NOP( ); +; line 600 : #endif +; line 601 : */ +; line 602 : SOE0 &= ~0x0004; // ( SCL = H ), SDA -> L +$DGL 0,18 + movw ax,!SOE0 ;[INF] 3, 1 + xch a,x ;[INF] 1, 1 + and a,#0FBH ; 251 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 603 : nop8(); +$DGL 0,19 + call !_nop8 ;[INF] 3, 3 +; line 604 : /* +; line 605 : NOP( ); +; line 606 : NOP( ); +; line 607 : NOP( ); +; line 608 : NOP( ); +; line 609 : #ifdef _OVERCLOCK_ +; line 610 : NOP( ); +; line 611 : NOP( ); +; line 612 : NOP( ); +; line 613 : NOP( ); +; line 614 : NOP( ); +; line 615 : #endif +; line 616 : */ +; line 617 : iic_mcu_send_st( ); +$DGL 0,33 + br !_iic_mcu_send_st ;[INF] 3, 3 +??ef_iic_mcu_send_re_st: +??ee_iic_mcu_send_re_st: +; line 618 : } +; line 619 : +; line 620 : +; line 621 : +; line 622 : /* ======================================================== +; line 623 : ストップコンディション発行 +; line 624 : この前に、「最後のバイトの送受信」の時に前準備が必要です。 +; line 625 : ======================================================== */ +; line 626 : static void iic_mcu_send_sp( ) +; line 627 : { +_iic_mcu_send_sp: +$DGL 1,222 +??bf_iic_mcu_send_sp: +; line 628 : ST0 = 0x0004; +$DGL 0,2 + call !bs_S0086 ;[INF] 3, 3 +; line 629 : SOE0 = 0; // 受信の時はもっと前に「も」設定 +; してる。(NACK出力) +$DGL 0,3 + clrw ax ;[INF] 1, 1 + movw !SOE0,ax ;[INF] 3, 1 +; line 630 : SO0 = 0x0000 | TAUS_MASK; // SCL +$DGL 0,4 + movw ax,#0B0BH ; 2827 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 631 : nop8(); +$DGL 0,5 + call !_nop8 ;[INF] 3, 3 +; line 632 : /* +; line 633 : NOP( ); +; line 634 : NOP( ); +; line 635 : NOP( ); +; line 636 : NOP( ); +; line 637 : #ifdef _OVERCLOCK_ +; line 638 : NOP( ); +; line 639 : NOP( ); +; line 640 : NOP( ); +; line 641 : NOP( ); +; line 642 : NOP( ); +; line 643 : #endif +; line 644 : */ +; line 645 : SO0 = 0x0400 | TAUS_MASK; // SCL +$DGL 0,19 + movw ax,#0F0BH ; 3851 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 646 : nop8(); +$DGL 0,20 + call !_nop8 ;[INF] 3, 3 +; line 647 : /* +; line 648 : NOP( ); +; line 649 : NOP( ); +; line 650 : NOP( ); +; line 651 : NOP( ); +; line 652 : #ifdef _OVERCLOCK_ +; line 653 : NOP( ); +; line 654 : NOP( ); +; line 655 : NOP( ); +; line 656 : NOP( ); +; line 657 : NOP( ); +; line 658 : #endif +; line 659 : */ +; line 660 : SO0 = 0x0404 | TAUS_MASK; +$DGL 0,34 + movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 661 : } +$DGL 0,35 +??ef_iic_mcu_send_sp: + ret ;[INF] 1, 6 +??ee_iic_mcu_send_sp: +; line 662 : +; line 663 : +; line 664 : +; line 665 : +; line 666 : /* ======================================================== +; line 667 : ペリフェラルモジュールの初期化 +; line 668 : ======================================================== */ +; line 669 : void iic_mcu_start( ) +; line 670 : { +_iic_mcu_start: +$DGL 1,228 +??bf_iic_mcu_start: +; line 671 : DST1 = 0; +$DGL 0,2 + clr1 DRC1.0 ;[INF] 3, 2 +; line 672 : NOP( ); // 2clkもしくは、DSTn==0をポーリ +; ング +$DGL 0,3 + nop ;[INF] 1, 1 +; line 673 : NOP( ); +$DGL 0,4 + nop ;[INF] 1, 1 +; line 674 : DEN1 = 0; +$DGL 0,5 + clr1 DRC1.7 ;[INF] 3, 2 +; line 675 : I2C_PU_on(); +$DGL 0,6 +??bb00_iic_mcu_start: + set1 PM5.3 ;[INF] 3, 2 + set1 PM3.3 ;[INF] 3, 2 + or P14,#03H ; 3 ;[INF] 3, 2 + set1 P5.3 ;[INF] 3, 2 + clr1 PM5.3 ;[INF] 3, 2 + set1 P3.3 ;[INF] 3, 2 + clr1 PM3.3 ;[INF] 3, 2 +??eb00_iic_mcu_start: +; line 676 : SAU0EN = 1; +$DGL 0,7 + set1 !PER0.2 ;[INF] 4, 2 +; line 677 : nop8(); +$DGL 0,8 + call !_nop8 ;[INF] 3, 3 +; line 678 : /* +; line 679 : NOP( ); +; line 680 : NOP( ); +; line 681 : NOP( ); +; line 682 : NOP( ); +; line 683 : #ifdef _OVERCLOCK_ +; line 684 : NOP( ); +; line 685 : NOP( ); +; line 686 : NOP( ); +; line 687 : NOP( ); +; line 688 : NOP( ); +; line 689 : #endif +; line 690 : */ +; line 691 : SPS0 = 0x0000; // シリアルユニットのクロック０。 +; (8M/2)/1 +$DGL 0,22 + clrw ax ;[INF] 1, 1 + movw !SPS0,ax ;[INF] 3, 1 +; line 692 : SMR02 = bSMR0n_FIXEDBIT | bMD0n2; // 簡易I2Cに設定 +$DGL 0,23 + mov x,#024H ; 36 ;[INF] 2, 1 + movw !SMR02,ax ;[INF] 3, 1 +; line 693 : #ifdef _OVERCLOCK_ +; line 694 : SDR02 = 12 << 9; // ボーレート設定 (8M/2)/1/(x+1 +; )/2 +$DGL 0,25 + movw SDR02,#01800H ; 6144 ;[INF] 4, 1 +; line 695 : #else +; line 696 : SDR02 = 5 << 9; // ボーレート設定 (8M/2)/1/(x+1) +; /2 +; line 697 : #endif +; line 698 : +; line 699 : SO0 = 0x0404 | TAUS_MASK; // 最初はHH +$DGL 0,30 + movw ax,#0F0FH ; 3855 ;[INF] 3, 1 + movw !SO0,ax ;[INF] 3, 1 +; line 700 : iic_mcu_busy = 0; +$DGL 0,31 + clr1 _iic_mcu_busy ;[INF] 3, 2 +; line 701 : iic_mcu_wo_dma = 0; +$DGL 0,32 + clr1 _iic_mcu_wo_dma ;[INF] 3, 2 +; line 702 : +; line 703 : +; line 704 : // バスのリセット +; line 705 : IICIF10 = 0; +$DGL 0,36 + clr1 IF1L.0 ;[INF] 3, 2 +; line 706 : IICMK10 = 1; +$DGL 0,37 + set1 MK1L.0 ;[INF] 3, 2 +; line 707 : +; line 708 : iic_mcu_send_st(); +$DGL 0,39 + call !_iic_mcu_send_st ;[INF] 3, 3 +; line 709 : +; line 710 : SIO10 = 0xFF; +$DGL 0,41 + mov SIO10,#0FFH ; 255 ;[INF] 3, 1 +; line 711 : while( IICIF10 == 0 ){} // 通信中 +$DGL 0,42 +?L0078: + bt IF1L.0,$?L0079 ;[INF] 4, 5 +??bb01_iic_mcu_start: +??eb01_iic_mcu_start: + br $?L0078 ;[INF] 2, 3 +?L0079: +; line 712 : iic_mcu_send_sp(); +$DGL 0,43 + call !_iic_mcu_send_sp ;[INF] 3, 3 +; line 713 : +; line 714 : SIR02 = SSR02; +$DGL 0,45 + movw ax,!SSR02 ;[INF] 3, 1 + movw !SIR02,ax ;[INF] 3, 1 +; line 715 : +; line 716 : iic_mcu_initialized = 1; +$DGL 0,47 + set1 _iic_mcu_initialized ;[INF] 3, 2 +; line 717 : } +$DGL 0,48 +??ef_iic_mcu_start: + ret ;[INF] 1, 6 +??ee_iic_mcu_start: +; line 718 : +; line 719 : +; line 720 : +; line 721 : /* ======================================================== +; line 722 : モジュールの停止 +; line 723 : 再度使うときは初期化が必要 +; line 724 : ======================================================== */ +; line 725 : void iic_mcu_stop( ) +; line 726 : { +_iic_mcu_stop: +$DGL 1,242 +??bf_iic_mcu_stop: +; line 727 : while( iic_mcu_busy ) +$DGL 0,2 +?L0082: + bf _iic_mcu_busy,$?L0083 ;[INF] 4, 5 +; line 728 : {; +??bb00_iic_mcu_stop: +??eb00_iic_mcu_stop: +; line 729 : } // DMA動作中はもう少し待つ +$DGL 0,4 + br $?L0082 ;[INF] 2, 3 +?L0083: +; line 730 : iic_mcu_send_re_st( ); // SCL,SDAをLLにする +$DGL 0,5 + call !_iic_mcu_send_re_st ;[INF] 3, 3 +; line 731 : I2C_PU_off(); +$DGL 0,6 +??bb01_iic_mcu_stop: + set1 PM5.3 ;[INF] 3, 2 + set1 PM3.3 ;[INF] 3, 2 + and P14,#0FCH ; 252 ;[INF] 3, 2 + clr1 P5.3 ;[INF] 3, 2 + clr1 PM5.3 ;[INF] 3, 2 + clr1 P3.3 ;[INF] 3, 2 + clr1 PM3.3 ;[INF] 3, 2 +??eb01_iic_mcu_stop: +; line 732 : SAU0EN = 0; +$DGL 0,7 + clr1 !PER0.2 ;[INF] 4, 2 +; line 733 : iic_mcu_initialized = 0; +$DGL 0,8 + clr1 _iic_mcu_initialized ;[INF] 3, 2 +; line 734 : } +$DGL 0,9 +??ef_iic_mcu_stop: + ret ;[INF] 1, 6 +??ee_iic_mcu_stop: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c +; +; $FUNC nop8(76) +; void=(void) +; CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes +; +; $FUNC iic_mcu_read_a_byte(87) +; bc=(unsigned char SLA:x, unsigned char adrs:[sp+4]) +; CODE SIZE= 111 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 10 bytes +; +; $CALL iic_mcu_start(93) +; void=(void) +; +; $CALL iic_mcu_call_slave(110) +; bc=(int:ax) +; +; $CALL iic_mcu_send_a_byte(118) +; bc=(int:ax) +; +; $CALL iic_mcu_send_re_st(122) +; void=(void) +; +; $CALL iic_mcu_send_a_byte(123) +; bc=(int:ax) +; +; $CALL iic_mcu_send_sp(139) +; void=(void) +; +; $FUNC iic_mcu_read(158) +; bc=(unsigned char slave:x, unsigned char adrs:[sp+4], +; unsigned char len:[sp+6], pointer dest:[sp+8]) +; CODE SIZE= 111 bytes, CLOCK_SIZE= 141 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_start(165) +; void=(void) +; +; $CALL iic_mcu_call_slave(188) +; bc=(int:ax) +; +; $CALL iic_mcu_send_a_byte(195) +; bc=(int:ax) +; +; $CALL iic_mcu_send_re_st(199) +; void=(void) +; +; $CALL iic_mcu_send_a_byte(200) +; bc=(int:ax) +; +; $CALL iic_mcu_send_sp(225) +; void=(void) +; +; $FUNC iic_mcu_write_a_byte(242) +; bc=(unsigned char SLA:x, unsigned char adrs:[sp+4], +; unsigned char dat:[sp+6]) +; CODE SIZE= 56 bytes, CLOCK_SIZE= 79 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_start(247) +; void=(void) +; +; $CALL iic_mcu_call_slave(266) +; bc=(int:ax) +; +; $CALL iic_mcu_send_a_byte(271) +; bc=(int:ax) +; +; $CALL iic_mcu_send_a_byte(272) +; bc=(int:ax) +; +; $CALL iic_mcu_send_sp(273) +; void=(void) +; +; $FUNC iic_mcu_write(297) +; bc=(unsigned char slave:x, unsigned char adrs:[sp+4], +; unsigned char len:[sp+6], pointer src:[sp+8]) +; CODE SIZE= 127 bytes, CLOCK_SIZE= 121 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_start(303) +; void=(void) +; +; $CALL iic_mcu_call_slave(327) +; bc=(int:ax) +; +; $FUNC int_dma1(388) +; void=(void) +; CODE SIZE= 108 bytes, CLOCK_SIZE= 86 clocks, STACK_SIZE= 26 bytes +; +; $CALL nop8(408) +; void=(void) +; +; $CALL nop8(423) +; void=(void) +; +; $FUNC int_iic10(452) +; void=(void) +; CODE SIZE= 109 bytes, CLOCK_SIZE= 83 clocks, STACK_SIZE= 26 bytes +; +; $CALL nop8(469) +; void=(void) +; +; $CALL nop8(484) +; void=(void) +; +; $FUNC iic_mcu_call_slave(513) +; bc=(unsigned char slave:x) +; CODE SIZE= 22 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes +; +; $CALL iic_mcu_send_st(514) +; void=(void) +; +; $CALL iic_mcu_send_a_byte(517) +; bc=(int:ax) +; +; $CALL iic_mcu_send_sp(519) +; void=(void) +; +; $FUNC iic_mcu_send_a_byte(533) +; bc=(unsigned char dat:x) +; CODE SIZE= 36 bytes, CLOCK_SIZE= 37 clocks, STACK_SIZE= 2 bytes +; +; $FUNC iic_mcu_send_st(556) +; void=(void) +; CODE SIZE= 37 bytes, CLOCK_SIZE= 32 clocks, STACK_SIZE= 4 bytes +; +; $CALL nop8(558) +; void=(void) +; +; $FUNC iic_mcu_send_re_st(585) +; void=(void) +; CODE SIZE= 41 bytes, CLOCK_SIZE= 25 clocks, STACK_SIZE= 4 bytes +; +; $CALL nop8(588) +; void=(void) +; +; $CALL nop8(603) +; void=(void) +; +; $CALL iic_mcu_send_st(617) +; void=(void) +; +; $FUNC iic_mcu_send_sp(627) +; void=(void) +; CODE SIZE= 32 bytes, CLOCK_SIZE= 31 clocks, STACK_SIZE= 4 bytes +; +; $CALL nop8(631) +; void=(void) +; +; $CALL nop8(646) +; void=(void) +; +; $FUNC iic_mcu_start(670) +; void=(void) +; CODE SIZE= 92 bytes, CLOCK_SIZE= 65 clocks, STACK_SIZE= 4 bytes +; +; $CALL nop8(677) +; void=(void) +; +; $CALL iic_mcu_send_st(708) +; void=(void) +; +; $CALL iic_mcu_send_sp(712) +; void=(void) +; +; $FUNC iic_mcu_stop(726) +; void=(void) +; CODE SIZE= 38 bytes, CLOCK_SIZE= 35 clocks, STACK_SIZE= 4 bytes +; +; $CALL iic_mcu_send_re_st(730) +; void=(void) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/i2c_twl.asm b/branches/0.10(X3)/inter_asm/i2c_twl.asm new file mode 100644 index 0000000..da3ebe3 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/i2c_twl.asm @@ -0,0 +1,754 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c +; In-file : i2c_twl.c +; Asm-file : inter_asm\i2c_twl.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 06FH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, i2c_twl.c +$DGS MOD_NAM, i2c_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _int_iic_twl, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H +$DGS BEG_FUN, ??bf_int_iic_twl, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 052H, 01CH, 01BH +$DGS AUT_VAR, _temp, 05H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _tot, 02H, 0FFFFH, 0DH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 01DH +$DGS BEG_BLK, ??bb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 01FH +$DGS BEG_BLK, ??bb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 023H +$DGS END_BLK, ??eb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 02BH +$DGS END_BLK, ??eb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS END_BLK, ??eb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS END_BLK, ??eb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01EH, 00H, 02FH +$DGS AUT_VAR, _my_iics, 01H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 01FH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 022H, 00H, 033H +$DGS END_BLK, ??eb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 025H +$DGS BEG_BLK, ??bb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 027H, 00H, 035H +$DGS BEG_BLK, ??bb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 037H +$DGS BEG_BLK, ??bb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 039H +$DGS BEG_BLK, ??bb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 03DH +$DGS END_BLK, ??eb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS BEG_BLK, ??bb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 045H +$DGS END_BLK, ??eb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS END_BLK, ??eb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS END_BLK, ??eb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS BEG_BLK, ??bb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02FH, 00H, 049H +$DGS END_BLK, ??eb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 032H +$DGS BEG_BLK, ??bb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 04BH +$DGS BEG_BLK, ??bb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 04DH +$DGS BEG_BLK, ??bb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 051H +$DGS END_BLK, ??eb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS BEG_BLK, ??bb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 05BH +$DGS END_BLK, ??eb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS END_BLK, ??eb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS END_BLK, ??eb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS END_BLK, ??eb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03AH +$DGS BEG_BLK, ??bb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03CH, 00H, 00H +$DGS END_BLK, ??eb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 046H +$DGS END_BLK, ??eb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 047H +$DGS END_FUN, ??ef_int_iic_twl, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 048H +$DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H +$DGS BEG_FUN, ??bf_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09FH, 00H, 069H +$DGS END_FUN, ??ef_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 024H +$DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 06FH, 00H, 00H +$DGS BEG_FUN, ??bf_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0C8H, 00H, 06FH +$DGS END_FUN, ??ef_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _vreg_adrs, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _pre_dat, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _tot, U, U, 0DH, 026H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _@RTARG0 + EXTRN _adrs_table_twl_ext2int + EXTRN _vreg_twl_read + EXTRN _vreg_twl_write + PUBLIC _vreg_adrs + PUBLIC _pre_dat + PUBLIC _tot + PUBLIC _int_iic_twl + PUBLIC _IIC_twl_Init + PUBLIC _IIC_twl_Stop + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP +_vreg_adrs: DS (1) +_pre_dat: DS (1) +_tot: DS (2) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : #pragma sfr /* 特殊機能レジスタ使用 */ +; line 2 : +; line 3 : +; line 4 : +; line 5 : /*============================================================== +; ==============*/ +; line 6 : #include "incs.h" +; line 7 : #include "i2c_twl_defs.h" +; line 8 : +; line 9 : +; line 10 : extern u8 vreg_twl[]; +; line 11 : +; line 12 : #ifdef _MCU_BSR_ +; line 13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_ +; line 14 : +; line 15 : // ワーキングモデルはI2Cが逆 +; line 16 : #define ACKD ACKD0 +; line 17 : #define ACKE ACKE0 +; line 18 : #define COI COI0 +; line 19 : #define IICAEN IICA0EN +; line 20 : #define IICRSV IICRSV0 +; line 21 : #define IICA IICA0 +; line 22 : #define IICAIF IICAIF0 +; line 23 : #define IICAMK IICAMK0 +; line 24 : #define IICAPR0 IICAPR00 +; line 25 : #define IICAPR1 IICAPR10 +; line 26 : #define IICCTL0 IICCTL00 +; line 27 : #define IICE IICE0 +; line 28 : #define IICF IICF0 +; line 29 : #define IICS IICS0 +; line 30 : #define IICWH IICWH0 +; line 31 : #define IICWL IICWL0 +; line 32 : #define LREL LREL0 +; line 33 : #define SPD SPD0 +; line 34 : #define SPIE SPIE0 +; line 35 : #define STCEN STCEN0 +; line 36 : #define STD STD0 +; line 37 : #define SVA SVA0 +; line 38 : #define WREL WREL0 +; line 39 : #define WTIM WTIM0 +; line 40 : #define SMC SMC0 +; line 41 : +; line 42 : #endif +; line 43 : +; line 44 : #ifndef _MCU_BSR_ +; line 45 : +; line 46 : // ke3の時はダミー関数 +; line 47 : void IIC_twl_Stop( void ) +; line 48 : { +; line 49 : } +; line 50 : void IIC_twl_Init( void ) +; line 51 : { +; line 52 : } +; line 53 : #else +; line 54 : +; line 55 : +; line 56 : /*============================================================== +; ==============*/ +; line 57 : u8 vreg_adrs; +; line 58 : u8 pre_dat; +; line 59 : +; line 60 : +; line 61 : u16 tot; +; line 62 : +; line 63 : +; line 64 : // 注！　↓はマクロなので、returnはメインループに戻ります。 +; line 65 : #define wait_next { \ +; line 66 : tot = 0; \ +; line 67 : while( IICAIF != 1 ){ \ +; line 68 : if( SPD ){ \ +; line 69 : LREL = 1; \ +; line 70 : return; \ +; line 71 : } \ +; line 72 : tot++; \ +; line 73 : if( tot == 0 ){ \ +; line 74 : LREL = 1; \ +; line 75 : return; \ +; line 76 : } \ +; line 77 : } \ +; line 78 : } +; line 79 : +; line 80 : +; line 81 : __interrupt void int_iic_twl( ) +; line 82 : { + +@@BASE CSEG BASE +_int_iic_twl: +$DGL 1,21 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_int_iic_twl: +; line 83 : u8 temp; +; line 84 : u16 tot; +; line 85 : +; line 86 : // WDT_Restart(); +; line 87 : // フラグ１回目 スレーブアドレス,R/W +; line 88 : /* COI != 1 なら、割り込みはいらない +; line 89 : if( COI != 1 ){ // 被呼び出し？ +; line 90 : LREL = 1; // 呼ばれたのは他のID +; line 91 : return; +; line 92 : }else{ +; line 93 : ACKE0 = 1; // 自動でackを返すようにする +; line 94 : WREL = 1; // ウェイト解除して次のバイトを待つ +; line 95 : } +; line 96 : */ +; line 97 : WREL = 1; // ウェイト解除して次のバイトを待 +; つ +$DGL 0,16 + set1 !IICCTL00.5 ;[INF] 4, 2 +; line 98 : wait_next; // １バイト受信完了を待つ +$DGL 0,17 +??bb00_int_iic_twl: + clrw ax ;[INF] 1, 1 + movw [hl+2],ax ; tot ;[INF] 2, 1 +?L0003: + bt IF1L.3,$?L0004 ;[INF] 4, 5 +??bb01_int_iic_twl: + bf IICS0.0,$?L0005 ;[INF] 4, 5 +??bb02_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br !?L0010 ;[INF] 3, 3 +??eb02_int_iic_twl: +?L0005: + incw [hl+2] ; tot ;[INF] 3, 2 + clrw ax ;[INF] 1, 1 + cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + bnz $?L0003 ;[INF] 2, 4 +??bb03_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br !?L0010 ;[INF] 3, 3 +??eb03_int_iic_twl: +??eb01_int_iic_twl: +?L0004: +??eb00_int_iic_twl: +; line 99 : +; line 100 : // ２回目 R/W レジスタアドレス +; line 101 : temp = IICA; +$DGL 0,20 + mov a,IICA0 ;[INF] 2, 1 + mov [hl+5],a ; temp ;[INF] 2, 1 +; line 102 : IICAIF = 0; +$DGL 0,21 + clr1 IF1L.3 ;[INF] 3, 2 +; line 103 : WREL = 1; +$DGL 0,22 + set1 !IICCTL00.5 ;[INF] 4, 2 +; line 104 : +; line 105 : vreg_adrs = adrs_table_twl_ext2int( temp ); +$DGL 0,24 + mov a,[hl+5] ; temp ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + call !_adrs_table_twl_ext2int ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_vreg_adrs,a ;[INF] 3, 1 +; line 106 : +; line 107 : // ３回目 +; line 108 : // スタートコンディションか、データ受信完了フラグ待ち +; line 109 : +; line 110 : while( 1 ) +?L0009: +; line 111 : { +??bb04_int_iic_twl: +; line 112 : u8 my_iics = IICS; +$DGL 0,31 + mov a,IICS0 ;[INF] 2, 1 + mov [hl+1],a ; my_iics ;[INF] 2, 1 +; line 113 : +; line 114 : if( my_iics & 0x01 ) // SPD +$DGL 0,33 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0011 ;[INF] 2, 4 +; line 115 : { // 強制終了 +??bb05_int_iic_twl: +; line 116 : LREL = 1; +$DGL 0,35 + set1 !IICCTL00.6 ;[INF] 4, 2 +; line 117 : return; +$DGL 0,36 + br !?L0010 ;[INF] 3, 3 +??eb05_int_iic_twl: +; line 118 : } +?L0011: +; line 119 : else if( my_iics & 0x02 ) // ( STD && !SPD ) +$DGL 0,38 + mov a,[hl+1] ; my_iics ;[INF] 2, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0013 ;[INF] 2, 4 +; line 120 : { +??bb06_int_iic_twl: +; line 121 : // 送信 // (スタートコンディション検出) +; line 122 : pre_dat = vreg_twl_read( vreg_adrs ); // mcu内 +; 部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除 +$DGL 0,41 + mov x,!_vreg_adrs ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + call !_vreg_twl_read ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_pre_dat,a ;[INF] 3, 1 +; line 123 : +; line 124 : // 自局をRで呼ばれるのを待つ +; line 125 : wait_next; +$DGL 0,44 +??bb07_int_iic_twl: + clrw ax ;[INF] 1, 1 + movw [hl+2],ax ; tot ;[INF] 2, 1 +?L0015: + bt IF1L.3,$?L0016 ;[INF] 4, 5 +??bb08_int_iic_twl: + bf IICS0.0,$?L0017 ;[INF] 4, 5 +??bb09_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br $?L0010 ;[INF] 2, 3 +??eb09_int_iic_twl: +?L0017: + incw [hl+2] ; tot ;[INF] 3, 2 + clrw ax ;[INF] 1, 1 + cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + bnz $?L0015 ;[INF] 2, 4 +??bb0A_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br $?L0010 ;[INF] 2, 3 +??eb0A_int_iic_twl: +; line 126 : IICAIF = 0; +$DGL 0,45 +??eb08_int_iic_twl: +?L0016: +??eb07_int_iic_twl: + clr1 IF1L.3 ;[INF] 3, 2 +; line 127 : if( COI != 1 ) +$DGL 0,46 + bt IICS0.4,$?L0021 ;[INF] 4, 5 +; line 128 : { // 被呼び出し？ +??bb0B_int_iic_twl: +; line 129 : LREL = 1; // 呼ばれたのは他のID（あれ？） +$DGL 0,48 + set1 !IICCTL00.6 ;[INF] 4, 2 +; line 130 : return; +$DGL 0,49 + br $?L0010 ;[INF] 2, 3 +??eb0B_int_iic_twl: +; line 131 : } +?L0021: +; line 132 : IICA = pre_dat; // データを送る。ウェイトも解除さ +; れる。 +$DGL 0,51 + mov a,!_pre_dat ;[INF] 3, 1 + mov IICA0,a ;[INF] 2, 1 +; line 133 : +; line 134 : wait_next; +$DGL 0,53 +??bb0C_int_iic_twl: + clrw ax ;[INF] 1, 1 + movw [hl+2],ax ; tot ;[INF] 2, 1 +?L0023: + bt IF1L.3,$?L0024 ;[INF] 4, 5 +??bb0D_int_iic_twl: + bf IICS0.0,$?L0025 ;[INF] 4, 5 +??bb0E_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br $?L0010 ;[INF] 2, 3 +??eb0E_int_iic_twl: +?L0025: + incw [hl+2] ; tot ;[INF] 3, 2 + clrw ax ;[INF] 1, 1 + cmpw ax,[hl+2] ; tot ;[INF] 3, 1 + bnz $?L0023 ;[INF] 2, 4 +??bb0F_int_iic_twl: + set1 !IICCTL00.6 ;[INF] 4, 2 + br $?L0010 ;[INF] 2, 3 +??eb0F_int_iic_twl: +; line 135 : // ４回目。(送信データ後の、ACK/NACK後)　どうしても発 +; 生してしまう。 +??eb0D_int_iic_twl: +?L0024: +??eb0C_int_iic_twl: +; line 136 : IICAIF = 0; // おしまい +$DGL 0,55 + clr1 IF1L.3 ;[INF] 3, 2 +; line 137 : LREL = 1; +$DGL 0,56 + set1 !IICCTL00.6 ;[INF] 4, 2 +; line 138 : return; +$DGL 0,57 + br $?L0010 ;[INF] 2, 3 +??eb06_int_iic_twl: +; line 139 : } +?L0013: +; line 140 : else if( IICAIF && (( my_iics & 0x03 ) == 0 )) // !STD +; && !SPD ) +$DGL 0,59 + bf IF1L.3,$?L0029 ;[INF] 4, 5 + mov a,[hl+1] ; my_iics ;[INF] 2, 1 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0029 ;[INF] 2, 4 +; line 141 : { +??bb10_int_iic_twl: +; line 142 : // 受信 // +; line 143 : IICAIF = 0; +$DGL 0,62 + clr1 IF1L.3 ;[INF] 3, 2 +; line 144 : temp = IICA; +$DGL 0,63 + mov a,IICA0 ;[INF] 2, 1 + mov [hl+5],a ; temp ;[INF] 2, 1 +; line 145 : WREL = 1; +$DGL 0,64 + set1 !IICCTL00.5 ;[INF] 4, 2 +; line 146 : +; line 147 : // 通常アクセス(ライト) // +; line 148 : LREL = 1; // スタートコンディション待ちへ( +; 連続書き込み未対応のため) +$DGL 0,67 + set1 !IICCTL00.6 ;[INF] 4, 2 +; line 149 : vreg_twl_write( vreg_adrs, temp ); +$DGL 0,68 + mov a,[hl+5] ; temp ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,!_vreg_adrs ;[INF] 3, 1 + call !_vreg_twl_write ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 150 : return; // 受信おしまい // +$DGL 0,69 + br $?L0010 ;[INF] 2, 3 +??eb10_int_iic_twl: +; line 151 : } +?L0029: +??eb04_int_iic_twl: +; line 152 : } +$DGL 0,71 + br !?L0009 ;[INF] 3, 3 +?L0010: +; line 153 : } +$DGL 0,72 +??ef_int_iic_twl: + addw sp,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_iic_twl: +; line 154 : +; line 155 : +; line 156 : +; line 157 : /*****************************************************/ +; line 158 : void IIC_twl_Init( void ) +; line 159 : { + +ROM_CODE CSEG BASE +_IIC_twl_Init: +$DGL 1,99 +??bf_IIC_twl_Init: +; line 160 : +; line 161 : IICAEN = 1; +$DGL 0,3 + set1 !PER0.4 ;[INF] 4, 2 +; line 162 : +; line 163 : IICE = 0; /* IICA disable */ +$DGL 0,5 + clr1 !IICCTL00.7 ;[INF] 4, 2 +; line 164 : +; line 165 : IICAMK = 1; /* INTIICA disable */ +$DGL 0,7 + set1 MK1L.3 ;[INF] 3, 2 +; line 166 : IICAIF = 0; /* clear INTIICA interrupt flag +; */ +$DGL 0,8 + clr1 IF1L.3 ;[INF] 3, 2 +; line 167 : +; line 168 : IICAPR0 = 0; /* set INTIICA high priority */ +$DGL 0,10 + clr1 PR01L.3 ;[INF] 3, 2 +; line 169 : IICAPR1 = 0; /* set INTIICA high priority */ +$DGL 0,11 + clr1 PR11L.3 ;[INF] 3, 2 +; line 170 : P20 &= ~0x3; +$DGL 0,12 + mov a,!P20 ;[INF] 3, 1 + and a,#0FCH ; 252 ;[INF] 2, 1 + mov !P20,a ;[INF] 3, 1 +; line 171 : +; line 172 : SVA = IIC_T_SLAVEADDRESS; +$DGL 0,14 + mov !SVA0,#04AH ; 74 ;[INF] 4, 1 +; line 173 : IICF = 0x01; +$DGL 0,15 + oneb !IICF0 ;[INF] 3, 1 +; line 174 : +; line 175 : STCEN = 1; // リスタートの許可 +$DGL 0,17 + set1 IICF0.1 ;[INF] 3, 2 +; line 176 : IICRSV = 1; // 通信予約をさせない:スレーブに +; 徹する +$DGL 0,18 + set1 IICF0.0 ;[INF] 3, 2 +; line 177 : +; line 178 : SPIE = 0; // ストップコンディションでの割り +; 込みを禁止 +$DGL 0,20 + clr1 !IICCTL00.4 ;[INF] 4, 2 +; line 179 : WTIM = 1; // 自動でACKを返した後clkをLに固 +; 定する +$DGL 0,21 + set1 !IICCTL00.3 ;[INF] 4, 2 +; line 180 : ACKE = 1; // ダメCPUは無視して次の通信をは +; じめるかもしれないんで早くclkを開放しないといけない +$DGL 0,22 + set1 !IICCTL00.2 ;[INF] 4, 2 +; line 181 : +; line 182 : IICWH = 5; +$DGL 0,24 + mov !IICWH0,#05H ; 5 ;[INF] 4, 1 +; line 183 : IICWL = 10; // L期間の長さ（？） +$DGL 0,25 + mov !IICWL0,#0AH ; 10 ;[INF] 4, 1 +; line 184 : +; line 185 : SMC = 1; +$DGL 0,27 + set1 !IICCTL10.3 ;[INF] 4, 2 +; line 186 : +; line 187 : IICAMK = 0; // 割り込みを許可 +$DGL 0,29 + clr1 MK1L.3 ;[INF] 3, 2 +; line 188 : +; line 189 : IICE = 1; +$DGL 0,31 + set1 !IICCTL00.7 ;[INF] 4, 2 +; line 190 : +; line 191 : PM20 &= ~0x3; /* set clock pin for IICA */ +$DGL 0,33 + mov a,!PM20 ;[INF] 3, 1 + and a,#0FCH ; 252 ;[INF] 2, 1 + mov !PM20,a ;[INF] 3, 1 +; line 192 : +; line 193 : LREL = 1; +$DGL 0,35 + set1 !IICCTL00.6 ;[INF] 4, 2 +; line 194 : } +$DGL 0,36 +??ef_IIC_twl_Init: + ret ;[INF] 1, 6 +??ee_IIC_twl_Init: +; line 195 : +; line 196 : +; line 197 : +; line 198 : //************************************************************** +; ************** +; line 199 : void IIC_twl_Stop( void ) +; line 200 : { +_IIC_twl_Stop: +$DGL 1,105 +??bf_IIC_twl_Stop: +; line 201 : IICE = 0; /* IICA disable */ +$DGL 0,2 + clr1 !IICCTL00.7 ;[INF] 4, 2 +; line 202 : IICAEN = 0; +$DGL 0,3 + clr1 !PER0.4 ;[INF] 4, 2 +; line 203 : } +$DGL 0,4 +??ef_IIC_twl_Stop: + ret ;[INF] 1, 6 +??ee_IIC_twl_Stop: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c +; +; $FUNC int_iic_twl(82) +; void=(void) +; CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes +; +; $CALL adrs_table_twl_ext2int(105) +; bc=(int:ax) +; +; $CALL vreg_twl_read(122) +; bc=(int:ax) +; +; $CALL vreg_twl_write(149) +; void=(int:ax, int:[sp+4]) +; +; $FUNC IIC_twl_Init(159) +; void=(void) +; CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes +; +; $FUNC IIC_twl_Stop(200) +; void=(void) +; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/ini_VECT.asm b/branches/0.10(X3)/inter_asm/ini_VECT.asm new file mode 100644 index 0000000..407b8a7 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/ini_VECT.asm @@ -0,0 +1,1175 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 May 2010 Time:20:03:34 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no ini_VECT.c +; In-file : ini_VECT.c +; Asm-file : inter_asm\ini_VECT.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0115H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, ini_VECT.c +$DGS MOD_NAM, ini_VECT, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT10, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT1C, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT24, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT2A, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT34, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT4A, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT5A, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@VECT62, U, U, 00H, 078H, 00H, 00H +$DGS GLV_SYM, _fn_intwdti, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 025H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intwdti, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 04BH, 00H, 01FH +$DGS BEG_BLK, ??bb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intwdti, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intwdti, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intlvi, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 02FH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intlvi, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 052H, 00H, 029H +$DGS BEG_BLK, ??bb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intlvi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intlvi, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intp0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 039H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intp0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 059H, 00H, 033H +$DGS BEG_BLK, ??bb00_fn_intp0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intp0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intp0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intp1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 043H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intp1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 061H, 00H, 03DH +$DGS BEG_BLK, ??bb00_fn_intp1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intp1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intp1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intp2, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 04DH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intp2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 068H, 00H, 047H +$DGS BEG_BLK, ??bb00_fn_intp2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intp2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intp2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intp3, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intp3, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 06FH, 00H, 051H +$DGS BEG_BLK, ??bb00_fn_intp3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intp3, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intp3, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _intp21_RFTx, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 061H, 00H, 00H +$DGS BEG_FUN, ??bf_intp21_RFTx, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 078H, 00H, 05BH +$DGS BEG_BLK, ??bb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_intp21_RFTx, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_intp21_RFTx, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intcmp0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intcmp0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 087H, 00H, 065H +$DGS BEG_BLK, ??bb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intcmp0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intcmp0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intcmp1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intcmp1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 08EH, 00H, 06FH +$DGS BEG_BLK, ??bb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intcmp1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intcmp1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intdma0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intdma0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 095H, 00H, 079H +$DGS BEG_BLK, ??bb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intdma0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intdma0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intst0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 089H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intst0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09FH, 00H, 083H +$DGS BEG_BLK, ??bb00_fn_intst0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intst0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intst0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intsr0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intsr0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0A8H, 00H, 08DH +$DGS BEG_BLK, ??bb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intsr0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intsr0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intsre0, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 09DH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intsre0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0B1H, 00H, 097H +$DGS BEG_BLK, ??bb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intsre0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intsre0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intst1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0A7H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intst1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0B9H, 00H, 0A1H +$DGS BEG_BLK, ??bb00_fn_intst1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intst1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intst1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intsr1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0B1H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intsr1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0C3H, 00H, 0ABH +$DGS BEG_BLK, ??bb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intsr1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intsr1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intsre1, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0BBH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intsre1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0CAH, 00H, 0B5H +$DGS BEG_BLK, ??bb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intsre1, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intsre1, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm01, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0C5H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm01, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0D4H, 00H, 0BFH +$DGS BEG_BLK, ??bb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm01, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm01, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm02, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0CFH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm02, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0DCH, 00H, 0C9H +$DGS BEG_BLK, ??bb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm02, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm02, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm03, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0D9H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm03, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0E3H, 00H, 0D3H +$DGS BEG_BLK, ??bb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm03, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm03, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intrtc, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0E3H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intrtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0ECH, 00H, 0DDH +$DGS BEG_BLK, ??bb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intrtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intrtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_intmd, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0EDH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_intmd, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0F6H, 00H, 0E7H +$DGS BEG_BLK, ??bb00_fn_intmd, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_intmd, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_intmd, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm04, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0F7H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm04, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0FEH, 00H, 0F1H +$DGS BEG_BLK, ??bb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm04, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm04, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm05, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0101H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm05, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0106H, 00H, 0FBH +$DGS BEG_BLK, ??bb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm05, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm05, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm06, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 010BH, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm06, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 010EH, 00H, 0105H +$DGS BEG_BLK, ??bb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm06, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm06, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _fn_inttm07, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0115H, 00H, 00H +$DGS BEG_FUN, ??bf_fn_inttm07, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0116H, 00H, 010FH +$DGS BEG_BLK, ??bb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_fn_inttm07, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05H +$DGS END_FUN, ??ef_fn_inttm07, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06H +$DGS GLV_SYM, _@vect10, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect12, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect1c, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect24, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect2a, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect34, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect36, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect38, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect3a, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect4a, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect5a, U, U, 00H, 026H, 00H, 00H +$DGS GLV_SYM, _@vect62, U, U, 00H, 026H, 00H, 00H + + EXTRN _intp4_extdc + EXTRN _intp5_shell + EXTRN _int_dma1 + EXTRN _int_iic10 + EXTRN _int_iic_twl + EXTRN _int_adc + EXTRN _int_rtc + EXTRN _int_rtc_int + EXTRN _int_kr + EXTRN _intp6_PM_irq + EXTRN _int_iic_ctr + EXTRN _intp23_ACC_ready + PUBLIC _fn_intwdti + PUBLIC _fn_intlvi + PUBLIC _fn_intp0 + PUBLIC _fn_intp1 + PUBLIC _fn_intp2 + PUBLIC _fn_intp3 + PUBLIC _intp21_RFTx + PUBLIC _fn_intcmp0 + PUBLIC _fn_intcmp1 + PUBLIC _fn_intdma0 + PUBLIC _fn_intst0 + PUBLIC _fn_intsr0 + PUBLIC _fn_intsre0 + PUBLIC _fn_intst1 + PUBLIC _fn_intsr1 + PUBLIC _fn_intsre1 + PUBLIC _fn_inttm01 + PUBLIC _fn_inttm02 + PUBLIC _fn_inttm03 + PUBLIC _fn_intrtc + PUBLIC _fn_intmd + PUBLIC _fn_inttm04 + PUBLIC _fn_inttm05 + PUBLIC _fn_inttm06 + PUBLIC _fn_inttm07 + PUBLIC _@vect10 + PUBLIC _@vect12 + PUBLIC _@vect1c + PUBLIC _@vect24 + PUBLIC _@vect2a + PUBLIC _@vect34 + PUBLIC _@vect36 + PUBLIC _@vect38 + PUBLIC _@vect3a + PUBLIC _@vect4a + PUBLIC _@vect5a + PUBLIC _@vect62 + +@@BITS BSEG + +@@CNST CSEG MIRRORP + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : #pragma nop +; line 2 : +; line 3 : +; line 4 : #include "config.h" +; line 5 : +; line 6 : //#pragma interrupt INTWDTI fn_intwdti // 未使用 +; line 7 : //#pragma interrupt INTLVI fn_intlvi // 未使用 +; line 8 : +; line 9 : //#pragma interrupt INTP0 intp0_slp // SLP (CPUより、要求 +; ) ポーリング +; line 10 : //#pragma interrupt INTP1 fn_intp1 // (I2C) +; line 11 : //#pragma interrupt INTP2 fn_intp2 // (I2C) +; line 12 : //#pragma interrupt INTP3 fn_intp3 // 未搭載 +; line 13 : #pragma interrupt INTP4 intp4_extdc // EXTDC, ただし電源off +; から起こすのみ。通常はポーリング +; line 14 : #pragma interrupt INTP5 intp5_shell // SHELL_CLOSE, ただし電 +; 源offから起こすのみ。通常はポーリング +; line 15 : #pragma interrupt INTP6 intp6_PM_irq // CODEC経由で旧PMICへの +; コマンド書き込み +; line 16 : +; line 17 : //#ifdef _MCU_BSR_ // 割り込みそのものは +; 使いません +; line 18 : //#pragma interrupt INTP21 intp21_RFTx // 電波送信パルス +; line 19 : //#else +; line 20 : //#pragma interrupt INTP7 intp21_RFTx +; line 21 : //#endif +; line 22 : +; line 23 : #ifdef _MCU_BSR_ +; line 24 : #pragma interrupt INTP23 intp23_ACC_ready // 加速度センサ +; 、データ準備完了 +; line 25 : #endif +; line 26 : +; line 27 : //#pragma interrupt INTCMP0 fn_intcmp0 +; line 28 : //#pragma interrupt INTCMP1 fn_intcmp1 +; line 29 : //#pragma interrupt INTDMA0 fn_intdma0 +; line 30 : #pragma interrupt INTDMA1 int_dma1 +; line 31 : +; line 32 : //#pragma interrupt INTST0 fn_intst0 +; line 33 : /* #pragma interrupt INTCSI00 fn_intcsi00 */ +; line 34 : //#pragma interrupt INTSR0 fn_intsr0 +; line 35 : /* #pragma interrupt INTCSI01 fn_intcsi01 */ +; line 36 : //#pragma interrupt INTSRE0 fn_intsre0 +; line 37 : +; line 38 : //#pragma interrupt INTST1 fn_intst1 +; line 39 : /* #pragma interrupt INTCSI10 fn_intcsi10 */ +; line 40 : #pragma interrupt INTIIC10 int_iic10 +; line 41 : //#pragma interrupt INTSR1 fn_intsr1 +; line 42 : //#pragma interrupt INTSRE1 fn_intsre1 +; line 43 : +; line 44 : +; line 45 : #ifdef _MCU_KE3_ +; line 46 : #pragma interrupt INTIICA int_iic_ctr // CTR側 +; line 47 : #else +; line 48 : +; line 49 : // TSはマザボでテレコ、WMは回路図がテレコで結局一致… +; line 50 : #pragma interrupt INTIICA0 int_iic_twl +; line 51 : #pragma interrupt INTIICA1 int_iic_ctr +; line 52 : #endif +; line 53 : +; line 54 : //#pragma interrupt INTTM00 fn_inttm00 +; line 55 : //#pragma interrupt INTTM01 fn_inttm01 +; line 56 : //#pragma interrupt INTTM02 fn_inttm02 +; line 57 : //#pragma interrupt INTTM03 fn_inttm03 +; line 58 : +; line 59 : #pragma interrupt INTAD int_adc +; line 60 : #pragma interrupt INTRTC int_rtc +; line 61 : #pragma interrupt INTRTCI int_rtc_int +; line 62 : #pragma interrupt INTKR int_kr +; line 63 : //#pragma interrupt INTMD fn_intmd +; line 64 : +; line 65 : //#pragma interrupt INTTM04 fn_inttm04 +; line 66 : //#pragma interrupt INTTM05 fn_inttm05 +; line 67 : //#pragma interrupt INTTM06 fn_inttm06 +; line 68 : //#pragma interrupt INTTM07 fn_inttm07 +; line 69 : +; line 70 : +; line 71 : /****************************************************/ +; line 72 : /* 未使用時のダミー関数定義 */ +; line 73 : /****************************************************/ +; line 74 : __interrupt void fn_intwdti( ) +; line 75 : { + +@@BASE CSEG BASE +_fn_intwdti: +$DGL 1,27 +??bf_fn_intwdti: +; line 76 : while( 1 ) +?L0003: +; line 77 : { +??bb00_fn_intwdti: +; line 78 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intwdti: +; line 79 : } +$DGL 0,5 + br $?L0003 ;[INF] 2, 3 +; line 80 : } +$DGL 0,6 +??ef_fn_intwdti: + reti ;[INF] 2, 6 +??ee_fn_intwdti: +; line 81 : __interrupt void fn_intlvi( ) +; line 82 : { +_fn_intlvi: +$DGL 1,37 +??bf_fn_intlvi: +; line 83 : while( 1 ) +?L0007: +; line 84 : { +??bb00_fn_intlvi: +; line 85 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intlvi: +; line 86 : } +$DGL 0,5 + br $?L0007 ;[INF] 2, 3 +; line 87 : } +$DGL 0,6 +??ef_fn_intlvi: + reti ;[INF] 2, 6 +??ee_fn_intlvi: +; line 88 : +; line 89 : __interrupt void fn_intp0(){ +_fn_intp0: +$DGL 1,47 +??bf_fn_intp0: +; line 90 : while( 1 ) +?L0011: +; line 91 : { +??bb00_fn_intp0: +; line 92 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intp0: +; line 93 : } +$DGL 0,5 + br $?L0011 ;[INF] 2, 3 +; line 94 : } +$DGL 0,6 +??ef_fn_intp0: + reti ;[INF] 2, 6 +??ee_fn_intp0: +; line 95 : +; line 96 : __interrupt void fn_intp1( ) +; line 97 : { +_fn_intp1: +$DGL 1,57 +??bf_fn_intp1: +; line 98 : while( 1 ) +?L0015: +; line 99 : { +??bb00_fn_intp1: +; line 100 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intp1: +; line 101 : } +$DGL 0,5 + br $?L0015 ;[INF] 2, 3 +; line 102 : } // +$DGL 0,6 +??ef_fn_intp1: + reti ;[INF] 2, 6 +??ee_fn_intp1: +; line 103 : __interrupt void fn_intp2( ) +; line 104 : { +_fn_intp2: +$DGL 1,67 +??bf_fn_intp2: +; line 105 : while( 1 ) +?L0019: +; line 106 : { +??bb00_fn_intp2: +; line 107 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intp2: +; line 108 : } +$DGL 0,5 + br $?L0019 ;[INF] 2, 3 +; line 109 : } +$DGL 0,6 +??ef_fn_intp2: + reti ;[INF] 2, 6 +??ee_fn_intp2: +; line 110 : __interrupt void fn_intp3( ) +; line 111 : { +_fn_intp3: +$DGL 1,77 +??bf_fn_intp3: +; line 112 : while( 1 ) +?L0023: +; line 113 : { +??bb00_fn_intp3: +; line 114 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intp3: +; line 115 : } +$DGL 0,5 + br $?L0023 ;[INF] 2, 3 +; line 116 : } +$DGL 0,6 +??ef_fn_intp3: + reti ;[INF] 2, 6 +??ee_fn_intp3: +; line 117 : +; line 118 : +; line 119 : __interrupt void intp21_RFTx( ) +; line 120 : { +_intp21_RFTx: +$DGL 1,87 +??bf_intp21_RFTx: +; line 121 : while( 1 ) +?L0027: +; line 122 : { +??bb00_intp21_RFTx: +; line 123 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_intp21_RFTx: +; line 124 : } +$DGL 0,5 + br $?L0027 ;[INF] 2, 3 +; line 125 : } +$DGL 0,6 +??ef_intp21_RFTx: + reti ;[INF] 2, 6 +??ee_intp21_RFTx: +; line 126 : +; line 127 : +; line 128 : //__interrupt void fn_intp4(){ while(1){} } // pm.c +; line 129 : //__interrupt void fn_intp5(){ while(1){} } // pm.c +; line 130 : //__interrupt void fn_intp6(){ while(1){} } // pm.c +; line 131 : //__interrupt void fn_intp7(){ while(1){} } // led.c +; line 132 : //__interrupt void fn_intp21(){ while(1){} } // led.c +; line 133 : +; line 134 : __interrupt void fn_intcmp0( ) +; line 135 : { +_fn_intcmp0: +$DGL 1,97 +??bf_fn_intcmp0: +; line 136 : while( 1 ) +?L0031: +; line 137 : { +??bb00_fn_intcmp0: +; line 138 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intcmp0: +; line 139 : } +$DGL 0,5 + br $?L0031 ;[INF] 2, 3 +; line 140 : } +$DGL 0,6 +??ef_fn_intcmp0: + reti ;[INF] 2, 6 +??ee_fn_intcmp0: +; line 141 : __interrupt void fn_intcmp1( ) +; line 142 : { +_fn_intcmp1: +$DGL 1,107 +??bf_fn_intcmp1: +; line 143 : while( 1 ) +?L0035: +; line 144 : { +??bb00_fn_intcmp1: +; line 145 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intcmp1: +; line 146 : } +$DGL 0,5 + br $?L0035 ;[INF] 2, 3 +; line 147 : } +$DGL 0,6 +??ef_fn_intcmp1: + reti ;[INF] 2, 6 +??ee_fn_intcmp1: +; line 148 : __interrupt void fn_intdma0( ) +; line 149 : { +_fn_intdma0: +$DGL 1,117 +??bf_fn_intdma0: +; line 150 : while( 1 ) +?L0039: +; line 151 : { +??bb00_fn_intdma0: +; line 152 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intdma0: +; line 153 : } +$DGL 0,5 + br $?L0039 ;[INF] 2, 3 +; line 154 : } +$DGL 0,6 +??ef_fn_intdma0: + reti ;[INF] 2, 6 +??ee_fn_intdma0: +; line 155 : +; line 156 : //__interrupt void fn_intdma1(){} // i2c_mcu.cにある +; line 157 : +; line 158 : __interrupt void fn_intst0( ) +; line 159 : { +_fn_intst0: +$DGL 1,127 +??bf_fn_intst0: +; line 160 : while( 1 ) +?L0043: +; line 161 : { +??bb00_fn_intst0: +; line 162 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intst0: +; line 163 : } +$DGL 0,5 + br $?L0043 ;[INF] 2, 3 +; line 164 : } +$DGL 0,6 +??ef_fn_intst0: + reti ;[INF] 2, 6 +??ee_fn_intst0: +; line 165 : +; line 166 : /* __interrupt void fn_intcsi00(){} */ +; line 167 : __interrupt void fn_intsr0( ) +; line 168 : { +_fn_intsr0: +$DGL 1,137 +??bf_fn_intsr0: +; line 169 : while( 1 ) +?L0047: +; line 170 : { +??bb00_fn_intsr0: +; line 171 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intsr0: +; line 172 : } +$DGL 0,5 + br $?L0047 ;[INF] 2, 3 +; line 173 : } +$DGL 0,6 +??ef_fn_intsr0: + reti ;[INF] 2, 6 +??ee_fn_intsr0: +; line 174 : +; line 175 : /* __interrupt void fn_intcsi01(){} */ +; line 176 : __interrupt void fn_intsre0( ) +; line 177 : { +_fn_intsre0: +$DGL 1,147 +??bf_fn_intsre0: +; line 178 : while( 1 ) +?L0051: +; line 179 : { +??bb00_fn_intsre0: +; line 180 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intsre0: +; line 181 : } +$DGL 0,5 + br $?L0051 ;[INF] 2, 3 +; line 182 : } +$DGL 0,6 +??ef_fn_intsre0: + reti ;[INF] 2, 6 +??ee_fn_intsre0: +; line 183 : +; line 184 : __interrupt void fn_intst1( ) +; line 185 : { +_fn_intst1: +$DGL 1,157 +??bf_fn_intst1: +; line 186 : while( 1 ) +?L0055: +; line 187 : { +??bb00_fn_intst1: +; line 188 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intst1: +; line 189 : } +$DGL 0,5 + br $?L0055 ;[INF] 2, 3 +; line 190 : } +$DGL 0,6 +??ef_fn_intst1: + reti ;[INF] 2, 6 +??ee_fn_intst1: +; line 191 : +; line 192 : /* __interrupt void fn_intcsi10(){} */ +; line 193 : //__interrupt void fn_intiic10(){ while(1){} } +; line 194 : __interrupt void fn_intsr1( ) +; line 195 : { +_fn_intsr1: +$DGL 1,167 +??bf_fn_intsr1: +; line 196 : while( 1 ) +?L0059: +; line 197 : { +??bb00_fn_intsr1: +; line 198 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intsr1: +; line 199 : } +$DGL 0,5 + br $?L0059 ;[INF] 2, 3 +; line 200 : } +$DGL 0,6 +??ef_fn_intsr1: + reti ;[INF] 2, 6 +??ee_fn_intsr1: +; line 201 : __interrupt void fn_intsre1( ) +; line 202 : { +_fn_intsre1: +$DGL 1,177 +??bf_fn_intsre1: +; line 203 : while( 1 ) +?L0063: +; line 204 : { +??bb00_fn_intsre1: +; line 205 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intsre1: +; line 206 : } +$DGL 0,5 + br $?L0063 ;[INF] 2, 3 +; line 207 : } +$DGL 0,6 +??ef_fn_intsre1: + reti ;[INF] 2, 6 +??ee_fn_intsre1: +; line 208 : +; line 209 : //__interrupt void fn_intiica(){} // i2c.cにある +; line 210 : /* __interrupt void fn_inttm00(){} *//* sub.cにて定義 */ +; line 211 : __interrupt void fn_inttm01( ) +; line 212 : { +_fn_inttm01: +$DGL 1,187 +??bf_fn_inttm01: +; line 213 : while( 1 ) +?L0067: +; line 214 : { +??bb00_fn_inttm01: +; line 215 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm01: +; line 216 : } +$DGL 0,5 + br $?L0067 ;[INF] 2, 3 +; line 217 : } +$DGL 0,6 +??ef_fn_inttm01: + reti ;[INF] 2, 6 +??ee_fn_inttm01: +; line 218 : +; line 219 : __interrupt void fn_inttm02( ) +; line 220 : { +_fn_inttm02: +$DGL 1,197 +??bf_fn_inttm02: +; line 221 : while( 1 ) +?L0071: +; line 222 : { +??bb00_fn_inttm02: +; line 223 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm02: +; line 224 : } +$DGL 0,5 + br $?L0071 ;[INF] 2, 3 +; line 225 : } +$DGL 0,6 +??ef_fn_inttm02: + reti ;[INF] 2, 6 +??ee_fn_inttm02: +; line 226 : __interrupt void fn_inttm03( ) +; line 227 : { +_fn_inttm03: +$DGL 1,207 +??bf_fn_inttm03: +; line 228 : while( 1 ) +?L0075: +; line 229 : { +??bb00_fn_inttm03: +; line 230 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm03: +; line 231 : } +$DGL 0,5 + br $?L0075 ;[INF] 2, 3 +; line 232 : } +$DGL 0,6 +??ef_fn_inttm03: + reti ;[INF] 2, 6 +??ee_fn_inttm03: +; line 233 : +; line 234 : //__interrupt void fn_intad(){ while(1){} } // adc.c +; line 235 : __interrupt void fn_intrtc( ) +; line 236 : { +_fn_intrtc: +$DGL 1,217 +??bf_fn_intrtc: +; line 237 : while( 1 ) +?L0079: +; line 238 : { +??bb00_fn_intrtc: +; line 239 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intrtc: +; line 240 : } +$DGL 0,5 + br $?L0079 ;[INF] 2, 3 +; line 241 : } +$DGL 0,6 +??ef_fn_intrtc: + reti ;[INF] 2, 6 +??ee_fn_intrtc: +; line 242 : +; line 243 : //__interrupt void int_rtcint(){} // rtc.cにある +; line 244 : //__interrupt void fn_intkr(){} // main.c +; line 245 : __interrupt void fn_intmd( ) +; line 246 : { +_fn_intmd: +$DGL 1,227 +??bf_fn_intmd: +; line 247 : while( 1 ) +?L0083: +; line 248 : { +??bb00_fn_intmd: +; line 249 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_intmd: +; line 250 : } +$DGL 0,5 + br $?L0083 ;[INF] 2, 3 +; line 251 : } +$DGL 0,6 +??ef_fn_intmd: + reti ;[INF] 2, 6 +??ee_fn_intmd: +; line 252 : +; line 253 : __interrupt void fn_inttm04( ) +; line 254 : { +_fn_inttm04: +$DGL 1,237 +??bf_fn_inttm04: +; line 255 : while( 1 ) +?L0087: +; line 256 : { +??bb00_fn_inttm04: +; line 257 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm04: +; line 258 : } +$DGL 0,5 + br $?L0087 ;[INF] 2, 3 +; line 259 : } +$DGL 0,6 +??ef_fn_inttm04: + reti ;[INF] 2, 6 +??ee_fn_inttm04: +; line 260 : +; line 261 : __interrupt void fn_inttm05( ) +; line 262 : { +_fn_inttm05: +$DGL 1,247 +??bf_fn_inttm05: +; line 263 : while( 1 ) +?L0091: +; line 264 : { +??bb00_fn_inttm05: +; line 265 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm05: +; line 266 : } +$DGL 0,5 + br $?L0091 ;[INF] 2, 3 +; line 267 : } +$DGL 0,6 +??ef_fn_inttm05: + reti ;[INF] 2, 6 +??ee_fn_inttm05: +; line 268 : +; line 269 : __interrupt void fn_inttm06( ) +; line 270 : { +_fn_inttm06: +$DGL 1,257 +??bf_fn_inttm06: +; line 271 : while( 1 ) +?L0095: +; line 272 : { +??bb00_fn_inttm06: +; line 273 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm06: +; line 274 : } +$DGL 0,5 + br $?L0095 ;[INF] 2, 3 +; line 275 : } +$DGL 0,6 +??ef_fn_inttm06: + reti ;[INF] 2, 6 +??ee_fn_inttm06: +; line 276 : +; line 277 : __interrupt void fn_inttm07( ) +; line 278 : { +_fn_inttm07: +$DGL 1,267 +??bf_fn_inttm07: +; line 279 : while( 1 ) +?L0099: +; line 280 : { +??bb00_fn_inttm07: +; line 281 : NOP(); +$DGL 0,4 + nop ;[INF] 1, 1 +??eb00_fn_inttm07: +; line 282 : } +$DGL 0,5 + br $?L0099 ;[INF] 2, 3 +; line 283 : } +$DGL 0,6 +??ef_fn_inttm07: + reti ;[INF] 2, 6 +??ee_fn_inttm07: + +@@VECT10 CSEG AT 0010H +_@vect10: + DW _intp4_extdc +_@vect12: + DW _intp5_shell + +@@VECT1C CSEG AT 001CH +_@vect1c: + DW _int_dma1 + +@@VECT24 CSEG AT 0024H +_@vect24: + DW _int_iic10 + +@@VECT2A CSEG AT 002AH +_@vect2a: + DW _int_iic_twl + +@@VECT34 CSEG AT 0034H +_@vect34: + DW _int_adc +_@vect36: + DW _int_rtc +_@vect38: + DW _int_rtc_int +_@vect3a: + DW _int_kr + +@@VECT4A CSEG AT 004AH +_@vect4a: + DW _intp6_PM_irq + +@@VECT5A CSEG AT 005AH +_@vect5a: + DW _int_iic_ctr + +@@VECT62 CSEG AT 0062H +_@vect62: + DW _intp23_ACC_ready + +@@CODE CSEG BASE + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara_0.10\ini_VECT.c +; +; $FUNC fn_intwdti(75) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intlvi(82) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intp0(89) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intp1(97) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intp2(104) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intp3(111) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC intp21_RFTx(120) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intcmp0(135) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intcmp1(142) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intdma0(149) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intst0(159) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intsr0(168) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intsre0(177) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intst1(185) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intsr1(195) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intsre1(202) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm01(212) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm02(220) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm03(227) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intrtc(236) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_intmd(246) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm04(254) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm05(262) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm06(270) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes +; +; $FUNC fn_inttm07(278) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/led.asm b/branches/0.10(X3)/inter_asm/led.asm new file mode 100644 index 0000000..3c5fe5f --- /dev/null +++ b/branches/0.10(X3)/inter_asm/led.asm @@ -0,0 +1,2142 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no led.c +; In-file : led.c +; Asm-file : inter_asm\led.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 017FH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, led.c +$DGS MOD_NAM, led, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS LAB_SYM, bs_S0172, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0172, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0173, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0173, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0174, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0174, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0175, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0175, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS STA_SYM, _MSG_MAIL, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _LED_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H +$DGS BEG_FUN, ??bf_LED_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 051H +$DGS BEG_BLK, ??bb00_LED_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 027H, 00H, 00H +$DGS END_BLK, ??eb00_LED_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS END_FUN, ??ef_LED_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02BH +$DGS GLV_SYM, _LED_stop, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 05DH, 00H, 00H +$DGS BEG_FUN, ??bf_LED_stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 057H, 00H, 05DH +$DGS END_FUN, ??ef_LED_stop, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 05H +$DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_led_pow, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 078H, 00H, 061H +$DGS BEG_BLK, ??bb00_tsk_led_pow, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 063H +$DGS BEG_BLK, ??bb01_tsk_led_pow, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 00H +$DGS END_BLK, ??eb01_tsk_led_pow, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS END_BLK, ??eb00_tsk_led_pow, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02DH +$DGS END_FUN, ??ef_tsk_led_pow, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02FH +$DGS STA_SYM, _led_pow_normal, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 096H, 00H, 00H +$DGS BEG_FUN, ??bf_led_pow_normal, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0AEH, 00H, 070H +$DGS STA_SYM, _state, ?L0031, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 072H +$DGS BEG_BLK, ??bb01_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 076H +$DGS END_BLK, ??eb01_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb02_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 07CH +$DGS END_BLK, ??eb02_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS END_BLK, ??eb00_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb03_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 07EH +$DGS BEG_BLK, ??bb04_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 082H +$DGS END_BLK, ??eb04_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01AH +$DGS BEG_BLK, ??bb05_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 088H +$DGS END_BLK, ??eb05_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01EH +$DGS END_BLK, ??eb03_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 021H +$DGS BEG_BLK, ??bb06_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 023H, 00H, 08AH +$DGS BEG_BLK, ??bb07_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 026H, 00H, 08EH +$DGS END_BLK, ??eb07_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 028H +$DGS BEG_BLK, ??bb08_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 00H +$DGS END_BLK, ??eb08_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS END_BLK, ??eb06_led_pow_normal, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02DH +$DGS END_FUN, ??ef_led_pow_normal, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 030H +$DGS STA_SYM, _led_pow_hotaru, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0D8H, 00H, 00H +$DGS BEG_FUN, ??bf_led_pow_hotaru, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0E5H, 00H, 09EH +$DGS STA_SYM, _delay, ?L0052, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _state, ?L0053, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _blue_to, ?L0054, U, 0DH, 03H, 00H, 00H +$DGS STA_SYM, _red_to, ?L0055, U, 0DH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 0A2H +$DGS END_BLK, ??eb00_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS BEG_BLK, ??bb01_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 0A6H +$DGS END_BLK, ??eb01_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS BEG_BLK, ??bb02_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 0A8H +$DGS BEG_BLK, ??bb03_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 0ACH +$DGS END_BLK, ??eb03_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS BEG_BLK, ??bb04_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 0B2H +$DGS END_BLK, ??eb04_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01AH +$DGS END_BLK, ??eb02_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS BEG_BLK, ??bb05_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01EH, 00H, 0B4H +$DGS BEG_BLK, ??bb06_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 0B8H +$DGS END_BLK, ??eb06_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 022H +$DGS BEG_BLK, ??bb07_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 024H, 00H, 0BEH +$DGS END_BLK, ??eb07_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS END_BLK, ??eb05_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 027H +$DGS BEG_BLK, ??bb08_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 0C0H +$DGS BEG_BLK, ??bb09_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 0C4H +$DGS END_BLK, ??eb09_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 034H +$DGS BEG_BLK, ??bb0A_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 036H, 00H, 0C8H +$DGS END_BLK, ??eb0A_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 039H +$DGS BEG_BLK, ??bb0B_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03FH, 00H, 0CCH +$DGS END_BLK, ??eb0B_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 041H +$DGS BEG_BLK, ??bb0C_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 0D2H +$DGS END_BLK, ??eb0C_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 045H +$DGS END_BLK, ??eb08_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 047H +$DGS BEG_BLK, ??bb0D_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04AH, 00H, 00H +$DGS END_BLK, ??eb0D_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04CH +$DGS END_FUN, ??ef_led_pow_hotaru, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04EH +$DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0106H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_led_wifi, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 013CH, 00H, 0E0H +$DGS STA_SYM, _task_interval, ?L0079, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _remain_wifi_tx, ?L0080, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _state_wifi_tx, ?L0081, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _flag_wifi_TX, ?L0082, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 0E4H +$DGS END_BLK, ??eb00_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS BEG_BLK, ??bb01_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0FH, 00H, 0E6H +$DGS BEG_BLK, ??bb02_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 0ECH +$DGS END_BLK, ??eb02_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS END_BLK, ??eb01_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS BEG_BLK, ??bb03_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 0F0H +$DGS END_BLK, ??eb03_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb04_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01DH, 00H, 0F2H +$DGS BEG_BLK, ??bb05_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02DH, 00H, 0F4H +$DGS BEG_BLK, ??bb06_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 0F8H +$DGS END_BLK, ??eb06_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 038H +$DGS BEG_BLK, ??bb07_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03BH, 00H, 0FEH +$DGS END_BLK, ??eb07_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03EH +$DGS END_BLK, ??eb05_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 041H +$DGS BEG_BLK, ??bb08_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 00H +$DGS END_BLK, ??eb08_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 048H +$DGS END_BLK, ??eb04_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04BH +$DGS END_FUN, ??ef_tsk_led_wifi, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04CH +$DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 014AH, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_led_notify, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0191H, 02H, 010EH +$DGS STA_SYM, _task_interval, ?L0107, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _flg_char_space, ?L0108, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _state_notify_led, ?L0109, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _flag_wifi_TX, ?L0110, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 0112H +$DGS END_BLK, ??eb00_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS BEG_BLK, ??bb01_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 0114H +$DGS BEG_BLK, ??bb02_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01FH, 00H, 0118H +$DGS END_BLK, ??eb02_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 027H +$DGS BEG_BLK, ??bb03_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 011CH +$DGS END_BLK, ??eb03_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS BEG_BLK, ??bb04_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 032H, 00H, 0120H +$DGS REG_VAR, _dat, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 033H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb05_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 038H, 00H, 0124H +$DGS END_BLK, ??eb05_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03CH +$DGS BEG_BLK, ??bb06_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 041H, 00H, 0128H +$DGS END_BLK, ??eb06_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 043H +$DGS BEG_BLK, ??bb07_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 045H, 00H, 012CH +$DGS END_BLK, ??eb07_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 047H +$DGS BEG_BLK, ??bb08_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04BH, 00H, 012EH +$DGS BEG_BLK, ??bb09_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04FH, 00H, 0132H +$DGS END_BLK, ??eb09_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 052H +$DGS BEG_BLK, ??bb0A_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 054H, 00H, 0138H +$DGS END_BLK, ??eb0A_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 057H +$DGS END_BLK, ??eb08_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05CH +$DGS BEG_BLK, ??bb0B_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05EH, 00H, 013AH +$DGS BEG_BLK, ??bb0C_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 060H, 00H, 013EH +$DGS END_BLK, ??eb0C_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 063H +$DGS BEG_BLK, ??bb0D_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 065H, 00H, 00H +$DGS END_BLK, ??eb0D_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 068H +$DGS END_BLK, ??eb0B_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06AH +$DGS END_BLK, ??eb04_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06BH +$DGS END_BLK, ??eb01_tsk_led_notify, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06CH +$DGS END_FUN, ??ef_tsk_led_notify, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 06DH +$DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 017FH, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_led_cam, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0208H, 00H, 0151H +$DGS STA_SYM, _state_led_cam, ?L0142, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _task_interval, ?L0143, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _state_led_cam_twl, ?L0144, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 0155H +$DGS END_BLK, ??eb00_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0AH +$DGS BEG_BLK, ??bb01_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 0157H +$DGS BEG_BLK, ??bb02_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01EH, 00H, 015BH +$DGS END_BLK, ??eb02_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 021H +$DGS BEG_BLK, ??bb03_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 023H, 00H, 015FH +$DGS END_BLK, ??eb03_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS BEG_BLK, ??bb04_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 0163H +$DGS END_BLK, ??eb04_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS BEG_BLK, ??bb05_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 032H, 00H, 0167H +$DGS END_BLK, ??eb05_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 034H +$DGS BEG_BLK, ??bb06_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 039H, 00H, 016BH +$DGS END_BLK, ??eb06_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03DH +$DGS BEG_BLK, ??bb07_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03FH, 00H, 016FH +$DGS END_BLK, ??eb07_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 041H +$DGS BEG_BLK, ??bb08_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 045H, 00H, 0171H +$DGS BEG_BLK, ??bb09_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04DH, 00H, 0175H +$DGS END_BLK, ??eb09_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 050H +$DGS BEG_BLK, ??bb0A_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 052H, 00H, 00H +$DGS END_BLK, ??eb0A_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 055H +$DGS END_BLK, ??eb08_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05FH +$DGS END_BLK, ??eb01_tsk_led_cam, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 060H +$DGS END_FUN, ??ef_tsk_led_cam, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 062H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@isrem, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + + EXTRN _vreg_ctr + EXTRN _system_status + EXTRN _@RTARG0 + EXTRN @@isrem + EXTRN _vreg_twl + PUBLIC _LED_init + PUBLIC _LED_stop + PUBLIC _tsk_led_pow + PUBLIC _tsk_led_wifi + PUBLIC _tsk_led_notify + PUBLIC _tsk_led_cam + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 +_MSG_MAIL: DB 0F6H ; 246 + DB 0DAH ; 218 + DB 06EH ; 110 + DB 094H ; 148 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0142: DS (1) + DS (1) + +@@DATA DSEG BASEP +?L0031: DS (1) +?L0052: DS (1) +?L0053: DS (1) + DS (1) +?L0054: DS (2) +?L0055: DS (2) +?L0079: DS (1) +?L0080: DS (1) +?L0081: DS (1) +?L0082: DS (1) +?L0107: DS (1) +?L0108: DS (1) +?L0109: DS (1) +?L0110: DS (1) +?L0143: DS (1) +?L0144: DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_S0172: + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0172: + +ROM_CODE CSEG BASE +bs_S0173: + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw TDR03,ax ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0173: + +ROM_CODE CSEG BASE +bs_S0174: + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw TDR05,ax ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0174: + +ROM_CODE CSEG BASE +bs_S0175: + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0175: + +; *** Sub-Routine Information *** +; +; $SUB bs_S0172 +; CODE SIZE= 6 bytes +; +; $SUB bs_S0173 +; CODE SIZE= 7 bytes +; +; $SUB bs_S0174 +; CODE SIZE= 7 bytes +; +; $SUB bs_S0175 +; CODE SIZE= 7 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : LED.c +; line 3 : +; line 4 : ======================================================== */ +; line 5 : #pragma sfr +; line 6 : +; line 7 : +; line 8 : #include "incs.h" +; line 9 : #include "led.h" +; line 10 : +; line 11 : +; line 12 : +; line 13 : // ======================================================== +; line 14 : // TPS0 +; line 15 : #define BIT_PRS012 ( 1 << 2 ) +; line 16 : #define BIT_PRS002 ( 1 << 6 ) +; line 17 : +; line 18 : // TMR0 +; line 19 : #define BIT_CKS0 15 +; line 20 : #define BIT_CCS0 12 +; line 21 : #define BIT_MASTER0 11 +; line 22 : #define BIT_STS0 8 +; line 23 : #define BIT_CIS0 6 +; line 24 : #define BIT_MD123 1 +; line 25 : #define BIT_MD0 0 +; line 26 : +; line 27 : // ======================================================== +; line 28 : static void led_pow_normal( ); +; line 29 : static void led_pow_hotaru( ); +; line 30 : +; line 31 : +; line 32 : +; line 33 : // ======================================================== +; line 34 : static const char MSG_MAIL[] = { 0b11110110, 0b11011010, 0b01101 +; 110, 0b10010100 }; +; line 35 : #define MSG_SPD 60 +; line 36 : // ↑255/3以下であること！ +; line 37 : +; line 38 : // ======================================================== +; line 39 : void LED_init( ) +; line 40 : { + +ROM_CODE CSEG BASE +_LED_init: +$DGL 1,77 +??bf_LED_init: +; line 41 : /** +; line 42 : PWMのセット、とりあえず全部消灯 +; line 43 : +; line 44 : マスタチャネル：０　(P01:/reset2)　マスターは偶数チャネルしかで +; きない +; line 45 : スレーブ　　　　１　ＳＬＴＯ。(３Ｄ ＬＥＤ？) +; line 46 : 　　　　　　　　２　カメラ +; line 47 : 　　　　　　　　３　WiFi +; line 48 : 　　　　　　　　４　(ピンはＲＴＣ32kHz out に使用) +; line 49 : 　　　　　　　　５　充電 +; line 50 : 　　　　　　　　６　電源 Ｌ +; line 51 : 　　　　　　　　７　電源 Ｈ +; line 52 : */ +; line 53 : TAU0EN = 1; +$DGL 0,14 + set1 !PER2.0 ;[INF] 4, 2 +; line 54 : TPS0 = BIT_PRS012 | BIT_PRS002; // マスタークロックはCK0 +; 1,8M/2 /2^4 = 250kHz +$DGL 0,15 + movw ax,#044H ; 68 ;[INF] 3, 1 + movw !TPS0,ax ;[INF] 3, 1 +; line 55 : +; line 56 : TMR00 = +; line 57 : 1 << BIT_CKS0 | 0 << BIT_CCS0 | 1 << BIT_MASTER0 | 0 << +; BIT_STS0 | 0 +; line 58 : << BIT_CIS0 | 0 << BIT_MD123 | 1 << BIT_MD0; +$DGL 0,19 + movw ax,#08801H ; -30719 ;[INF] 3, 1 + movw !TMR00,ax ;[INF] 3, 1 +; line 59 : TMR01 = TMR02 = TMR03 = TMR04 = TMR05 = TMR06 = TMR07 = +; line 60 : 1 << BIT_CKS0 | 0 << BIT_CCS0 | 0 << BIT_MASTER0 | 4 << +; BIT_STS0 | 0 +; line 61 : << BIT_CIS0 | 4 << BIT_MD123 | 1 << BIT_MD0; +$DGL 0,22 + movw ax,#08409H ; -31735 ;[INF] 3, 1 + movw !TMR07,ax ;[INF] 3, 1 + movw !TMR06,ax ;[INF] 3, 1 + movw !TMR05,ax ;[INF] 3, 1 + movw !TMR04,ax ;[INF] 3, 1 + movw !TMR03,ax ;[INF] 3, 1 + movw !TMR02,ax ;[INF] 3, 1 + movw !TMR01,ax ;[INF] 3, 1 +; line 62 : ISC = 0; +$DGL 0,23 + clrb !ISC ;[INF] 3, 1 +; line 63 : TOM0 = 0b0000000011111110; // 出力モード。4はPWM出力しないが +; 1にしないとTO5以降にクロックが届かない +$DGL 0,24 + movw ax,#0FEH ; 254 ;[INF] 3, 1 + movw !TOM0,ax ;[INF] 3, 1 +; line 64 : +; line 65 : #ifdef _MCU_BSR_ +; line 66 : TOL0 = 0b0000000000000000; // 出力を反転させるかフラグ +$DGL 0,27 + clrw ax ;[INF] 1, 1 + movw !TOL0,ax ;[INF] 3, 1 +; line 67 : #else +; line 68 : TOL0 = 0b0000000000000100; // 出力を反転させるかフラグ +; line 69 : #endif +; line 70 : +; line 71 : TO0 = 0; // タイマー動作中で、タイマー出力 +; にしてないときのピンのラッチ。タイマー出力を使わないなら０ +$DGL 0,32 + movw !TO0,ax ;[INF] 3, 1 +; line 72 : TOE0 = 0b0000000011101110; // TOxをタイマーモジュールが制御？ +$DGL 0,33 + mov x,#0EEH ; 238 ;[INF] 2, 1 + movw !TOE0,ax ;[INF] 3, 1 +; line 73 : TS0 = 0b0000000011101111; // 動作開始 +$DGL 0,34 + incw ax ;[INF] 1, 1 + movw !TS0,ax ;[INF] 3, 1 +; line 74 : +; line 75 : TDR00 = LED_BRIGHT_MAX - 1; // 10bit, 周期 +$DGL 0,36 + movw TDR00,#0FEH ; 254 ;[INF] 4, 1 +; line 76 : +; line 77 : if( system_status.reboot ) +$DGL 0,38 + mov a,!_system_status+2 ;[INF] 3, 1 + bf a.3,$?L0003 ;[INF] 3, 5 +; line 78 : { +??bb00_LED_init: +; line 79 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; +$DGL 0,40 + clrb !_vreg_ctr+41 ;[INF] 3, 1 +; line 80 : LED_duty_pow_H = LED_BRIGHT_MAX; +$DGL 0,41 + movw TDR06,#0FFH ; 255 ;[INF] 4, 1 +??eb00_LED_init: +; line 81 : } +?L0003: +; line 82 : } +$DGL 0,43 +??ef_LED_init: + ret ;[INF] 1, 6 +??ee_LED_init: +; line 83 : +; line 84 : +; line 85 : +; line 86 : void LED_stop( ) +; line 87 : { +_LED_stop: +$DGL 1,87 +??bf_LED_stop: +; line 88 : TT0 = 0b0000000011101111; // 一斉停止（しないとだめ） +$DGL 0,2 + movw ax,#0EFH ; 239 ;[INF] 3, 1 + movw !TT0,ax ;[INF] 3, 1 +; line 89 : TOE0 = 0b0000000000000000; // TOxをタイマーモジュールが制御？ +; (GPIOになる) +$DGL 0,3 + clrw ax ;[INF] 1, 1 + movw !TOE0,ax ;[INF] 3, 1 +; line 90 : TAU0EN = 0; +$DGL 0,4 + clr1 !PER2.0 ;[INF] 4, 2 +; line 91 : } +$DGL 0,5 +??ef_LED_stop: + ret ;[INF] 1, 6 +??ee_LED_stop: +; line 92 : +; line 93 : +; line 94 : +; line 95 : +; line 96 : /* ======================================================== +; line 97 : // 電源LED +; line 98 : LED_POW_B,R 6,7 +; line 99 : +; line 100 : TDR00　周期(0x03FF。TPS0で250kHzでカウントアップ。10bitなら250 +; Hz位になる) +; line 101 : TDR0x　Duty 0で消灯、TDR00(より大 =0x03FF以上)で点灯です。 +; line 102 : +; line 103 : enum pwr_state_{ +; line 104 : OFF_TRIG = 0, +; line 105 : OFF, +; line 106 : ON_TRIG, +; line 107 : ON, +; line 108 : SLEEP_TRIG, +; line 109 : SLEEP +; line 110 : }; +; line 111 : +; line 112 : enum LED_ILUM_MODE{ +; line 113 : LED_POW_ILM_AUTO, +; line 114 : LED_POW_ILM_ON, +; line 115 : LED_POW_ILM_HOTARU, +; line 116 : LED_POW_ILM_CEOFF +; line 117 : }; +; line 118 : ======================================================== */ +; line 119 : void tsk_led_pow( ) +; line 120 : { +_tsk_led_pow: +$DGL 1,93 +??bf_tsk_led_pow: +; line 121 : switch ( vreg_ctr[VREG_C_LED_POW] ) +$DGL 0,2 + mov x,!_vreg_ctr+41 ;[INF] 3, 1 + call !bs_S0172 ;[INF] 3, 3 + bz $?L0010 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0013 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0012 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0011 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0015 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0016 ;[INF] 2, 4 + br $?L0013 ;[INF] 2, 3 +; line 122 : { +??bb00_tsk_led_pow: +; line 123 : // 自動切り替え +; line 124 : case ( LED_POW_ILM_AUTO ): +?L0010: +; line 125 : switch ( system_status.pwr_state ) +$DGL 0,6 + mov a,!_system_status ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + subw ax,#03H ; 3 ;[INF] 3, 1 + bz $?L0021 ;[INF] 2, 4 + subw ax,#02H ; 2 ;[INF] 3, 1 + bnz $?L0009 ;[INF] 2, 4 +; line 126 : { +??bb01_tsk_led_pow: +; line 127 : case SLEEP: +; line 128 : led_pow_hotaru( ); +$DGL 0,9 + call !_led_pow_hotaru ;[INF] 3, 3 +; line 129 : break; +$DGL 0,10 + ret ;[INF] 1, 6 +; line 130 : +; line 131 : case ON: +?L0021: +; line 132 : led_pow_normal( ); +$DGL 0,13 + call !_led_pow_normal ;[INF] 3, 3 +; line 133 : break; +$DGL 0,14 + ret ;[INF] 1, 6 +; line 134 : +; line 135 : default: +; line 136 : break; +??eb01_tsk_led_pow: +; line 137 : } +; line 138 : break; +; line 139 : +; line 140 : // 強制 +; line 141 : case ( LED_POW_ILM_OFF ): +?L0011: +; line 142 : LED_duty_pow_H -= ( LED_duty_pow_H == 0x0000 ) ? 0 : 1; +$DGL 0,23 + clrw ax ;[INF] 1, 1 + cmpw ax,!TDR06 ;[INF] 3, 1 + skz ;[INF] 2, 1 + onew ax ;[INF] 1, 1 +?L0026: + movw bc,ax ;[INF] 1, 1 + movw ax,TDR06 ;[INF] 2, 1 + subw ax,bc ;[INF] 1, 1 + movw TDR06,ax ;[INF] 2, 1 +; line 143 : LED_duty_pow_L -= ( LED_duty_pow_L == 0x0000 ) ? 0 : 1; +$DGL 0,24 + clrw ax ;[INF] 1, 1 + cmpw ax,!TDR07 ;[INF] 3, 1 + skz ;[INF] 2, 1 + onew ax ;[INF] 1, 1 +?L0028: + movw bc,ax ;[INF] 1, 1 + movw ax,TDR07 ;[INF] 2, 1 + subw ax,bc ;[INF] 1, 1 + movw TDR07,ax ;[INF] 2, 1 +; line 144 : break; +$DGL 0,25 + ret ;[INF] 1, 6 +; line 145 : +; line 146 : case ( LED_POW_ILM_HOTARU ): +?L0012: +; line 147 : led_pow_hotaru( ); +$DGL 0,28 + call !_led_pow_hotaru ;[INF] 3, 3 +; line 148 : break; +$DGL 0,29 + ret ;[INF] 1, 6 +; line 149 : +; line 150 : case ( LED_POW_ILM_ON ): +?L0013: +; line 151 : default: +; line 152 : led_pow_normal( ); +$DGL 0,33 + call !_led_pow_normal ;[INF] 3, 3 +; line 153 : break; +$DGL 0,34 + ret ;[INF] 1, 6 +; line 154 : +; line 155 : case ( LED_POW_ILM_ONLY_RED ): +?L0015: +; line 156 : LED_duty_pow_H = 0x0000; +$DGL 0,37 + clrw ax ;[INF] 1, 1 + movw TDR06,ax ;[INF] 2, 1 +; line 157 : LED_duty_pow_L = LED_BRIGHT_MAX; +$DGL 0,38 + movw TDR07,#0FFH ; 255 ;[INF] 4, 1 +; line 158 : break; +$DGL 0,39 + ret ;[INF] 1, 6 +; line 159 : +; line 160 : case ( LED_POW_ILM_ONLY_BLUE ): +?L0016: +; line 161 : LED_duty_pow_H = LED_BRIGHT_MAX; +$DGL 0,42 + movw TDR06,#0FFH ; 255 ;[INF] 4, 1 +; line 162 : LED_duty_pow_L = 0x0000; +$DGL 0,43 + clrw ax ;[INF] 1, 1 + movw TDR07,ax ;[INF] 2, 1 +; line 163 : break; +??eb00_tsk_led_pow: +; line 164 : } +?L0009: +; line 165 : +; line 166 : } +$DGL 0,47 +??ef_tsk_led_pow: + ret ;[INF] 1, 6 +??ee_tsk_led_pow: +; line 167 : +; line 168 : +; line 169 : +; line 170 : /* ======================================================== +; line 171 : 電池残量で、　青→赤→赤点滅 +; line 172 : ======================================================== */ +; line 173 : static void led_pow_normal( ) +; line 174 : { +_led_pow_normal: +$DGL 1,107 +??bf_led_pow_normal: +; line 175 : static u8 state; +; line 176 : +; line 177 : if( vreg_ctr[VREG_C_BT_REMAIN] < 3 ) +$DGL 0,4 + cmp !_vreg_ctr+11,#03H ; 3 ;[INF] 4, 1 + bnc $?L0032 ;[INF] 2, 4 +; line 178 : { +??bb00_led_pow_normal: +; line 179 : // 赤点滅 +; line 180 : state++; +$DGL 0,7 + inc !?L0031 ; state ;[INF] 3, 2 +; line 181 : if( state < 127 ) +$DGL 0,8 + cmp !?L0031,#07FH ; state,127 ;[INF] 4, 1 + bnc $?L0034 ;[INF] 2, 4 +; line 182 : { +??bb01_led_pow_normal: +; line 183 : LED_duty_pow_H = 0x0000; +$DGL 0,10 + clrw ax ;[INF] 1, 1 + movw TDR06,ax ;[INF] 2, 1 +; line 184 : LED_duty_pow_L = 0x0000; +$DGL 0,11 + movw TDR07,ax ;[INF] 2, 1 +??eb01_led_pow_normal: +; line 185 : } +$DGL 0,12 + br $?L0035 ;[INF] 2, 3 +?L0034: +; line 186 : else +; line 187 : { +??bb02_led_pow_normal: +; line 188 : LED_duty_pow_L = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,15 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw TDR07,ax ;[INF] 2, 1 +??eb02_led_pow_normal: +; line 189 : } +?L0035: +; line 190 : return; +$DGL 0,17 + ret ;[INF] 1, 6 +??eb00_led_pow_normal: +; line 191 : +; line 192 : } +?L0032: +; line 193 : else if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) +$DGL 0,20 + cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + bnc $?L0036 ;[INF] 2, 4 +; line 194 : { +??bb03_led_pow_normal: +; line 195 : // 赤点灯 +; line 196 : if( LED_duty_pow_H != 0x0000 ) +$DGL 0,23 + clrw ax ;[INF] 1, 1 + cmpw ax,!TDR06 ;[INF] 3, 1 + skz ;[INF] 2, 1 +; line 197 : { // 青フェードアウト +??bb04_led_pow_normal: +; line 198 : LED_duty_pow_H -= 1; +$DGL 0,25 + decw !TDR06 ;[INF] 3, 2 +??eb04_led_pow_normal: +; line 199 : } +?L0038: +; line 200 : if( LED_duty_pow_L != vreg_ctr[VREG_C_LED_BRIGHT] ) +$DGL 0,27 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + cmpw ax,!TDR07 ;[INF] 3, 1 + bz $?L0048 ;[INF] 2, 4 +; line 201 : { // 赤フェードイン +??bb05_led_pow_normal: +; line 202 : LED_duty_pow_L += ( LED_duty_pow_L < vreg_ctr[VREG_C +; _LED_BRIGHT] ) ? 1 : -1; +$DGL 0,29 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + movw bc,ax ;[INF] 1, 1 + movw ax,TDR07 ;[INF] 2, 1 + cmpw ax,bc ;[INF] 1, 1 + bnc $?L0042 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0043 ;[INF] 2, 3 +?L0042: + clrw ax ;[INF] 1, 1 + decw ax ;[INF] 1, 1 +?L0043: + movw bc,ax ;[INF] 1, 1 + movw ax,TDR07 ;[INF] 2, 1 + addw ax,bc ;[INF] 1, 1 + movw TDR07,ax ;[INF] 2, 1 +??eb05_led_pow_normal: +; line 203 : } +; line 204 : return; +$DGL 0,31 + ret ;[INF] 1, 6 +??eb03_led_pow_normal: +; line 205 : +; line 206 : } +?L0036: +; line 207 : else +; line 208 : { +??bb06_led_pow_normal: +; line 209 : // 青点灯 +; line 210 : if( LED_duty_pow_H != vreg_ctr[VREG_C_LED_BRIGHT] ) +$DGL 0,37 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + cmpw ax,!TDR06 ;[INF] 3, 1 + bz $?L0044 ;[INF] 2, 4 +; line 211 : { +??bb07_led_pow_normal: +; line 212 : LED_duty_pow_H += ( LED_duty_pow_H < vreg_ctr[VREG_C +; _LED_BRIGHT] ) ? 1 : -1; +$DGL 0,39 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + movw bc,ax ;[INF] 1, 1 + movw ax,TDR06 ;[INF] 2, 1 + cmpw ax,bc ;[INF] 1, 1 + bnc $?L0046 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0047 ;[INF] 2, 3 +?L0046: + clrw ax ;[INF] 1, 1 + decw ax ;[INF] 1, 1 +?L0047: + movw bc,ax ;[INF] 1, 1 + movw ax,TDR06 ;[INF] 2, 1 + addw ax,bc ;[INF] 1, 1 + movw TDR06,ax ;[INF] 2, 1 +??eb07_led_pow_normal: +; line 213 : } +?L0044: +; line 214 : if( LED_duty_pow_L != 0x0000 ) +$DGL 0,41 + clrw ax ;[INF] 1, 1 + cmpw ax,!TDR07 ;[INF] 3, 1 + skz ;[INF] 2, 1 +; line 215 : { +??bb08_led_pow_normal: +; line 216 : LED_duty_pow_L -= 1; +$DGL 0,43 + decw !TDR07 ;[INF] 3, 2 +??eb08_led_pow_normal: +; line 217 : } +?L0048: +??eb06_led_pow_normal: +; line 218 : } +; line 219 : +; line 220 : return; +; line 221 : } +$DGL 0,48 +??ef_led_pow_normal: + ret ;[INF] 1, 6 +??ee_led_pow_normal: +; line 222 : +; line 223 : +; line 224 : +; line 225 : /* ======================================================== +; line 226 : ホタルパターン +; line 227 : ======================================================== */ +; line 228 : static void led_pow_hotaru( ) +; line 229 : { +_led_pow_hotaru: +$DGL 1,150 +??bf_led_pow_hotaru: +; line 230 : static u8 delay; +; line 231 : static u8 state; +; line 232 : static u16 blue_to; +; line 233 : static u16 red_to; +; line 234 : +; line 235 : if( delay != 0 ) +$DGL 0,7 + cmp0 !?L0052 ; delay ;[INF] 3, 1 + bz $?L0056 ;[INF] 2, 4 +; line 236 : { +??bb00_led_pow_hotaru: +; line 237 : delay -= 1; +$DGL 0,9 + dec !?L0052 ; delay ;[INF] 3, 2 +; line 238 : return; +$DGL 0,10 + ret ;[INF] 1, 6 +??eb00_led_pow_hotaru: +; line 239 : } +?L0056: +; line 240 : else +; line 241 : { +??bb01_led_pow_hotaru: +; line 242 : delay = 10; +$DGL 0,14 + mov !?L0052,#0AH ; delay,10 ;[INF] 4, 1 +??eb01_led_pow_hotaru: +; line 243 : } +; line 244 : +; line 245 : if( LED_duty_pow_L != red_to ) +$DGL 0,17 + movw ax,TDR07 ;[INF] 2, 1 + cmpw ax,!?L0055 ; red_to ;[INF] 3, 1 + bz $?L0061 ;[INF] 2, 4 +; line 246 : { +??bb02_led_pow_hotaru: +; line 247 : if( LED_duty_pow_L > red_to ) +$DGL 0,19 + movw ax,!?L0055 ; red_to ;[INF] 3, 1 + cmpw ax,!TDR07 ;[INF] 3, 1 + bnc $?L0060 ;[INF] 2, 4 +; line 248 : { +??bb03_led_pow_hotaru: +; line 249 : LED_duty_pow_L -= 1; +$DGL 0,21 + decw !TDR07 ;[INF] 3, 2 +??eb03_led_pow_hotaru: +; line 250 : } +$DGL 0,22 + br $?L0061 ;[INF] 2, 3 +?L0060: +; line 251 : else +; line 252 : { +??bb04_led_pow_hotaru: +; line 253 : LED_duty_pow_L += 2; +$DGL 0,25 + movw ax,TDR07 ;[INF] 2, 1 + incw ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + movw TDR07,ax ;[INF] 2, 1 +??eb04_led_pow_hotaru: +; line 254 : } +?L0061: +??eb02_led_pow_hotaru: +; line 255 : } +; line 256 : +; line 257 : if( LED_duty_pow_H != blue_to ) +$DGL 0,29 + movw ax,TDR06 ;[INF] 2, 1 + cmpw ax,!?L0054 ; blue_to ;[INF] 3, 1 + bz $?L0065 ;[INF] 2, 4 +; line 258 : { +??bb05_led_pow_hotaru: +; line 259 : if( LED_duty_pow_H > blue_to ) +$DGL 0,31 + movw ax,!?L0054 ; blue_to ;[INF] 3, 1 + cmpw ax,!TDR06 ;[INF] 3, 1 + bnc $?L0064 ;[INF] 2, 4 +; line 260 : { +??bb06_led_pow_hotaru: +; line 261 : LED_duty_pow_H -= 1; +$DGL 0,33 + decw !TDR06 ;[INF] 3, 2 +??eb06_led_pow_hotaru: +; line 262 : } +$DGL 0,34 + br $?L0065 ;[INF] 2, 3 +?L0064: +; line 263 : else +; line 264 : { +??bb07_led_pow_hotaru: +; line 265 : LED_duty_pow_H += 2; +$DGL 0,37 + movw ax,TDR06 ;[INF] 2, 1 + incw ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + movw TDR06,ax ;[INF] 2, 1 +??eb07_led_pow_hotaru: +; line 266 : } +?L0065: +??eb05_led_pow_hotaru: +; line 267 : } +; line 268 : +; line 269 : switch ( state ) +$DGL 0,41 + mov x,!?L0053 ; state ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + clrw bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0067 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bz $?L0067 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bnz $?L0068 ;[INF] 2, 4 +; line 270 : { +??bb08_led_pow_hotaru: +; line 271 : // フェードイン +; line 272 : case ( 0 ): +?L0067: +; line 273 : case ( 2 ): +; line 274 : case ( 4 ): +; line 275 : if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) +$DGL 0,47 + cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + bnc $?L0071 ;[INF] 2, 4 +; line 276 : { +??bb09_led_pow_hotaru: +; line 277 : // 赤いとき +; line 278 : blue_to = 0; +$DGL 0,50 + clrw ax ;[INF] 1, 1 + movw !?L0054,ax ; blue_to ;[INF] 3, 1 +; line 279 : red_to = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,51 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + movw !?L0055,ax ; red_to ;[INF] 3, 1 +??eb09_led_pow_hotaru: +; line 280 : } +$DGL 0,52 + br $?L0066 ;[INF] 2, 3 +?L0071: +; line 281 : else +; line 282 : { +??bb0A_led_pow_hotaru: +; line 283 : blue_to = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,55 + mov x,!_vreg_ctr+40 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw !?L0054,ax ; blue_to ;[INF] 3, 1 +; line 284 : red_to = 0; +$DGL 0,56 + clrw ax ;[INF] 1, 1 + movw !?L0055,ax ; red_to ;[INF] 3, 1 +??eb0A_led_pow_hotaru: +; line 285 : } +; line 286 : break; +$DGL 0,58 + br $?L0066 ;[INF] 2, 3 +; line 287 : +; line 288 : default: +?L0068: +; line 289 : // フェードアウト +; line 290 : if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) +$DGL 0,62 + cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + bnc $?L0073 ;[INF] 2, 4 +; line 291 : { +??bb0B_led_pow_hotaru: +; line 292 : red_to = 2; +$DGL 0,64 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + movw !?L0055,ax ; red_to ;[INF] 3, 1 +??eb0B_led_pow_hotaru: +; line 293 : } +$DGL 0,65 + br $?L0066 ;[INF] 2, 3 +?L0073: +; line 294 : else +; line 295 : { +??bb0C_led_pow_hotaru: +; line 296 : blue_to = 2; +$DGL 0,68 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + movw !?L0054,ax ; blue_to ;[INF] 3, 1 +??eb0C_led_pow_hotaru: +; line 297 : } +; line 298 : break; +??eb08_led_pow_hotaru: +; line 299 : } +?L0066: +; line 300 : +; line 301 : if( ( LED_duty_pow_H == blue_to ) && ( LED_duty_pow_L == red +; _to ) ) +$DGL 0,73 + movw ax,TDR06 ;[INF] 2, 1 + cmpw ax,!?L0054 ; blue_to ;[INF] 3, 1 + bnz $?L0075 ;[INF] 2, 4 + movw ax,TDR07 ;[INF] 2, 1 + cmpw ax,!?L0055 ; red_to ;[INF] 3, 1 + sknz ;[INF] 2, 1 +; line 302 : { +??bb0D_led_pow_hotaru: +; line 303 : state += 1; +$DGL 0,75 + inc !?L0053 ; state ;[INF] 3, 2 +??eb0D_led_pow_hotaru: +; line 304 : } +?L0075: +; line 305 : return; +; line 306 : } +$DGL 0,78 +??ef_led_pow_hotaru: + ret ;[INF] 1, 6 +??ee_led_pow_hotaru: +; line 307 : +; line 308 : +; line 309 : +; line 310 : /* ======================================================== +; line 311 : * 割り込みそのものは使いません * +; line 312 : LED_Wifi 3 +; line 313 : todo 直書きの点滅間隔など +; line 314 : ======================================================== */ +; line 315 : void tsk_led_wifi( ) +; line 316 : { +_tsk_led_wifi: +$DGL 1,216 +??bf_tsk_led_wifi: +; line 317 : static u8 task_interval; +; line 318 : static u8 remain_wifi_tx; +; line 319 : static u8 state_wifi_tx; +; line 320 : static u8 flag_wifi_TX; +; line 321 : +; line 322 : +; line 323 : if( task_interval-- != 0 ) +$DGL 0,8 + mov a,!?L0079 ; task_interval ;[INF] 3, 1 + dec !?L0079 ; task_interval ;[INF] 3, 2 + cmp0 a ;[INF] 1, 1 + bnz $?L0089 ;[INF] 2, 4 +; line 324 : { +??bb00_tsk_led_wifi: +; line 325 : return; +??eb00_tsk_led_wifi: +; line 326 : } +; line 327 : +; line 328 : // 送信パルスのラッチ +; line 329 : if( vreg_ctr[VREG_C_LED_WIFI] == WIFI_LED_TXAUTO ) +$DGL 0,14 + cmp !_vreg_ctr+42,#02H ; 2 ;[INF] 4, 1 + bnz $?L0085 ;[INF] 2, 4 +; line 330 : { +??bb01_tsk_led_wifi: +; line 331 : if( WIFI_txLatch ) +$DGL 0,16 + bf IF2H.5,$?L0086 ;[INF] 4, 5 +; line 332 : { +??bb02_tsk_led_wifi: +; line 333 : WIFI_txLatch = 0; +$DGL 0,18 + clr1 IF2H.5 ;[INF] 3, 2 +; line 334 : flag_wifi_TX = 2; +$DGL 0,19 + mov !?L0082,#02H ; flag_wifi_TX,2 ;[INF] 4, 1 +??eb02_tsk_led_wifi: +; line 335 : } +; line 336 : } +$DGL 0,21 +??eb01_tsk_led_wifi: + br $?L0086 ;[INF] 2, 3 +?L0085: +; line 337 : else +; line 338 : { +??bb03_tsk_led_wifi: +; line 339 : flag_wifi_TX = 0; +$DGL 0,24 + clrb !?L0082 ; flag_wifi_TX ;[INF] 3, 1 +??eb03_tsk_led_wifi: +; line 340 : } +?L0086: +; line 341 : +; line 342 : +; line 343 : switch ( vreg_ctr[VREG_C_LED_WIFI] ) +$DGL 0,28 + mov x,!_vreg_ctr+42 ;[INF] 3, 1 + call !bs_S0172 ;[INF] 3, 3 + bz $?L0090 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0092 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0093 ;[INF] 2, 4 +; line 344 : { +??bb04_tsk_led_wifi: +; line 345 : case ( WIFI_LED_OFF ): +?L0090: +; line 346 : default: +; line 347 : LED_duty_WiFi = 0; +$DGL 0,32 + clrw ax ;[INF] 1, 1 + movw TDR03,ax ;[INF] 2, 1 +; line 348 : state_wifi_tx = 0; +$DGL 0,33 + clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 +; line 349 : remain_wifi_tx = 0; +$DGL 0,34 + clrb !?L0080 ; remain_wifi_tx ;[INF] 3, 1 +; line 350 : break; +$DGL 0,35 + ret ;[INF] 1, 6 +; line 351 : +; line 352 : case ( WIFI_LED_ON ): +?L0092: +; line 353 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,38 + call !bs_S0173 ;[INF] 3, 3 +; line 354 : state_wifi_tx = 0; +$DGL 0,39 + clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 +; line 355 : remain_wifi_tx = 0; +$DGL 0,40 + clrb !?L0080 ; remain_wifi_tx ;[INF] 3, 1 +; line 356 : break; +$DGL 0,41 + ret ;[INF] 1, 6 +; line 357 : +; line 358 : case ( WIFI_LED_TXAUTO ): +?L0093: +; line 359 : if( flag_wifi_TX != 0 ) // 短いパルスを捕まえるために、割 +; り込みフラグを見る +$DGL 0,44 + cmp0 !?L0082 ; flag_wifi_TX ;[INF] 3, 1 + bz $?L0096 ;[INF] 2, 4 +; line 360 : { +??bb05_tsk_led_wifi: +; line 361 : // 送信パターン +; line 362 : switch ( state_wifi_tx ) +$DGL 0,47 + mov x,!?L0081 ; state_wifi_tx ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0099 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bz $?L0099 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bnz $?L0100 ;[INF] 2, 4 +; line 363 : { +??bb06_tsk_led_wifi: +; line 364 : case ( 1 ): +?L0099: +; line 365 : case ( 3 ): +; line 366 : case ( 5 ): +; line 367 : LED_duty_WiFi = 0; +$DGL 0,52 + clrw ax ;[INF] 1, 1 + movw TDR03,ax ;[INF] 2, 1 +; line 368 : break; +$DGL 0,53 + br $?L0098 ;[INF] 2, 3 +; line 369 : default: +?L0100: +; line 370 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,55 + call !bs_S0173 ;[INF] 3, 3 +??eb06_tsk_led_wifi: +; line 371 : } +?L0098: +; line 372 : state_wifi_tx++; +$DGL 0,57 + inc !?L0081 ; state_wifi_tx ;[INF] 3, 2 +; line 373 : if( state_wifi_tx == 32 ) +$DGL 0,58 + cmp !?L0081,#020H ; state_wifi_tx,32 ;[INF] 4, 1 + bnz $?L0103 ;[INF] 2, 4 +; line 374 : { +??bb07_tsk_led_wifi: +; line 375 : state_wifi_tx = 0; +$DGL 0,60 + clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 +; line 376 : flag_wifi_TX -= 1; +$DGL 0,61 + dec !?L0082 ; flag_wifi_TX ;[INF] 3, 2 +??eb07_tsk_led_wifi: +; line 377 : } +?L0103: +; line 378 : task_interval = 22; +$DGL 0,63 + mov !?L0079,#016H ; task_interval,22 ;[INF] 4, 1 +; line 379 : return; +$DGL 0,64 + ret ;[INF] 1, 6 +??eb05_tsk_led_wifi: +; line 380 : } +?L0096: +; line 381 : else +; line 382 : { +??bb08_tsk_led_wifi: +; line 383 : // 送信フラグ待ち +; line 384 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,69 + call !bs_S0173 ;[INF] 3, 3 +; line 385 : task_interval = 200; +$DGL 0,70 + mov !?L0079,#0C8H ; task_interval,200 ;[INF] 4, 1 +; line 386 : return; +??eb08_tsk_led_wifi: +; line 387 : } +; line 388 : break; +??eb04_tsk_led_wifi: +; line 389 : +; line 390 : } +?L0089: +; line 391 : } +$DGL 0,76 +??ef_tsk_led_wifi: + ret ;[INF] 1, 6 +??ee_tsk_led_wifi: +; line 392 : +; line 393 : +; line 394 : +; line 395 : +; line 396 : /* ======================================================== +; line 397 : * 割り込みそのものは使いません * +; line 398 : LED_Wifi2 P24 （未） +; line 399 : ======================================================== */ +; line 400 : void tsk_led_notify( ) +; line 401 : { +_tsk_led_notify: +$DGL 1,262 + push hl ;[INF] 1, 1 +??bf_tsk_led_notify: +; line 402 : static u8 task_interval; +; line 403 : static u8 flg_char_space; +; line 404 : static u8 state_notify_led; // 点灯パターンの進行具合 +; line 405 : static u8 flag_wifi_TX; +; line 406 : +; line 407 : +; line 408 : if( task_interval-- != 0 ) +$DGL 0,8 + mov a,!?L0107 ; task_interval ;[INF] 3, 1 + dec !?L0107 ; task_interval ;[INF] 3, 2 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 + br !?L0135 ;[INF] 3, 3 +; line 409 : { +??bb00_tsk_led_notify: +; line 410 : return; +??eb00_tsk_led_notify: +; line 411 : } +; line 412 : +; line 413 : switch ( vreg_ctr[VREG_C_LED_NOTIFY] ) +$DGL 0,13 + mov x,!_vreg_ctr+45 ;[INF] 3, 1 + call !bs_S0172 ;[INF] 3, 3 + bz $?L0114 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0116 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0117 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0118 ;[INF] 2, 4 +; line 414 : { +??bb01_tsk_led_notify: +; line 415 : case ( NOTIFY_LED_OFF ): +?L0114: +; line 416 : default: +; line 417 : LED_duty_NOTIFY = 0; +$DGL 0,17 + clrw ax ;[INF] 1, 1 + movw TDR05,ax ;[INF] 2, 1 +; line 418 : state_notify_led = 0; +$DGL 0,18 + clrb !?L0109 ; state_notify_led ;[INF] 3, 1 +; line 419 : flg_char_space = 0; +$DGL 0,19 + clrb !?L0108 ; flg_char_space ;[INF] 3, 1 +; line 420 : break; +$DGL 0,20 + br !?L0135 ;[INF] 3, 3 +; line 421 : +; line 422 : case ( NOTIFY_LED_ON ): +?L0116: +; line 423 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,23 + call !bs_S0174 ;[INF] 3, 3 +; line 424 : state_notify_led = 0; +$DGL 0,24 + clrb !?L0109 ; state_notify_led ;[INF] 3, 1 +; line 425 : flg_char_space = 0; +$DGL 0,25 + clrb !?L0108 ; flg_char_space ;[INF] 3, 1 +; line 426 : break; +$DGL 0,26 + br !?L0135 ;[INF] 3, 3 +; line 427 : +; line 428 : case ( NOTIFY_LED_PTN0 ): +?L0117: +; line 429 : // ゆっくりバースト +; line 430 : switch ( state_notify_led ) +$DGL 0,30 + mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0122 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bz $?L0122 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bnz $?L0123 ;[INF] 2, 4 +; line 431 : { +??bb02_tsk_led_notify: +; line 432 : case ( 1 ): +?L0122: +; line 433 : case ( 3 ): +; line 434 : case ( 5 ): +; line 435 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,35 + call !bs_S0174 ;[INF] 3, 3 +; line 436 : break; +$DGL 0,36 + br $?L0121 ;[INF] 2, 3 +; line 437 : default: +?L0123: +; line 438 : LED_duty_NOTIFY = 0; +$DGL 0,38 + clrw ax ;[INF] 1, 1 + movw TDR05,ax ;[INF] 2, 1 +??eb02_tsk_led_notify: +; line 439 : } +?L0121: +; line 440 : state_notify_led++; +$DGL 0,40 + inc !?L0109 ; state_notify_led ;[INF] 3, 2 +; line 441 : if( state_notify_led == 16 ) +$DGL 0,41 + cmp !?L0109,#010H ; state_notify_led,16 ;[INF] 4, 1 + sknz ;[INF] 2, 1 +; line 442 : { +??bb03_tsk_led_notify: +; line 443 : state_notify_led = 0; +$DGL 0,43 + clrb !?L0109 ; state_notify_led ;[INF] 3, 1 +??eb03_tsk_led_notify: +; line 444 : } +?L0126: +; line 445 : task_interval = 50; +$DGL 0,45 + mov !?L0107,#032H ; task_interval,50 ;[INF] 4, 1 +; line 446 : return; +$DGL 0,46 + br $?L0135 ;[INF] 2, 3 +; line 447 : +; line 448 : case ( NOTIFY_LED_PTN1 ): +?L0118: +; line 449 : // データテーブルに従って点滅 +; line 450 : { +??bb04_tsk_led_notify: +; line 451 : u8 dat; +; line 452 : +; line 453 : task_interval = MSG_SPD; // 共通のため。場合によって +; 上書き +$DGL 0,53 + mov !?L0107,#03CH ; task_interval,60 ;[INF] 4, 1 +; line 454 : +; line 455 : if( flg_char_space != 0 ) +$DGL 0,55 + cmp0 !?L0108 ; flg_char_space ;[INF] 3, 1 + bz $?L0128 ;[INF] 2, 4 +; line 456 : { +??bb05_tsk_led_notify: +; line 457 : LED_duty_NOTIFY = 0; +$DGL 0,57 + clrw ax ;[INF] 1, 1 + movw TDR05,ax ;[INF] 2, 1 +; line 458 : flg_char_space = 0; +$DGL 0,58 + clrb !?L0108 ; flg_char_space ;[INF] 3, 1 +; line 459 : return; +$DGL 0,59 + br $?L0135 ;[INF] 2, 3 +??eb05_tsk_led_notify: +; line 460 : } +?L0128: +; line 461 : +; line 462 : // データバッファの見る位置の更新 +; line 463 : dat = ( MSG_MAIL[state_notify_led / 4] << ( ( state_ +; notify_led % 4 ) * 2 ) ) & 0xC0; +$DGL 0,63 + mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + mov x,#04H ; 4 ;[INF] 2, 1 + call !@@isrem ;[INF] 3, 3 + addw ax,ax ;[INF] 1, 1 + xch a,x ;[INF] 1, 1 + mov c,a ;[INF] 1, 1 + xch a,x ;[INF] 1, 1 + mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + sarw ax,2 ;[INF] 2, 1 + addw ax,#loww (_MSG_MAIL) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,[de] ;[INF] 1, 1 + sarw ax,8 ;[INF] 2, 1 + cmp0 c ;[INF] 1, 1 + bz $?L0130 ;[INF] 2, 4 +?L0131: + addw ax,ax ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $?L0131 ;[INF] 2, 4 +?L0130: + mov a,x ;[INF] 1, 1 + and a,#0C0H ; 192 ;[INF] 2, 1 + mov l,a ;[INF] 1, 1 +; line 464 : if( dat == 0 ) +$DGL 0,64 + cmp0 a ;[INF] 1, 1 + bnz $?L0132 ;[INF] 2, 4 +; line 465 : { +??bb06_tsk_led_notify: +; line 466 : state_notify_led = 0; +$DGL 0,66 + clrb !?L0109 ; state_notify_led ;[INF] 3, 1 +??eb06_tsk_led_notify: +; line 467 : } +$DGL 0,67 + br $?L0133 ;[INF] 2, 3 +?L0132: +; line 468 : else +; line 469 : { +??bb07_tsk_led_notify: +; line 470 : state_notify_led += 1; +$DGL 0,70 + inc !?L0109 ; state_notify_led ;[INF] 3, 2 +??eb07_tsk_led_notify: +; line 471 : } +?L0133: +; line 472 : +; line 473 : flg_char_space = 1; +$DGL 0,73 + oneb !?L0108 ; flg_char_space ;[INF] 3, 1 +; line 474 : if(( dat & 0b10000000 ) != 0 ) +$DGL 0,74 + mov a,l ;[INF] 1, 1 + and a,#080H ; 128 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0134 ;[INF] 2, 4 +; line 475 : { +??bb08_tsk_led_notify: +; line 476 : // 点灯はさせる +; line 477 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,77 + call !bs_S0174 ;[INF] 3, 3 +; line 478 : if(( dat & 0b01000000 ) == 0 ) +$DGL 0,78 + mov a,l ;[INF] 1, 1 + and a,#040H ; 64 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0135 ;[INF] 2, 4 +; line 479 : { +??bb09_tsk_led_notify: +??eb09_tsk_led_notify: +; line 480 : // 短 +; line 481 : // nothing to do +; line 482 : } +; line 483 : else +; line 484 : { +??bb0A_tsk_led_notify: +; line 485 : // 長 +; line 486 : task_interval = ( MSG_SPD * 3 ); +$DGL 0,86 + mov !?L0107,#0B4H ; task_interval,180 ;[INF] 4, 1 +??eb0A_tsk_led_notify: +; line 487 : } +; line 488 : // 次は単語間休み、とかの判定をさせたかったが +; line 489 : /// １バイトに２ビットずつデータが並んでおり、次 +; のバイトに +; line 490 : /// またがるようなときが面倒なのでやめる +; line 491 : return; +$DGL 0,91 + br $?L0135 ;[INF] 2, 3 +??eb08_tsk_led_notify: +; line 492 : } +?L0134: +; line 493 : else +; line 494 : { +??bb0B_tsk_led_notify: +; line 495 : if(( dat & 0b01000000 ) == 0 ) +$DGL 0,95 + mov a,l ;[INF] 1, 1 + and a,#040H ; 64 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + sknz ;[INF] 2, 1 +; line 496 : { +??bb0C_tsk_led_notify: +; line 497 : // 一文終了 +; line 498 : task_interval = ( MSG_SPD * 3 ); +$DGL 0,98 + mov !?L0107,#0B4H ; task_interval,180 ;[INF] 4, 1 +??eb0C_tsk_led_notify: +; line 499 : } +; line 500 : else +; line 501 : { +??bb0D_tsk_led_notify: +??eb0D_tsk_led_notify: +; line 502 : // 単語間 +; line 503 : // nothing to do +; line 504 : } +; line 505 : return; +??eb0B_tsk_led_notify: +; line 506 : } +?L0135: +??eb04_tsk_led_notify: +; line 507 : } +??eb01_tsk_led_notify: +; line 508 : } +; line 509 : } +$DGL 0,109 +??ef_tsk_led_notify: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_led_notify: +; line 510 : +; line 511 : +; line 512 : +; line 513 : +; line 514 : /******************************************************//** +; line 515 : LED_Cam TO02 +; line 516 : \n BLINK,*_PLUSE の時は、1周期分は必ずその状態になります。 +; line 517 : \n その間に OFF→BLINK などされると、OFFが無視されます。 +; line 518 : *********************************************************/ +; line 519 : void tsk_led_cam( ) +; line 520 : { +_tsk_led_cam: +$DGL 1,330 +??bf_tsk_led_cam: +; line 521 : static u8 state_led_cam = 0; +; line 522 : static u8 task_interval; +; line 523 : static u8 state_led_cam_twl; +; line 524 : +; line 525 : if( task_interval != 0 ) +$DGL 0,6 + cmp0 !?L0143 ; task_interval ;[INF] 3, 1 + bz $?L0145 ;[INF] 2, 4 +; line 526 : { +??bb00_tsk_led_cam: +; line 527 : task_interval -= 1; +$DGL 0,8 + dec !?L0143 ; task_interval ;[INF] 3, 2 +; line 528 : return; +$DGL 0,9 + ret ;[INF] 1, 6 +??eb00_tsk_led_cam: +; line 529 : } +?L0145: +; line 530 : +; line 531 : // ブリンクのように待たせたいとき以外は毎週起動する +; line 532 : // (レジスタの変更にすぐに反応する) +; line 533 : +; line 534 : switch ( vreg_ctr[VREG_C_LED_CAM] ) +$DGL 0,15 + mov x,!_vreg_ctr+43 ;[INF] 3, 1 + call !bs_S0172 ;[INF] 3, 3 + bz $?L0148 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0151 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0150 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0154 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0152 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0153 ;[INF] 2, 4 +; line 535 : { +??bb01_tsk_led_cam: +; line 536 : case ( CAM_LED_OFF ): +?L0148: +; line 537 : default: +; line 538 : LED_duty_CAM = 0; +$DGL 0,19 + clrw ax ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 +; line 539 : state_led_cam = 0; +$DGL 0,20 + clrb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 540 : break; +$DGL 0,21 + ret ;[INF] 1, 6 +; line 541 : +; line 542 : case ( CAM_LED_ON ): +?L0150: +; line 543 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,24 + call !bs_S0175 ;[INF] 3, 3 +; line 544 : state_led_cam = 0; +$DGL 0,25 + clrb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 545 : break; +$DGL 0,26 + ret ;[INF] 1, 6 +; line 546 : +; line 547 : case ( CAM_LED_BLINK ): +?L0151: +; line 548 : if( state_led_cam == 0 ) +$DGL 0,29 + cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + bnz $?L0157 ;[INF] 2, 4 +; line 549 : { +??bb02_tsk_led_cam: +; line 550 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,31 + call !bs_S0175 ;[INF] 3, 3 +; line 551 : state_led_cam = 1; +$DGL 0,32 + oneb !?L0142 ; state_led_cam ;[INF] 3, 1 +??eb02_tsk_led_cam: +; line 552 : } +$DGL 0,33 + br $?L0158 ;[INF] 2, 3 +?L0157: +; line 553 : else +; line 554 : { +??bb03_tsk_led_cam: +; line 555 : LED_duty_CAM = 0; +$DGL 0,36 + clrw ax ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 +; line 556 : state_led_cam = 0; +$DGL 0,37 + clrb !?L0142 ; state_led_cam ;[INF] 3, 1 +??eb03_tsk_led_cam: +; line 557 : } +?L0158: +; line 558 : task_interval = 250; +$DGL 0,39 + mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 +; line 559 : break; +$DGL 0,40 + ret ;[INF] 1, 6 +; line 560 : +; line 561 : case ( CAM_LED_ON_PLUSE ): +?L0152: +; line 562 : if( state_led_cam == 0 ) +$DGL 0,43 + cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + bnz $?L0159 ;[INF] 2, 4 +; line 563 : { +??bb04_tsk_led_cam: +; line 564 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,45 + call !bs_S0175 ;[INF] 3, 3 +; line 565 : state_led_cam = 1; +$DGL 0,46 + oneb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 566 : task_interval = 250; +$DGL 0,47 + mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 +??eb04_tsk_led_cam: +; line 567 : } +$DGL 0,48 + ret ;[INF] 1, 6 +?L0159: +; line 568 : else +; line 569 : { +??bb05_tsk_led_cam: +; line 570 : vreg_ctr[VREG_C_LED_CAM] = CAM_LED_OFF; +$DGL 0,51 + clrb !_vreg_ctr+43 ;[INF] 3, 1 +??eb05_tsk_led_cam: +; line 571 : } +; line 572 : break; +$DGL 0,53 + ret ;[INF] 1, 6 +; line 573 : +; line 574 : case ( CAM_LED_OFF_PLUSE ): +?L0153: +; line 575 : if( state_led_cam == 0 ) +$DGL 0,56 + cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + bnz $?L0161 ;[INF] 2, 4 +; line 576 : { +??bb06_tsk_led_cam: +; line 577 : LED_duty_CAM = 0; +$DGL 0,58 + clrw ax ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 +; line 578 : state_led_cam = 1; +$DGL 0,59 + oneb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 579 : task_interval = 250; +$DGL 0,60 + mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 +??eb06_tsk_led_cam: +; line 580 : } +$DGL 0,61 + ret ;[INF] 1, 6 +?L0161: +; line 581 : else +; line 582 : { +??bb07_tsk_led_cam: +; line 583 : vreg_ctr[VREG_C_LED_CAM] = CAM_LED_ON; +$DGL 0,64 + mov !_vreg_ctr+43,#02H ; 2 ;[INF] 4, 1 +??eb07_tsk_led_cam: +; line 584 : } +; line 585 : break; +$DGL 0,66 + ret ;[INF] 1, 6 +; line 586 : +; line 587 : case ( CAM_LED_BY_TWL ): +?L0154: +; line 588 : switch ( vreg_twl[ REG_TWL_INT_ADRS_CAM ] ){ // switchの +; ネストとか… +$DGL 0,69 + mov x,!_vreg_twl+5 ;[INF] 3, 1 + call !bs_S0172 ;[INF] 3, 3 + bz $?L0164 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0166 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0165 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + br $?L0166 ;[INF] 2, 3 +??bb08_tsk_led_cam: +; line 589 : case( TWL_CAMLED_OFF ): +?L0164: +; line 590 : LED_duty_CAM = 0; +$DGL 0,71 + clrw ax ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 +; line 591 : state_led_cam = 0; +$DGL 0,72 + clrb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 592 : break; +$DGL 0,73 + ret ;[INF] 1, 6 +; line 593 : +; line 594 : case( TWL_CAMLED_BLINK ): +?L0165: +; line 595 : if( state_led_cam == 0 ) +$DGL 0,76 + cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + bnz $?L0170 ;[INF] 2, 4 +; line 596 : { +??bb09_tsk_led_cam: +; line 597 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,78 + call !bs_S0175 ;[INF] 3, 3 +; line 598 : state_led_cam = 1; +$DGL 0,79 + oneb !?L0142 ; state_led_cam ;[INF] 3, 1 +??eb09_tsk_led_cam: +; line 599 : } +$DGL 0,80 + br $?L0171 ;[INF] 2, 3 +?L0170: +; line 600 : else +; line 601 : { +??bb0A_tsk_led_cam: +; line 602 : LED_duty_CAM = 0; +$DGL 0,83 + clrw ax ;[INF] 1, 1 + movw TDR02,ax ;[INF] 2, 1 +; line 603 : state_led_cam = 0; +$DGL 0,84 + clrb !?L0142 ; state_led_cam ;[INF] 3, 1 +??eb0A_tsk_led_cam: +; line 604 : } +?L0171: +; line 605 : task_interval = 250; +$DGL 0,86 + mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 +; line 606 : break; +$DGL 0,87 + ret ;[INF] 1, 6 +; line 607 : +; line 608 : case( TWL_CAMLED_ON ): +?L0166: +; line 609 : case( TWL_CAMLED_DEF_ON ): +; line 610 : default: +; line 611 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; +$DGL 0,92 + call !bs_S0175 ;[INF] 3, 3 +; line 612 : state_led_cam = 1; +$DGL 0,93 + oneb !?L0142 ; state_led_cam ;[INF] 3, 1 +; line 613 : break; +??eb08_tsk_led_cam: +; line 614 : } +?L0163: +??eb01_tsk_led_cam: +; line 615 : } +; line 616 : return; +; line 617 : } +$DGL 0,98 +??ef_tsk_led_cam: + ret ;[INF] 1, 6 +??ee_tsk_led_cam: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c +; +; $FUNC LED_init(40) +; void=(void) +; CODE SIZE= 83 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 0 bytes +; +; $FUNC LED_stop(87) +; void=(void) +; CODE SIZE= 15 bytes, CLOCK_SIZE= 12 clocks, STACK_SIZE= 0 bytes +; +; $FUNC tsk_led_pow(120) +; void=(void) +; CODE SIZE= 99 bytes, CLOCK_SIZE= 133 clocks, STACK_SIZE= 4 bytes +; +; $CALL led_pow_hotaru(128) +; void=(void) +; +; $CALL led_pow_normal(132) +; void=(void) +; +; $CALL led_pow_hotaru(147) +; void=(void) +; +; $CALL led_pow_normal(152) +; void=(void) +; +; $FUNC led_pow_normal(174) +; void=(void) +; CODE SIZE= 113 bytes, CLOCK_SIZE= 104 clocks, STACK_SIZE= 0 bytes +; +; $FUNC led_pow_hotaru(229) +; void=(void) +; CODE SIZE= 149 bytes, CLOCK_SIZE= 126 clocks, STACK_SIZE= 0 bytes +; +; $FUNC tsk_led_wifi(316) +; void=(void) +; CODE SIZE= 123 bytes, CLOCK_SIZE= 159 clocks, STACK_SIZE= 4 bytes +; +; $FUNC tsk_led_notify(401) +; void=(void) +; CODE SIZE= 200 bytes, CLOCK_SIZE= 208 clocks, STACK_SIZE= 6 bytes +; +; $FUNC tsk_led_cam(520) +; void=(void) +; CODE SIZE= 166 bytes, CLOCK_SIZE= 258 clocks, STACK_SIZE= 4 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/loader.asm b/branches/0.10(X3)/inter_asm/loader.asm new file mode 100644 index 0000000..4f457b6 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/loader.asm @@ -0,0 +1,1044 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no loader.c +; In-file : loader.c +; Asm-file : inter_asm\loader.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, loader.c +$DGS MOD_NAM, loader, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS GLV_SYM, _main, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 073H, 00H, 00H +$DGS BEG_FUN, ??bf_main, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 045H, 02H, 045H +$DGS BEG_BLK, ??bb00_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 047H +$DGS BEG_BLK, ??bb01_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 04BH +$DGS END_BLK, ??eb01_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb02_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 04FH +$DGS END_BLK, ??eb02_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS BEG_BLK, ??bb03_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 055H +$DGS REG_VAR, _pwup_delay0, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 018H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS REG_VAR, _pwup_delay1, 07H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 019H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb04_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 057H +$DGS BEG_BLK, ??bb05_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01FH, 00H, 05FH +$DGS END_BLK, ??eb05_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 021H +$DGS END_BLK, ??eb04_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS END_BLK, ??eb03_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 027H +$DGS BEG_BLK, ??bb06_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 065H +$DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 02BH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS REG_VAR, _comp, 07H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 02CH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb07_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 031H, 00H, 069H +$DGS END_BLK, ??eb07_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 033H +$DGS BEG_BLK, ??bb08_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 036H, 00H, 00H +$DGS END_BLK, ??eb08_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03AH +$DGS END_BLK, ??eb06_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03BH +$DGS END_BLK, ??eb00_main, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03FH +$DGS END_FUN, ??ef_main, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 040H +$DGS GLV_SYM, _int_kr, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 079H, 00H, 00H +$DGS BEG_FUN, ??bf_int_kr, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 08CH, 00H, 079H +$DGS END_FUN, ??ef_int_kr, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02H +$DGS GLV_SYM, _intp4, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H +$DGS BEG_FUN, ??bf_intp4, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 095H, 00H, 07FH +$DGS END_FUN, ??ef_intp4, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02H +$DGS GLV_SYM, _intp5, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 085H, 00H, 00H +$DGS BEG_FUN, ??bf_intp5, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09DH, 00H, 085H +$DGS END_FUN, ??ef_intp5, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02H +$DGS GLV_SYM, _hdwinit, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 08BH, 00H, 00H +$DGS BEG_FUN, ??bf_hdwinit, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0A4H, 00H, 08BH +$DGS END_FUN, ??ef_hdwinit, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 015H +$DGS STA_SYM, _hdwinit2, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H +$DGS BEG_FUN, ??bf_hdwinit2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0BCH, 00H, 08FH +$DGS BEG_BLK, ??bb00_hdwinit2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 093H +$DGS END_BLK, ??eb00_hdwinit2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb01_hdwinit2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 00H +$DGS END_BLK, ??eb01_hdwinit2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS END_FUN, ??ef_hdwinit2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0D1H +$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _firm_restore, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _main_loop, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _WDT_Restart + EXTRN _system_status + EXTRN _vreg_ctr + EXTRN _firm_restore + EXTRN _main_loop + PUBLIC _main + PUBLIC _int_kr + PUBLIC _intp4 + PUBLIC _intp5 + PUBLIC _hdwinit + +@@BITS BSEG + +@@CNST CSEG MIRRORP + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +LDR_CNSL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : /* ======================================================== +; line 2 : MCU CTR BSR +; line 3 : 2009/03/30 +; line 4 : 開発技術部 藤田 +; line 5 : +; line 6 : ブートローダー部 +; line 7 : ホストの通信と、自己書き換え、ファームのチェックを行う。 +; line 8 : +; line 9 : ======================================================== */ +; line 10 : #pragma SFR +; line 11 : #pragma di +; line 12 : #pragma ei +; line 13 : #pragma nop +; line 14 : #pragma stop +; line 15 : #pragma halt +; line 16 : #pragma opc +; line 17 : +; line 18 : +; line 19 : #include "incs_loader.h" +; line 20 : +; line 21 : #include "fsl.h" +; line 22 : #include "fsl_user.h" +; line 23 : +; line 24 : #include "i2c_ctr.h" +; line 25 : #include "i2c_mcu.h" +; line 26 : #include "pm.h" +; line 27 : #include "rtc.h" +; line 28 : +; line 29 : #include "reboot.h" +; line 30 : +; line 31 : +; line 32 : // ======================================================== +; line 33 : #if (FSL_DATA_BUFFER_SIZE>0) +; line 34 : fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE]; +; line 35 : #endif +; line 36 : +; line 37 : +; line 38 : +; line 39 : #ifdef FSL_INT_BACKUP +; line 40 : static fsl_u08 fsl_MK0L_bak_u08; /* if (interrupt back +; up required) */ +; line 41 : static fsl_u08 fsl_MK0H_bak_u08; /* { +; */ +; line 42 : static fsl_u08 fsl_MK1L_bak_u08; /* reserve space fo +; r backup information */ +; line 43 : static fsl_u08 fsl_MK1H_bak_u08; /* of interrupt mas +; k flags */ +; line 44 : static fsl_u08 fsl_MK2L_bak_u08; /* +; */ +; line 45 : static fsl_u08 fsl_MK2H_bak_u08; /* } +; */ +; line 46 : #endif +; line 47 : +; line 48 : +; line 49 : +; line 50 : // magic.c の記述と違わないように注意！ +; line 51 : #define MGC_LOAD 0x0FF6 +; line 52 : #define MGC_FOOT 0x4FF6 +; line 53 : +; line 54 : +; line 55 : +; line 56 : // ======================================================== +; line 57 : void FSL_Open( void ); +; line 58 : void FSL_Close( void ); +; line 59 : void hdwinit( void ); +; line 60 : void power_save( ); +; line 61 : static void hdwinit2( ); +; line 62 : +; line 63 : extern void main_loop( ); +; line 64 : +; line 65 : +; line 66 : +; line 67 : // ======================================================== +; line 68 : void main( ) +; line 69 : { + +LDR_CODE CSEG BASE +_main: +$DGL 1,65 + push hl ;[INF] 1, 1 +??bf_main: +; line 70 : while( 1 ) +?L0003: +; line 71 : { +??bb00_main: +; line 72 : WDT_Restart( ); +$DGL 0,4 + call !_WDT_Restart ;[INF] 3, 3 +; line 73 : if( RTCEN ) +$DGL 0,5 + push hl ;[INF] 1, 1 + movw hl,#0F0H ; 240 ;[INF] 3, 1 + mov1 CY,[hl].7 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0005 ;[INF] 2, 4 +; line 74 : { +??bb01_main: +; line 75 : system_status.reboot = 1; +$DGL 0,7 + set1 !_system_status+2.3 ;[INF] 4, 2 +??eb01_main: +; line 76 : } +$DGL 0,8 + br $?L0008 ;[INF] 2, 3 +?L0005: +; line 77 : else if( ( RESF & 0x10 ) != 0) // WDRF,WDTでリセット +$DGL 0,9 + mov a,#010H ; 16 ;[INF] 2, 1 + and a,!RESF ;[INF] 3, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0007 ;[INF] 2, 4 +; line 78 : { +??bb02_main: +; line 79 : system_status.reboot = 1; +$DGL 0,11 + set1 !_system_status+2.3 ;[INF] 4, 2 +; line 80 : #ifdef _PMIC_TWL_ +; line 81 : // 暴走してしまうので再起動させる +; line 82 : PM_reset_ast(); +; line 83 : /// hdwinit2ないでリセット解除される。続きに続行して +; よい（頭痛が痛い的） +; line 84 : #endif +; line 85 : vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_ +; RESET; +$DGL 0,17 + set1 !_vreg_ctr+2.1 ;[INF] 4, 2 +; line 86 : // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); +; line 87 : // ↑I2Cの初期化後に行う +; line 88 : hdwinit2( ); +$DGL 0,20 + call !_hdwinit2 ;[INF] 3, 3 +??eb02_main: +; line 89 : } +$DGL 0,21 + br $?L0008 ;[INF] 2, 3 +?L0007: +; line 90 : else +; line 91 : { +??bb03_main: +; line 92 : u8 pwup_delay0 = 0; +$DGL 0,24 + movw hl,#00H ; 0 ;[INF] 3, 1 +; line 93 : u8 pwup_delay1 = 0; +; line 94 : +; line 95 : do +?L0009: +; line 96 : { // 電池接続時、16ms待ってみる(チ +; ャタリング対策) +??bb04_main: +; line 97 : pwup_delay0 += 1; +$DGL 0,29 + inc l ;[INF] 1, 1 +; line 98 : do +?L0012: +; line 99 : { +??bb05_main: +; line 100 : pwup_delay1 += 1; +$DGL 0,32 + inc h ;[INF] 1, 1 +??eb05_main: +; line 101 : } +; line 102 : while( pwup_delay1 != 0 ); // u16にするとコ +; ンパイラが怒るんだが…。 +$DGL 0,34 + mov a,h ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0012 ;[INF] 2, 4 +??eb04_main: +; line 103 : } +; line 104 : while( pwup_delay0 != 0 ); +$DGL 0,36 + mov a,l ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0009 ;[INF] 2, 4 +; line 105 : +; line 106 : hdwinit2( ); +$DGL 0,38 + call !_hdwinit2 ;[INF] 3, 3 +??eb03_main: +; line 107 : } +?L0008: +; line 108 : +; line 109 : // ファームの整合性チェック // +; line 110 : { +??bb06_main: +; line 111 : u8 i; +; line 112 : u8 comp = 0; +$DGL 0,44 + movw hl,#00H ; 0 ;[INF] 3, 1 +; line 113 : +; line 114 : // ローダーと本体は同じバージョンか？ +; line 115 : /// 次へのアップデートの途中で終わってないか？ +; line 116 : for( i = 0; i < sizeof( __TIME__ ); i++ ) // si +; zeof( __TIME__ ) = 8 らし +$DGL 0,48 +?L0015: + mov a,l ;[INF] 1, 1 + cmp a,#09H ; 9 ;[INF] 2, 1 + bnc $?L0016 ;[INF] 2, 4 +; line 117 : { +??bb07_main: +; line 118 : comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( +; u8 * )( MGC_FOOT + i ) ) ? 0 : 1; +$DGL 0,50 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + addw ax,#0FF6H ; 4086 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + sar a,7 ;[INF] 2, 1 + mov ES,a ;[INF] 2, 1 + pop de ;[INF] 1, 1 + mov a,ES:[de] ;[INF] 2, 2 + mov c,a ;[INF] 1, 1 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + addw ax,#04FF6H ; 20470 ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,[de] ;[INF] 1, 1 + cmp c,a ;[INF] 2, 1 + bnz $?L0018 ;[INF] 2, 4 + clrw ax ;[INF] 1, 1 + br $?L0019 ;[INF] 2, 3 +?L0018: + onew ax ;[INF] 1, 1 +?L0019: + mov a,x ;[INF] 1, 1 + add h,a ;[INF] 2, 1 +??eb07_main: +; line 119 : } +$DGL 0,51 + inc l ;[INF] 1, 1 + br $?L0015 ;[INF] 2, 3 +?L0016: +; line 120 : +; line 121 : if( comp != 0 ) +$DGL 0,53 + mov a,h ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 +; line 122 : { +??bb08_main: +; line 123 : // ファームリストアを試みる +; line 124 : firm_restore( ); +$DGL 0,56 + call !_firm_restore ;[INF] 3, 3 +??eb08_main: +; line 125 : // 帰ってこない。リセットをかける。 +; line 126 : } +?L0020: +??eb06_main: +; line 127 : } +; line 128 : +; line 129 : // 通常運転 +; line 130 : main_loop( ); +$DGL 0,62 + call !_main_loop ;[INF] 3, 3 +??eb00_main: +; line 131 : } +$DGL 0,63 + br $?L0003 ;[INF] 2, 3 +; line 132 : } +$DGL 0,64 +??ef_main: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_main: +; line 133 : +; line 134 : +; line 135 : +; line 136 : /* ======================================================== +; line 137 : キーリターン割り込み +; line 138 : ======================================================== */ +; line 139 : __interrupt void int_kr( ) +; line 140 : { + +@@BASE CSEG BASE +_int_kr: +$DGL 1,115 +??bf_int_kr: +; line 141 : } +$DGL 0,2 +??ef_int_kr: + reti ;[INF] 2, 6 +??ee_int_kr: +; line 142 : +; line 143 : +; line 144 : +; line 145 : /* ======================================================== +; line 146 : ext dc +; line 147 : ======================================================== */ +; line 148 : __interrupt void intp4( ) +; line 149 : { +_intp4: +$DGL 1,121 +??bf_intp4: +; line 150 : } +$DGL 0,2 +??ef_intp4: + reti ;[INF] 2, 6 +??ee_intp4: +; line 151 : +; line 152 : +; line 153 : /* ======================================================== +; line 154 : shell close +; line 155 : ======================================================== */ +; line 156 : __interrupt void intp5( ) +; line 157 : { +_intp5: +$DGL 1,127 +??bf_intp5: +; line 158 : } +$DGL 0,2 +??ef_intp5: + reti ;[INF] 2, 6 +??ee_intp5: +; line 159 : +; line 160 : +; line 161 : +; line 162 : // ======================================================== +; line 163 : void hdwinit( void ) +; line 164 : { // スタートアップルーチンが勝手に +; 呼びます + +LDR_CODE CSEG BASE +_hdwinit: +$DGL 1,133 + di ;[INF] 3, 4 +??bf_hdwinit: +; line 165 : DI( ); /* マスタ割り込み禁止 */ +; line 166 : +; line 167 : CMC = 0b00010110; /* X1発振せず(入力ポート)、XT1使用 +; 、推奨の推奨で超低電力発振 */ +$DGL 0,4 + mov CMC,#016H ; 22 ;[INF] 3, 1 +; line 168 : CSC = 0b10000000; /* X1発振なし、XT1発振あり、高速内 +; 蔵発振動作 */ +$DGL 0,5 + mov CSC,#080H ; 128 ;[INF] 3, 1 +; line 169 : #ifdef _MCU_BSR_ +; line 170 : OSMC = 0x01; /* 隠しレジスタ */ +$DGL 0,7 + oneb !OSMC ;[INF] 3, 1 +; line 171 : #endif +; line 172 : #ifdef _OVERCLOCK_ +; line 173 : CKC = 0b00001000; /* CPU/周辺クロック=fMAIN、fMAIN= +; fMX、fCLK=fMX */ +$DGL 0,10 + mov CKC,#08H ; 8 ;[INF] 3, 1 +; line 174 : #else +; line 175 : // CKC デフォルトでよい +; line 176 : #endif +; line 177 : +; line 178 : /*--- 低電圧検出回路の設定 ---*/ +; line 179 : /* リセット解除時のデフォルトは、オプション・バイトにて指定さ +; れる */ +; line 180 : LVIS = 0b00000000; /* VLVI = 4.22±0.1V */ +$DGL 0,17 + clrb !LVIS ;[INF] 3, 1 +; line 181 : LVIM = 0b00000000; /* LVI動作禁止 */ +$DGL 0,18 + clrb !LVIM ;[INF] 3, 1 +; line 182 : /* 電源電圧(VDD)＜検出電圧(VLVI)時に割込発生 */ +; line 183 : /* 電源電圧(VDD)≧検出電圧 +; line 12 : +; line 13 : #include "accero.h" +; line 14 : #include "pedometer.h" +; line 15 : +; line 16 : +; line 17 : static void hosu_increment(); +; line 18 : u16 get_long_hour(); +; line 19 : +; line 20 : +; line 21 : +; line 22 : extern u16 pool[]; +; line 23 : +; line 24 : +; line 25 : +; line 26 : /*========================================================= +; line 27 : 　歩数計 +; line 28 : ========================================================*/ +; line 29 : void pedometer() +; line 30 : { + +ROM_CODE CSEG BASE +_pedometer: +$DGL 1,29 + push hl ;[INF] 1, 1 + subw sp,#024H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_pedometer: +; line 31 : static s16 th_H = 15000; // 閾値。暫定。動的変更とかしたい… +; ので変数 +; line 32 : static s16 th_L = 11000; +; line 33 : static u16 acc_norm[3]; // 加速度の大きさのヒストリ。数字が大 +; きい方が古い +; line 34 : static u16 acc_norm_temp; +; line 35 : static u8 interval_hh; // 山-山間の時間。短過ぎたらはじく。 +; line 36 : static u8 time_l; // 前回の極小からの経過時間 +; line 37 : static u16 peak_l; // 谷の深さ +; line 38 : static u16 peak_h; // 山の高さ +; line 39 : static u16 norm_hist[TAP]; +; line 40 : +; line 41 : static u8 hist_indx; +; line 42 : static u8 t_rise; +; line 43 : +; line 44 : signed long filterd; +; line 45 : +; line 46 : u8 i; +; line 47 : +; line 48 : signed long temp1,temp2,temp3; +; line 49 : signed long temp4,temp5,temp6; +; line 50 : +; line 51 : u16 sx16 = abs( (u16)vreg_ctr[VREG_C_ACC_XH] * 256 + vreg_ct +; r[VREG_C_ACC_XL] ); +$DGL 0,22 + mov a,!_vreg_ctr+70 ;[INF] 3, 1 + clrb x ;[INF] 1, 1 + mov c,!_vreg_ctr+69 ;[INF] 3, 1 + call !bs_F0097 ;[INF] 3, 3 + movw [hl+4],ax ; sx16 ;[INF] 2, 1 +; line 52 : u16 sy16 = abs( (u16)vreg_ctr[VREG_C_ACC_YH] * 256 + vreg_ct +; r[VREG_C_ACC_YL] ); +$DGL 0,23 + mov a,!_vreg_ctr+72 ;[INF] 3, 1 + clrb x ;[INF] 1, 1 + mov c,!_vreg_ctr+71 ;[INF] 3, 1 + call !bs_F0097 ;[INF] 3, 3 + movw [hl+2],ax ; sy16 ;[INF] 2, 1 +; line 53 : u16 sz16 = abs( (u16)vreg_ctr[VREG_C_ACC_ZH] * 256 + vreg_ct +; r[VREG_C_ACC_ZL] ); +$DGL 0,24 + mov a,!_vreg_ctr+74 ;[INF] 3, 1 + clrb x ;[INF] 1, 1 + mov c,!_vreg_ctr+73 ;[INF] 3, 1 + call !bs_F0097 ;[INF] 3, 3 + movw [hl],ax ; sz16 ;[INF] 1, 1 +; line 54 : +; line 55 : // ベクトルのノルム +; line 56 : #ifdef _mcu_ +; line 57 : norm_hist[ hist_indx & TAP-1 ] = sqrt( (long)sx16 * ( sx16 / +; 2 ) + +; line 58 : (long)sy16 * ( sy16 / +; 2 ) + +; line 59 : (long)sz16 * ( sz16 / +; 2 ) +; line 60 : ); +$DGL 0,31 + movw ax,[hl+4] ; sx16 ;[INF] 2, 1 + call !bs_S0099 ;[INF] 3, 3 + movw ax,[hl+4] ; sx16 ;[INF] 2, 1 + shrw ax,1 ;[INF] 2, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + clrw ax ;[INF] 1, 1 + movw _@RTARG6,ax ;[INF] 2, 1 + call !@@lsmul ;[INF] 3, 3 + call !bs_S0098 ;[INF] 3, 3 + movw ax,[hl+2] ; sy16 ;[INF] 2, 1 + call !bs_S0099 ;[INF] 3, 3 + movw ax,[hl+2] ; sy16 ;[INF] 2, 1 + shrw ax,1 ;[INF] 2, 1 + movw bc,_@RTARG4 ;[INF] 2, 1 + push bc ;[INF] 1, 1 + call !bs_S0096 ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,_@RTARG6 ;[INF] 2, 1 + call !@@lsadd ;[INF] 3, 3 + call !bs_S0098 ;[INF] 3, 3 + movw ax,[hl] ; sz16 ;[INF] 1, 1 + call !bs_S0099 ;[INF] 3, 3 + movw ax,[hl] ; sz16 ;[INF] 1, 1 + shrw ax,1 ;[INF] 2, 1 + movw bc,_@RTARG4 ;[INF] 2, 1 + push bc ;[INF] 1, 1 + call !bs_S0096 ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,_@RTARG6 ;[INF] 2, 1 + call !@@lsadd ;[INF] 3, 3 + call !@@lstof ;[INF] 3, 3 + movw bc,_@RTARG2 ;[INF] 2, 1 + movw ax,_@RTARG0 ;[INF] 2, 1 + call !!_sqrt ;[INF] 4, 3 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + mov a,!?L0012 ; hist_indx ;[INF] 3, 1 + and a,#03FH ; 63 ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (?L0011) ; norm_hist ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + movw ax,bc ;[INF] 1, 1 + movw _@RTARG2,ax ;[INF] 2, 1 + bt _@RTARG3.7,$?L0014 ;[INF] 4, 5 + call !@@ftolu ;[INF] 3, 3 + br $?L0015 ;[INF] 2, 3 +?L0014: + call !@@ftols ;[INF] 3, 3 +?L0015: + movw ax,_@RTARG0 ;[INF] 2, 1 + movw [de],ax ;[INF] 1, 1 +; line 61 : #endif +; line 62 : +; line 63 : #ifdef _pc_ +; line 64 : norm_hist[ hist_indx & TAP-1 ] = normh * 256 + norml; +; line 65 : #endif +; line 66 : +; line 67 : hist_indx += 1; +$DGL 0,38 + inc !?L0012 ; hist_indx ;[INF] 3, 2 +; line 68 : +; line 69 : // ヒストリにフィルタを掛けて、今回の値を求める +; line 70 : filterd = 0; +$DGL 0,41 + clrw ax ;[INF] 1, 1 + movw [hl+32],ax ; filterd ;[INF] 2, 1 + movw [hl+34],ax ; filterd ;[INF] 2, 1 +; line 71 : // for( i = 8; i != 55; i++ ) // 係数が０ばかりのため +; line 72 : for( i = 0; i != 46; i++ ) // 係数テーブルをいじりました。パ +; ラメータ調整時注意 +$DGL 0,43 + mov [hl+31],a ; i ;[INF] 2, 1 +?L0016: + mov a,[hl+31] ; i ;[INF] 2, 1 + cmp a,#02EH ; 46 ;[INF] 2, 1 + bz $?L0017 ;[INF] 2, 4 +; line 73 : { +??bb00_pedometer: +; line 74 : filterd += (signed long)norm_hist[ ( hist_indx + i ) & T +; AP-1 ] * lpf_coeff[ i ]; +$DGL 0,45 + mov a,!?L0012 ; hist_indx ;[INF] 3, 1 + add a,[hl+31] ; i ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + rolc a,1 ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + and a,#03FH ; 63 ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + movw ax,?L0011[bc] ; norm_hist ;[INF] 3, 1 + call !bs_S0099 ;[INF] 3, 3 + mov a,[hl+31] ; i ;[INF] 2, 1 + mov b,a ;[INF] 1, 1 + mov a,_lpf_coeff[b] ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + movw _@RTARG6,ax ;[INF] 2, 1 + call !@@lsmul ;[INF] 3, 3 + movw ax,[hl+32] ; filterd ;[INF] 2, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,[hl+34] ; filterd ;[INF] 2, 1 + call !@@lsadd ;[INF] 3, 3 + movw ax,_@RTARG2 ;[INF] 2, 1 + movw [hl+34],ax ; filterd ;[INF] 2, 1 + movw ax,_@RTARG0 ;[INF] 2, 1 + movw [hl+32],ax ; filterd ;[INF] 2, 1 +??eb00_pedometer: +; line 75 : } +$DGL 0,46 + inc [hl+31] ; i ;[INF] 3, 2 + br $?L0016 ;[INF] 2, 3 +?L0017: +; line 76 : +; line 77 : filterd += (4096)*512; +; line 78 : acc_norm_temp = (s16)( filterd /1024 & 0xFFFF ); // ←FIL_CO +; EFF_QUANTから正規化 +$DGL 0,49 + movw ax,[hl+32] ; filterd ;[INF] 2, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + movw ax,[hl+34] ; filterd ;[INF] 2, 1 + movw _@RTARG2,ax ;[INF] 2, 1 + movw _@RTARG4,#0400H ; 1024 ;[INF] 4, 1 + clrw ax ;[INF] 1, 1 + call !@@lsdiv ;[INF] 3, 3 + movw _@RTARG4,#0FFFFH ; -1 ;[INF] 4, 1 + clrw ax ;[INF] 1, 1 + call !@@lsband ;[INF] 3, 3 + movw ax,_@RTARG0 ;[INF] 2, 1 + movw !?L0006,ax ; acc_norm_temp ;[INF] 3, 1 +; line 79 : /* +; line 80 : if( acc_norm[0] < acc_norm_temp ) +; line 81 : { +; line 82 : t_rise += 1; +; line 83 : if( t_rise == 0 ) +; line 84 : t_rise == 254; +; line 85 : } +; line 86 : else +; line 87 : { +; line 88 : t_rise = 0; +; line 89 : } +; line 90 : */ +; line 91 : if( acc_norm[0] != acc_norm_temp ) +$DGL 0,62 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0006 ; acc_norm_temp ;[INF] 3, 1 + bz $?L0019 ;[INF] 2, 4 +; line 92 : { +??bb01_pedometer: +; line 93 : acc_norm[2] = acc_norm[1]; // ヒストリ +$DGL 0,64 + movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + movw !?L0005+4,ax ; acc_norm ;[INF] 3, 1 +; line 94 : acc_norm[1] = acc_norm[0]; +$DGL 0,65 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + movw !?L0005+2,ax ; acc_norm ;[INF] 3, 1 +; line 95 : acc_norm[0] = acc_norm_temp; +$DGL 0,66 + movw ax,!?L0006 ; acc_norm_temp ;[INF] 3, 1 + movw !?L0005,ax ; acc_norm ;[INF] 3, 1 +??eb01_pedometer: +; line 96 : } +?L0019: +; line 97 : +; line 98 : if( acc_norm[2] <= acc_norm[1] && acc_norm[1] > acc_norm[0] +; line 99 : && acc_norm[0] > th_H ) +$DGL 0,70 + movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0005+4 ; acc_norm ;[INF] 3, 1 + bc $?L0021 ;[INF] 2, 4 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + bnc $?L0021 ;[INF] 2, 4 + movw ax,!?L0003 ; th_H ;[INF] 3, 1 + cmpw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + bnc $?L0021 ;[INF] 2, 4 +; line 100 : // 極大で、閾値を超えていた +; line 101 : { +??bb02_pedometer: +; line 102 : if( 21 < interval_hh ) +$DGL 0,73 + cmp !?L0007,#016H ; interval_hh,22 ;[INF] 4, 1 + bc $?L0023 ;[INF] 2, 4 +; line 103 : // 前回の極大からの間隔がほどよい +; line 104 : { +??bb03_pedometer: +; line 105 : if(( interval_hh < 160 ) && ( time_l < interval_hh ) +; ) +$DGL 0,76 + cmp !?L0007,#0A0H ; interval_hh,160 ;[INF] 4, 1 + bnc $?L0027 ;[INF] 2, 4 + mov a,!?L0008 ; time_l ;[INF] 3, 1 + cmp a,!?L0007 ; interval_hh ;[INF] 3, 1 + bnc $?L0027 ;[INF] 2, 4 +; line 106 : // 谷を挟んでいる +; line 107 : { +??bb04_pedometer: +; line 108 : if( acc_norm[0] - peak_l > 4200 ){ +$DGL 0,79 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + subw ax,!?L0009 ; peak_l ;[INF] 3, 1 + cmpw ax,#01069H ; 4201 ;[INF] 3, 1 + skc ;[INF] 2, 1 +??bb05_pedometer: +; line 109 : // 一歩増えました +; line 110 : hosu_increment(); +$DGL 0,81 + call !_hosu_increment ;[INF] 3, 3 +??eb05_pedometer: +; line 111 : } +?L0027: +; line 112 : } +??eb04_pedometer: +; line 113 : interval_hh = 0; +$DGL 0,84 + clrb !?L0007 ; interval_hh ;[INF] 3, 1 +??eb03_pedometer: +; line 114 : } +?L0023: +; line 115 : if( acc_norm[0] > 18000 ) +$DGL 0,86 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + cmpw ax,#04651H ; 18001 ;[INF] 3, 1 + bc $?L0029 ;[INF] 2, 4 +; line 116 : { +??bb06_pedometer: +; line 117 : th_L = acc_norm[0] - 10000; +$DGL 0,88 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + subw ax,#02710H ; 10000 ;[INF] 3, 1 + movw !?L0004,ax ; th_L ;[INF] 3, 1 +??eb06_pedometer: +; line 118 : } +$DGL 0,89 + br $?L0022 ;[INF] 2, 3 +?L0029: +; line 119 : else +; line 120 : { +??bb07_pedometer: +; line 121 : th_L = 11000; +$DGL 0,92 + movw ax,#02AF8H ; 11000 ;[INF] 3, 1 + movw !?L0004,ax ; th_L ;[INF] 3, 1 +??eb07_pedometer: +; line 122 : } +; line 123 : } +$DGL 0,94 +??eb02_pedometer: + br $?L0022 ;[INF] 2, 3 +?L0021: +; line 124 : else +; line 125 : { +??bb08_pedometer: +; line 126 : interval_hh += ( interval_hh != 255 ) ? 1: 0; // 飽和加算 +; って楽に書けたらいいのに +$DGL 0,97 + cmp !?L0007,#0FFH ; interval_hh,255 ;[INF] 4, 1 + bz $?L0031 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0032 ;[INF] 2, 3 +?L0031: + clrw ax ;[INF] 1, 1 +?L0032: + movw de,#loww (?L0007) ; interval_hh ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + add a,x ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +??eb08_pedometer: +; line 127 : } +?L0022: +; line 128 : +; line 129 : // (2) 直近の極小からの時間 +; line 130 : if( acc_norm[2] >= acc_norm[1] && acc_norm[1] < acc_norm[0] +; line 131 : && acc_norm[0] < th_L ) +$DGL 0,102 + movw ax,!?L0005+4 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + bc $?L0033 ;[INF] 2, 4 + movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + bnc $?L0033 ;[INF] 2, 4 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + cmpw ax,!?L0004 ; th_L ;[INF] 3, 1 + bnc $?L0033 ;[INF] 2, 4 +; line 132 : { +??bb09_pedometer: +; line 133 : // 極小を検出 +; line 134 : time_l = 0; +$DGL 0,105 + clrb !?L0008 ; time_l ;[INF] 3, 1 +; line 135 : peak_l = acc_norm[0]; +$DGL 0,106 + movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + movw !?L0009,ax ; peak_l ;[INF] 3, 1 +??eb09_pedometer: +; line 136 : } +$DGL 0,107 + br $?L0034 ;[INF] 2, 3 +?L0033: +; line 137 : else +; line 138 : { +??bb0A_pedometer: +; line 139 : time_l += ( time_l != 255 ) ? 1: 0; +$DGL 0,110 + cmp !?L0008,#0FFH ; time_l,255 ;[INF] 4, 1 + bz $?L0035 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0036 ;[INF] 2, 3 +?L0035: + clrw ax ;[INF] 1, 1 +?L0036: + movw de,#loww (?L0008) ; time_l ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + add a,x ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +??eb0A_pedometer: +; line 140 : } +?L0034: +; line 141 : +; line 142 : { +??bb0B_pedometer: +??eb0B_pedometer: +; line 143 : /* +; line 144 : static u8 i = 0; +; line 145 : +; line 146 : vreg_ctr[VREG_C_FREE_0] = i++; +; line 147 : +; line 148 : vreg_ctr[VREG_C_FREE_1] = (u8)( acc_norm[0] / 256 & 0x00 +; FF ); +; line 149 : vreg_ctr[VREG_C_FREE_2] = (u8)( acc_norm[0] & 0x00FF ); +; line 150 : +; line 151 : vreg_ctr[VREG_C_FREE_3] = (u8)( norm_hist[ hist_indx -1 +; & TAP-1 ] / 256 & 0xFF ); +; line 152 : vreg_ctr[VREG_C_FREE_4] = (u8)( norm_hist[ hist_indx -1 +; & TAP-1 ] & 0xFF ); +; line 153 : +; line 154 : vreg_ctr[VREG_C_FREE_5] = interval_hh; +; line 155 : vreg_ctr[VREG_C_FREE_6] = time_l; +; line 156 : +; line 157 : vreg_ctr[VREG_C_FREE_7] = vreg_ctr[ VREG_C_ACC_HOSU_L ]; +; line 158 : vreg_ctr[VREG_C_FREE_8] = (u8)( peak_l / 256 & 0x00FF ); +; line 159 : vreg_ctr[VREG_C_FREE_9] = (u8)( peak_l & 0x00FF ); +; line 160 : // vreg_ctr[VREG_C_FREE_A] = (u8)( norm_avg[0] / 256 & 0x +; 00FF ); +; line 161 : // vreg_ctr[VREG_C_FREE_B] = (u8)( norm_avg[0] & +; 0x00FF ); +; line 162 : */ +; line 163 : } +; line 164 : } +$DGL 0,135 +??ef_pedometer: + addw sp,#024H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_pedometer: +; line 165 : +; line 166 : +; line 167 : +; line 168 : /*========================================================= +; line 169 : 　歩数＋１ +; line 170 : 　　累積をインクリメント +; line 171 : 　履歴を更新 +; line 172 : ========================================================*/ +; line 173 : u8 p_record; +; line 174 : u8 last_hour = 0x23; // 履歴の最新は何時？ +; line 175 : u8 last_day = 0x30; +; line 176 : u8 last_month = 0x12; +; line 177 : u8 last_year = 0x99; +; line 178 : +; line 179 : #define HOSU_NODATA 0xFFFF +; line 180 : #define HOSU_MAX 0xFFFE +; line 181 : +; line 182 : static void hosu_increment() +; line 183 : { +_hosu_increment: +$DGL 1,107 + push hl ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_hosu_increment: +; line 184 : static u16 last_hour_fny; +; line 185 : +; line 186 : // 累積の更新 // +; line 187 : // いろいろ失敗した... +; line 188 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_L ] == 0 ) +$DGL 0,6 + inc !_vreg_ctr+75 ;[INF] 3, 2 + cmp0 !_vreg_ctr+75 ;[INF] 3, 1 + bnz $?L0044 ;[INF] 2, 4 +; line 189 : { +??bb00_hosu_increment: +; line 190 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_M ] == 0 ) +$DGL 0,8 + inc !_vreg_ctr+76 ;[INF] 3, 2 + cmp0 !_vreg_ctr+76 ;[INF] 3, 1 + bnz $?L0044 ;[INF] 2, 4 +; line 191 : { +??bb01_hosu_increment: +; line 192 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_H ] == 0 ){ +$DGL 0,10 + inc !_vreg_ctr+77 ;[INF] 3, 2 + cmp0 !_vreg_ctr+77 ;[INF] 3, 1 + bnz $?L0044 ;[INF] 2, 4 +??bb02_hosu_increment: +; line 193 : vreg_ctr[ VREG_C_ACC_HOSU_L ] = 255; // カンスト +; orz +$DGL 0,11 + mov !_vreg_ctr+75,#0FFH ; 255 ;[INF] 4, 1 +; line 194 : vreg_ctr[ VREG_C_ACC_HOSU_M ] = 255; +$DGL 0,12 + mov !_vreg_ctr+76,#0FFH ; 255 ;[INF] 4, 1 +; line 195 : vreg_ctr[ VREG_C_ACC_HOSU_H ] = 255; +$DGL 0,13 + mov !_vreg_ctr+77,#0FFH ; 255 ;[INF] 4, 1 +??eb02_hosu_increment: +; line 196 : } +?L0044: +??eb01_hosu_increment: +; line 197 : } +??eb00_hosu_increment: +; line 198 : } +; line 199 : +; line 200 : { +??bb03_hosu_increment: +; line 201 : // 毎時履歴の更新 ///////////////////////////// +; line 202 : // 空白の時間を考慮する。１時間以上放置されたなど。 +; line 203 : u16 now_hour; +; line 204 : u8 now_year; +; line 205 : +; line 206 : // 時計を止める必要が有るので↓は一気に行って下さい +; line 207 : DI(); +$DGL 0,25 + di ;[INF] 3, 4 +; line 208 : RWAIT = 1; +$DGL 0,26 + set1 RTCC1.0 ;[INF] 3, 2 +; line 209 : while( !RWST ){;} +$DGL 0,27 +?L0046: + bt RTCC1.1,$?L0047 ;[INF] 4, 5 +??bb04_hosu_increment: +??eb04_hosu_increment: + br $?L0046 ;[INF] 2, 3 +?L0047: +; line 210 : now_year = bcdtob( YEAR ); +$DGL 0,28 + mov a,YEAR ;[INF] 2, 1 + call !@@bcdtob ;[INF] 3, 3 + mov [hl+3],a ; now_year ;[INF] 2, 1 +; line 211 : last_hour = HOUR; // 履歴読み出し時に使用。BCDのまま +; でよい +$DGL 0,29 + mov a,HOUR ;[INF] 2, 1 + mov !_last_hour,a ;[INF] 3, 1 +; line 212 : last_day = DAY; +$DGL 0,30 + mov a,DAY ;[INF] 2, 1 + mov !_last_day,a ;[INF] 3, 1 +; line 213 : last_month = MONTH; +$DGL 0,31 + mov a,MONTH ;[INF] 2, 1 + mov !_last_month,a ;[INF] 3, 1 +; line 214 : now_hour = get_long_hour(); +$DGL 0,32 + call !_get_long_hour ;[INF] 3, 3 + movw ax,bc ;[INF] 1, 1 + movw [hl+4],ax ; now_hour ;[INF] 2, 1 +; line 215 : // RWAIT = 0; ↑で行っています +; line 216 : // EI(); 〃 +; line 217 : +; line 218 : // 歩数計が止まっていた時間を考慮して必要なら進める // +; line 219 : if( last_year == now_year ) +$DGL 0,37 + mov a,!_last_year ;[INF] 3, 1 + cmp a,[hl+3] ; now_year ;[INF] 2, 1 + bnz $?L0048 ;[INF] 2, 4 +; line 220 : { +??bb05_hosu_increment: +; line 221 : if( now_hour > last_hour_fny ) +$DGL 0,39 + movw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + cmpw ax,[hl+4] ; now_hour ;[INF] 3, 1 + bnc $?L0056 ;[INF] 2, 4 +; line 222 : { +??bb06_hosu_increment: +; line 223 : fill_hosu_hist_hours( now_hour - last_hour_fny ) +; ; +$DGL 0,41 + movw ax,[hl+4] ; now_hour ;[INF] 2, 1 + subw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + call !_fill_hosu_hist_hours ;[INF] 3, 3 +??eb06_hosu_increment: +; line 224 : } +; line 225 : } +$DGL 0,43 +??eb05_hosu_increment: + br $?L0056 ;[INF] 2, 3 +?L0048: +; line 226 : else if( last_year == ( now_year -1 ) ) +$DGL 0,44 + mov a,[hl+3] ; now_year ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + decw ax ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + mov x,!_last_year ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + cmpw ax,bc ;[INF] 1, 1 + bnz $?L0052 ;[INF] 2, 4 +; line 227 : { +??bb07_hosu_increment: +; line 228 : // 年をまたいでいるとき +; line 229 : u16 temp_hours = ( ( 365 + (( now_year & 0x03 ) == +; 1 ? 1: 0 )) * 24 ) - last_hour_fny + now_hour; +$DGL 0,47 + mov a,[hl+3] ; now_year ;[INF] 2, 1 + and a,#03H ; 3 ;[INF] 2, 1 + dec a ;[INF] 1, 1 + bnz $?L0054 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0055 ;[INF] 2, 3 +?L0054: + clrw ax ;[INF] 1, 1 +?L0055: + addw ax,#016DH ; 365 ;[INF] 3, 1 + shlw ax,3 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + addw ax,ax ;[INF] 1, 1 + addw ax,bc ;[INF] 1, 1 + subw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + addw ax,[hl+4] ; now_hour ;[INF] 3, 1 + movw [hl],ax ; temp_hours ;[INF] 1, 1 +; line 230 : fill_hosu_hist_hours( temp_hours ); +$DGL 0,48 + call !_fill_hosu_hist_hours ;[INF] 3, 3 +??eb07_hosu_increment: +; line 231 : } +$DGL 0,49 + br $?L0056 ;[INF] 2, 3 +?L0052: +; line 232 : else if( last_year < now_year ) +$DGL 0,50 + mov a,!_last_year ;[INF] 3, 1 + cmp a,[hl+3] ; now_year ;[INF] 2, 1 + bnc $?L0056 ;[INF] 2, 4 +; line 233 : { +??bb08_hosu_increment: +; line 234 : // 数年放置 +; line 235 : fill_hosu_hist_hours( 0 ); +$DGL 0,53 + clrw ax ;[INF] 1, 1 + call !_fill_hosu_hist_hours ;[INF] 3, 3 +??eb08_hosu_increment: +; line 236 : } +?L0056: +; line 237 : else +; line 238 : { +??bb09_hosu_increment: +??eb09_hosu_increment: +; line 239 : // カレンダーが巻き戻るなど +; line 240 : // ノーケアでよい +; line 241 : } +; line 242 : last_year = now_year; +$DGL 0,60 + mov a,[hl+3] ; now_year ;[INF] 2, 1 + mov !_last_year,a ;[INF] 3, 1 +; line 243 : last_hour_fny = now_hour; +$DGL 0,61 + movw ax,[hl+4] ; now_hour ;[INF] 2, 1 + movw !?L0039,ax ; last_hour_fny ;[INF] 3, 1 +; line 244 : +; line 245 : // 実際にインクリメント +; line 246 : if( pool[ p_record ] == HOSU_NODATA ) +$DGL 0,64 + mov x,!_p_record ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,ax ;[INF] 1, 1 + addw ax,#loww (_pool) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + cmpw ax,#0FFFFH ; -1 ;[INF] 3, 1 + bnz $?L0058 ;[INF] 2, 4 +; line 247 : { +??bb0A_hosu_increment: +; line 248 : pool[ p_record ] = 1; +$DGL 0,66 + onew ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 +??eb0A_hosu_increment: +; line 249 : } +$DGL 0,67 + br $?L0060 ;[INF] 2, 3 +?L0058: +; line 250 : else if( pool[ p_record ] != HOSU_MAX ) +$DGL 0,68 + mov x,!_p_record ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,ax ;[INF] 1, 1 + addw ax,#loww (_pool) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + cmpw ax,#0FFFEH ; -2 ;[INF] 3, 1 + bz $?L0060 ;[INF] 2, 4 +; line 251 : { +??bb0B_hosu_increment: +; line 252 : pool[ p_record ] += 1; +$DGL 0,70 + movw ax,[de] ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 +??eb0B_hosu_increment: +; line 253 : } +?L0060: +??eb03_hosu_increment: +; line 254 : } +; line 255 : } +$DGL 0,73 +??ef_hosu_increment: + addw sp,#06H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_hosu_increment: +; line 256 : +; line 257 : +; line 258 : +; line 259 : /* ======================================================== +; line 260 : 空白の時間を適切に0にして、 +; line 261 : 今を含む１時間のデータを書く位置にポインタ？を進める +; line 262 : ======================================================== */ +; line 263 : void fill_hosu_hist_hours( u16 hours ) +; line 264 : { +_fill_hosu_hist_hours: +$DGL 1,168 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_fill_hosu_hist_hours: +; line 265 : if( hours > 255 ) +$DGL 0,2 + movw ax,hl ;[INF] 1, 1 + cmpw ax,#0100H ; 256 ;[INF] 3, 1 + bc $?L0064 ;[INF] 2, 4 +; line 266 : { +??bb00_fill_hosu_hist_hours: +; line 267 : hours = 0; +$DGL 0,4 + clrw ax ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??eb00_fill_hosu_hist_hours: +; line 268 : } +?L0064: +; line 269 : +; line 270 : // 空白の数時間の設定 +; line 271 : do +; line 272 : { +??bb01_fill_hosu_hist_hours: +; line 273 : p_record += 1; +$DGL 0,10 + inc !_p_record ;[INF] 3, 2 +; line 274 : pool[ p_record ] = 0; +$DGL 0,11 + mov c,!_p_record ;[INF] 3, 1 + clrb b ;[INF] 1, 1 + shlw bc,1 ;[INF] 2, 1 + clrw ax ;[INF] 1, 1 + movw _pool[bc],ax ;[INF] 3, 1 +; line 275 : hours -= 1; +$DGL 0,12 + decw hl ;[INF] 1, 1 +??eb01_fill_hosu_hist_hours: +; line 276 : } +; line 277 : while( hours != 0 ); +$DGL 0,14 + clrw ax ;[INF] 1, 1 + cmpw ax,hl ;[INF] 1, 1 + bnz $?L0064 ;[INF] 2, 4 +; line 278 : } +$DGL 0,15 +??ef_fill_hosu_hist_hours: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_fill_hosu_hist_hours: +; line 279 : +; line 280 : +; line 281 : +; line 282 : /* ======================================================== +; line 283 : 空白の時間を適切に0にして、 +; line 284 : 今を含む１時間のデータを書く位置にポインタ？を進める +; line 285 : ======================================================== */ +; line 286 : void clear_hosu_hist() +; line 287 : { +_clear_hosu_hist: +$DGL 1,183 + push hl ;[INF] 1, 1 +??bf_clear_hosu_hist: +; line 288 : u8 hours = 0; +$DGL 0,2 + mov l,#00H ; 0 ;[INF] 2, 1 +; line 289 : // 空白の数時間の設定 +; line 290 : do +?L0071: +; line 291 : { +??bb00_clear_hosu_hist: +; line 292 : pool[ hours ] = 0xFFFF; +$DGL 0,6 + mov a,l ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + decw ax ;[INF] 1, 1 + movw _pool[bc],ax ;[INF] 3, 1 +; line 293 : hours -= 1; +$DGL 0,7 + dec l ;[INF] 1, 1 +??eb00_clear_hosu_hist: +; line 294 : } +; line 295 : while( hours != 0 ); +$DGL 0,9 + mov a,l ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0071 ;[INF] 2, 4 +; line 296 : vreg_ctr[ VREG_C_ACC_HOSU_L ] = 0; +$DGL 0,10 + clrb !_vreg_ctr+75 ;[INF] 3, 1 +; line 297 : vreg_ctr[ VREG_C_ACC_HOSU_M ] = 0; +$DGL 0,11 + clrb !_vreg_ctr+76 ;[INF] 3, 1 +; line 298 : vreg_ctr[ VREG_C_ACC_HOSU_H ] = 0; +$DGL 0,12 + clrb !_vreg_ctr+77 ;[INF] 3, 1 +; line 299 : } +$DGL 0,13 +??ef_clear_hosu_hist: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_clear_hosu_hist: +; line 300 : +; line 301 : +; line 302 : extern u8 iic_burst_state; +; line 303 : bit record_read_msb_lsb; +; line 304 : +; line 305 : /* ======================================================== +; line 306 : 歩数計ヒストリ読み出しの後処理(初期化) +; line 307 : 読み出しポインタのクリア +; line 308 : ======================================================== */ +; line 309 : void hosu_read_end( ) +; line 310 : { +_hosu_read_end: +$DGL 1,194 +??bf_hosu_read_end: +; line 311 : record_read_msb_lsb = 0; +$DGL 0,2 + clr1 _record_read_msb_lsb ;[INF] 3, 2 +; line 312 : } +$DGL 0,3 +??ef_hosu_read_end: + ret ;[INF] 1, 6 +??ee_hosu_read_end: +; line 313 : +; line 314 : +; line 315 : /* ======================================================== +; line 316 : 歩数計のヒストリを返す。 +; line 317 : １回呼ぶ度に、ヒストリの下位、上位、一時間遡って下位上位... +; line 318 : ======================================================== */ +; line 319 : u8 hosu_read( ) +; line 320 : { +_hosu_read: +$DGL 1,200 + push hl ;[INF] 1, 1 + subw sp,#04H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_hosu_read: +; line 321 : u8 dat; +; line 322 : u16 temp; +; line 323 : static u8 p_record_buffer; +; line 324 : +; line 325 : switch( iic_burst_state ){ +$DGL 0,6 + mov x,!_iic_burst_state ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0080 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0081 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0082 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0083 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0084 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0085 ;[INF] 2, 4 + br $?L0086 ;[INF] 2, 3 +??bb00_hosu_read: +; line 326 : case( 0 ): +?L0080: +; line 327 : p_record_buffer = p_record; +$DGL 0,8 + mov a,!_p_record ;[INF] 3, 1 + mov !?L0078,a ; p_record_buffer ;[INF] 3, 1 +; line 328 : iic_burst_state += 1; +$DGL 0,9 + inc !_iic_burst_state ;[INF] 3, 2 +; line 329 : return( last_hour ); +$DGL 0,10 + mov x,!_last_hour ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0079 ;[INF] 2, 3 +; line 330 : +; line 331 : case( 1 ): +?L0081: +; line 332 : iic_burst_state += 1; +$DGL 0,13 + inc !_iic_burst_state ;[INF] 3, 2 +; line 333 : return( last_day ); +$DGL 0,14 + mov x,!_last_day ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0079 ;[INF] 2, 3 +; line 334 : +; line 335 : case( 2 ): +?L0082: +; line 336 : iic_burst_state += 1; +$DGL 0,17 + inc !_iic_burst_state ;[INF] 3, 2 +; line 337 : return( last_month ); +$DGL 0,18 + mov x,!_last_month ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0079 ;[INF] 2, 3 +; line 338 : +; line 339 : case( 3 ): +?L0083: +; line 340 : iic_burst_state += 1; +$DGL 0,21 + inc !_iic_burst_state ;[INF] 3, 2 +; line 341 : return( btobcd(last_year) ); +$DGL 0,22 + mov a,!_last_year ;[INF] 3, 1 + call !@@bbcd ;[INF] 3, 3 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0079 ;[INF] 2, 3 +; line 342 : +; line 343 : case( 4 ): +?L0084: +; line 344 : iic_burst_state += 1; +$DGL 0,25 + inc !_iic_burst_state ;[INF] 3, 2 +; line 345 : return( 0x55 ); // reserved dummy +$DGL 0,26 + movw bc,#055H ; 85 ;[INF] 3, 1 + br $?L0079 ;[INF] 2, 3 +; line 346 : +; line 347 : case( 5 ): +?L0085: +; line 348 : iic_burst_state += 1; +$DGL 0,29 + inc !_iic_burst_state ;[INF] 3, 2 +; line 349 : return( 0xAA ); // reserved. dummy +$DGL 0,30 + movw bc,#0AAH ; 170 ;[INF] 3, 1 + br $?L0079 ;[INF] 2, 3 +; line 350 : +; line 351 : default: +?L0086: +; line 352 : temp = pool[ p_record_buffer ]; +$DGL 0,33 + mov c,!?L0078 ; p_record_buffer ;[INF] 3, 1 + clrb b ;[INF] 1, 1 + shlw bc,1 ;[INF] 2, 1 + movw ax,_pool[bc] ;[INF] 3, 1 + movw [hl],ax ; temp ;[INF] 1, 1 +; line 353 : if( record_read_msb_lsb == 0 ) +$DGL 0,34 + bt _record_read_msb_lsb,$?L0089 ;[INF] 4, 5 +; line 354 : { +??bb01_hosu_read: +; line 355 : dat = (u8)( temp & 0x00FF ); +$DGL 0,36 + mov a,[hl] ; temp ;[INF] 1, 1 + mov [hl+3],a ; dat ;[INF] 2, 1 +??eb01_hosu_read: +; line 356 : } +$DGL 0,37 + br $?L0090 ;[INF] 2, 3 +?L0089: +; line 357 : else +; line 358 : { +??bb02_hosu_read: +; line 359 : dat = (u8)(( temp >> 8 ) & 0x00FF ); +$DGL 0,40 + mov a,[hl+1] ; temp ;[INF] 2, 1 + mov [hl+3],a ; dat ;[INF] 2, 1 +; line 360 : p_record_buffer -= 1; +$DGL 0,41 + dec !?L0078 ; p_record_buffer ;[INF] 3, 2 +??eb02_hosu_read: +; line 361 : } +?L0090: +; line 362 : record_read_msb_lsb += 1; +$DGL 0,43 + set1 CY ;[INF] 2, 1 + xor1 CY,_record_read_msb_lsb ;[INF] 3, 1 + rolc a,1 ;[INF] 2, 1 + rorc a,1 ;[INF] 2, 1 + mov1 _record_read_msb_lsb,CY ;[INF] 3, 2 +; line 363 : return( dat ); +$DGL 0,44 + mov a,[hl+3] ; dat ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 +??eb00_hosu_read: +; line 364 : } +?L0079: +; line 365 : } +$DGL 0,46 +??ef_hosu_read: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_hosu_read: +; line 366 : +; line 367 : +; line 368 : +; line 369 : /* ======================================================== +; line 370 : 今年の元旦からの経過時間(hour)を返す。 +; line 371 : 引数 無し +; line 372 : 返値 u16 long_hour +; line 373 : ======================================================== */ +; line 374 : static const u16 DAYS_FROM_HNY[] = { +; line 375 : 0, +; line 376 : 0, 31, 31+28, 59+31, 90+30, +; line 377 : 120+31, 151+30, 181+31, 212+31, 243+30, +; line 378 : 273+31, 304+30 }; +; line 379 : +; line 380 : u16 get_long_hour() +; line 381 : { +_get_long_hour: +$DGL 1,223 + push hl ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_get_long_hour: +; line 382 : u16 long_hour; +; line 383 : u8 year_hex; +; line 384 : u8 month_hex; +; line 385 : u8 day_hex; +; line 386 : u8 hour_hex; +; line 387 : +; line 388 : year_hex = bcdtob( YEAR ); +$DGL 0,8 + mov a,YEAR ;[INF] 2, 1 + call !@@bcdtob ;[INF] 3, 3 + mov [hl+3],a ; year_hex ;[INF] 2, 1 +; line 389 : month_hex = bcdtob( MONTH ); +$DGL 0,9 + mov a,MONTH ;[INF] 2, 1 + call !@@bcdtob ;[INF] 3, 3 + mov [hl+2],a ; month_hex ;[INF] 2, 1 +; line 390 : day_hex = bcdtob( DAY ); +$DGL 0,10 + mov a,DAY ;[INF] 2, 1 + call !@@bcdtob ;[INF] 3, 3 + mov [hl+1],a ; day_hex ;[INF] 2, 1 +; line 391 : hour_hex = bcdtob( HOUR ); +$DGL 0,11 + mov a,HOUR ;[INF] 2, 1 + call !@@bcdtob ;[INF] 3, 3 + mov [hl],a ; hour_hex ;[INF] 1, 1 +; line 392 : +; line 393 : RWAIT = 0; +$DGL 0,13 + clr1 RTCC1.0 ;[INF] 3, 2 +; line 394 : EI(); +$DGL 0,14 + ei ;[INF] 3, 4 +; line 395 : +; line 396 : // まず日数の部分 +; line 397 : long_hour = DAYS_FROM_HNY[ month_hex ]; +$DGL 0,17 + mov a,[hl+2] ; month_hex ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + movw ax,_DAYS_FROM_HNY[bc] ;[INF] 3, 1 + movw [hl+4],ax ; long_hour ;[INF] 2, 1 +; line 398 : if(( ( year_hex & 0x03 ) == 0 ) && ( ( 3 <= month_hex ) +$DGL 0,18 + mov a,[hl+3] ; year_hex ;[INF] 2, 1 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0093 ;[INF] 2, 4 + mov a,[hl+2] ; month_hex ;[INF] 2, 1 + cmp a,#03H ; 3 ;[INF] 2, 1 + bnc $?L0095 ;[INF] 2, 4 +; line 399 : || (( 2 == month_hex ) +; && ( day_hex == 29 )) )) +$DGL 0,19 + mov a,[hl+2] ; month_hex ;[INF] 2, 1 + cmp a,#02H ; 2 ;[INF] 2, 1 + bnz $?L0093 ;[INF] 2, 4 + mov a,[hl+1] ; day_hex ;[INF] 2, 1 + cmp a,#01DH ; 29 ;[INF] 2, 1 + sknz ;[INF] 2, 1 +?L0095: +; line 400 : { +??bb00_get_long_hour: +; line 401 : // 閏年で、閏日より後 +; line 402 : long_hour += 1; +$DGL 0,22 + incw [hl+4] ; long_hour ;[INF] 3, 2 +??eb00_get_long_hour: +; line 403 : } +?L0093: +; line 404 : long_hour += day_hex - 1; +$DGL 0,24 + mov a,[hl+1] ; day_hex ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + decw ax ;[INF] 1, 1 + addw ax,[hl+4] ; long_hour ;[INF] 3, 1 + movw [hl+4],ax ; long_hour ;[INF] 2, 1 +; line 405 : long_hour *= 24; // 日数→時間 +$DGL 0,25 + shlw ax,3 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + addw ax,ax ;[INF] 1, 1 + addw ax,bc ;[INF] 1, 1 + movw [hl+4],ax ; long_hour ;[INF] 2, 1 +; line 406 : +; line 407 : long_hour += hour_hex; +$DGL 0,27 + mov a,[hl+4] ; long_hour ;[INF] 2, 1 + add a,[hl] ; hour_hex ;[INF] 1, 1 + mov x,a ;[INF] 1, 1 + mov a,[hl+5] ; long_hour ;[INF] 2, 1 + addc a,#00H ; 0 ;[INF] 2, 1 + movw [hl+4],ax ; long_hour ;[INF] 2, 1 +; line 408 : +; line 409 : return( long_hour ); +$DGL 0,29 + movw bc,ax ;[INF] 1, 1 +; line 410 : } +$DGL 0,30 +??ef_get_long_hour: + addw sp,#06H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_get_long_hour: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c +; +; $FUNC pedometer(30) +; void=(void) +; CODE SIZE= 447 bytes, CLOCK_SIZE= 435 clocks, STACK_SIZE= 50 bytes +; +; $CALL abs(51) +; bc=(int:ax) +; +; $CALL abs(52) +; bc=(int:ax) +; +; $CALL abs(53) +; bc=(int:ax) +; +; $CALL sqrt(60) +; bc,de=(double:ax,bc) +; +; $CALL hosu_increment(110) +; void=(void) +; +; $FUNC hosu_increment(183) +; void=(void) +; CODE SIZE= 213 bytes, CLOCK_SIZE= 166 clocks, STACK_SIZE= 12 bytes +; +; $CALL get_long_hour(214) +; bc=(void) +; +; $CALL fill_hosu_hist_hours(223) +; void=(unsigned short:ax) +; +; $CALL fill_hosu_hist_hours(230) +; void=(unsigned short:ax) +; +; $CALL fill_hosu_hist_hours(235) +; void=(unsigned short:ax) +; +; $FUNC fill_hosu_hist_hours(264) +; void=(unsigned short hours:ax) +; CODE SIZE= 30 bytes, CLOCK_SIZE= 31 clocks, STACK_SIZE= 2 bytes +; +; $FUNC clear_hosu_hist(287) +; void=(void) +; CODE SIZE= 29 bytes, CLOCK_SIZE= 26 clocks, STACK_SIZE= 2 bytes +; +; $FUNC hosu_read_end(310) +; void=(void) +; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes +; +; $FUNC hosu_read(320) +; bc=(void) +; CODE SIZE= 146 bytes, CLOCK_SIZE= 124 clocks, STACK_SIZE= 10 bytes +; +; $FUNC get_long_hour(381) +; bc=(void) +; CODE SIZE= 110 bytes, CLOCK_SIZE= 84 clocks, STACK_SIZE= 12 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/pm.asm b/branches/0.10(X3)/inter_asm/pm.asm new file mode 100644 index 0000000..333813e --- /dev/null +++ b/branches/0.10(X3)/inter_asm/pm.asm @@ -0,0 +1,3970 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no pm.c +; In-file : pm.c +; Asm-file : inter_asm\pm.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0217H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, pm.c +$DGS MOD_NAM, pm, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 06DH +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 041H, 01H +$DGS LAB_SYM, bs_F0153, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0153, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0154, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0154, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0155, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0155, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0151, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0151, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0152, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0152, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0149, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0149, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0150, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0150, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0146, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0146, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0147, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0147, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0148, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0148, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0144, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0144, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0145, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0145, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS STA_SYM, _BT_PARAM, U, U, 0500CH, 03H, 01H, 0FH +$DGS AUX_STR, 00H, 00H, 01C0H, 07H, 040H, 00H, 00H, 00H +$DGS STA_SYM, _BT_PANA_RCOMP, U, U, 0500CH, 03H, 00H, 00H +$DGS STA_SYM, _BT_PANA_TEMPCOUP, U, U, 05006H, 03H, 00H, 00H +$DGS STA_SYM, _BT_PANA_TEMPCODN, U, U, 05006H, 03H, 00H, 00H +$DGS GLV_SYM, _PM_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 09AH, 00H, 00H +$DGS BEG_FUN, ??bf_PM_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02EH, 08H, 07CH +$DGS AUT_VAR, _temp, 07H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _origParam, 03H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H +$DGS STR_STR, .7fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 02H, 073H +$DGS MEB_STR, _lsb, 00H, 0FFFFH, 0CH, 08H, 00H, 00H +$DGS MEB_STR, _msb, 01H, 0FFFFH, 0CH, 08H, 00H, 00H +$DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 06DH, 02H +$DGS UNI_TAG, .6fake, 00H, 0FFFEH, 09H, 0CH, 01H, 00H +$DGS AUX_TAG, 02H, 07AH +$DGS MEB_UNI, __u16, 00H, 0FFFFH, 0DH, 0BH, 00H, 00H +$DGS MEB_UNI, _chars, 00H, 0FFFFH, 08H, 0BH, 01H, 00H +$DGS AUX_STR, 06DH, 00H, 02H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 073H, 02H +$DGS AUT_VAR, _dat_16, 00H, 0FFFFH, 09H, 01H, 01H, 00H +$DGS AUX_STR, 073H, 00H, 02H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb00_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 080H +$DGS END_BLK, ??eb00_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb01_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 082H +$DGS BEG_BLK, ??bb02_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 084H +$DGS BEG_BLK, ??bb03_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 08AH +$DGS END_BLK, ??eb03_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS END_BLK, ??eb02_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS BEG_BLK, ??bb04_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 08EH +$DGS END_BLK, ??eb04_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 040H +$DGS BEG_BLK, ??bb05_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04FH, 00H, 092H +$DGS END_BLK, ??eb05_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 051H +$DGS BEG_BLK, ??bb06_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 051H, 00H, 00H +$DGS END_BLK, ??eb06_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 053H +$DGS END_BLK, ??eb01_PM_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05DH +$DGS END_FUN, ??ef_PM_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 068H +$DGS GLV_SYM, _PM_bt_temp_update, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0B8H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0A3H, 02H, 0A2H +$DGS STA_SYM, _count, ?L0018, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _rawdat_old, ?L0019, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _temperature, ?L0020, U, 03H, 03H, 00H, 00H +$DGS AUT_VAR, _newrcomp, 00H, 0FFFFH, 0DH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 0A6H +$DGS END_BLK, ??eb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 0A8H +$DGS BEG_BLK, ??bb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01AH, 00H, 0ACH +$DGS END_BLK, ??eb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS BEG_BLK, ??bb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01EH, 00H, 0B0H +$DGS END_BLK, ??eb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 020H +$DGS BEG_BLK, ??bb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 00H +$DGS END_BLK, ??eb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS END_BLK, ??eb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02BH +$DGS END_FUN, ??ef_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02FH +$DGS GLV_SYM, _PM_LCD_on, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0C3H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_LCD_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0E3H, 02H, 0BDH +$DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 00H +$DGS END_BLK, ??eb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS END_FUN, ??ef_PM_LCD_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 023H +$DGS GLV_SYM, _PM_LCD_off, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0DFH, 00H, 00H +$DGS BEG_FUN, ??bf_PM_LCD_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0109H, 02H, 0C7H +$DGS BEG_BLK, ??bb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 0CBH +$DGS REG_VAR, _tot, 06H, 0FFFFH, 010CH, 04H, 01H, 00H +$DGS AUX_STR, 00H, 0BH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 0CDH +$DGS BEG_BLK, ??bb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 0D1H +$DGS END_BLK, ??eb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 0D5H +$DGS END_BLK, ??eb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS BEG_BLK, ??bb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 00H +$DGS END_BLK, ??eb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS END_BLK, ??eb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 017H +$DGS END_BLK, ??eb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS END_FUN, ??ef_PM_LCD_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 028H +$DGS GLV_SYM, _PM_BL_set, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0112H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_BL_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 013AH, 06H, 0E6H +$DGS FUN_ARG, _dat, 04H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS AUT_VAR, _blset, 03H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _intset, 02H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 0EAH +$DGS END_BLK, ??eb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 0EEH +$DGS END_BLK, ??eb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS BEG_BLK, ??bb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 0F2H +$DGS END_BLK, ??eb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS BEG_BLK, ??bb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 021H, 00H, 0F6H +$DGS END_BLK, ??eb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 024H +$DGS BEG_BLK, ??bb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 0FAH +$DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 034H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 037H, 00H, 0FCH +$DGS BEG_BLK, ??bb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 039H, 00H, 0100H +$DGS END_BLK, ??eb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 039H +$DGS BEG_BLK, ??bb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03BH, 00H, 0104H +$DGS END_BLK, ??eb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03BH +$DGS BEG_BLK, ??bb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03CH, 00H, 010CH +$DGS END_BLK, ??eb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03CH +$DGS END_BLK, ??eb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03DH +$DGS END_BLK, ??eb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03EH +$DGS BEG_BLK, ??bb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 00H +$DGS END_BLK, ??eb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 045H +$DGS END_FUN, ??ef_PM_BL_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 049H +$DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0119H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 018BH, 02H, 0119H +$DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS END_FUN, ??ef_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 07H +$DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 011FH, 00H, 00H +$DGS BEG_FUN, ??bf_tski_vcom_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 01C2H, 00H, 011FH +$DGS END_FUN, ??ef_tski_vcom_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0142H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 01D2H, 02H, 0124H +$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 0128H +$DGS END_BLK, ??eb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 012CH +$DGS END_BLK, ??eb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS BEG_BLK, ??bb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 0130H +$DGS END_BLK, ??eb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS BEG_BLK, ??bb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 019H, 00H, 0134H +$DGS END_BLK, ??eb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 0138H +$DGS END_BLK, ??eb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 032H +$DGS BEG_BLK, ??bb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 013CH +$DGS END_BLK, ??eb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 033H +$DGS BEG_BLK, ??bb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 00H +$DGS END_BLK, ??eb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS END_FUN, ??ef_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 069H +$DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0150H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0247H, 00H, 0146H +$DGS BEG_BLK, ??bb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 014AH +$DGS END_BLK, ??eb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS BEG_BLK, ??bb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 00H +$DGS END_BLK, ??eb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS END_FUN, ??ef_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 020H +$DGS GLV_SYM, _tsk_batt, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 01A1H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_batt, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 027DH, 00H, 0157H +$DGS STA_SYM, _task_interval, ?L0077, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _charge_hys, ?L0078, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _pm_extdc_old, ?L0079, U, 034CH, 028H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 015BH +$DGS END_BLK, ??eb00_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 09H +$DGS BEG_BLK, ??bb01_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 015FH +$DGS END_BLK, ??eb01_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb02_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 0161H +$DGS BEG_BLK, ??bb03_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 0163H +$DGS BEG_BLK, ??bb04_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 0165H +$DGS BEG_BLK, ??bb05_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 0169H +$DGS END_BLK, ??eb05_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS BEG_BLK, ??bb06_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 0171H +$DGS END_BLK, ??eb06_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS END_BLK, ??eb04_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS END_BLK, ??eb03_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS BEG_BLK, ??bb07_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01AH, 00H, 0173H +$DGS BEG_BLK, ??bb08_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 0175H +$DGS BEG_BLK, ??bb09_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 0179H +$DGS END_BLK, ??eb09_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS BEG_BLK, ??bb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 0183H +$DGS END_BLK, ??eb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS END_BLK, ??eb08_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS END_BLK, ??eb07_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS END_BLK, ??eb02_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01EH +$DGS BEG_BLK, ??bb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 024H, 00H, 0187H +$DGS END_BLK, ??eb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS BEG_BLK, ??bb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 018BH +$DGS END_BLK, ??eb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02CH +$DGS BEG_BLK, ??bb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 034H, 00H, 018FH +$DGS END_BLK, ??eb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 037H +$DGS BEG_BLK, ??bb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 039H, 00H, 0193H +$DGS END_BLK, ??eb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03CH +$DGS BEG_BLK, ??bb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 0195H +$DGS BEG_BLK, ??bb10_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 0199H +$DGS END_BLK, ??eb10_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 043H +$DGS BEG_BLK, ??bb11_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 00H +$DGS END_BLK, ??eb11_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 043H +$DGS END_BLK, ??eb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 043H +$DGS END_FUN, ??ef_tsk_batt, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04DH +$DGS GLV_SYM, _intp4_extdc, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 01A7H, 00H, 00H +$DGS BEG_FUN, ??bf_intp4_extdc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02D4H, 00H, 01A7H +$DGS END_FUN, ??ef_intp4_extdc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03H +$DGS GLV_SYM, _intp5_shell, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 01ADH, 00H, 00H +$DGS BEG_FUN, ??bf_intp5_shell, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02DFH, 00H, 01ADH +$DGS END_FUN, ??ef_intp5_shell, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03H +$DGS GLV_SYM, _intp6_PM_irq, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 01B7H, 00H, 00H +$DGS BEG_FUN, ??bf_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02E8H, 016H, 01B1H +$DGS BEG_BLK, ??bb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06H +$DGS END_FUN, ??ef_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 07H +$DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 01ECH, 00H, 00H +$DGS BEG_FUN, ??bf_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02F8H, 02H, 01BEH +$DGS STA_SYM, _reg_shadow, ?L0112, U, 0CH, 03H, 00H, 00H +$DGS REG_VAR, _reg1_old, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS REG_VAR, _irq_work, 07H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 01C2H +$DGS END_BLK, ??eb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS BEG_BLK, ??bb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 01C4H +$DGS BEG_BLK, ??bb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 01C8H +$DGS END_BLK, ??eb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS BEG_BLK, ??bb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 01CEH +$DGS END_BLK, ??eb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS END_BLK, ??eb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS BEG_BLK, ??bb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 01D0H +$DGS BEG_BLK, ??bb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 022H, 00H, 01D4H +$DGS END_BLK, ??eb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 025H +$DGS BEG_BLK, ??bb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 027H, 00H, 01DAH +$DGS END_BLK, ??eb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS END_BLK, ??eb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02BH +$DGS BEG_BLK, ??bb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04BH, 00H, 01DEH +$DGS END_BLK, ??eb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04DH +$DGS BEG_BLK, ??bb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 051H, 00H, 01E0H +$DGS BEG_BLK, ??bb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 056H, 00H, 01E6H +$DGS END_BLK, ??eb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 058H +$DGS END_BLK, ??eb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 059H +$DGS BEG_BLK, ??bb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05EH, 00H, 00H +$DGS END_BLK, ??eb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 061H +$DGS END_FUN, ??ef_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 063H +$DGS STA_SYM, _PM_get_batt_left, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0200H, 00H, 00H +$DGS BEG_FUN, ??bf_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0364H, 02H, 01F0H +$DGS BEG_BLK, ??bb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 01F2H +$DGS BEG_BLK, ??bb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 01FAH +$DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 06H, 02H, 02H, 00H, 00H, 00H, 00H +$DGS END_BLK, ??eb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS END_BLK, ??eb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS BEG_BLK, ??bb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 00H +$DGS END_BLK, ??eb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS END_FUN, ??ef_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01AH +$DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0206H, 00H, 00H +$DGS BEG_FUN, ??bf_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0388H, 00H, 0206H +$DGS END_FUN, ??ef_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 020CH, 00H, 00H +$DGS BEG_FUN, ??bf_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 038EH, 00H, 020CH +$DGS END_FUN, ??ef_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0217H, 00H, 00H +$DGS BEG_FUN, ??bf_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0394H, 02H, 0211H +$DGS REG_VAR, _cmd_BL, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 00H +$DGS END_BLK, ??eb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS END_FUN, ??ef_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0DH +$DGS GLV_SYM, _raw_adc_temperature, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _rcomp, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _temp_co_up, U, U, 06H, 026H, 00H, 00H +$DGS GLV_SYM, _temp_co_dn, U, U, 06H, 026H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_busy, U, U, 0134CH, 02H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_wo_dma, U, U, 034CH, 02H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, @@lstof, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG4, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@fmul, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@fdiv, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@fsub, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@ftols, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@frev, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG3, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, @@ftolu, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + + EXTRN _iic_mcu_write + EXTRN _iic_mcu_write_a_byte + EXTRN _wait_ms + EXTRN _iic_mcu_read_a_byte + EXTRN _vreg_ctr + EXTRN _@RTARG0 + EXTRN _@RTARG2 + EXTRN _system_status + EXTRN _iic_mcu_read + EXTRN _get_adc + EXTRN _renge_task_immed_add + EXTRN @@lstof + EXTRN _@RTARG4 + EXTRN @@fmul + EXTRN @@fdiv + EXTRN @@fsub + EXTRN @@ftols + EXTRN @@frev + EXTRN _@RTARG3 + EXTRN @@ftolu + EXTRN _set_irq + EXTRN _@SEGAX + EXTRN _@SEGDE + EXTRN _iic_mcu_bus_status + EXTBIT _iic_mcu_busy + EXTBIT _iic_mcu_wo_dma + PUBLIC _raw_adc_temperature + PUBLIC _rcomp + PUBLIC _temp_co_up + PUBLIC _temp_co_dn + PUBLIC _PM_init + PUBLIC _PM_bt_temp_update + PUBLIC _PM_LCD_on + PUBLIC _PM_LCD_off + PUBLIC _PM_BL_set + PUBLIC _PM_LCD_vcom_set + PUBLIC _tski_vcom_set + PUBLIC _PM_sys_pow_on + PUBLIC _PM_sys_pow_off + PUBLIC _tsk_batt + PUBLIC _intp4_extdc + PUBLIC _intp5_shell + PUBLIC _intp6_PM_irq + PUBLIC _ntr_pmic_comm + PUBLIC _tski_PM_LCD_on + PUBLIC _tski_PM_LCD_off + PUBLIC _tski_PM_BL_set + +@@BITS BSEG +?L0079 DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 +_BT_PARAM: DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 0ADH ; 173 + DB 030H ; 48 + DB 0AEH ; 174 + DB 070H ; 112 + DB 0B0H ; 176 + DB 00H ; 0 + DB 0B3H ; 179 + DB 00H ; 0 + DB 0B4H ; 180 + DB 070H ; 112 + DB 0B5H ; 181 + DB 0A0H ; 160 + DB 0B7H ; 183 + DB 080H ; 128 + DB 0BAH ; 186 + DB 00H ; 0 + DB 0BBH ; 187 + DB 090H ; 144 + DB 0BDH ; 189 + DB 00H ; 0 + DB 0BEH ; 190 + DB 00H ; 0 + DB 0BFH ; 191 + DB 0F0H ; 240 + DB 0C3H ; 195 + DB 00H ; 0 + DB 0C5H ; 197 + DB 0C0H ; 192 + DB 0C8H ; 200 + DB 00H ; 0 + DB 0CAH ; 202 + DB 0C0H ; 192 + DB 04H ; 4 + DB 00H ; 0 + DB 012H ; 18 + DB 00H ; 0 + DB 0CH ; 12 + DB 010H ; 16 + DB 024H ; 36 + DB 00H ; 0 + DB 010H ; 16 + DB 0D0H ; 208 + DB 01BH ; 27 + DB 0F0H ; 240 + DB 0AH ; 10 + DB 0F0H ; 240 + DB 08H ; 8 + DB 0E0H ; 224 + DB 0CH ; 12 + DB 0F0H ; 240 + DB 08H ; 8 + DB 0C0H ; 192 + DB 08H ; 8 + DB 0B0H ; 176 + DB 07H ; 7 + DB 0F0H ; 240 + DB 0BH ; 11 + DB 00H ; 0 + DB 05H ; 5 + DB 0D0H ; 208 + DB 02H ; 2 + DB 00H ; 0 + DB 09H ; 9 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB 0ADH ; 173 + DB 030H ; 48 + DB 0AEH ; 174 + DB 070H ; 112 + DB 0B0H ; 176 + DB 00H ; 0 + DB 0B3H ; 179 + DB 00H ; 0 + DB 0B4H ; 180 + DB 070H ; 112 + DB 0B5H ; 181 + DB 0A0H ; 160 + DB 0B7H ; 183 + DB 080H ; 128 + DB 0BAH ; 186 + DB 00H ; 0 + DB 0BBH ; 187 + DB 090H ; 144 + DB 0BDH ; 189 + DB 00H ; 0 + DB 0BEH ; 190 + DB 00H ; 0 + DB 0BFH ; 191 + DB 0F0H ; 240 + DB 0C3H ; 195 + DB 00H ; 0 + DB 0C5H ; 197 + DB 0C0H ; 192 + DB 0C8H ; 200 + DB 00H ; 0 + DB 0CAH ; 202 + DB 0C0H ; 192 + DB 04H ; 4 + DB 00H ; 0 + DB 012H ; 18 + DB 00H ; 0 + DB 0CH ; 12 + DB 010H ; 16 + DB 024H ; 36 + DB 00H ; 0 + DB 010H ; 16 + DB 0D0H ; 208 + DB 01BH ; 27 + DB 0F0H ; 240 + DB 0AH ; 10 + DB 0F0H ; 240 + DB 08H ; 8 + DB 0E0H ; 224 + DB 0CH ; 12 + DB 0F0H ; 240 + DB 08H ; 8 + DB 0C0H ; 192 + DB 08H ; 8 + DB 0B0H ; 176 + DB 07H ; 7 + DB 0F0H ; 240 + DB 0BH ; 11 + DB 00H ; 0 + DB 05H ; 5 + DB 0D0H ; 208 + DB 02H ; 2 + DB 00H ; 0 + DB 09H ; 9 + DB 00H ; 0 +_BT_PANA_RCOMP: DB 087H ; 135 +_BT_PANA_TEMPCOUP: DW 0999AH,03E99H ; 1050253722 +_BT_PANA_TEMPCODN: DW 00000H,03F00H ; 1056964608 + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB 00H ; 0 + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0018: DS (1) +?L0077: DS (1) +?L0078: DS (1) + DS (1) + +@@DATA DSEG BASEP +_raw_adc_temperature: DS (1) +_rcomp: DS (1) +_temp_co_up: DS (4) +_temp_co_dn: DS (4) +?L0019: DS (1) + DS (1) +?L0020: DS (2) +?L0112: DS (1) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0153: + mov x,#06CH ; 108 ;[INF] 2, 1 + br !_iic_mcu_write ;[INF] 3, 3 +es_F0153: + +ROM_CODE CSEG BASE +bs_F0154: + mov x,#084H ; 132 ;[INF] 2, 1 + br !_iic_mcu_write_a_byte ;[INF] 3, 3 +es_F0154: + +ROM_CODE CSEG BASE +bs_F0155: + movw ax,#010H ; 16 ;[INF] 3, 1 + br !_wait_ms ;[INF] 3, 3 +es_F0155: + +ROM_CODE CSEG BASE +bs_F0151: + push ax ;[INF] 1, 1 + mov x,#06CH ; 108 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0151: + +ROM_CODE CSEG BASE +bs_S0152: + mov c,a ;[INF] 1, 1 + movw de,#loww (_vreg_ctr+19) ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + or a,c ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_S0152: + +ROM_CODE CSEG BASE +bs_F0149: + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0149: + +ROM_CODE CSEG BASE +bs_F0150: + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0150: + +ROM_CODE CSEG BASE +bs_F0146: + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0146: + +ROM_CODE CSEG BASE +bs_F0147: + movw ax,#03H ; 3 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + and a,#01H ; 1 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0147: + +ROM_CODE CSEG BASE +bs_F0148: + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0148: + +ROM_CODE CSEG BASE +bs_S0144: + movw ax,!?L0020 ; temperature ;[INF] 3, 1 + subw ax,#014H ; 20 ;[INF] 3, 1 + movw bc,ax ;[INF] 1, 1 + sarw ax,15 ;[INF] 2, 1 + xchw ax,bc ;[INF] 1, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + movw ax,bc ;[INF] 1, 1 + movw _@RTARG2,ax ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0144: + +ROM_CODE CSEG BASE +bs_F0145: + movw ax,#07H ; 7 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0145: + +; *** Sub-Routine Information *** +; +; $SUB bs_S0144 +; CODE SIZE= 16 bytes +; +; $SUB bs_F0145 +; CODE SIZE= 15 bytes +; +; $SUB bs_F0146 +; CODE SIZE= 12 bytes +; +; $SUB bs_F0147 +; CODE SIZE= 14 bytes +; +; $SUB bs_F0148 +; CODE SIZE= 13 bytes +; +; $SUB bs_F0149 +; CODE SIZE= 12 bytes +; +; $SUB bs_F0150 +; CODE SIZE= 11 bytes +; +; $SUB bs_F0151 +; CODE SIZE= 9 bytes +; +; $SUB bs_S0152 +; CODE SIZE= 9 bytes +; +; $SUB bs_F0153 +; CODE SIZE= 5 bytes +; +; $SUB bs_F0154 +; CODE SIZE= 5 bytes +; +; $SUB bs_F0155 +; CODE SIZE= 6 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : 対PMIC +; line 3 : 藤田＠開技 +; line 4 : nintendo +; line 5 : '08 Dec +; line 6 : ======================================================== */ +; line 7 : #pragma nop +; line 8 : +; line 9 : #include "incs.h" +; line 10 : #include "adc.h" +; line 11 : #include "led.h" +; line 12 : #include "pm.h" +; line 13 : #include "renge.h" +; line 14 : +; line 15 : #include "batt_params.h" +; line 16 : +; line 17 : #include +; line 18 : #include "fsl_user.h" +; line 19 : extern u16 pool[]; +; line 20 : +; line 21 : // ======================================================== +; line 22 : +; line 23 : +; line 24 : // ======================================================== +; line 25 : u8 raw_adc_temperature; +; line 26 : u8 rcomp; +; line 27 : float temp_co_up; +; line 28 : float temp_co_dn; +; line 29 : +; line 30 : // ======================================================== +; line 31 : static void PM_get_batt_left(); +; line 32 : +; line 33 : +; line 34 : /******************************************************//** +; line 35 : PMIC達の初期化 +; line 36 : \n 電池メーカー識別 +; line 37 : \n 電池残量ICのセット +; line 38 : \n バージョン情報の取得 +; line 39 : \n +; line 40 : \n 以下のピンは主にここで操作・監視されます。 +; line 41 : \n ・PM_BT_DET,_P +; line 42 : *********************************************************/ +; line 43 : #define swap_endian_16( x ) (unsigned int)( x << 8 | x >> 8 ) +; line 44 : +; line 45 : void PM_init( ) +; line 46 : { + +ROM_CODE CSEG BASE +_PM_init: +$DGL 1,102 + push hl ;[INF] 1, 1 + subw sp,#08H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_PM_init: +; line 47 : u8 temp; +; line 48 : u8 origParam[4]; +; line 49 : union{ +; line 50 : u16 _u16; // ↓でわかるように、little endi +; an です。注意。 +; line 51 : struct{ +; line 52 : u8 lsb; +; line 53 : u8 msb; +; line 54 : }chars; +; line 55 : }dat_16; +; line 56 : +; line 57 : system_status.model = MODEL_JIKKI; +$DGL 0,12 + clrb !_system_status+3 ;[INF] 3, 1 +; line 58 : wait_ms( 150 ); +$DGL 0,13 + movw ax,#096H ; 150 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 59 : +; line 60 : // -1. なんかおかしい…　リセットをかけてみる +; line 61 : dat_16._u16 = swap_endian_16( 0x5400 ); // reset +$DGL 0,16 + movw ax,#054H ; 84 ;[INF] 3, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 62 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_COMMAND, 2, &d +; at_16 ); // こいつはNACKを返す +$DGL 0,17 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#0FEH ; 254 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 63 : +; line 64 : // 0. バッテリ残量IC クイックスタート +; line 65 : dat_16._u16 = swap_endian_16( 0x4000 ); // quick start +$DGL 0,20 + movw ax,#040H ; 64 ;[INF] 3, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 66 : if( iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_MODE, 2, & +; dat_16 ) != ERR_SUCCESS ) +$DGL 0,21 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#06H ; 6 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 + cmp0 c ;[INF] 1, 1 + bz $?L0003 ;[INF] 2, 4 +; line 67 : { +??bb00_PM_init: +; line 68 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; +$DGL 0,23 + set1 !_vreg_ctr+14.0 ;[INF] 4, 2 +; line 69 : system_status.model = MODEL_TS_BOARD; +$DGL 0,24 + oneb !_system_status+3 ;[INF] 3, 1 +??eb00_PM_init: +; line 70 : } +$DGL 0,25 + br !?L0004 ;[INF] 3, 3 +?L0003: +; line 71 : else +; line 72 : { +??bb01_PM_init: +; line 73 : // 1. ロック解除 +; line 74 : dat_16._u16 = swap_endian_16( 0x4057 ); // unlock key +$DGL 0,29 + movw ax,#05740H ; 22336 ;[INF] 3, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 75 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, & +; dat_16 ); +$DGL 0,30 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#03EH ; 62 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 76 : +; line 77 : // 2. 初期パラメータを一時保存 +; line 78 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, o +; rigParam ); +$DGL 0,33 + movw ax,hl ;[INF] 1, 1 + addw ax,#03H ;[INF] 3, 1 + push ax ;[INF] 1, 1 + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0CH ; 12 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#06CH ; 108 ;[INF] 2, 1 + call !_iic_mcu_read ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 79 : +; line 80 : // 3. 一時的にOCVを変更 +; line 81 : dat_16._u16 = swap_endian_16( 0xD4C0 ); // マジックナンバ +; ー的なもの。メーカー指定 +$DGL 0,36 + movw ax,#0C0D4H ; -16172 ;[INF] 3, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 82 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d +; at_16 ); +$DGL 0,37 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#0EH ; 14 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 83 : +; line 84 : // 4. 一時的にRCOMPを変更 +; line 85 : dat_16._u16 = swap_endian_16( 0xFF00 ); +$DGL 0,40 + clrw ax ;[INF] 1, 1 + dec x ;[INF] 1, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 86 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, +; &dat_16 ); +$DGL 0,41 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#0CH ; 12 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 87 : +; line 88 : // 電池メーカーの識別 +; line 89 : BT_DET_P = 1; +$DGL 0,44 + set1 P1.6 ;[INF] 3, 2 +; line 90 : temp = ( u8 ) ( ( get_adc( ADC_SEL_BATT_DET ) >> 5 ) -1 +; ); // 識別値０の白箱の分、インデックス合わせ +$DGL 0,45 + movw ax,#09H ; 9 ;[INF] 3, 1 + call !_get_adc ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + shrw ax,13 ;[INF] 2, 1 + decw ax ;[INF] 1, 1 + mov a,x ;[INF] 1, 1 + mov [hl+7],a ; temp ;[INF] 2, 1 +; line 91 : BT_DET_P = 0; +$DGL 0,46 + clr1 P1.6 ;[INF] 3, 2 +; line 92 : +; line 93 : iic_mcu_set_wo_dma( ); +$DGL 0,48 +??bb02_PM_init: +?L0005: + bf _iic_mcu_busy,$?L0006 ;[INF] 4, 5 +??bb03_PM_init: +??eb03_PM_init: + br $?L0005 ;[INF] 2, 3 +?L0006: + set1 _iic_mcu_wo_dma ;[INF] 3, 2 +??eb02_PM_init: +; line 94 : // 5.メーカー別パラメータのロード +; line 95 : switch ( temp ) +$DGL 0,50 + mov a,[hl+7] ; temp ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + clrw bc ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0008 ;[INF] 2, 4 + subw ax,#03H ; 3 ;[INF] 3, 1 + bz $?L0009 ;[INF] 2, 4 + subw ax,#04H ; 4 ;[INF] 3, 1 + br $?L0009 ;[INF] 2, 3 +; line 96 : { +??bb04_PM_init: +; line 97 : case( BT_VENDER_SHIROBAKO ): +?L0008: +; line 98 : system_status.model = MODEL_SHIROBAKO; +$DGL 0,53 + mov !_system_status+3,#02H ; 2 ;[INF] 4, 1 +; line 99 : break; +$DGL 0,54 + br $?L0007 ;[INF] 2, 3 +; line 100 : +; line 101 : case( BT_VENDER_PANA ): +?L0009: +; line 102 : case( BT_VENDER_MAXELL ): +; line 103 : default: +; line 104 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_BT_PAR +; AM, 64, &BT_PARAM[0] ); +$DGL 0,59 + movw de,#loww (_BT_PARAM) ;[INF] 3, 1 + push de ;[INF] 1, 1 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 105 : rcomp = BT_PANA_RCOMP; +$DGL 0,60 + mov a,!_BT_PANA_RCOMP ;[INF] 3, 1 + mov !_rcomp,a ;[INF] 3, 1 +; line 106 : temp_co_up = BT_PANA_TEMPCOUP; +$DGL 0,61 + movw bc,!_BT_PANA_TEMPCOUP+2 ;[INF] 3, 1 + movw ax,!_BT_PANA_TEMPCOUP ;[INF] 3, 1 + movw !_temp_co_up,ax ;[INF] 3, 1 + xchw ax,bc ;[INF] 1, 1 + movw !_temp_co_up+2,ax ;[INF] 3, 1 +; line 107 : temp_co_dn = BT_PANA_TEMPCODN; +$DGL 0,62 + movw bc,!_BT_PANA_TEMPCODN+2 ;[INF] 3, 1 + movw ax,!_BT_PANA_TEMPCODN ;[INF] 3, 1 + movw !_temp_co_dn,ax ;[INF] 3, 1 + xchw ax,bc ;[INF] 1, 1 + movw !_temp_co_dn+2,ax ;[INF] 3, 1 +; line 108 : break; +??eb04_PM_init: +; line 109 : } +?L0007: +; line 110 : +; line 111 : // 6. 150ms以上待つ +; line 112 : wait_ms( 200 ); +$DGL 0,67 + movw ax,#0C8H ; 200 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 113 : +; line 114 : // 7. OCVに「とある値」を書く +; line 115 : dat_16._u16 = swap_endian_16( 0xD4C0 ); +$DGL 0,70 + movw ax,#0C0D4H ; -16172 ;[INF] 3, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 116 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d +; at_16 ); +$DGL 0,71 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#0EH ; 14 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 117 : +; line 118 : // 8. 150〜600ms待つ。600msは厳守 +; line 119 : wait_ms( 200 ); +$DGL 0,74 + movw ax,#0C8H ; 200 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 120 : +; line 121 : // 9. SOCを読む。ベリファイのため。 +; line 122 : temp = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R +; EG_SOC ); +$DGL 0,77 + movw ax,#04H ; 4 ;[INF] 3, 1 + call !bs_F0151 ;[INF] 3, 3 + mov [hl+7],a ; temp ;[INF] 2, 1 +; line 123 : +; line 124 : if( 0x6D == temp || temp == 0x6E || temp == 0x6F ){ +$DGL 0,79 + cmp a,#06DH ; 109 ;[INF] 2, 1 + bz $?L0015 ;[INF] 2, 4 + mov a,[hl+7] ; temp ;[INF] 2, 1 + cmp a,#06EH ; 110 ;[INF] 2, 1 + bz $?L0015 ;[INF] 2, 4 + mov a,[hl+7] ; temp ;[INF] 2, 1 + cmp a,#06FH ; 111 ;[INF] 2, 1 +?L0015: +??bb05_PM_init: +??eb05_PM_init: +; line 125 : // カスタムモデル書き込みOK！ +; line 126 : }else{ +??bb06_PM_init: +??eb06_PM_init: +; line 127 : // 失敗だったらリトライするのか？ +; line 128 : } +; line 129 : +; line 130 : // 10.元のRCOMPとOCVを書き戻す +; line 131 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, +; origParam ); +$DGL 0,86 + movw ax,hl ;[INF] 1, 1 + addw ax,#03H ;[INF] 3, 1 + push ax ;[INF] 1, 1 + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0CH ; 12 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 132 : +; line 133 : // 11. ロック +; line 134 : dat_16._u16 = swap_endian_16( 0x0000 ); // lock key +$DGL 0,89 + clrw ax ;[INF] 1, 1 + movw [hl],ax ; dat_16 ;[INF] 1, 1 +; line 135 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, & +; dat_16 ); +$DGL 0,90 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#03EH ; 62 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +??eb01_PM_init: +; line 136 : +; line 137 : // おしまい // +; line 138 : } +?L0004: +; line 139 : +; line 140 : // 電池温度測定 +; line 141 : BT_TEMP_P = 1; // 電池温度監視スタート +$DGL 0,96 + set1 P1.7 ;[INF] 3, 2 +; line 142 : raw_adc_temperature = get_adc( ADC_SEL_BATT_TEMP ); // 温度の +; temp。 +$DGL 0,97 + movw ax,#08H ; 8 ;[INF] 3, 1 + call !_get_adc ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_raw_adc_temperature,a ;[INF] 3, 1 +; line 143 : renge_task_immed_add( PM_bt_temp_update ); +$DGL 0,98 + movw ax,#loww (_PM_bt_temp_update) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 144 : +; line 145 : // PMIC バージョン読み出し +; line 146 : // temp = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VER +; ); +; line 147 : // vreg_ctr[ VREG_C_PM_INFO ] = temp; +; line 148 : // デバッグ用は別にまとめた +; line 149 : } +$DGL 0,104 +??ef_PM_init: + addw sp,#08H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_init: +; line 150 : +; line 151 : +; line 152 : +; line 153 : +; line 154 : +; line 155 : +; line 156 : /* ======================================================== +; line 157 : raw_adc_temperatureに入っている値を℃に変換するとともに、 +; line 158 : ・レジスタにセット +; line 159 : ・残量ICにセット +; line 160 : todo +; line 161 : ======================================================== */ +; line 162 : task_status_immed PM_bt_temp_update( ) +; line 163 : { +_PM_bt_temp_update: +$DGL 1,154 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_PM_bt_temp_update: +; line 164 : static u8 count = 0; // たまにしか書きに行かない +; line 165 : +; line 166 : static u8 rawdat_old; +; line 167 : static s16 temperature; // todo +; line 168 : u16 newrcomp; +; line 169 : +; line 170 : /* +; line 171 : サーミスタ - 10kΩ分圧点の時、 +; line 172 : 常用温度では分圧比のカーブがほぼリニアで、 +; line 173 : 村田 T[℃] = 81.48 - 111.97 x ratio +; line 174 : TDK T = 81.406 - 111.81 x ratio +; line 175 : */ +; line 176 : if( rawdat_old != raw_adc_temperature ){ +$DGL 0,14 + mov a,!?L0019 ; rawdat_old ;[INF] 3, 1 + cmp a,!_raw_adc_temperature ;[INF] 3, 1 + bz $?L0021 ;[INF] 2, 4 +??bb00_PM_bt_temp_update: +; line 177 : DBG_P_n = 1; +$DGL 0,15 + set1 P2.2 ;[INF] 3, 2 +; line 178 : temperature = 81.45 - 111.9 * raw_adc_temperature/256.0; +$DGL 0,16 + mov a,!_raw_adc_temperature ;[INF] 3, 1 + shrw ax,8 ;[INF] 2, 1 + clrw bc ;[INF] 1, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + movw ax,bc ;[INF] 1, 1 + movw _@RTARG2,ax ;[INF] 2, 1 + call !@@lstof ;[INF] 3, 3 + movw _@RTARG4,#0CCCDH ; -13107 ;[INF] 4, 1 + movw ax,#042DFH ; 17119 ;[INF] 3, 1 + call !@@fmul ;[INF] 3, 3 + movw _@RTARG4,#00H ; 0 ;[INF] 4, 1 + movw ax,#04380H ; 17280 ;[INF] 3, 1 + call !@@fdiv ;[INF] 3, 3 + movw ax,_@RTARG0 ;[INF] 2, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,_@RTARG2 ;[INF] 2, 1 + movw _@RTARG0,#0E666H ; -6554 ;[INF] 4, 1 + movw _@RTARG2,#042A2H ; 17058 ;[INF] 4, 1 + call !@@fsub ;[INF] 3, 3 + call !@@ftols ;[INF] 3, 3 + movw ax,_@RTARG0 ;[INF] 2, 1 + movw !?L0020,ax ; temperature ;[INF] 3, 1 +; line 179 : vreg_ctr[VREG_C_BT_TEMP] = (u8)temperature; +$DGL 0,17 + mov a,!?L0020 ; temperature ;[INF] 3, 1 + mov !_vreg_ctr+10,a ;[INF] 3, 1 +; line 180 : DBG_P_n = 0; +$DGL 0,18 + clr1 P2.2 ;[INF] 3, 2 +??eb00_PM_bt_temp_update: +; line 181 : } +?L0021: +; line 182 : +; line 183 : // 時々書きにゆく +; line 184 : if( count == 0 ) +$DGL 0,22 + cmp0 !?L0018 ; count ;[INF] 3, 1 + bnz $?L0031 ;[INF] 2, 4 +; line 185 : { +??bb01_PM_bt_temp_update: +; line 186 : DBG_P_n = 1; +$DGL 0,24 + set1 P2.2 ;[INF] 3, 2 +; line 187 : if( vreg_ctr[VREG_C_BT_TEMP] > 20 ) +$DGL 0,25 + cmp !_vreg_ctr+10,#015H ; 21 ;[INF] 4, 1 + bc $?L0025 ;[INF] 2, 4 +; line 188 : { +??bb02_PM_bt_temp_update: +; line 189 : newrcomp = -( ( temperature - 20 ) * temp_co_up ); +$DGL 0,27 + call !bs_S0144 ;[INF] 3, 3 + call !@@lstof ;[INF] 3, 3 + movw ax,!_temp_co_up ;[INF] 3, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,!_temp_co_up+2 ;[INF] 3, 1 + call !@@fmul ;[INF] 3, 3 + call !@@frev ;[INF] 3, 3 + bt _@RTARG3.7,$?L0027 ;[INF] 4, 5 + call !@@ftolu ;[INF] 3, 3 + br $?L0028 ;[INF] 2, 3 +?L0027: + call !@@ftols ;[INF] 3, 3 +?L0028: + movw ax,_@RTARG0 ;[INF] 2, 1 + movw [hl],ax ; newrcomp ;[INF] 1, 1 +??eb02_PM_bt_temp_update: +; line 190 : } +$DGL 0,28 + br $?L0026 ;[INF] 2, 3 +?L0025: +; line 191 : else +; line 192 : { +??bb03_PM_bt_temp_update: +; line 193 : newrcomp = -( ( temperature - 20 ) * temp_co_dn ); +$DGL 0,31 + call !bs_S0144 ;[INF] 3, 3 + call !@@lstof ;[INF] 3, 3 + movw ax,!_temp_co_dn ;[INF] 3, 1 + movw _@RTARG4,ax ;[INF] 2, 1 + movw ax,!_temp_co_dn+2 ;[INF] 3, 1 + call !@@fmul ;[INF] 3, 3 + call !@@frev ;[INF] 3, 3 + bt _@RTARG3.7,$?L0029 ;[INF] 4, 5 + call !@@ftolu ;[INF] 3, 3 + br $?L0030 ;[INF] 2, 3 +?L0029: + call !@@ftols ;[INF] 3, 3 +?L0030: + movw ax,_@RTARG0 ;[INF] 2, 1 + movw [hl],ax ; newrcomp ;[INF] 1, 1 +??eb03_PM_bt_temp_update: +; line 194 : } +?L0026: +; line 195 : newrcomp += rcomp; +$DGL 0,33 + mov x,!_rcomp ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + addw ax,[hl+0] ; newrcomp ;[INF] 3, 1 + movw [hl],ax ; newrcomp ;[INF] 1, 1 +; line 196 : +; line 197 : newrcomp = swap_endian_16( (u16)newrcomp ); +$DGL 0,35 + shlw ax,8 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + or a,[hl+1] ; newrcomp ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + movw [hl],ax ; newrcomp ;[INF] 1, 1 +; line 198 : DBG_P_n = 0; +$DGL 0,36 + clr1 P2.2 ;[INF] 3, 2 +; line 199 : +; line 200 : if( iic_mcu_write +; line 201 : ( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, &newrcomp +; ) == ERR_SUCCESS ) +$DGL 0,39 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#0CH ; 12 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0153 ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 + cmp0 c ;[INF] 1, 1 + bnz $?L0031 ;[INF] 2, 4 +; line 202 : { +??bb04_PM_bt_temp_update: +; line 203 : rawdat_old = raw_adc_temperature; +$DGL 0,41 + mov a,!_raw_adc_temperature ;[INF] 3, 1 + mov !?L0019,a ; rawdat_old ;[INF] 3, 1 +??eb04_PM_bt_temp_update: +; line 204 : } +?L0031: +??eb01_PM_bt_temp_update: +; line 205 : } +; line 206 : count += 1; +$DGL 0,44 + inc !?L0018 ; count ;[INF] 3, 2 +; line 207 : +; line 208 : return ( ERR_SUCCESS ); +$DGL 0,46 + clrw bc ;[INF] 1, 1 +; line 209 : } +$DGL 0,47 +??ef_PM_bt_temp_update: + pop ax ;[INF] 1, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_bt_temp_update: +; line 210 : +; line 211 : +; line 212 : +; line 213 : #ifdef _PMIC_TWL_ +; line 214 : u8 blset; +; line 215 : #endif +; line 216 : +; line 217 : #ifndef _PARRADIUM_ +; line 218 : /* ======================================================== +; line 219 : 液晶系の電源制御 +; line 220 : 　ステータスフラグはすぐに立ててしまう。 +; line 221 : 　不感応時間があるし、 +; line 222 : 起動失敗であれば電源が落ちる +; line 223 : 別のタスクで電源落ちは監視していて、ステータスもクリアする +; line 224 : ======================================================== */ +; line 225 : // BSR // +; line 226 : err PM_LCD_on( ) +; line 227 : { +_PM_LCD_on: +$DGL 1,184 + push hl ;[INF] 1, 1 +??bf_PM_LCD_on: +; line 228 : u8 rv; +; line 229 : +; line 230 : PM_VDDLCD_on( ); +$DGL 0,4 + call !bs_F0145 ;[INF] 3, 3 +; line 231 : +; line 232 : wait_ms( DELAY_PM_TSS_50B_AND_TCOM ); +$DGL 0,6 + movw ax,#011H ; 17 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 233 : +; line 234 : PM_TCOM_on( ); +$DGL 0,8 + movw ax,#0FH ; 15 ;[INF] 3, 1 + call !bs_F0146 ;[INF] 3, 3 +; line 235 : +; line 236 : wait_ms( DELAY_PM_TCOM_TO_VCS ); +$DGL 0,10 + movw ax,#03H ; 3 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 237 : +; line 238 : PM_VCS_on( ); +$DGL 0,12 + movw ax,#01FH ; 31 ;[INF] 3, 1 + call !bs_F0146 ;[INF] 3, 3 +; line 239 : +; line 240 : wait_ms( DELAY_PM_VCS_TO_BL ); +$DGL 0,14 + movw ax,#016H ; 22 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 241 : #ifdef _PM_BUG_ +; line 242 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0x4A ); // バグ持 +; ちPMIC対策 +; line 243 : #endif +; line 244 : +; line 245 : rv = PM_chk_LDSW( ); +$DGL 0,19 + call !bs_F0147 ;[INF] 3, 3 + mov l,a ;[INF] 1, 1 +; line 246 : +; line 247 : if( rv != 0 ) +$DGL 0,21 + cmp0 a ;[INF] 1, 1 + bz $?L0035 ;[INF] 2, 4 +; line 248 : { +??bb00_PM_LCD_on: +; line 249 : // 電源起動エラーなら電源も切れてしまう。ここではケアしな +; い +; line 250 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; +$DGL 0,24 + set1 !_vreg_ctr+15.7 ;[INF] 4, 2 +; line 251 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); +$DGL 0,25 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#013H ; 19 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 252 : +; line 253 : SND_DEPOP_DEACT; // 1でミュート +??eb00_PM_LCD_on: +; line 254 : } +?L0035: +; line 255 : +; line 256 : #ifdef _PMIC_TWL_ +; line 257 : PM_TEG_LCD_dis( 0 ); +; line 258 : blset = ( PM_REG_BIT_BL_U | PM_REG_BIT_BL_L ); +; line 259 : #endif +; line 260 : return ( rv ); +$DGL 0,34 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 +; line 261 : } +$DGL 0,35 +??ef_PM_LCD_on: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_LCD_on: +; line 262 : +; line 263 : // BSR // +; line 264 : void PM_LCD_off() +; line 265 : { +_PM_LCD_off: +$DGL 1,195 + push hl ;[INF] 1, 1 +??bf_PM_LCD_off: +; line 266 : SND_DEPOP_ACT; +; line 267 : +; line 268 : // BLついてたら消す +; line 269 : #ifdef _PMIC_TWL_ +; line 270 : if( blset != 0 ) +; line 271 : #else +; line 272 : if( ( iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) & +; 0x03 ) != 0 ) +$DGL 0,8 + call !bs_F0149 ;[INF] 3, 3 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0039 ;[INF] 2, 4 +; line 273 : #endif +; line 274 : { +??bb00_PM_LCD_off: +; line 275 : u8 tot; +; line 276 : +; line 277 : PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ) +; ; +$DGL 0,13 + movw ax,#014H ; 20 ;[INF] 3, 1 + call !_PM_BL_set ;[INF] 3, 3 +; line 278 : vreg_ctr[VREG_C_STATUS] &= 0b10011111; +$DGL 0,14 + movw de,#loww (_vreg_ctr+15) ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + and a,#09FH ; 159 ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 279 : +; line 280 : if( (( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr +; [ VREG_C_IRQ_MASK3 ] ) != 0 ) +$DGL 0,16 + mov a,[de+12] ;[INF] 2, 1 + xor a,#0FFH ; 255 ;[INF] 2, 1 + mov x,#0FFH ; 255 ;[INF] 2, 1 + and a,#014H ; 20 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0041 ;[INF] 2, 4 +; line 281 : { +??bb01_PM_LCD_off: +; line 282 : vreg_ctr[ VREG_C_IRQ3 ] |= ( ( REG_BIT_BL_U_OFF | RE +; G_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ); +$DGL 0,18 + mov a,[de+12] ;[INF] 2, 1 + xor a,#0FFH ; 255 ;[INF] 2, 1 + and a,#014H ; 20 ;[INF] 2, 1 + call !bs_S0152 ;[INF] 3, 3 +; line 283 : IRQ0_neg; +$DGL 0,19 +??bb02_PM_LCD_off: + set1 PM7.6 ;[INF] 3, 2 +??eb02_PM_LCD_off: +; line 284 : tot = 0; +$DGL 0,20 + mov l,#00H ; 0 ;[INF] 2, 1 +; line 285 : while( !IRQ0 && ( ++tot != 0 ) ){;} +$DGL 0,21 +?L0043: + bt P7.6,$?L0044 ;[INF] 4, 5 + inc l ;[INF] 1, 1 + mov a,l ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0043 ;[INF] 2, 4 +??bb03_PM_LCD_off: +??eb03_PM_LCD_off: +?L0044: +; line 286 : IRQ0_ast; +$DGL 0,22 +??bb04_PM_LCD_off: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb04_PM_LCD_off: +??eb01_PM_LCD_off: +; line 287 : } +?L0041: +; line 288 : vreg_ctr[VREG_C_COMMAND2] &= ~( REG_BIT_CMD_BL_U_OFF | R +; EG_BIT_CMD_BL_L_OFF ); +$DGL 0,24 + movw de,#loww (_vreg_ctr+34) ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + and a,#0EBH ; 235 ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +??eb00_PM_LCD_off: +; line 289 : } +?L0039: +; line 290 : +; line 291 : #ifdef _PMIC_TWL_ +; line 292 : PM_TEG_LCD_dis( 1 ); +; line 293 : blset = 0; +; line 294 : #endif +; line 295 : +; line 296 : PM_TCOM_VCS_off( ); +$DGL 0,32 + call !bs_F0145 ;[INF] 3, 3 +; line 297 : wait_ms( DELAY_PM_LCD_OFF ); +$DGL 0,33 + movw ax,#033H ; 51 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 298 : +; line 299 : PM_VDDLCD_off( ); // 残ってたの全部止めます。 +$DGL 0,35 + clrw ax ;[INF] 1, 1 + call !bs_F0146 ;[INF] 3, 3 +; line 300 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; +$DGL 0,36 + clr1 !_vreg_ctr+15.7 ;[INF] 4, 2 +; line 301 : +; line 302 : +; line 303 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); +$DGL 0,39 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#013H ; 19 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 304 : } +$DGL 0,40 +??ef_PM_LCD_off: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_LCD_off: +; line 305 : +; line 306 : +; line 307 : +; line 308 : /* ======================================================== +; line 309 : 　バックライトの個別on/off +; line 310 : 　現状から　on/off/維持　のフラグなので面倒 +; line 311 : 　　例えば、BL on/on の状態で、on/onにしろと言われても、on/on割り +; 込みを入れます。 +; line 312 : ======================================================== */ +; line 313 : err PM_BL_set( u8 dat ) +; line 314 : { +_PM_BL_set: +$DGL 1,223 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + subw sp,#04H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_PM_BL_set: +; line 315 : #ifndef _PMIC_TWL_ +; line 316 : u8 blset; +; line 317 : #endif +; line 318 : u8 intset = 0; +$DGL 0,5 + mov [hl+2],#00H ; intset,0 ;[INF] 3, 1 +; line 319 : // RMWを行う +; line 320 : +; line 321 : #ifndef _PMIC_TWL_ +; line 322 : // Read +; line 323 : blset = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) +; ; +$DGL 0,10 + call !bs_F0149 ;[INF] 3, 3 + mov [hl+3],a ; blset ;[INF] 2, 1 +; line 324 : #endif +; line 325 : +; line 326 : // Modify +; line 327 : // ue +; line 328 : if(( dat & REG_BIT_CMD_BL_U_ON ) != 0 ) +$DGL 0,15 + mov a,[hl+4] ; dat ;[INF] 2, 1 + and a,#020H ; 32 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0047 ;[INF] 2, 4 +; line 329 : { +??bb00_PM_BL_set: +; line 330 : blset |= PM_REG_BIT_BL_U; +$DGL 0,17 + mov a,[hl+3] ; blset ;[INF] 2, 1 + or a,#01H ; 1 ;[INF] 2, 1 + mov [hl+3],a ; blset ;[INF] 2, 1 +; line 331 : intset |= REG_BIT_BL_U_ON; +$DGL 0,18 + mov a,[hl+2] ; intset ;[INF] 2, 1 + or a,#020H ; 32 ;[INF] 2, 1 + mov [hl+2],a ; intset ;[INF] 2, 1 +??eb00_PM_BL_set: +; line 332 : } +$DGL 0,19 + br $?L0049 ;[INF] 2, 3 +?L0047: +; line 333 : else if(( dat & REG_BIT_CMD_BL_U_OFF ) != 0 ) +$DGL 0,20 + mov a,[hl+4] ; dat ;[INF] 2, 1 + and a,#010H ; 16 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0049 ;[INF] 2, 4 +; line 334 : { +??bb01_PM_BL_set: +; line 335 : blset &= ~PM_REG_BIT_BL_U; +$DGL 0,22 + mov a,[hl+3] ; blset ;[INF] 2, 1 + and a,#0FEH ; 254 ;[INF] 2, 1 + mov [hl+3],a ; blset ;[INF] 2, 1 +; line 336 : intset |= REG_BIT_BL_U_OFF; +$DGL 0,23 + mov a,[hl+2] ; intset ;[INF] 2, 1 + or a,#010H ; 16 ;[INF] 2, 1 + mov [hl+2],a ; intset ;[INF] 2, 1 +??eb01_PM_BL_set: +; line 337 : } +?L0049: +; line 338 : +; line 339 : // shita +; line 340 : if(( dat & REG_BIT_CMD_BL_L_ON ) != 0 ) +$DGL 0,27 + mov a,[hl+4] ; dat ;[INF] 2, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0051 ;[INF] 2, 4 +; line 341 : { +??bb02_PM_BL_set: +; line 342 : blset |= PM_REG_BIT_BL_L; +$DGL 0,29 + mov a,[hl+3] ; blset ;[INF] 2, 1 + or a,#02H ; 2 ;[INF] 2, 1 + mov [hl+3],a ; blset ;[INF] 2, 1 +; line 343 : intset |= REG_BIT_BL_L_ON; +$DGL 0,30 + mov a,[hl+2] ; intset ;[INF] 2, 1 + or a,#08H ; 8 ;[INF] 2, 1 + mov [hl+2],a ; intset ;[INF] 2, 1 +??eb02_PM_BL_set: +; line 344 : } +$DGL 0,31 + br $?L0053 ;[INF] 2, 3 +?L0051: +; line 345 : else if(( dat & REG_BIT_CMD_BL_L_OFF ) != 0 ) +$DGL 0,32 + mov a,[hl+4] ; dat ;[INF] 2, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0053 ;[INF] 2, 4 +; line 346 : { +??bb03_PM_BL_set: +; line 347 : blset &= ~PM_REG_BIT_BL_L; +$DGL 0,34 + mov a,[hl+3] ; blset ;[INF] 2, 1 + and a,#0FDH ; 253 ;[INF] 2, 1 + mov [hl+3],a ; blset ;[INF] 2, 1 +; line 348 : intset |= REG_BIT_BL_L_OFF; +$DGL 0,35 + mov a,[hl+2] ; intset ;[INF] 2, 1 + or a,#04H ; 4 ;[INF] 2, 1 + mov [hl+2],a ; intset ;[INF] 2, 1 +??eb03_PM_BL_set: +; line 349 : } +?L0053: +; line 350 : +; line 351 : /* +; line 352 : SoCがPWMを出すようレジスタをセットしてから遅延が有るため、ステー +; タスを先に +; line 353 : 更新してしまう。 +; line 354 : // Write +; line 355 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); +; line 356 : if( blset != 0x00 ){ +; line 357 : wait_ms( 10 ); +; line 358 : } +; line 359 : */ +; line 360 : vreg_ctr[VREG_C_STATUS] = (( vreg_ctr[VREG_C_STATUS] & 0b100 +; 11111 ) +; line 361 : | (( blset << 6 ) | ( blset << 4 ) +; ) & 0b01100000 ); +$DGL 0,48 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + and a,#09FH ; 159 ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+3] ; blset ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + shlw ax,6 ;[INF] 2, 1 + movw de,ax ;[INF] 1, 1 + mov a,[hl+3] ; blset ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + shlw ax,4 ;[INF] 2, 1 + or a,d ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + or a,e ;[INF] 2, 1 + and a,#060H ; 96 ;[INF] 2, 1 + or c,a ;[INF] 2, 1 + mov a,c ;[INF] 1, 1 + mov !_vreg_ctr+15,a ;[INF] 3, 1 +; line 362 : // PMICのBLのビットと、MCUのSTATUSレジスタのビット位置が逆な +; ため入れ替え +; line 363 : +; line 364 : { +??bb04_PM_BL_set: +; line 365 : u8 tot; +; line 366 : +; line 367 : if( ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 ) +$DGL 0,54 + mov a,!_vreg_ctr+27 ;[INF] 3, 1 + xor a,#0FFH ; 255 ;[INF] 2, 1 + mov x,#0FFH ; 255 ;[INF] 2, 1 + and a,[hl+2] ; intset ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0055 ;[INF] 2, 4 +; line 368 : { +??bb05_PM_BL_set: +; line 369 : vreg_ctr[ VREG_C_IRQ3 ] |= ( intset & ~vreg_ctr[ VRE +; G_C_IRQ_MASK3 ] ); +$DGL 0,56 + mov a,!_vreg_ctr+27 ;[INF] 3, 1 + xor a,#0FFH ; 255 ;[INF] 2, 1 + and a,[hl+2] ; intset ;[INF] 2, 1 + call !bs_S0152 ;[INF] 3, 3 +; line 370 : IRQ0_neg; +$DGL 0,57 +??bb06_PM_BL_set: + set1 PM7.6 ;[INF] 3, 2 +??eb06_PM_BL_set: +; line 371 : tot = 0; +$DGL 0,58 + mov [hl+1],#00H ; tot,0 ;[INF] 3, 1 +; line 372 : while( !IRQ0 && ( ++tot != 0 ) ){;} // 割り込みを入 +; れ直す +$DGL 0,59 +?L0057: + bt P7.6,$?L0058 ;[INF] 4, 5 + inc [hl+1] ; tot ;[INF] 3, 2 + mov a,[hl+1] ; tot ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0057 ;[INF] 2, 4 +??bb07_PM_BL_set: +??eb07_PM_BL_set: +?L0058: +; line 373 : IRQ0_ast; +$DGL 0,60 +??bb08_PM_BL_set: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb08_PM_BL_set: +??eb05_PM_BL_set: +; line 374 : } +?L0055: +??eb04_PM_BL_set: +; line 375 : } +; line 376 : +; line 377 : // Write +; line 378 : if( blset != 0 ) // BLを付ける場合はウェイトを挟まないとPWM +; が来ておらず +$DGL 0,65 + mov a,[hl+3] ; blset ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0059 ;[INF] 2, 4 +; line 379 : /// シャットダウンすることがある +; line 380 : { +??bb09_PM_BL_set: +; line 381 : wait_ms( 10 ); +$DGL 0,68 + movw ax,#0AH ; 10 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +??eb09_PM_BL_set: +; line 382 : } +?L0059: +; line 383 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); +$DGL 0,70 + mov a,[hl+3] ; blset ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#04H ; 4 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 384 : +; line 385 : return( ERR_SUCCESS ); // ここでは異常チェック不要 +$DGL 0,72 + clrw bc ;[INF] 1, 1 +; line 386 : } +$DGL 0,73 +??ef_PM_BL_set: + addw sp,#06H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_BL_set: +; line 387 : +; line 388 : +; line 389 : +; line 390 : /* ======================================================== +; line 391 : 液晶の対向電圧の設定を行います。 +; line 392 : 仮想レジスタの内容を送るだけ +; line 393 : ======================================================== */ +; line 394 : err PM_LCD_vcom_set( ) +; line 395 : { +_PM_LCD_vcom_set: +$DGL 1,274 + push hl ;[INF] 1, 1 +??bf_PM_LCD_vcom_set: +; line 396 : u8 rv; +; line 397 : +; line 398 : rv = iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC +; 1, vreg_ctr[VREG_C_VCOM_T] ); // がっかりなことに、PMICはバース +; ト書き込み不可 +$DGL 0,4 + mov x,!_vreg_ctr+3 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#06H ; 6 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + mov a,c ;[INF] 1, 1 + mov l,a ;[INF] 1, 1 +; line 399 : rv |= iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DA +; C2, vreg_ctr[VREG_C_VCOM_B] ); +$DGL 0,5 + mov x,!_vreg_ctr+4 ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#07H ; 7 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + mov a,c ;[INF] 1, 1 + or l,a ;[INF] 2, 1 +; line 400 : return ( rv ); +$DGL 0,6 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 +; line 401 : } +$DGL 0,7 +??ef_PM_LCD_vcom_set: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_LCD_vcom_set: +; line 402 : +; line 403 : +; line 404 : +; line 405 : #else +; line 406 : // パラディウム上のSoCでチェックしたいとき、PMICも液晶もつながっ +; てないので +; line 407 : // 異常終了しないようにダミー関数にする +; line 408 : err PM_LCD_on( ) +; line 409 : { +; line 410 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; +; line 411 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); +; line 412 : SND_DEPOP_DEACT; // 1でミュート +; line 413 : return ( ERR_SUCCESS ); +; line 414 : } +; line 415 : +; line 416 : +; line 417 : void PM_LCD_off( ) +; line 418 : { +; line 419 : SND_DEPOP_ACT; +; line 420 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; +; line 421 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); +; line 422 : } +; line 423 : +; line 424 : +; line 425 : err PM_BL_set( u8 ) +; line 426 : { +; line 427 : wait_ms( 10 ); +; line 428 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & ~( +; REG_BIT_BL_U | REG_BIT_BL_L ) +; line 429 : | ( command_bl_set & REG_BIT_CMD_BL_U_ON )? REG_BIT_BL_U +; line 430 : | ( command_bl_set & REG_BIT_CMD_BL_L_ON )? REG_BIT_BL_L +; line 431 : ); +; line 432 : return ( PM_chk_LDSW( ) ); +; line 433 : } +; line 434 : +; line 435 : +; line 436 : err PM_LCD_vcom_set( ) +; line 437 : { +; line 438 : return ( ERR_SUCCESS ); +; line 439 : } +; line 440 : +; line 441 : #endif +; line 442 : +; line 443 : +; line 444 : +; line 445 : /* ======================================================== +; line 446 : ↑で、レジスタ書き込みから呼び出される時のため +; line 447 : 　I2Cの取り合いの関係でここから呼ぶ +; line 448 : ======================================================== */ +; line 449 : task_status_immed tski_vcom_set( ) +; line 450 : { +_tski_vcom_set: +$DGL 1,281 +??bf_tski_vcom_set: +; line 451 : PM_LCD_vcom_set( ); +$DGL 0,2 + call !_PM_LCD_vcom_set ;[INF] 3, 3 +; line 452 : return ( ERR_FINISED ); +$DGL 0,3 + clrw bc ;[INF] 1, 1 +; line 453 : } +$DGL 0,4 +??ef_tski_vcom_set: + ret ;[INF] 1, 6 +??ee_tski_vcom_set: +; line 454 : +; line 455 : +; line 456 : +; line 457 : /* ======================================================== +; line 458 : シーケンスの通り電源を立ち上げてゆきます。 +; line 459 : 返値 0 最後まで正常に完了した。 +; line 460 : 1 ショートなどで電源があがりきらなかった +; line 461 : +; line 462 : 以下のピンは主にここで操作・監視されます。 +; line 463 : ・POW_CONT1,2 TEG電源のみ +; line 464 : ======================================================== */ +; line 465 : err PM_sys_pow_on( ) +; line 466 : { +_PM_sys_pow_on: +$DGL 1,287 + push hl ;[INF] 1, 1 +??bf_PM_sys_pow_on: +; line 467 : #ifdef _PMIC_CTR_ +; line 468 : u8 temp; +; line 469 : +; line 470 : // 電池温度測定 +; line 471 : while( ADCEN != 0 ) +$DGL 0,6 +?L0067: + push hl ;[INF] 1, 1 + movw hl,#0F0H ; 240 ;[INF] 3, 1 + mov1 CY,[hl].5 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bc $?L0067 ;[INF] 2, 4 +; line 472 : {; +??bb00_PM_sys_pow_on: +??eb00_PM_sys_pow_on: +; line 473 : } +; line 474 : BT_TEMP_P = 1; +$DGL 0,9 + set1 P1.7 ;[INF] 3, 2 +; line 475 : vreg_ctr[VREG_C_BT_TEMP] = get_adc( ADC_SEL_BATT_TEMP ); +$DGL 0,10 + movw ax,#08H ; 8 ;[INF] 3, 1 + call !_get_adc ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + mov !_vreg_ctr+10,a ;[INF] 3, 1 +; line 476 : BT_TEMP_P = 0; +$DGL 0,11 + clr1 P1.7 ;[INF] 3, 2 +; line 477 : PM_bt_temp_update( ); // 温度のtemp。　残量ICに行きます +$DGL 0,12 + call !_PM_bt_temp_update ;[INF] 3, 3 +; line 478 : +; line 479 : // 残量チェック +; line 480 : PM_get_batt_left(); // 先に、PM_init()が実行されてい +; る必要があります。(大丈夫) +$DGL 0,15 + call !_PM_get_batt_left ;[INF] 3, 3 +; line 481 : // todo: batt remain -> volatage? +; line 482 : if( vreg_ctr[VREG_C_BT_REMAIN] < 0 ) +$DGL 0,17 + cmp0 !_vreg_ctr+11 ;[INF] 3, 1 + bnc $?L0069 ;[INF] 2, 4 +; line 483 : { +??bb01_PM_sys_pow_on: +; line 484 : return ( 1 ); +$DGL 0,19 + onew bc ;[INF] 1, 1 + br $?L0066 ;[INF] 2, 3 +??eb01_PM_sys_pow_on: +; line 485 : } +?L0069: +; line 486 : +; line 487 : // 電源順次立ち上げ +; line 488 : // PM_reset_ast( ); 不要 PM_LDSW_onまかせ +; line 489 : RESET2_ast; +$DGL 0,24 +??bb02_PM_sys_pow_on: + clr1 P0.1 ;[INF] 3, 2 + clr1 PM0.1 ;[INF] 3, 2 +??eb02_PM_sys_pow_on: +; line 490 : FCRAM_RST_ast; +$DGL 0,25 +??bb03_PM_sys_pow_on: + clr1 P3.0 ;[INF] 3, 2 +??eb03_PM_sys_pow_on: +; line 491 : +; line 492 : PM_LDSW_on( ); +$DGL 0,27 + call !bs_F0148 ;[INF] 3, 3 +; line 493 : +; line 494 : wait_ms( 1 ); +$DGL 0,29 + onew ax ;[INF] 1, 1 + call !_wait_ms ;[INF] 3, 3 +; line 495 : #ifdef _PM_BUG_ +; line 496 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0xCA ); // バグ持 +; ちPMIC対策 OVP解除 +; line 497 : #endif +; line 498 : +; line 499 : wait_ms( DELAY_PM_TW_PWUP ); +$DGL 0,34 + call !bs_F0155 ;[INF] 3, 3 +; line 500 : +; line 501 : PM_VDD_on( ); +$DGL 0,36 + movw ax,#0FH ; 15 ;[INF] 3, 1 + call !bs_F0150 ;[INF] 3, 3 +; line 502 : wait_ms( DELAY_PM_TW_PWUP ); +$DGL 0,37 + call !bs_F0155 ;[INF] 3, 3 +; line 503 : +; line 504 : PM_VDD50A_on( ); // 液晶電源ではなく、ledとかに使うものです +$DGL 0,39 + movw ax,#01FH ; 31 ;[INF] 3, 1 + call !bs_F0150 ;[INF] 3, 3 +; line 505 : +; line 506 : wait_ms( DELAY_PM_TW_PWUP ); +$DGL 0,41 + call !bs_F0155 ;[INF] 3, 3 +; line 507 : +; line 508 : PM_VDD_normMode(); +$DGL 0,43 + clrw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#05H ; 5 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 509 : #ifdef _PM_BUG_ +; line 510 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, 0x +; 03 ); // バグ持ちPMIC対策 強制PWM +; line 511 : #endif +; line 512 : if( PM_chk_LDSW( ) == 0 ) +$DGL 0,47 + call !bs_F0147 ;[INF] 3, 3 + cmp0 a ;[INF] 1, 1 + bnz $?L0071 ;[INF] 2, 4 +; line 513 : { +??bb04_PM_sys_pow_on: +; line 514 : return ( ERR_ERR ); +$DGL 0,49 + onew bc ;[INF] 1, 1 + br $?L0066 ;[INF] 2, 3 +??eb04_PM_sys_pow_on: +; line 515 : } +?L0071: +; line 516 : FCRAM_RST_neg; +$DGL 0,51 +??bb05_PM_sys_pow_on: + set1 P3.0 ;[INF] 3, 2 +??eb05_PM_sys_pow_on: +; line 517 : PM_reset_neg(); +$DGL 0,52 + movw ax,#03H ; 3 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 518 : RESET2_neg; +$DGL 0,53 +??bb06_PM_sys_pow_on: + set1 PM0.1 ;[INF] 3, 2 +??eb06_PM_sys_pow_on: +; line 519 : /* +; line 520 : wait_ms( 100 ); +; line 521 : { +; line 522 : // CODEC 不定レジスタ初期化 +; line 523 : u8 codec_reg_init[3] = { 0,0,0 }; +; line 524 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg +; _init ); +; line 525 : } +; line 526 : */ +; line 527 : +; line 528 : #else +; line 529 : // TWL PMIC +; line 530 : u8 temp; +; line 531 : +; line 532 : // 電源投入 +; line 533 : PM_reset_ast(); +; line 534 : RESET2_ast; +; line 535 : FCRAM_RST_ast; +; line 536 : +; line 537 : PM_TEG_PWSW = 1; +; line 538 : wait_ms( 160 ); +; line 539 : PM_TEG_PWSW = 0; +; line 540 : +; line 541 : +; line 542 : // 残量確認 +; line 543 : temp = 99; +; line 544 : if( temp < 5 ) +; line 545 : { +; line 546 : return ( ERR_ERR ); +; line 547 : } +; line 548 : vreg_ctr[VREG_C_BT_REMAIN] = temp; +; line 549 : FCRAM_RST_neg; +; line 550 : PM_reset_neg(); +; line 551 : RESET2_neg; +; line 552 : wait_ms( 100 ); +; line 553 : if( !RESET1_n ) +; line 554 : { +; line 555 : // 起動失敗 +; line 556 : PM_reset_ast(); +; line 557 : RESET2_ast; +; line 558 : FCRAM_RST_ast; +; line 559 : return ( ERR_ERR ); +; line 560 : } +; line 561 : /* +; line 562 : { // CODEC 不定レジスタ初期化 +; line 563 : u8 codec_reg_init[3] = { 0,0,0 }; +; line 564 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg +; _init ); +; line 565 : } +; line 566 : */ +; line 567 : #endif +; line 568 : +; line 569 : return ( ERR_SUCCESS ); +$DGL 0,104 + clrw bc ;[INF] 1, 1 +; line 570 : } +?L0066: +$DGL 0,105 +??ef_PM_sys_pow_on: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_sys_pow_on: +; line 571 : +; line 572 : +; line 573 : +; line 574 : +; line 575 : +; line 576 : +; line 577 : +; line 578 : /* ======================================================== +; line 579 : 電源OFFシーケンス +; line 580 : todo: 電源異常断の場合 +; line 581 : ======================================================== */ +; line 582 : err PM_sys_pow_off( ) +; line 583 : { +_PM_sys_pow_off: +$DGL 1,322 +??bf_PM_sys_pow_off: +; line 584 : #ifdef _PMIC_CTR_ +; line 585 : // PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ); +; line 586 : // PM_LCD_off( ); // TCOM,VCS OFF も消してき +; ます。 +; line 587 : +; line 588 : PM_reset_ast( ); +$DGL 0,6 + call !bs_F0148 ;[INF] 3, 3 +; line 589 : RESET2_ast; +$DGL 0,7 +??bb00_PM_sys_pow_off: + clr1 P0.1 ;[INF] 3, 2 + clr1 PM0.1 ;[INF] 3, 2 +??eb00_PM_sys_pow_off: +; line 590 : FCRAM_RST_ast; +$DGL 0,8 +??bb01_PM_sys_pow_off: + clr1 P3.0 ;[INF] 3, 2 +??eb01_PM_sys_pow_off: +; line 591 : +; line 592 : PM_off( ); +$DGL 0,10 + clrw ax ;[INF] 1, 1 + call !bs_F0150 ;[INF] 3, 3 +; line 593 : +; line 594 : PM_LDSW_off( ); +$DGL 0,12 + clrw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#03H ; 3 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + call !bs_F0154 ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 595 : #else +; line 596 : +; line 597 : if( RESET1_n ) +; line 598 : { +; line 599 : PM_reset_ast(); +; line 600 : RESET2_ast; +; line 601 : FCRAM_RST_ast; +; line 602 : PM_TEG_PWSW = 1; +; line 603 : wait_ms( 250 ); +; line 604 : wait_ms( 250 ); +; line 605 : wait_ms( 250 ); +; line 606 : PM_TEG_PWSW = 0; +; line 607 : } +; line 608 : PM_reset_ast(); +; line 609 : RESET2_ast; +; line 610 : FCRAM_RST_ast; +; line 611 : +; line 612 : #endif +; line 613 : return ( ERR_SUCCESS ); +$DGL 0,31 + clrw bc ;[INF] 1, 1 +; line 614 : } +$DGL 0,32 +??ef_PM_sys_pow_off: + ret ;[INF] 1, 6 +??ee_PM_sys_pow_off: +; line 615 : +; line 616 : +; line 617 : +; line 618 : /* ======================================================== +; line 619 : 電池の管理 +; line 620 : +; line 621 : 以下のピンは主にここで操作・監視されます。 +; line 622 : ・PM_BT_AUTH 現状、GPI in +; line 623 : ・PM_CHARGE_n CCIC /CHG in +; line 624 : ・PM_CHARGE_ERR_n /FLT in +; line 625 : ・PM_EXTDC_n /DOK INTP4 in +; line 626 : ・PM_CHARGE_EN_n /CEN out +; line 627 : +; line 628 : 以下の物は関係ありそうですが別のところで主に監視されています。 +; line 629 : ・LED_Pow R, B, Charge tsk_LED +; line 630 : ・BT_TEMP,_P tsk_ADC +; line 631 : +; line 632 : PM_EXTDCは割り込みメインにするかも +; line 633 : ======================================================== */ +; line 634 : #define INTERVAL_TSK_BATT 250 +; line 635 : +; line 636 : void tsk_batt( ) +; line 637 : { +_tsk_batt: +$DGL 1,336 +??bf_tsk_batt: +; line 638 : static u8 task_interval = 0; +; line 639 : static u8 charge_hys = 0; // ヒステリシスで上限下限を拡張す +; るとき１ +; line 640 : static bit pm_extdc_old; +; line 641 : +; line 642 : if( task_interval-- != 0 ) +$DGL 0,6 + mov a,!?L0077 ; task_interval ;[INF] 3, 1 + dec !?L0077 ; task_interval ;[INF] 3, 2 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 + br !?L0076 ;[INF] 3, 3 +; line 643 : { +??bb00_tsk_batt: +; line 644 : return; +??eb00_tsk_batt: +; line 645 : } +; line 646 : else +; line 647 : { +??bb01_tsk_batt: +; line 648 : task_interval = (u8)( INTERVAL_TSK_BATT / SYS_INTERVAL_T +; ICK ); +$DGL 0,12 + mov !?L0077,#080H ; task_interval,128 ;[INF] 4, 1 +??eb01_tsk_batt: +; line 649 : } +; line 650 : +; line 651 : +; line 652 : // アダプタ？ // +; line 653 : if( pm_extdc_old != !PM_EXTDC_n ) +$DGL 0,17 + mov1 CY,P7.0 ;[INF] 3, 1 + onew ax ;[INF] 1, 1 + subc x,a ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + mov1 CY,?L0079 ;[INF] 3, 1 + addc x,a ;[INF] 2, 1 + cmpw ax,bc ;[INF] 1, 1 + bz $?L0085 ;[INF] 2, 4 +; line 654 : { +??bb02_tsk_batt: +; line 655 : pm_extdc_old = !PM_EXTDC_n; +$DGL 0,19 + mov1 CY,P7.0 ;[INF] 3, 1 + onew ax ;[INF] 1, 1 + subc x,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + rorc a,1 ;[INF] 2, 1 + mov1 ?L0079,CY ;[INF] 3, 2 +; line 656 : if( pm_extdc_old ) +$DGL 0,20 + bf ?L0079,$?L0088 ;[INF] 4, 5 +; line 657 : { +??bb03_tsk_batt: +; line 658 : set_bit( 1, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP +; PLY ); +$DGL 0,22 +??bb04_tsk_batt: +??bb05_tsk_batt: + set1 !_vreg_ctr+15.3 ;[INF] 4, 2 +??eb05_tsk_batt: +??bb06_tsk_batt: +??eb06_tsk_batt: +; line 659 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_CONNECT ); +$DGL 0,23 +??eb04_tsk_batt: + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#011H ; 17 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb03_tsk_batt: +; line 660 : } +$DGL 0,24 + br $?L0085 ;[INF] 2, 3 +; line 661 : else +; line 662 : { +??bb07_tsk_batt: +; line 663 : set_bit( 0, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP +; PLY ); +$DGL 0,27 +??bb08_tsk_batt: +??bb09_tsk_batt: +??eb09_tsk_batt: +?L0088: +??bb0A_tsk_batt: + clr1 !_vreg_ctr+15.3 ;[INF] 4, 2 +??eb0A_tsk_batt: +??eb08_tsk_batt: +; line 664 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_DISC ); +$DGL 0,28 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#011H ; 17 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb07_tsk_batt: +; line 665 : } +?L0085: +??eb02_tsk_batt: +; line 666 : } +; line 667 : +; line 668 : +; line 669 : // 充電 /////////////////////////// +; line 670 : // 温度付きヒステリシス +; line 671 : if( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) +$DGL 0,35 + cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1 + sknc ;[INF] 2, 1 +; line 672 : { +??bb0B_tsk_batt: +; line 673 : charge_hys = 1; +$DGL 0,37 + oneb !?L0078 ; charge_hys ;[INF] 3, 1 +??eb0B_tsk_batt: +; line 674 : } +?L0090: +; line 675 : +; line 676 : if( ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) +; line 677 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) +$DGL 0,41 + cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1 + bc $?L0092 ;[INF] 2, 4 + cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1 + sknc ;[INF] 2, 1 +; line 678 : { +??bb0C_tsk_batt: +; line 679 : charge_hys = 0; +$DGL 0,43 + clrb !?L0078 ; charge_hys ;[INF] 3, 1 +??eb0C_tsk_batt: +; line 680 : } +?L0092: +; line 681 : +; line 682 : if( ( ( charge_hys == 1 ) +; line 683 : && ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) +; line 684 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) +; line 685 : || +$DGL 0,49 + cmp !?L0078,#01H ; charge_hys,1 ;[INF] 4, 1 + bnz $?L0097 ;[INF] 2, 4 + cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1 + bc $?L0097 ;[INF] 2, 4 + cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1 + bc $?L0096 ;[INF] 2, 4 +?L0097: +; line 686 : ( ( charge_hys == 0 ) +$DGL 0,50 + cmp0 !?L0078 ; charge_hys ;[INF] 3, 1 + bnz $?L0094 ;[INF] 2, 4 +; line 687 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) ) ) +$DGL 0,51 + cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1 + bnc $?L0094 ;[INF] 2, 4 +?L0096: +; line 688 : { +??bb0D_tsk_batt: +; line 689 : #ifndef _MODEL_WM0_ +; line 690 : BT_CHG_ENABLE(); // 温度範囲OKで充電再開 +$DGL 0,54 + clr1 P4.3 ;[INF] 3, 2 +??eb0D_tsk_batt: +; line 691 : } +$DGL 0,55 + br $?L0095 ;[INF] 2, 3 +?L0094: +; line 692 : else +; line 693 : { +??bb0E_tsk_batt: +; line 694 : BT_CHG_DISABLE(); // 温度危険！　充電停止 +$DGL 0,58 + set1 P4.3 ;[INF] 3, 2 +??eb0E_tsk_batt: +; line 695 : #endif +; line 696 : } +?L0095: +; line 697 : #ifdef _MODEL_WM0_ +; line 698 : // CHG_ENABLEピンは /WL_RST に配線されているので +; line 699 : #endif +; line 700 : +; line 701 : // 充電 // +; line 702 : // →割り込み。miscの中でよろしくやってくれている。 +; line 703 : set_bit( !BT_CHG_n, vreg_ctr[VREG_C_STATUS], REG_BIT_BATT_CH +; ARGE ); +$DGL 0,67 +??bb0F_tsk_batt: + bt P5.1,$?L0098 ;[INF] 4, 5 +??bb10_tsk_batt: + set1 !_vreg_ctr+15.4 ;[INF] 4, 2 +??eb10_tsk_batt: + br $?L0099 ;[INF] 2, 3 +?L0098: +??bb11_tsk_batt: + clr1 !_vreg_ctr+15.4 ;[INF] 4, 2 +??eb11_tsk_batt: +?L0099: +??eb0F_tsk_batt: +; line 704 : LED_CHARGE = !BT_CHG_n ? 1 : 0; +$DGL 0,68 + bt P5.1,$?L0100 ;[INF] 4, 5 + onew ax ;[INF] 1, 1 + br $?L0101 ;[INF] 2, 3 +?L0100: + clrw ax ;[INF] 1, 1 +?L0101: + mov a,x ;[INF] 1, 1 + rorc a,1 ;[INF] 2, 1 + mov1 P2.4,CY ;[INF] 3, 2 +; line 705 : +; line 706 : +; line 707 : // 電池残量 // +; line 708 : PM_get_batt_left(); +$DGL 0,72 + call !_PM_get_batt_left ;[INF] 3, 3 +; line 709 : +; line 710 : // dubug monitor +; line 711 : +; line 712 : return; +; line 713 : } +?L0076: +$DGL 0,77 +??ef_tsk_batt: + ret ;[INF] 1, 6 +??ee_tsk_batt: +; line 714 : +; line 715 : +; line 716 : +; line 717 : +; line 718 : /*========================================================= +; line 719 : extDC割り込み +; line 720 : 電源OFFから起こす（充電の温度監視のため）のみ +; line 721 : 普段はポーリング(pm) +; line 722 : =========================================================*/ +; line 723 : __interrupt void intp4_extdc( ) +; line 724 : { + +@@BASE CSEG BASE +_intp4_extdc: +$DGL 1,417 +??bf_intp4_extdc: +; line 725 : ; +; line 726 : } +$DGL 0,3 +??ef_intp4_extdc: + reti ;[INF] 2, 6 +??ee_intp4_extdc: +; line 727 : +; line 728 : +; line 729 : +; line 730 : /*========================================================= +; line 731 : フタ開け閉め割り込み +; line 732 : 普段はポーング(misc) +; line 733 : =========================================================*/ +; line 734 : __interrupt void intp5_shell( ) +; line 735 : { +_intp5_shell: +$DGL 1,423 +??bf_intp5_shell: +; line 736 : ; +; line 737 : } +$DGL 0,3 +??ef_intp5_shell: + reti ;[INF] 2, 6 +??ee_intp5_shell: +; line 738 : +; line 739 : +; line 740 : /*========================================================= +; line 741 : 旧PMICへのコマンド書き込み +; line 742 : =========================================================*/ +; line 743 : __interrupt void intp6_PM_irq( ) +; line 744 : { +_intp6_PM_irq: +$DGL 1,429 + push ax ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push de ;[INF] 1, 1 + push hl ;[INF] 1, 1 + mov c,#0CH ;[INF] 2, 1 + dec c ;[INF] 1, 1 + dec c ;[INF] 1, 1 + movw ax,_@SEGAX[c] ;[INF] 3, 1 + push ax ;[INF] 1, 1 + bnz $$-6 ;[INF] 2, 4 + mov a,ES ;[INF] 2, 1 + mov x,a ;[INF] 1, 1 + mov a,CS ;[INF] 2, 1 + push ax ;[INF] 1, 1 +??bf_intp6_PM_irq: +; line 745 : if( system_status.pwr_state == ON ) +$DGL 0,2 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bnz $?L0108 ;[INF] 2, 4 +; line 746 : { +??bb00_intp6_PM_irq: +; line 747 : EI(); +$DGL 0,4 + ei ;[INF] 3, 4 +; line 748 : renge_task_immed_add( ntr_pmic_comm ); +$DGL 0,5 + movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb00_intp6_PM_irq: +; line 749 : } +?L0108: +; line 750 : } +$DGL 0,7 +??ef_intp6_PM_irq: + pop ax ;[INF] 1, 1 + mov CS,a ;[INF] 2, 1 + mov a,x ;[INF] 1, 1 + mov ES,a ;[INF] 2, 1 + movw de,#_@SEGAX ;[INF] 3, 1 + mov c,#06H ;[INF] 2, 1 + pop ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw de ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $$-5 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 + pop de ;[INF] 1, 1 + pop bc ;[INF] 1, 1 + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_intp6_PM_irq: +; line 751 : +; line 752 : +; line 753 : +; line 754 : extern u8 temp_debug_3; +; line 755 : +; line 756 : /* ======================================================== +; line 757 : PMICからの割り込みを受けて、NTR PMIC互換レジスタからリード +; line 758 : ======================================================== */ +; line 759 : task_status_immed ntr_pmic_comm( ) +; line 760 : { + +ROM_CODE CSEG BASE +_ntr_pmic_comm: +$DGL 1,439 + push hl ;[INF] 1, 1 +??bf_ntr_pmic_comm: +; line 761 : static u8 reg_shadow; +; line 762 : u8 reg1_old; +; line 763 : u8 irq_work = 0; +$DGL 0,4 + mov h,#00H ; 0 ;[INF] 2, 1 +; line 764 : +; line 765 : reg1_old = reg_shadow; +$DGL 0,6 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + mov l,a ;[INF] 1, 1 +; line 766 : reg_shadow = iic_mcu_read_a_byte( IIC_SLA_CODEC, CODEC_REG_P +; M ); +$DGL 0,7 + movw ax,#010H ; 16 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#0A4H ; 164 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov !?L0112,a ; reg_shadow ;[INF] 3, 1 +; line 767 : if( iic_mcu_bus_status != ERR_SUCCESS ) +$DGL 0,8 + cmp0 !_iic_mcu_bus_status ;[INF] 3, 1 + bz $?L0113 ;[INF] 2, 4 +; line 768 : { +??bb00_ntr_pmic_comm: +; line 769 : return ( ERR_FINISED ); +$DGL 0,10 + clrw bc ;[INF] 1, 1 + br !?L0111 ;[INF] 3, 3 +??eb00_ntr_pmic_comm: +; line 770 : } +?L0113: +; line 771 : +; line 772 : DI( ); +$DGL 0,13 + di ;[INF] 3, 4 +; line 773 : +; line 774 : // バックライト 上 //////////////////////////////////// +; line 775 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_U ) != +; 0 ) +$DGL 0,16 + mov a,l ;[INF] 1, 1 + xor a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0118 ;[INF] 2, 4 +; line 776 : { +??bb01_ntr_pmic_comm: +; line 777 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_U ) == 0 ) +; // 消えた +$DGL 0,18 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0117 ;[INF] 2, 4 +; line 778 : { +??bb02_ntr_pmic_comm: +; line 779 : // irq_work = REG_BIT_TWL_BL_U_OFF; +; line 780 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_OFF ); +$DGL 0,21 + movw ax,#010H ; 16 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb02_ntr_pmic_comm: +; line 781 : } +$DGL 0,22 + br $?L0118 ;[INF] 2, 3 +?L0117: +; line 782 : else +; line 783 : { +??bb03_ntr_pmic_comm: +; line 784 : // irq_work = REG_BIT_TWL_BL_U_ON; +; line 785 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_ON ); +$DGL 0,26 + movw ax,#020H ; 32 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb03_ntr_pmic_comm: +; line 786 : } +?L0118: +??eb01_ntr_pmic_comm: +; line 787 : } +; line 788 : +; line 789 : // バックライト 下 +; line 790 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_L ) != +; 0 ) +$DGL 0,31 + mov a,l ;[INF] 1, 1 + xor a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0122 ;[INF] 2, 4 +; line 791 : { +??bb04_ntr_pmic_comm: +; line 792 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_L ) == 0 ) +; // 消えた +$DGL 0,33 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0121 ;[INF] 2, 4 +; line 793 : { +??bb05_ntr_pmic_comm: +; line 794 : // irq_work = REG_BIT_TWL_BL_L_OFF; +; line 795 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_OFF ); +$DGL 0,36 + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb05_ntr_pmic_comm: +; line 796 : } +$DGL 0,37 + br $?L0122 ;[INF] 2, 3 +?L0121: +; line 797 : else +; line 798 : { +??bb06_ntr_pmic_comm: +; line 799 : // irq_work = REG_BIT_TWL_BL_L_ON; +; line 800 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_ON ); +$DGL 0,41 + movw ax,#08H ; 8 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb06_ntr_pmic_comm: +; line 801 : } +?L0122: +??eb04_ntr_pmic_comm: +; line 802 : } +; line 803 : +; line 804 : #if 0 +; line 805 : irq_work &= ~VREG_C_IRQ_MASK2; +; line 806 : // set_irq 相当品 +; line 807 : if( irq_work != 0 ) +; line 808 : { +; line 809 : u8 tot; +; line 810 : +; line 811 : DI(); +; line 812 : vreg_ctr[ VREG_C_IRQ2 ] |= irq_work; +; line 813 : EI(); +; line 814 : IRQ0_neg; // 一瞬上げてパルスを送り直す +; line 815 : tot = 0; +; line 816 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.Dなのでちゃんと +; あがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) +; line 817 : IRQ0_ast; +; line 818 : } +; line 819 : #endif +; line 820 : +; line 821 : #if 0 +; line 822 : // バックライト設定 +; line 823 : // 勝手に消しておく +; line 824 : /// 今のところさらに細かくは分けないけど… +; line 825 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_BL_U | REG_BIT_TWL_REQ_ +; BL_U ) ) == 0 ) +; line 826 : { +; line 827 : vreg_ctr[ VREG_C_COMMAND2 ] = ( REG_BIT_CMD_BL_U_OFF | R +; EG_BIT_CMD_BL_U_OFF ); +; line 828 : renge_task_immed_add( tski_PM_BL_set ); +; line 829 : } +; line 830 : #endif +; line 831 : +; line 832 : // offリクエスト ////////////////////////////////////// +; line 833 : if( ( reg_shadow & REG_BIT_TWL_REQ_OFF_REQ ) != 0 ) +$DGL 0,74 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#040H ; 64 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0123 ;[INF] 2, 4 +; line 834 : { +??bb07_ntr_pmic_comm: +; line 835 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); +$DGL 0,76 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb07_ntr_pmic_comm: +; line 836 : } +?L0123: +; line 837 : +; line 838 : // リセットリクエスト ///////////////////////////////// +; line 839 : if( ( reg_shadow & REG_BIT_TWL_REQ_RST_REQ ) != 0 ) +$DGL 0,80 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0125 ;[INF] 2, 4 +; line 840 : { +??bb08_ntr_pmic_comm: +; line 841 : // CODECバグ回避 +; line 842 : // リセット単品でなかったら無視 +; line 843 : // codec 修正済↓ +; line 844 : // if( ( reg1_old ^ reg_shadow ) == REG_BIT_TWL_REQ_RST_R +; EQ ) +; line 845 : { +??bb09_ntr_pmic_comm: +; line 846 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); +$DGL 0,87 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb09_ntr_pmic_comm: +; line 847 : } +??eb08_ntr_pmic_comm: +; line 848 : } +?L0125: +; line 849 : +; line 850 : // バックライトをマスクして書き戻す +; line 851 : EI( ); +$DGL 0,92 + ei ;[INF] 3, 4 +; line 852 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R +; EQ_RST_REQ )) != 0 ) +$DGL 0,93 + mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + and a,#041H ; 65 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0127 ;[INF] 2, 4 +; line 853 : { +??bb0A_ntr_pmic_comm: +; line 854 : reg_shadow &= ~( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R +; EQ_RST_REQ ); +$DGL 0,95 + movw de,#loww (?L0112) ; reg_shadow ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + and a,#0BEH ; 190 ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 855 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_PM, reg_s +; hadow ); +$DGL 0,96 + mov x,!?L0112 ; reg_shadow ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#010H ; 16 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#0A4H ; 164 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +??eb0A_ntr_pmic_comm: +; line 856 : } +?L0127: +; line 857 : return ( ERR_FINISED ); +$DGL 0,98 + clrw bc ;[INF] 1, 1 +; line 858 : } +?L0111: +$DGL 0,99 +??ef_ntr_pmic_comm: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_ntr_pmic_comm: +; line 859 : +; line 860 : +; line 861 : +; line 862 : /********************************************************** +; line 863 : 電池残量ICから残量を取得し、レジスタに書き込む。 +; line 864 : 　電池残量ICが無い・故障などの時はとりあえず残量99%とする。 +; line 865 : 　　　　　　　　↑は status_1で確認可能。電源投入時にチェックし +; ています。 +; line 866 : 　PM_init()が実行されている必要があります。 +; line 867 : **********************************************************/ +; line 868 : static void PM_get_batt_left(){ +_PM_get_batt_left: +$DGL 1,492 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_PM_get_batt_left: +; line 869 : if(( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_GASGAUGE_ERR ) == +; 0 ) +$DGL 0,2 + mov a,!_vreg_ctr+14 ;[INF] 3, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0131 ;[INF] 2, 4 +; line 870 : { +??bb00_PM_get_batt_left: +; line 871 : // 電池残量の取得 +; line 872 : { +??bb01_PM_get_batt_left: +; line 873 : u8 temp[2]; +; line 874 : +; line 875 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC, 2, +; temp ); +$DGL 0,8 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#06CH ; 108 ;[INF] 2, 1 + call !_iic_mcu_read ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +; line 876 : +; line 877 : vreg_ctr[ VREG_C_BT_REMAIN ] = temp[0]; +$DGL 0,10 + mov a,[hl] ; temp ;[INF] 1, 1 + mov !_vreg_ctr+11,a ;[INF] 3, 1 +; line 878 : vreg_ctr[ VREG_C_BT_REMAIN_FINE ] = temp[1]; +$DGL 0,11 + mov a,[hl+1] ; temp ;[INF] 2, 1 + mov !_vreg_ctr+12,a ;[INF] 3, 1 +??eb01_PM_get_batt_left: +; line 879 : // todo 閾値を超えたら割り込み +; line 880 : } +; line 881 : +; line 882 : vreg_ctr[ VREG_C_BT_VOLTAGE ] = iic_mcu_read_a_byte( IIC +; _SLA_BT_GAUGE, BT_GAUGE_REG_VCELL ); +$DGL 0,15 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + call !bs_F0151 ;[INF] 3, 3 + mov !_vreg_ctr+13,a ;[INF] 3, 1 +??eb00_PM_get_batt_left: +; line 883 : } +$DGL 0,16 + br $?L0132 ;[INF] 2, 3 +?L0131: +; line 884 : else +; line 885 : { +??bb02_PM_get_batt_left: +; line 886 : vreg_ctr[ VREG_C_BT_REMAIN ] = 99; +$DGL 0,19 + mov !_vreg_ctr+11,#063H ; 99 ;[INF] 4, 1 +??eb02_PM_get_batt_left: +; line 887 : } +?L0132: +; line 888 : +; line 889 : // PMIC-NTRに電池残量を教えてあげる +; line 890 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_BT, +; line 891 : ( vreg_ctr[ VREG_C_BT_REMAIN ] < 5 )? +; 1 : 0 ); // 1で電池切れ +$DGL 0,24 + cmp !_vreg_ctr+11,#05H ; 5 ;[INF] 4, 1 + bnc $?L0133 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0134 ;[INF] 2, 3 +?L0133: + clrw ax ;[INF] 1, 1 +?L0134: + clrb a ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#0A4H ; 164 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 892 : +; line 893 : } +$DGL 0,26 +??ef_PM_get_batt_left: + pop ax ;[INF] 1, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_PM_get_batt_left: +; line 894 : +; line 895 : +; line 896 : +; line 897 : +; line 898 : +; line 899 : /********************************************************** +; line 900 : command2 液晶系 +; line 901 : 　 ラッパー的な物。ERR_SUCCESSしか返さないが… +; line 902 : **********************************************************/ +; line 903 : task_status_immed tski_PM_LCD_on() +; line 904 : { +_tski_PM_LCD_on: +$DGL 1,512 +??bf_tski_PM_LCD_on: +; line 905 : PM_LCD_on(); +$DGL 0,2 + call !_PM_LCD_on ;[INF] 3, 3 +; line 906 : return( ERR_SUCCESS ); +$DGL 0,3 + clrw bc ;[INF] 1, 1 +; line 907 : } +$DGL 0,4 +??ef_tski_PM_LCD_on: + ret ;[INF] 1, 6 +??ee_tski_PM_LCD_on: +; line 908 : +; line 909 : task_status_immed tski_PM_LCD_off() +; line 910 : { +_tski_PM_LCD_off: +$DGL 1,518 +??bf_tski_PM_LCD_off: +; line 911 : PM_LCD_off(); +$DGL 0,2 + call !_PM_LCD_off ;[INF] 3, 3 +; line 912 : return( ERR_SUCCESS ); +$DGL 0,3 + clrw bc ;[INF] 1, 1 +; line 913 : } +$DGL 0,4 +??ef_tski_PM_LCD_off: + ret ;[INF] 1, 6 +??ee_tski_PM_LCD_off: +; line 914 : +; line 915 : task_status_immed tski_PM_BL_set() +; line 916 : { +_tski_PM_BL_set: +$DGL 1,524 + push hl ;[INF] 1, 1 +??bf_tski_PM_BL_set: +; line 917 : u8 cmd_BL; // ↓volatileとか付けなくても大丈 +; 夫みたい +; line 918 : +; line 919 : do +?L0141: +; line 920 : { +??bb00_tski_PM_BL_set: +; line 921 : cmd_BL = vreg_ctr[VREG_C_COMMAND2]; +$DGL 0,6 + mov a,!_vreg_ctr+34 ;[INF] 3, 1 + mov l,a ;[INF] 1, 1 +; line 922 : PM_BL_set( cmd_BL ); // マスク済み +$DGL 0,7 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + call !_PM_BL_set ;[INF] 3, 3 +??eb00_tski_PM_BL_set: +; line 923 : } +; line 924 : while( cmd_BL != vreg_ctr[VREG_C_COMMAND2] ); +$DGL 0,9 + mov a,l ;[INF] 1, 1 + cmp a,!_vreg_ctr+34 ;[INF] 3, 1 + bnz $?L0141 ;[INF] 2, 4 +; line 925 : vreg_ctr[VREG_C_COMMAND2] = 0; +$DGL 0,10 + clrb !_vreg_ctr+34 ;[INF] 3, 1 +; line 926 : +; line 927 : return( ERR_SUCCESS ); +$DGL 0,12 + clrw bc ;[INF] 1, 1 +; line 928 : } +$DGL 0,13 +??ef_tski_PM_BL_set: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tski_PM_BL_set: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c +; +; $FUNC PM_init(46) +; void=(void) +; CODE SIZE= 335 bytes, CLOCK_SIZE= 294 clocks, STACK_SIZE= 20 bytes +; +; $CALL wait_ms(58) +; void=(int:ax) +; +; $CALL iic_mcu_write(62) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_write(66) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_write(75) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_read(78) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_write(82) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_write(86) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL get_adc(90) +; bc=(int:ax) +; +; $CALL iic_mcu_write(104) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL wait_ms(112) +; void=(int:ax) +; +; $CALL iic_mcu_write(116) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL wait_ms(119) +; void=(int:ax) +; +; $CALL iic_mcu_read_a_byte(122) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write(131) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_write(135) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL get_adc(142) +; bc=(int:ax) +; +; $CALL renge_task_immed_add(143) +; bc=(pointer:ax) +; +; $FUNC PM_bt_temp_update(163) +; bc=(void) +; CODE SIZE= 217 bytes, CLOCK_SIZE= 196 clocks, STACK_SIZE= 14 bytes +; +; $CALL iic_mcu_write(201) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $FUNC PM_LCD_on(227) +; bc=(void) +; CODE SIZE= 59 bytes, CLOCK_SIZE= 114 clocks, STACK_SIZE= 14 bytes +; +; $CALL iic_mcu_write_a_byte(230) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(232) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(234) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(236) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(238) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(240) +; void=(int:ax) +; +; $CALL iic_mcu_read_a_byte(245) +; bc=(int:ax, int:[sp+4]) +; +; $CALL set_irq(251) +; void=(int:ax, int:[sp+4]) +; +; $FUNC PM_LCD_off(265) +; void=(void) +; CODE SIZE= 96 bytes, CLOCK_SIZE= 139 clocks, STACK_SIZE= 14 bytes +; +; $CALL iic_mcu_read_a_byte(272) +; bc=(int:ax, int:[sp+4]) +; +; $CALL PM_BL_set(277) +; bc=(int:ax) +; +; $CALL iic_mcu_write_a_byte(296) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(297) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(299) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL set_irq(303) +; void=(int:ax, int:[sp+4]) +; +; $FUNC PM_BL_set(314) +; bc=(unsigned char dat:x) +; CODE SIZE= 202 bytes, CLOCK_SIZE= 176 clocks, STACK_SIZE= 18 bytes +; +; $CALL iic_mcu_read_a_byte(323) +; bc=(int:ax, int:[sp+4]) +; +; $CALL wait_ms(381) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(383) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC PM_LCD_vcom_set(395) +; bc=(void) +; CODE SIZE= 37 bytes, CLOCK_SIZE= 41 clocks, STACK_SIZE= 10 bytes +; +; $CALL iic_mcu_write_a_byte(398) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL iic_mcu_write_a_byte(399) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC tski_vcom_set(450) +; bc=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes +; +; $CALL PM_LCD_vcom_set(451) +; bc=(void) +; +; $FUNC PM_sys_pow_on(466) +; bc=(void) +; CODE SIZE= 115 bytes, CLOCK_SIZE= 182 clocks, STACK_SIZE= 14 bytes +; +; $CALL get_adc(475) +; bc=(int:ax) +; +; $CALL PM_bt_temp_update(477) +; bc=(void) +; +; $CALL PM_get_batt_left(480) +; void=(void) +; +; $CALL iic_mcu_write_a_byte(492) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(494) +; void=(int:ax) +; +; $CALL wait_ms(499) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(501) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(502) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(504) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(506) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(508) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL iic_mcu_read_a_byte(512) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write_a_byte(517) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC PM_sys_pow_off(583) +; bc=(void) +; CODE SIZE= 28 bytes, CLOCK_SIZE= 62 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_write_a_byte(588) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL iic_mcu_write_a_byte(592) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL iic_mcu_write_a_byte(594) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC tsk_batt(637) +; void=(void) +; CODE SIZE= 168 bytes, CLOCK_SIZE= 133 clocks, STACK_SIZE= 6 bytes +; +; $CALL set_irq(659) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(664) +; void=(int:ax, int:[sp+4]) +; +; $CALL PM_get_batt_left(708) +; void=(void) +; +; $FUNC intp4_extdc(724) +; void=(void) +; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes +; +; $FUNC intp5_shell(735) +; void=(void) +; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes +; +; $FUNC intp6_PM_irq(744) +; void=(void) +; CODE SIZE= 59 bytes, CLOCK_SIZE= 55 clocks, STACK_SIZE= 26 bytes +; +; $CALL renge_task_immed_add(748) +; bc=(pointer:ax) +; +; $FUNC ntr_pmic_comm(760) +; bc=(void) +; CODE SIZE= 180 bytes, CLOCK_SIZE= 152 clocks, STACK_SIZE= 10 bytes +; +; $CALL iic_mcu_read_a_byte(766) +; bc=(int:ax, int:[sp+4]) +; +; $CALL set_irq(780) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(785) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(795) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(800) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(835) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(846) +; void=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write_a_byte(855) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC PM_get_batt_left(868) +; void=(void) +; CODE SIZE= 76 bytes, CLOCK_SIZE= 77 clocks, STACK_SIZE= 14 bytes +; +; $CALL iic_mcu_read(875) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) +; +; $CALL iic_mcu_read_a_byte(882) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write_a_byte(891) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC tski_PM_LCD_on(904) +; bc=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes +; +; $CALL PM_LCD_on(905) +; bc=(void) +; +; $FUNC tski_PM_LCD_off(910) +; bc=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes +; +; $CALL PM_LCD_off(911) +; void=(void) +; +; $FUNC tski_PM_BL_set(916) +; bc=(void) +; CODE SIZE= 22 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 6 bytes +; +; $CALL PM_BL_set(922) +; bc=(int:ax) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/reboot.asm b/branches/0.10(X3)/inter_asm/reboot.asm new file mode 100644 index 0000000..afdecc1 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/reboot.asm @@ -0,0 +1,134 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no reboot.c +; In-file : reboot.c +; Asm-file : inter_asm\reboot.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, reboot.c +$DGS MOD_NAM, reboot, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS GLV_SYM, _my_reboot, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H +$DGS BEG_FUN, ??bf_my_reboot, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 019H +$DGS END_FUN, ??ef_my_reboot, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0BH + + PUBLIC _my_reboot + +@@BITS BSEG + +@@CNST CSEG MIRRORP + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +LDR_CNSL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : /********************************************************//* +; line 2 : +; line 3 : むりやりリブート +; line 4 : +; line 5 : ファイル中にインラインアセンブラがあると、 +; line 6 : そのモジュール全部最適化が聞かなくなるため追い出した +; line 7 : +; line 8 : **********************************************************/ +; line 9 : #pragma SFR +; line 10 : +; line 11 : #include "incs_loader.h" +; line 12 : +; line 13 : +; line 14 : void my_reboot(){ + +LDR_CODE CSEG BASE +_my_reboot: +$DGL 1,19 +??bf_my_reboot: +; line 15 : #asm + +$DGL 0,4 + MOV PSW,#06H ; ダミーのPSWをセット +$DGL 0,5 + MOVW AX,#000d0h ; リセットのベクタ値を取り込んでいます。 +$DGL 0,6 + PUSH PSW +$DGL 0,7 + PUSH AX ; これでRETIのためのスタックを準備 +$DGL 0,8 + RETI ; これでリセット・ベクタに分岐 + +; line 16 : +; line 17 : MOV PSW,#06H ; ダミーのPSWをセット +; line 18 : MOVW AX,#000d0h ; リセットのベクタ値を取り +; 込んでいます。 +; line 19 : PUSH PSW +; line 20 : PUSH AX ; これでRETIのためのスタック +; を準備 +; line 21 : RETI ; これでリセット・ベクタに分 +; 岐 +; line 22 : +; line 23 : #endasm +; line 24 : } +$DGL 0,11 +??ef_my_reboot: + ret ;[INF] 1, 6 +??ee_my_reboot: + +LDR_CODL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c +; +; $FUNC my_reboot(14) +; void=(void) +; CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/renge.asm b/branches/0.10(X3)/inter_asm/renge.asm new file mode 100644 index 0000000..b37b0a0 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/renge.asm @@ -0,0 +1,1365 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no renge\renge.c +; In-file : renge\renge.c +; Asm-file : inter_asm\renge.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0EEH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, renge.c +$DGS MOD_NAM, renge, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, .1fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 019H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS LAB_SYM, bs_S0096, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0096, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0094, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0094, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0095, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0095, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _tasks, U, U, 01H, 03H, 01H, 027H +$DGS AUX_STR, 00H, 00H, 016H, 0BH, 00H, 00H, 00H, 04H +$DGS GLV_SYM, _renge_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 027H, 00H, 00H +$DGS BEG_FUN, ??bf_renge_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 035H, 00H, 027H +$DGS END_FUN, ??ef_renge_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09H +$DGS GLV_SYM, _renge_task_interval_run, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 036H, 00H, 00H +$DGS BEG_FUN, ??bf_renge_task_interval_run, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 051H, 02H, 02CH +$DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 02EH +$DGS BEG_BLK, ??bb01_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 00H +$DGS END_BLK, ??eb01_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS END_BLK, ??eb00_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS END_FUN, ??ef_renge_task_interval_run, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 012H +$DGS STA_SYM, _renge_task_immed_init, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 041H, 00H, 00H +$DGS BEG_FUN, ??bf_renge_task_immed_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 075H, 02H, 03BH +$DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_renge_task_immed_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 00H +$DGS END_BLK, ??eb00_renge_task_immed_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06H +$DGS END_FUN, ??ef_renge_task_immed_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 07H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 062H, 00H, 00H +$DGS BEG_FUN, ??bf_renge_task_immed_add, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 083H, 04H, 048H +$DGS FUN_ARG, _new_task, 02H, 0FFFFH, 01H, 09H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS AUT_VAR, _i, 01H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 04AH +$DGS BEG_BLK, ??bb01_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 04CH +$DGS BEG_BLK, ??bb02_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 052H +$DGS END_BLK, ??eb02_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS END_BLK, ??eb01_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS BEG_BLK, ??bb03_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 054H +$DGS BEG_BLK, ??bb04_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 019H, 00H, 056H +$DGS BEG_BLK, ??bb05_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 00H +$DGS END_BLK, ??eb05_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01EH +$DGS END_BLK, ??eb04_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS END_BLK, ??eb03_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 022H +$DGS END_BLK, ??eb00_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS END_FUN, ??ef_renge_task_immed_add, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 027H +$DGS GLV_SYM, _renge_task_immed_run, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0DEH, 00H, 00H +$DGS BEG_FUN, ??bf_renge_task_immed_run, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0B0H, 04H, 068H +$DGS AUT_VAR, _list_id, 03H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _last_task_id, 02H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 06AH +$DGS BEG_BLK, ??bb01_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 06CH +$DGS BEG_BLK, ??bb02_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 06EH +$DGS BEG_BLK, ??bb03_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 072H +$DGS END_BLK, ??eb03_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb04_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 074H +$DGS BEG_BLK, ??bb05_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 07CH +$DGS END_BLK, ??eb05_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS END_BLK, ??eb04_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01AH +$DGS END_BLK, ??eb02_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS BEG_BLK, ??bb06_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01EH, 00H, 07EH +$DGS BEG_BLK, ??bb07_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 021H, 00H, 080H +$DGS BEG_BLK, ??bb08_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 023H, 00H, 08AH +$DGS END_BLK, ??eb08_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 025H +$DGS END_BLK, ??eb07_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS END_BLK, ??eb06_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 028H +$DGS END_BLK, ??eb01_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS BEG_BLK, ??bb09_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02DH, 00H, 08CH +$DGS BEG_BLK, ??bb0A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02FH, 00H, 092H +$DGS AUT_VAR, _i, 01H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 030H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS AUT_VAR, _j, 00H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 030H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb0B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 096H +$DGS END_BLK, ??eb0B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 035H +$DGS BEG_BLK, ??bb0C_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03CH, 00H, 098H +$DGS BEG_BLK, ??bb0D_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03FH, 00H, 09AH +$DGS BEG_BLK, ??bb0E_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 041H, 00H, 09CH +$DGS BEG_BLK, ??bb0F_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 044H, 00H, 0A0H +$DGS END_BLK, ??eb0F_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 046H +$DGS BEG_BLK, ??bb10_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04BH, 00H, 0A2H +$DGS BEG_BLK, ??bb11_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04DH, 00H, 0AAH +$DGS END_BLK, ??eb11_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04FH +$DGS END_BLK, ??eb10_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 050H +$DGS END_BLK, ??eb0E_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 054H +$DGS BEG_BLK, ??bb12_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 056H, 00H, 0B0H +$DGS END_BLK, ??eb12_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05BH +$DGS END_BLK, ??eb0D_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05CH +$DGS BEG_BLK, ??bb13_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05EH, 00H, 0B2H +$DGS BEG_BLK, ??bb14_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 062H, 00H, 0B8H +$DGS END_BLK, ??eb14_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 065H +$DGS END_BLK, ??eb13_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 068H +$DGS BEG_BLK, ??bb15_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06BH, 00H, 0BEH +$DGS END_BLK, ??eb15_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 071H +$DGS END_BLK, ??eb0C_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 072H +$DGS BEG_BLK, ??bb16_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 077H, 00H, 0C0H +$DGS BEG_BLK, ??bb17_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 079H, 00H, 0C2H +$DGS BEG_BLK, ??bb18_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 0C4H +$DGS BEG_BLK, ??bb19_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0CCH +$DGS END_BLK, ??eb19_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS END_BLK, ??eb18_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 083H +$DGS END_BLK, ??eb17_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 087H +$DGS BEG_BLK, ??bb1A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 089H, 00H, 0D8H +$DGS END_BLK, ??eb1A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08BH +$DGS END_BLK, ??eb16_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08CH +$DGS END_BLK, ??eb0A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08EH +$DGS END_BLK, ??eb09_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08FH +$DGS END_BLK, ??eb00_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 090H +$DGS BEG_BLK, ??bb1B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 098H, 00H, 00H +$DGS END_BLK, ??eb1B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 09BH +$DGS END_FUN, ??ef_renge_task_immed_run, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09EH +$DGS GLV_SYM, _wait_ms, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0EEH, 00H, 00H +$DGS BEG_FUN, ??bf_wait_ms, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0157H, 04H, 0E4H +$DGS FUN_ARG, _ms, 02H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS AUT_VAR, _fine, 00H, 0FFFFH, 0DH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_wait_ms, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0E6H +$DGS BEG_BLK, ??bb01_wait_ms, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 00H +$DGS END_BLK, ??eb01_wait_ms, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS END_BLK, ??eb00_wait_ms, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS END_FUN, ??ef_wait_ms, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 011H +$DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _renge_task_immediate_not_empty, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _system_time, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _tasks_immed, U, U, 0AH, 026H, 01H, 027H +$DGS AUX_STR, 013H, 00H, 010H, 08H, 00H, 00H, 00H, 04H +$DGS GLV_SYM, _tsk_sw, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_adc, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_batt, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_debug, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_debug2, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_sys, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _tsk_sw + EXTRN _tsk_adc + EXTRN _tsk_batt + EXTRN _tsk_led_pow + EXTRN _tsk_led_wifi + EXTRN _tsk_led_notify + EXTRN _tsk_led_cam + EXTRN _tsk_misc_stat + EXTRN _tsk_debug + EXTRN _tsk_debug2 + EXTRN _tsk_sys + EXTRN _WDT_Restart + PUBLIC _renge_flg_interval + PUBLIC _renge_task_interval_run_force + PUBLIC _renge_task_immediate_not_empty + PUBLIC _system_time + PUBLIC _tasks_immed + PUBLIC _renge_init + PUBLIC _renge_task_interval_run + PUBLIC _renge_task_immed_add + PUBLIC _renge_task_immed_run + PUBLIC _wait_ms + +@@BITS BSEG +_renge_flg_interval DBIT +_renge_task_interval_run_force DBIT +_renge_task_immediate_not_empty DBIT + +@@CNST CSEG MIRRORP + +@@R_INIT CSEG UNIT64KP + DW loww (_tsk_sw) + DW loww (_tsk_adc) + DW loww (_tsk_batt) + DW loww (_tsk_led_pow) + DW loww (_tsk_led_wifi) + DW loww (_tsk_led_notify) + DW loww (_tsk_led_cam) + DW loww (_tsk_misc_stat) + DW loww (_tsk_debug) + DW loww (_tsk_debug2) + DW loww (_tsk_sys) + +@@INIT DSEG BASEP +_tasks: DS (22) + +@@DATA DSEG BASEP +_system_time: DS (1) + DS (1) +_tasks_immed: DS (16) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_S0096: + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + onew ax ;[INF] 1, 1 + movw _tasks_immed[bc],ax ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0096: + +ROM_CODE CSEG BASE +bs_S0094: + mov a,[hl+1] ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0094: + +ROM_CODE CSEG BASE +bs_S0095: + mov a,[hl+3] ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_S0095: + +; *** Sub-Routine Information *** +; +; $SUB bs_S0094 +; CODE SIZE= 13 bytes +; +; $SUB bs_S0095 +; CODE SIZE= 13 bytes +; +; $SUB bs_S0096 +; CODE SIZE= 9 bytes + +; End of Sub-Routines + +; line 1 : #pragma section @@CODE ROM_CODE +; line 2 : #pragma nop +; line 3 : #pragma ei +; line 4 : #pragma di +; line 5 : #pragma sfr +; line 6 : +; line 7 : /*************************************************************** +; *************** +; line 8 : タスクシステム？ +; line 9 : なるほど、iTRONにはコンフィギュレータがあるはずだ。 +; line 10 : →作りました +; line 11 : ctr_mcu_config.rb 参照。 task_config.hが作成されます。 +; line 12 : *************************************************************** +; **************/ +; line 13 : #include "renge.h" +; line 14 : #include "renge_task_intval.h" +; line 15 : #include "renge_task_immediate.h" +; line 16 : #include "..\WDT.h" +; line 17 : #include "..\config.h" +; line 18 : #include "..\user_define.h" +; line 19 : +; line 20 : +; line 21 : #define _renge_test_ +; line 22 : +; line 23 : //************************************************************** +; **************** +; line 24 : bit renge_flg_interval; +; line 25 : bit renge_task_interval_run_force; +; line 26 : bit renge_task_immediate_not_empty; +; line 27 : +; line 28 : u8 system_time; +; line 29 : +; line 30 : +; line 31 : +; line 32 : #include "..\bsr_system.h" +; line 33 : extern system_status_ system_status; +; line 34 : +; line 35 : +; line 36 : +; line 37 : //************************************************************** +; **************** +; line 38 : static void renge_task_immed_init(); +; line 39 : static void renge_task_immed_del(); +; line 40 : +; line 41 : +; line 42 : +; line 43 : //************************************************************** +; **************** +; line 44 : task_status_immed ( *tasks_immed[ TASK_IMMED_RUN_LIST_MAX ] )(); +; line 45 : +; line 46 : +; line 47 : +; line 48 : /*************************************************************** +; *************** +; line 49 : 初期化 +; line 50 : ・タスクシステムの動的部分の初期化 +; line 51 : ・インターバルタイマ +; line 52 : *************************************************************** +; **************/ +; line 53 : void renge_init(){ + +ROM_CODE CSEG BASE +_renge_init: +$DGL 1,33 +??bf_renge_init: +; line 54 : renge_task_immed_init(); +$DGL 0,2 + br !_renge_task_immed_init ;[INF] 3, 3 +??ef_renge_init: +??ee_renge_init: +; line 55 : /* +; line 56 : イベントタイマのセットなど +; line 57 : 今回はRTCを流用しているのでコメントアウト +; line 58 : #define renge_tick 19xxxxxxx [ms] +; line 59 : renge_interval_init(); → RTC_init(); +; line 60 : */ +; line 61 : } +; line 62 : +; line 63 : +; line 64 : +; line 65 : /*************************************************************** +; *************** +; line 66 : システムチックを進める +; line 67 : *************************************************************** +; **************/ +; line 68 : /* +; line 69 : void renge_interval(){ +; line 70 : // RTCがやってくれる +; line 71 : →__interrupt void int_rtc_int(); +; line 72 : } +; line 73 : */ +; line 74 : +; line 75 : +; line 76 : +; line 77 : /*************************************************************** +; *************** +; line 78 : コンパイル時に決まっている、インターバル起動のタスク +; line 79 : そのうち、逐次起動と混ぜるかもしれない。 +; line 80 : *************************************************************** +; **************/ +; line 81 : err renge_task_interval_run(){ +_renge_task_interval_run: +$DGL 1,39 + push hl ;[INF] 1, 1 +??bf_renge_task_interval_run: +; line 82 : u8 i; +; line 83 : +; line 84 : // インターバル起動 +; line 85 : if(( renge_flg_interval == 1 ) +; line 86 : || ( renge_task_interval_run_force != 0 )) // todo 統合 +$DGL 0,6 + bt _renge_flg_interval,$?L0007 ;[INF] 4, 5 + bf _renge_task_interval_run_force,$?L0009 ;[INF] 4, 5 +?L0007: +; line 87 : { +??bb00_renge_task_interval_run: +; line 88 : renge_task_interval_run_force = 0; +$DGL 0,8 + clr1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 89 : renge_flg_interval = 0; +$DGL 0,9 + clr1 _renge_flg_interval ;[INF] 3, 2 +; line 90 : for( i = 0; i != TSK_LAST; i += 1 ) +$DGL 0,10 + mov l,#00H ; 0 ;[INF] 2, 1 +?L0008: + mov a,l ;[INF] 1, 1 + cmp a,#0BH ; 11 ;[INF] 2, 1 + bz $?L0009 ;[INF] 2, 4 +; line 91 : { +??bb01_renge_task_interval_run: +; line 92 : tasks[ i ](); +$DGL 0,12 + mov c,a ;[INF] 1, 1 + clrb b ;[INF] 1, 1 + shlw bc,1 ;[INF] 2, 1 + movw ax,_tasks[bc] ;[INF] 3, 1 + mov CS,#00H ; 0 ;[INF] 3, 1 + call ax ;[INF] 2, 3 +; line 93 : // 逐次起動タスクがあったら起動しておく +; line 94 : renge_task_immed_run(); +$DGL 0,14 + call !_renge_task_immed_run ;[INF] 3, 3 +??eb01_renge_task_interval_run: +; line 95 : } +$DGL 0,15 + inc l ;[INF] 1, 1 + br $?L0008 ;[INF] 2, 3 +?L0009: +??eb00_renge_task_interval_run: +; line 96 : } +; line 97 : return( ERR_SUCCESS ); +$DGL 0,17 + clrw bc ;[INF] 1, 1 +; line 98 : } +$DGL 0,18 +??ef_renge_task_interval_run: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_renge_task_interval_run: +; line 99 : +; line 100 : +; line 101 : +; line 102 : /*************************************************************** +; ************** +; line 103 : ■逐一起動タスク■ +; line 104 : +; line 105 : ●task_immed を返す関数。 +; line 106 : ●システムtick、何らかの割り込み（I2C通信完了など）で +; line 107 : スリープから復帰したタイミングで実行されます。 +; line 108 : +; line 109 : ■返値　ERR_FINISED　タスクを削除 +; line 110 : 　　　　それ以外 次のタイミングでまた実行 +; line 111 : +; line 112 : *************************************************************** +; **************/ +; line 113 : +; line 114 : +; line 115 : /************************************** +; line 116 : **************************************/ +; line 117 : void renge_task_immed_init(){ +_renge_task_immed_init: +$DGL 1,54 + push hl ;[INF] 1, 1 +??bf_renge_task_immed_init: +; line 118 : u8 i; +; line 119 : +; line 120 : for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i++ ){ +$DGL 0,4 + mov l,#00H ; 0 ;[INF] 2, 1 +?L0013: + mov a,l ;[INF] 1, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0014 ;[INF] 2, 4 +??bb00_renge_task_immed_init: +; line 121 : tasks_immed[ i ] = TSK_IMM_EMPTY_; +$DGL 0,5 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + movw _tasks_immed[bc],ax ;[INF] 3, 1 +??eb00_renge_task_immed_init: +; line 122 : } +$DGL 0,6 + inc l ;[INF] 1, 1 + br $?L0013 ;[INF] 2, 3 +?L0014: +; line 123 : } +$DGL 0,7 +??ef_renge_task_immed_init: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_renge_task_immed_init: +; line 124 : +; line 125 : +; line 126 : +; line 127 : /************************************** +; line 128 : 逐次実行タスクの登録 +; line 129 : 割り込み禁止 36us → +; line 130 : **************************************/ +; line 131 : err renge_task_immed_add( task_status* new_task ){ +_renge_task_immed_add: +$DGL 1,65 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_renge_task_immed_add: +; line 132 : u8 i; +; line 133 : +; line 134 : // リストの空きの先頭に登録 +; line 135 : // 削除したばかりのタスクは、削除マーク(TSK_IMM_DELETED_)とな +; り、空きとは明示的に区別される +; line 136 : // 重複登録を避ける +; line 137 : for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) +$DGL 0,7 + mov [hl+1],#00H ; i,0 ;[INF] 3, 1 +?L0018: + mov a,[hl+1] ; i ;[INF] 2, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0019 ;[INF] 2, 4 +; line 138 : { +??bb00_renge_task_immed_add: +; line 139 : if( tasks_immed[ i ] != TSK_IMM_EMPTY_ ) +$DGL 0,9 + call !bs_S0094 ;[INF] 3, 3 + bz $?L0021 ;[INF] 2, 4 +; line 140 : { +??bb01_renge_task_immed_add: +; line 141 : // 重複登録チェック +; line 142 : if( tasks_immed[ i ] == new_task ) +$DGL 0,12 + movw ax,[de] ;[INF] 1, 1 + cmpw ax,[hl+2] ; new_task ;[INF] 3, 1 + bnz $?L0022 ;[INF] 2, 4 +; line 143 : { +??bb02_renge_task_immed_add: +; line 144 : // 重複登録はしない +; line 145 : NOP(); +$DGL 0,15 + nop ;[INF] 1, 1 +; line 146 : return( ERR_ERR ); +$DGL 0,16 + onew bc ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +??eb02_renge_task_immed_add: +; line 147 : } +; line 148 : } +??eb01_renge_task_immed_add: +?L0021: +; line 149 : else +; line 150 : { +??bb03_renge_task_immed_add: +; line 151 : // 空きを見つけた +; line 152 : // もたもたしているうちに割り込み等から割り込まれるの +; を考慮 +; line 153 : // 滅多にないはずだが +; line 154 : for( ; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) +$DGL 0,24 + mov a,[hl+1] ; i ;[INF] 2, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0026 ;[INF] 2, 4 +; line 155 : { +??bb04_renge_task_immed_add: +; line 156 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) +$DGL 0,26 + call !bs_S0094 ;[INF] 3, 3 + bnz $?L0028 ;[INF] 2, 4 +; line 157 : { +??bb05_renge_task_immed_add: +; line 158 : tasks_immed[ i ] = new_task; +$DGL 0,28 + movw ax,[hl+2] ; new_task ;[INF] 2, 1 + movw [de],ax ;[INF] 1, 1 +; line 159 : return( ERR_SUCCESS ); +$DGL 0,29 + clrw bc ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +??eb05_renge_task_immed_add: +; line 160 : } +?L0028: +??eb04_renge_task_immed_add: +; line 161 : } +$DGL 0,31 + inc [hl+1] ; i ;[INF] 3, 2 + br $?L0021 ;[INF] 2, 3 +?L0026: +; line 162 : // 割り込まれてタスク登録できなくなった +; line 163 : return( ERR_ERR ); +$DGL 0,33 + onew bc ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +??eb03_renge_task_immed_add: +; line 164 : } +?L0022: +??eb00_renge_task_immed_add: +; line 165 : } +$DGL 0,35 + inc [hl+1] ; i ;[INF] 3, 2 + br $?L0018 ;[INF] 2, 3 +?L0019: +; line 166 : // タスク登録しすぎ(無いはず +; line 167 : NOP(); // デバッガで捕まえるため +$DGL 0,37 + nop ;[INF] 1, 1 +; line 168 : return( ERR_ERR ); +$DGL 0,38 + onew bc ;[INF] 1, 1 +; line 169 : } +?L0017: +$DGL 0,39 +??ef_renge_task_immed_add: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_renge_task_immed_add: +; line 170 : +; line 171 : +; line 172 : +; line 173 : /************************************** +; line 174 : 逐次実行タスクの実行 +; line 175 : **************************************/ +; line 176 : err renge_task_immed_run(){ +_renge_task_immed_run: +$DGL 1,98 + push hl ;[INF] 1, 1 + subw sp,#04H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_renge_task_immed_run: +; line 177 : u8 list_id; +; line 178 : u8 last_task_id; +; line 179 : +; line 180 : do{ +??bb00_renge_task_immed_run: +; line 181 : last_task_id = 0xFF; +$DGL 0,6 + mov [hl+2],#0FFH ; last_task_id,255 ;[INF] 3, 1 +; line 182 : for( list_id = 0; list_id < TASK_IMMED_RUN_LIST_MAX; list_ +; id += 1 ){ +$DGL 0,7 + mov [hl+3],#00H ; list_id,0 ;[INF] 3, 1 +?L0035: + mov a,[hl+3] ; list_id ;[INF] 2, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0036 ;[INF] 2, 4 +??bb01_renge_task_immed_run: +; line 183 : if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ){ +$DGL 0,8 + call !bs_S0095 ;[INF] 3, 3 + bz $?L0038 ;[INF] 2, 4 +??bb02_renge_task_immed_run: +; line 184 : #ifdef _renge_test_ +; line 185 : if( tasks_immed[ list_id ] == TSK_IMM_DELETED_ ) +$DGL 0,10 + movw ax,[de] ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + cmpw ax,bc ;[INF] 1, 1 + bnz $?L0040 ;[INF] 2, 4 +; line 186 : { +??bb03_renge_task_immed_run: +; line 187 : NOP(); +$DGL 0,12 + nop ;[INF] 1, 1 +??eb03_renge_task_immed_run: +; line 188 : // タスク管理の不備 +; line 189 : // 存在しないタスクを実行しようとした +; line 190 : // タスクの削除後の処理がまずい +; line 191 : // 予期しないタイミングで immed_run が呼ばれた +; line 192 : } +$DGL 0,17 + br $?L0039 ;[INF] 2, 3 +?L0040: +; line 193 : else +; line 194 : #endif +; line 195 : { +??bb04_renge_task_immed_run: +; line 196 : if( tasks_immed[ list_id ]() == ERR_SUCCESS ) +$DGL 0,21 + mov a,[hl+3] ; list_id ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + clrb b ;[INF] 1, 1 + shlw bc,1 ;[INF] 2, 1 + movw ax,_tasks_immed[bc] ;[INF] 3, 1 + mov CS,#00H ; 0 ;[INF] 3, 1 + call ax ;[INF] 2, 3 + cmp0 c ;[INF] 1, 1 + bnz $?L0042 ;[INF] 2, 4 +; line 197 : { +??bb05_renge_task_immed_run: +; line 198 : tasks_immed[ list_id ] = TSK_IMM_DELETED_; +$DGL 0,23 + mov a,[hl+3] ; list_id ;[INF] 2, 1 + call !bs_S0096 ;[INF] 3, 3 +??eb05_renge_task_immed_run: +; line 199 : } +?L0042: +; line 200 : last_task_id = list_id; +$DGL 0,25 + mov a,[hl+3] ; list_id ;[INF] 2, 1 + mov [hl+2],a ; last_task_id ;[INF] 2, 1 +??eb04_renge_task_immed_run: +; line 201 : } +; line 202 : } +$DGL 0,27 +??eb02_renge_task_immed_run: + br $?L0039 ;[INF] 2, 3 +?L0038: +; line 203 : #ifdef _renge_test_ +; line 204 : else +; line 205 : { +??bb06_renge_task_immed_run: +; line 206 : list_id += 1; +$DGL 0,31 + inc [hl+3] ; list_id ;[INF] 3, 2 +; line 207 : for( ; list_id < TASK_IMMED_RUN_LIST_MAX; list_id+ +; + ) +$DGL 0,32 +?L0044: + mov a,[hl+3] ; list_id ;[INF] 2, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0036 ;[INF] 2, 4 +; line 208 : { +??bb07_renge_task_immed_run: +; line 209 : if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ) +$DGL 0,34 + call !bs_S0095 ;[INF] 3, 3 + skz ;[INF] 2, 1 +; line 210 : { +??bb08_renge_task_immed_run: +; line 211 : NOP(); // ? +$DGL 0,36 + nop ;[INF] 1, 1 +??eb08_renge_task_immed_run: +; line 212 : } +?L0047: +??eb07_renge_task_immed_run: +; line 213 : } +$DGL 0,38 + inc [hl+3] ; list_id ;[INF] 3, 2 + br $?L0044 ;[INF] 2, 3 +; line 214 : break; +??eb06_renge_task_immed_run: +; line 215 : } +?L0039: +??eb01_renge_task_immed_run: +; line 216 : #endif +; line 217 : } +$DGL 0,42 + inc [hl+3] ; list_id ;[INF] 3, 2 + br $?L0035 ;[INF] 2, 3 +?L0036: +; line 218 : +; line 219 : // タスク削除 +; line 220 : { +??bb09_renge_task_immed_run: +; line 221 : if( last_task_id != 0xFF ) +$DGL 0,46 + mov a,[hl+2] ; last_task_id ;[INF] 2, 1 + inc a ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0049 ;[INF] 3, 3 +; line 222 : { +??bb0A_renge_task_immed_run: +; line 223 : u8 i,j; +; line 224 : +; line 225 : #ifdef _renge_test_ +; line 226 : if ( tasks_immed[ 1 ] != 0 ){ +$DGL 0,51 + clrw ax ;[INF] 1, 1 + cmpw ax,!_tasks_immed+2 ;[INF] 3, 1 + skz ;[INF] 2, 1 +??bb0B_renge_task_immed_run: +; line 227 : NOP(); +$DGL 0,52 + nop ;[INF] 1, 1 +??eb0B_renge_task_immed_run: +; line 228 : } +?L0051: +; line 229 : #endif +; line 230 : // リスト前詰め +; line 231 : +; line 232 : i = 0; // 前詰め後リストの最後尾 +$DGL 0,57 + mov [hl+1],#00H ; i,0 ;[INF] 3, 1 +; line 233 : j = 1; // リストの後ろの方のタスクを探す +$DGL 0,58 + mov [hl+0],#01H ; j,1 ;[INF] 3, 1 +; line 234 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) +$DGL 0,59 +?L0053: + mov a,[hl] ; j ;[INF] 1, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + skc ;[INF] 2, 1 + br !?L0054 ;[INF] 3, 3 +; line 235 : { +??bb0C_renge_task_immed_run: +; line 236 : DI(); +$DGL 0,61 + di ;[INF] 3, 4 +; line 237 : if( tasks_immed[ i ] == TSK_IMM_DELETED_ ) +$DGL 0,62 + mov a,[hl+1] ; i ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + movw ax,_tasks_immed[bc] ;[INF] 3, 1 + onew bc ;[INF] 1, 1 + cmpw ax,bc ;[INF] 1, 1 + bnz $?L0056 ;[INF] 2, 4 +; line 238 : { +??bb0D_renge_task_immed_run: +; line 239 : if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) +$DGL 0,64 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + bnz $?L0058 ;[INF] 2, 4 +; line 240 : { +??bb0E_renge_task_immed_run: +; line 241 : // リストの最後だった +; line 242 : for( ; i < j ; i += 1 ) +$DGL 0,67 +?L0060: + mov a,[hl+1] ; i ;[INF] 2, 1 + cmp a,[hl] ; j ;[INF] 1, 1 + bnc $?L0061 ;[INF] 2, 4 +; line 243 : { +??bb0F_renge_task_immed_run: +; line 244 : tasks_immed[ i ] = TSK_IMM_EMPTY_; +$DGL 0,69 + mov a,[hl+1] ; i ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + movw _tasks_immed[bc],ax ;[INF] 3, 1 +??eb0F_renge_task_immed_run: +; line 245 : } +$DGL 0,70 + inc [hl+1] ; i ;[INF] 3, 2 + br $?L0060 ;[INF] 2, 3 +?L0061: +; line 246 : #ifdef _renge_test_ +; line 247 : /// ほんと? +; line 248 : j += 1; +$DGL 0,73 + inc [hl+0] ; j ;[INF] 3, 2 +; line 249 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j+ +; + ) +$DGL 0,74 +?L0063: + mov a,[hl] ; j ;[INF] 1, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0064 ;[INF] 2, 4 +; line 250 : { +??bb10_renge_task_immed_run: +; line 251 : if( tasks_immed[ j ] != TSK_IMM_EM +; PTY_ ) +$DGL 0,76 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + skz ;[INF] 2, 1 +; line 252 : { +??bb11_renge_task_immed_run: +; line 253 : NOP(); // ? +$DGL 0,78 + nop ;[INF] 1, 1 +??eb11_renge_task_immed_run: +; line 254 : } +?L0066: +; line 255 : } +$DGL 0,80 +??eb10_renge_task_immed_run: + inc [hl+0] ; j ;[INF] 3, 2 + br $?L0063 ;[INF] 2, 3 +?L0064: +; line 256 : #endif +; line 257 : EI(); +$DGL 0,82 + ei ;[INF] 3, 4 +; line 258 : break; +$DGL 0,83 + br $?L0054 ;[INF] 2, 3 +??eb0E_renge_task_immed_run: +; line 259 : } +?L0058: +; line 260 : if( tasks_immed[ j ] != TSK_IMM_DELETED_ ) +$DGL 0,85 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + cmpw ax,bc ;[INF] 1, 1 + bz $?L0057 ;[INF] 2, 4 +; line 261 : { +??bb12_renge_task_immed_run: +; line 262 : // 探索隊が前詰めすべきタスクを見つけた +; line 263 : tasks_immed[ i ] = tasks_immed[ j ]; +$DGL 0,88 + movw ax,[de] ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + mov a,[hl+1] ; i ;[INF] 2, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + xchw ax,bc ;[INF] 1, 1 + movw _tasks_immed[bc],ax ;[INF] 3, 1 +; line 264 : tasks_immed[ j ] = TSK_IMM_DELETED_; +$DGL 0,89 + mov a,[hl] ; j ;[INF] 1, 1 + call !bs_S0096 ;[INF] 3, 3 +; line 265 : i += 1; +$DGL 0,90 + inc [hl+1] ; i ;[INF] 3, 2 +??eb12_renge_task_immed_run: +; line 266 : } +; line 267 : } +$DGL 0,92 +??eb0D_renge_task_immed_run: + br $?L0057 ;[INF] 2, 3 +?L0056: +; line 268 : else +; line 269 : { +??bb13_renge_task_immed_run: +; line 270 : #ifdef _renge_test_ +; line 271 : // タスクが滞留 +; line 272 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) +$DGL 0,97 + call !bs_S0094 ;[INF] 3, 3 + sknz ;[INF] 2, 1 +; line 273 : { +??bb14_renge_task_immed_run: +; line 274 : NOP(); +$DGL 0,99 + nop ;[INF] 1, 1 +??eb14_renge_task_immed_run: +; line 275 : // そんなはずない +; line 276 : } +?L0070: +; line 277 : #endif +; line 278 : i += 1; +$DGL 0,103 + inc [hl+1] ; i ;[INF] 3, 2 +??eb13_renge_task_immed_run: +; line 279 : } +?L0057: +; line 280 : EI(); +$DGL 0,105 + ei ;[INF] 3, 4 +; line 281 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) +$DGL 0,106 + call !bs_S0094 ;[INF] 3, 3 + bnz $?L0072 ;[INF] 2, 4 +; line 282 : { +??bb15_renge_task_immed_run: +; line 283 : #ifdef _renge_test_ +; line 284 : NOP(); +$DGL 0,109 + nop ;[INF] 1, 1 +; line 285 : #endif +; line 286 : break; +$DGL 0,111 + br $?L0054 ;[INF] 2, 3 +??eb15_renge_task_immed_run: +; line 287 : // リストの最後だった +; line 288 : } +?L0072: +??eb0C_renge_task_immed_run: +; line 289 : } +$DGL 0,114 + inc [hl+0] ; j ;[INF] 3, 2 + br !?L0053 ;[INF] 3, 3 +?L0054: +; line 290 : DI(); +$DGL 0,115 + di ;[INF] 3, 4 +; line 291 : +; line 292 : // ここまでで完全に前詰めされている +; line 293 : for( j = 0; j < TASK_IMMED_RUN_LIST_MAX; j++ ) +$DGL 0,118 + mov [hl+0],#00H ; j,0 ;[INF] 3, 1 +?L0074: + mov a,[hl] ; j ;[INF] 1, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0075 ;[INF] 2, 4 +; line 294 : { +??bb16_renge_task_immed_run: +; line 295 : if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) +$DGL 0,120 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + bnz $?L0077 ;[INF] 2, 4 +; line 296 : { +??bb17_renge_task_immed_run: +; line 297 : #ifdef _renge_test_ +; line 298 : NOP(); +$DGL 0,123 + nop ;[INF] 1, 1 +; line 299 : j += 1; +$DGL 0,124 + inc [hl+0] ; j ;[INF] 3, 2 +; line 300 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) +$DGL 0,125 +?L0079: + mov a,[hl] ; j ;[INF] 1, 1 + cmp a,#08H ; 8 ;[INF] 2, 1 + bnc $?L0075 ;[INF] 2, 4 +; line 301 : { +??bb18_renge_task_immed_run: +; line 302 : if( tasks_immed[ j ] != TSK_IMM_EMPTY_ +; ) +$DGL 0,127 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + skz ;[INF] 2, 1 +; line 303 : { +??bb19_renge_task_immed_run: +; line 304 : NOP(); // ? +$DGL 0,129 + nop ;[INF] 1, 1 +??eb19_renge_task_immed_run: +; line 305 : } +?L0082: +??eb18_renge_task_immed_run: +; line 306 : } +$DGL 0,131 + inc [hl+0] ; j ;[INF] 3, 2 + br $?L0079 ;[INF] 2, 3 +; line 307 : #endif +; line 308 : break; +??eb17_renge_task_immed_run: +; line 309 : // リストの最後 +; line 310 : } +?L0077: +; line 311 : if( tasks_immed[ j ] == TSK_IMM_DELETED_ ) +$DGL 0,136 + mov a,[hl] ; j ;[INF] 1, 1 + clrb x ;[INF] 1, 1 + shrw ax,7 ;[INF] 2, 1 + addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + movw ax,[de] ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + cmpw ax,bc ;[INF] 1, 1 + bnz $?L0084 ;[INF] 2, 4 +; line 312 : { +??bb1A_renge_task_immed_run: +; line 313 : tasks_immed[ j ] = TSK_IMM_EMPTY_; +$DGL 0,138 + clrw ax ;[INF] 1, 1 + movw [de],ax ;[INF] 1, 1 +??eb1A_renge_task_immed_run: +; line 314 : } +?L0084: +??eb16_renge_task_immed_run: +; line 315 : } +$DGL 0,140 + inc [hl+0] ; j ;[INF] 3, 2 + br $?L0074 ;[INF] 2, 3 +?L0075: +; line 316 : EI(); +$DGL 0,141 + ei ;[INF] 3, 4 +??eb0A_renge_task_immed_run: +; line 317 : } +?L0049: +??eb09_renge_task_immed_run: +; line 318 : } +??eb00_renge_task_immed_run: +; line 319 : } +; line 320 : #if 0 +; line 321 : while( last_task_id != 0xFF ); // タスクが残っていたら延々再実 +; 行 +; line 322 : #else +; line 323 : while( 0 ); +; line 324 : #endif +; line 325 : +; line 326 : if( last_task_id != 0xFF ) +$DGL 0,151 + mov a,[hl+2] ; last_task_id ;[INF] 2, 1 + inc a ;[INF] 1, 1 + bz $?L0086 ;[INF] 2, 4 +; line 327 : { +??bb1B_renge_task_immed_run: +; line 328 : // まだタスクが残ってる（また呼んでね） +; line 329 : return( ERR_ERR ); +$DGL 0,154 + onew bc ;[INF] 1, 1 + br $?L0031 ;[INF] 2, 3 +??eb1B_renge_task_immed_run: +; line 330 : } +?L0086: +; line 331 : +; line 332 : return( ERR_SUCCESS ); +$DGL 0,157 + clrw bc ;[INF] 1, 1 +; line 333 : } +?L0031: +$DGL 0,158 +??ef_renge_task_immed_run: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_renge_task_immed_run: +; line 334 : +; line 335 : +; line 336 : +; line 337 : /*************************************************************** +; *************** +; line 338 : 単位は ms +; line 339 : NOPを回すだけ、指定時間CPUを *占有します* 。 +; line 340 : 割り込みとか入るとその分遅れます。 +; line 341 : 少し誤差あります。 +; line 342 : *************************************************************** +; **************/ +; line 343 : void wait_ms( u8 ms ){ +_wait_ms: +$DGL 1,222 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_wait_ms: +; line 344 : u16 fine; +; line 345 : +; line 346 : WDT_Restart(); +$DGL 0,4 + call !_WDT_Restart ;[INF] 3, 3 +; line 347 : // まだ適当です！ +; line 348 : while( ms != 0 ){ +$DGL 0,6 +?L0090: + mov a,[hl+2] ; ms ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0091 ;[INF] 2, 4 +??bb00_wait_ms: +; line 349 : ms--; +$DGL 0,7 + dec [hl+2] ; ms ;[INF] 3, 2 +; line 350 : #ifdef _OVERCLOCK_ +; line 351 : fine = 860; +$DGL 0,9 + movw ax,#035CH ; 860 ;[INF] 3, 1 + movw [hl],ax ; fine ;[INF] 1, 1 +; line 352 : #else +; line 353 : fine = 430; +; line 354 : #endif +; line 355 : while( fine != 0 ){ +$DGL 0,13 +?L0092: + clrw ax ;[INF] 1, 1 + cmpw ax,[hl+0] ; fine ;[INF] 3, 1 + bz $?L0090 ;[INF] 2, 4 +??bb01_wait_ms: +; line 356 : fine -= 1; +$DGL 0,14 + decw [hl+0] ; fine ;[INF] 3, 2 +??eb01_wait_ms: +; line 357 : } +$DGL 0,15 + br $?L0092 ;[INF] 2, 3 +??eb00_wait_ms: +; line 358 : } +?L0091: +; line 359 : } +$DGL 0,17 +??ef_wait_ms: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_wait_ms: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c +; +; $FUNC renge_init(53) +; void=(void) +; CODE SIZE= 3 bytes, CLOCK_SIZE= 3 clocks, STACK_SIZE= 0 bytes +; +; $CALL renge_task_immed_init(54) +; void=(void) +; +; $FUNC renge_task_interval_run(81) +; bc=(void) +; CODE SIZE= 43 bytes, CLOCK_SIZE= 45 clocks, STACK_SIZE= 6 bytes +; +; $CALL (92) +; void=(void) +; +; $CALL renge_task_immed_run(94) +; bc=(void) +; +; $FUNC renge_task_immed_init(117) +; void=(void) +; CODE SIZE= 21 bytes, CLOCK_SIZE= 24 clocks, STACK_SIZE= 2 bytes +; +; $FUNC renge_task_immed_add(131) +; bc=(pointer new_task:ax) +; CODE SIZE= 66 bytes, CLOCK_SIZE= 98 clocks, STACK_SIZE= 10 bytes +; +; $FUNC renge_task_immed_run(176) +; bc=(void) +; CODE SIZE= 341 bytes, CLOCK_SIZE= 381 clocks, STACK_SIZE= 10 bytes +; +; $CALL (196) +; bc=(void) +; +; $FUNC wait_ms(343) +; void=(unsigned char ms:x) +; CODE SIZE= 36 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 10 bytes +; +; $CALL WDT_Restart(346) +; void=(void) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/rtc.asm b/branches/0.10(X3)/inter_asm/rtc.asm new file mode 100644 index 0000000..ae17cd9 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/rtc.asm @@ -0,0 +1,760 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no rtc.c +; In-file : rtc.c +; Asm-file : inter_asm\rtc.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, rtc.c +$DGS MOD_NAM, rtc, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _RTC_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 051H, 00H, 00H +$DGS BEG_FUN, ??bf_RTC_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 017H, 02H, 047H +$DGS BEG_BLK, ??bb00_RTC_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 04BH +$DGS END_BLK, ??eb00_RTC_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 017H +$DGS BEG_BLK, ??bb01_RTC_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 022H, 00H, 00H +$DGS END_BLK, ??eb01_RTC_init, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS END_FUN, ??ef_RTC_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 029H +$DGS GLV_SYM, _int_rtc, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 067H, 00H, 00H +$DGS BEG_FUN, ??bf_int_rtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 048H, 02H, 055H +$DGS BEG_BLK, ??bb00_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 057H +$DGS BEG_BLK, ??bb01_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 059H +$DGS BEG_BLK, ??bb02_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 05DH +$DGS END_BLK, ??eb02_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0AH +$DGS BEG_BLK, ??bb03_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 00H +$DGS END_BLK, ??eb03_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS END_BLK, ??eb01_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS END_BLK, ??eb00_int_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS END_FUN, ??ef_int_rtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 013H +$DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H +$DGS BEG_FUN, ??bf_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 063H, 02H, 06BH +$DGS BEG_BLK, ??bb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 06DH +$DGS BEG_BLK, ??bb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 00H +$DGS END_BLK, ??eb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS END_BLK, ??eb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS END_FUN, ??ef_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0EH +$DGS GLV_SYM, _set_rtc, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H +$DGS BEG_FUN, ??bf_set_rtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 07BH, 02H, 07BH +$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_set_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 00H +$DGS END_BLK, ??eb00_set_rtc, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS END_FUN, ??ef_set_rtc, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 09H +$DGS GLV_SYM, _rtc_unlock, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H +$DGS BEG_FUN, ??bf_rtc_unlock, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 08CH, 02H, 085H +$DGS BEG_BLK, ??bb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 087H +$DGS BEG_BLK, ??bb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 08DH +$DGS END_BLK, ??eb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS END_BLK, ??eb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 00H +$DGS END_BLK, ??eb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS END_FUN, ??ef_rtc_unlock, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01CH +$DGS GLV_SYM, _int_rtc_int, U, U, 0E001H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H +$DGS BEG_FUN, ??bf_int_rtc_int, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0B2H, 00H, 099H +$DGS END_FUN, ??ef_int_rtc_int, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03H +$DGS GLV_SYM, _rtc_work, U, U, 0CH, 026H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 07H, 07H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _rtc_lock, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _rtc_dirty, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 02H, 00H, 00H + + EXTRN _vreg_ctr + EXTRN _system_status + EXTBIT _renge_flg_interval + PUBLIC _rtc_work + PUBLIC _rtc_lock + PUBLIC _rtc_dirty + PUBLIC _rtc_alarm_dirty + PUBLIC _RTC_init + PUBLIC _int_rtc + PUBLIC _rtc_buf_reflesh + PUBLIC _set_rtc + PUBLIC _rtc_unlock + PUBLIC _int_rtc_int + +@@BITS BSEG +_rtc_lock DBIT +_rtc_dirty DBIT +_rtc_alarm_dirty DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP +_rtc_work: DS (7) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : /* ======================================================== +; line 2 : RTC +; line 3 : ======================================================== */ +; line 4 : #pragma sfr +; line 5 : #pragma inline +; line 6 : +; line 7 : +; line 8 : #include "incs.h" +; line 9 : +; line 10 : +; line 11 : +; line 12 : // ======================================================== +; line 13 : u8 rtc_work[7]; +; line 14 : bit rtc_lock; +; line 15 : bit rtc_dirty; +; line 16 : bit rtc_alarm_dirty; +; line 17 : +; line 18 : /* ======================================================== +; line 19 : ペリフェラルの初期化 +; line 20 : レジスタの電池交換ビットのセット +; line 21 : ======================================================== */ +; line 22 : void RTC_init( void ) +; line 23 : { + +ROM_CODE CSEG BASE +_RTC_init: +$DGL 1,67 + push hl ;[INF] 1, 1 +??bf_RTC_init: +; line 24 : +; line 25 : if( !RTCEN ) // ビットが立っていたらリブート +$DGL 0,3 + movw hl,#0F0H ; 240 ;[INF] 3, 1 + mov1 CY,[hl].7 ;[INF] 2, 1 + bc $?L0003 ;[INF] 2, 4 +; line 26 : { +??bb00_RTC_init: +; line 27 : RTCEN = 1; // モジュールON +$DGL 0,5 + set1 !PER0.7 ;[INF] 4, 2 +; line 28 : +; line 29 : // RTC設定 +; line 30 : RTCC0 = 0b00001000; /* 動作停止、24時間制、32k出力「ま +; だなし」、定周期割り込みなし */ +$DGL 0,8 + mov RTCC0,#08H ; 8 ;[INF] 3, 1 +; line 31 : RTCC1 = 0b11000000; /* アラーム割り込み有効＆動作開始 +; */ +$DGL 0,9 + mov RTCC1,#0C0H ; 192 ;[INF] 3, 1 +; line 32 : RTCC2 = 0b10000000; /* インターバル:32k/2^6=2ms、RTCD +; IV出力なし */ +$DGL 0,10 + mov RTCC2,#080H ; 128 ;[INF] 3, 1 +; line 33 : +; line 34 : SEC = 0x00; +$DGL 0,12 + clrb !SEC ;[INF] 3, 1 +; line 35 : MIN = 0x00; +$DGL 0,13 + clrb !MIN ;[INF] 3, 1 +; line 36 : HOUR = 0x15; +$DGL 0,14 + mov HOUR,#015H ; 21 ;[INF] 3, 1 +; line 37 : DAY = 0x01; +$DGL 0,15 + oneb !DAY ;[INF] 3, 1 +; line 38 : WEEK = 0x00; +$DGL 0,16 + clrb !WEEK ;[INF] 3, 1 +; line 39 : MONTH = 0x11; +$DGL 0,17 + mov MONTH,#011H ; 17 ;[INF] 3, 1 +; line 40 : YEAR = 0x09; +$DGL 0,18 + mov YEAR,#09H ; 9 ;[INF] 3, 1 +; line 41 : +; line 42 : ALARMWW = 0x7F; +$DGL 0,20 + mov ALARMWW,#07FH ; 127 ;[INF] 3, 1 +; line 43 : +; line 44 : vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT; +$DGL 0,22 + set1 !_vreg_ctr+2.0 ;[INF] 4, 2 +??eb00_RTC_init: +; line 45 : } +?L0003: +; line 46 : // 割り込み設定 +; line 47 : RTCIF = 0; +$DGL 0,25 + clr1 IF1H.1 ;[INF] 3, 2 +; line 48 : RTCIIF = 0; +$DGL 0,26 + clr1 IF1H.2 ;[INF] 3, 2 +; line 49 : RTCMK = 1; /* 割り込み(定周期)禁止 */ +$DGL 0,27 + set1 MK1H.1 ;[INF] 3, 2 +; line 50 : RTCIMK = 0; /* 割り込み(アラーム&インターバル +; )許可 */ +$DGL 0,28 + clr1 MK1H.2 ;[INF] 3, 2 +; line 51 : +; line 52 : RTCE = 1; /* 動作開始 */ +$DGL 0,30 + set1 RTCC0.7 ;[INF] 3, 2 +; line 53 : +; line 54 : RWAIT = 1; +$DGL 0,32 + set1 RTCC1.0 ;[INF] 3, 2 +; line 55 : while( !RWST ) +$DGL 0,33 +?L0005: + bt RTCC1.1,$?L0006 ;[INF] 4, 5 +; line 56 : {; +??bb01_RTC_init: +??eb01_RTC_init: +; line 57 : } +$DGL 0,35 + br $?L0005 ;[INF] 2, 3 +?L0006: +; line 58 : RWAIT = 0; +$DGL 0,36 + clr1 RTCC1.0 ;[INF] 3, 2 +; line 59 : +; line 60 : rtc_lock = 0; +$DGL 0,38 + clr1 _rtc_lock ;[INF] 3, 2 +; line 61 : rtc_dirty = 0; +$DGL 0,39 + clr1 _rtc_dirty ;[INF] 3, 2 +; line 62 : rtc_alarm_dirty = 0; +$DGL 0,40 + clr1 _rtc_alarm_dirty ;[INF] 3, 2 +; line 63 : } +$DGL 0,41 +??ef_RTC_init: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_RTC_init: +; line 64 : +; line 65 : +; line 66 : +; line 67 : /* ======================================================== +; line 68 : RTC アラーム割り込み +; line 69 : 2^6/fXT（1.953125 ms） +; line 70 : ======================================================== */ +; line 71 : __interrupt void int_rtc( ) +; line 72 : { + +@@BASE CSEG BASE +_int_rtc: +$DGL 1,81 + push ax ;[INF] 1, 1 +??bf_int_rtc: +; line 73 : // 日付も指定日で +; line 74 : if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY ) +; line 75 : && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH ) +; line 76 : && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) ) +$DGL 0,5 + mov a,!_vreg_ctr+58 ;[INF] 3, 1 + cmp a,!DAY ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 + mov a,!_vreg_ctr+59 ;[INF] 3, 1 + cmp a,!MONTH ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 + mov a,!_vreg_ctr+60 ;[INF] 3, 1 + cmp a,!YEAR ;[INF] 3, 1 + bnz $?L0013 ;[INF] 2, 4 +; line 77 : { +??bb00_int_rtc: +; line 78 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) = +; = 0 ) +$DGL 0,7 + mov a,!_vreg_ctr+25 ;[INF] 3, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0013 ;[INF] 2, 4 +; line 79 : { +??bb01_int_rtc: +; line 80 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM; +$DGL 0,9 + set1 !_vreg_ctr+17.2 ;[INF] 4, 2 +; line 81 : IRQ0_ast; +$DGL 0,10 +??bb02_int_rtc: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb02_int_rtc: +; line 82 : // マスクをしてあったら、電源を入れません +; line 83 : if(( system_status.pwr_state == BT_CHARGE ) || +$DGL 0,12 + cmp !_system_status,#06H ; 6 ;[INF] 4, 1 + bz $?L0015 ;[INF] 2, 4 +; line 84 : ( system_status.pwr_state == OFF )) +$DGL 0,13 + cmp !_system_status,#01H ; 1 ;[INF] 4, 1 + sknz ;[INF] 2, 1 +?L0015: +; line 85 : { +??bb03_int_rtc: +; line 86 : system_status.poweron_reason = RTC_ALARM; +$DGL 0,15 + mov !_system_status+1,#02H ; 2 ;[INF] 4, 1 +??eb03_int_rtc: +; line 87 : } +?L0013: +??eb01_int_rtc: +; line 88 : } +??eb00_int_rtc: +; line 89 : } +; line 90 : } +$DGL 0,19 +??ef_int_rtc: + pop ax ;[INF] 1, 1 + reti ;[INF] 2, 6 +??ee_int_rtc: +; line 91 : +; line 92 : +; line 93 : +; line 94 : /* ======================================================== +; line 95 : RTC のリード +; line 96 : レジスタは、sec,min,hour,week,day,month,year の順 +; line 97 : ======================================================== */ +; line 98 : void rtc_buf_reflesh( ) +; line 99 : { + +ROM_CODE CSEG BASE +_rtc_buf_reflesh: +$DGL 1,103 + push hl ;[INF] 1, 1 +??bf_rtc_buf_reflesh: +; line 100 : if( rtc_lock == 0 ) +$DGL 0,2 + bt _rtc_lock,$?L0018 ;[INF] 4, 5 +; line 101 : { +??bb00_rtc_buf_reflesh: +; line 102 : rtc_lock = 1; +$DGL 0,4 + set1 _rtc_lock ;[INF] 3, 2 +; line 103 : RWAIT = 1; +$DGL 0,5 + set1 RTCC1.0 ;[INF] 3, 2 +; line 104 : while( !RWST ) +$DGL 0,6 +?L0020: + bt RTCC1.1,$?L0021 ;[INF] 4, 5 +; line 105 : {; +??bb01_rtc_buf_reflesh: +??eb01_rtc_buf_reflesh: +; line 106 : } +$DGL 0,8 + br $?L0020 ;[INF] 2, 3 +?L0021: +; line 107 : +; line 108 : memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 ); +$DGL 0,10 + movw de,#loww (_vreg_ctr+48) ;[INF] 3, 1 + movw hl,#0FF92H ; -110 ;[INF] 3, 1 + mov c,#07H ; 7 ;[INF] 2, 1 +?L0022: + mov a,[hl] ;[INF] 1, 1 + mov [de],a ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw hl ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $?L0022 ;[INF] 2, 4 +; line 109 : RWAIT = 0; +$DGL 0,11 + clr1 RTCC1.0 ;[INF] 3, 2 +??eb00_rtc_buf_reflesh: +; line 110 : // renge_task_immed_add( tski_rtc_close ); +; line 111 : } +?L0018: +; line 112 : } +$DGL 0,14 +??ef_rtc_buf_reflesh: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_rtc_buf_reflesh: +; line 113 : +; line 114 : +; line 115 : +; line 116 : /* ======================================================== +; line 117 : RTC のライト +; line 118 : set_rtc_close と対で使って下さい。 +; line 119 : こいつはバッファにコピーするだけで、 +; line 120 : 実際にRTCにセットするのはset_rtc_close()です。 +; line 121 : ======================================================== */ +; line 122 : void set_rtc( u8 adrs, u8 data ) +; line 123 : { +_set_rtc: +$DGL 1,117 + push hl ;[INF] 1, 1 + mov a,[sp+6] ;[INF] 2, 1 + movw hl,ax ;[INF] 1, 1 +??bf_set_rtc: +; line 124 : if( rtc_dirty == 0 ) +$DGL 0,2 + bt _rtc_dirty,$?L0026 ;[INF] 4, 5 +; line 125 : { +??bb00_set_rtc: +; line 126 : rtc_dirty = 1; +$DGL 0,4 + set1 _rtc_dirty ;[INF] 3, 2 +; line 127 : memcpy( rtc_work, &SEC, 7 ); +$DGL 0,5 + push hl ;[INF] 1, 1 + movw de,#loww (_rtc_work) ;[INF] 3, 1 + movw ax,#0FF92H ; -110 ;[INF] 3, 1 + movw hl,ax ;[INF] 1, 1 + mov c,#07H ; 7 ;[INF] 2, 1 +?L0028: + mov a,[hl] ;[INF] 1, 1 + mov [de],a ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw hl ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $?L0028 ;[INF] 2, 4 + pop hl ;[INF] 1, 1 +??eb00_set_rtc: +; line 128 : // renge_task_immed_add( tski_rtc_close ); // I2C終了時に行う +; line 129 : } +?L0026: +; line 130 : rtc_work[adrs] = data; +$DGL 0,8 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,h ;[INF] 1, 1 + mov _rtc_work[b],a ;[INF] 3, 1 +; line 131 : } +$DGL 0,9 +??ef_set_rtc: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_set_rtc: +; line 132 : +; line 133 : +; line 134 : +; line 135 : /* ======================================================== +; line 136 : 必要ならば、RTCレジスタの更新 +; line 137 : ======================================================== */ +; line 138 : // task_status_immed tski_rtc_close(){ +; line 139 : void rtc_unlock( ) +; line 140 : { +_rtc_unlock: +$DGL 1,129 + push hl ;[INF] 1, 1 +??bf_rtc_unlock: +; line 141 : // リードロック +; line 142 : // if( rtc_lock != 0 ){ +; line 143 : rtc_lock = 0; +$DGL 0,4 + clr1 _rtc_lock ;[INF] 3, 2 +; line 144 : // } +; line 145 : +; line 146 : // ライトロック +; line 147 : if( rtc_dirty != 0 ) +$DGL 0,8 + bf _rtc_dirty,$?L0032 ;[INF] 4, 5 +; line 148 : { +??bb00_rtc_unlock: +; line 149 : rtc_dirty = 0; +$DGL 0,10 + clr1 _rtc_dirty ;[INF] 3, 2 +; line 150 : RWAIT = 1; +$DGL 0,11 + set1 RTCC1.0 ;[INF] 3, 2 +; line 151 : while( !RWST ) +$DGL 0,12 +?L0034: + bt RTCC1.1,$?L0035 ;[INF] 4, 5 +; line 152 : {; +??bb01_rtc_unlock: +??eb01_rtc_unlock: +; line 153 : } +$DGL 0,14 + br $?L0034 ;[INF] 2, 3 +?L0035: +; line 154 : memcpy( &SEC, rtc_work, 7 ); +$DGL 0,15 + movw de,#0FF92H ; -110 ;[INF] 3, 1 + movw hl,#loww (_rtc_work) ;[INF] 3, 1 + mov c,#07H ; 7 ;[INF] 2, 1 +?L0036: + mov a,[hl] ;[INF] 1, 1 + mov [de],a ;[INF] 1, 1 + incw de ;[INF] 1, 1 + incw hl ;[INF] 1, 1 + dec c ;[INF] 1, 1 + bnz $?L0036 ;[INF] 2, 4 +; line 155 : RWAIT = 0; +$DGL 0,16 + clr1 RTCC1.0 ;[INF] 3, 2 +??eb00_rtc_unlock: +; line 156 : } +?L0032: +; line 157 : +; line 158 : // アラームセット +; line 159 : if( rtc_alarm_dirty ) +$DGL 0,20 + bf _rtc_alarm_dirty,$?L0038 ;[INF] 4, 5 +; line 160 : { +??bb02_rtc_unlock: +; line 161 : WALE = 0; +$DGL 0,22 + clr1 RTCC1.7 ;[INF] 3, 2 +; line 162 : ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN]; +$DGL 0,23 + mov a,!_vreg_ctr+56 ;[INF] 3, 1 + mov ALARMWM,a ;[INF] 2, 1 +; line 163 : ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR]; +$DGL 0,24 + mov a,!_vreg_ctr+57 ;[INF] 3, 1 + mov ALARMWH,a ;[INF] 2, 1 +; line 164 : rtc_dirty = 0; +$DGL 0,25 + clr1 _rtc_dirty ;[INF] 3, 2 +; line 165 : WALE = 1; +$DGL 0,26 + set1 RTCC1.7 ;[INF] 3, 2 +??eb02_rtc_unlock: +; line 166 : } +?L0038: +; line 167 : } +$DGL 0,28 +??ef_rtc_unlock: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_rtc_unlock: +; line 168 : +; line 169 : +; line 170 : +; line 171 : +; line 172 : +; line 173 : /* ======================================================== +; line 174 : RTC システムチックタイマ割り込みベクタ +; line 175 : 2^6/fXT（1.953125 ms） +; line 176 : ======================================================== */ +; line 177 : __interrupt void int_rtc_int( ) +; line 178 : { + +@@BASE CSEG BASE +_int_rtc_int: +$DGL 1,147 +??bf_int_rtc_int: +; line 179 : renge_flg_interval = 1; +$DGL 0,2 + set1 _renge_flg_interval ;[INF] 3, 2 +; line 180 : } +$DGL 0,3 +??ef_int_rtc_int: + reti ;[INF] 2, 6 +??ee_int_rtc_int: + +@@CODEL CSEG + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c +; +; $FUNC RTC_init(23) +; void=(void) +; CODE SIZE= 87 bytes, CLOCK_SIZE= 57 clocks, STACK_SIZE= 2 bytes +; +; $FUNC int_rtc(72) +; void=(void) +; CODE SIZE= 62 bytes, CLOCK_SIZE= 47 clocks, STACK_SIZE= 2 bytes +; +; $FUNC rtc_buf_reflesh(99) +; void=(void) +; CODE SIZE= 37 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 2 bytes +; +; $FUNC set_rtc(123) +; void=(unsigned char adrs:x, unsigned char data:[sp+6]) +; CODE SIZE= 37 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 4 bytes +; +; $FUNC rtc_unlock(140) +; void=(void) +; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 2 bytes +; +; $FUNC int_rtc_int(178) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/self_flash.asm b/branches/0.10(X3)/inter_asm/self_flash.asm new file mode 100644 index 0000000..f199fd5 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/self_flash.asm @@ -0,0 +1,1310 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no self_flash.c +; In-file : self_flash.c +; Asm-file : inter_asm\self_flash.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0B4H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, self_flash.c +$DGS MOD_NAM, self_flash, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 019H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS LAB_SYM, bs_F0064, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0064, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0062, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0062, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0063, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0063, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0061, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0061, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0060, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0060, U, U, 00H, 06H, 00H, 00H +$DGS GLV_SYM, _firm_update, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H +$DGS BEG_FUN, ??bf_firm_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 061H, 06H, 029H +$DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 02DH +$DGS END_BLK, ??eb00_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 017H +$DGS BEG_BLK, ??bb01_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01FH, 00H, 02FH +$DGS BEG_BLK, ??bb02_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 035H +$DGS AUT_VAR, _p_buffer, 02H, 0FFFFH, 0CH, 01H, 01H, 01H +$DGS AUX_STR, 00H, 029H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS AUT_VAR, _buffer_fill, 01H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 02AH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb03_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 030H, 00H, 037H +$DGS BEG_BLK, ??bb04_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 031H, 00H, 03DH +$DGS END_BLK, ??eb04_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 031H +$DGS END_BLK, ??eb03_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 037H +$DGS BEG_BLK, ??bb05_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 043H +$DGS END_BLK, ??eb05_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04AH +$DGS END_BLK, ??eb02_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04CH +$DGS BEG_BLK, ??bb06_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04EH, 00H, 047H +$DGS END_BLK, ??eb06_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 051H +$DGS BEG_BLK, ??bb07_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 054H, 00H, 04DH +$DGS END_BLK, ??eb07_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 056H +$DGS END_BLK, ??eb01_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 057H +$DGS BEG_BLK, ??bb08_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05CH, 00H, 053H +$DGS AUT_VAR, _i, 03H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 05DH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS AUT_VAR, _comp, 02H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 05EH, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb09_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 062H, 00H, 057H +$DGS END_BLK, ??eb09_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 064H +$DGS BEG_BLK, ??bb0A_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 066H, 00H, 05BH +$DGS END_BLK, ??eb0A_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06CH +$DGS BEG_BLK, ??bb0B_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06EH, 00H, 00H +$DGS END_BLK, ??eb0B_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 075H +$DGS END_BLK, ??eb08_firm_update, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 076H +$DGS END_FUN, ??ef_firm_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 077H +$DGS GLV_SYM, _firm_restore, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H +$DGS BEG_FUN, ??bf_firm_restore, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0E3H, 00H, 069H +$DGS END_FUN, ??ef_firm_restore, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 013H +$DGS STA_SYM, _FSL_Open, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 077H, 00H, 00H +$DGS BEG_FUN, ??bf_FSL_Open, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0FCH, 00H, 06DH +$DGS BEG_BLK, ??bb00_FSL_Open, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 071H +$DGS END_BLK, ??eb00_FSL_Open, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS BEG_BLK, ??bb01_FSL_Open, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 00H +$DGS END_BLK, ??eb01_FSL_Open, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01BH +$DGS END_FUN, ??ef_FSL_Open, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01CH +$DGS STA_SYM, _FSL_Close, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H +$DGS BEG_FUN, ??bf_FSL_Close, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 011FH, 00H, 07BH +$DGS BEG_BLK, ??bb00_FSL_Close, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 00H +$DGS END_BLK, ??eb00_FSL_Close, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04H +$DGS END_FUN, ??ef_FSL_Close, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0EH +$DGS STA_SYM, _firm_duplicate, U, U, 0CH, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0A8H, 00H, 00H +$DGS BEG_FUN, ??bf_firm_duplicate, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0139H, 0AH, 08AH +$DGS FUN_ARG, _p_rom, 06H, 0FFFFH, 0CH, 09H, 01H, 01H +$DGS AUX_STR, 00H, 00H, 04H, 00H, 00H, 00H, 00H, 02H +$DGS FUN_ARG, _block_dest, 010H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 08CH +$DGS BEG_BLK, ??bb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 090H +$DGS END_BLK, ??eb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS BEG_BLK, ??bb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 015H, 00H, 096H +$DGS AUT_VAR, _buffer_fill, 03H, 0FFFFH, 0CH, 01H, 01H, 00H +$DGS AUX_STR, 00H, 016H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS AUT_VAR, _p_buff, 00H, 0FFFFH, 0CH, 01H, 01H, 01H +$DGS AUX_STR, 00H, 017H, 02H, 00H, 00H, 00H, 00H, 01H +$DGS BEG_BLK, ??bb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01DH, 00H, 09AH +$DGS END_BLK, ??eb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 022H +$DGS BEG_BLK, ??bb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02CH, 00H, 0A0H +$DGS END_BLK, ??eb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02FH +$DGS END_BLK, ??eb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS BEG_BLK, ??bb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 00H +$DGS END_BLK, ??eb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 036H +$DGS END_BLK, ??eb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 037H +$DGS END_FUN, ??ef_firm_duplicate, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03AH +$DGS STA_SYM, _my_FSL_Init, U, U, 0CH, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0AEH, 00H, 00H +$DGS BEG_FUN, ??bf_my_FSL_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0179H, 00H, 0AEH +$DGS END_FUN, ??ef_my_FSL_Init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0CH +$DGS GLV_SYM, _tski_mcu_reset, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 0B4H, 00H, 00H +$DGS BEG_FUN, ??bf_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0188H, 00H, 0B4H +$DGS END_FUN, ??ef_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0BH +$DGS GLV_SYM, _fsl_fx_MHz_u08, U, U, 0500CH, 026H, 00H, 00H +$DGS GLV_SYM, _fsl_low_voltage_u08, U, U, 0500CH, 026H, 00H, 00H +$DGS GLV_SYM, _FSL_Erase, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_IVerify, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _FSL_Write, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _pool, U, U, 0DH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_SwapBootCluster, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_InvertBootFlag, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, @@iscmp, U, U, 00H, 02H, 00H, 00H +$DGS GLV_SYM, _FSL_BlankCheck, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_Init, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_ModeCheck, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _FSL_ForceReset, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _FSL_Erase + EXTRN _FSL_IVerify + EXTRN _@RTARG0 + EXTRN _@RTARG2 + EXTRN _FSL_Write + EXTRN _pool + EXTRN _WDT_Restart + EXTRN _FSL_SwapBootCluster + EXTRN _FSL_InvertBootFlag + EXTRN @@iscmp + EXTRN _FSL_BlankCheck + EXTRN _FSL_Init + EXTRN _FSL_ModeCheck + EXTRN _FSL_ForceReset + PUBLIC _fsl_fx_MHz_u08 + PUBLIC _fsl_low_voltage_u08 + PUBLIC _firm_update + PUBLIC _firm_restore + PUBLIC _tski_mcu_reset + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_fsl_fx_MHz_u08: DB 08H ; 8 +_fsl_low_voltage_u08: DB 01H ; 1 + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +LDR_CNSL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +LDR_CODE CSEG BASE +bs_F0064: + mov a,[hl+5] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + br !_FSL_Erase ;[INF] 3, 3 +es_F0064: + +LDR_CODE CSEG BASE +bs_S0062: + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].0 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_S0062: + +LDR_CODE CSEG BASE +bs_F0063: + mov a,[hl+5] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + call !_FSL_IVerify ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0063: + +LDR_CODE CSEG BASE +bs_F0061: + movw _@RTARG0,ax ;[INF] 2, 1 + sarw ax,15 ;[INF] 2, 1 + movw _@RTARG2,ax ;[INF] 2, 1 + movw bc,_@RTARG2 ;[INF] 2, 1 + movw ax,_@RTARG0 ;[INF] 2, 1 + br !_FSL_Write ;[INF] 3, 3 +es_F0061: + +LDR_CODE CSEG BASE +bs_S0060: + mov a,[hl+5] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + shlw ax,10 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + mov a,[hl+4] ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + shlw ax,8 ;[INF] 2, 1 + addw ax,bc ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_S0060: + +; *** Sub-Routine Information *** +; +; $SUB bs_S0060 +; CODE SIZE= 15 bytes +; +; $SUB bs_F0061 +; CODE SIZE= 13 bytes +; +; $SUB bs_S0062 +; CODE SIZE= 8 bytes +; +; $SUB bs_F0063 +; CODE SIZE= 9 bytes +; +; $SUB bs_F0064 +; CODE SIZE= 7 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : 自己アップデータ +; line 3 : ======================================================== */ +; line 4 : #pragma SFR +; line 5 : #pragma di +; line 6 : #pragma ei +; line 7 : #pragma nop +; line 8 : #pragma stop +; line 9 : #pragma halt +; line 10 : +; line 11 : +; line 12 : #include "incs_loader.h" +; line 13 : +; line 14 : #include +; line 15 : #include "fsl_user.h" +; line 16 : #include "i2c_ctr.h" +; line 17 : +; line 18 : +; line 19 : +; line 20 : // ======================================================== +; line 21 : const u8 fsl_fx_MHz_u08 = 8; +; line 22 : const u8 fsl_low_voltage_u08 = 1; +; line 23 : +; line 24 : +; line 25 : // 自己フラッシュパラメータ +; line 26 : #define SAM_BLOCK_SIZE 1024 +; line 27 : #define SELF_UPDATE_BUFF_SIZE 256 +; line 28 : #define SELF_UPDATE_SPLIT_WRITE_NUM ( SAM_BLOCK_SIZE / SELF_U +; PDATE_BUFF_SIZE ) +; line 29 : #define SAM_WORD_SIZE 4 +; line 30 : +; line 31 : // ↓ブロック番号（1ブロック＝ +; 1kB） +; line 32 : #define INACTIVE_BOOTSECT_TOP 4 +; line 33 : #define FIRM_TOP 8 +; line 34 : #define FIRM_SIZE 12 +; line 35 : #define UPDATE_BLOCK_LAST ( FIRM_TOP + FIRM_SIZE - 1 +; ) +; line 36 : +; line 37 : +; line 38 : #ifdef _MCU_BSR_ +; line 39 : +; line 40 : +; line 41 : #define ACKD ACKD1 +; line 42 : #define ACKE ACKE1 +; line 43 : #define COI COI1 +; line 44 : #define IICAEN IICA1EN +; line 45 : #define IICAPR0 IICAPR10 +; line 46 : #define IICRSV IICRSV1 +; line 47 : #define IICA IICA1 +; line 48 : #define IICAIF IICAIF1 +; line 49 : #define IICAMK IICAMK1 +; line 50 : #define IICAPR1 IICAPR11 +; line 51 : #define IICCTL0 IICCTL01 +; line 52 : #define IICE IICE1 +; line 53 : #define IICF IICF1 +; line 54 : #define IICS IICS1 +; line 55 : #define IICWH IICWH1 +; line 56 : #define IICWL IICWL1 +; line 57 : #define LREL LREL1 +; line 58 : #define SPD SPD1 +; line 59 : #define SPIE SPIE1 +; line 60 : #define STCEN STCEN1 +; line 61 : #define STD STD1 +; line 62 : #define SVA SVA1 +; line 63 : #define WREL WREL1 +; line 64 : #define WTIM WTIM1 +; line 65 : #endif +; line 66 : +; line 67 : +; line 68 : +; line 69 : // ======================================================== +; line 70 : static void FSL_Open( void ); +; line 71 : static void FSL_Close( void ); +; line 72 : err firm_restore( ); +; line 73 : +; line 74 : static err my_FSL_Init(); +; line 75 : static err firm_duplicate( __far u8 * p_rom, u8 block_dest ); +; line 76 : +; line 77 : +; line 78 : +; line 79 : // ======================================================== +; line 80 : extern u16 pool[]; +; line 81 : +; line 82 : +; line 83 : // 0.D以降 新アップデータ向け +; line 84 : #define N_MGC_L 0x1FF6 +; line 85 : #define N_MGC_T 0x4FF6 +; line 86 : +; line 87 : +; line 88 : +; line 89 : /* ======================================================== +; line 90 : I2Cで受信して、 +; line 91 : 書き込み、 +; line 92 : チェックOK　→　新ファームに切り替えて再起動 +; line 93 : 　　　　NG　→　旧（現）ファームに戻して再起動 +; line 94 : （この関数からは戻りません） +; line 95 : ======================================================== */ +; line 96 : err firm_update( ) +; line 97 : { + +LDR_CODE CSEG BASE +_firm_update: +$DGL 1,35 + push hl ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_firm_update: +; line 98 : u8 target_block; +; line 99 : u8 split_write_count; // ブロックへちまちま書き込むカウ +; ンタ +; line 100 : +; line 101 : // 書き替え前準備 ///////////////////////////////////// +; line 102 : my_FSL_Init(); +$DGL 0,6 + call !_my_FSL_Init ;[INF] 3, 3 +; line 103 : +; line 104 : /* ファームのバックアップ +; line 105 : 0x2000 - 0x4FFF を +; line 106 : 0x5000 - 0x7FFF (ブロック 20 - 31) にコピー +; line 107 : */ +; line 108 : firm_duplicate( ( __far u8 * ) 0x2000, +; line 109 : ( 0x5000 / 0x0400 ) ); +$DGL 0,13 + movw ax,#014H ; 20 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + movw ax,#02000H ; 8192 ;[INF] 3, 1 + clrw bc ;[INF] 1, 1 + call !_firm_duplicate ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 110 : +; line 111 : // 全ブロック削除 ///////////////////////////////////// +; line 112 : // 電源断を判定するため、最初に全クラスタ消去する +; line 113 : //（新ファームが書かれるところに残ってる、以前のファームのフ +; ッタを消したい） +; line 114 : for( target_block = INACTIVE_BOOTSECT_TOP; +$DGL 0,18 + mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1 +?L0003: +; line 115 : target_block <= UPDATE_BLOCK_LAST; +$DGL 0,19 + mov a,[hl+5] ; target_block ;[INF] 2, 1 + cmp a,#014H ; 20 ;[INF] 2, 1 + bnc $?L0004 ;[INF] 2, 4 +; line 116 : target_block += 1 ) +; line 117 : { +??bb00_firm_update: +; line 118 : FSL_Erase( target_block ); +$DGL 0,22 + call !bs_F0064 ;[INF] 3, 3 +??eb00_firm_update: +; line 119 : } +$DGL 0,23 + inc [hl+5] ; target_block ;[INF] 3, 2 + br $?L0003 ;[INF] 2, 3 +?L0004: +; line 120 : +; line 121 : // 書き替え /////////////////////////////////////////// +; line 122 : // ●ストップコンディションが来るまで続ける +; line 123 : // ●終わったら、スタートアップルーチンに飛ぶ +; line 124 : for( target_block = INACTIVE_BOOTSECT_TOP; +$DGL 0,28 + mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1 +?L0006: +; line 125 : target_block <= UPDATE_BLOCK_LAST; +$DGL 0,29 + mov a,[hl+5] ; target_block ;[INF] 2, 1 + cmp a,#014H ; 20 ;[INF] 2, 1 + bnc $?L0007 ;[INF] 2, 4 +; line 126 : target_block += 1 ) +; line 127 : { +??bb01_firm_update: +; line 128 : // 新ファーム領域削除 +; line 129 : FSL_Erase( target_block ); +$DGL 0,33 + call !bs_F0064 ;[INF] 3, 3 +; line 130 : +; line 131 : // 分割書き込み +; line 132 : for( split_write_count = 0; +$DGL 0,36 + mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1 +?L0009: +; line 133 : ( ( split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM +; ) +; line 134 : && ( !SPD ) ); +$DGL 0,38 + mov a,[hl+4] ; split_write_count ;[INF] 2, 1 + cmp a,#04H ; 4 ;[INF] 2, 1 + bnc $?L0010 ;[INF] 2, 4 + call !bs_S0062 ;[INF] 3, 3 + bc $?L0010 ;[INF] 2, 4 +; line 135 : split_write_count += 1 ) +; line 136 : { +??bb02_firm_update: +; line 137 : u8* p_buffer = pool; +$DGL 0,41 + movw ax,#loww (_pool) ;[INF] 3, 1 + movw [hl+2],ax ; p_buffer ;[INF] 2, 1 +; line 138 : u8 buffer_fill = 0; +$DGL 0,42 + mov [hl+1],#00H ; buffer_fill,0 ;[INF] 3, 1 +; line 139 : +; line 140 : WDT_Restart( ); +$DGL 0,44 + call !_WDT_Restart ;[INF] 3, 3 +; line 141 : +; line 142 : // I2Cから書き込みデータをバッファにためる +; line 143 : do +?L0012: +; line 144 : { +??bb03_firm_update: +; line 145 : while( !IICAIF && !SPD ){;} +$DGL 0,49 + bt IF2H.3,$?L0016 ;[INF] 4, 5 + call !bs_S0062 ;[INF] 3, 3 + bnc $?L0012 ;[INF] 2, 4 +??bb04_firm_update: +??eb04_firm_update: +?L0016: +; line 146 : IICAIF = 0; +$DGL 0,50 + clr1 IF2H.3 ;[INF] 3, 2 +; line 147 : *p_buffer = IICA; +$DGL 0,51 + movw ax,[hl+2] ; p_buffer ;[INF] 2, 1 + movw de,ax ;[INF] 1, 1 + mov a,!IICA1 ;[INF] 3, 1 + mov [de],a ;[INF] 1, 1 +; line 148 : WREL = 1; +$DGL 0,52 + set1 !IICCTL01.5 ;[INF] 4, 2 +; line 149 : p_buffer += 1; +$DGL 0,53 + incw [hl+2] ; p_buffer ;[INF] 3, 2 +; line 150 : buffer_fill += 1; +$DGL 0,54 + inc [hl+1] ; buffer_fill ;[INF] 3, 2 +??eb03_firm_update: +; line 151 : } +; line 152 : while( ( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE +; ) && !SPD ); +$DGL 0,56 + mov a,[hl+1] ; buffer_fill ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0017 ;[INF] 2, 4 + call !bs_S0062 ;[INF] 3, 3 + bnc $?L0012 ;[INF] 2, 4 +?L0017: +; line 153 : +; line 154 : // 書き込み +; line 155 : // 最後だと、ゴミをパディングするが別にかまわない +; line 156 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC +; K_SIZE +; line 157 : + +; line 158 : split_write_count * +; line 159 : SELF_UPDATE_BUFF_SIZE +; ), +; line 160 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE +; / SAM_WORD_SIZE ) ) +; line 161 : +; line 162 : != FSL_OK ) +$DGL 0,66 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + call !bs_S0060 ;[INF] 3, 3 + call !bs_F0061 ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + cmp0 c ;[INF] 1, 1 + bz $?L0018 ;[INF] 2, 4 +; line 163 : { +??bb05_firm_update: +; line 164 : // 書き込み後のチェックエラー +; line 165 : // リブートののち、リストア +; line 166 : // FSL_ForceReset(); // リセット +; line 167 : FSL_SwapBootCluster( ); +$DGL 0,71 + call !_FSL_SwapBootCluster ;[INF] 3, 3 +; line 168 : // FSL_Close( ); +; line 169 : return ( ERR_ERR ); +$DGL 0,73 + onew bc ;[INF] 1, 1 + br $?L0030 ;[INF] 2, 3 +??eb05_firm_update: +; line 170 : } +?L0018: +??eb02_firm_update: +; line 171 : +; line 172 : } +$DGL 0,76 + inc [hl+4] ; split_write_count ;[INF] 3, 2 + br $?L0009 ;[INF] 2, 3 +?L0010: +; line 173 : // 1ブロック書き込み完了。内部ベリファイを行う +; line 174 : if( FSL_IVerify( target_block ) != FSL_OK ){ +$DGL 0,78 + call !bs_F0063 ;[INF] 3, 3 + skz ;[INF] 2, 1 +??bb06_firm_update: +; line 175 : // todo 再度消去→書き込み ベリファイを繰り返すだけじ +; ゃダメでした... +; line 176 : NOP(); +$DGL 0,80 + nop ;[INF] 1, 1 +??eb06_firm_update: +; line 177 : } +?L0020: +; line 178 : +; line 179 : if( SPD ) +$DGL 0,83 + call !bs_S0062 ;[INF] 3, 3 + bc $?L0007 ;[INF] 2, 4 +; line 180 : { +??bb07_firm_update: +; line 181 : break; +??eb07_firm_update: +; line 182 : } +??eb01_firm_update: +; line 183 : } +$DGL 0,87 + inc [hl+5] ; target_block ;[INF] 3, 2 + br $?L0006 ;[INF] 2, 3 +?L0007: +; line 184 : +; line 185 : LREL = 1; +$DGL 0,89 + set1 !IICCTL01.6 ;[INF] 4, 2 +; line 186 : +; line 187 : // 書き込んだファームのチェック // +; line 188 : { +??bb08_firm_update: +; line 189 : u8 i; +; line 190 : u8 comp = 0; +$DGL 0,94 + mov [hl+2],#00H ; comp,0 ;[INF] 3, 1 +; line 191 : +; line 192 : // ローダーのマジックと、本文の末尾のマジックは同じか確認 +; line 193 : for( i = 0; i < sizeof( __TIME__ ); i++ ) +$DGL 0,97 + mov [hl+3],#00H ; i,0 ;[INF] 3, 1 +?L0024: + mov a,[hl+3] ; i ;[INF] 2, 1 + cmp a,#09H ; 9 ;[INF] 2, 1 + bnc $?L0025 ;[INF] 2, 4 +; line 194 : { +??bb09_firm_update: +; line 195 : comp += ( *( u8 * ) ( N_MGC_L + i ) == *( u8 * ) ( N +; _MGC_T + i ) ) ? 0 : 1; +$DGL 0,99 + mov a,[hl+3] ; i ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + mov a,8182[bc] ;[INF] 3, 1 + mov c,a ;[INF] 1, 1 + mov a,[hl+3] ; i ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + addw ax,#04FF6H ; 20470 ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,[de] ;[INF] 1, 1 + cmp c,a ;[INF] 2, 1 + bnz $?L0027 ;[INF] 2, 4 + clrw ax ;[INF] 1, 1 + br $?L0028 ;[INF] 2, 3 +?L0027: + onew ax ;[INF] 1, 1 +?L0028: + mov a,x ;[INF] 1, 1 + add a,[hl+2] ; comp ;[INF] 2, 1 + mov [hl+2],a ; comp ;[INF] 2, 1 +??eb09_firm_update: +; line 196 : } +$DGL 0,100 + inc [hl+3] ; i ;[INF] 3, 2 + br $?L0024 ;[INF] 2, 3 +?L0025: +; line 197 : if( comp == 0 ) +$DGL 0,101 + mov a,[hl+2] ; comp ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0029 ;[INF] 2, 4 +; line 198 : { +??bb0A_firm_update: +; line 199 : FSL_InvertBootFlag( ); +$DGL 0,103 + call !_FSL_InvertBootFlag ;[INF] 3, 3 +; line 200 : FSL_SwapBootCluster( ); // リセットせずに頭から。F +; SL_Closeは不要 +$DGL 0,104 + call !_FSL_SwapBootCluster ;[INF] 3, 3 +??eb0A_firm_update: +; line 201 : // FSL_ForceReset(); // リセット +; line 202 : // FSL_SwapActiveBootCluster(); // ←スワップされてし +; まうので、続けられず暴走！ +; line 203 : // 戻ってこない // +; line 204 : } +$DGL 0,108 + br $?L0030 ;[INF] 2, 3 +?L0029: +; line 205 : else +; line 206 : { +??bb0B_firm_update: +; line 207 : // データエラー +; line 208 : // リブートののち、リストア +; line 209 : // FSL_ForceReset(); // リセット +; line 210 : FSL_SwapBootCluster( ); +$DGL 0,114 + call !_FSL_SwapBootCluster ;[INF] 3, 3 +??eb0B_firm_update: +; line 211 : // FSL_Close( ); +; line 212 : // 戻ってこない // +; line 213 : } +?L0030: +??eb08_firm_update: +; line 214 : } +; line 215 : } +$DGL 0,119 +??ef_firm_update: + addw sp,#06H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_firm_update: +; line 216 : +; line 217 : +; line 218 : +; line 219 : +; line 220 : /* ======================================================== +; line 221 : 　■ファームをバックアップ領域からリストアします。 +; line 222 : 　チェック後、最後の最後でブートスワップするので、 +; line 223 : 　ここではブートスワップは不要です。 +; line 224 : +; line 225 : ======================================================== */ +; line 226 : err firm_restore( ) +; line 227 : { +_firm_restore: +$DGL 1,99 +??bf_firm_restore: +; line 228 : my_FSL_Init(); +$DGL 0,2 + call !_my_FSL_Init ;[INF] 3, 3 +; line 229 : +; line 230 : /* ファームのリストア +; line 231 : 0x4800 - 0x7FFF (ブロック 18 - 27) から +; line 232 : 0x2000 - 0x47FF (ブロック 8 - 17) へコピー +; line 233 : */ +; line 234 : firm_duplicate( ( __far u8 * ) 0x5000, +; line 235 : FIRM_TOP ); +$DGL 0,9 + movw ax,#08H ; 8 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + movw ax,#05000H ; 20480 ;[INF] 3, 1 + clrw bc ;[INF] 1, 1 + call !_firm_duplicate ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 236 : +; line 237 : // todo +; line 238 : // 　リストア失敗したら、LEDちかちかとかさせて、サービス送 +; りにしてもらう +; line 239 : +; line 240 : // リブート +; line 241 : // スワップは不要です！ +; line 242 : FSL_SwapBootCluster(); +$DGL 0,16 + call !_FSL_SwapBootCluster ;[INF] 3, 3 +; line 243 : // FSL_ForceReset( ); +; line 244 : return ( ERR_SUCCESS ); +$DGL 0,18 + clrw bc ;[INF] 1, 1 +; line 245 : } +$DGL 0,19 +??ef_firm_restore: + ret ;[INF] 1, 6 +??ee_firm_restore: +; line 246 : +; line 247 : +; line 248 : +; line 249 : +; line 250 : // ======================================================== +; line 251 : static void FSL_Open( void ) +; line 252 : { +_FSL_Open: +$DGL 1,105 +??bf_FSL_Open: +; line 253 : /* save the configuration of the interrupt controller and se +; t */ +; line 254 : #ifdef FSL_INT_BACKUP +; line 255 : fsl_MK0L_bak_u08 = MK0L; /* if (interrupt backup required +; ) */ +; line 256 : fsl_MK0H_bak_u08 = MK0H; /* { +; */ +; line 257 : fsl_MK1L_bak_u08 = MK1L; /* +; */ +; line 258 : fsl_MK1H_bak_u08 = MK1H; /* save interrupt control +; ler */ +; line 259 : fsl_MK2L_bak_u08 = MK2L; /* configuration +; */ +; line 260 : fsl_MK2H_bak_u08 = MK2H; /* +; */ +; line 261 : MK0L = FSL_MK0L_MASK; /* +; */ +; line 262 : MK0H = FSL_MK0H_MASK; /* +; */ +; line 263 : MK1L = FSL_MK1L_MASK; /* prepare interrupt cont +; roller */ +; line 264 : MK1H = FSL_MK1H_MASK; /* for selfprogramming +; */ +; line 265 : MK2L = FSL_MK2L_MASK; /* +; */ +; line 266 : MK2H = FSL_MK2H_MASK; /* } +; */ +; line 267 : #endif +; line 268 : +; line 269 : // 何か前準備？ +; line 270 : // todo DMAを止める +; line 271 : while( DST1 ){;} +$DGL 0,20 +?L0035: + bf DRC1.0,$?L0036 ;[INF] 4, 5 +??bb00_FSL_Open: +??eb00_FSL_Open: + br $?L0035 ;[INF] 2, 3 +?L0036: +; line 272 : DEN1 = 0; +$DGL 0,21 + clr1 DRC1.7 ;[INF] 3, 2 +; line 273 : +; line 274 : MK0 = 0xFFFF; +$DGL 0,23 + movw MK0,#0FFFFH ; -1 ;[INF] 4, 1 +; line 275 : MK1 = 0xFFFF; +$DGL 0,24 + movw MK1,#0FFFFH ; -1 ;[INF] 4, 1 +; line 276 : MK2 = 0xFFFF; +$DGL 0,25 + movw MK2,#0FFFFH ; -1 ;[INF] 4, 1 +; line 277 : +; line 278 : FSL_FLMD0_HIGH; // フラッシュ書き替え許可 +$DGL 0,27 +??bb01_FSL_Open: + set1 BECTL.7 ;[INF] 3, 2 +??eb01_FSL_Open: +; line 279 : } +$DGL 0,28 +??ef_FSL_Open: + ret ;[INF] 1, 6 +??ee_FSL_Open: +; line 280 : +; line 281 : +; line 282 : +; line 283 : /*-------------------------------------------------------------- +; --------------------------------*/ +; line 284 : /* leave the "user room" and restore previous conditions +; */ +; line 285 : /*-------------------------------------------------------------- +; --------------------------------*/ +; line 286 : static void FSL_Close( void ) +; line 287 : { +_FSL_Close: +$DGL 1,119 +??bf_FSL_Close: +; line 288 : // 何か後始末？ +; line 289 : +; line 290 : FSL_FLMD0_LOW; // フラッシュライトプロテクト +$DGL 0,4 +??bb00_FSL_Close: + clr1 BECTL.7 ;[INF] 3, 2 +??eb00_FSL_Close: +; line 291 : +; line 292 : #ifdef FSL_INT_BACKUP +; line 293 : MK0L = fsl_MK0L_bak_u08; /* do{ +; */ +; line 294 : MK0H = fsl_MK0H_bak_u08; /* restore interrupt cont +; roller */ +; line 295 : MK1L = fsl_MK1L_bak_u08; /* configuration +; */ +; line 296 : MK1H = fsl_MK1H_bak_u08; /* +; */ +; line 297 : MK2L = fsl_MK2L_bak_u08; /* +; */ +; line 298 : MK2H = fsl_MK2H_bak_u08; /* } +; */ +; line 299 : #endif +; line 300 : } +$DGL 0,14 +??ef_FSL_Close: + ret ;[INF] 1, 6 +??ee_FSL_Close: +; line 301 : +; line 302 : +; line 303 : +; line 304 : /* ======================================================== +; line 305 : 　マイコン内でファームをコピーします。 +; line 306 : __far u8 * p_rom コピー元の先頭アドレス +; line 307 : block_dest コピー先の先頭ブロック +; line 308 : +; line 309 : コピー先に書けるようにmy_FSL_Initをあらかじめ実行する必要があり +; ます。 +; line 310 : ======================================================== */ +; line 311 : static err firm_duplicate( __far u8 * p_rom, +; line 312 : u8 block_dest ) +; line 313 : { +_firm_duplicate: +$DGL 1,129 + push hl ;[INF] 1, 1 + push bc ;[INF] 1, 1 + push ax ;[INF] 1, 1 + subw sp,#06H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_firm_duplicate: +; line 314 : u8 target_block; +; line 315 : u8 split_write_count; // ブロックへちまちま書き込むカウ +; ンタ +; line 316 : +; line 317 : // 書き込み先ブロックの数だけ繰り返す +; line 318 : for( target_block = block_dest; +$DGL 0,6 + mov a,[hl+16] ; block_dest ;[INF] 2, 1 + mov [hl+5],a ; target_block ;[INF] 2, 1 +?L0041: +; line 319 : target_block < block_dest + FIRM_SIZE; +$DGL 0,7 + mov a,[hl+16] ; block_dest ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + addw ax,#0CH ; 12 ;[INF] 3, 1 + movw bc,ax ;[INF] 1, 1 + mov a,[hl+5] ; target_block ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + movw _@RTARG0,ax ;[INF] 2, 1 + movw ax,bc ;[INF] 1, 1 + call !@@iscmp ;[INF] 3, 3 + bnc $?L0042 ;[INF] 2, 4 +; line 320 : target_block += 1 ) +; line 321 : { +??bb00_firm_duplicate: +; line 322 : WDT_Restart( ); +$DGL 0,10 + call !_WDT_Restart ;[INF] 3, 3 +; line 323 : // ブロック消去 +; line 324 : while( FSL_BlankCheck( target_block ) != FSL_OK ) +$DGL 0,12 +?L0044: + mov a,[hl+5] ; target_block ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + call !_FSL_BlankCheck ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + bz $?L0045 ;[INF] 2, 4 +; line 325 : { +??bb01_firm_duplicate: +; line 326 : FSL_Erase( target_block ); +$DGL 0,14 + call !bs_F0064 ;[INF] 3, 3 +??eb01_firm_duplicate: +; line 327 : } +$DGL 0,15 + br $?L0044 ;[INF] 2, 3 +?L0045: +; line 328 : +; line 329 : // 分割書き込み分繰り返す +; line 330 : for( split_write_count = 0; +$DGL 0,18 + mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1 +?L0046: +; line 331 : split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM; +$DGL 0,19 + mov a,[hl+4] ; split_write_count ;[INF] 2, 1 + cmp a,#04H ; 4 ;[INF] 2, 1 + bnc $?L0047 ;[INF] 2, 4 +; line 332 : split_write_count += 1 ) +; line 333 : { +??bb02_firm_duplicate: +; line 334 : u8 buffer_fill; +; line 335 : u8* p_buff; +; line 336 : +; line 337 : // 書き込みデータをバッファにためる +; line 338 : buffer_fill = 0; +$DGL 0,26 + mov [hl+3],#00H ; buffer_fill,0 ;[INF] 3, 1 +; line 339 : p_buff = pool; +$DGL 0,27 + movw ax,#loww (_pool) ;[INF] 3, 1 + movw [hl],ax ; p_buff ;[INF] 1, 1 +; line 340 : do +?L0049: +; line 341 : { +??bb03_firm_duplicate: +; line 342 : *p_buff = *p_rom; +$DGL 0,30 + movw ax,[hl+6] ; p_rom ;[INF] 2, 1 + movw de,ax ;[INF] 1, 1 + mov a,[hl+8] ; p_rom ;[INF] 2, 1 + mov ES,a ;[INF] 2, 1 + mov a,ES:[de] ;[INF] 2, 2 + mov c,a ;[INF] 1, 1 + movw ax,[hl] ; p_buff ;[INF] 1, 1 + movw de,ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov [de],a ;[INF] 1, 1 +; line 343 : p_rom += 1; +$DGL 0,31 + movw ax,[hl+6] ; p_rom ;[INF] 2, 1 + incw ax ;[INF] 1, 1 + movw [hl+6],ax ; p_rom ;[INF] 2, 1 +; line 344 : p_buff += 1; +$DGL 0,32 + incw [hl+0] ; p_buff ;[INF] 3, 2 +; line 345 : buffer_fill +=1; +$DGL 0,33 + inc [hl+3] ; buffer_fill ;[INF] 3, 2 +??eb03_firm_duplicate: +; line 346 : } +; line 347 : while( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE ) +; ; +$DGL 0,35 + mov a,[hl+3] ; buffer_fill ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0049 ;[INF] 2, 4 +; line 348 : +; line 349 : // 書き込み +; line 350 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC +; K_SIZE +; line 351 : + +; line 352 : split_write_count * +; line 353 : SELF_UPDATE_BUFF_SIZE +; ), +; line 354 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE +; / SAM_WORD_SIZE ) ) +; line 355 : != FSL_OK ) +$DGL 0,43 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + call !bs_S0060 ;[INF] 3, 3 + call !bs_F0061 ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + cmp0 c ;[INF] 1, 1 + bz $?L0052 ;[INF] 2, 4 +; line 356 : { +??bb04_firm_duplicate: +; line 357 : FSL_Close( ); +$DGL 0,45 + call !_FSL_Close ;[INF] 3, 3 +; line 358 : return ( ERR_ERR ); +$DGL 0,46 + onew bc ;[INF] 1, 1 + br $?L0040 ;[INF] 2, 3 +??eb04_firm_duplicate: +; line 359 : } +?L0052: +??eb02_firm_duplicate: +; line 360 : } +$DGL 0,48 + inc [hl+4] ; split_write_count ;[INF] 3, 2 + br $?L0046 ;[INF] 2, 3 +?L0047: +; line 361 : +; line 362 : // 1ブロック書き込み完了。内部電圧チェックを行う +; line 363 : while( FSL_IVerify( target_block ) != FSL_OK ){ +$DGL 0,51 + call !bs_F0063 ;[INF] 3, 3 + bnz $?L0047 ;[INF] 2, 4 +??bb05_firm_duplicate: +; line 364 : // todo +; line 365 : ; +??eb05_firm_duplicate: +; line 366 : } +??eb00_firm_duplicate: +; line 367 : } +$DGL 0,55 + inc [hl+5] ; target_block ;[INF] 3, 2 + br $?L0041 ;[INF] 2, 3 +?L0042: +; line 368 : return( ERR_SUCCESS ); +$DGL 0,56 + clrw bc ;[INF] 1, 1 +; line 369 : +; line 370 : } +?L0040: +$DGL 0,58 +??ef_firm_duplicate: + addw sp,#0AH ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_firm_duplicate: +; line 371 : +; line 372 : +; line 373 : +; line 374 : /* ======================================================== +; line 375 : ======================================================== */ +; line 376 : static err my_FSL_Init() +; line 377 : { +_my_FSL_Init: +$DGL 1,168 +??bf_my_FSL_Init: +; line 378 : RTCE = 0; +$DGL 0,2 + clr1 RTCC0.7 ;[INF] 3, 2 +; line 379 : +; line 380 : // 書き替え前準備 // +; line 381 : DI( ); +$DGL 0,5 + di ;[INF] 3, 4 +; line 382 : FSL_Open( ); // 割り込み禁止など +$DGL 0,6 + call !_FSL_Open ;[INF] 3, 3 +; line 383 : +; line 384 : FSL_Init( pool ); // ライブラリ初期化。割り込み中断考慮 +; せず +$DGL 0,8 + movw ax,#loww (_pool) ;[INF] 3, 1 + call !_FSL_Init ;[INF] 3, 3 +; line 385 : FSL_ModeCheck( ); // ライトプロテクトチェック。失敗するこ +; とを考慮せず +$DGL 0,9 + call !_FSL_ModeCheck ;[INF] 3, 3 +; line 386 : +; line 387 : return( ERR_SUCCESS ); +$DGL 0,11 + clrw bc ;[INF] 1, 1 +; line 388 : } +$DGL 0,12 +??ef_my_FSL_Init: + ret ;[INF] 1, 6 +??ee_my_FSL_Init: +; line 389 : +; line 390 : +; line 391 : task_status_immed tski_mcu_reset() +; line 392 : { +_tski_mcu_reset: +$DGL 1,174 +??bf_tski_mcu_reset: +; line 393 : // 普通に再起動 +; line 394 : my_FSL_Init(); +$DGL 0,3 + call !_my_FSL_Init ;[INF] 3, 3 +; line 395 : FSL_Close( ); +$DGL 0,4 + call !_FSL_Close ;[INF] 3, 3 +; line 396 : // FSL_SwapBootCluster(); +; line 397 : FSL_ForceReset(); // リセット +$DGL 0,6 + call !_FSL_ForceReset ;[INF] 3, 3 +; line 398 : +; line 399 : // 保険？ // +; line 400 : WDTE = 0xAA; // WDTで再起動（テスト向け） +$DGL 0,9 + mov WDTE,#0AAH ; 170 ;[INF] 3, 1 +; line 401 : return( ERR_SUCCESS ); // no reach +$DGL 0,10 + clrw bc ;[INF] 1, 1 +; line 402 : } +$DGL 0,11 +??ef_tski_mcu_reset: + ret ;[INF] 1, 6 +??ee_tski_mcu_reset: + +LDR_CODL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c +; +; $FUNC firm_update(97) +; bc=(void) +; CODE SIZE= 227 bytes, CLOCK_SIZE= 287 clocks, STACK_SIZE= 16 bytes +; +; $CALL my_FSL_Init(102) +; bc=(void) +; +; $CALL firm_duplicate(109) +; bc=(pointer:ax,bc, int:[sp+4]) +; +; $CALL FSL_Erase(118) +; bc=(unsigned int:ax) +; +; $CALL FSL_Erase(129) +; bc=(unsigned int:ax) +; +; $CALL WDT_Restart(140) +; void=(void) +; +; $CALL FSL_Write(162) +; bc=(unsigned long:ax,bc, int:[sp+4]) +; +; $CALL FSL_SwapBootCluster(167) +; void=(void) +; +; $CALL FSL_IVerify(174) +; bc=(unsigned int:ax) +; +; $CALL FSL_InvertBootFlag(199) +; bc=(void) +; +; $CALL FSL_SwapBootCluster(200) +; void=(void) +; +; $CALL FSL_SwapBootCluster(210) +; void=(void) +; +; $FUNC firm_restore(227) +; bc=(void) +; CODE SIZE= 20 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 6 bytes +; +; $CALL my_FSL_Init(228) +; bc=(void) +; +; $CALL firm_duplicate(235) +; bc=(pointer:ax,bc, int:[sp+4]) +; +; $CALL FSL_SwapBootCluster(242) +; void=(void) +; +; $FUNC FSL_Open(252) +; void=(void) +; CODE SIZE= 25 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 0 bytes +; +; $FUNC FSL_Close(287) +; void=(void) +; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes +; +; $FUNC firm_duplicate(313) +; bc=(pointer p_rom:ax,bc, unsigned char block_dest:[sp+4]) +; CODE SIZE= 136 bytes, CLOCK_SIZE= 161 clocks, STACK_SIZE= 20 bytes +; +; $CALL WDT_Restart(322) +; void=(void) +; +; $CALL FSL_BlankCheck(324) +; bc=(unsigned int:ax) +; +; $CALL FSL_Erase(326) +; bc=(unsigned int:ax) +; +; $CALL FSL_Write(355) +; bc=(unsigned long:ax,bc, int:[sp+4]) +; +; $CALL FSL_Close(357) +; void=(void) +; +; $CALL FSL_IVerify(363) +; bc=(unsigned int:ax) +; +; $FUNC my_FSL_Init(377) +; bc=(void) +; CODE SIZE= 20 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 4 bytes +; +; $CALL FSL_Open(382) +; void=(void) +; +; $CALL FSL_Init(384) +; bc=(pointer:ax) +; +; $CALL FSL_ModeCheck(385) +; bc=(void) +; +; $FUNC tski_mcu_reset(392) +; bc=(void) +; CODE SIZE= 14 bytes, CLOCK_SIZE= 17 clocks, STACK_SIZE= 4 bytes +; +; $CALL my_FSL_Init(394) +; bc=(void) +; +; $CALL FSL_Close(395) +; void=(void) +; +; $CALL FSL_ForceReset(397) +; void=(void) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/sw.asm b/branches/0.10(X3)/inter_asm/sw.asm new file mode 100644 index 0000000..1c27938 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/sw.asm @@ -0,0 +1,859 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no sw.c +; In-file : sw.c +; Asm-file : inter_asm\sw.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0CDH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, sw.c +$DGS MOD_NAM, sw, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_sw, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0CDH, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_sw, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 038H, 02H, 04BH +$DGS STA_SYM, _cnt_force_off, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 04FH +$DGS END_BLK, ??eb00_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS BEG_BLK, ??bb01_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 053H +$DGS END_BLK, ??eb01_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb02_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 057H +$DGS END_BLK, ??eb02_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS BEG_BLK, ??bb03_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 021H, 00H, 059H +$DGS BEG_BLK, ??bb04_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 028H, 00H, 05BH +$DGS BEG_BLK, ??bb05_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 061H +$DGS END_BLK, ??eb05_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 030H +$DGS END_BLK, ??eb04_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 031H +$DGS BEG_BLK, ??bb06_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 033H, 00H, 065H +$DGS END_BLK, ??eb06_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 039H +$DGS BEG_BLK, ??bb07_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03BH, 00H, 069H +$DGS END_BLK, ??eb07_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03FH +$DGS BEG_BLK, ??bb08_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 043H, 00H, 06BH +$DGS BEG_BLK, ??bb09_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 046H, 00H, 071H +$DGS END_BLK, ??eb09_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04AH +$DGS END_BLK, ??eb08_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04BH +$DGS BEG_BLK, ??bb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04DH, 00H, 075H +$DGS END_BLK, ??eb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04FH +$DGS BEG_BLK, ??bb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 053H, 00H, 079H +$DGS END_BLK, ??eb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 05FH +$DGS BEG_BLK, ??bb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 062H, 00H, 07BH +$DGS BEG_BLK, ??bb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 064H, 00H, 081H +$DGS END_BLK, ??eb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 066H +$DGS END_BLK, ??eb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 067H +$DGS BEG_BLK, ??bb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 069H, 00H, 085H +$DGS END_BLK, ??eb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 06BH +$DGS BEG_BLK, ??bb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06FH, 00H, 08BH +$DGS END_BLK, ??eb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 071H +$DGS END_BLK, ??eb03_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 074H +$DGS BEG_BLK, ??bb10_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07DH, 00H, 08DH +$DGS BEG_BLK, ??bb11_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 08FH +$DGS BEG_BLK, ??bb12_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 093H +$DGS END_BLK, ??eb12_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07EH +$DGS BEG_BLK, ??bb13_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 095H +$DGS BEG_BLK, ??bb14_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 099H +$DGS END_BLK, ??eb14_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07EH +$DGS BEG_BLK, ??bb15_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07EH, 00H, 0A1H +$DGS END_BLK, ??eb15_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07EH +$DGS END_BLK, ??eb13_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07EH +$DGS END_BLK, ??eb11_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07EH +$DGS BEG_BLK, ??bb16_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0A3H +$DGS BEG_BLK, ??bb17_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0A7H +$DGS END_BLK, ??eb17_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS BEG_BLK, ??bb18_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0A9H +$DGS BEG_BLK, ??bb19_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0ADH +$DGS END_BLK, ??eb19_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS BEG_BLK, ??bb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 080H, 00H, 0B5H +$DGS END_BLK, ??eb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS END_BLK, ??eb18_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS END_BLK, ??eb16_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 080H +$DGS BEG_BLK, ??bb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 082H, 00H, 0B7H +$DGS BEG_BLK, ??bb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 082H, 00H, 0BBH +$DGS END_BLK, ??eb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS BEG_BLK, ??bb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 082H, 00H, 0BDH +$DGS BEG_BLK, ??bb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 082H, 00H, 0C1H +$DGS END_BLK, ??eb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS BEG_BLK, ??bb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 082H, 00H, 00H +$DGS END_BLK, ??eb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS END_BLK, ??eb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS END_BLK, ??eb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 082H +$DGS END_BLK, ??eb10_tsk_sw, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 083H +$DGS END_FUN, ??ef_tsk_sw, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 086H +$DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _SW_home_count, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _SW_pow_mask, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _SW_home_mask, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _SW_wifi_mask, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _SW_HOME_n, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H + + EXTRN _set_irq + EXTRN _system_status + EXTRN _vreg_ctr + EXTBIT _renge_task_interval_run_force + PUBLIC _SW_pow_count + PUBLIC _SW_home_count + PUBLIC _SW_wifi_count + PUBLIC _SW_pow_mask + PUBLIC _SW_home_mask + PUBLIC _SW_wifi_mask + PUBLIC _SW_HOME_n + PUBLIC _tsk_sw + +@@BITS BSEG +_SW_pow_mask DBIT +_SW_home_mask DBIT +_SW_wifi_mask DBIT +_SW_HOME_n DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB 00H ; 0 + +@@INIT DSEG BASEP +?L0003: DS (1) +?L0004: DS (1) + +@@DATA DSEG BASEP +_SW_pow_count: DS (1) +_SW_home_count: DS (1) +_SW_wifi_count: DS (1) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0060: + push ax ;[INF] 1, 1 + mov x,#010H ; 16 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0060: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0060 +; CODE SIZE= 8 bytes + +; End of Sub-Routines + +; line 1 : #pragma SFR +; line 2 : #pragma NOP +; line 3 : #pragma HALT +; line 4 : #pragma STOP +; line 5 : +; line 6 : #include "incs.h" +; line 7 : +; line 8 : #include "i2c_twl.h" +; line 9 : #include "i2c_ctr.h" +; line 10 : #include "led.h" +; line 11 : #include "accero.h" +; line 12 : #include "pm.h" +; line 13 : #include "rtc.h" +; line 14 : +; line 15 : +; line 16 : +; line 17 : //========================================================= +; line 18 : #define INTERVAL_TSK_SW 16 +; line 19 : #define CLICK_THRESHOLD 1 +; line 20 : #define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW ) +; line 21 : +; line 22 : +; line 23 : +; line 24 : //========================================================= +; line 25 : u8 SW_pow_count, SW_home_count, SW_wifi_count; +; line 26 : bit SW_pow_mask, SW_home_mask, SW_wifi_mask; +; line 27 : +; line 28 : bit SW_HOME_n; +; line 29 : +; line 30 : +; line 31 : //========================================================= +; line 32 : // 押した時間を数える。押しっぱなしでも0に戻らない +; line 33 : // maskが非0の時は、一度離すまで無視する +; line 34 : #define count_sw_n( sw, counter, mask ) \ +; line 35 : { \ +; line 36 : if( sw ){ \ +; line 37 : mask = 0; \ +; line 38 : counter = 0; \ +; line 39 : }else{ \ +; line 40 : if( mask != 0 ){ \ +; line 41 : counter = 0; \ +; line 42 : }else{ \ +; line 43 : counter += 1; \ +; line 44 : if( counter == 0 ) counter = 255; \ +; line 45 : } \ +; line 46 : } \ +; line 47 : } +; line 48 : +; line 49 : +; line 50 : +; line 51 : /* ======================================================== +; line 52 : スイッチの監視 +; line 53 : 　チャタリングをはねたり、長押しや、押したトリガなどの検出など +; line 54 : ======================================================== */ +; line 55 : void tsk_sw( ) +; line 56 : { + +ROM_CODE CSEG BASE +_tsk_sw: +$DGL 1,69 + push hl ;[INF] 1, 1 +??bf_tsk_sw: +; line 57 : static u8 cnt_force_off = 0; +; line 58 : static u8 task_interval = 0; +; line 59 : +; line 60 : switch ( system_status.pwr_state ) +$DGL 0,5 + mov a,!_system_status ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + clrw bc ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0006 ;[INF] 2, 4 + subw ax,#02H ; 2 ;[INF] 3, 1 + bz $?L0007 ;[INF] 2, 4 + br $?L0005 ;[INF] 2, 3 +; line 61 : { +??bb00_tsk_sw: +; line 62 : case ( OFF_TRIG ): +?L0006: +; line 63 : SW_pow_count = 0; +$DGL 0,8 + clrb !_SW_pow_count ;[INF] 3, 1 +; line 64 : SW_wifi_count = 0; +$DGL 0,9 + clrb !_SW_wifi_count ;[INF] 3, 1 +; line 65 : SW_home_count = 0; +$DGL 0,10 + clrb !_SW_home_count ;[INF] 3, 1 +; line 66 : cnt_force_off = 0; +$DGL 0,11 + clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 +; line 67 : break; +$DGL 0,12 + br $?L0005 ;[INF] 2, 3 +; line 68 : +; line 69 : case ( ON_TRIG ): +?L0007: +; line 70 : // 電源投入 +; line 71 : SW_pow_mask = 1; +$DGL 0,16 + set1 _SW_pow_mask ;[INF] 3, 2 +; line 72 : SW_home_mask = 1; +$DGL 0,17 + set1 _SW_home_mask ;[INF] 3, 2 +; line 73 : SW_wifi_mask = 1; +$DGL 0,18 + set1 _SW_wifi_mask ;[INF] 3, 2 +; line 74 : break; +??eb00_tsk_sw: +; line 75 : } +?L0005: +; line 76 : +; line 77 : if( task_interval-- != 0 ) +$DGL 0,22 + mov a,!?L0004 ; task_interval ;[INF] 3, 1 + dec !?L0004 ; task_interval ;[INF] 3, 2 + cmp0 a ;[INF] 1, 1 + skz ;[INF] 2, 1 + br !?L0058 ;[INF] 3, 3 +; line 78 : { +??bb01_tsk_sw: +; line 79 : return; +??eb01_tsk_sw: +; line 80 : } +; line 81 : else +; line 82 : { +??bb02_tsk_sw: +; line 83 : task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TIC +; K ); +$DGL 0,28 + mov !?L0004,#08H ; task_interval,8 ;[INF] 4, 1 +??eb02_tsk_sw: +; line 84 : } +; line 85 : +; line 86 : +; line 87 : switch ( system_status.pwr_state ) +$DGL 0,32 + mov a,!_system_status ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + onew bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,bc ;[INF] 1, 1 + bz $?L0013 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bz $?L0013 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + sknh ;[INF] 2, 1 + br !?L0012 ;[INF] 3, 3 +; line 88 : { +??bb03_tsk_sw: +; line 89 : case ( ON ): +?L0013: +; line 90 : case ( SLEEP ): +; line 91 : case ( BT_CHARGE ): +; line 92 : case ( OFF ): +; line 93 : // 電源スイッチの監視 // +; line 94 : if( SW_POW_n ) +$DGL 0,39 + bf P7.3,$?L0016 ;[INF] 4, 5 +; line 95 : { +??bb04_tsk_sw: +; line 96 : if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_c +; ount <= HOLD_THREASHOLD ) ) +$DGL 0,41 + cmp !_SW_pow_count,#02H ; 2 ;[INF] 4, 1 + bc $?L0022 ;[INF] 2, 4 + cmp !_SW_pow_count,#026H ; 38 ;[INF] 4, 1 + bnc $?L0022 ;[INF] 2, 4 +; line 97 : { +??bb05_tsk_sw: +; line 98 : #ifdef _SW_HOME_ENABLE_ +; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK ); +$DGL 0,44 + onew ax ;[INF] 1, 1 + call !bs_F0060 ;[INF] 3, 3 +??eb05_tsk_sw: +; line 100 : #else +; line 101 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); +; line 102 : #endif +; line 103 : } +; line 104 : } +$DGL 0,49 +??eb04_tsk_sw: + br $?L0022 ;[INF] 2, 3 +?L0016: +; line 105 : else if( SW_pow_count == HOLD_THREASHOLD ) +$DGL 0,50 + cmp !_SW_pow_count,#025H ; 37 ;[INF] 4, 1 + bnz $?L0020 ;[INF] 2, 4 +; line 106 : { +??bb06_tsk_sw: +; line 107 : #ifdef _SW_HOME_ENABLE_ +; line 108 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD ); +$DGL 0,53 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + call !bs_F0060 ;[INF] 3, 3 +??eb06_tsk_sw: +; line 109 : #else +; line 110 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); +; line 111 : #endif +; line 112 : } +$DGL 0,57 + br $?L0022 ;[INF] 2, 3 +?L0020: +; line 113 : else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) ) +$DGL 0,58 + cmp !_SW_pow_count,#094H ; 148 ;[INF] 4, 1 + bnz $?L0022 ;[INF] 2, 4 +; line 114 : { // todo +??bb07_tsk_sw: +; line 115 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED; +$DGL 0,60 + mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 +; line 116 : system_status.pwr_state = OFF_TRIG; +$DGL 0,61 + clrb !_system_status ;[INF] 3, 1 +; line 117 : renge_task_interval_run_force = 1; +$DGL 0,62 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +??eb07_tsk_sw: +; line 118 : } +?L0022: +; line 119 : +; line 120 : // 電源OFF割り込みを入れたが… +; line 121 : if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0 +; ) +$DGL 0,66 + mov a,!_vreg_ctr+16 ;[INF] 3, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0024 ;[INF] 2, 4 +; line 122 : { +??bb08_tsk_sw: +; line 123 : cnt_force_off += 1; +$DGL 0,68 + inc !?L0003 ; cnt_force_off ;[INF] 3, 2 +; line 124 : if( cnt_force_off >= 13 ) +$DGL 0,69 + cmp !?L0003,#0DH ; cnt_force_off,13 ;[INF] 4, 1 + bc $?L0025 ;[INF] 2, 4 +; line 125 : { // …返事がない。強制的に切る。 +??bb09_tsk_sw: +; line 126 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RE +; D; +$DGL 0,71 + mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 +; line 127 : system_status.pwr_state = OFF_TRIG; +$DGL 0,72 + clrb !_system_status ;[INF] 3, 1 +; line 128 : renge_task_interval_run_force = 1; +$DGL 0,73 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +??eb09_tsk_sw: +; line 129 : } +; line 130 : } +$DGL 0,75 +??eb08_tsk_sw: + br $?L0025 ;[INF] 2, 3 +?L0024: +; line 131 : else +; line 132 : { +??bb0A_tsk_sw: +; line 133 : cnt_force_off = 0; +$DGL 0,78 + clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 +??eb0A_tsk_sw: +; line 134 : } +?L0025: +; line 135 : +; line 136 : // HOME スイッチ // +; line 137 : switch( system_status.model ) +$DGL 0,82 + mov a,!_system_status+3 ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0029 ;[INF] 2, 4 + decw ax ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + bnh $?L0030 ;[INF] 3, 4 + br $?L0031 ;[INF] 2, 3 +; line 138 : { +??bb0B_tsk_sw: +; line 139 : #ifdef _MODEL_CTR_ +; line 140 : case( MODEL_JIKKI ): +?L0029: +; line 141 : SW_HOME_n = SW_HOME_n_JIKKI; +$DGL 0,86 + movw hl,#0510H ; 1296 ;[INF] 3, 1 + mov1 CY,[hl].4 ;[INF] 2, 1 + mov1 _SW_HOME_n,CY ;[INF] 3, 2 +; line 142 : break; +$DGL 0,87 + br $?L0028 ;[INF] 2, 3 +; line 143 : #endif +; line 144 : case( MODEL_TS_BOARD ): +?L0030: +; line 145 : case( MODEL_SHIROBAKO ): +; line 146 : SW_HOME_n = SW_HOME_n_TSBOARD; +$DGL 0,91 + mov1 CY,P2.0 ;[INF] 3, 1 + mov1 _SW_HOME_n,CY ;[INF] 3, 2 +; line 147 : break; +$DGL 0,92 + br $?L0028 ;[INF] 2, 3 +; line 148 : default: +?L0031: +; line 149 : SW_HOME_n = 1; +$DGL 0,94 + set1 _SW_HOME_n ;[INF] 3, 2 +??eb0B_tsk_sw: +; line 150 : } +?L0028: +; line 151 : +; line 152 : if( SW_HOME_n ) +$DGL 0,97 + bf _SW_HOME_n,$?L0034 ;[INF] 4, 5 +; line 153 : { +??bb0C_tsk_sw: +; line 154 : if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home +; _count <= HOLD_THREASHOLD ) ) +$DGL 0,99 + cmp !_SW_home_count,#02H ; 2 ;[INF] 4, 1 + bc $?L0038 ;[INF] 2, 4 + cmp !_SW_home_count,#026H ; 38 ;[INF] 4, 1 + bnc $?L0038 ;[INF] 2, 4 +; line 155 : { +??bb0D_tsk_sw: +; line 156 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); +$DGL 0,101 + movw ax,#04H ; 4 ;[INF] 3, 1 + call !bs_F0060 ;[INF] 3, 3 +??eb0D_tsk_sw: +; line 157 : } +; line 158 : } +$DGL 0,103 +??eb0C_tsk_sw: + br $?L0038 ;[INF] 2, 3 +?L0034: +; line 159 : else if( SW_home_count == HOLD_THREASHOLD ) +$DGL 0,104 + cmp !_SW_home_count,#025H ; 37 ;[INF] 4, 1 + bnz $?L0038 ;[INF] 2, 4 +; line 160 : { +??bb0E_tsk_sw: +; line 161 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); +$DGL 0,106 + movw ax,#08H ; 8 ;[INF] 3, 1 + call !bs_F0060 ;[INF] 3, 3 +??eb0E_tsk_sw: +; line 162 : } +?L0038: +; line 163 : +; line 164 : // wifi sw // +; line 165 : if( SW_wifi_count == CLICK_THRESHOLD ) +$DGL 0,110 + cmp !_SW_wifi_count,#01H ; 1 ;[INF] 4, 1 + bnz $?L0012 ;[INF] 2, 4 +; line 166 : { +??bb0F_tsk_sw: +; line 167 : set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK ); +$DGL 0,112 + movw ax,#010H ; 16 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb0F_tsk_sw: +; line 168 : } +; line 169 : +; line 170 : break; +??eb03_tsk_sw: +; line 171 : } +?L0012: +; line 172 : +; line 173 : // ボタン押し時間のカウント +; line 174 : /* +; line 175 : if( ( system_status.pwr_state == ON ) +; line 176 : || ( system_status.pwr_state == OFF ) +; line 177 : || ( system_status.pwr_state == BT_CHARGE ) ) +; line 178 : */ +; line 179 : +; line 180 : { +??bb10_tsk_sw: +; line 181 : count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask ); +$DGL 0,126 +??bb11_tsk_sw: + bf P7.3,$?L0042 ;[INF] 4, 5 +??bb12_tsk_sw: + clr1 _SW_pow_mask ;[INF] 3, 2 + clrb !_SW_pow_count ;[INF] 3, 1 +??eb12_tsk_sw: + br $?L0046 ;[INF] 2, 3 +?L0042: +??bb13_tsk_sw: + bf _SW_pow_mask,$?L0044 ;[INF] 4, 5 +??bb14_tsk_sw: + clrb !_SW_pow_count ;[INF] 3, 1 +??eb14_tsk_sw: + br $?L0046 ;[INF] 2, 3 +?L0044: +??bb15_tsk_sw: + inc !_SW_pow_count ;[INF] 3, 2 + cmp0 !_SW_pow_count ;[INF] 3, 1 + sknz ;[INF] 2, 1 + mov !_SW_pow_count,#0FFH ; 255 ;[INF] 4, 1 +?L0046: +??eb15_tsk_sw: +??eb13_tsk_sw: +??eb11_tsk_sw: +; line 182 : #ifdef _SW_HOME_ENABLE_ +; line 183 : count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask ); +$DGL 0,128 +??bb16_tsk_sw: + bf _SW_HOME_n,$?L0048 ;[INF] 4, 5 +??bb17_tsk_sw: + clr1 _SW_home_mask ;[INF] 3, 2 + clrb !_SW_home_count ;[INF] 3, 1 +??eb17_tsk_sw: + br $?L0052 ;[INF] 2, 3 +?L0048: +??bb18_tsk_sw: + bf _SW_home_mask,$?L0050 ;[INF] 4, 5 +??bb19_tsk_sw: + clrb !_SW_home_count ;[INF] 3, 1 +??eb19_tsk_sw: + br $?L0052 ;[INF] 2, 3 +?L0050: +??bb1A_tsk_sw: + inc !_SW_home_count ;[INF] 3, 2 + cmp0 !_SW_home_count ;[INF] 3, 1 + sknz ;[INF] 2, 1 + mov !_SW_home_count,#0FFH ; 255 ;[INF] 4, 1 +?L0052: +??eb1A_tsk_sw: +??eb18_tsk_sw: +??eb16_tsk_sw: +; line 184 : #endif +; line 185 : count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask ); +$DGL 0,130 +??bb1B_tsk_sw: + bf P7.4,$?L0054 ;[INF] 4, 5 +??bb1C_tsk_sw: + clr1 _SW_wifi_mask ;[INF] 3, 2 + clrb !_SW_wifi_count ;[INF] 3, 1 +??eb1C_tsk_sw: + br $?L0058 ;[INF] 2, 3 +?L0054: +??bb1D_tsk_sw: + bf _SW_wifi_mask,$?L0056 ;[INF] 4, 5 +??bb1E_tsk_sw: + clrb !_SW_wifi_count ;[INF] 3, 1 +??eb1E_tsk_sw: + br $?L0058 ;[INF] 2, 3 +?L0056: +??bb1F_tsk_sw: + inc !_SW_wifi_count ;[INF] 3, 2 + cmp0 !_SW_wifi_count ;[INF] 3, 1 + sknz ;[INF] 2, 1 + mov !_SW_wifi_count,#0FFH ; 255 ;[INF] 4, 1 +?L0058: +??eb1F_tsk_sw: +??eb1D_tsk_sw: +??eb1B_tsk_sw: +??eb10_tsk_sw: +; line 186 : } +; line 187 : +; line 188 : return; +; line 189 : } +$DGL 0,134 +??ef_tsk_sw: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_sw: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c +; +; $FUNC tsk_sw(56) +; void=(void) +; CODE SIZE= 351 bytes, CLOCK_SIZE= 329 clocks, STACK_SIZE= 12 bytes +; +; $CALL set_irq(99) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(108) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(156) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(161) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(167) +; void=(int:ax, int:[sp+4]) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/task_debug.asm b/branches/0.10(X3)/inter_asm/task_debug.asm new file mode 100644 index 0000000..f032482 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/task_debug.asm @@ -0,0 +1,369 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_debug.c +; In-file : task_debug.c +; Asm-file : inter_asm\task_debug.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 05CH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, task_debug.c +$DGS MOD_NAM, task_debug, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_debug, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 050H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_debug, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 010H, 02H, 04AH +$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS STA_SYM, _count, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_debug, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 00H +$DGS END_BLK, ??eb00_tsk_debug, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS END_FUN, ??ef_tsk_debug, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 017H +$DGS GLV_SYM, _tsk_debug2, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 05CH, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_debug2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02BH, 04H, 056H +$DGS AUT_VAR, _str, 00H, 0FFFFH, 0CH, 01H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 00H +$DGS END_BLK, ??eb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS END_FUN, ??ef_tsk_debug2, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01EH +$DGS GLV_SYM, _temp_debug_3, U, U, 0CH, 026H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _system_status + EXTRN _vreg_ctr + EXTRN _iic_mcu_write + PUBLIC _tsk_debug + PUBLIC _temp_debug_3 + PUBLIC _tsk_debug2 + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0003: DS (1) + DS (1) + +@@DATA DSEG BASEP +?L0004: DS (1) +_temp_debug_3: DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; line 1 : #pragma SFR +; line 2 : #pragma NOP +; line 3 : #pragma HALT +; line 4 : #pragma STOP +; line 5 : +; line 6 : #include "incs.h" +; line 7 : #include "renge.h" +; line 8 : #include "pm.h" +; line 9 : +; line 10 : #include "accero.h" +; line 11 : +; line 12 : +; line 13 : /* ======================================================== +; line 14 : ======================================================== */ +; line 15 : void tsk_debug( ) +; line 16 : { + +ROM_CODE CSEG BASE +_tsk_debug: +$DGL 1,67 + push hl ;[INF] 1, 1 +??bf_tsk_debug: +; line 17 : u8 temp; +; line 18 : static u8 count = 0; +; line 19 : static u8 task_interval; +; line 20 : +; line 21 : if( system_status.pwr_state == ON_TRIG ){ +$DGL 0,6 + cmp !_system_status,#02H ; 2 ;[INF] 4, 1 +??bb00_tsk_debug: +??eb00_tsk_debug: +; line 22 : +; line 23 : #ifdef _MODEL_WM0_ +; line 24 : PM_CHG_TIMEOUT_DISABLE(); // +; /WL_RST に配線されています +; line 25 : #endif +; line 26 : #ifndef _MODEL_CTR_ +; line 27 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 ); // +; ACR←0x80 揮発モードへ +; line 28 : #endif +; line 29 : +; line 30 : /* +; line 31 : temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_ +; DO ); +; line 32 : count += 1; +; line 33 : iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, co +; unt ); +; line 34 : iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count ); +; line 35 : */ +; line 36 : } +; line 37 : return; +; line 38 : } +$DGL 0,23 +??ef_tsk_debug: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_debug: +; line 39 : +; line 40 : u8 temp_debug_3; +; line 41 : +; line 42 : void tsk_debug2( ) +; line 43 : { +_tsk_debug2: +$DGL 1,80 + push hl ;[INF] 1, 1 + subw sp,#04H ;[INF] 2, 1 + movw hl,sp ;[INF] 3, 1 +??bf_tsk_debug2: +; line 44 : u8 str[4]; +; line 45 : +; line 46 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr +; _state == SLEEP ) ) +$DGL 0,4 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bz $?L0011 ;[INF] 2, 4 + cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + bnz $?L0009 ;[INF] 2, 4 +?L0011: +; line 47 : { +??bb00_tsk_debug2: +; line 48 : /* +; line 49 : str[3] = vreg_ctr[ VREG_C_FREE0 ]; +; line 50 : str[2] = vreg_ctr[ VREG_C_FREE1 ]; +; line 51 : str[1] = vreg_ctr[ VREG_C_STATUS ]; +; line 52 : str[0] = vreg_ctr[ VREG_C_RTC_SEC ]; +; line 53 : */ +; line 54 : str[3] = vreg_ctr[ VREG_C_SND_VOL ]; +$DGL 0,12 + mov a,!_vreg_ctr+9 ;[INF] 3, 1 + mov [hl+3],a ; str ;[INF] 2, 1 +; line 55 : str[2] = vreg_ctr[ VREG_C_TUNE ]; +$DGL 0,13 + mov a,!_vreg_ctr+8 ;[INF] 3, 1 + mov [hl+2],a ; str ;[INF] 2, 1 +; line 56 : str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ]; +$DGL 0,14 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + mov [hl+1],a ; str ;[INF] 2, 1 +; line 57 : str[0] = SEC; +$DGL 0,15 + mov a,SEC ;[INF] 2, 1 + mov [hl],a ; str ;[INF] 1, 1 +; line 58 : +; line 59 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR +; EG_C_IRQ1 ] ); +; line 60 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura ); +; line 61 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR +; EG_C_SND_VOL ] ); +; line 62 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR +; EG_TUNE ] ); +; line 63 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR +; EG_C_ACC_ZH ] ); +; line 64 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VR +; EG_C_TUNE ] ); +; line 65 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR +; EG_C_SND_VOL ] ); +; line 66 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR +; EG_C_STATUS ] ); +; line 67 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR +; EG_C_ACC_ZH ] ); +; line 68 : +; line 69 : iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] ); +$DGL 0,27 + movw ax,hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw ax,#04H ; 4 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + clrw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#044H ; 68 ;[INF] 2, 1 + call !_iic_mcu_write ;[INF] 3, 3 + addw sp,#06H ; 6 ;[INF] 2, 1 +??eb00_tsk_debug2: +; line 70 : } +?L0009: +; line 71 : return; +; line 72 : } +$DGL 0,30 +??ef_tsk_debug2: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_debug2: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c +; +; $FUNC tsk_debug(16) +; void=(void) +; CODE SIZE= 7 bytes, CLOCK_SIZE= 9 clocks, STACK_SIZE= 2 bytes +; +; $FUNC tsk_debug2(43) +; void=(void) +; CODE SIZE= 55 bytes, CLOCK_SIZE= 40 clocks, STACK_SIZE= 16 bytes +; +; $CALL iic_mcu_write(69) +; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/task_misc.asm b/branches/0.10(X3)/inter_asm/task_misc.asm new file mode 100644 index 0000000..7b0cd98 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/task_misc.asm @@ -0,0 +1,1121 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_misc.c +; In-file : task_misc.c +; Asm-file : inter_asm\task_misc.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0EAH, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, task_misc.c +$DGS MOD_NAM, task_misc, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 047H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 041H, 01H +$DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 098H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 037H, 02H, 052H +$DGS STA_SYM, _interval_task_misc_stat, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS STA_SYM, _state_old, ?L0004, U, 0CH, 03H, 00H, 00H +$DGS REG_VAR, _diff, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 056H +$DGS END_BLK, ??eb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0FH, 00H, 05AH +$DGS END_BLK, ??eb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 05CH +$DGS BEG_BLK, ??bb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 060H +$DGS END_BLK, ??eb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 066H +$DGS END_BLK, ??eb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS END_BLK, ??eb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 068H +$DGS BEG_BLK, ??bb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 020H, 00H, 06AH +$DGS BEG_BLK, ??bb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 024H, 00H, 06CH +$DGS BEG_BLK, ??bb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 027H, 00H, 070H +$DGS END_BLK, ??eb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 029H +$DGS BEG_BLK, ??bb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02BH, 00H, 076H +$DGS END_BLK, ??eb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02DH +$DGS END_BLK, ??eb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02EH +$DGS BEG_BLK, ??bb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 031H, 00H, 078H +$DGS BEG_BLK, ??bb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 034H, 00H, 07CH +$DGS END_BLK, ??eb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 036H +$DGS BEG_BLK, ??bb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 038H, 00H, 084H +$DGS END_BLK, ??eb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03AH +$DGS END_BLK, ??eb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03BH +$DGS END_BLK, ??eb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03CH +$DGS BEG_BLK, ??bb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 049H, 00H, 086H +$DGS BEG_BLK, ??bb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04BH, 00H, 088H +$DGS BEG_BLK, ??bb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04CH, 00H, 090H +$DGS END_BLK, ??eb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04EH +$DGS END_BLK, ??eb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04FH +$DGS END_BLK, ??eb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 050H +$DGS BEG_BLK, ??bb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 054H, 00H, 00H +$DGS END_BLK, ??eb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 057H +$DGS END_BLK, ??eb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 058H +$DGS END_FUN, ??ef_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 05AH +$DGS GLV_SYM, _do_command0, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0CEH, 00H, 00H +$DGS BEG_FUN, ??bf_do_command0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 09FH, 00H, 09CH +$DGS BEG_BLK, ??bb00_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 09EH +$DGS BEG_BLK, ??bb01_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0A2H +$DGS END_BLK, ??eb01_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb02_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 0A4H +$DGS BEG_BLK, ??bb03_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0CH, 00H, 0A6H +$DGS BEG_BLK, ??bb04_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 0AAH +$DGS END_BLK, ??eb04_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS BEG_BLK, ??bb05_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0FH, 00H, 0B0H +$DGS END_BLK, ??eb05_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS END_BLK, ??eb03_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS BEG_BLK, ??bb06_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 0B2H +$DGS BEG_BLK, ??bb07_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 0B8H +$DGS END_BLK, ??eb07_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS END_BLK, ??eb06_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 014H +$DGS BEG_BLK, ??bb08_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 016H, 00H, 0BAH +$DGS BEG_BLK, ??bb09_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 0C0H +$DGS END_BLK, ??eb09_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 017H +$DGS END_BLK, ??eb08_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS BEG_BLK, ??bb0A_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01AH, 00H, 0C4H +$DGS END_BLK, ??eb0A_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01AH +$DGS BEG_BLK, ??bb0B_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 00H +$DGS END_BLK, ??eb0B_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS END_BLK, ??eb02_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 025H +$DGS END_BLK, ??eb00_do_command0, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 026H +$DGS END_FUN, ??ef_do_command0, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02AH +$DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0EAH, 00H, 00H +$DGS BEG_FUN, ??bf_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0D9H, 02H, 0D3H +$DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0D7H +$DGS END_BLK, ??eb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 0DBH +$DGS END_BLK, ??eb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 0DFH +$DGS END_BLK, ??eb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS BEG_BLK, ??bb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 0E3H +$DGS END_BLK, ??eb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS BEG_BLK, ??bb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 00H +$DGS END_BLK, ??eb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 031H +$DGS LAB_SYM, _end, ?L0046, U, 00H, 06H, 00H, 00H +$DGS END_FUN, ??ef_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03AH +$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _iic_mcu_read_a_byte + EXTRN _vreg_ctr + EXTRN _system_status + EXTRN _set_irq + EXTRN _tsk_cbk_accero + EXTRN _renge_task_immed_add + EXTRN _ntr_pmic_comm + EXTRN _iic_mcu_write_a_byte + EXTRN _wait_ms + EXTRN _iic_burst_state + EXTRN _get_adc + PUBLIC _tsk_misc_stat + PUBLIC _do_command0 + PUBLIC _tski_mcu_info_read + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0003: DS (1) + DS (1) + +@@DATA DSEG BASEP +?L0004: DS (1) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0060: + push ax ;[INF] 1, 1 + mov x,#06CH ; 108 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov !IICA1,a ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_F0060: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0060 +; CODE SIZE= 12 bytes + +; End of Sub-Routines + +; line 1 : #pragma SFR +; line 2 : #pragma NOP +; line 3 : #pragma HALT +; line 4 : #pragma STOP +; line 5 : +; line 6 : #include "incs.h" +; line 7 : #include "renge.h" +; line 8 : #include "pm.h" +; line 9 : +; line 10 : #include "accero.h" +; line 11 : #include "adc.h" +; line 12 : #include "i2c_mcu.h" +; line 13 : +; line 14 : +; line 15 : #ifdef _MCU_BSR_ +; line 16 : #define ACKD ACKD1 +; line 17 : #define ACKE ACKE1 +; line 18 : #define COI COI1 +; line 19 : #define IICAEN IICA1EN +; line 20 : #define IICRSV IICRSV1 +; line 21 : #define IICA IICA1 +; line 22 : #define IICAIF IICAIF1 +; line 23 : #define IICAMK IICAMK1 +; line 24 : #define IICAPR0 IICAPR11 +; line 25 : #define IICAPR1 IICAPR01 +; line 26 : #define IICCTL0 IICCTL10 +; line 27 : #define IICE IICE1 +; line 28 : #define IICF IICF1 +; line 29 : #define IICS IICS1 +; line 30 : #define IICWH IICWH1 +; line 31 : #define IICWL IICWL1 +; line 32 : #define LREL LREL1 +; line 33 : #define SPD SPD1 +; line 34 : #define SPIE SPIE1 +; line 35 : #define STCEN STCEN1 +; line 36 : #define STD STD1 +; line 37 : #define SVA SVA1 +; line 38 : #define WREL WREL1 +; line 39 : #define WTIM WTIM1 +; line 40 : #define TRC TRC1 +; line 41 : #define SMC SMC1 +; line 42 : #define DFC DFC1 +; line 43 : #endif +; line 44 : +; line 45 : +; line 46 : +; line 47 : // ======================================================== +; line 48 : #define INTERVAL_TSK_MISC_STAT 4 +; line 49 : +; line 50 : +; line 51 : /* ======================================================== +; line 52 : ステータスレジスタなど +; line 53 : ======================================================== */ +; line 54 : void tsk_misc_stat( ) +; line 55 : { + +ROM_CODE CSEG BASE +_tsk_misc_stat: +$DGL 1,75 + push hl ;[INF] 1, 1 +??bf_tsk_misc_stat: +; line 56 : static u8 interval_task_misc_stat = 0; +; line 57 : static u8 state_old; // ステータス変化検出→割り込み +; の為 +; line 58 : #ifdef _BL_INDEPENDENT_ +; line 59 : static u8 state2_old; +; line 60 : #endif +; line 61 : u8 diff; +; line 62 : +; line 63 : if( interval_task_misc_stat != 0 ) +$DGL 0,9 + cmp0 !?L0003 ; interval_task_misc_stat ;[INF] 3, 1 + bz $?L0005 ;[INF] 2, 4 +; line 64 : { +??bb00_tsk_misc_stat: +; line 65 : interval_task_misc_stat -= 1; +$DGL 0,11 + dec !?L0003 ; interval_task_misc_stat ;[INF] 3, 2 +; line 66 : return; +$DGL 0,12 + br !?L0028 ;[INF] 3, 3 +??eb00_tsk_misc_stat: +; line 67 : } +?L0005: +; line 68 : else +; line 69 : { +??bb01_tsk_misc_stat: +; line 70 : interval_task_misc_stat = ( INTERVAL_TSK_MISC_STAT / SYS +; _INTERVAL_TICK ); +$DGL 0,16 + mov !?L0003,#02H ; interval_task_misc_stat,2 ;[INF] 4, 1 +??eb01_tsk_misc_stat: +; line 71 : } +; line 72 : +; line 73 : set_bit( SHELL_OPEN, vreg_ctr[VREG_C_STATUS], REG_BIT_ST_SHE +; LL_OPEN ); +$DGL 0,19 +??bb02_tsk_misc_stat: + bf P7.1,$?L0007 ;[INF] 4, 5 +??bb03_tsk_misc_stat: + set1 !_vreg_ctr+15.1 ;[INF] 4, 2 +??eb03_tsk_misc_stat: + br $?L0008 ;[INF] 2, 3 +?L0007: +??bb04_tsk_misc_stat: + clr1 !_vreg_ctr+15.1 ;[INF] 4, 2 +??eb04_tsk_misc_stat: +?L0008: +??eb02_tsk_misc_stat: +; line 74 : +; line 75 : // ステータスレジスタ関係 → 割り込み // +; line 76 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr +; _state == SLEEP ) ) +$DGL 0,22 + cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + bz $?L0011 ;[INF] 2, 4 + cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + skz ;[INF] 2, 1 + br !?L0028 ;[INF] 3, 3 +?L0011: +; line 77 : { +??bb05_tsk_misc_stat: +; line 78 : // pm.c で、その場で行います。 +; line 79 : // REG_BIT_LCD_ON/OFF +; line 80 : // REG_BIT_BL_ON/OFF +; line 81 : // REG_BIT_BT_DC_CONNECT/DISC +; line 82 : +; line 83 : +; line 84 : diff = vreg_ctr[VREG_C_STATUS] ^ state_old; +$DGL 0,30 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + xor a,!?L0004 ; state_old ;[INF] 3, 1 + mov l,a ;[INF] 1, 1 +; line 85 : if( diff != 0 ) +$DGL 0,31 + cmp0 a ;[INF] 1, 1 + bz $?L0021 ;[INF] 2, 4 +; line 86 : { +??bb06_tsk_misc_stat: +; line 87 : state_old = vreg_ctr[VREG_C_STATUS]; +$DGL 0,33 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + mov !?L0004,a ; state_old ;[INF] 3, 1 +; line 88 : +; line 89 : if( diff & REG_BIT_BATT_CHARGE ) +$DGL 0,35 + mov a,l ;[INF] 1, 1 + and a,#010H ; 16 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0017 ;[INF] 2, 4 +; line 90 : { +??bb07_tsk_misc_stat: +; line 91 : // 充電状態に以下略 +; line 92 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARG +; E ) +$DGL 0,38 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + and a,#010H ; 16 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0016 ;[INF] 2, 4 +; line 93 : { +??bb08_tsk_misc_stat: +; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_START ) +; ; +$DGL 0,40 + movw ax,#080H ; 128 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#011H ; 17 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb08_tsk_misc_stat: +; line 95 : } +$DGL 0,41 + br $?L0017 ;[INF] 2, 3 +?L0016: +; line 96 : else +; line 97 : { +??bb09_tsk_misc_stat: +; line 98 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_STOP ); +$DGL 0,44 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#011H ; 17 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb09_tsk_misc_stat: +; line 99 : } +?L0017: +??eb07_tsk_misc_stat: +; line 100 : } +; line 101 : +; line 102 : if( diff & REG_BIT_ST_SHELL_OPEN ) +$DGL 0,48 + mov a,l ;[INF] 1, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0021 ;[INF] 2, 4 +; line 103 : { +??bb0A_tsk_misc_stat: +; line 104 : // 蓋の開け閉め +; line 105 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_O +; PEN ) +$DGL 0,51 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0020 ;[INF] 2, 4 +; line 106 : { +??bb0B_tsk_misc_stat: +; line 107 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_OPEN ); +$DGL 0,53 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#010H ; 16 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb0B_tsk_misc_stat: +; line 108 : } +$DGL 0,54 + br $?L0021 ;[INF] 2, 3 +?L0020: +; line 109 : else +; line 110 : { +??bb0C_tsk_misc_stat: +; line 111 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_CLOSE ); +$DGL 0,57 + movw ax,#020H ; 32 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#010H ; 16 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb0C_tsk_misc_stat: +; line 112 : } +?L0021: +??eb0A_tsk_misc_stat: +; line 113 : } +??eb06_tsk_misc_stat: +; line 114 : } +; line 115 : +; line 116 : +; line 117 : //#ifdef _MCU_KE3_ +; line 118 : // KE3では必須です。 +; line 119 : /* ===================================================== +; === +; line 120 : 加速度センサ割り込みピンがオリジナルマイコンには無いの +; で +; line 121 : ポーリングする。 +; line 122 : 歩数計用 +; line 123 : BSRマイコンはaccero.cで割り込みルーチンからタスク登録 +; します。 +; line 124 : ===================================================== +; === */ +; line 125 : // 割り込みの取りこぼし？ +; line 126 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) +$DGL 0,72 + mov a,!_vreg_ctr+64 ;[INF] 3, 1 + and a,#03H ; 3 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0026 ;[INF] 2, 4 +; line 127 : { +??bb0D_tsk_misc_stat: +; line 128 : if( ACC_VALID ) +$DGL 0,74 + push hl ;[INF] 1, 1 + movw hl,#0510H ; 1296 ;[INF] 3, 1 + mov1 CY,[hl].5 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bnc $?L0026 ;[INF] 2, 4 +; line 129 : { +??bb0E_tsk_misc_stat: +; line 130 : if( renge_task_immed_add( tsk_cbk_accero ) == ER +; R_SUCCESS ){ +$DGL 0,76 + movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + sknz ;[INF] 2, 1 +??bb0F_tsk_misc_stat: +; line 131 : NOP(); +$DGL 0,77 + nop ;[INF] 1, 1 +??eb0F_tsk_misc_stat: +; line 132 : } +?L0026: +??eb0E_tsk_misc_stat: +; line 133 : } +??eb0D_tsk_misc_stat: +; line 134 : } +; line 135 : //#endif +; line 136 : +; line 137 : // 割り込みの取りこぼし？ +; line 138 : if( !PM_IRQ_n ){ +$DGL 0,84 + bt P7.2,$?L0028 ;[INF] 4, 5 +??bb10_tsk_misc_stat: +; line 139 : renge_task_immed_add( ntr_pmic_comm ); +$DGL 0,85 + movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 140 : NOP(); +$DGL 0,86 + nop ;[INF] 1, 1 +??eb10_tsk_misc_stat: +; line 141 : } +?L0028: +??eb05_tsk_misc_stat: +; line 142 : } +; line 143 : return; +; line 144 : } +$DGL 0,90 +??ef_tsk_misc_stat: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tsk_misc_stat: +; line 145 : +; line 146 : +; line 147 : +; line 148 : +; line 149 : +; line 150 : /* ======================================================== +; line 151 : 逐一起動タスク +; line 152 : ======================================================== */ +; line 153 : +; line 154 : /* ======================================================== +; line 155 : COMMANDレジスタへの書き込み +; line 156 : 　 0なら呼ばれません。ケア不要 +; line 157 : ======================================================== */ +; line 158 : task_status_immed do_command0( ) +; line 159 : { +_do_command0: +$DGL 1,152 +??bf_do_command0: +; line 160 : // command0 本体電源など +; line 161 : if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BI +; T_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) ! +; = 0x00 ) +$DGL 0,3 + mov a,!_vreg_ctr+32 ;[INF] 3, 1 + and a,#0FH ; 15 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0035 ;[INF] 2, 4 +; line 162 : { +??bb00_do_command0: +; line 163 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ ) +$DGL 0,5 + mov a,!_vreg_ctr+32 ;[INF] 3, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0034 ;[INF] 2, 4 +; line 164 : { +??bb01_do_command0: +; line 165 : system_status.pwr_state = OFF_TRIG; +$DGL 0,7 + clrb !_system_status ;[INF] 3, 1 +??eb01_do_command0: +; line 166 : } +$DGL 0,8 + br $?L0035 ;[INF] 2, 3 +?L0034: +; line 167 : else +; line 168 : { +??bb02_do_command0: +; line 169 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ ) +$DGL 0,11 + mov a,!_vreg_ctr+32 ;[INF] 3, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0036 ;[INF] 2, 4 +; line 170 : { +??bb03_do_command0: +; line 171 : PM_reset_ast( ); +$DGL 0,13 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 172 : RESET2_ast; +$DGL 0,14 +??bb04_do_command0: + clr1 P0.1 ;[INF] 3, 2 + clr1 PM0.1 ;[INF] 3, 2 +??eb04_do_command0: +; line 173 : FCRAM_RST_ast; +$DGL 0,15 +??bb05_do_command0: + clr1 P3.0 ;[INF] 3, 2 +??eb05_do_command0: +??eb03_do_command0: +; line 174 : } +?L0036: +; line 175 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_ +; REQ ) +$DGL 0,17 + mov a,!_vreg_ctr+32 ;[INF] 3, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0038 ;[INF] 2, 4 +; line 176 : { +??bb06_do_command0: +; line 177 : FCRAM_RST_ast; +$DGL 0,19 +??bb07_do_command0: + clr1 P3.0 ;[INF] 3, 2 +??eb07_do_command0: +??eb06_do_command0: +; line 178 : } +$DGL 0,20 + br $?L0040 ;[INF] 2, 3 +?L0038: +; line 179 : else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_ +; REQ ) +$DGL 0,21 + mov a,!_vreg_ctr+32 ;[INF] 3, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0040 ;[INF] 2, 4 +; line 180 : { +??bb08_do_command0: +; line 181 : RESET2_ast; +$DGL 0,23 +??bb09_do_command0: + clr1 P0.1 ;[INF] 3, 2 + clr1 PM0.1 ;[INF] 3, 2 +??eb09_do_command0: +??eb08_do_command0: +; line 182 : } +?L0040: +; line 183 : wait_ms( 5 ); +$DGL 0,25 + movw ax,#05H ; 5 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 184 : FCRAM_RST_neg; +$DGL 0,26 +??bb0A_do_command0: + set1 P3.0 ;[INF] 3, 2 +??eb0A_do_command0: +; line 185 : PM_reset_neg(); +$DGL 0,27 + movw ax,#03H ; 3 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 186 : RESET2_neg; +$DGL 0,28 +??bb0B_do_command0: + set1 PM0.1 ;[INF] 3, 2 +??eb0B_do_command0: +??eb02_do_command0: +; line 187 : /* +; line 188 : // CODEC 不定レジスタ初期化 +; line 189 : wait_ms( 100 ); +; line 190 : { +; line 191 : u8 codec_reg_init[3] = { 0,0,0 }; +; line 192 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, c +; odec_reg_init ); +; line 193 : } +; line 194 : */ +; line 195 : } +?L0035: +??eb00_do_command0: +; line 196 : } +; line 197 : +; line 198 : vreg_ctr[VREG_C_COMMAND0] = 0; +$DGL 0,40 + clrb !_vreg_ctr+32 ;[INF] 3, 1 +; line 199 : return ( ERR_FINISED ); +$DGL 0,41 + clrw bc ;[INF] 1, 1 +; line 200 : } +$DGL 0,42 +??ef_do_command0: + ret ;[INF] 1, 6 +??ee_do_command0: +; line 201 : +; line 202 : +; line 203 : +; line 204 : /* ======================================================== +; line 205 : 　互換向け、TWLアプリへの割り込み +; line 206 : 仮想レジスタの書き込み時に行います。 +; line 207 : ======================================================== */ +; line 208 : // task_status_immed do_command1( ) +; line 209 : +; line 210 : +; line 211 : extern u8 iic_burst_state; +; line 212 : /* ======================================================== +; line 213 : 　デバッグ用にいろいろ読んできます。 +; line 214 : 　返値はデータそのもの +; line 215 : ======================================================== */ +; line 216 : task_status_immed tski_mcu_info_read() +; line 217 : { +_tski_mcu_info_read: +$DGL 1,206 + push hl ;[INF] 1, 1 +??bf_tski_mcu_info_read: +; line 218 : u8 temp; +; line 219 : +; line 220 : +; line 221 : if( SPD ) +$DGL 0,5 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].0 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + bc $?L0046 ;[INF] 2, 4 +; line 222 : { +??bb00_tski_mcu_info_read: +; line 223 : goto end; +??eb00_tski_mcu_info_read: +; line 224 : } +; line 225 : +; line 226 : if( STD ) +$DGL 0,10 + push hl ;[INF] 1, 1 + movw hl,#0541H ; 1345 ;[INF] 3, 1 + mov1 CY,[hl].1 ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + sknc ;[INF] 2, 1 +; line 227 : { +??bb01_tski_mcu_info_read: +; line 228 : SPIE = 1; +$DGL 0,12 + set1 !IICCTL01.4 ;[INF] 4, 2 +??eb01_tski_mcu_info_read: +; line 229 : } +?L0047: +; line 230 : +; line 231 : if( IICAIF == 0 ) +$DGL 0,15 + bt IF2H.3,$?L0049 ;[INF] 4, 5 +; line 232 : { +??bb02_tski_mcu_info_read: +; line 233 : return( ERR_CONTINUE ); +$DGL 0,17 + onew bc ;[INF] 1, 1 + br $?L0043 ;[INF] 2, 3 +??eb02_tski_mcu_info_read: +; line 234 : } +?L0049: +; line 235 : else +; line 236 : { +??bb03_tski_mcu_info_read: +; line 237 : IICAIF = 0; +$DGL 0,21 + clr1 IF2H.3 ;[INF] 3, 2 +??eb03_tski_mcu_info_read: +; line 238 : } +; line 239 : +; line 240 : switch( iic_burst_state++ ){ +$DGL 0,24 + mov a,!_iic_burst_state ;[INF] 3, 1 + inc !_iic_burst_state ;[INF] 3, 2 + shrw ax,8 ;[INF] 2, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0052 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0053 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0054 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0055 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0056 ;[INF] 2, 4 + br $?L0046 ;[INF] 2, 3 +??bb04_tski_mcu_info_read: +; line 241 : case( 0 ): // 本体種類識別 +?L0052: +; line 242 : IICA = (u8)system_status.model; +$DGL 0,26 + mov a,!_system_status+3 ;[INF] 3, 1 + mov !IICA1,a ;[INF] 3, 1 +; line 243 : break; +$DGL 0,27 + br $?L0051 ;[INF] 2, 3 +; line 244 : +; line 245 : case( 1 ): // IICがなにかエラーでも知らない。00かFFな +; らエラーの可能性が高い +?L0053: +; line 246 : IICA = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VE +; R ); +$DGL 0,30 + clrw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov !IICA1,a ;[INF] 3, 1 +; line 247 : break; +$DGL 0,31 + br $?L0051 ;[INF] 2, 3 +; line 248 : +; line 249 : case( 2 ): // 電池メーカーの識別 +?L0054: +; line 250 : BT_DET_P = 1; +$DGL 0,34 + set1 P1.6 ;[INF] 3, 2 +; line 251 : IICA = ( u8 ) ( get_adc( ADC_SEL_BATT_DET ) >> 5 ); +$DGL 0,35 + movw ax,#09H ; 9 ;[INF] 3, 1 + call !_get_adc ;[INF] 3, 3 + mov a,c ;[INF] 1, 1 + shr a,5 ;[INF] 2, 1 + mov !IICA1,a ;[INF] 3, 1 +; line 252 : BT_DET_P = 0; +$DGL 0,36 + clr1 P1.6 ;[INF] 3, 2 +; line 253 : break; +$DGL 0,37 + br $?L0051 ;[INF] 2, 3 +; line 254 : +; line 255 : case( 3 ): // ガスゲージバージョン +?L0055: +; line 256 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R +; EG_VERSION ); +$DGL 0,40 + movw ax,#08H ; 8 ;[INF] 3, 1 + call !bs_F0060 ;[INF] 3, 3 +; line 257 : break; +$DGL 0,41 + br $?L0051 ;[INF] 2, 3 +; line 258 : +; line 259 : case( 4 ): // LSB +?L0056: +; line 260 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R +; EG_VERSION + 1 ); +$DGL 0,44 + movw ax,#09H ; 9 ;[INF] 3, 1 + call !bs_F0060 ;[INF] 3, 3 +; line 261 : break; +; line 262 : +; line 263 : default: +; line 264 : goto end; +??eb04_tski_mcu_info_read: +; line 265 : } +?L0051: +; line 266 : return( ERR_CONTINUE ); +$DGL 0,50 + onew bc ;[INF] 1, 1 + br $?L0043 ;[INF] 2, 3 +; line 267 : +; line 268 : end: +?L0046: +; line 269 : LREL = 1; +$DGL 0,53 + set1 !IICCTL01.6 ;[INF] 4, 2 +; line 270 : SPIE = 0; +$DGL 0,54 + clr1 !IICCTL01.4 ;[INF] 4, 2 +; line 271 : IICAMK = 0; +$DGL 0,55 + clr1 MK2H.3 ;[INF] 3, 2 +; line 272 : iic_burst_state = 0; +$DGL 0,56 + clrb !_iic_burst_state ;[INF] 3, 1 +; line 273 : return( ERR_FINISED ); +$DGL 0,57 + clrw bc ;[INF] 1, 1 +; line 274 : } +?L0043: +$DGL 0,58 +??ef_tski_mcu_info_read: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_tski_mcu_info_read: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c +; +; $FUNC tsk_misc_stat(55) +; void=(void) +; CODE SIZE= 173 bytes, CLOCK_SIZE= 145 clocks, STACK_SIZE= 8 bytes +; +; $CALL set_irq(94) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(98) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(107) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_irq(111) +; void=(int:ax, int:[sp+4]) +; +; $CALL renge_task_immed_add(130) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(139) +; bc=(pointer:ax) +; +; $FUNC do_command0(159) +; bc=(void) +; CODE SIZE= 106 bytes, CLOCK_SIZE= 88 clocks, STACK_SIZE= 8 bytes +; +; $CALL iic_mcu_write_a_byte(171) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(183) +; void=(int:ax) +; +; $CALL iic_mcu_write_a_byte(185) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $FUNC tski_mcu_info_read(217) +; bc=(void) +; CODE SIZE= 137 bytes, CLOCK_SIZE= 149 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_read_a_byte(246) +; bc=(int:ax, int:[sp+4]) +; +; $CALL get_adc(251) +; bc=(int:ax) +; +; $CALL iic_mcu_read_a_byte(256) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_read_a_byte(260) +; bc=(int:ax, int:[sp+4]) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/task_sys.asm b/branches/0.10(X3)/inter_asm/task_sys.asm new file mode 100644 index 0000000..321ff45 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/task_sys.asm @@ -0,0 +1,1320 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_sys.c +; In-file : task_sys.c +; Asm-file : inter_asm\task_sys.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0C7H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, task_sys.c +$DGS MOD_NAM, task_sys, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 01EH +$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 025H +$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 01EH, 01H +$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 02FH +$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 025H, 01H +$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H +$DGS AUX_TAG, 04H, 041H +$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H +$DGS AUX_BIT, 00H, 01H +$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H +$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H +$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 02FH, 04H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 047H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 041H, 01H +$DGS LAB_SYM, bs_F0057, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0057, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_sys, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0A6H, 00H, 00H +$DGS BEG_FUN, ??bf_tsk_sys, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 023H, 00H, 050H +$DGS STA_SYM, _timeout, ?L0003, U, 0CH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 052H +$DGS BEG_BLK, ??bb01_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 054H +$DGS BEG_BLK, ??bb02_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 058H +$DGS END_BLK, ??eb02_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 012H +$DGS BEG_BLK, ??bb03_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 014H, 00H, 05CH +$DGS END_BLK, ??eb03_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 016H +$DGS BEG_BLK, ??bb04_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 018H, 00H, 060H +$DGS END_BLK, ??eb04_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01CH +$DGS BEG_BLK, ??bb05_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01FH, 00H, 066H +$DGS END_BLK, ??eb05_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 022H +$DGS END_BLK, ??eb01_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 029H +$DGS BEG_BLK, ??bb06_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 034H, 00H, 06AH +$DGS END_BLK, ??eb06_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 039H +$DGS BEG_BLK, ??bb07_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 048H, 00H, 06EH +$DGS END_BLK, ??eb07_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 04BH +$DGS BEG_BLK, ??bb08_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04DH, 00H, 072H +$DGS END_BLK, ??eb08_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 051H +$DGS BEG_BLK, ??bb09_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 065H, 00H, 076H +$DGS END_BLK, ??eb09_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 067H +$DGS BEG_BLK, ??bb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 069H, 00H, 07AH +$DGS END_BLK, ??eb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 069H +$DGS BEG_BLK, ??bb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 084H, 00H, 07EH +$DGS END_BLK, ??eb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 087H +$DGS BEG_BLK, ??bb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 092H, 00H, 082H +$DGS END_BLK, ??eb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0A1H +$DGS BEG_BLK, ??bb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0A9H, 00H, 086H +$DGS END_BLK, ??eb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0ABH +$DGS BEG_BLK, ??bb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0B1H, 00H, 08AH +$DGS END_BLK, ??eb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0B1H +$DGS BEG_BLK, ??bb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0C4H, 00H, 08EH +$DGS END_BLK, ??eb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0C7H +$DGS BEG_BLK, ??bb10_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DEH, 00H, 090H +$DGS BEG_BLK, ??bb11_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0E5H, 00H, 096H +$DGS END_BLK, ??eb11_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EAH +$DGS END_BLK, ??eb10_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0ECH +$DGS BEG_BLK, ??bb12_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EEH, 00H, 098H +$DGS BEG_BLK, ??bb13_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0F2H, 00H, 09EH +$DGS END_BLK, ??eb13_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0F2H +$DGS END_BLK, ??eb12_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0110H +$DGS BEG_BLK, ??bb14_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0114H, 00H, 00H +$DGS END_BLK, ??eb14_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0117H +$DGS END_BLK, ??eb00_tsk_sys, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0119H +$DGS END_FUN, ??ef_tsk_sys, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 011AH +$DGS STA_SYM, _chk_emergencyExit, U, U, 01H, 03H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0C1H, 00H, 00H +$DGS BEG_FUN, ??bf_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0143H, 00H, 0ABH +$DGS STA_SYM, _state, ?L0048, U, 04H, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 0ADH +$DGS BEG_BLK, ??bb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 08H, 00H, 0B1H +$DGS END_BLK, ??eb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 0B3H +$DGS BEG_BLK, ??bb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 010H, 00H, 0BBH +$DGS END_BLK, ??eb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 017H +$DGS END_BLK, ??eb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 018H +$DGS END_BLK, ??eb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 00H +$DGS END_BLK, ??eb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01DH +$DGS END_FUN, ??ef_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 01FH +$DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 026H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 0C7H, 00H, 00H +$DGS BEG_FUN, ??bf_tski_firm_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0181H, 00H, 0C7H +$DGS END_FUN, ??ef_tski_firm_update, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 04H +$DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H +$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _LED_init, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _LED_stop, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 02H, 00H, 00H +$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _firm_update, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + + EXTRN _iic_mcu_write_a_byte + EXTRN _system_status + EXTRN _SW_pow_count + EXTRN _iic_mcu_start + EXTRN _PM_init + EXTRN _PM_sys_pow_on + EXTRN _iic_mcu_stop + EXTRN _PM_LCD_vcom_set + EXTRN _vreg_ctr + EXTRN _LED_init + EXTRN _IIC_ctr_Init + EXTRN _set_irq + EXTRN _IIC_twl_Init + EXTRN _wait_ms + EXTRN _LED_stop + EXTRN _IIC_ctr_Stop + EXTRN _IIC_twl_Stop + EXTRN _PM_sys_pow_off + EXTRN _SW_wifi_count + EXTRN _iic_mcu_read_a_byte + EXTRN _do_command0 + EXTRN _renge_task_immed_add + EXTRN _firm_update + EXTBIT _renge_task_interval_run_force + PUBLIC _tsk_sys + PUBLIC _tski_firm_update + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DB 00H ; 0 + DB (1) + +@@INIT DSEG BASEP +?L0003: DS (1) + DS (1) + +@@DATA DSEG BASEP +?L0048: DS (2) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_F0057: + push ax ;[INF] 1, 1 + mov x,#05H ; 5 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 + ret ;[INF] 1, 6 +es_F0057: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0057 +; CODE SIZE= 12 bytes + +; End of Sub-Routines + +; line 1 : #pragma SFR +; line 2 : #pragma NOP +; line 3 : #pragma HALT +; line 4 : #pragma STOP +; line 5 : +; line 6 : #include "incs.h" +; line 7 : +; line 8 : #include "i2c_twl.h" +; line 9 : #include "i2c_ctr.h" +; line 10 : #include "led.h" +; line 11 : #include "accero.h" +; line 12 : #include "pm.h" +; line 13 : #include "rtc.h" +; line 14 : #include "sw.h" +; line 15 : #include "adc.h" +; line 16 : +; line 17 : +; line 18 : +; line 19 : //========================================================= +; line 20 : static void chk_emergencyExit(); +; line 21 : +; line 22 : +; line 23 : +; line 24 : //========================================================= +; line 25 : +; line 26 : +; line 27 : +; line 28 : /* ======================================================== +; line 29 : マイコン内部で必要なもの +; line 30 : ・省電力に入れる +; line 31 : 　system_status.pwr_state == OFF_TRIG で、このタスクが呼ばれる +; と、 +; line 32 : 省電力モードに入ります +; line 33 : ======================================================== */ +; line 34 : void tsk_sys( ) +; line 35 : { + +ROM_CODE CSEG BASE +_tsk_sys: +$DGL 1,75 +??bf_tsk_sys: +; line 36 : static u8 timeout = 0; +; line 37 : +; line 38 : switch ( system_status.pwr_state ) +$DGL 0,4 + mov a,!_system_status ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + sknz ;[INF] 2, 1 + br !?L0010 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + bz $?L0005 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0006 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0007 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0008 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0009 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0011 ;[INF] 3, 3 + br !?L0038 ;[INF] 3, 3 +; line 39 : { +??bb00_tsk_sys: +; line 40 : case OFF: //------------------------------- +; ------------------------ +?L0005: +; line 41 : // スイッチ操作などで割り込みが発生し、スリープが解除され +; るとここに来ます。 +; line 42 : +; line 43 : #ifndef _PARRADIUM_ +; line 44 : switch ( system_status.poweron_reason ) +$DGL 0,10 + mov a,!_system_status+1 ;[INF] 3, 1 + sarw ax,8 ;[INF] 2, 1 + subw ax,#02H ; 2 ;[INF] 3, 1 + bz $?L0015 ;[INF] 2, 4 +; line 45 : { +??bb01_tsk_sys: +; line 46 : default: +; line 47 : // スイッチで電源on +; line 48 : +; line 49 : if( SW_pow_count != 0 ) +$DGL 0,15 + cmp0 !_SW_pow_count ;[INF] 3, 1 + bz $?L0018 ;[INF] 2, 4 +; line 50 : { +??bb02_tsk_sys: +; line 51 : timeout = 0; +$DGL 0,17 + clrb !?L0003 ; timeout ;[INF] 3, 1 +??eb02_tsk_sys: +; line 52 : } +$DGL 0,18 + br $?L0019 ;[INF] 2, 3 +?L0018: +; line 53 : else +; line 54 : { +??bb03_tsk_sys: +; line 55 : timeout += 1; +$DGL 0,21 + inc !?L0003 ; timeout ;[INF] 3, 2 +??eb03_tsk_sys: +; line 56 : } +?L0019: +; line 57 : if( timeout > 127 ) +$DGL 0,23 + mov a,!?L0003 ; timeout ;[INF] 3, 1 + addw ax,ax ;[INF] 1, 1 + bnc $?L0020 ;[INF] 2, 4 +; line 58 : { +??bb04_tsk_sys: +; line 59 : system_status.pwr_state = OFF_TRIG; // スイッ +; チはノイズだった。寝る。 +$DGL 0,25 + clrb !_system_status ;[INF] 3, 1 +; line 60 : renge_task_interval_run_force = 1; +$DGL 0,26 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 61 : return; +$DGL 0,27 + ret ;[INF] 1, 6 +??eb04_tsk_sys: +; line 62 : } +?L0020: +; line 63 : +; line 64 : if( SW_pow_count < 3 ) +$DGL 0,30 + cmp !_SW_pow_count,#03H ; 3 ;[INF] 4, 1 + sknc ;[INF] 2, 1 + br !?L0004 ;[INF] 3, 3 +; line 65 : { +??bb05_tsk_sys: +; line 66 : // もう少しスイッチの様子を見る +; line 67 : return; +??eb05_tsk_sys: +; line 68 : } +; line 69 : // 電源投入 +; line 70 : system_status.poweron_reason = PWSW; +$DGL 0,36 + oneb !_system_status+1 ;[INF] 3, 1 +; line 71 : break; +; line 72 : +; line 73 : case ( RTC_ALARM ): +; line 74 : break; +??eb01_tsk_sys: +; line 75 : } +?L0015: +; line 76 : +; line 77 : timeout = 0; +$DGL 0,43 + clrb !?L0003 ; timeout ;[INF] 3, 1 +; line 78 : +; line 79 : // 電源投入 // +; line 80 : iic_mcu_start( ); +$DGL 0,46 + call !_iic_mcu_start ;[INF] 3, 3 +; line 81 : +; line 82 : // ↓で電池残量ICの起動待ちウェイトなどがあります。 +; line 83 : PM_init( ); // 電池残量ICの設定 +$DGL 0,49 + call !_PM_init ;[INF] 3, 3 +; line 84 : +; line 85 : if( PM_sys_pow_on( ) != ERR_SUCCESS ) +$DGL 0,51 + call !_PM_sys_pow_on ;[INF] 3, 3 + cmp0 c ;[INF] 1, 1 + bz $?L0024 ;[INF] 2, 4 +; line 86 : { // 電源起動不可エラー +??bb06_tsk_sys: +; line 87 : renge_task_interval_run_force = 1; +$DGL 0,53 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 88 : iic_mcu_stop( ); +$DGL 0,54 + call !_iic_mcu_stop ;[INF] 3, 3 +; line 89 : system_status.pwr_state = OFF_TRIG; +$DGL 0,55 + clrb !_system_status ;[INF] 3, 1 +; line 90 : return; +$DGL 0,56 + ret ;[INF] 1, 6 +??eb06_tsk_sys: +; line 91 : } +?L0024: +; line 92 : PM_CHG_TIMEOUT_ENABLE(); +; line 93 : // IRQ0_active; +; line 94 : +; line 95 : #else +; line 96 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; +; line 97 : system_status.poweron_reason = PWSW; +; line 98 : #endif // _PARADDIUM_ +; line 99 : +; line 100 : PM_LCD_vcom_set( ); // LCDの対向電圧値など書き込み +$DGL 0,66 + call !_PM_LCD_vcom_set ;[INF] 3, 3 +; line 101 : #ifdef _PMIC_TWL_ +; line 102 : PM_TEG_LCD_dis( 0 ); +; line 103 : #endif +; line 104 : +; line 105 : if( system_status.poweron_reason == PWSW ) +$DGL 0,71 + cmp !_system_status+1,#01H ; 1 ;[INF] 4, 1 + bnz $?L0026 ;[INF] 2, 4 +; line 106 : { +??bb07_tsk_sys: +; line 107 : // 電源ボタンでのonの時は、LEDを点灯させる +; line 108 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; +$DGL 0,74 + clrb !_vreg_ctr+41 ;[INF] 3, 1 +??eb07_tsk_sys: +; line 109 : } +$DGL 0,75 + br $?L0027 ;[INF] 2, 3 +?L0026: +; line 110 : else +; line 111 : { +??bb08_tsk_sys: +; line 112 : // とりあえず、LED消灯状態で起動させる +; line 113 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; +$DGL 0,79 + mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1 +??eb08_tsk_sys: +; line 114 : // todo? +; line 115 : } +?L0027: +; line 116 : system_status.pwr_state = ON_TRIG; +$DGL 0,82 + mov !_system_status,#02H ; 2 ;[INF] 4, 1 +; line 117 : // ここまで来ると、電源投入確定 +; line 118 : break; +$DGL 0,84 + ret ;[INF] 1, 6 +; line 119 : +; line 120 : case ON_TRIG: //------------------------------- +; ------------------------ +?L0006: +; line 121 : +; line 122 : LED_init( ); +$DGL 0,88 + call !_LED_init ;[INF] 3, 3 +; line 123 : +; line 124 : PU7 = 0b00011101; // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_ +; EXTDC_n +$DGL 0,90 + mov !PU7,#01DH ; 29 ;[INF] 4, 1 +; line 125 : +; line 126 : IIC_ctr_Init( ); +$DGL 0,92 + call !_IIC_ctr_Init ;[INF] 3, 3 +; line 127 : if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT +; _RESET ) +; line 128 : /* +; line 129 : if( vreg_ctr[ VREG_C_IRQ0 ] +; line 130 : | vreg_ctr[ VREG_C_IRQ0 ] +; line 131 : | vreg_ctr[ VREG_C_IRQ0 ] +; line 132 : | vreg_ctr[ VREG_C_IRQ0 ] +; line 133 : */ +; line 134 : != 0 ) +$DGL 0,100 + mov a,!_vreg_ctr+2 ;[INF] 3, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0028 ;[INF] 2, 4 +; line 135 : { +??bb09_tsk_sys: +; line 136 : set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); +$DGL 0,102 + movw ax,#080H ; 128 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#010H ; 16 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +??eb09_tsk_sys: +; line 137 : } +?L0028: +; line 138 : IIC_twl_Init( ); +$DGL 0,104 + call !_IIC_twl_Init ;[INF] 3, 3 +; line 139 : RTC_32k_on( ); +$DGL 0,105 +??bb0A_tsk_sys: + set1 RTCC0.4 ;[INF] 3, 2 +??eb0A_tsk_sys: +; line 140 : +; line 141 : KRM = 0b00000000; +$DGL 0,107 + clrb !KRM ;[INF] 3, 1 +; line 142 : +; line 143 : system_status.poweron_reason = NONE; +$DGL 0,109 + clrb !_system_status+1 ;[INF] 3, 1 +; line 144 : renge_task_interval_run_force = 1; +$DGL 0,110 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 145 : +; line 146 : MK0 = INT_MSK0_RSV; +$DGL 0,112 + movw MK0,#0EF3FH ; -4289 ;[INF] 4, 1 +; line 147 : MK1 = INT_MSK1_RSV; +$DGL 0,113 + movw MK1,#0F0F6H ; -3850 ;[INF] 4, 1 +; line 148 : #ifdef _MCU_BSR_ +; line 149 : // MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT +; _MSK2_CODEC_PMIRQ ); +; line 150 : // PMK21 = 0; // wifi 使わない +; line 151 : PMK6 = 0; // pm_irq +$DGL 0,117 + clr1 MK2L.3 ;[INF] 3, 2 +; line 152 : #else +; line 153 : MK2L = ~INT_MSK2_WIFI_TX_KE3; +; line 154 : #endif +; line 155 : +; line 156 : system_status.reboot = 0; +$DGL 0,122 + clr1 !_system_status+2.3 ;[INF] 4, 2 +; line 157 : system_status.pwr_state = ON; +$DGL 0,123 + mov !_system_status,#03H ; 3 ;[INF] 4, 1 +; line 158 : break; +$DGL 0,124 + ret ;[INF] 1, 6 +; line 159 : +; line 160 : case ON: //------------------------------- +; -------------- +?L0007: +; line 161 : // PMICによる強制電源断チェック +; line 162 : // デバッガがreset1をアサートすることもある。そのときは全 +; 部リセット +; line 163 : chk_emergencyExit(); +$DGL 0,129 + call !_chk_emergencyExit ;[INF] 3, 3 +; line 164 : +; line 165 : // SLP監視 +; line 166 : if( SLP_REQ ){ +$DGL 0,132 + bf P12.0,$?L0030 ;[INF] 4, 5 +??bb0B_tsk_sys: +; line 167 : system_status.pwr_state = SLEEP_TRIG; +$DGL 0,133 + mov !_system_status,#04H ; 4 ;[INF] 4, 1 +; line 168 : renge_task_interval_run_force = 1; +$DGL 0,134 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +??eb0B_tsk_sys: +; line 169 : } +?L0030: +; line 170 : break; +$DGL 0,136 + ret ;[INF] 1, 6 +; line 171 : +; line 172 : case SLEEP_TRIG: //------------------------------- +; ------ +?L0008: +; line 173 : PM_VDD_ecoMode(); +$DGL 0,139 + movw ax,#027H ; 39 ;[INF] 3, 1 + call !bs_F0057 ;[INF] 3, 3 +; line 174 : system_status.pwr_state = SLEEP; +$DGL 0,140 + mov !_system_status,#05H ; 5 ;[INF] 4, 1 +; line 175 : break; +$DGL 0,141 + ret ;[INF] 1, 6 +; line 176 : +; line 177 : case SLEEP: //------------------------------- +; ----------- +?L0009: +; line 178 : chk_emergencyExit(); +$DGL 0,144 + call !_chk_emergencyExit ;[INF] 3, 3 +; line 179 : // スリープから復帰 +; line 180 : if( !SLP_REQ ){ +$DGL 0,146 + bt P12.0,$?L0032 ;[INF] 4, 5 +??bb0C_tsk_sys: +; line 181 : PM_VDD_normMode(); +$DGL 0,147 + clrw ax ;[INF] 1, 1 + call !bs_F0057 ;[INF] 3, 3 +; line 182 : wait_ms( 5 ); // tdly_sw +$DGL 0,148 + movw ax,#05H ; 5 ;[INF] 3, 1 + call !_wait_ms ;[INF] 3, 3 +; line 183 : +; line 184 : #ifdef _MODEL_CTR_ +; line 185 : SLP_ACK = 1; +$DGL 0,151 + set1 P7.7 ;[INF] 3, 2 +; line 186 : NOP(); // 適当ウェイト +$DGL 0,152 + nop ;[INF] 1, 1 +; line 187 : NOP(); +$DGL 0,153 + nop ;[INF] 1, 1 +; line 188 : NOP(); +$DGL 0,154 + nop ;[INF] 1, 1 +; line 189 : NOP(); +$DGL 0,155 + nop ;[INF] 1, 1 +; line 190 : SLP_ACK = 0; +$DGL 0,156 + clr1 P7.7 ;[INF] 3, 2 +; line 191 : #endif +; line 192 : +; line 193 : system_status.pwr_state = ON_TRIG; +$DGL 0,159 + mov !_system_status,#02H ; 2 ;[INF] 4, 1 +; line 194 : renge_task_interval_run_force = 1; +$DGL 0,160 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +??eb0C_tsk_sys: +; line 195 : } +?L0032: +; line 196 : +; line 197 : break; +$DGL 0,163 + ret ;[INF] 1, 6 +; line 198 : +; line 199 : case OFF_TRIG: //------------------------------- +; -------- +?L0010: +; line 200 : // LED消灯を待つ +; line 201 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; +$DGL 0,167 + mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1 +; line 202 : if(( LED_duty_pow_H != 0 ) || ( LED_duty_pow_L != 0 )) +$DGL 0,168 + clrw ax ;[INF] 1, 1 + cmpw ax,!TDR06 ;[INF] 3, 1 + bnz $?L0036 ;[INF] 2, 4 + cmpw ax,!TDR07 ;[INF] 3, 1 + skz ;[INF] 2, 1 +?L0036: +; line 203 : { +??bb0D_tsk_sys: +; line 204 : return; +$DGL 0,170 + ret ;[INF] 1, 6 +??eb0D_tsk_sys: +; line 205 : } +?L0034: +; line 206 : +; line 207 : PM_CHG_TIMEOUT_ENABLE(); +; line 208 : LED_stop( ); +$DGL 0,174 + call !_LED_stop ;[INF] 3, 3 +; line 209 : IIC_ctr_Stop( ); +$DGL 0,175 + call !_IIC_ctr_Stop ;[INF] 3, 3 +; line 210 : IIC_twl_Stop( ); +$DGL 0,176 + call !_IIC_twl_Stop ;[INF] 3, 3 +; line 211 : RTC_32k_off(); +$DGL 0,177 +??bb0E_tsk_sys: + clr1 RTCC0.4 ;[INF] 3, 2 +??eb0E_tsk_sys: +; line 212 : +; line 213 : vreg_ctr[VREG_C_IRQ0] = 0; +$DGL 0,179 + clrb !_vreg_ctr+16 ;[INF] 3, 1 +; line 214 : vreg_ctr[VREG_C_IRQ1] = 0; +$DGL 0,180 + clrb !_vreg_ctr+17 ;[INF] 3, 1 +; line 215 : vreg_ctr[VREG_C_IRQ2] = 0; +$DGL 0,181 + clrb !_vreg_ctr+18 ;[INF] 3, 1 +; line 216 : vreg_ctr[VREG_C_IRQ3] = 0; +$DGL 0,182 + clrb !_vreg_ctr+19 ;[INF] 3, 1 +; line 217 : +; line 218 : // 電源オン条件の割り込みセット +; line 219 : // PWSW KR3 押すとL +; line 220 : // BG24 KR4 +; line 221 : // ふた開け INTP5 閉じるとL +; line 222 : // ACアダプタ INTP4 アダプタありでL +; line 223 : // RTC +; line 224 : +; line 225 : #ifdef _PMIC_TWL_ +; line 226 : PM_TEG_LCD_dis( 1 ); +; line 227 : #endif +; line 228 : // IRQ0_deactive; +; line 229 : // pullup_off(); ↓ +; line 230 : { +??bb0F_tsk_sys: +; line 231 : PU5 = 0b00000011; // PM_CHG,PM_CHGERR +$DGL 0,197 + mov !PU5,#03H ; 3 ;[INF] 4, 1 +; line 232 : PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC +$DGL 0,198 + mov !PU7,#019H ; 25 ;[INF] 4, 1 +??eb0F_tsk_sys: +; line 233 : } +; line 234 : +; line 235 : PM_sys_pow_off( ); +$DGL 0,201 + call !_PM_sys_pow_off ;[INF] 3, 3 +; line 236 : +; line 237 : KRM = ( KR_SW_POW ); // Mask ではなく、Modeなのだそう +; だ。紛らわしい +$DGL 0,203 + mov KRM,#08H ; 8 ;[INF] 3, 1 +; line 238 : // intp20系は後ほど +; line 239 : MK0 = ~( INT_MSK0_EXTDC ); +$DGL 0,205 + movw MK0,#0FFBFH ; -65 ;[INF] 4, 1 +; line 240 : MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCALARM | INT_MSK1_RTCI +; NTVAL ); +$DGL 0,206 + movw MK1,#0F1FFH ; -3585 ;[INF] 4, 1 +; line 241 : MK2L = 0b11111111; +$DGL 0,207 + mov MK2L,#0FFH ; 255 ;[INF] 3, 1 +; line 242 : +; line 243 : IF0 = 0; +$DGL 0,209 + clrw ax ;[INF] 1, 1 + movw IF0,ax ;[INF] 2, 1 +; line 244 : IF1 = 0; +$DGL 0,210 + movw IF1,ax ;[INF] 2, 1 +; line 245 : IF2 = 0; +$DGL 0,211 + movw IF2,ax ;[INF] 2, 1 +; line 246 : +; line 247 : timeout = 0; +$DGL 0,213 + clrb !?L0003 ; timeout ;[INF] 3, 1 +; line 248 : +; line 249 : system_status.pwr_state = BT_CHARGE; +$DGL 0,215 + mov !_system_status,#06H ; 6 ;[INF] 4, 1 +; line 250 : SW_pow_count = 0; +$DGL 0,216 + clrb !_SW_pow_count ;[INF] 3, 1 +; line 251 : SW_wifi_count = 0; +$DGL 0,217 + clrb !_SW_wifi_count ;[INF] 3, 1 +; line 252 : // no break // +; line 253 : +; line 254 : case BT_CHARGE: +?L0011: +; line 255 : if( !PM_EXTDC_n ) +$DGL 0,221 + bt P7.0,$?L0037 ;[INF] 4, 5 +; line 256 : { +??bb10_tsk_sys: +; line 257 : // アダプタ有り：充電温度監視 +; line 258 : BT_TEMP_P = 1; +$DGL 0,224 + set1 P1.7 ;[INF] 3, 2 +; line 259 : +; line 260 : // 電源on？ +; line 261 : if( ( SW_pow_count > 3 ) || ( SW_wifi_count > 3 ) +; line 262 : || ( system_status.poweron_reason == RTC_ALARM ) +; ) +$DGL 0,228 + cmp !_SW_pow_count,#04H ; 4 ;[INF] 4, 1 + bnc $?L0041 ;[INF] 2, 4 + cmp !_SW_wifi_count,#04H ; 4 ;[INF] 4, 1 + bnc $?L0041 ;[INF] 2, 4 + cmp !_system_status+1,#02H ; 2 ;[INF] 4, 1 + bnz $?L0004 ;[INF] 2, 4 +?L0041: +; line 263 : { +??bb11_tsk_sys: +; line 264 : system_status.pwr_state = OFF; // 若干抵抗有るが +; ... +$DGL 0,230 + oneb !_system_status ;[INF] 3, 1 +; line 265 : renge_task_interval_run_force = 1; +$DGL 0,231 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 266 : KRMK = 1; +$DGL 0,232 + set1 MK1H.3 ;[INF] 3, 2 +; line 267 : return; +$DGL 0,233 + ret ;[INF] 1, 6 +??eb11_tsk_sys: +; line 268 : } +; line 269 : return; +??eb10_tsk_sys: +; line 270 : } +?L0037: +; line 271 : else +; line 272 : { +??bb12_tsk_sys: +; line 273 : // 省電力へ移行 +; line 274 : BT_TEMP_P = 0; +$DGL 0,240 + clr1 P1.7 ;[INF] 3, 2 +; line 275 : while( RWST ) +$DGL 0,241 +?L0042: + bf RTCC1.1,$?L0043 ;[INF] 4, 5 +; line 276 : {;} +$DGL 0,242 +??bb13_tsk_sys: +??eb13_tsk_sys: + br $?L0042 ;[INF] 2, 3 +?L0043: +; line 277 : +; line 278 : iic_mcu_stop( ); +$DGL 0,244 + call !_iic_mcu_stop ;[INF] 3, 3 +; line 279 : +; line 280 : // 割り込み待ちで寝る // +; line 281 : RTCIMK = 1; +$DGL 0,247 + set1 MK1H.2 ;[INF] 3, 2 +; line 282 : #ifndef _PARRADIUM_ +; line 283 : +; line 284 : #ifdef _MCU_BSR_ +; line 285 : CKC = 0b00001001; +$DGL 0,251 + mov CKC,#09H ; 9 ;[INF] 3, 1 +; line 286 : OSMC = 0x00; +$DGL 0,252 + clrb !OSMC ;[INF] 3, 1 +; line 287 : #endif +; line 288 : STOP( ); +$DGL 0,254 + stop ;[INF] 2, 3 +; line 289 : #ifdef _MCU_BSR_ +; line 290 : OSMC = 0x01; +$DGL 0,256 + oneb !OSMC ;[INF] 3, 1 +; line 291 : CKC = 0b00001000; +$DGL 0,257 + mov CKC,#08H ; 8 ;[INF] 3, 1 +; line 292 : #endif +; line 293 : +; line 294 : #endif +; line 295 : RTCIMK = 0; +$DGL 0,261 + clr1 MK1H.2 ;[INF] 3, 2 +; line 296 : // 起きる // +; line 297 : +; line 298 : // 起きる条件は +; line 299 : // ・KeyReturn割り込み（電源ボたん） +; line 300 : // ・RTCアラーム +; line 301 : // ・アダプタ挿抜 +; line 302 : system_status.pwr_state = OFF; // +$DGL 0,268 + oneb !_system_status ;[INF] 3, 1 +; line 303 : renge_task_interval_run_force = 1; +$DGL 0,269 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +; line 304 : KRMK = 1; +$DGL 0,270 + set1 MK1H.3 ;[INF] 3, 2 +; line 305 : return; +$DGL 0,271 + ret ;[INF] 1, 6 +??eb12_tsk_sys: +; line 306 : } +?L0038: +; line 307 : +; line 308 : default: +; line 309 : while( 1 ) +; line 310 : { +??bb14_tsk_sys: +; line 311 : NOP( ); +$DGL 0,277 + nop ;[INF] 1, 1 +??eb14_tsk_sys: +; line 312 : // あり得ないステート +; line 313 : } +$DGL 0,279 + br $?L0038 ;[INF] 2, 3 +??eb00_tsk_sys: +; line 314 : +; line 315 : } +?L0004: +; line 316 : } +$DGL 0,282 +??ef_tsk_sys: + ret ;[INF] 1, 6 +??ee_tsk_sys: +; line 317 : +; line 318 : +; line 319 : +; line 320 : /*******************************************************//** +; line 321 : PMICが電源異常で止めたか確認 +; line 322 : **********************************************************/ +; line 323 : static void chk_emergencyExit(){ +_chk_emergencyExit: +$DGL 1,166 +??bf_chk_emergencyExit: +; line 324 : #ifndef _PARRADIUM_ +; line 325 : static state; +; line 326 : +; line 327 : if( !RESET1_n ) +$DGL 0,5 + bt P0.0,$?L0049 ;[INF] 4, 5 +; line 328 : { +??bb00_chk_emergencyExit: +; line 329 : if( PM_chk_LDSW( ) == 0 ) +$DGL 0,7 + movw ax,#03H ; 3 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_read_a_byte ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0051 ;[INF] 2, 4 +; line 330 : { +??bb01_chk_emergencyExit: +; line 331 : // PMICが異常終了判断をした +; line 332 : system_status.pwr_state = OFF_TRIG; +$DGL 0,10 + clrb !_system_status ;[INF] 3, 1 +; line 333 : renge_task_interval_run_force = 1; +$DGL 0,11 + set1 _renge_task_interval_run_force ;[INF] 3, 2 +??eb01_chk_emergencyExit: +; line 334 : } +$DGL 0,12 + ret ;[INF] 1, 6 +?L0051: +; line 335 : else +; line 336 : { +??bb02_chk_emergencyExit: +; line 337 : if( state == 0 ) +$DGL 0,15 + clrw ax ;[INF] 1, 1 + cmpw ax,!?L0048 ; state ;[INF] 3, 1 + bnz $?L0050 ;[INF] 2, 4 +; line 338 : { +??bb03_chk_emergencyExit: +; line 339 : state = 1; +$DGL 0,17 + onew ax ;[INF] 1, 1 + movw !?L0048,ax ; state ;[INF] 3, 1 +; line 340 : // デバッガなりがリセットをかけた +; line 341 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, +; 0 ); +$DGL 0,19 + clrw ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#04H ; 4 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + mov x,#084H ; 132 ;[INF] 2, 1 + call !_iic_mcu_write_a_byte ;[INF] 3, 3 + addw sp,#04H ; 4 ;[INF] 2, 1 +; line 342 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] +; & 0b10011111 ); +$DGL 0,20 + mov a,!_vreg_ctr+15 ;[INF] 3, 1 + and a,#09FH ; 159 ;[INF] 2, 1 + mov !_vreg_ctr+15,a ;[INF] 3, 1 +; line 343 : vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ; +$DGL 0,21 + set1 !_vreg_ctr+32.1 ;[INF] 4, 2 +; line 344 : renge_task_immed_add( do_command0 ); +$DGL 0,22 + movw ax,#loww (_do_command0) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb03_chk_emergencyExit: +; line 345 : } +; line 346 : } +??eb02_chk_emergencyExit: +; line 347 : } +$DGL 0,25 +??eb00_chk_emergencyExit: + ret ;[INF] 1, 6 +?L0049: +; line 348 : else +; line 349 : { +??bb04_chk_emergencyExit: +; line 350 : state = 0; +$DGL 0,28 + clrw ax ;[INF] 1, 1 + movw !?L0048,ax ; state ;[INF] 3, 1 +??eb04_chk_emergencyExit: +; line 351 : } +?L0050: +; line 352 : #endif +; line 353 : } +$DGL 0,31 +??ef_chk_emergencyExit: + ret ;[INF] 1, 6 +??ee_chk_emergencyExit: +; line 354 : +; line 355 : +; line 356 : +; line 357 : +; line 358 : +; line 359 : /* ======================================================== +; line 360 : CPUからのスリープ要求 +; line 361 : 　ポーリングにしました。 +; line 362 : ======================================================== */ +; line 363 : /* +; line 364 : __interrupt void intp0_slp( ) +; line 365 : { // SLP +; line 366 : if( SLP_REQ ){ +; line 367 : system_status.pwr_state = SLEEP_TRIG; +; line 368 : }else{ +; line 369 : system_status.pwr_state = ON_TRIG; +; line 370 : if( PM_BL_set() != ERR_SUCCESS ){ +; line 371 : renge_task_interval_run_force = 1; +; line 372 : iic_mcu_stop(); +; line 373 : system_status.pwr_state = OFF_TRIG; +; line 374 : } +; line 375 : } +; line 376 : renge_task_interval_run_force = 1; +; line 377 : } +; line 378 : */ +; line 379 : +; line 380 : +; line 381 : +; line 382 : /*******************************************************//** +; line 383 : 全く意味ないですが、気分的な物で... +; line 384 : **********************************************************/ +; line 385 : task_status_immed tski_firm_update(){ +_tski_firm_update: +$DGL 1,193 +??bf_tski_firm_update: +; line 386 : firm_update(); +$DGL 0,2 + call !_firm_update ;[INF] 3, 3 +; line 387 : return( ERR_SUCCESS ); +$DGL 0,3 + clrw bc ;[INF] 1, 1 +; line 388 : } +$DGL 0,4 +??ef_tski_firm_update: + ret ;[INF] 1, 6 +??ee_tski_firm_update: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c +; +; $FUNC tsk_sys(35) +; void=(void) +; CODE SIZE= 433 bytes, CLOCK_SIZE= 384 clocks, STACK_SIZE= 12 bytes +; +; $CALL iic_mcu_start(80) +; void=(void) +; +; $CALL PM_init(83) +; void=(void) +; +; $CALL PM_sys_pow_on(85) +; bc=(void) +; +; $CALL iic_mcu_stop(88) +; void=(void) +; +; $CALL PM_LCD_vcom_set(100) +; bc=(void) +; +; $CALL LED_init(122) +; void=(void) +; +; $CALL IIC_ctr_Init(126) +; void=(void) +; +; $CALL set_irq(136) +; void=(int:ax, int:[sp+4]) +; +; $CALL IIC_twl_Init(138) +; void=(void) +; +; $CALL chk_emergencyExit(163) +; void=(void) +; +; $CALL iic_mcu_write_a_byte(173) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL chk_emergencyExit(178) +; void=(void) +; +; $CALL iic_mcu_write_a_byte(181) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL wait_ms(182) +; void=(int:ax) +; +; $CALL LED_stop(208) +; void=(void) +; +; $CALL IIC_ctr_Stop(209) +; void=(void) +; +; $CALL IIC_twl_Stop(210) +; void=(void) +; +; $CALL PM_sys_pow_off(235) +; bc=(void) +; +; $CALL iic_mcu_stop(278) +; void=(void) +; +; $FUNC chk_emergencyExit(323) +; void=(void) +; CODE SIZE= 73 bytes, CLOCK_SIZE= 68 clocks, STACK_SIZE= 8 bytes +; +; $CALL iic_mcu_read_a_byte(329) +; bc=(int:ax, int:[sp+4]) +; +; $CALL iic_mcu_write_a_byte(341) +; bc=(int:ax, int:[sp+4], int:[sp+6]) +; +; $CALL renge_task_immed_add(344) +; bc=(pointer:ax) +; +; $FUNC tski_firm_update(385) +; bc=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes +; +; $CALL firm_update(386) +; bc=(void) + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/vreg_ctr.asm b/branches/0.10(X3)/inter_asm/vreg_ctr.asm new file mode 100644 index 0000000..790e675 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/vreg_ctr.asm @@ -0,0 +1,1605 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_ctr.c +; In-file : vreg_ctr.c +; Asm-file : inter_asm\vreg_ctr.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 0A1H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, vreg_ctr.c +$DGS MOD_NAM, vreg_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H +$DGS AUX_TAG, 01H, 019H +$DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H +$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H +$DGS AUX_EOS, 013H, 01H +$DGS LAB_SYM, bs_S0105, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0105, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0106, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0106, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0104, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0104, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0102, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0102, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_S0103, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0103, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, bs_F0101, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_F0101, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 02DH, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 02AH, 00H, 02DH +$DGS END_FUN, ??ef_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0DH +$DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 059H, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 042H, 02H, 033H +$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 035H +$DGS BEG_BLK, ??bb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01CH, 00H, 039H +$DGS END_BLK, ??eb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS BEG_BLK, ??bb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02DH, 00H, 03DH +$DGS END_BLK, ??eb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02FH +$DGS BEG_BLK, ??bb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 036H, 00H, 041H +$DGS END_BLK, ??eb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 038H +$DGS BEG_BLK, ??bb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03AH, 00H, 045H +$DGS END_BLK, ??eb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 03CH +$DGS BEG_BLK, ??bb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 041H, 00H, 049H +$DGS END_BLK, ??eb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 044H +$DGS BEG_BLK, ??bb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 049H, 00H, 04DH +$DGS END_BLK, ??eb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 055H +$DGS BEG_BLK, ??bb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0D1H, 00H, 051H +$DGS END_BLK, ??eb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0D3H +$DGS BEG_BLK, ??bb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0D9H, 00H, 00H +$DGS END_BLK, ??eb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0E3H +$DGS END_BLK, ??eb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0E4H +$DGS END_FUN, ??ef_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0E6H +$DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 07DH, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0131H, 02H, 05FH +$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS STA_SYM, _rsub_temp, ?L0073, U, 0DH, 03H, 00H, 00H +$DGS BEG_BLK, ??bb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 06H, 00H, 063H +$DGS END_BLK, ??eb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 067H +$DGS END_BLK, ??eb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS BEG_BLK, ??bb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0EH, 00H, 06BH +$DGS END_BLK, ??eb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 010H +$DGS BEG_BLK, ??bb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 012H, 00H, 06FH +$DGS END_BLK, ??eb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS BEG_BLK, ??bb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 017H, 00H, 073H +$DGS END_BLK, ??eb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 019H +$DGS BEG_BLK, ??bb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 01BH, 00H, 077H +$DGS END_BLK, ??eb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 01FH +$DGS BEG_BLK, ??bb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 023H, 00H, 00H +$DGS END_BLK, ??eb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 027H +$DGS END_FUN, ??ef_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02AH +$DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 088H, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 0161H, 02H, 082H +$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 00H +$DGS END_BLK, ??eb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS END_FUN, ??ef_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 012H +$DGS GLV_SYM, _set_irq, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 0A1H, 00H, 00H +$DGS BEG_FUN, ??bf_set_irq, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 018AH, 04H, 08FH +$DGS FUN_ARG, _irqreg, 02H, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS FUN_ARG, _irq_flg, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H +$DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 00H, 00H +$DGS BEG_BLK, ??bb00_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 091H +$DGS BEG_BLK, ??bb01_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 07H, 00H, 095H +$DGS END_BLK, ??eb01_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 07H +$DGS BEG_BLK, ??bb02_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0AH, 00H, 099H +$DGS END_BLK, ??eb02_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0AH +$DGS BEG_BLK, ??bb03_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 00H +$DGS END_BLK, ??eb03_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS END_BLK, ??eb00_set_irq, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0CH +$DGS END_FUN, ??ef_set_irq, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0EH +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 026H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 060H, 060H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _irq_readed, U, U, 034CH, 027H, 00H, 00H +$DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _set_rtc, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 02H, 00H, 00H +$DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _acc_read, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _acc_write, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _hosu_read, U, U, 0CH, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 02H, 01H, 02H +$DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + + EXTRN _vreg_twl + EXTRN _set_rtc + EXTRN _tski_vcom_set + EXTRN _renge_task_immed_add + EXTRN _tski_firm_update + EXTRN _do_command0 + EXTRN _tski_PM_LCD_on + EXTRN _tski_PM_LCD_off + EXTRN _tski_PM_BL_set + EXTRN _acc_hosu_set + EXTRN _acc_read + EXTRN _acc_write + EXTRN _clear_hosu_hist + EXTRN _rtc_buf_reflesh + EXTRN _hosu_read + EXTRN _tski_mcu_info_read + EXTBIT _rtc_alarm_dirty + PUBLIC _vreg_ctr + PUBLIC _irq_readed + PUBLIC _vreg_ctr_init + PUBLIC _vreg_ctr_write + PUBLIC _vreg_ctr_read + PUBLIC _vreg_ctr_after_read + PUBLIC _set_irq + +@@BITS BSEG +_irq_readed DBIT + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + +@@INIT DSEG BASEP + +@@DATA DSEG BASEP +_vreg_ctr: DS (96) +?L0073: DS (2) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_S0105: + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,h ;[INF] 1, 1 + mov _vreg_ctr[b],a ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0105: + +ROM_CODE CSEG BASE +bs_S0106: + movw de,#loww (_vreg_twl+1) ;[INF] 3, 1 + mov a,[de] ;[INF] 1, 1 + or a,x ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_S0106: + +ROM_CODE CSEG BASE +bs_S0104: + mov c,a ;[INF] 1, 1 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov _vreg_ctr[b],a ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0104: + +ROM_CODE CSEG BASE +bs_F0102: + shrw ax,8 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + subw ax,#030H ; 48 ;[INF] 3, 1 + call !_set_rtc ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0102: + +ROM_CODE CSEG BASE +bs_S0103: + mov a,h ;[INF] 1, 1 + and a,#03FH ; 63 ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov _vreg_ctr[b],a ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0103: + +ROM_CODE CSEG BASE +bs_F0101: + and a,#03FH ; 63 ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + push ax ;[INF] 1, 1 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + subw ax,#030H ; 48 ;[INF] 3, 1 + call !_set_rtc ;[INF] 3, 3 + pop ax ;[INF] 1, 1 + ret ;[INF] 1, 6 +es_F0101: + +; *** Sub-Routine Information *** +; +; $SUB bs_F0101 +; CODE SIZE= 15 bytes +; +; $SUB bs_F0102 +; CODE SIZE= 13 bytes +; +; $SUB bs_S0103 +; CODE SIZE= 11 bytes +; +; $SUB bs_S0104 +; CODE SIZE= 8 bytes +; +; $SUB bs_S0105 +; CODE SIZE= 7 bytes +; +; $SUB bs_S0106 +; CODE SIZE= 8 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : +; line 3 : CTR MCU I2Cレジスタ +; line 4 : +; line 5 : ====================================================== */ +; line 6 : #include "incs.h" +; line 7 : #include "vreg_ctr.h" +; line 8 : #include "rtc.h" +; line 9 : #include "led.h" +; line 10 : #include "accero.h" +; line 11 : #include "pm.h" +; line 12 : +; line 13 : #include +; line 14 : #include "fsl_user.h" +; line 15 : +; line 16 : extern u8 mcu_info_read(); // task_misc.c +; line 17 : +; line 18 : +; line 19 : +; line 20 : // ******************************************************** +; line 21 : u8 vreg_ctr[VREG_C_ENDMARK_]; +; line 22 : +; line 23 : bit irq_readed; // AAA型のため。 +; line 24 : +; line 25 : extern bit update; +; line 26 : extern u16 pool[]; +; line 27 : +; line 28 : +; line 29 : // ******************************************************** +; line 30 : extern task_status_immed tski_firm_update(); +; line 31 : extern task_status_immed tski_mcu_info_read(); +; line 32 : +; line 33 : // ******************************************************** +; line 34 : #ifdef _MCU_BSR_ +; line 35 : #define IICAMK IICAMK1 +; line 36 : #endif +; line 37 : +; line 38 : +; line 39 : // ******************************************************** +; line 40 : // 非ゼロの初期値の指定が必要なアドレス +; line 41 : void vreg_ctr_init( ) +; line 42 : { + +ROM_CODE CSEG BASE +_vreg_ctr_init: +$DGL 1,39 +??bf_vreg_ctr_init: +; line 43 : vreg_ctr[VREG_C_LED_BRIGHT] = 0xFF; +$DGL 0,2 + mov !_vreg_ctr+40,#0FFH ; 255 ;[INF] 4, 1 +; line 44 : +; line 45 : #ifdef _PMIC_TWL_ +; line 46 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR; +; line 47 : #else +; line 48 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR | 0x10; +$DGL 0,7 + mov !_vreg_ctr,#010H ; 16 ;[INF] 4, 1 +; line 49 : #endif +; line 50 : vreg_ctr[VREG_C_MCU_VER_MINOR] = MCU_VER_MINOR; +$DGL 0,9 + mov !_vreg_ctr+1,#010H ; 16 ;[INF] 4, 1 +; line 51 : +; line 52 : vreg_ctr[VREG_C_VCOM_T] = VCOM_DEFAULT_T; +$DGL 0,11 + mov !_vreg_ctr+3,#05CH ; 92 ;[INF] 4, 1 +; line 53 : vreg_ctr[VREG_C_VCOM_B] = VCOM_DEFAULT_B; +$DGL 0,12 + mov !_vreg_ctr+4,#05FH ; 95 ;[INF] 4, 1 +; line 54 : } +$DGL 0,13 +??ef_vreg_ctr_init: + ret ;[INF] 1, 6 +??ee_vreg_ctr_init: +; line 55 : +; line 56 : +; line 57 : +; line 58 : +; line 59 : // ******************************************************** +; line 60 : // I2C仮想レジスタに書きます。 +; line 61 : //　引数 adrs は内部アドレス +; line 62 : // 　書けないアドレスにアクセスした場合、何もしません。 +; line 63 : // ●書き込んだ結果、I2C_mcu通信が発生する場合、renge_task_immed +; _add() +; line 64 : // を使用しないと、I2C_mcu使用中でエラー終了した場合にリトライし +; ません。 +; line 65 : void vreg_ctr_write( u8 adrs, u8 data ) +; line 66 : { +_vreg_ctr_write: +$DGL 1,45 + push hl ;[INF] 1, 1 + mov a,[sp+6] ;[INF] 2, 1 + movw hl,ax ;[INF] 1, 1 +??bf_vreg_ctr_write: +; line 67 : if( adrs >= VREG_C_ENDMARK_ ) +$DGL 0,2 + mov a,l ;[INF] 1, 1 + cmp a,#060H ; 96 ;[INF] 2, 1 + skc ;[INF] 2, 1 + br !?L0067 ;[INF] 3, 3 +; line 68 : return; +; line 69 : +; line 70 : switch ( adrs ) +$DGL 0,5 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,de ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0008 ;[INF] 3, 3 + decw ax ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + skh ;[INF] 2, 1 + br !?L0009 ;[INF] 3, 3 + decw ax ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + skh ;[INF] 2, 1 + br !?L0010 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0011 ;[INF] 3, 3 + subw ax,#011H ; 17 ;[INF] 3, 1 + subw ax,#05H ; 5 ;[INF] 3, 1 + sknc ;[INF] 2, 1 + br !?L0012 ;[INF] 3, 3 + subw ax,#03H ; 3 ;[INF] 3, 1 + sknz ;[INF] 2, 1 + br !?L0013 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0015 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0014 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0038 ;[INF] 3, 3 + decw ax ;[INF] 1, 1 + subw ax,#04H ; 4 ;[INF] 3, 1 + sknc ;[INF] 2, 1 + br !?L0016 ;[INF] 3, 3 + subw ax,#00H ; 0 ;[INF] 3, 1 + sknz ;[INF] 2, 1 + br !?L0018 ;[INF] 3, 3 + decw ax ;[INF] 1, 1 + subw ax,#05H ; 5 ;[INF] 3, 1 + sknc ;[INF] 2, 1 + br !?L0019 ;[INF] 3, 3 + subw ax,de ;[INF] 1, 1 + subw ax,bc ;[INF] 1, 1 + skh ;[INF] 2, 1 + br !?L0020 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0021 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0022 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0023 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0024 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0025 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0026 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0027 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0028 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0029 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0030 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0031 ;[INF] 3, 3 + subw ax,#04H ; 4 ;[INF] 3, 1 + sknz ;[INF] 2, 1 + br !?L0032 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0033 ;[INF] 3, 3 + subw ax,de ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0034 ;[INF] 3, 3 + subw ax,bc ;[INF] 1, 1 + sknz ;[INF] 2, 1 + br !?L0035 ;[INF] 3, 3 + subw ax,#07H ; 7 ;[INF] 3, 1 + subw ax,#03H ; 3 ;[INF] 3, 1 + sknc ;[INF] 2, 1 + br !?L0036 ;[INF] 3, 3 + subw ax,#00H ; 0 ;[INF] 3, 1 + sknz ;[INF] 2, 1 + br !?L0037 ;[INF] 3, 3 + subw ax,de ;[INF] 1, 1 + subw ax,#010H ; 16 ;[INF] 3, 1 + sknc ;[INF] 2, 1 + br !?L0017 ;[INF] 3, 3 + br !?L0067 ;[INF] 3, 3 +; line 71 : { +??bb00_vreg_ctr_write: +; line 72 : +; line 73 : case ( VREG_C_MCU_STATUS ): +?L0008: +; line 74 : vreg_ctr[adrs] = data; +$DGL 0,9 + call !bs_S0105 ;[INF] 3, 3 +; line 75 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( ( data & 0xC0 ) >> +; 6 ); +$DGL 0,10 + and a,#0C0H ; 192 ;[INF] 2, 1 + shr a,6 ;[INF] 2, 1 + mov !_vreg_twl+3,a ;[INF] 3, 1 +; line 76 : break; +$DGL 0,11 + br !?L0067 ;[INF] 3, 3 +; line 77 : +; line 78 : case ( VREG_C_VCOM_T ): +?L0009: +; line 79 : case ( VREG_C_VCOM_B ): +; line 80 : renge_task_immed_add( tski_vcom_set ); +$DGL 0,15 + movw ax,#loww (_tski_vcom_set) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 81 : vreg_ctr[adrs] = data; +$DGL 0,16 + call !bs_S0105 ;[INF] 3, 3 +; line 82 : break; +$DGL 0,17 + br !?L0067 ;[INF] 3, 3 +; line 83 : +; line 84 : case ( VREG_C_DBG1 ): +?L0010: +; line 85 : case ( VREG_C_DBG2 ): +; line 86 : vreg_ctr[adrs] = data; +$DGL 0,21 + call !bs_S0105 ;[INF] 3, 3 +; line 87 : break; +$DGL 0,22 + br !?L0067 ;[INF] 3, 3 +; line 88 : case ( VREG_C_DBG3 ): +?L0011: +; line 89 : vreg_ctr[adrs] = data; +$DGL 0,24 + call !bs_S0105 ;[INF] 3, 3 +; line 90 : if( ( vreg_ctr[VREG_C_DBG1] == 'j' ) +; line 91 : && ( vreg_ctr[VREG_C_DBG2] == 'h' ) +; line 92 : && ( data == 'l' ) ) +$DGL 0,27 + cmp !_vreg_ctr+5,#06AH ; 106 ;[INF] 4, 1 + bnz $?L0041 ;[INF] 2, 4 + cmp !_vreg_ctr+6,#068H ; 104 ;[INF] 4, 1 + bnz $?L0041 ;[INF] 2, 4 + cmp a,#06CH ; 108 ;[INF] 2, 1 + bnz $?L0041 ;[INF] 2, 4 +; line 93 : { +??bb01_vreg_ctr_write: +; line 94 : renge_task_immed_add( tski_firm_update ); +$DGL 0,29 + movw ax,#loww (_tski_firm_update) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 95 : IICAMK = 1; +$DGL 0,30 + set1 MK2H.3 ;[INF] 3, 2 +??eb01_vreg_ctr_write: +; line 96 : } +?L0041: +; line 97 : break; +$DGL 0,32 + br !?L0067 ;[INF] 3, 3 +; line 98 : +; line 99 : case ( VREG_C_IRQ_MASK0 ): +?L0012: +; line 100 : case ( VREG_C_IRQ_MASK1 ): +; line 101 : case ( VREG_C_IRQ_MASK2 ): +; line 102 : case ( VREG_C_IRQ_MASK3 ): +; line 103 : case ( VREG_C_IRQ_MASK4 ): +; line 104 : vreg_ctr[adrs] = data; +$DGL 0,39 + call !bs_S0105 ;[INF] 3, 3 +; line 105 : break; +$DGL 0,40 + br !?L0067 ;[INF] 3, 3 +; line 106 : +; line 107 : case ( VREG_C_COMMAND0 ): +?L0013: +; line 108 : vreg_ctr[adrs] |= data; +$DGL 0,43 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,[de] ;[INF] 1, 1 + or a,h ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 109 : if( data != 0 ) +$DGL 0,44 + mov a,h ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0043 ;[INF] 2, 4 +; line 110 : { +??bb02_vreg_ctr_write: +; line 111 : renge_task_immed_add( do_command0 ); +$DGL 0,46 + movw ax,#loww (_do_command0) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb02_vreg_ctr_write: +; line 112 : } +?L0043: +; line 113 : break; +$DGL 0,48 + br !?L0067 ;[INF] 3, 3 +; line 114 : +; line 115 : case ( VREG_C_COMMAND2 ): +?L0014: +; line 116 : // こちらからの完了割り込みを待ってくれないそうです。 #- +; ω-) 何のための割り込みだ +; line 117 : // 液晶電源 +; line 118 : if(( data & REG_BIT_CMD_LCD_ON ) != 0 ) +$DGL 0,53 + mov a,h ;[INF] 1, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0045 ;[INF] 2, 4 +; line 119 : { +??bb03_vreg_ctr_write: +; line 120 : renge_task_immed_add( tski_PM_LCD_on ); +$DGL 0,55 + movw ax,#loww (_tski_PM_LCD_on) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb03_vreg_ctr_write: +; line 121 : } +$DGL 0,56 + br $?L0047 ;[INF] 2, 3 +?L0045: +; line 122 : else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 ) +$DGL 0,57 + mov a,h ;[INF] 1, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0047 ;[INF] 2, 4 +; line 123 : { +??bb04_vreg_ctr_write: +; line 124 : renge_task_immed_add( tski_PM_LCD_off ); +$DGL 0,59 + movw ax,#loww (_tski_PM_LCD_off) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb04_vreg_ctr_write: +; line 125 : } +?L0047: +; line 126 : +; line 127 : // バックライト設定 +; line 128 : /// 今のところさらに細かくは分けないけど… +; line 129 : if(( data & REG_BITS_CMD_BL ) != 0 ) +$DGL 0,64 + mov a,h ;[INF] 1, 1 + and a,#03CH ; 60 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0049 ;[INF] 2, 4 +; line 130 : { +??bb05_vreg_ctr_write: +; line 131 : vreg_ctr[adrs] = ( data & REG_BITS_CMD_BL ); +$DGL 0,66 + mov a,h ;[INF] 1, 1 + and a,#03CH ; 60 ;[INF] 2, 1 + call !bs_S0104 ;[INF] 3, 3 +; line 132 : renge_task_immed_add( tski_PM_BL_set ); +$DGL 0,67 + movw ax,#loww (_tski_PM_BL_set) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +??eb05_vreg_ctr_write: +; line 133 : } +?L0049: +; line 134 : break; +$DGL 0,69 + br !?L0067 ;[INF] 3, 3 +; line 135 : +; line 136 : case ( VREG_C_COMMAND1 ): +?L0015: +; line 137 : if( data != 0 ) +$DGL 0,72 + mov a,h ;[INF] 1, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0051 ;[INF] 2, 4 +; line 138 : { +??bb06_vreg_ctr_write: +; line 139 : // TWLに割り込みを入れる +; line 140 : /// 実際に割り込みを入れるのはSoC +; line 141 : vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT +; _SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; +; //pwsw_det +$DGL 0,76 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0053 ;[INF] 2, 4 + movw ax,#08H ; 8 ;[INF] 3, 1 + br $?L0054 ;[INF] 2, 3 +?L0053: + clrw ax ;[INF] 1, 1 +?L0054: + mov a,x ;[INF] 1, 1 + mov !_vreg_twl+1,a ;[INF] 3, 1 +; line 142 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT +; _SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; +; //reset_req +$DGL 0,77 + mov a,h ;[INF] 1, 1 + and a,#02H ; 2 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0055 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + br $?L0056 ;[INF] 2, 3 +?L0055: + clrw ax ;[INF] 1, 1 +?L0056: + call !bs_S0106 ;[INF] 3, 3 +; line 143 : +; line 144 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT +; _SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //of +; f_req +$DGL 0,79 + mov a,h ;[INF] 1, 1 + and a,#04H ; 4 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0057 ;[INF] 2, 4 + onew ax ;[INF] 1, 1 + incw ax ;[INF] 1, 1 + br $?L0058 ;[INF] 2, 3 +?L0057: + clrw ax ;[INF] 1, 1 +?L0058: + call !bs_S0106 ;[INF] 3, 3 +; line 145 : +; line 146 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT +; _SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; +; //batt_low +$DGL 0,81 + mov a,h ;[INF] 1, 1 + and a,#08H ; 8 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0059 ;[INF] 2, 4 + movw ax,#020H ; 32 ;[INF] 3, 1 + br $?L0060 ;[INF] 2, 3 +?L0059: + clrw ax ;[INF] 1, 1 +?L0060: + call !bs_S0106 ;[INF] 3, 3 +; line 147 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT +; _SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; +; //batt_empty +$DGL 0,82 + mov a,h ;[INF] 1, 1 + and a,#010H ; 16 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0061 ;[INF] 2, 4 + movw ax,#010H ; 16 ;[INF] 3, 1 + br $?L0062 ;[INF] 2, 3 +?L0061: + clrw ax ;[INF] 1, 1 +?L0062: + call !bs_S0106 ;[INF] 3, 3 +; line 148 : +; line 149 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT +; _SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00 +; ; //vol_changed +$DGL 0,84 + mov a,h ;[INF] 1, 1 + and a,#020H ; 32 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0063 ;[INF] 2, 4 + movw ax,#040H ; 64 ;[INF] 3, 1 + br $?L0064 ;[INF] 2, 3 +?L0063: + clrw ax ;[INF] 1, 1 +?L0064: + call !bs_S0106 ;[INF] 3, 3 +??eb06_vreg_ctr_write: +; line 150 : } +?L0051: +; line 151 : break; +$DGL 0,86 + br !?L0067 ;[INF] 3, 3 +; line 152 : +; line 153 : case ( VREG_C_DBG20 ): +?L0016: +; line 154 : case ( VREG_C_DBG21 ): +; line 155 : case ( VREG_C_DBG22 ): +; line 156 : case ( VREG_C_DBG23 ): +; line 157 : vreg_ctr[adrs] = data; +$DGL 0,92 + call !bs_S0105 ;[INF] 3, 3 +; line 158 : break; +$DGL 0,93 + br !?L0067 ;[INF] 3, 3 +; line 159 : +; line 160 : case ( VREG_C_FREE_0 ): +?L0017: +; line 161 : case ( VREG_C_FREE_1 ): +; line 162 : case ( VREG_C_FREE_2 ): +; line 163 : case ( VREG_C_FREE_3 ): +; line 164 : case ( VREG_C_FREE_4 ): +; line 165 : case ( VREG_C_FREE_5 ): +; line 166 : case ( VREG_C_FREE_6 ): +; line 167 : case ( VREG_C_FREE_7 ): +; line 168 : case ( VREG_C_FREE_8 ): +; line 169 : case ( VREG_C_FREE_9 ): +; line 170 : case ( VREG_C_FREE_A ): +; line 171 : case ( VREG_C_FREE_B ): +; line 172 : case ( VREG_C_FREE_C ): +; line 173 : case ( VREG_C_FREE_D ): +; line 174 : case ( VREG_C_FREE_E ): +; line 175 : case ( VREG_C_FREE_F ): +; line 176 : vreg_ctr[adrs] = data; +$DGL 0,111 + call !bs_S0105 ;[INF] 3, 3 +; line 177 : break; +$DGL 0,112 + br !?L0067 ;[INF] 3, 3 +; line 178 : +; line 179 : case ( VREG_C_LED_BRIGHT ): +?L0018: +; line 180 : vreg_ctr[adrs] = data; +$DGL 0,115 + call !bs_S0105 ;[INF] 3, 3 +; line 181 : break; +$DGL 0,116 + br !?L0067 ;[INF] 3, 3 +; line 182 : +; line 183 : case ( VREG_C_LED_POW ): +?L0019: +; line 184 : case ( VREG_C_LED_WIFI ): +; line 185 : case ( VREG_C_LED_CAM ): +; line 186 : case ( VREG_C_LED_TUNE ): +; line 187 : case ( VREG_C_LED_NOTIFY ): +; line 188 : vreg_ctr[adrs] = data & 0x0F; +$DGL 0,123 + mov a,h ;[INF] 1, 1 + and a,#0FH ; 15 ;[INF] 2, 1 + call !bs_S0104 ;[INF] 3, 3 +; line 189 : break; +$DGL 0,124 + br !?L0067 ;[INF] 3, 3 +; line 190 : +; line 191 : /// 非同期で動いているためここでは書かない。 +; line 192 : // 予約するだけでstopで書く +; line 193 : case ( VREG_C_RTC_SEC ): +?L0020: +; line 194 : case ( VREG_C_RTC_MIN ): +; line 195 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F ); +$DGL 0,130 + mov a,h ;[INF] 1, 1 + and a,#07FH ; 127 ;[INF] 2, 1 + call !bs_F0102 ;[INF] 3, 3 +; line 196 : break; +$DGL 0,131 + br !?L0067 ;[INF] 3, 3 +; line 197 : +; line 198 : case ( VREG_C_RTC_HOUR ): +?L0021: +; line 199 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); +$DGL 0,134 + mov a,h ;[INF] 1, 1 + call !bs_F0101 ;[INF] 3, 3 +; line 200 : break; +$DGL 0,135 + br !?L0067 ;[INF] 3, 3 +; line 201 : +; line 202 : case ( VREG_C_RTC_YOBI ): +?L0022: +; line 203 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 ); +$DGL 0,138 + mov a,h ;[INF] 1, 1 + and a,#07H ; 7 ;[INF] 2, 1 + call !bs_F0102 ;[INF] 3, 3 +; line 204 : break; +$DGL 0,139 + br !?L0067 ;[INF] 3, 3 +; line 205 : +; line 206 : case ( VREG_C_RTC_DAY ): +?L0023: +; line 207 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); +$DGL 0,142 + mov a,h ;[INF] 1, 1 + call !bs_F0101 ;[INF] 3, 3 +; line 208 : break; +$DGL 0,143 + br !?L0067 ;[INF] 3, 3 +; line 209 : +; line 210 : case ( VREG_C_RTC_MONTH ): +?L0024: +; line 211 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F ); +$DGL 0,146 + mov a,h ;[INF] 1, 1 + and a,#01FH ; 31 ;[INF] 2, 1 + call !bs_F0102 ;[INF] 3, 3 +; line 212 : break; +$DGL 0,147 + br $?L0067 ;[INF] 2, 3 +; line 213 : +; line 214 : case ( VREG_C_RTC_YEAR ): +?L0025: +; line 215 : set_rtc( adrs - VREG_C_RTC_SEC, data ); +$DGL 0,150 + mov a,h ;[INF] 1, 1 + call !bs_F0102 ;[INF] 3, 3 +; line 216 : break; +$DGL 0,151 + br $?L0067 ;[INF] 2, 3 +; line 217 : +; line 218 : case ( VREG_C_RTC_COMP ): +?L0026: +; line 219 : vreg_ctr[adrs] = data; +$DGL 0,154 + call !bs_S0105 ;[INF] 3, 3 +; line 220 : SUBCUD = data; +$DGL 0,155 + mov SUBCUD,a ;[INF] 2, 1 +; line 221 : break; +$DGL 0,156 + br $?L0067 ;[INF] 2, 3 +; line 222 : +; line 223 : case ( VREG_C_RTC_ALARM_MIN ): +?L0027: +; line 224 : vreg_ctr[adrs] = ( data & 0x7F ); +$DGL 0,159 + mov a,h ;[INF] 1, 1 + and a,#07FH ; 127 ;[INF] 2, 1 + call !bs_S0104 ;[INF] 3, 3 +; line 225 : rtc_alarm_dirty = 1; +$DGL 0,160 + set1 _rtc_alarm_dirty ;[INF] 3, 2 +; line 226 : break; +$DGL 0,161 + br $?L0067 ;[INF] 2, 3 +; line 227 : +; line 228 : case ( VREG_C_RTC_ALARM_HOUR ): +?L0028: +; line 229 : vreg_ctr[adrs] = ( data & 0x3F ); +$DGL 0,164 + call !bs_S0103 ;[INF] 3, 3 +; line 230 : rtc_alarm_dirty = 1; +$DGL 0,165 + set1 _rtc_alarm_dirty ;[INF] 3, 2 +; line 231 : break; +$DGL 0,166 + br $?L0067 ;[INF] 2, 3 +; line 232 : +; line 233 : // 書くだけでよい +; line 234 : case ( VREG_C_RTC_ALARM_DAY ): +?L0029: +; line 235 : vreg_ctr[adrs] = ( data & 0x3F ); +$DGL 0,170 + call !bs_S0103 ;[INF] 3, 3 +; line 236 : break; +$DGL 0,171 + br $?L0067 ;[INF] 2, 3 +; line 237 : +; line 238 : case ( VREG_C_RTC_ALARM_MONTH ): +?L0030: +; line 239 : vreg_ctr[adrs] = ( data & 0x1F ); +$DGL 0,174 + mov a,h ;[INF] 1, 1 + and a,#01FH ; 31 ;[INF] 2, 1 + call !bs_S0104 ;[INF] 3, 3 +; line 240 : break; +$DGL 0,175 + br $?L0067 ;[INF] 2, 3 +; line 241 : +; line 242 : case ( VREG_C_RTC_ALARM_YEAR ): +?L0031: +; line 243 : vreg_ctr[adrs] = data; +$DGL 0,178 + call !bs_S0105 ;[INF] 3, 3 +; line 244 : break; +$DGL 0,179 + br $?L0067 ;[INF] 2, 3 +; line 245 : +; line 246 : +; line 247 : case ( VREG_C_ACC_CONFIG ): +?L0032: +; line 248 : vreg_ctr[adrs] = data; +$DGL 0,183 + call !bs_S0105 ;[INF] 3, 3 +; line 249 : renge_task_immed_add( acc_hosu_set ); +$DGL 0,184 + movw ax,#loww (_acc_hosu_set) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 250 : break; +$DGL 0,185 + br $?L0067 ;[INF] 2, 3 +; line 251 : +; line 252 : case ( VREG_C_ACC_R_ADRS ): +?L0033: +; line 253 : vreg_ctr[adrs] = data; +$DGL 0,188 + call !bs_S0105 ;[INF] 3, 3 +; line 254 : renge_task_immed_add( acc_read ); +$DGL 0,189 + movw ax,#loww (_acc_read) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 255 : break; +$DGL 0,190 + br $?L0067 ;[INF] 2, 3 +; line 256 : +; line 257 : case ( VREG_C_ACC_W_ADRS ): +?L0034: +; line 258 : vreg_ctr[adrs] = data; +$DGL 0,193 + call !bs_S0105 ;[INF] 3, 3 +; line 259 : break; +$DGL 0,194 + br $?L0067 ;[INF] 2, 3 +; line 260 : +; line 261 : case ( VREG_C_ACC_W_BUF ): +?L0035: +; line 262 : vreg_ctr[adrs] = data; +$DGL 0,197 + call !bs_S0105 ;[INF] 3, 3 +; line 263 : renge_task_immed_add( acc_write ); +$DGL 0,198 + movw ax,#loww (_acc_write) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 264 : break; +$DGL 0,199 + br $?L0067 ;[INF] 2, 3 +; line 265 : +; line 266 : case ( VREG_C_ACC_HOSU_L ): +?L0036: +; line 267 : case ( VREG_C_ACC_HOSU_M ): +; line 268 : case ( VREG_C_ACC_HOSU_H ): +; line 269 : vreg_ctr[adrs] = data; +$DGL 0,204 + call !bs_S0105 ;[INF] 3, 3 +; line 270 : break; +$DGL 0,205 + br $?L0067 ;[INF] 2, 3 +; line 271 : +; line 272 : case ( VREG_C_ACC_HOSU_SETTING ): +?L0037: +; line 273 : if( ( data & 0x01 ) != 0 ) +$DGL 0,208 + mov a,h ;[INF] 1, 1 + and a,#01H ; 1 ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bz $?L0067 ;[INF] 2, 4 +; line 274 : { +??bb07_vreg_ctr_write: +; line 275 : clear_hosu_hist(); // 履歴クリア +$DGL 0,210 + call !_clear_hosu_hist ;[INF] 3, 3 +??eb07_vreg_ctr_write: +; line 276 : } +; line 277 : break; +$DGL 0,212 + br $?L0067 ;[INF] 2, 3 +; line 278 : +; line 279 : case ( VREG_C_COMMAND3 ): +?L0038: +; line 280 : vreg_ctr[adrs] = data; +$DGL 0,215 + call !bs_S0105 ;[INF] 3, 3 +; line 281 : switch ( data ) +$DGL 0,216 + shrw ax,8 ;[INF] 2, 1 + subw ax,#072H ; 114 ;[INF] 3, 1 + bz $?L0068 ;[INF] 2, 4 + subw ax,#05H ; 5 ;[INF] 3, 1 + sknz ;[INF] 2, 1 +; line 282 : { +??bb08_vreg_ctr_write: +; line 283 : case ( 'r' ): +?L0068: +; line 284 : // 割り込みルーチンからFSLライブラリを呼ぶのは禁止の +; ため +; line 285 : // renge_task_immed_add( tski_mcu_reset ); +; line 286 : // break; +; line 287 : +; line 288 : case ( 'w' ): +; line 289 : // WDTで再起動（テスト向け） +; line 290 : WDTE = 0xAA; +$DGL 0,225 + mov WDTE,#0AAH ; 170 ;[INF] 3, 1 +; line 291 : break; +??eb08_vreg_ctr_write: +; line 292 : } +?L0067: +??eb00_vreg_ctr_write: +; line 293 : } +; line 294 : return; +; line 295 : } +$DGL 0,230 +??ef_vreg_ctr_write: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_vreg_ctr_write: +; line 296 : +; line 297 : +; line 298 : +; line 299 : // ******************************************************** +; line 300 : // I2C仮想レジスタから読みます。 +; line 301 : // 戻り： xx データ +; line 302 : // 注意：次のアドレスの準備で呼ばれる ので、 +; line 303 : // リードされたらクリアなどは気をつける +; line 304 : u8 vreg_ctr_read( u8 adrs ) +; line 305 : { +_vreg_ctr_read: +$DGL 1,89 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_vreg_ctr_read: +; line 306 : static u16 rsub_temp; +; line 307 : +; line 308 : // RTCは読み出し途中に繰り上がるのを避けるため +; line 309 : if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR +; ) ) +$DGL 0,5 + mov a,l ;[INF] 1, 1 + cmp a,#030H ; 48 ;[INF] 2, 1 + bc $?L0074 ;[INF] 2, 4 + cmp a,#037H ; 55 ;[INF] 2, 1 + bnc $?L0074 ;[INF] 2, 4 +; line 310 : { +??bb00_vreg_ctr_read: +; line 311 : rtc_buf_reflesh( ); +$DGL 0,7 + call !_rtc_buf_reflesh ;[INF] 3, 3 +??eb00_vreg_ctr_read: +; line 312 : } +$DGL 0,8 + br $?L0084 ;[INF] 2, 3 +?L0074: +; line 313 : else if( adrs == VREG_C_MCU_STATUS ) +$DGL 0,9 + mov a,l ;[INF] 1, 1 + cmp a,#02H ; 2 ;[INF] 2, 1 + bnz $?L0076 ;[INF] 2, 4 +; line 314 : { +??bb01_vreg_ctr_read: +; line 315 : return( vreg_ctr[ VREG_C_MCU_STATUS ] | ( ( vreg_twl[ RE +; G_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) ); +$DGL 0,11 + mov a,!_vreg_twl+3 ;[INF] 3, 1 + and a,#03H ; 3 ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + shlw ax,6 ;[INF] 2, 1 + xch a,x ;[INF] 1, 1 + or a,!_vreg_ctr+2 ;[INF] 3, 1 + xch a,x ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0072 ;[INF] 2, 3 +??eb01_vreg_ctr_read: +; line 316 : } +?L0076: +; line 317 : else if( adrs == VREG_C_ACC_HOSU_HIST ) +$DGL 0,13 + mov a,l ;[INF] 1, 1 + cmp a,#04FH ; 79 ;[INF] 2, 1 + bnz $?L0078 ;[INF] 2, 4 +; line 318 : { +??bb02_vreg_ctr_read: +; line 319 : return( hosu_read() ); +$DGL 0,15 + call !_hosu_read ;[INF] 3, 3 + clrb b ;[INF] 1, 1 + br $?L0072 ;[INF] 2, 3 +??eb02_vreg_ctr_read: +; line 320 : } +?L0078: +; line 321 : else if( adrs == VREG_C_RTC_SEC_FINE_L ) +$DGL 0,17 + mov a,l ;[INF] 1, 1 + cmp a,#03DH ; 61 ;[INF] 2, 1 + bnz $?L0080 ;[INF] 2, 4 +; line 322 : { +??bb03_vreg_ctr_read: +; line 323 : rsub_temp = RSUBC; +$DGL 0,19 + movw ax,RSUBC ;[INF] 2, 1 + movw !?L0073,ax ; rsub_temp ;[INF] 3, 1 +; line 324 : return( (u8)( rsub_temp & 0xFF ) ); +$DGL 0,20 + mov x,!?L0073 ; rsub_temp ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0072 ;[INF] 2, 3 +??eb03_vreg_ctr_read: +; line 325 : } +?L0080: +; line 326 : else if( adrs == VREG_C_RTC_SEC_FINE_H ) +$DGL 0,22 + mov a,l ;[INF] 1, 1 + cmp a,#03EH ; 62 ;[INF] 2, 1 + bnz $?L0082 ;[INF] 2, 4 +; line 327 : { +??bb04_vreg_ctr_read: +; line 328 : return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) ); +$DGL 0,24 + mov x,!?L0073+1 ; rsub_temp ;[INF] 3, 1 + clrb a ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0072 ;[INF] 2, 3 +??eb04_vreg_ctr_read: +; line 329 : } +?L0082: +; line 330 : else if( adrs == VREG_C_INFO ) +$DGL 0,26 + mov a,l ;[INF] 1, 1 + cmp a,#07FH ; 127 ;[INF] 2, 1 + bnz $?L0084 ;[INF] 2, 4 +; line 331 : { +??bb05_vreg_ctr_read: +; line 332 : renge_task_immed_add( tski_mcu_info_read ); +$DGL 0,28 + movw ax,#loww (_tski_mcu_info_read) ;[INF] 3, 1 + call !_renge_task_immed_add ;[INF] 3, 3 +; line 333 : IICAMK = 1; +$DGL 0,29 + set1 MK2H.3 ;[INF] 3, 2 +; line 334 : return( 0x4A ); +$DGL 0,30 + movw bc,#04AH ; 74 ;[INF] 3, 1 + br $?L0072 ;[INF] 2, 3 +??eb05_vreg_ctr_read: +; line 335 : } +?L0084: +; line 336 : +; line 337 : #if 1 +; line 338 : if( adrs >= VREG_C_ENDMARK_ ) +$DGL 0,34 + mov a,l ;[INF] 1, 1 + cmp a,#060H ; 96 ;[INF] 2, 1 + bc $?L0086 ;[INF] 2, 4 +; line 339 : { +??bb06_vreg_ctr_read: +; line 340 : // VREG_C_INFO > VREG_C_ENDMARK_ なので +; line 341 : // いじるときは注意 +; line 342 : return( 0xEE ); +$DGL 0,38 + movw bc,#0EEH ; 238 ;[INF] 3, 1 + br $?L0072 ;[INF] 2, 3 +??eb06_vreg_ctr_read: +; line 343 : } +?L0086: +; line 344 : #endif +; line 345 : return ( vreg_ctr[adrs] ); +$DGL 0,41 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,_vreg_ctr[b] ;[INF] 3, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 +; line 346 : } +?L0072: +$DGL 0,42 +??ef_vreg_ctr_read: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_vreg_ctr_read: +; line 347 : +; line 348 : +; line 349 : +; line 350 : // ******************************************************** +; line 351 : // I2C仮想レジスタから読まれて何かするレジスタ +; line 352 : void vreg_ctr_after_read( u8 adrs ) +; line 353 : { +_vreg_ctr_after_read: +$DGL 1,125 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_vreg_ctr_after_read: +; line 354 : +; line 355 : // 割り込みフラグはリードでクリア +; line 356 : switch( adrs ) +$DGL 0,4 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + subw ax,#010H ; 16 ;[INF] 3, 1 + subw ax,#05H ; 5 ;[INF] 3, 1 + bnc $?L0092 ;[INF] 2, 4 +; line 357 : { +??bb00_vreg_ctr_after_read: +; line 358 : case VREG_C_IRQ0: +; line 359 : case VREG_C_IRQ1: +; line 360 : case VREG_C_IRQ2: +; line 361 : case VREG_C_IRQ3: +; line 362 : case VREG_C_IRQ4: +; line 363 : vreg_ctr[ adrs ] = 0; +$DGL 0,11 + mov a,l ;[INF] 1, 1 + mov c,a ;[INF] 1, 1 + mov _vreg_ctr[c],#00H ; 0 ;[INF] 4, 1 +; line 364 : irq_readed = 1; +$DGL 0,12 + set1 _irq_readed ;[INF] 3, 2 +; line 365 : break; +; line 366 : +; line 367 : default: +?L0092: +; line 368 : break; +??eb00_vreg_ctr_after_read: +; line 369 : } +; line 370 : } +$DGL 0,18 +??ef_vreg_ctr_after_read: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_vreg_ctr_after_read: +; line 371 : +; line 372 : +; line 373 : +; line 374 : +; line 375 : +; line 376 : +; line 377 : /*************************************************************** +; *************** +; line 378 : 割り込みを入れる +; line 379 : 割り込みマスクが必要と言うことでこんな事をする羽目になりました +; line 380 : *************************************************************** +; **************/ +; line 381 : #if 0 +; line 382 : // マスクされてたら、フラグは立てるが、割り込みは入れない。 +; line 383 : #define set_irq( irqreg, bitpos ) \ +; line 384 : { \ +; line 385 : vreg_ctr[ irqreg ] |= bitpos; \ +; line 386 : if( ( vreg_ctr[ irqreg+8 ] & bitpos ) == 0 ){ \ +; line 387 : IRQ0_ast; \ +; line 388 : } \ +; line 389 : } +; line 390 : #endif +; line 391 : +; line 392 : // マスクされてたら、フラグも立てず、割り込みも入れない。 +; line 393 : void set_irq( u8 irqreg, u8 irq_flg ) +; line 394 : { +_set_irq: +$DGL 1,136 + di ;[INF] 3, 4 + push hl ;[INF] 1, 1 + push ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + movw hl,sp ;[INF] 3, 1 +??bf_set_irq: +; line 395 : u8 tot; +; line 396 : +; line 397 : DI(); +; line 398 : if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 ){ +$DGL 0,5 + mov a,[hl+2] ; irqreg ;[INF] 2, 1 + mov b,a ;[INF] 1, 1 + mov a,_vreg_ctr+8[b] ;[INF] 3, 1 + and a,[hl+10] ; irq_flg ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0097 ;[INF] 2, 4 +??bb00_set_irq: +; line 399 : vreg_ctr[ irqreg ] |= irq_flg; +$DGL 0,6 + mov a,[hl+2] ; irqreg ;[INF] 2, 1 + shrw ax,8 ;[INF] 2, 1 + addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 + movw de,ax ;[INF] 1, 1 + mov a,[de] ;[INF] 1, 1 + or a,[hl+10] ; irq_flg ;[INF] 2, 1 + mov [de],a ;[INF] 1, 1 +; line 400 : IRQ0_neg; // 一瞬上げて落とし直す。 +$DGL 0,7 +??bb01_set_irq: + set1 PM7.6 ;[INF] 3, 2 +??eb01_set_irq: +; line 401 : // EI(); +; line 402 : tot = 0; +$DGL 0,9 + mov [hl+1],#00H ; tot,0 ;[INF] 3, 1 +; line 403 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.D.なのでちゃん +; とあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) +$DGL 0,10 +?L0099: + bt P7.6,$?L0100 ;[INF] 4, 5 + inc [hl+1] ; tot ;[INF] 3, 2 + mov a,[hl+1] ; tot ;[INF] 2, 1 + cmp0 a ;[INF] 1, 1 + bnz $?L0099 ;[INF] 2, 4 +??bb02_set_irq: +??eb02_set_irq: +?L0100: +; line 404 : IRQ0_ast; +$DGL 0,11 +??bb03_set_irq: + clr1 P7.6 ;[INF] 3, 2 + clr1 PM7.6 ;[INF] 3, 2 +??eb03_set_irq: +??eb00_set_irq: +; line 405 : } +?L0097: +; line 406 : EI(); +; line 407 : } +$DGL 0,14 +??ef_set_irq: + addw sp,#04H ;[INF] 2, 1 + pop hl ;[INF] 1, 1 + ei ;[INF] 3, 4 + ret ;[INF] 1, 6 +??ee_set_irq: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c +; +; $FUNC vreg_ctr_init(42) +; void=(void) +; CODE SIZE= 21 bytes, CLOCK_SIZE= 11 clocks, STACK_SIZE= 0 bytes +; +; $FUNC vreg_ctr_write(66) +; void=(unsigned char adrs:x, unsigned char data:[sp+6]) +; CODE SIZE= 660 bytes, CLOCK_SIZE= 961 clocks, STACK_SIZE= 12 bytes +; +; $CALL renge_task_immed_add(80) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(94) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(111) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(120) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(124) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(132) +; bc=(pointer:ax) +; +; $CALL set_rtc(195) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_rtc(199) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_rtc(203) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_rtc(207) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_rtc(211) +; void=(int:ax, int:[sp+4]) +; +; $CALL set_rtc(215) +; void=(int:ax, int:[sp+4]) +; +; $CALL renge_task_immed_add(249) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(254) +; bc=(pointer:ax) +; +; $CALL renge_task_immed_add(263) +; bc=(pointer:ax) +; +; $CALL clear_hosu_hist(275) +; void=(void) +; +; $FUNC vreg_ctr_read(305) +; bc=(unsigned char adrs:x) +; CODE SIZE= 117 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 6 bytes +; +; $CALL rtc_buf_reflesh(311) +; void=(void) +; +; $CALL hosu_read(319) +; bc=(void) +; +; $CALL renge_task_immed_add(332) +; bc=(pointer:ax) +; +; $FUNC vreg_ctr_after_read(353) +; void=(unsigned char adrs:x) +; CODE SIZE= 23 bytes, CLOCK_SIZE= 22 clocks, STACK_SIZE= 2 bytes +; +; $FUNC set_irq(394) +; void=(unsigned char irqreg:x, unsigned char irq_flg:[sp+4]) +; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 6 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/inter_asm/vreg_twl.asm b/branches/0.10(X3)/inter_asm/vreg_twl.asm new file mode 100644 index 0000000..20720b4 --- /dev/null +++ b/branches/0.10(X3)/inter_asm/vreg_twl.asm @@ -0,0 +1,738 @@ +; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + +; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i +; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ +; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c +; In-file : vreg_twl.c +; Asm-file : inter_asm\vreg_twl.asm +; Para-file : + +$PROCESSOR(9F0104) +$DEBUG +$NODEBUGA +$KANJICODE SJIS +$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + +$DGS FIL_NAM, .file, 062H, 0FFFEH, 03FH, 067H, 01H, 00H +$DGS AUX_FIL, vreg_twl.c +$DGS MOD_NAM, vreg_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H +$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H +$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H +$DGS LAB_SYM, bs_S0051, U, U, 00H, 06H, 00H, 00H +$DGS LAB_SYM, es_S0051, U, U, 00H, 06H, 00H, 00H +$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H +$DGS STA_SYM, _tasks, U, U, 01H, 03H, 01H, 027H +$DGS AUX_STR, 00H, 00H, 016H, 0BH, 00H, 00H, 00H, 04H +$DGS GLV_SYM, _vreg_twl_init, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 01FH, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_twl_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 019H, 00H, 01FH +$DGS END_FUN, ??ef_vreg_twl_init, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 03H +$DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 033H, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_twl_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 023H, 02H, 025H +$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 03H, 00H, 027H +$DGS BEG_BLK, ??bb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 05H, 00H, 02BH +$DGS END_BLK, ??eb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 08H +$DGS BEG_BLK, ??bb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 027H, 00H, 00H +$DGS END_BLK, ??eb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02AH +$DGS END_BLK, ??eb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 02BH +$DGS END_FUN, ??ef_vreg_twl_write, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 02DH +$DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H +$DGS BEG_FUN, ??bf_vreg_twl_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 059H, 02H, 039H +$DGS REG_PAR, _phy_adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS REG_VAR, _temp, 07H, 0FFFFH, 010CH, 04H, 00H, 00H +$DGS BEG_BLK, ??bb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 04H, 00H, 03BH +$DGS BEG_BLK, ??bb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 09H, 00H, 03FH +$DGS END_BLK, ??eb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0BH +$DGS BEG_BLK, ??bb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0BH, 00H, 043H +$DGS END_BLK, ??eb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0DH +$DGS BEG_BLK, ??bb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0DH, 00H, 047H +$DGS END_BLK, ??eb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0FH +$DGS BEG_BLK, ??bb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 0FH, 00H, 04BH +$DGS END_BLK, ??eb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 011H +$DGS BEG_BLK, ??bb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 011H, 00H, 04FH +$DGS END_BLK, ??eb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 013H +$DGS BEG_BLK, ??bb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 013H, 00H, 00H +$DGS END_BLK, ??eb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 015H +$DGS END_BLK, ??eb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 023H +$DGS END_FUN, ??ef_vreg_twl_read, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 024H +$DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 026H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 062H, 00H, 00H +$DGS BEG_FUN, ??bf_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H +$DGS AUX_BEG, 084H, 02H, 05CH +$DGS REG_PAR, _img, 06H, 0FFFFH, 010CH, 011H, 00H, 00H +$DGS BEG_BLK, ??bb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H +$DGS AUX_BEG, 02H, 00H, 00H +$DGS END_BLK, ??eb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H +$DGS AUX_END, 0EH +$DGS END_FUN, ??ef_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H +$DGS AUX_END, 0FH +$DGS GLV_SYM, _vreg_twl, U, U, 0CH, 026H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 0FH, 0FH, 00H, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_sw, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_adc, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_batt, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_debug, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_debug2, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _tsk_sys, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H +$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H +$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H +$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + + EXTRN _tsk_sw + EXTRN _tsk_adc + EXTRN _tsk_batt + EXTRN _tsk_led_pow + EXTRN _tsk_led_wifi + EXTRN _tsk_led_notify + EXTRN _tsk_led_cam + EXTRN _tsk_misc_stat + EXTRN _tsk_debug + EXTRN _tsk_debug2 + EXTRN _tsk_sys + EXTRN _set_irq + EXTRN _vreg_ctr + PUBLIC _vreg_twl + PUBLIC _vreg_twl_init + PUBLIC _vreg_twl_write + PUBLIC _vreg_twl_read + PUBLIC _adrs_table_twl_ext2int + +@@BITS BSEG + +@@CNST CSEG MIRRORP +_lpf_coeff: DB 01H ; 1 + DB 02H ; 2 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 00H ; 0 + DB 0FEH ; 254 + DB 0FBH ; 251 + DB 0F7H ; 247 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0FAH ; 250 + DB 04H ; 4 + DB 012H ; 18 + DB 025H ; 37 + DB 038H ; 56 + DB 04DH ; 77 + DB 05FH ; 95 + DB 06EH ; 110 + DB 077H ; 119 + DB 07AH ; 122 + DB 077H ; 119 + DB 06EH ; 110 + DB 05FH ; 95 + DB 04DH ; 77 + DB 038H ; 56 + DB 025H ; 37 + DB 012H ; 18 + DB 04H ; 4 + DB 0FAH ; 250 + DB 0F3H ; 243 + DB 0F0H ; 240 + DB 0F0H ; 240 + DB 0F3H ; 243 + DB 0F7H ; 247 + DB 0FBH ; 251 + DB 0FEH ; 254 + DB 00H ; 0 + DB 02H ; 2 + DB 03H ; 3 + DB 03H ; 3 + DB 02H ; 2 + DB 02H ; 2 + DB 01H ; 1 + DB (1) + +@@R_INIT CSEG UNIT64KP + DW loww (_tsk_sw) + DW loww (_tsk_adc) + DW loww (_tsk_batt) + DW loww (_tsk_led_pow) + DW loww (_tsk_led_wifi) + DW loww (_tsk_led_notify) + DW loww (_tsk_led_cam) + DW loww (_tsk_misc_stat) + DW loww (_tsk_debug) + DW loww (_tsk_debug2) + DW loww (_tsk_sys) + +@@INIT DSEG BASEP +_tasks: DS (22) + +@@DATA DSEG BASEP +_vreg_twl: DS (15) + DS (1) + +@@R_INIS CSEG UNIT64KP + +@@INIS DSEG SADDRP + +@@DATS DSEG SADDRP + +@@CNSTL CSEG PAGE64KP + +@@RLINIT CSEG UNIT64KP + +@@INITL DSEG UNIT64KP + +@@DATAL DSEG UNIT64KP + +@@CALT CSEG CALLT0 + +; Sub-Routines created by CC78K0R + +ROM_CODE CSEG BASE +bs_S0051: + mov a,h ;[INF] 1, 1 + and a,#03H ; 3 ;[INF] 2, 1 + mov c,a ;[INF] 1, 1 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,c ;[INF] 1, 1 + mov _vreg_twl[b],a ;[INF] 3, 1 + ret ;[INF] 1, 6 +es_S0051: + +; *** Sub-Routine Information *** +; +; $SUB bs_S0051 +; CODE SIZE= 11 bytes + +; End of Sub-Routines + +; line 1 : /* ======================================================== +; line 2 : +; line 3 : TWL互換側のI2Cレジスタ +; line 4 : +; line 5 : ======================================================== */ +; line 6 : #include "incs.h" +; line 7 : #include "jhl_defs.h" +; line 8 : #include "vreg_twl.h" +; line 9 : +; line 10 : #include "vreg_ctr.h" +; line 11 : #include "renge\renge_task_intval.h" +; line 12 : +; line 13 : // ======================================================== +; line 14 : #define TWL_REG_VER_INFO 0x35 +; line 15 : #define NON_EXIST_REG 0xFF +; line 16 : +; line 17 : // ======================================================== +; line 18 : u8 vreg_twl[_REG_TWL_INT_ADRS_ENDMARK]; +; line 19 : +; line 20 : +; line 21 : /* ======================================================== +; line 22 : 仮想レジスタの初期化 +; line 23 : ======================================================== */ +; line 24 : void vreg_twl_init( ) +; line 25 : { + +ROM_CODE CSEG BASE +_vreg_twl_init: +$DGL 1,25 +??bf_vreg_twl_init: +; line 26 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03; +$DGL 0,2 + mov !_vreg_twl+3,#03H ; 3 ;[INF] 4, 1 +; line 27 : } +$DGL 0,3 +??ef_vreg_twl_init: + ret ;[INF] 1, 6 +??ee_vreg_twl_init: +; line 28 : +; line 29 : +; line 30 : // ======================================================== +; line 31 : // I2C仮想レジスタに書く・何かアクションする +; line 32 : //　引数 adrs は内部アドレス +; line 33 : // 　存在しないアドレスにアクセスした場合、何もしません。 +; line 34 : void vreg_twl_write( u8 adrs, u8 data ) +; line 35 : { +_vreg_twl_write: +$DGL 1,31 + push hl ;[INF] 1, 1 + mov a,[sp+6] ;[INF] 2, 1 + movw hl,ax ;[INF] 1, 1 +??bf_vreg_twl_write: +; line 36 : switch ( adrs ) +$DGL 0,2 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + movw de,#02H ; 2 ;[INF] 3, 1 + subw ax,de ;[INF] 1, 1 + bz $?L0010 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0007 ;[INF] 2, 4 + subw ax,de ;[INF] 1, 1 + bz $?L0008 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0006 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0009 ;[INF] 2, 4 + br $?L0013 ;[INF] 2, 3 +; line 37 : { +??bb00_vreg_twl_write: +; line 38 : case ( REG_TWL_INT_ADRS_VOL ): +?L0006: +; line 39 : { +??bb01_vreg_twl_write: +; line 40 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE ); +$DGL 0,6 + movw ax,#040H ; 64 ;[INF] 3, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 41 : break; +$DGL 0,7 + br $?L0013 ;[INF] 2, 3 +??eb01_vreg_twl_write: +; line 42 : } +; line 43 : +; line 44 : case ( REG_TWL_INT_ADRS_MODE ): +?L0007: +; line 45 : vreg_twl[adrs] = ( data & 0x03 ); +$DGL 0,11 + call !bs_S0051 ;[INF] 3, 3 +; line 46 : break; +$DGL 0,12 + br $?L0013 ;[INF] 2, 3 +; line 47 : +; line 48 : case ( REG_TWL_INT_ADRS_CAM ): +?L0008: +; line 49 : vreg_twl[adrs] = ( data & 0x03 ); +$DGL 0,15 + call !bs_S0051 ;[INF] 3, 3 +; line 50 : tsk_led_cam(); // todo 大丈夫？ +$DGL 0,16 + call !_tsk_led_cam ;[INF] 3, 3 +; line 51 : break; +$DGL 0,17 + br $?L0013 ;[INF] 2, 3 +; line 52 : +; line 53 : case ( REG_TWL_INT_ADRS_TEMP0 ): +?L0009: +; line 54 : vreg_twl[adrs] = data; +$DGL 0,20 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,h ;[INF] 1, 1 + mov _vreg_twl[b],a ;[INF] 3, 1 +; line 55 : break; +$DGL 0,21 + br $?L0013 ;[INF] 2, 3 +; line 56 : +; line 57 : case ( REG_TWL_INT_ADRS_COMMAND ): +?L0010: +; line 58 : /* +; line 59 : if( data <= 2 ){ +; line 60 : if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 ) +; line 61 : { +; line 62 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); +; // OFFも実装していたらしい。 +; line 63 : break; +; line 64 : } +; line 65 : else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 ) +; line 66 : { +; line 67 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); +; //リセットしかない。他のは、SPIから来ます。 +; line 68 : break; +; line 69 : } +; line 70 : } +; line 71 : */ +; line 72 : if( data == REG_BIT_TWL_RESET_REQ ) +$DGL 0,38 + mov a,h ;[INF] 1, 1 + dec a ;[INF] 1, 1 + bnz $?L0013 ;[INF] 2, 4 +; line 73 : { +??bb02_vreg_twl_write: +; line 74 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); +; //リセットしかない。他のは、SPIから来ます。 +$DGL 0,40 + onew ax ;[INF] 1, 1 + push ax ;[INF] 1, 1 + mov x,#012H ; 18 ;[INF] 2, 1 + call !_set_irq ;[INF] 3, 3 + pop ax ;[INF] 1, 1 +; line 75 : break; +??eb02_vreg_twl_write: +; line 76 : } +?L0013: +??eb00_vreg_twl_write: +; line 77 : } +; line 78 : return; +; line 79 : } +$DGL 0,45 +??ef_vreg_twl_write: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_vreg_twl_write: +; line 80 : +; line 81 : +; line 82 : +; line 83 : // ======================================================== +; line 84 : // I2C仮想レジスタから読みます。 +; line 85 : //　引数 adrs 外から見たときの、アドレス +; line 86 : //　戻り xx データ +; line 87 : // 　存在しないアドレスにアクセスした場合、戻り値は0x5A +; line 88 : u8 vreg_twl_read( u8 phy_adrs ) +; line 89 : { +_vreg_twl_read: +$DGL 1,51 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_vreg_twl_read: +; line 90 : u8 temp; +; line 91 : +; line 92 : switch( phy_adrs ){ +$DGL 0,4 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0018 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0020 ;[INF] 2, 4 + subw ax,#03H ; 3 ;[INF] 3, 1 + bz $?L0019 ;[INF] 2, 4 + subw ax,#0FBH ; 251 ;[INF] 3, 1 + bz $?L0022 ;[INF] 2, 4 + br $?L0021 ;[INF] 2, 3 +??bb00_vreg_twl_read: +; line 93 : case( REG_TWL_INT_ADRS_VER_INFO ): +?L0018: +; line 94 : return( TWL_REG_VER_INFO ); +$DGL 0,6 + movw bc,#035H ; 53 ;[INF] 3, 1 + br $?L0017 ;[INF] 2, 3 +; line 95 : +; line 96 : case( REG_TWL_INT_ADRS_POWER_INFO ): +?L0019: +; line 97 : if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){ +$DGL 0,9 + cmp !_vreg_ctr+11,#05BH ; 91 ;[INF] 4, 1 + bc $?L0025 ;[INF] 2, 4 +??bb01_vreg_twl_read: +; line 98 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F; +$DGL 0,10 + mov !_vreg_twl+4,#0FH ; 15 ;[INF] 4, 1 +??eb01_vreg_twl_read: +; line 99 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){ +$DGL 0,11 + br $?L0034 ;[INF] 2, 3 +?L0025: + cmp !_vreg_ctr+11,#04CH ; 76 ;[INF] 4, 1 + bc $?L0027 ;[INF] 2, 4 +??bb02_vreg_twl_read: +; line 100 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B; +$DGL 0,12 + mov !_vreg_twl+4,#0BH ; 11 ;[INF] 4, 1 +??eb02_vreg_twl_read: +; line 101 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){ +$DGL 0,13 + br $?L0034 ;[INF] 2, 3 +?L0027: + cmp !_vreg_ctr+11,#033H ; 51 ;[INF] 4, 1 + bc $?L0029 ;[INF] 2, 4 +??bb03_vreg_twl_read: +; line 102 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07; +$DGL 0,14 + mov !_vreg_twl+4,#07H ; 7 ;[INF] 4, 1 +??eb03_vreg_twl_read: +; line 103 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){ +$DGL 0,15 + br $?L0034 ;[INF] 2, 3 +?L0029: + cmp !_vreg_ctr+11,#01AH ; 26 ;[INF] 4, 1 + bc $?L0031 ;[INF] 2, 4 +??bb04_vreg_twl_read: +; line 104 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03; +$DGL 0,16 + mov !_vreg_twl+4,#03H ; 3 ;[INF] 4, 1 +??eb04_vreg_twl_read: +; line 105 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 5 ){ +$DGL 0,17 + br $?L0034 ;[INF] 2, 3 +?L0031: + cmp !_vreg_ctr+11,#06H ; 6 ;[INF] 4, 1 + bc $?L0033 ;[INF] 2, 4 +??bb05_vreg_twl_read: +; line 106 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01; +$DGL 0,18 + oneb !_vreg_twl+4 ;[INF] 3, 1 +??eb05_vreg_twl_read: +; line 107 : }else{ +$DGL 0,19 + br $?L0034 ;[INF] 2, 3 +?L0033: +??bb06_vreg_twl_read: +; line 108 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00; +$DGL 0,20 + clrb !_vreg_twl+4 ;[INF] 3, 1 +??eb06_vreg_twl_read: +; line 109 : } +?L0034: +; line 110 : +; line 111 : return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !B +; T_CHG_n ? 0x80: 0x00 ) ); // アダプタbit +$DGL 0,23 + bt P5.1,$?L0035 ;[INF] 4, 5 + movw ax,#080H ; 128 ;[INF] 3, 1 + br $?L0036 ;[INF] 2, 3 +?L0035: + clrw ax ;[INF] 1, 1 +?L0036: + xch a,x ;[INF] 1, 1 + or a,!_vreg_twl+4 ;[INF] 3, 1 + xch a,x ;[INF] 1, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +; line 112 : +; line 113 : case( REG_TWL_INT_ADRS_IRQ ): +?L0020: +; line 114 : temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ]; +$DGL 0,26 + mov a,!_vreg_twl+1 ;[INF] 3, 1 +; line 115 : vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0; +$DGL 0,27 + clrb !_vreg_twl+1 ;[INF] 3, 1 +; line 116 : return( temp ); +$DGL 0,28 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +; line 117 : +; line 118 : default: +?L0021: +; line 119 : return( vreg_twl[ phy_adrs ] ); +$DGL 0,31 + mov a,l ;[INF] 1, 1 + mov b,a ;[INF] 1, 1 + mov a,_vreg_twl[b] ;[INF] 3, 1 + shrw ax,8 ;[INF] 2, 1 + movw bc,ax ;[INF] 1, 1 + br $?L0017 ;[INF] 2, 3 +; line 120 : +; line 121 : case( REG_TWL_ADRS_NON_EXIST ): +?L0022: +; line 122 : return( 0x00 ); +$DGL 0,34 + clrw bc ;[INF] 1, 1 +??eb00_vreg_twl_read: +; line 123 : } +?L0017: +; line 124 : } +$DGL 0,36 +??ef_vreg_twl_read: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_vreg_twl_read: +; line 125 : +; line 126 : +; line 127 : +; line 128 : // ======================================================== +; line 129 : // 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える +; line 130 : // 0xFFは存在しないアドレス。 +; line 131 : u8 adrs_table_twl_ext2int( u8 img ) +; line 132 : { +_adrs_table_twl_ext2int: +$DGL 1,87 + push hl ;[INF] 1, 1 + movw hl,ax ;[INF] 1, 1 +??bf_adrs_table_twl_ext2int: +; line 133 : switch( img ){ +$DGL 0,2 + movw ax,hl ;[INF] 1, 1 + clrb a ;[INF] 1, 1 + onew bc ;[INF] 1, 1 + subw ax,#00H ; 0 ;[INF] 3, 1 + bz $?L0046 ;[INF] 2, 4 + subw ax,#010H ; 16 ;[INF] 3, 1 + bz $?L0040 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0041 ;[INF] 2, 4 + subw ax,bc ;[INF] 1, 1 + bz $?L0047 ;[INF] 2, 4 + subw ax,#0EH ; 14 ;[INF] 3, 1 + bz $?L0042 ;[INF] 2, 4 + subw ax,#011H ; 17 ;[INF] 3, 1 + bz $?L0043 ;[INF] 2, 4 + subw ax,#0FH ; 15 ;[INF] 3, 1 + bz $?L0044 ;[INF] 2, 4 + subw ax,#030H ; 48 ;[INF] 3, 1 + bz $?L0045 ;[INF] 2, 4 + br $?L0048 ;[INF] 2, 3 +??bb00_adrs_table_twl_ext2int: +; line 134 : case( REG_TWL_ADRS_IRQ ): return( REG_TWL_INT_ADRS_ +; IRQ ); +$DGL 0,3 +?L0040: + onew bc ;[INF] 1, 1 + br $?L0039 ;[INF] 2, 3 +; line 135 : case( REG_TWL_ADRS_COMMAND ): return( REG_TWL_INT_ADRS_ +; COMMAND ); +$DGL 0,4 +?L0041: + onew bc ;[INF] 1, 1 + incw bc ;[INF] 1, 1 + br $?L0039 ;[INF] 2, 3 +; line 136 : case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_ +; POWER_INFO ); +$DGL 0,5 +?L0042: + movw bc,#04H ; 4 ;[INF] 3, 1 + br $?L0039 ;[INF] 2, 3 +; line 137 : case( REG_TWL_ADRS_CAM ): return( REG_TWL_INT_ADRS_ +; CAM ); +$DGL 0,6 +?L0043: + movw bc,#05H ; 5 ;[INF] 3, 1 + br $?L0039 ;[INF] 2, 3 +; line 138 : case( REG_TWL_ADRS_VOL ): return( REG_TWL_INT_ADRS_ +; VOL ); +$DGL 0,7 +?L0044: + movw bc,#06H ; 6 ;[INF] 3, 1 + br $?L0039 ;[INF] 2, 3 +; line 139 : case( REG_TWL_ADRS_TEMP0 ): return( REG_TWL_INT_ADRS_ +; TEMP0 ); +$DGL 0,8 +?L0045: + movw bc,#07H ; 7 ;[INF] 3, 1 + br $?L0039 ;[INF] 2, 3 +; line 140 : case( REG_TWL_ADRS_VER_INFO ): return( REG_TWL_INT_ADRS_ +; VER_INFO ); +$DGL 0,9 +?L0046: + clrw bc ;[INF] 1, 1 + br $?L0039 ;[INF] 2, 3 +; line 141 : case( REG_TWL_ADRS_MODE ): return( REG_TWL_INT_ADRS_ +; MODE ); +$DGL 0,10 +?L0047: + movw bc,#03H ; 3 ;[INF] 3, 1 + br $?L0039 ;[INF] 2, 3 +; line 142 : default: return( REG_TWL_ADRS_NON_ +; EXIST ); +$DGL 0,11 +?L0048: + clrw bc ;[INF] 1, 1 + dec c ;[INF] 1, 1 +??eb00_adrs_table_twl_ext2int: +; line 143 : // 0が読めればよい、書けなくて良い +; line 144 : // case( REG_TWL_ADRS_WIFI ): return( REG_TWL_INT_ADR +; S_WIFI ); +; line 145 : } +?L0039: +; line 146 : } +$DGL 0,15 +??ef_adrs_table_twl_ext2int: + pop hl ;[INF] 1, 1 + ret ;[INF] 1, 6 +??ee_adrs_table_twl_ext2int: + +@@CODEL CSEG + +@@BASE CSEG BASE + END + + +; *** Code Information *** +; +; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c +; +; $FUNC vreg_twl_init(25) +; void=(void) +; CODE SIZE= 5 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes +; +; $FUNC vreg_twl_write(35) +; void=(unsigned char adrs:x, unsigned char data:[sp+6]) +; CODE SIZE= 74 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 8 bytes +; +; $CALL set_irq(40) +; void=(int:ax, int:[sp+4]) +; +; $CALL tsk_led_cam(50) +; void=(void) +; +; $CALL set_irq(74) +; void=(int:ax, int:[sp+4]) +; +; $FUNC vreg_twl_read(89) +; bc=(unsigned char phy_adrs:x) +; CODE SIZE= 134 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 2 bytes +; +; $FUNC adrs_table_twl_ext2int(132) +; bc=(unsigned char img:x) +; CODE SIZE= 82 bytes, CLOCK_SIZE= 90 clocks, STACK_SIZE= 2 bytes + +; Target chip : uPD79F0104 +; Device file : E1.00b diff --git a/branches/0.10(X3)/jhl_defs.h b/branches/0.10(X3)/jhl_defs.h new file mode 100644 index 0000000..1c8afa1 --- /dev/null +++ b/branches/0.10(X3)/jhl_defs.h @@ -0,0 +1,26 @@ +#ifndef __jhl_defs_h__ +#define __jhl_defs_h__ + +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef signed short s16; + +typedef unsigned char err; + + +#include "config.h" + + + +#define set_bit( cond, reg, pos ) \ +{ \ + if( cond ){ \ + reg |= pos; \ + }else{ \ + reg &= ~pos; \ + } \ +} + + +#endif diff --git a/branches/0.10(X3)/led.c b/branches/0.10(X3)/led.c new file mode 100644 index 0000000..b231d0f --- /dev/null +++ b/branches/0.10(X3)/led.c @@ -0,0 +1,618 @@ +/* ======================================================== + LED.c + + ======================================================== */ +#pragma sfr + + +#include "incs.h" +#include "led.h" + + + +// ======================================================== +// TPS0 +#define BIT_PRS012 ( 1 << 2 ) +#define BIT_PRS002 ( 1 << 6 ) + +// TMR0 +#define BIT_CKS0 15 +#define BIT_CCS0 12 +#define BIT_MASTER0 11 +#define BIT_STS0 8 +#define BIT_CIS0 6 +#define BIT_MD123 1 +#define BIT_MD0 0 + +// ======================================================== +static void led_pow_normal( ); +static void led_pow_hotaru( ); + + + +// ======================================================== +static const char MSG_MAIL[] = { 0b11110110, 0b11011010, 0b01101110, 0b10010100 }; +#define MSG_SPD 60 +// ↑255/3以下であること！ + +// ======================================================== +void LED_init( ) +{ +/** + PWMのセット、とりあえず全部消灯 + + マスタチャネル：０　(P01:/reset2)　マスターは偶数チャネルしかできない + スレーブ　　　　１　ＳＬＴＯ。(３Ｄ ＬＥＤ？) + 　　　　　　　　２　カメラ + 　　　　　　　　３　WiFi + 　　　　　　　　４　(ピンはＲＴＣ32kHz out に使用) + 　　　　　　　　５　充電 + 　　　　　　　　６　電源 Ｌ + 　　　　　　　　７　電源 Ｈ + */ + TAU0EN = 1; + TPS0 = BIT_PRS012 | BIT_PRS002; // マスタークロックはCK01,8M/2 /2^4 = 250kHz + + TMR00 = + 1 << BIT_CKS0 | 0 << BIT_CCS0 | 1 << BIT_MASTER0 | 0 << BIT_STS0 | 0 + << BIT_CIS0 | 0 << BIT_MD123 | 1 << BIT_MD0; + TMR01 = TMR02 = TMR03 = TMR04 = TMR05 = TMR06 = TMR07 = + 1 << BIT_CKS0 | 0 << BIT_CCS0 | 0 << BIT_MASTER0 | 4 << BIT_STS0 | 0 + << BIT_CIS0 | 4 << BIT_MD123 | 1 << BIT_MD0; + ISC = 0; + TOM0 = 0b0000000011111110; // 出力モード。4はPWM出力しないが1にしないとTO5以降にクロックが届かない + +#ifdef _MCU_BSR_ + TOL0 = 0b0000000000000000; // 出力を反転させるかフラグ +#else + TOL0 = 0b0000000000000100; // 出力を反転させるかフラグ +#endif + + TO0 = 0; // タイマー動作中で、タイマー出力にしてないときのピンのラッチ。タイマー出力を使わないなら０ + TOE0 = 0b0000000011101110; // TOxをタイマーモジュールが制御？ + TS0 = 0b0000000011101111; // 動作開始 + + TDR00 = LED_BRIGHT_MAX - 1; // 10bit, 周期 + + if( system_status.reboot ) + { + vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; + LED_duty_pow_H = LED_BRIGHT_MAX; + } +} + + + +void LED_stop( ) +{ + TT0 = 0b0000000011101111; // 一斉停止（しないとだめ） + TOE0 = 0b0000000000000000; // TOxをタイマーモジュールが制御？(GPIOになる) + TAU0EN = 0; +} + + + + +/* ======================================================== + // 電源LED + LED_POW_B,R 6,7 + + TDR00　周期(0x03FF。TPS0で250kHzでカウントアップ。10bitなら250Hz位になる) + TDR0x　Duty 0で消灯、TDR00(より大 =0x03FF以上)で点灯です。 + + enum pwr_state_{ + OFF_TRIG = 0, + OFF, + ON_TRIG, + ON, + SLEEP_TRIG, + SLEEP +}; + +enum LED_ILUM_MODE{ + LED_POW_ILM_AUTO, + LED_POW_ILM_ON, + LED_POW_ILM_HOTARU, + LED_POW_ILM_CEOFF +}; + ======================================================== */ +void tsk_led_pow( ) +{ + switch ( vreg_ctr[VREG_C_LED_POW] ) + { + // 自動切り替え + case ( LED_POW_ILM_AUTO ): + switch ( system_status.pwr_state ) + { + case SLEEP: + led_pow_hotaru( ); + break; + + case ON: + led_pow_normal( ); + break; + + default: + break; + } + break; + + // 強制 + case ( LED_POW_ILM_OFF ): + LED_duty_pow_H -= ( LED_duty_pow_H == 0x0000 ) ? 0 : 1; + LED_duty_pow_L -= ( LED_duty_pow_L == 0x0000 ) ? 0 : 1; + break; + + case ( LED_POW_ILM_HOTARU ): + led_pow_hotaru( ); + break; + + case ( LED_POW_ILM_ON ): + default: + led_pow_normal( ); + break; + + case ( LED_POW_ILM_ONLY_RED ): + LED_duty_pow_H = 0x0000; + LED_duty_pow_L = LED_BRIGHT_MAX; + break; + + case ( LED_POW_ILM_ONLY_BLUE ): + LED_duty_pow_H = LED_BRIGHT_MAX; + LED_duty_pow_L = 0x0000; + break; + } + +} + + + +/* ======================================================== + 電池残量で、　青→赤→赤点滅 + ======================================================== */ +static void led_pow_normal( ) +{ + static u8 state; + + if( vreg_ctr[VREG_C_BT_REMAIN] < 3 ) + { + // 赤点滅 + state++; + if( state < 127 ) + { + LED_duty_pow_H = 0x0000; + LED_duty_pow_L = 0x0000; + } + else + { + LED_duty_pow_L = vreg_ctr[VREG_C_LED_BRIGHT]; + } + return; + + } + else if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + { + // 赤点灯 + if( LED_duty_pow_H != 0x0000 ) + { // 青フェードアウト + LED_duty_pow_H -= 1; + } + if( LED_duty_pow_L != vreg_ctr[VREG_C_LED_BRIGHT] ) + { // 赤フェードイン + LED_duty_pow_L += ( LED_duty_pow_L < vreg_ctr[VREG_C_LED_BRIGHT] ) ? 1 : -1; + } + return; + + } + else + { + // 青点灯 + if( LED_duty_pow_H != vreg_ctr[VREG_C_LED_BRIGHT] ) + { + LED_duty_pow_H += ( LED_duty_pow_H < vreg_ctr[VREG_C_LED_BRIGHT] ) ? 1 : -1; + } + if( LED_duty_pow_L != 0x0000 ) + { + LED_duty_pow_L -= 1; + } + } + + return; +} + + + +/* ======================================================== + ホタルパターン + ======================================================== */ +static void led_pow_hotaru( ) +{ + static u8 delay; + static u8 state; + static u16 blue_to; + static u16 red_to; + + if( delay != 0 ) + { + delay -= 1; + return; + } + else + { + delay = 10; + } + + if( LED_duty_pow_L != red_to ) + { + if( LED_duty_pow_L > red_to ) + { + LED_duty_pow_L -= 1; + } + else + { + LED_duty_pow_L += 2; + } + } + + if( LED_duty_pow_H != blue_to ) + { + if( LED_duty_pow_H > blue_to ) + { + LED_duty_pow_H -= 1; + } + else + { + LED_duty_pow_H += 2; + } + } + + switch ( state ) + { + // フェードイン + case ( 0 ): + case ( 2 ): + case ( 4 ): + if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + { + // 赤いとき + blue_to = 0; + red_to = vreg_ctr[VREG_C_LED_BRIGHT]; + } + else + { + blue_to = vreg_ctr[VREG_C_LED_BRIGHT]; + red_to = 0; + } + break; + + default: + // フェードアウト + if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + { + red_to = 2; + } + else + { + blue_to = 2; + } + break; + } + + if( ( LED_duty_pow_H == blue_to ) && ( LED_duty_pow_L == red_to ) ) + { + state += 1; + } + return; +} + + + +/* ======================================================== + * 割り込みそのものは使いません * + LED_Wifi 3 + todo 直書きの点滅間隔など + ======================================================== */ +void tsk_led_wifi( ) +{ + static u8 task_interval; + static u8 remain_wifi_tx; + static u8 state_wifi_tx; + static u8 flag_wifi_TX; + + + if( task_interval-- != 0 ) + { + return; + } + + // 送信パルスのラッチ + if( vreg_ctr[VREG_C_LED_WIFI] == WIFI_LED_TXAUTO ) + { + if( WIFI_txLatch ) + { + WIFI_txLatch = 0; + flag_wifi_TX = 2; + } + } + else + { + flag_wifi_TX = 0; + } + + + switch ( vreg_ctr[VREG_C_LED_WIFI] ) + { + case ( WIFI_LED_OFF ): + default: + LED_duty_WiFi = 0; + state_wifi_tx = 0; + remain_wifi_tx = 0; + break; + + case ( WIFI_LED_ON ): + LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + state_wifi_tx = 0; + remain_wifi_tx = 0; + break; + + case ( WIFI_LED_TXAUTO ): + if( flag_wifi_TX != 0 ) // 短いパルスを捕まえるために、割り込みフラグを見る + { + // 送信パターン + switch ( state_wifi_tx ) + { + case ( 1 ): + case ( 3 ): + case ( 5 ): + LED_duty_WiFi = 0; + break; + default: + LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + } + state_wifi_tx++; + if( state_wifi_tx == 32 ) + { + state_wifi_tx = 0; + flag_wifi_TX -= 1; + } + task_interval = 22; + return; + } + else + { + // 送信フラグ待ち + LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + task_interval = 200; + return; + } + break; + + } +} + + + + +/* ======================================================== + * 割り込みそのものは使いません * + LED_Wifi2 P24 （未） + ======================================================== */ +void tsk_led_notify( ) +{ + static u8 task_interval; + static u8 flg_char_space; + static u8 state_notify_led; // 点灯パターンの進行具合 + static u8 flag_wifi_TX; + + + if( task_interval-- != 0 ) + { + return; + } + + switch ( vreg_ctr[VREG_C_LED_NOTIFY] ) + { + case ( NOTIFY_LED_OFF ): + default: + LED_duty_NOTIFY = 0; + state_notify_led = 0; + flg_char_space = 0; + break; + + case ( NOTIFY_LED_ON ): + LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + state_notify_led = 0; + flg_char_space = 0; + break; + + case ( NOTIFY_LED_PTN0 ): + // ゆっくりバースト + switch ( state_notify_led ) + { + case ( 1 ): + case ( 3 ): + case ( 5 ): + LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + break; + default: + LED_duty_NOTIFY = 0; + } + state_notify_led++; + if( state_notify_led == 16 ) + { + state_notify_led = 0; + } + task_interval = 50; + return; + + case ( NOTIFY_LED_PTN1 ): + // データテーブルに従って点滅 + { + u8 dat; + + task_interval = MSG_SPD; // 共通のため。場合によって上書き + + if( flg_char_space != 0 ) + { + LED_duty_NOTIFY = 0; + flg_char_space = 0; + return; + } + + // データバッファの見る位置の更新 + dat = ( MSG_MAIL[state_notify_led / 4] << ( ( state_notify_led % 4 ) * 2 ) ) & 0xC0; + if( dat == 0 ) + { + state_notify_led = 0; + } + else + { + state_notify_led += 1; + } + + flg_char_space = 1; + if(( dat & 0b10000000 ) != 0 ) + { + // 点灯はさせる + LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + if(( dat & 0b01000000 ) == 0 ) + { + // 短 + // nothing to do + } + else + { + // 長 + task_interval = ( MSG_SPD * 3 ); + } + // 次は単語間休み、とかの判定をさせたかったが + /// １バイトに２ビットずつデータが並んでおり、次のバイトに + /// またがるようなときが面倒なのでやめる + return; + } + else + { + if(( dat & 0b01000000 ) == 0 ) + { + // 一文終了 + task_interval = ( MSG_SPD * 3 ); + } + else + { + // 単語間 + // nothing to do + } + return; + } + } + } +} + + + + +/******************************************************//** + LED_Cam TO02 +\n BLINK,*_PLUSE の時は、1周期分は必ずその状態になります。 +\n その間に OFF→BLINK などされると、OFFが無視されます。 + *********************************************************/ +void tsk_led_cam( ) +{ + static u8 state_led_cam = 0; + static u8 task_interval; + static u8 state_led_cam_twl; + + if( task_interval != 0 ) + { + task_interval -= 1; + return; + } + + // ブリンクのように待たせたいとき以外は毎週起動する + // (レジスタの変更にすぐに反応する) + + switch ( vreg_ctr[VREG_C_LED_CAM] ) + { + case ( CAM_LED_OFF ): + default: + LED_duty_CAM = 0; + state_led_cam = 0; + break; + + case ( CAM_LED_ON ): + LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + state_led_cam = 0; + break; + + case ( CAM_LED_BLINK ): + if( state_led_cam == 0 ) + { + LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + state_led_cam = 1; + } + else + { + LED_duty_CAM = 0; + state_led_cam = 0; + } + task_interval = 250; + break; + + case ( CAM_LED_ON_PLUSE ): + if( state_led_cam == 0 ) + { + LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + state_led_cam = 1; + task_interval = 250; + } + else + { + vreg_ctr[VREG_C_LED_CAM] = CAM_LED_OFF; + } + break; + + case ( CAM_LED_OFF_PLUSE ): + if( state_led_cam == 0 ) + { + LED_duty_CAM = 0; + state_led_cam = 1; + task_interval = 250; + } + else + { + vreg_ctr[VREG_C_LED_CAM] = CAM_LED_ON; + } + break; + + case ( CAM_LED_BY_TWL ): + switch ( vreg_twl[ REG_TWL_INT_ADRS_CAM ] ){ // switchのネストとか… + case( TWL_CAMLED_OFF ): + LED_duty_CAM = 0; + state_led_cam = 0; + break; + + case( TWL_CAMLED_BLINK ): + if( state_led_cam == 0 ) + { + LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + state_led_cam = 1; + } + else + { + LED_duty_CAM = 0; + state_led_cam = 0; + } + task_interval = 250; + break; + + case( TWL_CAMLED_ON ): + case( TWL_CAMLED_DEF_ON ): + default: + LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + state_led_cam = 1; + break; + } + } + return; +} + diff --git a/branches/0.10(X3)/led.h b/branches/0.10(X3)/led.h new file mode 100644 index 0000000..db22719 --- /dev/null +++ b/branches/0.10(X3)/led.h @@ -0,0 +1,90 @@ +#ifndef __led__ +#define __led__ + + +// ==================================== + +// LED_DUTY +#define LED_duty_pow_L TDR07 +#define LED_duty_pow_H TDR06 +#define LED_duty_WiFi TDR03 +#define LED_duty_NOTIFY TDR05 +#define LED_duty_CAM TDR02 +#define LED_duty_TUNE TDR01 +// wifi2はPWMできません。 + + +#define LED_BRIGHT_MAX 0x00FF + + +// ==================================== +#ifdef _MCU_BSR_ // 電波送信パルス +#define WIFI_txLatch PIF21 +#else +#define WIFI_txLatch PIF7 +#endif + + + +// ==================================== +enum LED_ILUM_MODE +{ + LED_POW_ILM_AUTO = 0, + LED_POW_ILM_ON, + LED_POW_ILM_HOTARU, + LED_POW_ILM_OFF, + LED_POW_ILM_ONLY_RED, + LED_POW_ILM_ONLY_BLUE +}; + + +enum LED_MODE_TUNE +{ + LED_TUNE_ILM_OFF = 0, + LED_TUNE_ILM_ON, + LED_TUNE_ILM_SVR +}; + + +// VREG_C_WIFI_LED +enum +{ + WIFI_LED_OFF = 0, + WIFI_LED_ON, + WIFI_LED_TXAUTO, + WIFI_LED_PTN0, + WIFI_LED_PTN1 +}; + + +// VREG_C_WIFI_NOTIFY +enum +{ + NOTIFY_LED_OFF = 0, + NOTIFY_LED_ON, + NOTIFY_LED_PTN0, + NOTIFY_LED_PTN1, + NOTIFY_LED_PTN2 +}; + + +// VREG_C_CAM_LED +enum +{ + CAM_LED_OFF = 0, + CAM_LED_BLINK, + CAM_LED_ON, + CAM_LED_BY_TWL, + CAM_LED_ON_PLUSE, + CAM_LED_OFF_PLUSE +}; + + + +// ==================================== +void LED_init( ); +void LED_stop( ); + + + +#endif diff --git a/branches/0.10(X3)/led.prn b/branches/0.10(X3)/led.prn new file mode 100644 index 0000000..3263ead --- /dev/null +++ b/branches/0.10(X3)/led.prn @@ -0,0 +1,2185 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\led.asm +Para-file: +In-file: inter_asm\led.asm +Obj-file: led.rel +Prn-file: led.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no led.c + 6 6 ; In-file : led.c + 7 7 ; Asm-file : inter_asm\led.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 017FH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, led.c + 18 18 $DGS MOD_NAM, led, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS LAB_SYM, bs_S0172, U, U, 00H, 06H, 00H, 00H + 82 82 $DGS LAB_SYM, es_S0172, U, U, 00H, 06H, 00H, 00H + 83 83 $DGS LAB_SYM, bs_S0173, U, U, 00H, 06H, 00H, 00H + 84 84 $DGS LAB_SYM, es_S0173, U, U, 00H, 06H, 00H, 00H + 85 85 $DGS LAB_SYM, bs_S0174, U, U, 00H, 06H, 00H, 00H + 86 86 $DGS LAB_SYM, es_S0174, U, U, 00H, 06H, 00H, 00H + 87 87 $DGS LAB_SYM, bs_S0175, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_S0175, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 91 91 $DGS STA_SYM, _MSG_MAIL, U, U, 05002H, 03H, 01H, 03H + 92 92 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H + 93 93 $DGS GLV_SYM, _LED_init, U, U, 01H, 026H, 01H, 02H + 94 94 $DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H + 95 95 $DGS BEG_FUN, ??bf_LED_init, U, U, 00H, 065H, 01H, 00H + 96 96 $DGS AUX_BEG, 028H, 00H, 051H + 97 97 $DGS BEG_BLK, ??bb00_LED_init, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_BEG, 027H, 00H, 00H + 99 99 $DGS END_BLK, ??eb00_LED_init, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_END, 02AH + 101 101 $DGS END_FUN, ??ef_LED_init, U, U, 00H, 065H, 01H, 00H + 102 102 $DGS AUX_END, 02BH + 103 103 $DGS GLV_SYM, _LED_stop, U, U, 01H, 026H, 01H, 02H + 104 104 $DGS AUX_FUN, 00H, U, U, 05DH, 00H, 00H + 105 105 $DGS BEG_FUN, ??bf_LED_stop, U, U, 00H, 065H, 01H, 00H + 106 106 $DGS AUX_BEG, 057H, 00H, 05DH + 107 107 $DGS END_FUN, ??ef_LED_stop, U, U, 00H, 065H, 01H, 00H + 108 108 $DGS AUX_END, 05H + 109 109 $DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 026H, 01H, 02H + 110 110 $DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H + 111 111 $DGS BEG_FUN, ??bf_tsk_led_pow, U, U, 00H, 065H, 01H, 00H + 112 112 $DGS AUX_BEG, 078H, 00H, 061H + 113 113 $DGS BEG_BLK, ??bb00_tsk_led_pow, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_BEG, 03H, 00H, 063H + 115 115 $DGS BEG_BLK, ??bb01_tsk_led_pow, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_BEG, 07H, 00H, 00H + 117 117 $DGS END_BLK, ??eb01_tsk_led_pow, U, U, 00H, 064H, 01H, 00H + 118 118 $DGS AUX_END, 012H + 119 119 $DGS END_BLK, ??eb00_tsk_led_pow, U, U, 00H, 064H, 01H, 00H + 120 120 $DGS AUX_END, 02DH + 121 121 $DGS END_FUN, ??ef_tsk_led_pow, U, U, 00H, 065H, 01H, 00H + 122 122 $DGS AUX_END, 02FH + 123 123 $DGS STA_SYM, _led_pow_normal, U, U, 01H, 03H, 01H, 02H + 124 124 $DGS AUX_FUN, 00H, U, U, 096H, 00H, 00H + 125 125 $DGS BEG_FUN, ??bf_led_pow_normal, U, U, 00H, 065H, 01H, 00H + 126 126 $DGS AUX_BEG, 0AEH, 00H, 070H + 127 127 $DGS STA_SYM, _state, ?L0031, U, 0CH, 03H, 00H, 00H + 128 128 $DGS BEG_BLK, ??bb00_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 129 129 $DGS AUX_BEG, 05H, 00H, 072H + 130 130 $DGS BEG_BLK, ??bb01_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 131 131 $DGS AUX_BEG, 09H, 00H, 076H + 132 132 $DGS END_BLK, ??eb01_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 133 133 $DGS AUX_END, 0CH + 134 134 $DGS BEG_BLK, ??bb02_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 135 135 $DGS AUX_BEG, 0EH, 00H, 07CH + 136 136 $DGS END_BLK, ??eb02_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 137 137 $DGS AUX_END, 010H + 138 138 $DGS END_BLK, ??eb00_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 139 139 $DGS AUX_END, 013H + 140 140 $DGS BEG_BLK, ??bb03_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 141 141 $DGS AUX_BEG, 015H, 00H, 07EH + 142 142 $DGS BEG_BLK, ??bb04_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 143 143 $DGS AUX_BEG, 018H, 00H, 082H + 144 144 $DGS END_BLK, ??eb04_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 145 145 $DGS AUX_END, 01AH + 146 146 $DGS BEG_BLK, ??bb05_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_BEG, 01CH, 00H, 088H + 148 148 $DGS END_BLK, ??eb05_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_END, 01EH + 150 150 $DGS END_BLK, ??eb03_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 151 151 $DGS AUX_END, 021H + 152 152 $DGS BEG_BLK, ??bb06_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 153 153 $DGS AUX_BEG, 023H, 00H, 08AH + 154 154 $DGS BEG_BLK, ??bb07_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_BEG, 026H, 00H, 08EH + 156 156 $DGS END_BLK, ??eb07_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_END, 028H + 158 158 $DGS BEG_BLK, ??bb08_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 159 159 $DGS AUX_BEG, 02AH, 00H, 00H + 160 160 $DGS END_BLK, ??eb08_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 161 161 $DGS AUX_END, 02CH + 162 162 $DGS END_BLK, ??eb06_led_pow_normal, U, U, 00H, 064H, 01H, 00H + 163 163 $DGS AUX_END, 02DH + 164 164 $DGS END_FUN, ??ef_led_pow_normal, U, U, 00H, 065H, 01H, 00H + 165 165 $DGS AUX_END, 030H + 166 166 $DGS STA_SYM, _led_pow_hotaru, U, U, 01H, 03H, 01H, 02H + 167 167 $DGS AUX_FUN, 00H, U, U, 0D8H, 00H, 00H + 168 168 $DGS BEG_FUN, ??bf_led_pow_hotaru, U, U, 00H, 065H, 01H, 00H + 169 169 $DGS AUX_BEG, 0E5H, 00H, 09EH + 170 170 $DGS STA_SYM, _delay, ?L0052, U, 0CH, 03H, 00H, 00H + 171 171 $DGS STA_SYM, _state, ?L0053, U, 0CH, 03H, 00H, 00H + 172 172 $DGS STA_SYM, _blue_to, ?L0054, U, 0DH, 03H, 00H, 00H + 173 173 $DGS STA_SYM, _red_to, ?L0055, U, 0DH, 03H, 00H, 00H + 174 174 $DGS BEG_BLK, ??bb00_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_BEG, 08H, 00H, 0A2H + 176 176 $DGS END_BLK, ??eb00_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_END, 0BH + 178 178 $DGS BEG_BLK, ??bb01_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_BEG, 0DH, 00H, 0A6H + 180 180 $DGS END_BLK, ??eb01_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_END, 0FH + 182 182 $DGS BEG_BLK, ??bb02_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 183 183 $DGS AUX_BEG, 012H, 00H, 0A8H + 184 184 $DGS BEG_BLK, ??bb03_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 185 185 $DGS AUX_BEG, 014H, 00H, 0ACH + 186 186 $DGS END_BLK, ??eb03_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 187 187 $DGS AUX_END, 016H + 188 188 $DGS BEG_BLK, ??bb04_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 189 189 $DGS AUX_BEG, 018H, 00H, 0B2H + 190 190 $DGS END_BLK, ??eb04_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_END, 01AH + 192 192 $DGS END_BLK, ??eb02_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_END, 01BH + 194 194 $DGS BEG_BLK, ??bb05_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_BEG, 01EH, 00H, 0B4H + 196 196 $DGS BEG_BLK, ??bb06_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_BEG, 020H, 00H, 0B8H + 198 198 $DGS END_BLK, ??eb06_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 199 199 $DGS AUX_END, 022H + 200 200 $DGS BEG_BLK, ??bb07_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 201 201 $DGS AUX_BEG, 024H, 00H, 0BEH + 202 202 $DGS END_BLK, ??eb07_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 203 203 $DGS AUX_END, 026H + 204 204 $DGS END_BLK, ??eb05_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 205 205 $DGS AUX_END, 027H + 206 206 $DGS BEG_BLK, ??bb08_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 207 207 $DGS AUX_BEG, 02AH, 00H, 0C0H + 208 208 $DGS BEG_BLK, ??bb09_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 209 209 $DGS AUX_BEG, 030H, 00H, 0C4H + 210 210 $DGS END_BLK, ??eb09_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 211 211 $DGS AUX_END, 034H + 212 212 $DGS BEG_BLK, ??bb0A_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 213 213 $DGS AUX_BEG, 036H, 00H, 0C8H + 214 214 $DGS END_BLK, ??eb0A_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 215 215 $DGS AUX_END, 039H + 216 216 $DGS BEG_BLK, ??bb0B_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 217 217 $DGS AUX_BEG, 03FH, 00H, 0CCH + 218 218 $DGS END_BLK, ??eb0B_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 219 219 $DGS AUX_END, 041H + 220 220 $DGS BEG_BLK, ??bb0C_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 221 221 $DGS AUX_BEG, 043H, 00H, 0D2H + 222 222 $DGS END_BLK, ??eb0C_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 223 223 $DGS AUX_END, 045H + 224 224 $DGS END_BLK, ??eb08_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 225 225 $DGS AUX_END, 047H + 226 226 $DGS BEG_BLK, ??bb0D_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 227 227 $DGS AUX_BEG, 04AH, 00H, 00H + 228 228 $DGS END_BLK, ??eb0D_led_pow_hotaru, U, U, 00H, 064H, 01H, 00H + 229 229 $DGS AUX_END, 04CH + 230 230 $DGS END_FUN, ??ef_led_pow_hotaru, U, U, 00H, 065H, 01H, 00H + 231 231 $DGS AUX_END, 04EH + 232 232 $DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 026H, 01H, 02H + 233 233 $DGS AUX_FUN, 00H, U, U, 0106H, 00H, 00H + 234 234 $DGS BEG_FUN, ??bf_tsk_led_wifi, U, U, 00H, 065H, 01H, 00H + 235 235 $DGS AUX_BEG, 013CH, 00H, 0E0H + 236 236 $DGS STA_SYM, _task_interval, ?L0079, U, 0CH, 03H, 00H, 00H + 237 237 $DGS STA_SYM, _remain_wifi_tx, ?L0080, U, 0CH, 03H, 00H, 00H + 238 238 $DGS STA_SYM, _state_wifi_tx, ?L0081, U, 0CH, 03H, 00H, 00H + 239 239 $DGS STA_SYM, _flag_wifi_TX, ?L0082, U, 0CH, 03H, 00H, 00H + 240 240 $DGS BEG_BLK, ??bb00_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 241 241 $DGS AUX_BEG, 09H, 00H, 0E4H + 242 242 $DGS END_BLK, ??eb00_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 243 243 $DGS AUX_END, 0BH + 244 244 $DGS BEG_BLK, ??bb01_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 245 245 $DGS AUX_BEG, 0FH, 00H, 0E6H + 246 246 $DGS BEG_BLK, ??bb02_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 247 247 $DGS AUX_BEG, 011H, 00H, 0ECH + 248 248 $DGS END_BLK, ??eb02_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 249 249 $DGS AUX_END, 014H + 250 250 $DGS END_BLK, ??eb01_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 251 251 $DGS AUX_END, 015H + 252 252 $DGS BEG_BLK, ??bb03_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 253 253 $DGS AUX_BEG, 017H, 00H, 0F0H + 254 254 $DGS END_BLK, ??eb03_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 255 255 $DGS AUX_END, 019H + 256 256 $DGS BEG_BLK, ??bb04_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 257 257 $DGS AUX_BEG, 01DH, 00H, 0F2H + 258 258 $DGS BEG_BLK, ??bb05_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 259 259 $DGS AUX_BEG, 02DH, 00H, 0F4H + 260 260 $DGS BEG_BLK, ??bb06_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 261 261 $DGS AUX_BEG, 030H, 00H, 0F8H + 262 262 $DGS END_BLK, ??eb06_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 263 263 $DGS AUX_END, 038H + 264 264 $DGS BEG_BLK, ??bb07_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 265 265 $DGS AUX_BEG, 03BH, 00H, 0FEH + 266 266 $DGS END_BLK, ??eb07_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 267 267 $DGS AUX_END, 03EH + 268 268 $DGS END_BLK, ??eb05_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 269 269 $DGS AUX_END, 041H + 270 270 $DGS BEG_BLK, ??bb08_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 271 271 $DGS AUX_BEG, 043H, 00H, 00H + 272 272 $DGS END_BLK, ??eb08_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 273 273 $DGS AUX_END, 048H + 274 274 $DGS END_BLK, ??eb04_tsk_led_wifi, U, U, 00H, 064H, 01H, 00H + 275 275 $DGS AUX_END, 04BH + 276 276 $DGS END_FUN, ??ef_tsk_led_wifi, U, U, 00H, 065H, 01H, 00H + 277 277 $DGS AUX_END, 04CH + 278 278 $DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 026H, 01H, 02H + 279 279 $DGS AUX_FUN, 00H, U, U, 014AH, 00H, 00H + 280 280 $DGS BEG_FUN, ??bf_tsk_led_notify, U, U, 00H, 065H, 01H, 00H + 281 281 $DGS AUX_BEG, 0191H, 02H, 010EH + 282 282 $DGS STA_SYM, _task_interval, ?L0107, U, 0CH, 03H, 00H, 00H + 283 283 $DGS STA_SYM, _flg_char_space, ?L0108, U, 0CH, 03H, 00H, 00H + 284 284 $DGS STA_SYM, _state_notify_led, ?L0109, U, 0CH, 03H, 00H, 00H + 285 285 $DGS STA_SYM, _flag_wifi_TX, ?L0110, U, 0CH, 03H, 00H, 00H + 286 286 $DGS BEG_BLK, ??bb00_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 287 287 $DGS AUX_BEG, 09H, 00H, 0112H + 288 288 $DGS END_BLK, ??eb00_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 289 289 $DGS AUX_END, 0BH + 290 290 $DGS BEG_BLK, ??bb01_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 291 291 $DGS AUX_BEG, 0EH, 00H, 0114H + 292 292 $DGS BEG_BLK, ??bb02_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 293 293 $DGS AUX_BEG, 01FH, 00H, 0118H + 294 294 $DGS END_BLK, ??eb02_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 295 295 $DGS AUX_END, 027H + 296 296 $DGS BEG_BLK, ??bb03_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 297 297 $DGS AUX_BEG, 02AH, 00H, 011CH + 298 298 $DGS END_BLK, ??eb03_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 299 299 $DGS AUX_END, 02CH + 300 300 $DGS BEG_BLK, ??bb04_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 301 301 $DGS AUX_BEG, 032H, 00H, 0120H + 302 302 $DGS REG_VAR, _dat, 06H, 0FFFFH, 010CH, 04H, 01H, 00H + 303 303 $DGS AUX_STR, 00H, 033H, 01H, 00H, 00H, 00H, 00H, 00H + 304 304 $DGS BEG_BLK, ??bb05_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 305 305 $DGS AUX_BEG, 038H, 00H, 0124H + 306 306 $DGS END_BLK, ??eb05_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 307 307 $DGS AUX_END, 03CH + 308 308 $DGS BEG_BLK, ??bb06_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 309 309 $DGS AUX_BEG, 041H, 00H, 0128H + 310 310 $DGS END_BLK, ??eb06_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 311 311 $DGS AUX_END, 043H + 312 312 $DGS BEG_BLK, ??bb07_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 313 313 $DGS AUX_BEG, 045H, 00H, 012CH + 314 314 $DGS END_BLK, ??eb07_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 315 315 $DGS AUX_END, 047H + 316 316 $DGS BEG_BLK, ??bb08_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 317 317 $DGS AUX_BEG, 04BH, 00H, 012EH + 318 318 $DGS BEG_BLK, ??bb09_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 319 319 $DGS AUX_BEG, 04FH, 00H, 0132H + 320 320 $DGS END_BLK, ??eb09_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 321 321 $DGS AUX_END, 052H + 322 322 $DGS BEG_BLK, ??bb0A_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 323 323 $DGS AUX_BEG, 054H, 00H, 0138H + 324 324 $DGS END_BLK, ??eb0A_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 325 325 $DGS AUX_END, 057H + 326 326 $DGS END_BLK, ??eb08_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 327 327 $DGS AUX_END, 05CH + 328 328 $DGS BEG_BLK, ??bb0B_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 329 329 $DGS AUX_BEG, 05EH, 00H, 013AH + 330 330 $DGS BEG_BLK, ??bb0C_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 331 331 $DGS AUX_BEG, 060H, 00H, 013EH + 332 332 $DGS END_BLK, ??eb0C_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 333 333 $DGS AUX_END, 063H + 334 334 $DGS BEG_BLK, ??bb0D_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 335 335 $DGS AUX_BEG, 065H, 00H, 00H + 336 336 $DGS END_BLK, ??eb0D_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 337 337 $DGS AUX_END, 068H + 338 338 $DGS END_BLK, ??eb0B_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 339 339 $DGS AUX_END, 06AH + 340 340 $DGS END_BLK, ??eb04_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 341 341 $DGS AUX_END, 06BH + 342 342 $DGS END_BLK, ??eb01_tsk_led_notify, U, U, 00H, 064H, 01H, 00H + 343 343 $DGS AUX_END, 06CH + 344 344 $DGS END_FUN, ??ef_tsk_led_notify, U, U, 00H, 065H, 01H, 00H + 345 345 $DGS AUX_END, 06DH + 346 346 $DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 026H, 01H, 02H + 347 347 $DGS AUX_FUN, 00H, U, U, 017FH, 00H, 00H + 348 348 $DGS BEG_FUN, ??bf_tsk_led_cam, U, U, 00H, 065H, 01H, 00H + 349 349 $DGS AUX_BEG, 0208H, 00H, 0151H + 350 350 $DGS STA_SYM, _state_led_cam, ?L0142, U, 0CH, 03H, 00H, 00H + 351 351 $DGS STA_SYM, _task_interval, ?L0143, U, 0CH, 03H, 00H, 00H + 352 352 $DGS STA_SYM, _state_led_cam_twl, ?L0144, U, 0CH, 03H, 00H, 00H + 353 353 $DGS BEG_BLK, ??bb00_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 354 354 $DGS AUX_BEG, 07H, 00H, 0155H + 355 355 $DGS END_BLK, ??eb00_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 356 356 $DGS AUX_END, 0AH + 357 357 $DGS BEG_BLK, ??bb01_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 358 358 $DGS AUX_BEG, 010H, 00H, 0157H + 359 359 $DGS BEG_BLK, ??bb02_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 360 360 $DGS AUX_BEG, 01EH, 00H, 015BH + 361 361 $DGS END_BLK, ??eb02_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 362 362 $DGS AUX_END, 021H + 363 363 $DGS BEG_BLK, ??bb03_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 364 364 $DGS AUX_BEG, 023H, 00H, 015FH + 365 365 $DGS END_BLK, ??eb03_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 366 366 $DGS AUX_END, 026H + 367 367 $DGS BEG_BLK, ??bb04_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 368 368 $DGS AUX_BEG, 02CH, 00H, 0163H + 369 369 $DGS END_BLK, ??eb04_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 370 370 $DGS AUX_END, 030H + 371 371 $DGS BEG_BLK, ??bb05_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 372 372 $DGS AUX_BEG, 032H, 00H, 0167H + 373 373 $DGS END_BLK, ??eb05_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 374 374 $DGS AUX_END, 034H + 375 375 $DGS BEG_BLK, ??bb06_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 376 376 $DGS AUX_BEG, 039H, 00H, 016BH + 377 377 $DGS END_BLK, ??eb06_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 378 378 $DGS AUX_END, 03DH + 379 379 $DGS BEG_BLK, ??bb07_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 380 380 $DGS AUX_BEG, 03FH, 00H, 016FH + 381 381 $DGS END_BLK, ??eb07_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 382 382 $DGS AUX_END, 041H + 383 383 $DGS BEG_BLK, ??bb08_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 384 384 $DGS AUX_BEG, 045H, 00H, 0171H + 385 385 $DGS BEG_BLK, ??bb09_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 386 386 $DGS AUX_BEG, 04DH, 00H, 0175H + 387 387 $DGS END_BLK, ??eb09_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 388 388 $DGS AUX_END, 050H + 389 389 $DGS BEG_BLK, ??bb0A_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 390 390 $DGS AUX_BEG, 052H, 00H, 00H + 391 391 $DGS END_BLK, ??eb0A_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 392 392 $DGS AUX_END, 055H + 393 393 $DGS END_BLK, ??eb08_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 394 394 $DGS AUX_END, 05FH + 395 395 $DGS END_BLK, ??eb01_tsk_led_cam, U, U, 00H, 064H, 01H, 00H + 396 396 $DGS AUX_END, 060H + 397 397 $DGS END_FUN, ??ef_tsk_led_cam, U, U, 00H, 065H, 01H, 00H + 398 398 $DGS AUX_END, 062H + 399 399 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 400 400 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 401 401 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 402 402 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 403 403 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 404 404 $DGS GLV_SYM, @@isrem, U, U, 00H, 02H, 00H, 00H + 405 405 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H + 406 406 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 407 407 + 408 408 EXTRN _vreg_ctr + 409 409 EXTRN _system_status + 410 410 EXTRN _@RTARG0 + 411 411 EXTRN @@isrem + 412 412 EXTRN _vreg_twl + 413 413 PUBLIC _LED_init + 414 414 PUBLIC _LED_stop + 415 415 PUBLIC _tsk_led_pow + 416 416 PUBLIC _tsk_led_wifi + 417 417 PUBLIC _tsk_led_notify + 418 418 PUBLIC _tsk_led_cam + 419 419 + 420 420 ----- @@BITS BSEG + 421 421 + 422 422 ----- @@CNST CSEG MIRRORP + 423 423 00000 01 _lpf_coeff: DB 01H ; 1 + 424 424 00001 02 DB 02H ; 2 + 425 425 00002 02 DB 02H ; 2 + 426 426 00003 03 DB 03H ; 3 + 427 427 00004 03 DB 03H ; 3 + 428 428 00005 02 DB 02H ; 2 + 429 429 00006 00 DB 00H ; 0 + 430 430 00007 FE DB 0FEH ; 254 + 431 431 00008 FB DB 0FBH ; 251 + 432 432 00009 F7 DB 0F7H ; 247 + 433 433 0000A F3 DB 0F3H ; 243 + 434 434 0000B F0 DB 0F0H ; 240 + 435 435 0000C F0 DB 0F0H ; 240 + 436 436 0000D F3 DB 0F3H ; 243 + 437 437 0000E FA DB 0FAH ; 250 + 438 438 0000F 04 DB 04H ; 4 + 439 439 00010 12 DB 012H ; 18 + 440 440 00011 25 DB 025H ; 37 + 441 441 00012 38 DB 038H ; 56 + 442 442 00013 4D DB 04DH ; 77 + 443 443 00014 5F DB 05FH ; 95 + 444 444 00015 6E DB 06EH ; 110 + 445 445 00016 77 DB 077H ; 119 + 446 446 00017 7A DB 07AH ; 122 + 447 447 00018 77 DB 077H ; 119 + 448 448 00019 6E DB 06EH ; 110 + 449 449 0001A 5F DB 05FH ; 95 + 450 450 0001B 4D DB 04DH ; 77 + 451 451 0001C 38 DB 038H ; 56 + 452 452 0001D 25 DB 025H ; 37 + 453 453 0001E 12 DB 012H ; 18 + 454 454 0001F 04 DB 04H ; 4 + 455 455 00020 FA DB 0FAH ; 250 + 456 456 00021 F3 DB 0F3H ; 243 + 457 457 00022 F0 DB 0F0H ; 240 + 458 458 00023 F0 DB 0F0H ; 240 + 459 459 00024 F3 DB 0F3H ; 243 + 460 460 00025 F7 DB 0F7H ; 247 + 461 461 00026 FB DB 0FBH ; 251 + 462 462 00027 FE DB 0FEH ; 254 + 463 463 00028 00 DB 00H ; 0 + 464 464 00029 02 DB 02H ; 2 + 465 465 0002A 03 DB 03H ; 3 + 466 466 0002B 03 DB 03H ; 3 + 467 467 0002C 02 DB 02H ; 2 + 468 468 0002D 02 DB 02H ; 2 + 469 469 0002E 01 DB 01H ; 1 + 470 470 0002F F6 _MSG_MAIL: DB 0F6H ; 246 + 471 471 00030 DA DB 0DAH ; 218 + 472 472 00031 6E DB 06EH ; 110 + 473 473 00032 94 DB 094H ; 148 + 474 474 00033 00 DB (1) + 475 475 + 476 476 ----- @@R_INIT CSEG UNIT64KP + 477 477 00000 00 DB 00H ; 0 + 478 478 00001 00 DB (1) + 479 479 + 480 480 ----- @@INIT DSEG BASEP + 481 481 00000 ?L0142: DS (1) + 482 482 00001 DS (1) + 483 483 + 484 484 ----- @@DATA DSEG BASEP + 485 485 00000 ?L0031: DS (1) + 486 486 00001 ?L0052: DS (1) + 487 487 00002 ?L0053: DS (1) + 488 488 00003 DS (1) + 489 489 00004 ?L0054: DS (2) + 490 490 00006 ?L0055: DS (2) + 491 491 00008 ?L0079: DS (1) + 492 492 00009 ?L0080: DS (1) + 493 493 0000A ?L0081: DS (1) + 494 494 0000B ?L0082: DS (1) + 495 495 0000C ?L0107: DS (1) + 496 496 0000D ?L0108: DS (1) + 497 497 0000E ?L0109: DS (1) + 498 498 0000F ?L0110: DS (1) + 499 499 00010 ?L0143: DS (1) + 500 500 00011 ?L0144: DS (1) + 501 501 + 502 502 ----- @@R_INIS CSEG UNIT64KP + 503 503 + 504 504 ----- @@INIS DSEG SADDRP + 505 505 + 506 506 ----- @@DATS DSEG SADDRP + 507 507 + 508 508 ----- @@CNSTL CSEG PAGE64KP + 509 509 + 510 510 ----- @@RLINIT CSEG UNIT64KP + 511 511 + 512 512 ----- @@INITL DSEG UNIT64KP + 513 513 + 514 514 ----- @@DATAL DSEG UNIT64KP + 515 515 + 516 516 ----- @@CALT CSEG CALLT0 + 517 517 + 518 518 ; Sub-Routines created by CC78K0R + 519 519 + 520 520 ----- ROM_CODE CSEG BASE + 521 521 00000 bs_S0172: + 522 522 00000 F1 clrb a ;[INF] 1, 1 + 523 523 00001 E7 onew bc ;[INF] 1, 1 + 524 524 00002 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 525 525 00005 D7 ret ;[INF] 1, 6 + 526 526 00006 es_S0172: + 527 527 + 528 528 ----- ROM_CODE CSEG BASE + 529 529 00006 bs_S0173: + 530 530 00006 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 531 531 00009 F1 clrb a ;[INF] 1, 1 + 532 532 0000A BE66 movw TDR03,ax ;[INF] 2, 1 + 533 533 0000C D7 ret ;[INF] 1, 6 + 534 534 0000D es_S0173: + 535 535 + 536 536 ----- ROM_CODE CSEG BASE + 537 537 0000D bs_S0174: + 538 538 0000D RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 539 539 00010 F1 clrb a ;[INF] 1, 1 + 540 540 00011 BE6A movw TDR05,ax ;[INF] 2, 1 + 541 541 00013 D7 ret ;[INF] 1, 6 + 542 542 00014 es_S0174: + 543 543 + 544 544 ----- ROM_CODE CSEG BASE + 545 545 00014 bs_S0175: + 546 546 00014 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 547 547 00017 F1 clrb a ;[INF] 1, 1 + 548 548 00018 BE64 movw TDR02,ax ;[INF] 2, 1 + 549 549 0001A D7 ret ;[INF] 1, 6 + 550 550 0001B es_S0175: + 551 551 + 552 552 ; *** Sub-Routine Information *** + 553 553 ; + 554 554 ; $SUB bs_S0172 + 555 555 ; CODE SIZE= 6 bytes + 556 556 ; + 557 557 ; $SUB bs_S0173 + 558 558 ; CODE SIZE= 7 bytes + 559 559 ; + 560 560 ; $SUB bs_S0174 + 561 561 ; CODE SIZE= 7 bytes + 562 562 ; + 563 563 ; $SUB bs_S0175 + 564 564 ; CODE SIZE= 7 bytes + 565 565 + 566 566 ; End of Sub-Routines + 567 567 + 568 568 ; line 1 : /* ======================================================== + 569 569 ; line 2 : LED.c + 570 570 ; line 3 : + 571 571 ; line 4 : ======================================================== */ + 572 572 ; line 5 : #pragma sfr + 573 573 ; line 6 : + 574 574 ; line 7 : + 575 575 ; line 8 : #include "incs.h" + 576 576 ; line 9 : #include "led.h" + 577 577 ; line 10 : + 578 578 ; line 11 : + 579 579 ; line 12 : + 580 580 ; line 13 : // ======================================================== + 581 581 ; line 14 : // TPS0 + 582 582 ; line 15 : #define BIT_PRS012 ( 1 << 2 ) + 583 583 ; line 16 : #define BIT_PRS002 ( 1 << 6 ) + 584 584 ; line 17 : + 585 585 ; line 18 : // TMR0 + 586 586 ; line 19 : #define BIT_CKS0 15 + 587 587 ; line 20 : #define BIT_CCS0 12 + 588 588 ; line 21 : #define BIT_MASTER0 11 + 589 589 ; line 22 : #define BIT_STS0 8 + 590 590 ; line 23 : #define BIT_CIS0 6 + 591 591 ; line 24 : #define BIT_MD123 1 + 592 592 ; line 25 : #define BIT_MD0 0 + 593 593 ; line 26 : + 594 594 ; line 27 : // ======================================================== + 595 595 ; line 28 : static void led_pow_normal( ); + 596 596 ; line 29 : static void led_pow_hotaru( ); + 597 597 ; line 30 : + 598 598 ; line 31 : + 599 599 ; line 32 : + 600 600 ; line 33 : // ======================================================== + 601 601 ; line 34 : static const char MSG_MAIL[] = { 0b11110110, 0b11011010, 0b01101 + 602 602 ; 110, 0b10010100 }; + 603 603 ; line 35 : #define MSG_SPD 60 + 604 604 ; line 36 : // ↑255/3以下であること！ + 605 605 ; line 37 : + 606 606 ; line 38 : // ======================================================== + 607 607 ; line 39 : void LED_init( ) + 608 608 ; line 40 : { + 609 609 + 610 610 ----- ROM_CODE CSEG BASE + 611 611 0001B _LED_init: + 612 612 $DGL 1,77 + 613 613 0001B ??bf_LED_init: + 614 614 ; line 41 : /** + 615 615 ; line 42 : PWMのセット、とりあえず全部消灯 + 616 616 ; line 43 : + 617 617 ; line 44 : マスタチャネル：０　(P01:/reset2)　マスターは偶数チャネルしかで + 618 618 ; きない + 619 619 ; line 45 : スレーブ　　　　１　ＳＬＴＯ。(３Ｄ ＬＥＤ？) + 620 620 ; line 46 : 　　　　　　　　２　カメラ + 621 621 ; line 47 : 　　　　　　　　３　WiFi + 622 622 ; line 48 : 　　　　　　　　４　(ピンはＲＴＣ32kHz out に使用) + 623 623 ; line 49 : 　　　　　　　　５　充電 + 624 624 ; line 50 : 　　　　　　　　６　電源 Ｌ + 625 625 ; line 51 : 　　　　　　　　７　電源 Ｈ + 626 626 ; line 52 : */ + 627 627 ; line 53 : TAU0EN = 1; + 628 628 $DGL 0,14 + 629 629 0001B 7100F200 set1 !PER2.0 ;[INF] 4, 2 + 630 630 ; line 54 : TPS0 = BIT_PRS012 | BIT_PRS002; // マスタークロックはCK0 + 631 631 ; 1,8M/2 /2^4 = 250kHz + 632 632 $DGL 0,15 + 633 633 0001F 304400 movw ax,#044H ; 68 ;[INF] 3, 1 + 634 634 00022 BFB601 movw !TPS0,ax ;[INF] 3, 1 + 635 635 ; line 55 : + 636 636 ; line 56 : TMR00 = + 637 637 ; line 57 : 1 << BIT_CKS0 | 0 << BIT_CCS0 | 1 << BIT_MASTER0 | 0 << + 638 638 ; BIT_STS0 | 0 + 639 639 ; line 58 : << BIT_CIS0 | 0 << BIT_MD123 | 1 << BIT_MD0; + 640 640 $DGL 0,19 + 641 641 00025 300188 movw ax,#08801H ; -30719 ;[INF] 3, 1 + 642 642 00028 BF9001 movw !TMR00,ax ;[INF] 3, 1 + 643 643 ; line 59 : TMR01 = TMR02 = TMR03 = TMR04 = TMR05 = TMR06 = TMR07 = + 644 644 ; line 60 : 1 << BIT_CKS0 | 0 << BIT_CCS0 | 0 << BIT_MASTER0 | 4 << + 645 645 ; BIT_STS0 | 0 + 646 646 ; line 61 : << BIT_CIS0 | 4 << BIT_MD123 | 1 << BIT_MD0; + 647 647 $DGL 0,22 + 648 648 0002B 300984 movw ax,#08409H ; -31735 ;[INF] 3, 1 + 649 649 0002E BF9E01 movw !TMR07,ax ;[INF] 3, 1 + 650 650 00031 BF9C01 movw !TMR06,ax ;[INF] 3, 1 + 651 651 00034 BF9A01 movw !TMR05,ax ;[INF] 3, 1 + 652 652 00037 BF9801 movw !TMR04,ax ;[INF] 3, 1 + 653 653 0003A BF9601 movw !TMR03,ax ;[INF] 3, 1 + 654 654 0003D BF9401 movw !TMR02,ax ;[INF] 3, 1 + 655 655 00040 BF9201 movw !TMR01,ax ;[INF] 3, 1 + 656 656 ; line 62 : ISC = 0; + 657 657 $DGL 0,23 + 658 658 00043 F53CFF clrb !ISC ;[INF] 3, 1 + 659 659 ; line 63 : TOM0 = 0b0000000011111110; // 出力モード。4はPWM出力しないが + 660 660 ; 1にしないとTO5以降にクロックが届かない + 661 661 $DGL 0,24 + 662 662 00046 30FE00 movw ax,#0FEH ; 254 ;[INF] 3, 1 + 663 663 00049 BFBE01 movw !TOM0,ax ;[INF] 3, 1 + 664 664 ; line 64 : + 665 665 ; line 65 : #ifdef _MCU_BSR_ + 666 666 ; line 66 : TOL0 = 0b0000000000000000; // 出力を反転させるかフラグ + 667 667 $DGL 0,27 + 668 668 0004C F6 clrw ax ;[INF] 1, 1 + 669 669 0004D BFBC01 movw !TOL0,ax ;[INF] 3, 1 + 670 670 ; line 67 : #else + 671 671 ; line 68 : TOL0 = 0b0000000000000100; // 出力を反転させるかフラグ + 672 672 ; line 69 : #endif + 673 673 ; line 70 : + 674 674 ; line 71 : TO0 = 0; // タイマー動作中で、タイマー出力 + 675 675 ; にしてないときのピンのラッチ。タイマー出力を使わないなら０ + 676 676 $DGL 0,32 + 677 677 00050 BFB801 movw !TO0,ax ;[INF] 3, 1 + 678 678 ; line 72 : TOE0 = 0b0000000011101110; // TOxをタイマーモジュールが制御？ + 679 679 $DGL 0,33 + 680 680 00053 50EE mov x,#0EEH ; 238 ;[INF] 2, 1 + 681 681 00055 BFBA01 movw !TOE0,ax ;[INF] 3, 1 + 682 682 ; line 73 : TS0 = 0b0000000011101111; // 動作開始 + 683 683 $DGL 0,34 + 684 684 00058 A1 incw ax ;[INF] 1, 1 + 685 685 00059 BFB201 movw !TS0,ax ;[INF] 3, 1 + 686 686 ; line 74 : + 687 687 ; line 75 : TDR00 = LED_BRIGHT_MAX - 1; // 10bit, 周期 + 688 688 $DGL 0,36 + 689 689 0005C C918FE00 movw TDR00,#0FEH ; 254 ;[INF] 4, 1 + 690 690 ; line 76 : + 691 691 ; line 77 : if( system_status.reboot ) + 692 692 $DGL 0,38 + 693 693 00060 R8F0200 mov a,!_system_status+2 ;[INF] 3, 1 + 694 694 00063 313507 bf a.3,$?L0003 ;[INF] 3, 5 + 695 695 ; line 78 : { + 696 696 00066 ??bb00_LED_init: + 697 697 ; line 79 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; + 698 698 $DGL 0,40 + 699 699 00066 RF52900 clrb !_vreg_ctr+41 ;[INF] 3, 1 + 700 700 ; line 80 : LED_duty_pow_H = LED_BRIGHT_MAX; + 701 701 $DGL 0,41 + 702 702 00069 CB6CFF00 movw TDR06,#0FFH ; 255 ;[INF] 4, 1 + 703 703 0006D ??eb00_LED_init: + 704 704 ; line 81 : } + 705 705 0006D ?L0003: + 706 706 ; line 82 : } + 707 707 $DGL 0,43 + 708 708 0006D ??ef_LED_init: + 709 709 0006D D7 ret ;[INF] 1, 6 + 710 710 0006E ??ee_LED_init: + 711 711 ; line 83 : + 712 712 ; line 84 : + 713 713 ; line 85 : + 714 714 ; line 86 : void LED_stop( ) + 715 715 ; line 87 : { + 716 716 0006E _LED_stop: + 717 717 $DGL 1,87 + 718 718 0006E ??bf_LED_stop: + 719 719 ; line 88 : TT0 = 0b0000000011101111; // 一斉停止（しないとだめ） + 720 720 $DGL 0,2 + 721 721 0006E 30EF00 movw ax,#0EFH ; 239 ;[INF] 3, 1 + 722 722 00071 BFB401 movw !TT0,ax ;[INF] 3, 1 + 723 723 ; line 89 : TOE0 = 0b0000000000000000; // TOxをタイマーモジュールが制御？ + 724 724 ; (GPIOになる) + 725 725 $DGL 0,3 + 726 726 00074 F6 clrw ax ;[INF] 1, 1 + 727 727 00075 BFBA01 movw !TOE0,ax ;[INF] 3, 1 + 728 728 ; line 90 : TAU0EN = 0; + 729 729 $DGL 0,4 + 730 730 00078 7108F200 clr1 !PER2.0 ;[INF] 4, 2 + 731 731 ; line 91 : } + 732 732 $DGL 0,5 + 733 733 0007C ??ef_LED_stop: + 734 734 0007C D7 ret ;[INF] 1, 6 + 735 735 0007D ??ee_LED_stop: + 736 736 ; line 92 : + 737 737 ; line 93 : + 738 738 ; line 94 : + 739 739 ; line 95 : + 740 740 ; line 96 : /* ======================================================== + 741 741 ; line 97 : // 電源LED + 742 742 ; line 98 : LED_POW_B,R 6,7 + 743 743 ; line 99 : + 744 744 ; line 100 : TDR00　周期(0x03FF。TPS0で250kHzでカウントアップ。10bitなら250 + 745 745 ; Hz位になる) + 746 746 ; line 101 : TDR0x　Duty 0で消灯、TDR00(より大 =0x03FF以上)で点灯です。 + 747 747 ; line 102 : + 748 748 ; line 103 : enum pwr_state_{ + 749 749 ; line 104 : OFF_TRIG = 0, + 750 750 ; line 105 : OFF, + 751 751 ; line 106 : ON_TRIG, + 752 752 ; line 107 : ON, + 753 753 ; line 108 : SLEEP_TRIG, + 754 754 ; line 109 : SLEEP + 755 755 ; line 110 : }; + 756 756 ; line 111 : + 757 757 ; line 112 : enum LED_ILUM_MODE{ + 758 758 ; line 113 : LED_POW_ILM_AUTO, + 759 759 ; line 114 : LED_POW_ILM_ON, + 760 760 ; line 115 : LED_POW_ILM_HOTARU, + 761 761 ; line 116 : LED_POW_ILM_CEOFF + 762 762 ; line 117 : }; + 763 763 ; line 118 : ======================================================== */ + 764 764 ; line 119 : void tsk_led_pow( ) + 765 765 ; line 120 : { + 766 766 0007D _tsk_led_pow: + 767 767 $DGL 1,93 + 768 768 0007D ??bf_tsk_led_pow: + 769 769 ; line 121 : switch ( vreg_ctr[VREG_C_LED_POW] ) + 770 770 $DGL 0,2 + 771 771 0007D RD92900 mov x,!_vreg_ctr+41 ;[INF] 3, 1 + 772 772 00080 RFD0000 call !bs_S0172 ;[INF] 3, 3 + 773 773 00083 DD11 bz $?L0010 ;[INF] 2, 4 + 774 774 00085 23 subw ax,bc ;[INF] 1, 1 + 775 775 00086 DD44 bz $?L0013 ;[INF] 2, 4 + 776 776 00088 23 subw ax,bc ;[INF] 1, 1 + 777 777 00089 DD3D bz $?L0012 ;[INF] 2, 4 + 778 778 0008B 23 subw ax,bc ;[INF] 1, 1 + 779 779 0008C DD1F bz $?L0011 ;[INF] 2, 4 + 780 780 0008E 23 subw ax,bc ;[INF] 1, 1 + 781 781 0008F DD3F bz $?L0015 ;[INF] 2, 4 + 782 782 00091 23 subw ax,bc ;[INF] 1, 1 + 783 783 00092 DD44 bz $?L0016 ;[INF] 2, 4 + 784 784 00094 EF36 br $?L0013 ;[INF] 2, 3 + 785 785 ; line 122 : { + 786 786 00096 ??bb00_tsk_led_pow: + 787 787 ; line 123 : // 自動切り替え + 788 788 ; line 124 : case ( LED_POW_ILM_AUTO ): + 789 789 00096 ?L0010: + 790 790 ; line 125 : switch ( system_status.pwr_state ) + 791 791 $DGL 0,6 + 792 792 00096 R8F0000 mov a,!_system_status ;[INF] 3, 1 + 793 793 00099 318F sarw ax,8 ;[INF] 2, 1 + 794 794 0009B 240300 subw ax,#03H ; 3 ;[INF] 3, 1 + 795 795 0009E DD09 bz $?L0021 ;[INF] 2, 4 + 796 796 000A0 240200 subw ax,#02H ; 2 ;[INF] 3, 1 + 797 797 000A3 DF3A bnz $?L0009 ;[INF] 2, 4 + 798 798 ; line 126 : { + 799 799 000A5 ??bb01_tsk_led_pow: + 800 800 ; line 127 : case SLEEP: + 801 801 ; line 128 : led_pow_hotaru( ); + 802 802 $DGL 0,9 + 803 803 000A5 RFD5101 call !_led_pow_hotaru ;[INF] 3, 3 + 804 804 ; line 129 : break; + 805 805 $DGL 0,10 + 806 806 000A8 D7 ret ;[INF] 1, 6 + 807 807 ; line 130 : + 808 808 ; line 131 : case ON: + 809 809 000A9 ?L0021: + 810 810 ; line 132 : led_pow_normal( ); + 811 811 $DGL 0,13 + 812 812 000A9 RFDE000 call !_led_pow_normal ;[INF] 3, 3 + 813 813 ; line 133 : break; + 814 814 $DGL 0,14 + 815 815 000AC D7 ret ;[INF] 1, 6 + 816 816 ; line 134 : + 817 817 ; line 135 : default: + 818 818 ; line 136 : break; + 819 819 000AD ??eb01_tsk_led_pow: + 820 820 ; line 137 : } + 821 821 ; line 138 : break; + 822 822 ; line 139 : + 823 823 ; line 140 : // 強制 + 824 824 ; line 141 : case ( LED_POW_ILM_OFF ): + 825 825 000AD ?L0011: + 826 826 ; line 142 : LED_duty_pow_H -= ( LED_duty_pow_H == 0x0000 ) ? 0 : 1; + 827 827 $DGL 0,23 + 828 828 000AD F6 clrw ax ;[INF] 1, 1 + 829 829 000AE 426CFF cmpw ax,!TDR06 ;[INF] 3, 1 + 830 830 000B1 61E8 skz ;[INF] 2, 1 + 831 831 000B3 E6 onew ax ;[INF] 1, 1 + 832 832 000B4 ?L0026: + 833 833 000B4 12 movw bc,ax ;[INF] 1, 1 + 834 834 000B5 AE6C movw ax,TDR06 ;[INF] 2, 1 + 835 835 000B7 23 subw ax,bc ;[INF] 1, 1 + 836 836 000B8 BE6C movw TDR06,ax ;[INF] 2, 1 + 837 837 ; line 143 : LED_duty_pow_L -= ( LED_duty_pow_L == 0x0000 ) ? 0 : 1; + 838 838 $DGL 0,24 + 839 839 000BA F6 clrw ax ;[INF] 1, 1 + 840 840 000BB 426EFF cmpw ax,!TDR07 ;[INF] 3, 1 + 841 841 000BE 61E8 skz ;[INF] 2, 1 + 842 842 000C0 E6 onew ax ;[INF] 1, 1 + 843 843 000C1 ?L0028: + 844 844 000C1 12 movw bc,ax ;[INF] 1, 1 + 845 845 000C2 AE6E movw ax,TDR07 ;[INF] 2, 1 + 846 846 000C4 23 subw ax,bc ;[INF] 1, 1 + 847 847 000C5 BE6E movw TDR07,ax ;[INF] 2, 1 + 848 848 ; line 144 : break; + 849 849 $DGL 0,25 + 850 850 000C7 D7 ret ;[INF] 1, 6 + 851 851 ; line 145 : + 852 852 ; line 146 : case ( LED_POW_ILM_HOTARU ): + 853 853 000C8 ?L0012: + 854 854 ; line 147 : led_pow_hotaru( ); + 855 855 $DGL 0,28 + 856 856 000C8 RFD5101 call !_led_pow_hotaru ;[INF] 3, 3 + 857 857 ; line 148 : break; + 858 858 $DGL 0,29 + 859 859 000CB D7 ret ;[INF] 1, 6 + 860 860 ; line 149 : + 861 861 ; line 150 : case ( LED_POW_ILM_ON ): + 862 862 000CC ?L0013: + 863 863 ; line 151 : default: + 864 864 ; line 152 : led_pow_normal( ); + 865 865 $DGL 0,33 + 866 866 000CC RFDE000 call !_led_pow_normal ;[INF] 3, 3 + 867 867 ; line 153 : break; + 868 868 $DGL 0,34 + 869 869 000CF D7 ret ;[INF] 1, 6 + 870 870 ; line 154 : + 871 871 ; line 155 : case ( LED_POW_ILM_ONLY_RED ): + 872 872 000D0 ?L0015: + 873 873 ; line 156 : LED_duty_pow_H = 0x0000; + 874 874 $DGL 0,37 + 875 875 000D0 F6 clrw ax ;[INF] 1, 1 + 876 876 000D1 BE6C movw TDR06,ax ;[INF] 2, 1 + 877 877 ; line 157 : LED_duty_pow_L = LED_BRIGHT_MAX; + 878 878 $DGL 0,38 + 879 879 000D3 CB6EFF00 movw TDR07,#0FFH ; 255 ;[INF] 4, 1 + 880 880 ; line 158 : break; + 881 881 $DGL 0,39 + 882 882 000D7 D7 ret ;[INF] 1, 6 + 883 883 ; line 159 : + 884 884 ; line 160 : case ( LED_POW_ILM_ONLY_BLUE ): + 885 885 000D8 ?L0016: + 886 886 ; line 161 : LED_duty_pow_H = LED_BRIGHT_MAX; + 887 887 $DGL 0,42 + 888 888 000D8 CB6CFF00 movw TDR06,#0FFH ; 255 ;[INF] 4, 1 + 889 889 ; line 162 : LED_duty_pow_L = 0x0000; + 890 890 $DGL 0,43 + 891 891 000DC F6 clrw ax ;[INF] 1, 1 + 892 892 000DD BE6E movw TDR07,ax ;[INF] 2, 1 + 893 893 ; line 163 : break; + 894 894 000DF ??eb00_tsk_led_pow: + 895 895 ; line 164 : } + 896 896 000DF ?L0009: + 897 897 ; line 165 : + 898 898 ; line 166 : } + 899 899 $DGL 0,47 + 900 900 000DF ??ef_tsk_led_pow: + 901 901 000DF D7 ret ;[INF] 1, 6 + 902 902 000E0 ??ee_tsk_led_pow: + 903 903 ; line 167 : + 904 904 ; line 168 : + 905 905 ; line 169 : + 906 906 ; line 170 : /* ======================================================== + 907 907 ; line 171 : 電池残量で、　青→赤→赤点滅 + 908 908 ; line 172 : ======================================================== */ + 909 909 ; line 173 : static void led_pow_normal( ) + 910 910 ; line 174 : { + 911 911 000E0 _led_pow_normal: + 912 912 $DGL 1,107 + 913 913 000E0 ??bf_led_pow_normal: + 914 914 ; line 175 : static u8 state; + 915 915 ; line 176 : + 916 916 ; line 177 : if( vreg_ctr[VREG_C_BT_REMAIN] < 3 ) + 917 917 $DGL 0,4 + 918 918 000E0 R400B0003 cmp !_vreg_ctr+11,#03H ; 3 ;[INF] 4, 1 + 919 919 000E4 DE17 bnc $?L0032 ;[INF] 2, 4 + 920 920 ; line 178 : { + 921 921 000E6 ??bb00_led_pow_normal: + 922 922 ; line 179 : // 赤点滅 + 923 923 ; line 180 : state++; + 924 924 $DGL 0,7 + 925 925 000E6 RA00000 inc !?L0031 ; state ;[INF] 3, 2 + 926 926 ; line 181 : if( state < 127 ) + 927 927 $DGL 0,8 + 928 928 000E9 R4000007F cmp !?L0031,#07FH ; state,127 ;[INF] 4, 1 + 929 929 000ED DE07 bnc $?L0034 ;[INF] 2, 4 + 930 930 ; line 182 : { + 931 931 000EF ??bb01_led_pow_normal: + 932 932 ; line 183 : LED_duty_pow_H = 0x0000; + 933 933 $DGL 0,10 + 934 934 000EF F6 clrw ax ;[INF] 1, 1 + 935 935 000F0 BE6C movw TDR06,ax ;[INF] 2, 1 + 936 936 ; line 184 : LED_duty_pow_L = 0x0000; + 937 937 $DGL 0,11 + 938 938 000F2 BE6E movw TDR07,ax ;[INF] 2, 1 + 939 939 000F4 ??eb01_led_pow_normal: + 940 940 ; line 185 : } + 941 941 $DGL 0,12 + 942 942 000F4 EF06 br $?L0035 ;[INF] 2, 3 + 943 943 000F6 ?L0034: + 944 944 ; line 186 : else + 945 945 ; line 187 : { + 946 946 000F6 ??bb02_led_pow_normal: + 947 947 ; line 188 : LED_duty_pow_L = vreg_ctr[VREG_C_LED_BRIGHT]; + 948 948 $DGL 0,15 + 949 949 000F6 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 950 950 000F9 F1 clrb a ;[INF] 1, 1 + 951 951 000FA BE6E movw TDR07,ax ;[INF] 2, 1 + 952 952 000FC ??eb02_led_pow_normal: + 953 953 ; line 189 : } + 954 954 000FC ?L0035: + 955 955 ; line 190 : return; + 956 956 $DGL 0,17 + 957 957 000FC D7 ret ;[INF] 1, 6 + 958 958 000FD ??eb00_led_pow_normal: + 959 959 ; line 191 : + 960 960 ; line 192 : } + 961 961 000FD ?L0032: + 962 962 ; line 193 : else if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + 963 963 $DGL 0,20 + 964 964 000FD R400B000C cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + 965 965 00101 DE27 bnc $?L0036 ;[INF] 2, 4 + 966 966 ; line 194 : { + 967 967 00103 ??bb03_led_pow_normal: + 968 968 ; line 195 : // 赤点灯 + 969 969 ; line 196 : if( LED_duty_pow_H != 0x0000 ) + 970 970 $DGL 0,23 + 971 971 00103 F6 clrw ax ;[INF] 1, 1 + 972 972 00104 426CFF cmpw ax,!TDR06 ;[INF] 3, 1 + 973 973 00107 61E8 skz ;[INF] 2, 1 + 974 974 ; line 197 : { // 青フェードアウト + 975 975 00109 ??bb04_led_pow_normal: + 976 976 ; line 198 : LED_duty_pow_H -= 1; + 977 977 $DGL 0,25 + 978 978 00109 B26CFF decw !TDR06 ;[INF] 3, 2 + 979 979 0010C ??eb04_led_pow_normal: + 980 980 ; line 199 : } + 981 981 0010C ?L0038: + 982 982 ; line 200 : if( LED_duty_pow_L != vreg_ctr[VREG_C_LED_BRIGHT] ) + 983 983 $DGL 0,27 + 984 984 0010C RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 985 985 0010F F1 clrb a ;[INF] 1, 1 + 986 986 00110 426EFF cmpw ax,!TDR07 ;[INF] 3, 1 + 987 987 00113 DD3B bz $?L0048 ;[INF] 2, 4 + 988 988 ; line 201 : { // 赤フェードイン + 989 989 00115 ??bb05_led_pow_normal: + 990 990 ; line 202 : LED_duty_pow_L += ( LED_duty_pow_L < vreg_ctr[VREG_C + 991 991 ; _LED_BRIGHT] ) ? 1 : -1; + 992 992 $DGL 0,29 + 993 993 00115 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 994 994 00118 12 movw bc,ax ;[INF] 1, 1 + 995 995 00119 AE6E movw ax,TDR07 ;[INF] 2, 1 + 996 996 0011B 43 cmpw ax,bc ;[INF] 1, 1 + 997 997 0011C DE03 bnc $?L0042 ;[INF] 2, 4 + 998 998 0011E E6 onew ax ;[INF] 1, 1 + 999 999 0011F EF02 br $?L0043 ;[INF] 2, 3 + 1000 1000 00121 ?L0042: + 1001 1001 00121 F6 clrw ax ;[INF] 1, 1 + 1002 1002 00122 B1 decw ax ;[INF] 1, 1 + 1003 1003 00123 ?L0043: + 1004 1004 00123 12 movw bc,ax ;[INF] 1, 1 + 1005 1005 00124 AE6E movw ax,TDR07 ;[INF] 2, 1 + 1006 1006 00126 03 addw ax,bc ;[INF] 1, 1 + 1007 1007 00127 BE6E movw TDR07,ax ;[INF] 2, 1 + 1008 1008 00129 ??eb05_led_pow_normal: + 1009 1009 ; line 203 : } + 1010 1010 ; line 204 : return; + 1011 1011 $DGL 0,31 + 1012 1012 00129 D7 ret ;[INF] 1, 6 + 1013 1013 0012A ??eb03_led_pow_normal: + 1014 1014 ; line 205 : + 1015 1015 ; line 206 : } + 1016 1016 0012A ?L0036: + 1017 1017 ; line 207 : else + 1018 1018 ; line 208 : { + 1019 1019 0012A ??bb06_led_pow_normal: + 1020 1020 ; line 209 : // 青点灯 + 1021 1021 ; line 210 : if( LED_duty_pow_H != vreg_ctr[VREG_C_LED_BRIGHT] ) + 1022 1022 $DGL 0,37 + 1023 1023 0012A RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 1024 1024 0012D F1 clrb a ;[INF] 1, 1 + 1025 1025 0012E 426CFF cmpw ax,!TDR06 ;[INF] 3, 1 + 1026 1026 00131 DD14 bz $?L0044 ;[INF] 2, 4 + 1027 1027 ; line 211 : { + 1028 1028 00133 ??bb07_led_pow_normal: + 1029 1029 ; line 212 : LED_duty_pow_H += ( LED_duty_pow_H < vreg_ctr[VREG_C + 1030 1030 ; _LED_BRIGHT] ) ? 1 : -1; + 1031 1031 $DGL 0,39 + 1032 1032 00133 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 1033 1033 00136 12 movw bc,ax ;[INF] 1, 1 + 1034 1034 00137 AE6C movw ax,TDR06 ;[INF] 2, 1 + 1035 1035 00139 43 cmpw ax,bc ;[INF] 1, 1 + 1036 1036 0013A DE03 bnc $?L0046 ;[INF] 2, 4 + 1037 1037 0013C E6 onew ax ;[INF] 1, 1 + 1038 1038 0013D EF02 br $?L0047 ;[INF] 2, 3 + 1039 1039 0013F ?L0046: + 1040 1040 0013F F6 clrw ax ;[INF] 1, 1 + 1041 1041 00140 B1 decw ax ;[INF] 1, 1 + 1042 1042 00141 ?L0047: + 1043 1043 00141 12 movw bc,ax ;[INF] 1, 1 + 1044 1044 00142 AE6C movw ax,TDR06 ;[INF] 2, 1 + 1045 1045 00144 03 addw ax,bc ;[INF] 1, 1 + 1046 1046 00145 BE6C movw TDR06,ax ;[INF] 2, 1 + 1047 1047 00147 ??eb07_led_pow_normal: + 1048 1048 ; line 213 : } + 1049 1049 00147 ?L0044: + 1050 1050 ; line 214 : if( LED_duty_pow_L != 0x0000 ) + 1051 1051 $DGL 0,41 + 1052 1052 00147 F6 clrw ax ;[INF] 1, 1 + 1053 1053 00148 426EFF cmpw ax,!TDR07 ;[INF] 3, 1 + 1054 1054 0014B 61E8 skz ;[INF] 2, 1 + 1055 1055 ; line 215 : { + 1056 1056 0014D ??bb08_led_pow_normal: + 1057 1057 ; line 216 : LED_duty_pow_L -= 1; + 1058 1058 $DGL 0,43 + 1059 1059 0014D B26EFF decw !TDR07 ;[INF] 3, 2 + 1060 1060 00150 ??eb08_led_pow_normal: + 1061 1061 ; line 217 : } + 1062 1062 00150 ?L0048: + 1063 1063 00150 ??eb06_led_pow_normal: + 1064 1064 ; line 218 : } + 1065 1065 ; line 219 : + 1066 1066 ; line 220 : return; + 1067 1067 ; line 221 : } + 1068 1068 $DGL 0,48 + 1069 1069 00150 ??ef_led_pow_normal: + 1070 1070 00150 D7 ret ;[INF] 1, 6 + 1071 1071 00151 ??ee_led_pow_normal: + 1072 1072 ; line 222 : + 1073 1073 ; line 223 : + 1074 1074 ; line 224 : + 1075 1075 ; line 225 : /* ======================================================== + 1076 1076 ; line 226 : ホタルパターン + 1077 1077 ; line 227 : ======================================================== */ + 1078 1078 ; line 228 : static void led_pow_hotaru( ) + 1079 1079 ; line 229 : { + 1080 1080 00151 _led_pow_hotaru: + 1081 1081 $DGL 1,150 + 1082 1082 00151 ??bf_led_pow_hotaru: + 1083 1083 ; line 230 : static u8 delay; + 1084 1084 ; line 231 : static u8 state; + 1085 1085 ; line 232 : static u16 blue_to; + 1086 1086 ; line 233 : static u16 red_to; + 1087 1087 ; line 234 : + 1088 1088 ; line 235 : if( delay != 0 ) + 1089 1089 $DGL 0,7 + 1090 1090 00151 RD50100 cmp0 !?L0052 ; delay ;[INF] 3, 1 + 1091 1091 00154 DD04 bz $?L0056 ;[INF] 2, 4 + 1092 1092 ; line 236 : { + 1093 1093 00156 ??bb00_led_pow_hotaru: + 1094 1094 ; line 237 : delay -= 1; + 1095 1095 $DGL 0,9 + 1096 1096 00156 RB00100 dec !?L0052 ; delay ;[INF] 3, 2 + 1097 1097 ; line 238 : return; + 1098 1098 $DGL 0,10 + 1099 1099 00159 D7 ret ;[INF] 1, 6 + 1100 1100 0015A ??eb00_led_pow_hotaru: + 1101 1101 ; line 239 : } + 1102 1102 0015A ?L0056: + 1103 1103 ; line 240 : else + 1104 1104 ; line 241 : { + 1105 1105 0015A ??bb01_led_pow_hotaru: + 1106 1106 ; line 242 : delay = 10; + 1107 1107 $DGL 0,14 + 1108 1108 0015A RCF01000A mov !?L0052,#0AH ; delay,10 ;[INF] 4, 1 + 1109 1109 0015E ??eb01_led_pow_hotaru: + 1110 1110 ; line 243 : } + 1111 1111 ; line 244 : + 1112 1112 ; line 245 : if( LED_duty_pow_L != red_to ) + 1113 1113 $DGL 0,17 + 1114 1114 0015E AE6E movw ax,TDR07 ;[INF] 2, 1 + 1115 1115 00160 R420600 cmpw ax,!?L0055 ; red_to ;[INF] 3, 1 + 1116 1116 00163 DD13 bz $?L0061 ;[INF] 2, 4 + 1117 1117 ; line 246 : { + 1118 1118 00165 ??bb02_led_pow_hotaru: + 1119 1119 ; line 247 : if( LED_duty_pow_L > red_to ) + 1120 1120 $DGL 0,19 + 1121 1121 00165 RAF0600 movw ax,!?L0055 ; red_to ;[INF] 3, 1 + 1122 1122 00168 426EFF cmpw ax,!TDR07 ;[INF] 3, 1 + 1123 1123 0016B DE05 bnc $?L0060 ;[INF] 2, 4 + 1124 1124 ; line 248 : { + 1125 1125 0016D ??bb03_led_pow_hotaru: + 1126 1126 ; line 249 : LED_duty_pow_L -= 1; + 1127 1127 $DGL 0,21 + 1128 1128 0016D B26EFF decw !TDR07 ;[INF] 3, 2 + 1129 1129 00170 ??eb03_led_pow_hotaru: + 1130 1130 ; line 250 : } + 1131 1131 $DGL 0,22 + 1132 1132 00170 EF06 br $?L0061 ;[INF] 2, 3 + 1133 1133 00172 ?L0060: + 1134 1134 ; line 251 : else + 1135 1135 ; line 252 : { + 1136 1136 00172 ??bb04_led_pow_hotaru: + 1137 1137 ; line 253 : LED_duty_pow_L += 2; + 1138 1138 $DGL 0,25 + 1139 1139 00172 AE6E movw ax,TDR07 ;[INF] 2, 1 + 1140 1140 00174 A1 incw ax ;[INF] 1, 1 + 1141 1141 00175 A1 incw ax ;[INF] 1, 1 + 1142 1142 00176 BE6E movw TDR07,ax ;[INF] 2, 1 + 1143 1143 00178 ??eb04_led_pow_hotaru: + 1144 1144 ; line 254 : } + 1145 1145 00178 ?L0061: + 1146 1146 00178 ??eb02_led_pow_hotaru: + 1147 1147 ; line 255 : } + 1148 1148 ; line 256 : + 1149 1149 ; line 257 : if( LED_duty_pow_H != blue_to ) + 1150 1150 $DGL 0,29 + 1151 1151 00178 AE6C movw ax,TDR06 ;[INF] 2, 1 + 1152 1152 0017A R420400 cmpw ax,!?L0054 ; blue_to ;[INF] 3, 1 + 1153 1153 0017D DD13 bz $?L0065 ;[INF] 2, 4 + 1154 1154 ; line 258 : { + 1155 1155 0017F ??bb05_led_pow_hotaru: + 1156 1156 ; line 259 : if( LED_duty_pow_H > blue_to ) + 1157 1157 $DGL 0,31 + 1158 1158 0017F RAF0400 movw ax,!?L0054 ; blue_to ;[INF] 3, 1 + 1159 1159 00182 426CFF cmpw ax,!TDR06 ;[INF] 3, 1 + 1160 1160 00185 DE05 bnc $?L0064 ;[INF] 2, 4 + 1161 1161 ; line 260 : { + 1162 1162 00187 ??bb06_led_pow_hotaru: + 1163 1163 ; line 261 : LED_duty_pow_H -= 1; + 1164 1164 $DGL 0,33 + 1165 1165 00187 B26CFF decw !TDR06 ;[INF] 3, 2 + 1166 1166 0018A ??eb06_led_pow_hotaru: + 1167 1167 ; line 262 : } + 1168 1168 $DGL 0,34 + 1169 1169 0018A EF06 br $?L0065 ;[INF] 2, 3 + 1170 1170 0018C ?L0064: + 1171 1171 ; line 263 : else + 1172 1172 ; line 264 : { + 1173 1173 0018C ??bb07_led_pow_hotaru: + 1174 1174 ; line 265 : LED_duty_pow_H += 2; + 1175 1175 $DGL 0,37 + 1176 1176 0018C AE6C movw ax,TDR06 ;[INF] 2, 1 + 1177 1177 0018E A1 incw ax ;[INF] 1, 1 + 1178 1178 0018F A1 incw ax ;[INF] 1, 1 + 1179 1179 00190 BE6C movw TDR06,ax ;[INF] 2, 1 + 1180 1180 00192 ??eb07_led_pow_hotaru: + 1181 1181 ; line 266 : } + 1182 1182 00192 ?L0065: + 1183 1183 00192 ??eb05_led_pow_hotaru: + 1184 1184 ; line 267 : } + 1185 1185 ; line 268 : + 1186 1186 ; line 269 : switch ( state ) + 1187 1187 $DGL 0,41 + 1188 1188 00192 RD90200 mov x,!?L0053 ; state ;[INF] 3, 1 + 1189 1189 00195 F1 clrb a ;[INF] 1, 1 + 1190 1190 00196 F7 clrw bc ;[INF] 1, 1 + 1191 1191 00197 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 1192 1192 0019A 23 subw ax,bc ;[INF] 1, 1 + 1193 1193 0019B DD06 bz $?L0067 ;[INF] 2, 4 + 1194 1194 0019D 25 subw ax,de ;[INF] 1, 1 + 1195 1195 0019E DD03 bz $?L0067 ;[INF] 2, 4 + 1196 1196 001A0 25 subw ax,de ;[INF] 1, 1 + 1197 1197 001A1 DF1F bnz $?L0068 ;[INF] 2, 4 + 1198 1198 ; line 270 : { + 1199 1199 001A3 ??bb08_led_pow_hotaru: + 1200 1200 ; line 271 : // フェードイン + 1201 1201 ; line 272 : case ( 0 ): + 1202 1202 001A3 ?L0067: + 1203 1203 ; line 273 : case ( 2 ): + 1204 1204 ; line 274 : case ( 4 ): + 1205 1205 ; line 275 : if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + 1206 1206 $DGL 0,47 + 1207 1207 001A3 R400B000C cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + 1208 1208 001A7 DE0C bnc $?L0071 ;[INF] 2, 4 + 1209 1209 ; line 276 : { + 1210 1210 001A9 ??bb09_led_pow_hotaru: + 1211 1211 ; line 277 : // 赤いとき + 1212 1212 ; line 278 : blue_to = 0; + 1213 1213 $DGL 0,50 + 1214 1214 001A9 F6 clrw ax ;[INF] 1, 1 + 1215 1215 001AA RBF0400 movw !?L0054,ax ; blue_to ;[INF] 3, 1 + 1216 1216 ; line 279 : red_to = vreg_ctr[VREG_C_LED_BRIGHT]; + 1217 1217 $DGL 0,51 + 1218 1218 001AD RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 1219 1219 001B0 RBF0600 movw !?L0055,ax ; red_to ;[INF] 3, 1 + 1220 1220 001B3 ??eb09_led_pow_hotaru: + 1221 1221 ; line 280 : } + 1222 1222 $DGL 0,52 + 1223 1223 001B3 EF1F br $?L0066 ;[INF] 2, 3 + 1224 1224 001B5 ?L0071: + 1225 1225 ; line 281 : else + 1226 1226 ; line 282 : { + 1227 1227 001B5 ??bb0A_led_pow_hotaru: + 1228 1228 ; line 283 : blue_to = vreg_ctr[VREG_C_LED_BRIGHT]; + 1229 1229 $DGL 0,55 + 1230 1230 001B5 RD92800 mov x,!_vreg_ctr+40 ;[INF] 3, 1 + 1231 1231 001B8 F1 clrb a ;[INF] 1, 1 + 1232 1232 001B9 RBF0400 movw !?L0054,ax ; blue_to ;[INF] 3, 1 + 1233 1233 ; line 284 : red_to = 0; + 1234 1234 $DGL 0,56 + 1235 1235 001BC F6 clrw ax ;[INF] 1, 1 + 1236 1236 001BD RBF0600 movw !?L0055,ax ; red_to ;[INF] 3, 1 + 1237 1237 001C0 ??eb0A_led_pow_hotaru: + 1238 1238 ; line 285 : } + 1239 1239 ; line 286 : break; + 1240 1240 $DGL 0,58 + 1241 1241 001C0 EF12 br $?L0066 ;[INF] 2, 3 + 1242 1242 ; line 287 : + 1243 1243 ; line 288 : default: + 1244 1244 001C2 ?L0068: + 1245 1245 ; line 289 : // フェードアウト + 1246 1246 ; line 290 : if( vreg_ctr[VREG_C_BT_REMAIN] < 12 ) + 1247 1247 $DGL 0,62 + 1248 1248 001C2 R400B000C cmp !_vreg_ctr+11,#0CH ; 12 ;[INF] 4, 1 + 1249 1249 001C6 DE07 bnc $?L0073 ;[INF] 2, 4 + 1250 1250 ; line 291 : { + 1251 1251 001C8 ??bb0B_led_pow_hotaru: + 1252 1252 ; line 292 : red_to = 2; + 1253 1253 $DGL 0,64 + 1254 1254 001C8 E6 onew ax ;[INF] 1, 1 + 1255 1255 001C9 A1 incw ax ;[INF] 1, 1 + 1256 1256 001CA RBF0600 movw !?L0055,ax ; red_to ;[INF] 3, 1 + 1257 1257 001CD ??eb0B_led_pow_hotaru: + 1258 1258 ; line 293 : } + 1259 1259 $DGL 0,65 + 1260 1260 001CD EF05 br $?L0066 ;[INF] 2, 3 + 1261 1261 001CF ?L0073: + 1262 1262 ; line 294 : else + 1263 1263 ; line 295 : { + 1264 1264 001CF ??bb0C_led_pow_hotaru: + 1265 1265 ; line 296 : blue_to = 2; + 1266 1266 $DGL 0,68 + 1267 1267 001CF E6 onew ax ;[INF] 1, 1 + 1268 1268 001D0 A1 incw ax ;[INF] 1, 1 + 1269 1269 001D1 RBF0400 movw !?L0054,ax ; blue_to ;[INF] 3, 1 + 1270 1270 001D4 ??eb0C_led_pow_hotaru: + 1271 1271 ; line 297 : } + 1272 1272 ; line 298 : break; + 1273 1273 001D4 ??eb08_led_pow_hotaru: + 1274 1274 ; line 299 : } + 1275 1275 001D4 ?L0066: + 1276 1276 ; line 300 : + 1277 1277 ; line 301 : if( ( LED_duty_pow_H == blue_to ) && ( LED_duty_pow_L == red + 1278 1278 ; _to ) ) + 1279 1279 $DGL 0,73 + 1280 1280 001D4 AE6C movw ax,TDR06 ;[INF] 2, 1 + 1281 1281 001D6 R420400 cmpw ax,!?L0054 ; blue_to ;[INF] 3, 1 + 1282 1282 001D9 DF0A bnz $?L0075 ;[INF] 2, 4 + 1283 1283 001DB AE6E movw ax,TDR07 ;[INF] 2, 1 + 1284 1284 001DD R420600 cmpw ax,!?L0055 ; red_to ;[INF] 3, 1 + 1285 1285 001E0 61F8 sknz ;[INF] 2, 1 + 1286 1286 ; line 302 : { + 1287 1287 001E2 ??bb0D_led_pow_hotaru: + 1288 1288 ; line 303 : state += 1; + 1289 1289 $DGL 0,75 + 1290 1290 001E2 RA00200 inc !?L0053 ; state ;[INF] 3, 2 + 1291 1291 001E5 ??eb0D_led_pow_hotaru: + 1292 1292 ; line 304 : } + 1293 1293 001E5 ?L0075: + 1294 1294 ; line 305 : return; + 1295 1295 ; line 306 : } + 1296 1296 $DGL 0,78 + 1297 1297 001E5 ??ef_led_pow_hotaru: + 1298 1298 001E5 D7 ret ;[INF] 1, 6 + 1299 1299 001E6 ??ee_led_pow_hotaru: + 1300 1300 ; line 307 : + 1301 1301 ; line 308 : + 1302 1302 ; line 309 : + 1303 1303 ; line 310 : /* ======================================================== + 1304 1304 ; line 311 : * 割り込みそのものは使いません * + 1305 1305 ; line 312 : LED_Wifi 3 + 1306 1306 ; line 313 : todo 直書きの点滅間隔など + 1307 1307 ; line 314 : ======================================================== */ + 1308 1308 ; line 315 : void tsk_led_wifi( ) + 1309 1309 ; line 316 : { + 1310 1310 001E6 _tsk_led_wifi: + 1311 1311 $DGL 1,216 + 1312 1312 001E6 ??bf_tsk_led_wifi: + 1313 1313 ; line 317 : static u8 task_interval; + 1314 1314 ; line 318 : static u8 remain_wifi_tx; + 1315 1315 ; line 319 : static u8 state_wifi_tx; + 1316 1316 ; line 320 : static u8 flag_wifi_TX; + 1317 1317 ; line 321 : + 1318 1318 ; line 322 : + 1319 1319 ; line 323 : if( task_interval-- != 0 ) + 1320 1320 $DGL 0,8 + 1321 1321 001E6 R8F0800 mov a,!?L0079 ; task_interval ;[INF] 3, 1 + 1322 1322 001E9 RB00800 dec !?L0079 ; task_interval ;[INF] 3, 2 + 1323 1323 001EC D1 cmp0 a ;[INF] 1, 1 + 1324 1324 001ED DF71 bnz $?L0089 ;[INF] 2, 4 + 1325 1325 ; line 324 : { + 1326 1326 001EF ??bb00_tsk_led_wifi: + 1327 1327 ; line 325 : return; + 1328 1328 001EF ??eb00_tsk_led_wifi: + 1329 1329 ; line 326 : } + 1330 1330 ; line 327 : + 1331 1331 ; line 328 : // 送信パルスのラッチ + 1332 1332 ; line 329 : if( vreg_ctr[VREG_C_LED_WIFI] == WIFI_LED_TXAUTO ) + 1333 1333 $DGL 0,14 + 1334 1334 001EF R402A0002 cmp !_vreg_ctr+42,#02H ; 2 ;[INF] 4, 1 + 1335 1335 001F3 DF0D bnz $?L0085 ;[INF] 2, 4 + 1336 1336 ; line 330 : { + 1337 1337 001F5 ??bb01_tsk_led_wifi: + 1338 1338 ; line 331 : if( WIFI_txLatch ) + 1339 1339 $DGL 0,16 + 1340 1340 001F5 31D4D10C bf IF2H.5,$?L0086 ;[INF] 4, 5 + 1341 1341 ; line 332 : { + 1342 1342 001F9 ??bb02_tsk_led_wifi: + 1343 1343 ; line 333 : WIFI_txLatch = 0; + 1344 1344 $DGL 0,18 + 1345 1345 001F9 715BD1 clr1 IF2H.5 ;[INF] 3, 2 + 1346 1346 ; line 334 : flag_wifi_TX = 2; + 1347 1347 $DGL 0,19 + 1348 1348 001FC RCF0B0002 mov !?L0082,#02H ; flag_wifi_TX,2 ;[INF] 4, 1 + 1349 1349 00200 ??eb02_tsk_led_wifi: + 1350 1350 ; line 335 : } + 1351 1351 ; line 336 : } + 1352 1352 $DGL 0,21 + 1353 1353 00200 ??eb01_tsk_led_wifi: + 1354 1354 00200 EF03 br $?L0086 ;[INF] 2, 3 + 1355 1355 00202 ?L0085: + 1356 1356 ; line 337 : else + 1357 1357 ; line 338 : { + 1358 1358 00202 ??bb03_tsk_led_wifi: + 1359 1359 ; line 339 : flag_wifi_TX = 0; + 1360 1360 $DGL 0,24 + 1361 1361 00202 RF50B00 clrb !?L0082 ; flag_wifi_TX ;[INF] 3, 1 + 1362 1362 00205 ??eb03_tsk_led_wifi: + 1363 1363 ; line 340 : } + 1364 1364 00205 ?L0086: + 1365 1365 ; line 341 : + 1366 1366 ; line 342 : + 1367 1367 ; line 343 : switch ( vreg_ctr[VREG_C_LED_WIFI] ) + 1368 1368 $DGL 0,28 + 1369 1369 00205 RD92A00 mov x,!_vreg_ctr+42 ;[INF] 3, 1 + 1370 1370 00208 RFD0000 call !bs_S0172 ;[INF] 3, 3 + 1371 1371 0020B DD06 bz $?L0090 ;[INF] 2, 4 + 1372 1372 0020D 23 subw ax,bc ;[INF] 1, 1 + 1373 1373 0020E DD0D bz $?L0092 ;[INF] 2, 4 + 1374 1374 00210 23 subw ax,bc ;[INF] 1, 1 + 1375 1375 00211 DD14 bz $?L0093 ;[INF] 2, 4 + 1376 1376 ; line 344 : { + 1377 1377 00213 ??bb04_tsk_led_wifi: + 1378 1378 ; line 345 : case ( WIFI_LED_OFF ): + 1379 1379 00213 ?L0090: + 1380 1380 ; line 346 : default: + 1381 1381 ; line 347 : LED_duty_WiFi = 0; + 1382 1382 $DGL 0,32 + 1383 1383 00213 F6 clrw ax ;[INF] 1, 1 + 1384 1384 00214 BE66 movw TDR03,ax ;[INF] 2, 1 + 1385 1385 ; line 348 : state_wifi_tx = 0; + 1386 1386 $DGL 0,33 + 1387 1387 00216 RF50A00 clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 + 1388 1388 ; line 349 : remain_wifi_tx = 0; + 1389 1389 $DGL 0,34 + 1390 1390 00219 RF50900 clrb !?L0080 ; remain_wifi_tx ;[INF] 3, 1 + 1391 1391 ; line 350 : break; + 1392 1392 $DGL 0,35 + 1393 1393 0021C D7 ret ;[INF] 1, 6 + 1394 1394 ; line 351 : + 1395 1395 ; line 352 : case ( WIFI_LED_ON ): + 1396 1396 0021D ?L0092: + 1397 1397 ; line 353 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + 1398 1398 $DGL 0,38 + 1399 1399 0021D RFD0600 call !bs_S0173 ;[INF] 3, 3 + 1400 1400 ; line 354 : state_wifi_tx = 0; + 1401 1401 $DGL 0,39 + 1402 1402 00220 RF50A00 clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 + 1403 1403 ; line 355 : remain_wifi_tx = 0; + 1404 1404 $DGL 0,40 + 1405 1405 00223 RF50900 clrb !?L0080 ; remain_wifi_tx ;[INF] 3, 1 + 1406 1406 ; line 356 : break; + 1407 1407 $DGL 0,41 + 1408 1408 00226 D7 ret ;[INF] 1, 6 + 1409 1409 ; line 357 : + 1410 1410 ; line 358 : case ( WIFI_LED_TXAUTO ): + 1411 1411 00227 ?L0093: + 1412 1412 ; line 359 : if( flag_wifi_TX != 0 ) // 短いパルスを捕まえるために、割 + 1413 1413 ; り込みフラグを見る + 1414 1414 $DGL 0,44 + 1415 1415 00227 RD50B00 cmp0 !?L0082 ; flag_wifi_TX ;[INF] 3, 1 + 1416 1416 0022A DD2D bz $?L0096 ;[INF] 2, 4 + 1417 1417 ; line 360 : { + 1418 1418 0022C ??bb05_tsk_led_wifi: + 1419 1419 ; line 361 : // 送信パターン + 1420 1420 ; line 362 : switch ( state_wifi_tx ) + 1421 1421 $DGL 0,47 + 1422 1422 0022C RD90A00 mov x,!?L0081 ; state_wifi_tx ;[INF] 3, 1 + 1423 1423 0022F F1 clrb a ;[INF] 1, 1 + 1424 1424 00230 E7 onew bc ;[INF] 1, 1 + 1425 1425 00231 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 1426 1426 00234 23 subw ax,bc ;[INF] 1, 1 + 1427 1427 00235 DD06 bz $?L0099 ;[INF] 2, 4 + 1428 1428 00237 25 subw ax,de ;[INF] 1, 1 + 1429 1429 00238 DD03 bz $?L0099 ;[INF] 2, 4 + 1430 1430 0023A 25 subw ax,de ;[INF] 1, 1 + 1431 1431 0023B DF05 bnz $?L0100 ;[INF] 2, 4 + 1432 1432 ; line 363 : { + 1433 1433 0023D ??bb06_tsk_led_wifi: + 1434 1434 ; line 364 : case ( 1 ): + 1435 1435 0023D ?L0099: + 1436 1436 ; line 365 : case ( 3 ): + 1437 1437 ; line 366 : case ( 5 ): + 1438 1438 ; line 367 : LED_duty_WiFi = 0; + 1439 1439 $DGL 0,52 + 1440 1440 0023D F6 clrw ax ;[INF] 1, 1 + 1441 1441 0023E BE66 movw TDR03,ax ;[INF] 2, 1 + 1442 1442 ; line 368 : break; + 1443 1443 $DGL 0,53 + 1444 1444 00240 EF03 br $?L0098 ;[INF] 2, 3 + 1445 1445 ; line 369 : default: + 1446 1446 00242 ?L0100: + 1447 1447 ; line 370 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + 1448 1448 $DGL 0,55 + 1449 1449 00242 RFD0600 call !bs_S0173 ;[INF] 3, 3 + 1450 1450 00245 ??eb06_tsk_led_wifi: + 1451 1451 ; line 371 : } + 1452 1452 00245 ?L0098: + 1453 1453 ; line 372 : state_wifi_tx++; + 1454 1454 $DGL 0,57 + 1455 1455 00245 RA00A00 inc !?L0081 ; state_wifi_tx ;[INF] 3, 2 + 1456 1456 ; line 373 : if( state_wifi_tx == 32 ) + 1457 1457 $DGL 0,58 + 1458 1458 00248 R400A0020 cmp !?L0081,#020H ; state_wifi_tx,32 ;[INF] 4, 1 + 1459 1459 0024C DF06 bnz $?L0103 ;[INF] 2, 4 + 1460 1460 ; line 374 : { + 1461 1461 0024E ??bb07_tsk_led_wifi: + 1462 1462 ; line 375 : state_wifi_tx = 0; + 1463 1463 $DGL 0,60 + 1464 1464 0024E RF50A00 clrb !?L0081 ; state_wifi_tx ;[INF] 3, 1 + 1465 1465 ; line 376 : flag_wifi_TX -= 1; + 1466 1466 $DGL 0,61 + 1467 1467 00251 RB00B00 dec !?L0082 ; flag_wifi_TX ;[INF] 3, 2 + 1468 1468 00254 ??eb07_tsk_led_wifi: + 1469 1469 ; line 377 : } + 1470 1470 00254 ?L0103: + 1471 1471 ; line 378 : task_interval = 22; + 1472 1472 $DGL 0,63 + 1473 1473 00254 RCF080016 mov !?L0079,#016H ; task_interval,22 ;[INF] 4, 1 + 1474 1474 ; line 379 : return; + 1475 1475 $DGL 0,64 + 1476 1476 00258 D7 ret ;[INF] 1, 6 + 1477 1477 00259 ??eb05_tsk_led_wifi: + 1478 1478 ; line 380 : } + 1479 1479 00259 ?L0096: + 1480 1480 ; line 381 : else + 1481 1481 ; line 382 : { + 1482 1482 00259 ??bb08_tsk_led_wifi: + 1483 1483 ; line 383 : // 送信フラグ待ち + 1484 1484 ; line 384 : LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT]; + 1485 1485 $DGL 0,69 + 1486 1486 00259 RFD0600 call !bs_S0173 ;[INF] 3, 3 + 1487 1487 ; line 385 : task_interval = 200; + 1488 1488 $DGL 0,70 + 1489 1489 0025C RCF0800C8 mov !?L0079,#0C8H ; task_interval,200 ;[INF] 4, 1 + 1490 1490 ; line 386 : return; + 1491 1491 00260 ??eb08_tsk_led_wifi: + 1492 1492 ; line 387 : } + 1493 1493 ; line 388 : break; + 1494 1494 00260 ??eb04_tsk_led_wifi: + 1495 1495 ; line 389 : + 1496 1496 ; line 390 : } + 1497 1497 00260 ?L0089: + 1498 1498 ; line 391 : } + 1499 1499 $DGL 0,76 + 1500 1500 00260 ??ef_tsk_led_wifi: + 1501 1501 00260 D7 ret ;[INF] 1, 6 + 1502 1502 00261 ??ee_tsk_led_wifi: + 1503 1503 ; line 392 : + 1504 1504 ; line 393 : + 1505 1505 ; line 394 : + 1506 1506 ; line 395 : + 1507 1507 ; line 396 : /* ======================================================== + 1508 1508 ; line 397 : * 割り込みそのものは使いません * + 1509 1509 ; line 398 : LED_Wifi2 P24 （未） + 1510 1510 ; line 399 : ======================================================== */ + 1511 1511 ; line 400 : void tsk_led_notify( ) + 1512 1512 ; line 401 : { + 1513 1513 00261 _tsk_led_notify: + 1514 1514 $DGL 1,262 + 1515 1515 00261 C7 push hl ;[INF] 1, 1 + 1516 1516 00262 ??bf_tsk_led_notify: + 1517 1517 ; line 402 : static u8 task_interval; + 1518 1518 ; line 403 : static u8 flg_char_space; + 1519 1519 ; line 404 : static u8 state_notify_led; // 点灯パターンの進行具合 + 1520 1520 ; line 405 : static u8 flag_wifi_TX; + 1521 1521 ; line 406 : + 1522 1522 ; line 407 : + 1523 1523 ; line 408 : if( task_interval-- != 0 ) + 1524 1524 $DGL 0,8 + 1525 1525 00262 R8F0C00 mov a,!?L0107 ; task_interval ;[INF] 3, 1 + 1526 1526 00265 RB00C00 dec !?L0107 ; task_interval ;[INF] 3, 2 + 1527 1527 00268 D1 cmp0 a ;[INF] 1, 1 + 1528 1528 00269 61E8 skz ;[INF] 2, 1 + 1529 1529 0026B RED2703 br !?L0135 ;[INF] 3, 3 + 1530 1530 ; line 409 : { + 1531 1531 0026E ??bb00_tsk_led_notify: + 1532 1532 ; line 410 : return; + 1533 1533 0026E ??eb00_tsk_led_notify: + 1534 1534 ; line 411 : } + 1535 1535 ; line 412 : + 1536 1536 ; line 413 : switch ( vreg_ctr[VREG_C_LED_NOTIFY] ) + 1537 1537 $DGL 0,13 + 1538 1538 0026E RD92D00 mov x,!_vreg_ctr+45 ;[INF] 3, 1 + 1539 1539 00271 RFD0000 call !bs_S0172 ;[INF] 3, 3 + 1540 1540 00274 DD09 bz $?L0114 ;[INF] 2, 4 + 1541 1541 00276 23 subw ax,bc ;[INF] 1, 1 + 1542 1542 00277 DD12 bz $?L0116 ;[INF] 2, 4 + 1543 1543 00279 23 subw ax,bc ;[INF] 1, 1 + 1544 1544 0027A DD1B bz $?L0117 ;[INF] 2, 4 + 1545 1545 0027C 23 subw ax,bc ;[INF] 1, 1 + 1546 1546 0027D DD43 bz $?L0118 ;[INF] 2, 4 + 1547 1547 ; line 414 : { + 1548 1548 0027F ??bb01_tsk_led_notify: + 1549 1549 ; line 415 : case ( NOTIFY_LED_OFF ): + 1550 1550 0027F ?L0114: + 1551 1551 ; line 416 : default: + 1552 1552 ; line 417 : LED_duty_NOTIFY = 0; + 1553 1553 $DGL 0,17 + 1554 1554 0027F F6 clrw ax ;[INF] 1, 1 + 1555 1555 00280 BE6A movw TDR05,ax ;[INF] 2, 1 + 1556 1556 ; line 418 : state_notify_led = 0; + 1557 1557 $DGL 0,18 + 1558 1558 00282 RF50E00 clrb !?L0109 ; state_notify_led ;[INF] 3, 1 + 1559 1559 ; line 419 : flg_char_space = 0; + 1560 1560 $DGL 0,19 + 1561 1561 00285 RF50D00 clrb !?L0108 ; flg_char_space ;[INF] 3, 1 + 1562 1562 ; line 420 : break; + 1563 1563 $DGL 0,20 + 1564 1564 00288 RED2703 br !?L0135 ;[INF] 3, 3 + 1565 1565 ; line 421 : + 1566 1566 ; line 422 : case ( NOTIFY_LED_ON ): + 1567 1567 0028B ?L0116: + 1568 1568 ; line 423 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + 1569 1569 $DGL 0,23 + 1570 1570 0028B RFD0D00 call !bs_S0174 ;[INF] 3, 3 + 1571 1571 ; line 424 : state_notify_led = 0; + 1572 1572 $DGL 0,24 + 1573 1573 0028E RF50E00 clrb !?L0109 ; state_notify_led ;[INF] 3, 1 + 1574 1574 ; line 425 : flg_char_space = 0; + 1575 1575 $DGL 0,25 + 1576 1576 00291 RF50D00 clrb !?L0108 ; flg_char_space ;[INF] 3, 1 + 1577 1577 ; line 426 : break; + 1578 1578 $DGL 0,26 + 1579 1579 00294 RED2703 br !?L0135 ;[INF] 3, 3 + 1580 1580 ; line 427 : + 1581 1581 ; line 428 : case ( NOTIFY_LED_PTN0 ): + 1582 1582 00297 ?L0117: + 1583 1583 ; line 429 : // ゆっくりバースト + 1584 1584 ; line 430 : switch ( state_notify_led ) + 1585 1585 $DGL 0,30 + 1586 1586 00297 RD90E00 mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + 1587 1587 0029A F1 clrb a ;[INF] 1, 1 + 1588 1588 0029B E7 onew bc ;[INF] 1, 1 + 1589 1589 0029C 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 1590 1590 0029F 23 subw ax,bc ;[INF] 1, 1 + 1591 1591 002A0 DD06 bz $?L0122 ;[INF] 2, 4 + 1592 1592 002A2 25 subw ax,de ;[INF] 1, 1 + 1593 1593 002A3 DD03 bz $?L0122 ;[INF] 2, 4 + 1594 1594 002A5 25 subw ax,de ;[INF] 1, 1 + 1595 1595 002A6 DF05 bnz $?L0123 ;[INF] 2, 4 + 1596 1596 ; line 431 : { + 1597 1597 002A8 ??bb02_tsk_led_notify: + 1598 1598 ; line 432 : case ( 1 ): + 1599 1599 002A8 ?L0122: + 1600 1600 ; line 433 : case ( 3 ): + 1601 1601 ; line 434 : case ( 5 ): + 1602 1602 ; line 435 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + 1603 1603 $DGL 0,35 + 1604 1604 002A8 RFD0D00 call !bs_S0174 ;[INF] 3, 3 + 1605 1605 ; line 436 : break; + 1606 1606 $DGL 0,36 + 1607 1607 002AB EF03 br $?L0121 ;[INF] 2, 3 + 1608 1608 ; line 437 : default: + 1609 1609 002AD ?L0123: + 1610 1610 ; line 438 : LED_duty_NOTIFY = 0; + 1611 1611 $DGL 0,38 + 1612 1612 002AD F6 clrw ax ;[INF] 1, 1 + 1613 1613 002AE BE6A movw TDR05,ax ;[INF] 2, 1 + 1614 1614 002B0 ??eb02_tsk_led_notify: + 1615 1615 ; line 439 : } + 1616 1616 002B0 ?L0121: + 1617 1617 ; line 440 : state_notify_led++; + 1618 1618 $DGL 0,40 + 1619 1619 002B0 RA00E00 inc !?L0109 ; state_notify_led ;[INF] 3, 2 + 1620 1620 ; line 441 : if( state_notify_led == 16 ) + 1621 1621 $DGL 0,41 + 1622 1622 002B3 R400E0010 cmp !?L0109,#010H ; state_notify_led,16 ;[INF] 4, 1 + 1623 1623 002B7 61F8 sknz ;[INF] 2, 1 + 1624 1624 ; line 442 : { + 1625 1625 002B9 ??bb03_tsk_led_notify: + 1626 1626 ; line 443 : state_notify_led = 0; + 1627 1627 $DGL 0,43 + 1628 1628 002B9 RF50E00 clrb !?L0109 ; state_notify_led ;[INF] 3, 1 + 1629 1629 002BC ??eb03_tsk_led_notify: + 1630 1630 ; line 444 : } + 1631 1631 002BC ?L0126: + 1632 1632 ; line 445 : task_interval = 50; + 1633 1633 $DGL 0,45 + 1634 1634 002BC RCF0C0032 mov !?L0107,#032H ; task_interval,50 ;[INF] 4, 1 + 1635 1635 ; line 446 : return; + 1636 1636 $DGL 0,46 + 1637 1637 002C0 EF65 br $?L0135 ;[INF] 2, 3 + 1638 1638 ; line 447 : + 1639 1639 ; line 448 : case ( NOTIFY_LED_PTN1 ): + 1640 1640 002C2 ?L0118: + 1641 1641 ; line 449 : // データテーブルに従って点滅 + 1642 1642 ; line 450 : { + 1643 1643 002C2 ??bb04_tsk_led_notify: + 1644 1644 ; line 451 : u8 dat; + 1645 1645 ; line 452 : + 1646 1646 ; line 453 : task_interval = MSG_SPD; // 共通のため。場合によって + 1647 1647 ; 上書き + 1648 1648 $DGL 0,53 + 1649 1649 002C2 RCF0C003C mov !?L0107,#03CH ; task_interval,60 ;[INF] 4, 1 + 1650 1650 ; line 454 : + 1651 1651 ; line 455 : if( flg_char_space != 0 ) + 1652 1652 $DGL 0,55 + 1653 1653 002C6 RD50D00 cmp0 !?L0108 ; flg_char_space ;[INF] 3, 1 + 1654 1654 002C9 DD08 bz $?L0128 ;[INF] 2, 4 + 1655 1655 ; line 456 : { + 1656 1656 002CB ??bb05_tsk_led_notify: + 1657 1657 ; line 457 : LED_duty_NOTIFY = 0; + 1658 1658 $DGL 0,57 + 1659 1659 002CB F6 clrw ax ;[INF] 1, 1 + 1660 1660 002CC BE6A movw TDR05,ax ;[INF] 2, 1 + 1661 1661 ; line 458 : flg_char_space = 0; + 1662 1662 $DGL 0,58 + 1663 1663 002CE RF50D00 clrb !?L0108 ; flg_char_space ;[INF] 3, 1 + 1664 1664 ; line 459 : return; + 1665 1665 $DGL 0,59 + 1666 1666 002D1 EF54 br $?L0135 ;[INF] 2, 3 + 1667 1667 002D3 ??eb05_tsk_led_notify: + 1668 1668 ; line 460 : } + 1669 1669 002D3 ?L0128: + 1670 1670 ; line 461 : + 1671 1671 ; line 462 : // データバッファの見る位置の更新 + 1672 1672 ; line 463 : dat = ( MSG_MAIL[state_notify_led / 4] << ( ( state_ + 1673 1673 ; notify_led % 4 ) * 2 ) ) & 0xC0; + 1674 1674 $DGL 0,63 + 1675 1675 002D3 RD90E00 mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + 1676 1676 002D6 F1 clrb a ;[INF] 1, 1 + 1677 1677 002D7 RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 1678 1678 002D9 5004 mov x,#04H ; 4 ;[INF] 2, 1 + 1679 1679 002DB RFD0000 call !@@isrem ;[INF] 3, 3 + 1680 1680 002DE 01 addw ax,ax ;[INF] 1, 1 + 1681 1681 002DF 08 xch a,x ;[INF] 1, 1 + 1682 1682 002E0 72 mov c,a ;[INF] 1, 1 + 1683 1683 002E1 08 xch a,x ;[INF] 1, 1 + 1684 1684 002E2 RD90E00 mov x,!?L0109 ; state_notify_led ;[INF] 3, 1 + 1685 1685 002E5 F1 clrb a ;[INF] 1, 1 + 1686 1686 002E6 312F sarw ax,2 ;[INF] 2, 1 + 1687 1687 002E8 R042F00 addw ax,#loww (_MSG_MAIL) ;[INF] 3, 1 + 1688 1688 002EB 14 movw de,ax ;[INF] 1, 1 + 1689 1689 002EC 89 mov a,[de] ;[INF] 1, 1 + 1690 1690 002ED 318F sarw ax,8 ;[INF] 2, 1 + 1691 1691 002EF D2 cmp0 c ;[INF] 1, 1 + 1692 1692 002F0 DD04 bz $?L0130 ;[INF] 2, 4 + 1693 1693 002F2 ?L0131: + 1694 1694 002F2 01 addw ax,ax ;[INF] 1, 1 + 1695 1695 002F3 92 dec c ;[INF] 1, 1 + 1696 1696 002F4 DFFC bnz $?L0131 ;[INF] 2, 4 + 1697 1697 002F6 ?L0130: + 1698 1698 002F6 60 mov a,x ;[INF] 1, 1 + 1699 1699 002F7 5CC0 and a,#0C0H ; 192 ;[INF] 2, 1 + 1700 1700 002F9 76 mov l,a ;[INF] 1, 1 + 1701 1701 ; line 464 : if( dat == 0 ) + 1702 1702 $DGL 0,64 + 1703 1703 002FA D1 cmp0 a ;[INF] 1, 1 + 1704 1704 002FB DF05 bnz $?L0132 ;[INF] 2, 4 + 1705 1705 ; line 465 : { + 1706 1706 002FD ??bb06_tsk_led_notify: + 1707 1707 ; line 466 : state_notify_led = 0; + 1708 1708 $DGL 0,66 + 1709 1709 002FD RF50E00 clrb !?L0109 ; state_notify_led ;[INF] 3, 1 + 1710 1710 00300 ??eb06_tsk_led_notify: + 1711 1711 ; line 467 : } + 1712 1712 $DGL 0,67 + 1713 1713 00300 EF03 br $?L0133 ;[INF] 2, 3 + 1714 1714 00302 ?L0132: + 1715 1715 ; line 468 : else + 1716 1716 ; line 469 : { + 1717 1717 00302 ??bb07_tsk_led_notify: + 1718 1718 ; line 470 : state_notify_led += 1; + 1719 1719 $DGL 0,70 + 1720 1720 00302 RA00E00 inc !?L0109 ; state_notify_led ;[INF] 3, 2 + 1721 1721 00305 ??eb07_tsk_led_notify: + 1722 1722 ; line 471 : } + 1723 1723 00305 ?L0133: + 1724 1724 ; line 472 : + 1725 1725 ; line 473 : flg_char_space = 1; + 1726 1726 $DGL 0,73 + 1727 1727 00305 RE50D00 oneb !?L0108 ; flg_char_space ;[INF] 3, 1 + 1728 1728 ; line 474 : if(( dat & 0b10000000 ) != 0 ) + 1729 1729 $DGL 0,74 + 1730 1730 00308 66 mov a,l ;[INF] 1, 1 + 1731 1731 00309 5C80 and a,#080H ; 128 ;[INF] 2, 1 + 1732 1732 0030B D1 cmp0 a ;[INF] 1, 1 + 1733 1733 0030C DD0F bz $?L0134 ;[INF] 2, 4 + 1734 1734 ; line 475 : { + 1735 1735 0030E ??bb08_tsk_led_notify: + 1736 1736 ; line 476 : // 点灯はさせる + 1737 1737 ; line 477 : LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT]; + 1738 1738 $DGL 0,77 + 1739 1739 0030E RFD0D00 call !bs_S0174 ;[INF] 3, 3 + 1740 1740 ; line 478 : if(( dat & 0b01000000 ) == 0 ) + 1741 1741 $DGL 0,78 + 1742 1742 00311 66 mov a,l ;[INF] 1, 1 + 1743 1743 00312 5C40 and a,#040H ; 64 ;[INF] 2, 1 + 1744 1744 00314 D1 cmp0 a ;[INF] 1, 1 + 1745 1745 00315 DD10 bz $?L0135 ;[INF] 2, 4 + 1746 1746 ; line 479 : { + 1747 1747 00317 ??bb09_tsk_led_notify: + 1748 1748 00317 ??eb09_tsk_led_notify: + 1749 1749 ; line 480 : // 短 + 1750 1750 ; line 481 : // nothing to do + 1751 1751 ; line 482 : } + 1752 1752 ; line 483 : else + 1753 1753 ; line 484 : { + 1754 1754 00317 ??bb0A_tsk_led_notify: + 1755 1755 ; line 485 : // 長 + 1756 1756 ; line 486 : task_interval = ( MSG_SPD * 3 ); + 1757 1757 $DGL 0,86 + 1758 1758 00317 RCF0C00B4 mov !?L0107,#0B4H ; task_interval,180 ;[INF] 4, 1 + 1759 1759 0031B ??eb0A_tsk_led_notify: + 1760 1760 ; line 487 : } + 1761 1761 ; line 488 : // 次は単語間休み、とかの判定をさせたかったが + 1762 1762 ; line 489 : /// １バイトに２ビットずつデータが並んでおり、次 + 1763 1763 ; のバイトに + 1764 1764 ; line 490 : /// またがるようなときが面倒なのでやめる + 1765 1765 ; line 491 : return; + 1766 1766 $DGL 0,91 + 1767 1767 0031B EF0A br $?L0135 ;[INF] 2, 3 + 1768 1768 0031D ??eb08_tsk_led_notify: + 1769 1769 ; line 492 : } + 1770 1770 0031D ?L0134: + 1771 1771 ; line 493 : else + 1772 1772 ; line 494 : { + 1773 1773 0031D ??bb0B_tsk_led_notify: + 1774 1774 ; line 495 : if(( dat & 0b01000000 ) == 0 ) + 1775 1775 $DGL 0,95 + 1776 1776 0031D 66 mov a,l ;[INF] 1, 1 + 1777 1777 0031E 5C40 and a,#040H ; 64 ;[INF] 2, 1 + 1778 1778 00320 D1 cmp0 a ;[INF] 1, 1 + 1779 1779 00321 61F8 sknz ;[INF] 2, 1 + 1780 1780 ; line 496 : { + 1781 1781 00323 ??bb0C_tsk_led_notify: + 1782 1782 ; line 497 : // 一文終了 + 1783 1783 ; line 498 : task_interval = ( MSG_SPD * 3 ); + 1784 1784 $DGL 0,98 + 1785 1785 00323 RCF0C00B4 mov !?L0107,#0B4H ; task_interval,180 ;[INF] 4, 1 + 1786 1786 00327 ??eb0C_tsk_led_notify: + 1787 1787 ; line 499 : } + 1788 1788 ; line 500 : else + 1789 1789 ; line 501 : { + 1790 1790 00327 ??bb0D_tsk_led_notify: + 1791 1791 00327 ??eb0D_tsk_led_notify: + 1792 1792 ; line 502 : // 単語間 + 1793 1793 ; line 503 : // nothing to do + 1794 1794 ; line 504 : } + 1795 1795 ; line 505 : return; + 1796 1796 00327 ??eb0B_tsk_led_notify: + 1797 1797 ; line 506 : } + 1798 1798 00327 ?L0135: + 1799 1799 00327 ??eb04_tsk_led_notify: + 1800 1800 ; line 507 : } + 1801 1801 00327 ??eb01_tsk_led_notify: + 1802 1802 ; line 508 : } + 1803 1803 ; line 509 : } + 1804 1804 $DGL 0,109 + 1805 1805 00327 ??ef_tsk_led_notify: + 1806 1806 00327 C6 pop hl ;[INF] 1, 1 + 1807 1807 00328 D7 ret ;[INF] 1, 6 + 1808 1808 00329 ??ee_tsk_led_notify: + 1809 1809 ; line 510 : + 1810 1810 ; line 511 : + 1811 1811 ; line 512 : + 1812 1812 ; line 513 : + 1813 1813 ; line 514 : /******************************************************//** + 1814 1814 ; line 515 : LED_Cam TO02 + 1815 1815 ; line 516 : \n BLINK,*_PLUSE の時は、1周期分は必ずその状態になります。 + 1816 1816 ; line 517 : \n その間に OFF→BLINK などされると、OFFが無視されます。 + 1817 1817 ; line 518 : *********************************************************/ + 1818 1818 ; line 519 : void tsk_led_cam( ) + 1819 1819 ; line 520 : { + 1820 1820 00329 _tsk_led_cam: + 1821 1821 $DGL 1,330 + 1822 1822 00329 ??bf_tsk_led_cam: + 1823 1823 ; line 521 : static u8 state_led_cam = 0; + 1824 1824 ; line 522 : static u8 task_interval; + 1825 1825 ; line 523 : static u8 state_led_cam_twl; + 1826 1826 ; line 524 : + 1827 1827 ; line 525 : if( task_interval != 0 ) + 1828 1828 $DGL 0,6 + 1829 1829 00329 RD51000 cmp0 !?L0143 ; task_interval ;[INF] 3, 1 + 1830 1830 0032C DD04 bz $?L0145 ;[INF] 2, 4 + 1831 1831 ; line 526 : { + 1832 1832 0032E ??bb00_tsk_led_cam: + 1833 1833 ; line 527 : task_interval -= 1; + 1834 1834 $DGL 0,8 + 1835 1835 0032E RB01000 dec !?L0143 ; task_interval ;[INF] 3, 2 + 1836 1836 ; line 528 : return; + 1837 1837 $DGL 0,9 + 1838 1838 00331 D7 ret ;[INF] 1, 6 + 1839 1839 00332 ??eb00_tsk_led_cam: + 1840 1840 ; line 529 : } + 1841 1841 00332 ?L0145: + 1842 1842 ; line 530 : + 1843 1843 ; line 531 : // ブリンクのように待たせたいとき以外は毎週起動する + 1844 1844 ; line 532 : // (レジスタの変更にすぐに反応する) + 1845 1845 ; line 533 : + 1846 1846 ; line 534 : switch ( vreg_ctr[VREG_C_LED_CAM] ) + 1847 1847 $DGL 0,15 + 1848 1848 00332 RD92B00 mov x,!_vreg_ctr+43 ;[INF] 3, 1 + 1849 1849 00335 RFD0000 call !bs_S0172 ;[INF] 3, 3 + 1850 1850 00338 DD0F bz $?L0148 ;[INF] 2, 4 + 1851 1851 0033A 23 subw ax,bc ;[INF] 1, 1 + 1852 1852 0033B DD1A bz $?L0151 ;[INF] 2, 4 + 1853 1853 0033D 23 subw ax,bc ;[INF] 1, 1 + 1854 1854 0033E DD10 bz $?L0150 ;[INF] 2, 4 + 1855 1855 00340 23 subw ax,bc ;[INF] 1, 1 + 1856 1856 00341 DD55 bz $?L0154 ;[INF] 2, 4 + 1857 1857 00343 23 subw ax,bc ;[INF] 1, 1 + 1858 1858 00344 DD29 bz $?L0152 ;[INF] 2, 4 + 1859 1859 00346 23 subw ax,bc ;[INF] 1, 1 + 1860 1860 00347 DD3A bz $?L0153 ;[INF] 2, 4 + 1861 1861 ; line 535 : { + 1862 1862 00349 ??bb01_tsk_led_cam: + 1863 1863 ; line 536 : case ( CAM_LED_OFF ): + 1864 1864 00349 ?L0148: + 1865 1865 ; line 537 : default: + 1866 1866 ; line 538 : LED_duty_CAM = 0; + 1867 1867 $DGL 0,19 + 1868 1868 00349 F6 clrw ax ;[INF] 1, 1 + 1869 1869 0034A BE64 movw TDR02,ax ;[INF] 2, 1 + 1870 1870 ; line 539 : state_led_cam = 0; + 1871 1871 $DGL 0,20 + 1872 1872 0034C RF50000 clrb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1873 1873 ; line 540 : break; + 1874 1874 $DGL 0,21 + 1875 1875 0034F D7 ret ;[INF] 1, 6 + 1876 1876 ; line 541 : + 1877 1877 ; line 542 : case ( CAM_LED_ON ): + 1878 1878 00350 ?L0150: + 1879 1879 ; line 543 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + 1880 1880 $DGL 0,24 + 1881 1881 00350 RFD1400 call !bs_S0175 ;[INF] 3, 3 + 1882 1882 ; line 544 : state_led_cam = 0; + 1883 1883 $DGL 0,25 + 1884 1884 00353 RF50000 clrb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1885 1885 ; line 545 : break; + 1886 1886 $DGL 0,26 + 1887 1887 00356 D7 ret ;[INF] 1, 6 + 1888 1888 ; line 546 : + 1889 1889 ; line 547 : case ( CAM_LED_BLINK ): + 1890 1890 00357 ?L0151: + 1891 1891 ; line 548 : if( state_led_cam == 0 ) + 1892 1892 $DGL 0,29 + 1893 1893 00357 RD50000 cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + 1894 1894 0035A DF08 bnz $?L0157 ;[INF] 2, 4 + 1895 1895 ; line 549 : { + 1896 1896 0035C ??bb02_tsk_led_cam: + 1897 1897 ; line 550 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + 1898 1898 $DGL 0,31 + 1899 1899 0035C RFD1400 call !bs_S0175 ;[INF] 3, 3 + 1900 1900 ; line 551 : state_led_cam = 1; + 1901 1901 $DGL 0,32 + 1902 1902 0035F RE50000 oneb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1903 1903 00362 ??eb02_tsk_led_cam: + 1904 1904 ; line 552 : } + 1905 1905 $DGL 0,33 + 1906 1906 00362 EF06 br $?L0158 ;[INF] 2, 3 + 1907 1907 00364 ?L0157: + 1908 1908 ; line 553 : else + 1909 1909 ; line 554 : { + 1910 1910 00364 ??bb03_tsk_led_cam: + 1911 1911 ; line 555 : LED_duty_CAM = 0; + 1912 1912 $DGL 0,36 + 1913 1913 00364 F6 clrw ax ;[INF] 1, 1 + 1914 1914 00365 BE64 movw TDR02,ax ;[INF] 2, 1 + 1915 1915 ; line 556 : state_led_cam = 0; + 1916 1916 $DGL 0,37 + 1917 1917 00367 RF50000 clrb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1918 1918 0036A ??eb03_tsk_led_cam: + 1919 1919 ; line 557 : } + 1920 1920 0036A ?L0158: + 1921 1921 ; line 558 : task_interval = 250; + 1922 1922 $DGL 0,39 + 1923 1923 0036A RCF1000FA mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 + 1924 1924 ; line 559 : break; + 1925 1925 $DGL 0,40 + 1926 1926 0036E D7 ret ;[INF] 1, 6 + 1927 1927 ; line 560 : + 1928 1928 ; line 561 : case ( CAM_LED_ON_PLUSE ): + 1929 1929 0036F ?L0152: + 1930 1930 ; line 562 : if( state_led_cam == 0 ) + 1931 1931 $DGL 0,43 + 1932 1932 0036F RD50000 cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + 1933 1933 00372 DF0B bnz $?L0159 ;[INF] 2, 4 + 1934 1934 ; line 563 : { + 1935 1935 00374 ??bb04_tsk_led_cam: + 1936 1936 ; line 564 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + 1937 1937 $DGL 0,45 + 1938 1938 00374 RFD1400 call !bs_S0175 ;[INF] 3, 3 + 1939 1939 ; line 565 : state_led_cam = 1; + 1940 1940 $DGL 0,46 + 1941 1941 00377 RE50000 oneb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1942 1942 ; line 566 : task_interval = 250; + 1943 1943 $DGL 0,47 + 1944 1944 0037A RCF1000FA mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 + 1945 1945 0037E ??eb04_tsk_led_cam: + 1946 1946 ; line 567 : } + 1947 1947 $DGL 0,48 + 1948 1948 0037E D7 ret ;[INF] 1, 6 + 1949 1949 0037F ?L0159: + 1950 1950 ; line 568 : else + 1951 1951 ; line 569 : { + 1952 1952 0037F ??bb05_tsk_led_cam: + 1953 1953 ; line 570 : vreg_ctr[VREG_C_LED_CAM] = CAM_LED_OFF; + 1954 1954 $DGL 0,51 + 1955 1955 0037F RF52B00 clrb !_vreg_ctr+43 ;[INF] 3, 1 + 1956 1956 00382 ??eb05_tsk_led_cam: + 1957 1957 ; line 571 : } + 1958 1958 ; line 572 : break; + 1959 1959 $DGL 0,53 + 1960 1960 00382 D7 ret ;[INF] 1, 6 + 1961 1961 ; line 573 : + 1962 1962 ; line 574 : case ( CAM_LED_OFF_PLUSE ): + 1963 1963 00383 ?L0153: + 1964 1964 ; line 575 : if( state_led_cam == 0 ) + 1965 1965 $DGL 0,56 + 1966 1966 00383 RD50000 cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + 1967 1967 00386 DF0B bnz $?L0161 ;[INF] 2, 4 + 1968 1968 ; line 576 : { + 1969 1969 00388 ??bb06_tsk_led_cam: + 1970 1970 ; line 577 : LED_duty_CAM = 0; + 1971 1971 $DGL 0,58 + 1972 1972 00388 F6 clrw ax ;[INF] 1, 1 + 1973 1973 00389 BE64 movw TDR02,ax ;[INF] 2, 1 + 1974 1974 ; line 578 : state_led_cam = 1; + 1975 1975 $DGL 0,59 + 1976 1976 0038B RE50000 oneb !?L0142 ; state_led_cam ;[INF] 3, 1 + 1977 1977 ; line 579 : task_interval = 250; + 1978 1978 $DGL 0,60 + 1979 1979 0038E RCF1000FA mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 + 1980 1980 00392 ??eb06_tsk_led_cam: + 1981 1981 ; line 580 : } + 1982 1982 $DGL 0,61 + 1983 1983 00392 D7 ret ;[INF] 1, 6 + 1984 1984 00393 ?L0161: + 1985 1985 ; line 581 : else + 1986 1986 ; line 582 : { + 1987 1987 00393 ??bb07_tsk_led_cam: + 1988 1988 ; line 583 : vreg_ctr[VREG_C_LED_CAM] = CAM_LED_ON; + 1989 1989 $DGL 0,64 + 1990 1990 00393 RCF2B0002 mov !_vreg_ctr+43,#02H ; 2 ;[INF] 4, 1 + 1991 1991 00397 ??eb07_tsk_led_cam: + 1992 1992 ; line 584 : } + 1993 1993 ; line 585 : break; + 1994 1994 $DGL 0,66 + 1995 1995 00397 D7 ret ;[INF] 1, 6 + 1996 1996 ; line 586 : + 1997 1997 ; line 587 : case ( CAM_LED_BY_TWL ): + 1998 1998 00398 ?L0154: + 1999 1999 ; line 588 : switch ( vreg_twl[ REG_TWL_INT_ADRS_CAM ] ){ // switchの + 2000 2000 ; ネストとか… + 2001 2001 $DGL 0,69 + 2002 2002 00398 RD90500 mov x,!_vreg_twl+5 ;[INF] 3, 1 + 2003 2003 0039B RFD0000 call !bs_S0172 ;[INF] 3, 3 + 2004 2004 0039E DD09 bz $?L0164 ;[INF] 2, 4 + 2005 2005 003A0 23 subw ax,bc ;[INF] 1, 1 + 2006 2006 003A1 DD25 bz $?L0166 ;[INF] 2, 4 + 2007 2007 003A3 23 subw ax,bc ;[INF] 1, 1 + 2008 2008 003A4 DD0A bz $?L0165 ;[INF] 2, 4 + 2009 2009 003A6 23 subw ax,bc ;[INF] 1, 1 + 2010 2010 003A7 EF1F br $?L0166 ;[INF] 2, 3 + 2011 2011 003A9 ??bb08_tsk_led_cam: + 2012 2012 ; line 589 : case( TWL_CAMLED_OFF ): + 2013 2013 003A9 ?L0164: + 2014 2014 ; line 590 : LED_duty_CAM = 0; + 2015 2015 $DGL 0,71 + 2016 2016 003A9 F6 clrw ax ;[INF] 1, 1 + 2017 2017 003AA BE64 movw TDR02,ax ;[INF] 2, 1 + 2018 2018 ; line 591 : state_led_cam = 0; + 2019 2019 $DGL 0,72 + 2020 2020 003AC RF50000 clrb !?L0142 ; state_led_cam ;[INF] 3, 1 + 2021 2021 ; line 592 : break; + 2022 2022 $DGL 0,73 + 2023 2023 003AF D7 ret ;[INF] 1, 6 + 2024 2024 ; line 593 : + 2025 2025 ; line 594 : case( TWL_CAMLED_BLINK ): + 2026 2026 003B0 ?L0165: + 2027 2027 ; line 595 : if( state_led_cam == 0 ) + 2028 2028 $DGL 0,76 + 2029 2029 003B0 RD50000 cmp0 !?L0142 ; state_led_cam ;[INF] 3, 1 + 2030 2030 003B3 DF08 bnz $?L0170 ;[INF] 2, 4 + 2031 2031 ; line 596 : { + 2032 2032 003B5 ??bb09_tsk_led_cam: + 2033 2033 ; line 597 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + 2034 2034 $DGL 0,78 + 2035 2035 003B5 RFD1400 call !bs_S0175 ;[INF] 3, 3 + 2036 2036 ; line 598 : state_led_cam = 1; + 2037 2037 $DGL 0,79 + 2038 2038 003B8 RE50000 oneb !?L0142 ; state_led_cam ;[INF] 3, 1 + 2039 2039 003BB ??eb09_tsk_led_cam: + 2040 2040 ; line 599 : } + 2041 2041 $DGL 0,80 + 2042 2042 003BB EF06 br $?L0171 ;[INF] 2, 3 + 2043 2043 003BD ?L0170: + 2044 2044 ; line 600 : else + 2045 2045 ; line 601 : { + 2046 2046 003BD ??bb0A_tsk_led_cam: + 2047 2047 ; line 602 : LED_duty_CAM = 0; + 2048 2048 $DGL 0,83 + 2049 2049 003BD F6 clrw ax ;[INF] 1, 1 + 2050 2050 003BE BE64 movw TDR02,ax ;[INF] 2, 1 + 2051 2051 ; line 603 : state_led_cam = 0; + 2052 2052 $DGL 0,84 + 2053 2053 003C0 RF50000 clrb !?L0142 ; state_led_cam ;[INF] 3, 1 + 2054 2054 003C3 ??eb0A_tsk_led_cam: + 2055 2055 ; line 604 : } + 2056 2056 003C3 ?L0171: + 2057 2057 ; line 605 : task_interval = 250; + 2058 2058 $DGL 0,86 + 2059 2059 003C3 RCF1000FA mov !?L0143,#0FAH ; task_interval,250 ;[INF] 4, 1 + 2060 2060 ; line 606 : break; + 2061 2061 $DGL 0,87 + 2062 2062 003C7 D7 ret ;[INF] 1, 6 + 2063 2063 ; line 607 : + 2064 2064 ; line 608 : case( TWL_CAMLED_ON ): + 2065 2065 003C8 ?L0166: + 2066 2066 ; line 609 : case( TWL_CAMLED_DEF_ON ): + 2067 2067 ; line 610 : default: + 2068 2068 ; line 611 : LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT]; + 2069 2069 $DGL 0,92 + 2070 2070 003C8 RFD1400 call !bs_S0175 ;[INF] 3, 3 + 2071 2071 ; line 612 : state_led_cam = 1; + 2072 2072 $DGL 0,93 + 2073 2073 003CB RE50000 oneb !?L0142 ; state_led_cam ;[INF] 3, 1 + 2074 2074 ; line 613 : break; + 2075 2075 003CE ??eb08_tsk_led_cam: + 2076 2076 ; line 614 : } + 2077 2077 003CE ?L0163: + 2078 2078 003CE ??eb01_tsk_led_cam: + 2079 2079 ; line 615 : } + 2080 2080 ; line 616 : return; + 2081 2081 ; line 617 : } + 2082 2082 $DGL 0,98 + 2083 2083 003CE ??ef_tsk_led_cam: + 2084 2084 003CE D7 ret ;[INF] 1, 6 + 2085 2085 003CF ??ee_tsk_led_cam: + 2086 2086 + 2087 2087 ----- @@CODEL CSEG + 2088 2088 + 2089 2089 ----- @@BASE CSEG BASE + 2090 2090 END + 2091 2091 + 2092 2092 + 2093 2093 ; *** Code Information *** + 2094 2094 ; + 2095 2095 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c + 2096 2096 ; + 2097 2097 ; $FUNC LED_init(40) + 2098 2098 ; void=(void) + 2099 2099 ; CODE SIZE= 83 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 0 bytes + 2100 2100 ; + 2101 2101 ; $FUNC LED_stop(87) + 2102 2102 ; void=(void) + 2103 2103 ; CODE SIZE= 15 bytes, CLOCK_SIZE= 12 clocks, STACK_SIZE= 0 bytes + 2104 2104 ; + 2105 2105 ; $FUNC tsk_led_pow(120) + 2106 2106 ; void=(void) + 2107 2107 ; CODE SIZE= 99 bytes, CLOCK_SIZE= 133 clocks, STACK_SIZE= 4 bytes + 2108 2108 ; + 2109 2109 ; $CALL led_pow_hotaru(128) + 2110 2110 ; void=(void) + 2111 2111 ; + 2112 2112 ; $CALL led_pow_normal(132) + 2113 2113 ; void=(void) + 2114 2114 ; + 2115 2115 ; $CALL led_pow_hotaru(147) + 2116 2116 ; void=(void) + 2117 2117 ; + 2118 2118 ; $CALL led_pow_normal(152) + 2119 2119 ; void=(void) + 2120 2120 ; + 2121 2121 ; $FUNC led_pow_normal(174) + 2122 2122 ; void=(void) + 2123 2123 ; CODE SIZE= 113 bytes, CLOCK_SIZE= 104 clocks, STACK_SIZE= 0 bytes + 2124 2124 ; + 2125 2125 ; $FUNC led_pow_hotaru(229) + 2126 2126 ; void=(void) + 2127 2127 ; CODE SIZE= 149 bytes, CLOCK_SIZE= 126 clocks, STACK_SIZE= 0 bytes + 2128 2128 ; + 2129 2129 ; $FUNC tsk_led_wifi(316) + 2130 2130 ; void=(void) + 2131 2131 ; CODE SIZE= 123 bytes, CLOCK_SIZE= 159 clocks, STACK_SIZE= 4 bytes + 2132 2132 ; + 2133 2133 ; $FUNC tsk_led_notify(401) + 2134 2134 ; void=(void) + 2135 2135 ; CODE SIZE= 200 bytes, CLOCK_SIZE= 208 clocks, STACK_SIZE= 6 bytes + 2136 2136 ; + 2137 2137 ; $FUNC tsk_led_cam(520) + 2138 2138 ; void=(void) + 2139 2139 ; CODE SIZE= 166 bytes, CLOCK_SIZE= 258 clocks, STACK_SIZE= 4 bytes + 2140 2140 + 2141 2141 ; Target chip : uPD79F0104 + 2142 2142 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00034H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00012H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 003CFH ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/led.rel b/branches/0.10(X3)/led.rel new file mode 100644 index 0000000..6b82911 Binary files /dev/null and b/branches/0.10(X3)/led.rel differ diff --git a/branches/0.10(X3)/loader.c b/branches/0.10(X3)/loader.c new file mode 100644 index 0000000..7ec6e79 --- /dev/null +++ b/branches/0.10(X3)/loader.c @@ -0,0 +1,396 @@ +/* ======================================================== + MCU CTR BSR + 2009/03/30 + 開発技術部 藤田 + + ブートローダー部 + ホストの通信と、自己書き換え、ファームのチェックを行う。 + + ======================================================== */ +#pragma SFR +#pragma di +#pragma ei +#pragma nop +#pragma stop +#pragma halt +#pragma opc + + +#include "incs_loader.h" + +#include "fsl.h" +#include "fsl_user.h" + +#include "i2c_ctr.h" +#include "i2c_mcu.h" +#include "pm.h" +#include "rtc.h" + +#include "reboot.h" + + +// ======================================================== +#if (FSL_DATA_BUFFER_SIZE>0) +fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE]; +#endif + + + +#ifdef FSL_INT_BACKUP +static fsl_u08 fsl_MK0L_bak_u08; /* if (interrupt backup required) */ +static fsl_u08 fsl_MK0H_bak_u08; /* { */ +static fsl_u08 fsl_MK1L_bak_u08; /* reserve space for backup information */ +static fsl_u08 fsl_MK1H_bak_u08; /* of interrupt mask flags */ +static fsl_u08 fsl_MK2L_bak_u08; /* */ +static fsl_u08 fsl_MK2H_bak_u08; /* } */ +#endif + + + +// magic.c の記述と違わないように注意！ +#define MGC_LOAD 0x0FF6 +#define MGC_FOOT 0x4FF6 + + + +// ======================================================== +void FSL_Open( void ); +void FSL_Close( void ); +void hdwinit( void ); +void power_save( ); +static void hdwinit2( ); + +extern void main_loop( ); + + + +// ======================================================== +void main( ) +{ + while( 1 ) + { + WDT_Restart( ); + if( RTCEN ) + { + system_status.reboot = 1; + } + else if( ( RESF & 0x10 ) != 0) // WDRF,WDTでリセット + { + system_status.reboot = 1; +#ifdef _PMIC_TWL_ + // 暴走してしまうので再起動させる + PM_reset_ast(); + /// hdwinit2ないでリセット解除される。続きに続行してよい（頭痛が痛い的） +#endif + vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_RESET; + // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); + // ↑I2Cの初期化後に行う + hdwinit2( ); + } + else + { + u8 pwup_delay0 = 0; + u8 pwup_delay1 = 0; + + do + { // 電池接続時、16ms待ってみる(チャタリング対策) + pwup_delay0 += 1; + do + { + pwup_delay1 += 1; + } + while( pwup_delay1 != 0 ); // u16にするとコンパイラが怒るんだが…。 + } + while( pwup_delay0 != 0 ); + + hdwinit2( ); + } + + // ファームの整合性チェック // + { + u8 i; + u8 comp = 0; + + // ローダーと本体は同じバージョンか？ + /// 次へのアップデートの途中で終わってないか？ + for( i = 0; i < sizeof( __TIME__ ); i++ ) // sizeof( __TIME__ ) = 8 らし + { + comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( u8 * )( MGC_FOOT + i ) ) ? 0 : 1; + } + + if( comp != 0 ) + { + // ファームリストアを試みる + firm_restore( ); + // 帰ってこない。リセットをかける。 + } + } + + // 通常運転 + main_loop( ); + } +} + + + +/* ======================================================== + キーリターン割り込み + ======================================================== */ +__interrupt void int_kr( ) +{ +} + + + +/* ======================================================== + ext dc + ======================================================== */ +__interrupt void intp4( ) +{ +} + + +/* ======================================================== + shell close + ======================================================== */ +__interrupt void intp5( ) +{ +} + + + +// ======================================================== +void hdwinit( void ) +{ // スタートアップルーチンが勝手に呼びます + DI( ); /* マスタ割り込み禁止 */ + + CMC = 0b00010110; /* X1発振せず(入力ポート)、XT1使用、推奨の推奨で超低電力発振 */ + CSC = 0b10000000; /* X1発振なし、XT1発振あり、高速内蔵発振動作 */ +#ifdef _MCU_BSR_ + OSMC = 0x01; /* 隠しレジスタ */ +#endif +#ifdef _OVERCLOCK_ + CKC = 0b00001000; /* CPU/周辺クロック=fMAIN、fMAIN=fMX、fCLK=fMX */ +#else + // CKC デフォルトでよい +#endif + + /*--- 低電圧検出回路の設定 ---*/ + /* リセット解除時のデフォルトは、オプション・バイトにて指定される */ + LVIS = 0b00000000; /* VLVI = 4.22±0.1V */ + LVIM = 0b00000000; /* LVI動作禁止 */ + /* 電源電圧(VDD)＜検出電圧(VLVI)時に割込発生 */ + /* 電源電圧(VDD)≧検出電圧0) + 250 250 ; line 34 : fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE]; + 251 251 ; line 35 : #endif + 252 252 ; line 36 : + 253 253 ; line 37 : + 254 254 ; line 38 : + 255 255 ; line 39 : #ifdef FSL_INT_BACKUP + 256 256 ; line 40 : static fsl_u08 fsl_MK0L_bak_u08; /* if (interrupt back + 257 257 ; up required) */ + 258 258 ; line 41 : static fsl_u08 fsl_MK0H_bak_u08; /* { + 259 259 ; */ + 260 260 ; line 42 : static fsl_u08 fsl_MK1L_bak_u08; /* reserve space fo + 261 261 ; r backup information */ + 262 262 ; line 43 : static fsl_u08 fsl_MK1H_bak_u08; /* of interrupt mas + 263 263 ; k flags */ + 264 264 ; line 44 : static fsl_u08 fsl_MK2L_bak_u08; /* + 265 265 ; */ + 266 266 ; line 45 : static fsl_u08 fsl_MK2H_bak_u08; /* } + 267 267 ; */ + 268 268 ; line 46 : #endif + 269 269 ; line 47 : + 270 270 ; line 48 : + 271 271 ; line 49 : + 272 272 ; line 50 : // magic.c の記述と違わないように注意！ + 273 273 ; line 51 : #define MGC_LOAD 0x0FF6 + 274 274 ; line 52 : #define MGC_FOOT 0x4FF6 + 275 275 ; line 53 : + 276 276 ; line 54 : + 277 277 ; line 55 : + 278 278 ; line 56 : // ======================================================== + 279 279 ; line 57 : void FSL_Open( void ); + 280 280 ; line 58 : void FSL_Close( void ); + 281 281 ; line 59 : void hdwinit( void ); + 282 282 ; line 60 : void power_save( ); + 283 283 ; line 61 : static void hdwinit2( ); + 284 284 ; line 62 : + 285 285 ; line 63 : extern void main_loop( ); + 286 286 ; line 64 : + 287 287 ; line 65 : + 288 288 ; line 66 : + 289 289 ; line 67 : // ======================================================== + 290 290 ; line 68 : void main( ) + 291 291 ; line 69 : { + 292 292 + 293 293 ----- LDR_CODE CSEG BASE + 294 294 00000 _main: + 295 295 $DGL 1,65 + 296 296 00000 C7 push hl ;[INF] 1, 1 + 297 297 00001 ??bf_main: + 298 298 ; line 70 : while( 1 ) + 299 299 00001 ?L0003: + 300 300 ; line 71 : { + 301 301 00001 ??bb00_main: + 302 302 ; line 72 : WDT_Restart( ); + 303 303 $DGL 0,4 + 304 304 00001 RFD0000 call !_WDT_Restart ;[INF] 3, 3 + 305 305 ; line 73 : if( RTCEN ) + 306 306 $DGL 0,5 + 307 307 00004 C7 push hl ;[INF] 1, 1 + 308 308 00005 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1 + 309 309 00008 71F4 mov1 CY,[hl].7 ;[INF] 2, 1 + 310 310 0000A C6 pop hl ;[INF] 1, 1 + 311 311 0000B DE06 bnc $?L0005 ;[INF] 2, 4 + 312 312 ; line 74 : { + 313 313 0000D ??bb01_main: + 314 314 ; line 75 : system_status.reboot = 1; + 315 315 $DGL 0,7 + 316 316 0000D R71300200 set1 !_system_status+2.3 ;[INF] 4, 2 + 317 317 00011 ??eb01_main: + 318 318 ; line 76 : } + 319 319 $DGL 0,8 + 320 320 00011 EF25 br $?L0008 ;[INF] 2, 3 + 321 321 00013 ?L0005: + 322 322 ; line 77 : else if( ( RESF & 0x10 ) != 0) // WDRF,WDTでリセット + 323 323 $DGL 0,9 + 324 324 00013 5110 mov a,#010H ; 16 ;[INF] 2, 1 + 325 325 00015 5FA8FF and a,!RESF ;[INF] 3, 1 + 326 326 00018 D1 cmp0 a ;[INF] 1, 1 + 327 327 00019 DD0D bz $?L0007 ;[INF] 2, 4 + 328 328 ; line 78 : { + 329 329 0001B ??bb02_main: + 330 330 ; line 79 : system_status.reboot = 1; + 331 331 $DGL 0,11 + 332 332 0001B R71300200 set1 !_system_status+2.3 ;[INF] 4, 2 + 333 333 ; line 80 : #ifdef _PMIC_TWL_ + 334 334 ; line 81 : // 暴走してしまうので再起動させる + 335 335 ; line 82 : PM_reset_ast(); + 336 336 ; line 83 : /// hdwinit2ないでリセット解除される。続きに続行して + 337 337 ; よい（頭痛が痛い的） + 338 338 ; line 84 : #endif + 339 339 ; line 85 : vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_ + 340 340 ; RESET; + 341 341 $DGL 0,17 + 342 342 0001F R71100200 set1 !_vreg_ctr+2.1 ;[INF] 4, 2 + 343 343 ; line 86 : // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); + 344 344 ; line 87 : // ↑I2Cの初期化後に行う + 345 345 ; line 88 : hdwinit2( ); + 346 346 $DGL 0,20 + 347 347 00023 RFD8700 call !_hdwinit2 ;[INF] 3, 3 + 348 348 00026 ??eb02_main: + 349 349 ; line 89 : } + 350 350 $DGL 0,21 + 351 351 00026 EF10 br $?L0008 ;[INF] 2, 3 + 352 352 00028 ?L0007: + 353 353 ; line 90 : else + 354 354 ; line 91 : { + 355 355 00028 ??bb03_main: + 356 356 ; line 92 : u8 pwup_delay0 = 0; + 357 357 $DGL 0,24 + 358 358 00028 360000 movw hl,#00H ; 0 ;[INF] 3, 1 + 359 359 ; line 93 : u8 pwup_delay1 = 0; + 360 360 ; line 94 : + 361 361 ; line 95 : do + 362 362 0002B ?L0009: + 363 363 ; line 96 : { // 電池接続時、16ms待ってみる(チ + 364 364 ; ャタリング対策) + 365 365 0002B ??bb04_main: + 366 366 ; line 97 : pwup_delay0 += 1; + 367 367 $DGL 0,29 + 368 368 0002B 86 inc l ;[INF] 1, 1 + 369 369 ; line 98 : do + 370 370 0002C ?L0012: + 371 371 ; line 99 : { + 372 372 0002C ??bb05_main: + 373 373 ; line 100 : pwup_delay1 += 1; + 374 374 $DGL 0,32 + 375 375 0002C 87 inc h ;[INF] 1, 1 + 376 376 0002D ??eb05_main: + 377 377 ; line 101 : } + 378 378 ; line 102 : while( pwup_delay1 != 0 ); // u16にするとコ + 379 379 ; ンパイラが怒るんだが…。 + 380 380 $DGL 0,34 + 381 381 0002D 67 mov a,h ;[INF] 1, 1 + 382 382 0002E D1 cmp0 a ;[INF] 1, 1 + 383 383 0002F DFFB bnz $?L0012 ;[INF] 2, 4 + 384 384 00031 ??eb04_main: + 385 385 ; line 103 : } + 386 386 ; line 104 : while( pwup_delay0 != 0 ); + 387 387 $DGL 0,36 + 388 388 00031 66 mov a,l ;[INF] 1, 1 + 389 389 00032 D1 cmp0 a ;[INF] 1, 1 + 390 390 00033 DFF6 bnz $?L0009 ;[INF] 2, 4 + 391 391 ; line 105 : + 392 392 ; line 106 : hdwinit2( ); + 393 393 $DGL 0,38 + 394 394 00035 RFD8700 call !_hdwinit2 ;[INF] 3, 3 + 395 395 00038 ??eb03_main: + 396 396 ; line 107 : } + 397 397 00038 ?L0008: + 398 398 ; line 108 : + 399 399 ; line 109 : // ファームの整合性チェック // + 400 400 ; line 110 : { + 401 401 00038 ??bb06_main: + 402 402 ; line 111 : u8 i; + 403 403 ; line 112 : u8 comp = 0; + 404 404 $DGL 0,44 + 405 405 00038 360000 movw hl,#00H ; 0 ;[INF] 3, 1 + 406 406 ; line 113 : + 407 407 ; line 114 : // ローダーと本体は同じバージョンか？ + 408 408 ; line 115 : /// 次へのアップデートの途中で終わってないか？ + 409 409 ; line 116 : for( i = 0; i < sizeof( __TIME__ ); i++ ) // si + 410 410 ; zeof( __TIME__ ) = 8 らし + 411 411 $DGL 0,48 + 412 412 0003B ?L0015: + 413 413 0003B 66 mov a,l ;[INF] 1, 1 + 414 414 0003C 4C09 cmp a,#09H ; 9 ;[INF] 2, 1 + 415 415 0003E DE23 bnc $?L0016 ;[INF] 2, 4 + 416 416 ; line 117 : { + 417 417 00040 ??bb07_main: + 418 418 ; line 118 : comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( + 419 419 ; u8 * )( MGC_FOOT + i ) ) ? 0 : 1; + 420 420 $DGL 0,50 + 421 421 00040 17 movw ax,hl ;[INF] 1, 1 + 422 422 00041 F1 clrb a ;[INF] 1, 1 + 423 423 00042 04F60F addw ax,#0FF6H ; 4086 ;[INF] 3, 1 + 424 424 00045 C1 push ax ;[INF] 1, 1 + 425 425 00046 317B sar a,7 ;[INF] 2, 1 + 426 426 00048 9EFD mov ES,a ;[INF] 2, 1 + 427 427 0004A C4 pop de ;[INF] 1, 1 + 428 428 0004B 1189 mov a,ES:[de] ;[INF] 2, 2 + 429 429 0004D 72 mov c,a ;[INF] 1, 1 + 430 430 0004E 17 movw ax,hl ;[INF] 1, 1 + 431 431 0004F F1 clrb a ;[INF] 1, 1 + 432 432 00050 04F64F addw ax,#04FF6H ; 20470 ;[INF] 3, 1 + 433 433 00053 14 movw de,ax ;[INF] 1, 1 + 434 434 00054 89 mov a,[de] ;[INF] 1, 1 + 435 435 00055 6142 cmp c,a ;[INF] 2, 1 + 436 436 00057 DF03 bnz $?L0018 ;[INF] 2, 4 + 437 437 00059 F6 clrw ax ;[INF] 1, 1 + 438 438 0005A EF01 br $?L0019 ;[INF] 2, 3 + 439 439 0005C ?L0018: + 440 440 0005C E6 onew ax ;[INF] 1, 1 + 441 441 0005D ?L0019: + 442 442 0005D 60 mov a,x ;[INF] 1, 1 + 443 443 0005E 6107 add h,a ;[INF] 2, 1 + 444 444 00060 ??eb07_main: + 445 445 ; line 119 : } + 446 446 $DGL 0,51 + 447 447 00060 86 inc l ;[INF] 1, 1 + 448 448 00061 EFD8 br $?L0015 ;[INF] 2, 3 + 449 449 00063 ?L0016: + 450 450 ; line 120 : + 451 451 ; line 121 : if( comp != 0 ) + 452 452 $DGL 0,53 + 453 453 00063 67 mov a,h ;[INF] 1, 1 + 454 454 00064 D1 cmp0 a ;[INF] 1, 1 + 455 455 00065 61E8 skz ;[INF] 2, 1 + 456 456 ; line 122 : { + 457 457 00067 ??bb08_main: + 458 458 ; line 123 : // ファームリストアを試みる + 459 459 ; line 124 : firm_restore( ); + 460 460 $DGL 0,56 + 461 461 00067 RFD0000 call !_firm_restore ;[INF] 3, 3 + 462 462 0006A ??eb08_main: + 463 463 ; line 125 : // 帰ってこない。リセットをかける。 + 464 464 ; line 126 : } + 465 465 0006A ?L0020: + 466 466 0006A ??eb06_main: + 467 467 ; line 127 : } + 468 468 ; line 128 : + 469 469 ; line 129 : // 通常運転 + 470 470 ; line 130 : main_loop( ); + 471 471 $DGL 0,62 + 472 472 0006A RFD0000 call !_main_loop ;[INF] 3, 3 + 473 473 0006D ??eb00_main: + 474 474 ; line 131 : } + 475 475 $DGL 0,63 + 476 476 0006D EF92 br $?L0003 ;[INF] 2, 3 + 477 477 ; line 132 : } + 478 478 $DGL 0,64 + 479 479 0006F ??ef_main: + 480 480 0006F C6 pop hl ;[INF] 1, 1 + 481 481 00070 D7 ret ;[INF] 1, 6 + 482 482 00071 ??ee_main: + 483 483 ; line 133 : + 484 484 ; line 134 : + 485 485 ; line 135 : + 486 486 ; line 136 : /* ======================================================== + 487 487 ; line 137 : キーリターン割り込み + 488 488 ; line 138 : ======================================================== */ + 489 489 ; line 139 : __interrupt void int_kr( ) + 490 490 ; line 140 : { + 491 491 + 492 492 ----- @@BASE CSEG BASE + 493 493 00000 _int_kr: + 494 494 $DGL 1,115 + 495 495 00000 ??bf_int_kr: + 496 496 ; line 141 : } + 497 497 $DGL 0,2 + 498 498 00000 ??ef_int_kr: + 499 499 00000 61FC reti ;[INF] 2, 6 + 500 500 00002 ??ee_int_kr: + 501 501 ; line 142 : + 502 502 ; line 143 : + 503 503 ; line 144 : + 504 504 ; line 145 : /* ======================================================== + 505 505 ; line 146 : ext dc + 506 506 ; line 147 : ======================================================== */ + 507 507 ; line 148 : __interrupt void intp4( ) + 508 508 ; line 149 : { + 509 509 00002 _intp4: + 510 510 $DGL 1,121 + 511 511 00002 ??bf_intp4: + 512 512 ; line 150 : } + 513 513 $DGL 0,2 + 514 514 00002 ??ef_intp4: + 515 515 00002 61FC reti ;[INF] 2, 6 + 516 516 00004 ??ee_intp4: + 517 517 ; line 151 : + 518 518 ; line 152 : + 519 519 ; line 153 : /* ======================================================== + 520 520 ; line 154 : shell close + 521 521 ; line 155 : ======================================================== */ + 522 522 ; line 156 : __interrupt void intp5( ) + 523 523 ; line 157 : { + 524 524 00004 _intp5: + 525 525 $DGL 1,127 + 526 526 00004 ??bf_intp5: + 527 527 ; line 158 : } + 528 528 $DGL 0,2 + 529 529 00004 ??ef_intp5: + 530 530 00004 61FC reti ;[INF] 2, 6 + 531 531 00006 ??ee_intp5: + 532 532 ; line 159 : + 533 533 ; line 160 : + 534 534 ; line 161 : + 535 535 ; line 162 : // ======================================================== + 536 536 ; line 163 : void hdwinit( void ) + 537 537 ; line 164 : { // スタートアップルーチンが勝手に + 538 538 ; 呼びます + 539 539 + 540 540 ----- LDR_CODE CSEG BASE + 541 541 00071 _hdwinit: + 542 542 $DGL 1,133 + 543 543 00071 717BFA di ;[INF] 3, 4 + 544 544 00074 ??bf_hdwinit: + 545 545 ; line 165 : DI( ); /* マスタ割り込み禁止 */ + 546 546 ; line 166 : + 547 547 ; line 167 : CMC = 0b00010110; /* X1発振せず(入力ポート)、XT1使用 + 548 548 ; 、推奨の推奨で超低電力発振 */ + 549 549 $DGL 0,4 + 550 550 00074 CEA016 mov CMC,#016H ; 22 ;[INF] 3, 1 + 551 551 ; line 168 : CSC = 0b10000000; /* X1発振なし、XT1発振あり、高速内 + 552 552 ; 蔵発振動作 */ + 553 553 $DGL 0,5 + 554 554 00077 CEA180 mov CSC,#080H ; 128 ;[INF] 3, 1 + 555 555 ; line 169 : #ifdef _MCU_BSR_ + 556 556 ; line 170 : OSMC = 0x01; /* 隠しレジスタ */ + 557 557 $DGL 0,7 + 558 558 0007A E5F300 oneb !OSMC ;[INF] 3, 1 + 559 559 ; line 171 : #endif + 560 560 ; line 172 : #ifdef _OVERCLOCK_ + 561 561 ; line 173 : CKC = 0b00001000; /* CPU/周辺クロック=fMAIN、fMAIN= + 562 562 ; fMX、fCLK=fMX */ + 563 563 $DGL 0,10 + 564 564 0007D CEA408 mov CKC,#08H ; 8 ;[INF] 3, 1 + 565 565 ; line 174 : #else + 566 566 ; line 175 : // CKC デフォルトでよい + 567 567 ; line 176 : #endif + 568 568 ; line 177 : + 569 569 ; line 178 : /*--- 低電圧検出回路の設定 ---*/ + 570 570 ; line 179 : /* リセット解除時のデフォルトは、オプション・バイトにて指定さ + 571 571 ; れる */ + 572 572 ; line 180 : LVIS = 0b00000000; /* VLVI = 4.22±0.1V */ + 573 573 $DGL 0,17 + 574 574 00080 F5AAFF clrb !LVIS ;[INF] 3, 1 + 575 575 ; line 181 : LVIM = 0b00000000; /* LVI動作禁止 */ + 576 576 $DGL 0,18 + 577 577 00083 F5A9FF clrb !LVIM ;[INF] 3, 1 + 578 578 ; line 182 : /* 電源電圧(VDD)＜検出電圧(VLVI)時に割込発生 */ + 579 579 ; line 183 : /* 電源電圧(VDD)≧検出電圧 tempA[0][1], "offset" => tempA[0][2], "type" => tempA[0][3], "data" => tempA[0][4], "CRC" => tempA[0][5] } + + break if src_in["type"].hex == 01 + break if src_in["len"].hex == 00 + # next if src_in["type"].hex != 00 + if( src_in["type"].hex != 00 ) +# p dat + next + end + + offset = src_in["offset"].hex + next if(( 0x1000 <= offset ) && ( offset < 0x2000 )) + + dataTemp = src_in["data"].scan(/\w\w/) + + ( 0...(src_in["len"].to_s.hex) ).each{|i| + bindata[ offset + i ] = ( dataTemp[ i ] ).to_s.hex + } +end + +### format data and output ############# +4096.times{ + bindata.delete_at(4096) +} +dest.write( bindata[0..(0x4FFF - 0x1000)].pack("c*") ) +dest.close + +printf( "intel-HEX to bsr bin converter\n file converted!\n\n" ) diff --git a/branches/0.10(X3)/pedo_alg_thre_det2.c b/branches/0.10(X3)/pedo_alg_thre_det2.c new file mode 100644 index 0000000..44d64cf --- /dev/null +++ b/branches/0.10(X3)/pedo_alg_thre_det2.c @@ -0,0 +1,411 @@ +/* ******************************************************** + + + + +********************************************************* */ +#pragma MUL +#pragma BCD + +#include "incs.h" +#include + +#include "accero.h" +#include "pedometer.h" + + +static void hosu_increment(); +u16 get_long_hour(); + + + +extern u16 pool[]; + + + +/*========================================================= +　歩数計 + ========================================================*/ +void pedometer() +{ + static s16 th_H = 15000; // 閾値。暫定。動的変更とかしたい…ので変数 + static s16 th_L = 11000; + static u16 acc_norm[3]; // 加速度の大きさのヒストリ。数字が大きい方が古い + static u16 acc_norm_temp; + static u8 interval_hh; // 山-山間の時間。短過ぎたらはじく。 + static u8 time_l; // 前回の極小からの経過時間 + static u16 peak_l; // 谷の深さ + static u16 peak_h; // 山の高さ + static u16 norm_hist[TAP]; + + static u8 hist_indx; + static u8 t_rise; + + signed long filterd; + + u8 i; + + signed long temp1,temp2,temp3; + signed long temp4,temp5,temp6; + + u16 sx16 = abs( (u16)vreg_ctr[VREG_C_ACC_XH] * 256 + vreg_ctr[VREG_C_ACC_XL] ); + u16 sy16 = abs( (u16)vreg_ctr[VREG_C_ACC_YH] * 256 + vreg_ctr[VREG_C_ACC_YL] ); + u16 sz16 = abs( (u16)vreg_ctr[VREG_C_ACC_ZH] * 256 + vreg_ctr[VREG_C_ACC_ZL] ); + + // ベクトルのノルム +#ifdef _mcu_ + norm_hist[ hist_indx & TAP-1 ] = sqrt( (long)sx16 * ( sx16 / 2 ) + + (long)sy16 * ( sy16 / 2 ) + + (long)sz16 * ( sz16 / 2 ) + ); +#endif + +#ifdef _pc_ + norm_hist[ hist_indx & TAP-1 ] = normh * 256 + norml; +#endif + + hist_indx += 1; + + // ヒストリにフィルタを掛けて、今回の値を求める + filterd = 0; +// for( i = 8; i != 55; i++ ) // 係数が０ばかりのため + for( i = 0; i != 46; i++ ) // 係数テーブルをいじりました。パラメータ調整時注意 + { + filterd += (signed long)norm_hist[ ( hist_indx + i ) & TAP-1 ] * lpf_coeff[ i ]; + } + + filterd += (4096)*512; + acc_norm_temp = (s16)( filterd /1024 & 0xFFFF ); // ←FIL_COEFF_QUANTから正規化 +/* + if( acc_norm[0] < acc_norm_temp ) + { + t_rise += 1; + if( t_rise == 0 ) + t_rise == 254; + } + else + { + t_rise = 0; + } +*/ + if( acc_norm[0] != acc_norm_temp ) + { + acc_norm[2] = acc_norm[1]; // ヒストリ + acc_norm[1] = acc_norm[0]; + acc_norm[0] = acc_norm_temp; + } + + if( acc_norm[2] <= acc_norm[1] && acc_norm[1] > acc_norm[0] + && acc_norm[0] > th_H ) + // 極大で、閾値を超えていた + { + if( 21 < interval_hh ) + // 前回の極大からの間隔がほどよい + { + if(( interval_hh < 160 ) && ( time_l < interval_hh )) + // 谷を挟んでいる + { + if( acc_norm[0] - peak_l > 4200 ){ + // 一歩増えました + hosu_increment(); + } + } + interval_hh = 0; + } + if( acc_norm[0] > 18000 ) + { + th_L = acc_norm[0] - 10000; + } + else + { + th_L = 11000; + } + } + else + { + interval_hh += ( interval_hh != 255 ) ? 1: 0; // 飽和加算って楽に書けたらいいのに + } + + // (2) 直近の極小からの時間 + if( acc_norm[2] >= acc_norm[1] && acc_norm[1] < acc_norm[0] + && acc_norm[0] < th_L ) + { + // 極小を検出 + time_l = 0; + peak_l = acc_norm[0]; + } + else + { + time_l += ( time_l != 255 ) ? 1: 0; + } + + { +/* +static u8 i = 0; + + vreg_ctr[VREG_C_FREE_0] = i++; + + vreg_ctr[VREG_C_FREE_1] = (u8)( acc_norm[0] / 256 & 0x00FF ); + vreg_ctr[VREG_C_FREE_2] = (u8)( acc_norm[0] & 0x00FF ); + + vreg_ctr[VREG_C_FREE_3] = (u8)( norm_hist[ hist_indx -1 & TAP-1 ] / 256 & 0xFF ); + vreg_ctr[VREG_C_FREE_4] = (u8)( norm_hist[ hist_indx -1 & TAP-1 ] & 0xFF ); + + vreg_ctr[VREG_C_FREE_5] = interval_hh; + vreg_ctr[VREG_C_FREE_6] = time_l; + + vreg_ctr[VREG_C_FREE_7] = vreg_ctr[ VREG_C_ACC_HOSU_L ]; + vreg_ctr[VREG_C_FREE_8] = (u8)( peak_l / 256 & 0x00FF ); + vreg_ctr[VREG_C_FREE_9] = (u8)( peak_l & 0x00FF ); +// vreg_ctr[VREG_C_FREE_A] = (u8)( norm_avg[0] / 256 & 0x00FF ); + // vreg_ctr[VREG_C_FREE_B] = (u8)( norm_avg[0] & 0x00FF ); +*/ + } +} + + + +/*========================================================= +　歩数＋１ +　　累積をインクリメント + 　履歴を更新 + ========================================================*/ +u8 p_record; +u8 last_hour = 0x23; // 履歴の最新は何時？ +u8 last_day = 0x30; +u8 last_month = 0x12; +u8 last_year = 0x99; + +#define HOSU_NODATA 0xFFFF +#define HOSU_MAX 0xFFFE + +static void hosu_increment() +{ + static u16 last_hour_fny; + + // 累積の更新 // + // いろいろ失敗した... + if( ++vreg_ctr[ VREG_C_ACC_HOSU_L ] == 0 ) + { + if( ++vreg_ctr[ VREG_C_ACC_HOSU_M ] == 0 ) + { + if( ++vreg_ctr[ VREG_C_ACC_HOSU_H ] == 0 ){ + vreg_ctr[ VREG_C_ACC_HOSU_L ] = 255; // カンスト orz + vreg_ctr[ VREG_C_ACC_HOSU_M ] = 255; + vreg_ctr[ VREG_C_ACC_HOSU_H ] = 255; + } + } + } + + { + // 毎時履歴の更新 ///////////////////////////// + // 空白の時間を考慮する。１時間以上放置されたなど。 + u16 now_hour; + u8 now_year; + + // 時計を止める必要が有るので↓は一気に行って下さい + DI(); + RWAIT = 1; + while( !RWST ){;} + now_year = bcdtob( YEAR ); + last_hour = HOUR; // 履歴読み出し時に使用。BCDのままでよい + last_day = DAY; + last_month = MONTH; + now_hour = get_long_hour(); + // RWAIT = 0; ↑で行っています + // EI(); 〃 + + // 歩数計が止まっていた時間を考慮して必要なら進める // + if( last_year == now_year ) + { + if( now_hour > last_hour_fny ) + { + fill_hosu_hist_hours( now_hour - last_hour_fny ); + } + } + else if( last_year == ( now_year -1 ) ) + { + // 年をまたいでいるとき + u16 temp_hours = ( ( 365 + (( now_year & 0x03 ) == 1 ? 1: 0 )) * 24 ) - last_hour_fny + now_hour; + fill_hosu_hist_hours( temp_hours ); + } + else if( last_year < now_year ) + { + // 数年放置 + fill_hosu_hist_hours( 0 ); + } + else + { + // カレンダーが巻き戻るなど + // ノーケアでよい + } + last_year = now_year; + last_hour_fny = now_hour; + + // 実際にインクリメント + if( pool[ p_record ] == HOSU_NODATA ) + { + pool[ p_record ] = 1; + } + else if( pool[ p_record ] != HOSU_MAX ) + { + pool[ p_record ] += 1; + } + } +} + + + +/* ======================================================== +空白の時間を適切に0にして、 +今を含む１時間のデータを書く位置にポインタ？を進める +======================================================== */ +void fill_hosu_hist_hours( u16 hours ) +{ + if( hours > 255 ) + { + hours = 0; + } + + // 空白の数時間の設定 + do + { + p_record += 1; + pool[ p_record ] = 0; + hours -= 1; + } + while( hours != 0 ); +} + + + +/* ======================================================== +空白の時間を適切に0にして、 +今を含む１時間のデータを書く位置にポインタ？を進める +======================================================== */ +void clear_hosu_hist() +{ + u8 hours = 0; + // 空白の数時間の設定 + do + { + pool[ hours ] = 0xFFFF; + hours -= 1; + } + while( hours != 0 ); + vreg_ctr[ VREG_C_ACC_HOSU_L ] = 0; + vreg_ctr[ VREG_C_ACC_HOSU_M ] = 0; + vreg_ctr[ VREG_C_ACC_HOSU_H ] = 0; +} + + +extern u8 iic_burst_state; +bit record_read_msb_lsb; + +/* ======================================================== + 歩数計ヒストリ読み出しの後処理(初期化) + 読み出しポインタのクリア +======================================================== */ +void hosu_read_end( ) +{ + record_read_msb_lsb = 0; +} + + +/* ======================================================== + 歩数計のヒストリを返す。 + １回呼ぶ度に、ヒストリの下位、上位、一時間遡って下位上位... +======================================================== */ +u8 hosu_read( ) +{ + u8 dat; + u16 temp; + static u8 p_record_buffer; + + switch( iic_burst_state ){ + case( 0 ): + p_record_buffer = p_record; + iic_burst_state += 1; + return( last_hour ); + + case( 1 ): + iic_burst_state += 1; + return( last_day ); + + case( 2 ): + iic_burst_state += 1; + return( last_month ); + + case( 3 ): + iic_burst_state += 1; + return( btobcd(last_year) ); + + case( 4 ): + iic_burst_state += 1; + return( 0x55 ); // reserved dummy + + case( 5 ): + iic_burst_state += 1; + return( 0xAA ); // reserved. dummy + + default: + temp = pool[ p_record_buffer ]; + if( record_read_msb_lsb == 0 ) + { + dat = (u8)( temp & 0x00FF ); + } + else + { + dat = (u8)(( temp >> 8 ) & 0x00FF ); + p_record_buffer -= 1; + } + record_read_msb_lsb += 1; + return( dat ); + } +} + + + +/* ======================================================== + 今年の元旦からの経過時間(hour)を返す。 + 引数 無し + 返値 u16 long_hour +======================================================== */ +static const u16 DAYS_FROM_HNY[] = { + 0, + 0, 31, 31+28, 59+31, 90+30, + 120+31, 151+30, 181+31, 212+31, 243+30, + 273+31, 304+30 }; + +u16 get_long_hour() +{ + u16 long_hour; + u8 year_hex; + u8 month_hex; + u8 day_hex; + u8 hour_hex; + + year_hex = bcdtob( YEAR ); + month_hex = bcdtob( MONTH ); + day_hex = bcdtob( DAY ); + hour_hex = bcdtob( HOUR ); + + RWAIT = 0; + EI(); + + // まず日数の部分 + long_hour = DAYS_FROM_HNY[ month_hex ]; + if(( ( year_hex & 0x03 ) == 0 ) && ( ( 3 <= month_hex ) + || (( 2 == month_hex ) && ( day_hex == 29 )) )) + { + // 閏年で、閏日より後 + long_hour += 1; + } + long_hour += day_hex - 1; + long_hour *= 24; // 日数→時間 + + long_hour += hour_hex; + + return( long_hour ); +} + diff --git a/branches/0.10(X3)/pedo_alg_thre_det2.prn b/branches/0.10(X3)/pedo_alg_thre_det2.prn new file mode 100644 index 0000000..ced1369 --- /dev/null +++ b/branches/0.10(X3)/pedo_alg_thre_det2.prn @@ -0,0 +1,1754 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\pedo_alg_thre_det2.asm +Para-file: +In-file: inter_asm\pedo_alg_thre_det2.asm +Obj-file: pedo_alg_thre_det2.rel +Prn-file: pedo_alg_thre_det2.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no pedo_alg_thre_de + 6 6 ; t2.c + 7 7 ; In-file : pedo_alg_thre_det2.c + 8 8 ; Asm-file : inter_asm\pedo_alg_thre_det2.asm + 9 9 ; Para-file : + 10 10 + 11 11 $PROCESSOR(9F0104) + 12 12 $DEBUG + 13 13 $NODEBUGA + 14 14 $KANJICODE SJIS + 15 15 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 16 16 + 17 17 $DGS FIL_NAM, .file, 0EEH, 0FFFEH, 03FH, 067H, 01H, 00H + 18 18 $DGS AUX_FIL, pedo_alg_thre_det2.c + 19 19 $DGS MOD_NAM, pedo_alg_thre_det2, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 20 20 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 36 36 $DGS LAB_SYM, bs_S0099, U, U, 00H, 06H, 00H, 00H + 37 37 $DGS LAB_SYM, es_S0099, U, U, 00H, 06H, 00H, 00H + 38 38 $DGS LAB_SYM, bs_F0097, U, U, 00H, 06H, 00H, 00H + 39 39 $DGS LAB_SYM, es_F0097, U, U, 00H, 06H, 00H, 00H + 40 40 $DGS LAB_SYM, bs_S0098, U, U, 00H, 06H, 00H, 00H + 41 41 $DGS LAB_SYM, es_S0098, U, U, 00H, 06H, 00H, 00H + 42 42 $DGS LAB_SYM, bs_S0096, U, U, 00H, 06H, 00H, 00H + 43 43 $DGS LAB_SYM, es_S0096, U, U, 00H, 06H, 00H, 00H + 44 44 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 45 45 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 46 46 $DGS GLV_SYM, _pedometer, U, U, 01H, 026H, 01H, 02H + 47 47 $DGS AUX_FUN, 00H, U, U, 06BH, 00H, 00H + 48 48 $DGS BEG_FUN, ??bf_pedometer, U, U, 00H, 065H, 01H, 00H + 49 49 $DGS AUX_BEG, 01EH, 024H, 039H + 50 50 $DGS STA_SYM, _th_H, ?L0003, U, 03H, 03H, 00H, 00H + 51 51 $DGS STA_SYM, _th_L, ?L0004, U, 03H, 03H, 00H, 00H + 52 52 $DGS STA_SYM, _acc_norm, ?L0005, U, 0DH, 03H, 01H, 03H + 53 53 $DGS AUX_STR, 00H, 00H, 06H, 03H, 00H, 00H, 00H, 00H + 54 54 $DGS STA_SYM, _acc_norm_temp, ?L0006, U, 0DH, 03H, 00H, 00H + 55 55 $DGS STA_SYM, _interval_hh, ?L0007, U, 0CH, 03H, 00H, 00H + 56 56 $DGS STA_SYM, _time_l, ?L0008, U, 0CH, 03H, 00H, 00H + 57 57 $DGS STA_SYM, _peak_l, ?L0009, U, 0DH, 03H, 00H, 00H + 58 58 $DGS STA_SYM, _peak_h, ?L0010, U, 0DH, 03H, 00H, 00H + 59 59 $DGS STA_SYM, _norm_hist, ?L0011, U, 0DH, 03H, 01H, 03H + 60 60 $DGS AUX_STR, 00H, 00H, 080H, 040H, 00H, 00H, 00H, 00H + 61 61 $DGS STA_SYM, _hist_indx, ?L0012, U, 0CH, 03H, 00H, 00H + 62 62 $DGS STA_SYM, _t_rise, ?L0013, U, 0CH, 03H, 00H, 00H + 63 63 $DGS AUT_VAR, _filterd, 020H, 0FFFFH, 05H, 01H, 00H, 00H + 64 64 $DGS AUT_VAR, _i, 01FH, 0FFFFH, 0CH, 01H, 00H, 00H + 65 65 $DGS AUT_VAR, _temp1, 01AH, 0FFFFH, 05H, 01H, 00H, 00H + 66 66 $DGS AUT_VAR, _temp2, 016H, 0FFFFH, 05H, 01H, 00H, 00H + 67 67 $DGS AUT_VAR, _temp3, 012H, 0FFFFH, 05H, 01H, 00H, 00H + 68 68 $DGS AUT_VAR, _temp4, 0EH, 0FFFFH, 05H, 01H, 00H, 00H + 69 69 $DGS AUT_VAR, _temp5, 0AH, 0FFFFH, 05H, 01H, 00H, 00H + 70 70 $DGS AUT_VAR, _temp6, 06H, 0FFFFH, 05H, 01H, 00H, 00H + 71 71 $DGS AUT_VAR, _sx16, 04H, 0FFFFH, 0DH, 01H, 00H, 00H + 72 72 $DGS AUT_VAR, _sy16, 02H, 0FFFFH, 0DH, 01H, 00H, 00H + 73 73 $DGS AUT_VAR, _sz16, 00H, 0FFFFH, 0DH, 01H, 00H, 00H + 74 74 $DGS BEG_BLK, ??bb00_pedometer, U, U, 00H, 064H, 01H, 00H + 75 75 $DGS AUX_BEG, 02CH, 00H, 03DH + 76 76 $DGS END_BLK, ??eb00_pedometer, U, U, 00H, 064H, 01H, 00H + 77 77 $DGS AUX_END, 02EH + 78 78 $DGS BEG_BLK, ??bb01_pedometer, U, U, 00H, 064H, 01H, 00H + 79 79 $DGS AUX_BEG, 03FH, 00H, 041H + 80 80 $DGS END_BLK, ??eb01_pedometer, U, U, 00H, 064H, 01H, 00H + 81 81 $DGS AUX_END, 043H + 82 82 $DGS BEG_BLK, ??bb02_pedometer, U, U, 00H, 064H, 01H, 00H + 83 83 $DGS AUX_BEG, 048H, 00H, 043H + 84 84 $DGS BEG_BLK, ??bb03_pedometer, U, U, 00H, 064H, 01H, 00H + 85 85 $DGS AUX_BEG, 04BH, 00H, 045H + 86 86 $DGS BEG_BLK, ??bb04_pedometer, U, U, 00H, 064H, 01H, 00H + 87 87 $DGS AUX_BEG, 04EH, 00H, 047H + 88 88 $DGS BEG_BLK, ??bb05_pedometer, U, U, 00H, 064H, 01H, 00H + 89 89 $DGS AUX_BEG, 04FH, 00H, 04FH + 90 90 $DGS END_BLK, ??eb05_pedometer, U, U, 00H, 064H, 01H, 00H + 91 91 $DGS AUX_END, 052H + 92 92 $DGS END_BLK, ??eb04_pedometer, U, U, 00H, 064H, 01H, 00H + 93 93 $DGS AUX_END, 053H + 94 94 $DGS END_BLK, ??eb03_pedometer, U, U, 00H, 064H, 01H, 00H + 95 95 $DGS AUX_END, 055H + 96 96 $DGS BEG_BLK, ??bb06_pedometer, U, U, 00H, 064H, 01H, 00H + 97 97 $DGS AUX_BEG, 057H, 00H, 053H + 98 98 $DGS END_BLK, ??eb06_pedometer, U, U, 00H, 064H, 01H, 00H + 99 99 $DGS AUX_END, 059H + 100 100 $DGS BEG_BLK, ??bb07_pedometer, U, U, 00H, 064H, 01H, 00H + 101 101 $DGS AUX_BEG, 05BH, 00H, 059H + 102 102 $DGS END_BLK, ??eb07_pedometer, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_END, 05DH + 104 104 $DGS END_BLK, ??eb02_pedometer, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_END, 05EH + 106 106 $DGS BEG_BLK, ??bb08_pedometer, U, U, 00H, 064H, 01H, 00H + 107 107 $DGS AUX_BEG, 060H, 00H, 05DH + 108 108 $DGS END_BLK, ??eb08_pedometer, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_END, 062H + 110 110 $DGS BEG_BLK, ??bb09_pedometer, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_BEG, 067H, 00H, 061H + 112 112 $DGS END_BLK, ??eb09_pedometer, U, U, 00H, 064H, 01H, 00H + 113 113 $DGS AUX_END, 06BH + 114 114 $DGS BEG_BLK, ??bb0A_pedometer, U, U, 00H, 064H, 01H, 00H + 115 115 $DGS AUX_BEG, 06DH, 00H, 065H + 116 116 $DGS END_BLK, ??eb0A_pedometer, U, U, 00H, 064H, 01H, 00H + 117 117 $DGS AUX_END, 06FH + 118 118 $DGS BEG_BLK, ??bb0B_pedometer, U, U, 00H, 064H, 01H, 00H + 119 119 $DGS AUX_BEG, 071H, 00H, 00H + 120 120 $DGS END_BLK, ??eb0B_pedometer, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_END, 086H + 122 122 $DGS END_FUN, ??ef_pedometer, U, U, 00H, 065H, 01H, 00H + 123 123 $DGS AUX_END, 087H + 124 124 $DGS STA_SYM, _hosu_increment, U, U, 01H, 03H, 01H, 02H + 125 125 $DGS AUX_FUN, 00H, U, U, 0A8H, 00H, 00H + 126 126 $DGS BEG_FUN, ??bf_hosu_increment, U, U, 00H, 065H, 01H, 00H + 127 127 $DGS AUX_BEG, 0B7H, 06H, 070H + 128 128 $DGS STA_SYM, _last_hour_fny, ?L0039, U, 0DH, 03H, 00H, 00H + 129 129 $DGS BEG_BLK, ??bb00_hosu_increment, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_BEG, 07H, 00H, 072H + 131 131 $DGS BEG_BLK, ??bb01_hosu_increment, U, U, 00H, 064H, 01H, 00H + 132 132 $DGS AUX_BEG, 09H, 00H, 074H + 133 133 $DGS BEG_BLK, ??bb02_hosu_increment, U, U, 00H, 064H, 01H, 00H + 134 134 $DGS AUX_BEG, 0AH, 00H, 07CH + 135 135 $DGS END_BLK, ??eb02_hosu_increment, U, U, 00H, 064H, 01H, 00H + 136 136 $DGS AUX_END, 0EH + 137 137 $DGS END_BLK, ??eb01_hosu_increment, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_END, 0FH + 139 139 $DGS END_BLK, ??eb00_hosu_increment, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_END, 010H + 141 141 $DGS BEG_BLK, ??bb03_hosu_increment, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_BEG, 012H, 00H, 082H + 143 143 $DGS AUT_VAR, _now_hour, 04H, 0FFFFH, 0DH, 01H, 01H, 00H + 144 144 $DGS AUX_STR, 00H, 015H, 02H, 00H, 00H, 00H, 00H, 00H + 145 145 $DGS AUT_VAR, _now_year, 03H, 0FFFFH, 0CH, 01H, 01H, 00H + 146 146 $DGS AUX_STR, 00H, 016H, 01H, 00H, 00H, 00H, 00H, 00H + 147 147 $DGS BEG_BLK, ??bb04_hosu_increment, U, U, 00H, 064H, 01H, 00H + 148 148 $DGS AUX_BEG, 01BH, 00H, 086H + 149 149 $DGS END_BLK, ??eb04_hosu_increment, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_END, 01BH + 151 151 $DGS BEG_BLK, ??bb05_hosu_increment, U, U, 00H, 064H, 01H, 00H + 152 152 $DGS AUX_BEG, 026H, 00H, 088H + 153 153 $DGS BEG_BLK, ??bb06_hosu_increment, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_BEG, 028H, 00H, 08EH + 155 155 $DGS END_BLK, ??eb06_hosu_increment, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_END, 02AH + 157 157 $DGS END_BLK, ??eb05_hosu_increment, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_END, 02BH + 159 159 $DGS BEG_BLK, ??bb07_hosu_increment, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_BEG, 02DH, 00H, 094H + 161 161 $DGS AUT_VAR, _temp_hours, 00H, 0FFFFH, 0DH, 01H, 01H, 00H + 162 162 $DGS AUX_STR, 00H, 02FH, 02H, 00H, 00H, 00H, 00H, 00H + 163 163 $DGS END_BLK, ??eb07_hosu_increment, U, U, 00H, 064H, 01H, 00H + 164 164 $DGS AUX_END, 031H + 165 165 $DGS BEG_BLK, ??bb08_hosu_increment, U, U, 00H, 064H, 01H, 00H + 166 166 $DGS AUX_BEG, 033H, 00H, 098H + 167 167 $DGS END_BLK, ??eb08_hosu_increment, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_END, 036H + 169 169 $DGS BEG_BLK, ??bb09_hosu_increment, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_BEG, 038H, 00H, 09CH + 171 171 $DGS END_BLK, ??eb09_hosu_increment, U, U, 00H, 064H, 01H, 00H + 172 172 $DGS AUX_END, 03BH + 173 173 $DGS BEG_BLK, ??bb0A_hosu_increment, U, U, 00H, 064H, 01H, 00H + 174 174 $DGS AUX_BEG, 041H, 00H, 0A0H + 175 175 $DGS END_BLK, ??eb0A_hosu_increment, U, U, 00H, 064H, 01H, 00H + 176 176 $DGS AUX_END, 043H + 177 177 $DGS BEG_BLK, ??bb0B_hosu_increment, U, U, 00H, 064H, 01H, 00H + 178 178 $DGS AUX_BEG, 045H, 00H, 00H + 179 179 $DGS END_BLK, ??eb0B_hosu_increment, U, U, 00H, 064H, 01H, 00H + 180 180 $DGS AUX_END, 047H + 181 181 $DGS END_BLK, ??eb03_hosu_increment, U, U, 00H, 064H, 01H, 00H + 182 182 $DGS AUX_END, 048H + 183 183 $DGS END_FUN, ??ef_hosu_increment, U, U, 00H, 065H, 01H, 00H + 184 184 $DGS AUX_END, 049H + 185 185 $DGS GLV_SYM, _fill_hosu_hist_hours, U, U, 01H, 026H, 01H, 02H + 186 186 $DGS AUX_FUN, 00H, U, U, 0B7H, 00H, 00H + 187 187 $DGS BEG_FUN, ??bf_fill_hosu_hist_hours, U, U, 00H, 065H, 01H, 00H + 188 188 $DGS AUX_BEG, 0108H, 02H, 0ADH + 189 189 $DGS REG_PAR, _hours, 0103H, 0FFFFH, 010DH, 011H, 00H, 00H + 190 190 $DGS BEG_BLK, ??bb00_fill_hosu_hist_hours, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_BEG, 03H, 00H, 0B1H + 192 192 $DGS END_BLK, ??eb00_fill_hosu_hist_hours, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_END, 05H + 194 194 $DGS BEG_BLK, ??bb01_fill_hosu_hist_hours, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_BEG, 09H, 00H, 00H + 196 196 $DGS END_BLK, ??eb01_fill_hosu_hist_hours, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_END, 0DH + 198 198 $DGS END_FUN, ??ef_fill_hosu_hist_hours, U, U, 00H, 065H, 01H, 00H + 199 199 $DGS AUX_END, 0FH + 200 200 $DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 026H, 01H, 02H + 201 201 $DGS AUX_FUN, 00H, U, U, 0C2H, 00H, 00H + 202 202 $DGS BEG_FUN, ??bf_clear_hosu_hist, U, U, 00H, 065H, 01H, 00H + 203 203 $DGS AUX_BEG, 011FH, 02H, 0BCH + 204 204 $DGS REG_VAR, _hours, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 205 205 $DGS BEG_BLK, ??bb00_clear_hosu_hist, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_BEG, 05H, 00H, 00H + 207 207 $DGS END_BLK, ??eb00_clear_hosu_hist, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_END, 08H + 209 209 $DGS END_FUN, ??ef_clear_hosu_hist, U, U, 00H, 065H, 01H, 00H + 210 210 $DGS AUX_END, 0DH + 211 211 $DGS GLV_SYM, _hosu_read_end, U, U, 01H, 026H, 01H, 02H + 212 212 $DGS AUX_FUN, 00H, U, U, 0C8H, 00H, 00H + 213 213 $DGS BEG_FUN, ??bf_hosu_read_end, U, U, 00H, 065H, 01H, 00H + 214 214 $DGS AUX_BEG, 0136H, 00H, 0C8H + 215 215 $DGS END_FUN, ??ef_hosu_read_end, U, U, 00H, 065H, 01H, 00H + 216 216 $DGS AUX_END, 03H + 217 217 $DGS GLV_SYM, _hosu_read, U, U, 0CH, 026H, 01H, 02H + 218 218 $DGS AUX_FUN, 00H, U, U, 0DDH, 00H, 00H + 219 219 $DGS BEG_FUN, ??bf_hosu_read, U, U, 00H, 065H, 01H, 00H + 220 220 $DGS AUX_BEG, 0140H, 04H, 0CFH + 221 221 $DGS AUT_VAR, _dat, 03H, 0FFFFH, 0CH, 01H, 00H, 00H + 222 222 $DGS AUT_VAR, _temp, 00H, 0FFFFH, 0DH, 01H, 00H, 00H + 223 223 $DGS STA_SYM, _p_record_buffer, ?L0078, U, 0CH, 03H, 00H, 00H + 224 224 $DGS BEG_BLK, ??bb00_hosu_read, U, U, 00H, 064H, 01H, 00H + 225 225 $DGS AUX_BEG, 06H, 00H, 0D1H + 226 226 $DGS BEG_BLK, ??bb01_hosu_read, U, U, 00H, 064H, 01H, 00H + 227 227 $DGS AUX_BEG, 023H, 00H, 0D5H + 228 228 $DGS END_BLK, ??eb01_hosu_read, U, U, 00H, 064H, 01H, 00H + 229 229 $DGS AUX_END, 025H + 230 230 $DGS BEG_BLK, ??bb02_hosu_read, U, U, 00H, 064H, 01H, 00H + 231 231 $DGS AUX_BEG, 027H, 00H, 00H + 232 232 $DGS END_BLK, ??eb02_hosu_read, U, U, 00H, 064H, 01H, 00H + 233 233 $DGS AUX_END, 02AH + 234 234 $DGS END_BLK, ??eb00_hosu_read, U, U, 00H, 064H, 01H, 00H + 235 235 $DGS AUX_END, 02DH + 236 236 $DGS END_FUN, ??ef_hosu_read, U, U, 00H, 065H, 01H, 00H + 237 237 $DGS AUX_END, 02EH + 238 238 $DGS STA_SYM, _DAYS_FROM_HNY, U, U, 0500DH, 03H, 01H, 03H + 239 239 $DGS AUX_STR, 00H, 00H, 01AH, 0DH, 00H, 00H, 00H, 00H + 240 240 $DGS GLV_SYM, _get_long_hour, U, U, 0DH, 026H, 01H, 02H + 241 241 $DGS AUX_FUN, 00H, U, U, 0EEH, 00H, 00H + 242 242 $DGS BEG_FUN, ??bf_get_long_hour, U, U, 00H, 065H, 01H, 00H + 243 243 $DGS AUX_BEG, 017DH, 06H, 0E8H + 244 244 $DGS AUT_VAR, _long_hour, 04H, 0FFFFH, 0DH, 01H, 00H, 00H + 245 245 $DGS AUT_VAR, _year_hex, 03H, 0FFFFH, 0CH, 01H, 00H, 00H + 246 246 $DGS AUT_VAR, _month_hex, 02H, 0FFFFH, 0CH, 01H, 00H, 00H + 247 247 $DGS AUT_VAR, _day_hex, 01H, 0FFFFH, 0CH, 01H, 00H, 00H + 248 248 $DGS AUT_VAR, _hour_hex, 00H, 0FFFFH, 0CH, 01H, 00H, 00H + 249 249 $DGS BEG_BLK, ??bb00_get_long_hour, U, U, 00H, 064H, 01H, 00H + 250 250 $DGS AUX_BEG, 014H, 00H, 00H + 251 251 $DGS END_BLK, ??eb00_get_long_hour, U, U, 00H, 064H, 01H, 00H + 252 252 $DGS AUX_END, 017H + 253 253 $DGS END_FUN, ??ef_get_long_hour, U, U, 00H, 065H, 01H, 00H + 254 254 $DGS AUX_END, 01EH + 255 255 $DGS GLV_SYM, _p_record, U, U, 0CH, 026H, 00H, 00H + 256 256 $DGS GLV_SYM, _last_hour, U, U, 0CH, 026H, 00H, 00H + 257 257 $DGS GLV_SYM, _last_day, U, U, 0CH, 026H, 00H, 00H + 258 258 $DGS GLV_SYM, _last_month, U, U, 0CH, 026H, 00H, 00H + 259 259 $DGS GLV_SYM, _last_year, U, U, 0CH, 026H, 00H, 00H + 260 260 $DGS GLV_SYM, _record_read_msb_lsb, U, U, 034CH, 027H, 00H, 00H + 261 261 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 262 262 $DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H + 263 263 $DGS GLV_SYM, _abs, U, U, 04H, 02H, 01H, 02H + 264 264 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 265 265 $DGS GLV_SYM, _@RTARG4, U, U, 00H, 02H, 00H, 00H + 266 266 $DGS GLV_SYM, _@RTARG6, U, U, 00H, 02H, 00H, 00H + 267 267 $DGS GLV_SYM, @@lsmul, U, U, 00H, 02H, 00H, 00H + 268 268 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 269 269 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 270 270 $DGS GLV_SYM, @@lsadd, U, U, 00H, 02H, 00H, 00H + 271 271 $DGS GLV_SYM, @@lstof, U, U, 00H, 02H, 00H, 00H + 272 272 $DGS GLV_SYM, _sqrt, U, U, 07H, 02H, 01H, 02H + 273 273 $DGS AUX_FUN, 00H, U, U, 00H, 01H, 00H + 274 274 $DGS GLV_SYM, _@RTARG3, U, U, 00H, 02H, 00H, 00H + 275 275 $DGS GLV_SYM, @@ftolu, U, U, 00H, 02H, 00H, 00H + 276 276 $DGS GLV_SYM, @@ftols, U, U, 00H, 02H, 00H, 00H + 277 277 $DGS GLV_SYM, @@lsdiv, U, U, 00H, 02H, 00H, 00H + 278 278 $DGS GLV_SYM, @@lsband, U, U, 00H, 02H, 00H, 00H + 279 279 $DGS GLV_SYM, @@bcdtob, U, U, 00H, 02H, 00H, 00H + 280 280 $DGS GLV_SYM, _pool, U, U, 0DH, 02H, 01H, 03H + 281 281 $DGS AUX_STR, 00H, 00H, 02H, 01H, 00H, 00H, 00H, 00H + 282 282 $DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 02H, 00H, 00H + 283 283 $DGS GLV_SYM, @@bbcd, U, U, 00H, 02H, 00H, 00H + 284 284 + 285 285 EXTRN _@RTARG0 + 286 286 EXTRN _@RTARG2 + 287 287 EXTRN _abs + 288 288 EXTRN _@RTARG4 + 289 289 EXTRN _@RTARG6 + 290 290 EXTRN @@lsmul + 291 291 EXTRN _vreg_ctr + 292 292 EXTRN @@lsadd + 293 293 EXTRN @@lstof + 294 294 EXTRN _sqrt + 295 295 EXTRN _@RTARG3 + 296 296 EXTRN @@ftolu + 297 297 EXTRN @@ftols + 298 298 EXTRN @@lsdiv + 299 299 EXTRN @@lsband + 300 300 EXTRN @@bcdtob + 301 301 EXTRN _pool + 302 302 EXTRN _iic_burst_state + 303 303 EXTRN @@bbcd + 304 304 PUBLIC _pedometer + 305 305 PUBLIC _p_record + 306 306 PUBLIC _last_hour + 307 307 PUBLIC _last_day + 308 308 PUBLIC _last_month + 309 309 PUBLIC _last_year + 310 310 PUBLIC _fill_hosu_hist_hours + 311 311 PUBLIC _clear_hosu_hist + 312 312 PUBLIC _record_read_msb_lsb + 313 313 PUBLIC _hosu_read_end + 314 314 PUBLIC _hosu_read + 315 315 PUBLIC _get_long_hour + 316 316 + 317 317 ----- @@BITS BSEG + 318 318 00000.0 _record_read_msb_lsb DBIT + 319 319 + 320 320 ----- @@CNST CSEG MIRRORP + 321 321 00000 01 _lpf_coeff: DB 01H ; 1 + 322 322 00001 02 DB 02H ; 2 + 323 323 00002 02 DB 02H ; 2 + 324 324 00003 03 DB 03H ; 3 + 325 325 00004 03 DB 03H ; 3 + 326 326 00005 02 DB 02H ; 2 + 327 327 00006 00 DB 00H ; 0 + 328 328 00007 FE DB 0FEH ; 254 + 329 329 00008 FB DB 0FBH ; 251 + 330 330 00009 F7 DB 0F7H ; 247 + 331 331 0000A F3 DB 0F3H ; 243 + 332 332 0000B F0 DB 0F0H ; 240 + 333 333 0000C F0 DB 0F0H ; 240 + 334 334 0000D F3 DB 0F3H ; 243 + 335 335 0000E FA DB 0FAH ; 250 + 336 336 0000F 04 DB 04H ; 4 + 337 337 00010 12 DB 012H ; 18 + 338 338 00011 25 DB 025H ; 37 + 339 339 00012 38 DB 038H ; 56 + 340 340 00013 4D DB 04DH ; 77 + 341 341 00014 5F DB 05FH ; 95 + 342 342 00015 6E DB 06EH ; 110 + 343 343 00016 77 DB 077H ; 119 + 344 344 00017 7A DB 07AH ; 122 + 345 345 00018 77 DB 077H ; 119 + 346 346 00019 6E DB 06EH ; 110 + 347 347 0001A 5F DB 05FH ; 95 + 348 348 0001B 4D DB 04DH ; 77 + 349 349 0001C 38 DB 038H ; 56 + 350 350 0001D 25 DB 025H ; 37 + 351 351 0001E 12 DB 012H ; 18 + 352 352 0001F 04 DB 04H ; 4 + 353 353 00020 FA DB 0FAH ; 250 + 354 354 00021 F3 DB 0F3H ; 243 + 355 355 00022 F0 DB 0F0H ; 240 + 356 356 00023 F0 DB 0F0H ; 240 + 357 357 00024 F3 DB 0F3H ; 243 + 358 358 00025 F7 DB 0F7H ; 247 + 359 359 00026 FB DB 0FBH ; 251 + 360 360 00027 FE DB 0FEH ; 254 + 361 361 00028 00 DB 00H ; 0 + 362 362 00029 02 DB 02H ; 2 + 363 363 0002A 03 DB 03H ; 3 + 364 364 0002B 03 DB 03H ; 3 + 365 365 0002C 02 DB 02H ; 2 + 366 366 0002D 02 DB 02H ; 2 + 367 367 0002E 01 DB 01H ; 1 + 368 368 0002F 00 DB (1) + 369 369 00030 0000 _DAYS_FROM_HNY: DW 00H ; 0 + 370 370 00032 0000 DW 00H ; 0 + 371 371 00034 1F00 DW 01FH ; 31 + 372 372 00036 3B00 DW 03BH ; 59 + 373 373 00038 5A00 DW 05AH ; 90 + 374 374 0003A 7800 DW 078H ; 120 + 375 375 0003C 9700 DW 097H ; 151 + 376 376 0003E B500 DW 0B5H ; 181 + 377 377 00040 D400 DW 0D4H ; 212 + 378 378 00042 F300 DW 0F3H ; 243 + 379 379 00044 1101 DW 0111H ; 273 + 380 380 00046 3001 DW 0130H ; 304 + 381 381 00048 4E01 DW 014EH ; 334 + 382 382 + 383 383 ----- @@R_INIT CSEG UNIT64KP + 384 384 00000 983A DW 03A98H ; 15000 + 385 385 00002 F82A DW 02AF8H ; 11000 + 386 386 00004 23 DB 023H ; 35 + 387 387 00005 30 DB 030H ; 48 + 388 388 00006 12 DB 012H ; 18 + 389 389 00007 99 DB 099H ; 153 + 390 390 + 391 391 ----- @@INIT DSEG BASEP + 392 392 00000 ?L0003: DS (2) + 393 393 00002 ?L0004: DS (2) + 394 394 00004 _last_hour: DS (1) + 395 395 00005 _last_day: DS (1) + 396 396 00006 _last_month: DS (1) + 397 397 00007 _last_year: DS (1) + 398 398 + 399 399 ----- @@DATA DSEG BASEP + 400 400 00000 ?L0005: DS (6) + 401 401 00006 ?L0006: DS (2) + 402 402 00008 ?L0007: DS (1) + 403 403 00009 ?L0008: DS (1) + 404 404 0000A ?L0009: DS (2) + 405 405 0000C ?L0010: DS (2) + 406 406 0000E ?L0011: DS (128) + 407 407 0008E ?L0012: DS (1) + 408 408 0008F ?L0013: DS (1) + 409 409 00090 _p_record: DS (1) + 410 410 00091 DS (1) + 411 411 00092 ?L0039: DS (2) + 412 412 00094 ?L0078: DS (1) + 413 413 00095 DS (1) + 414 414 + 415 415 ----- @@R_INIS CSEG UNIT64KP + 416 416 + 417 417 ----- @@INIS DSEG SADDRP + 418 418 + 419 419 ----- @@DATS DSEG SADDRP + 420 420 + 421 421 ----- @@CNSTL CSEG PAGE64KP + 422 422 + 423 423 ----- @@RLINIT CSEG UNIT64KP + 424 424 + 425 425 ----- @@INITL DSEG UNIT64KP + 426 426 + 427 427 ----- @@DATAL DSEG UNIT64KP + 428 428 + 429 429 ----- @@CALT CSEG CALLT0 + 430 430 + 431 431 ; Sub-Routines created by CC78K0R + 432 432 + 433 433 ----- ROM_CODE CSEG BASE + 434 434 00000 bs_S0099: + 435 435 00000 RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 436 436 00002 F6 clrw ax ;[INF] 1, 1 + 437 437 00003 RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 438 438 00005 D7 ret ;[INF] 1, 6 + 439 439 00006 es_S0099: + 440 440 + 441 441 ----- ROM_CODE CSEG BASE + 442 442 00006 bs_F0097: + 443 443 00006 F3 clrb b ;[INF] 1, 1 + 444 444 00007 03 addw ax,bc ;[INF] 1, 1 + 445 445 00008 RFD0000 call !_abs ;[INF] 3, 3 + 446 446 0000B 13 movw ax,bc ;[INF] 1, 1 + 447 447 0000C D7 ret ;[INF] 1, 6 + 448 448 0000D es_F0097: + 449 449 + 450 450 ----- ROM_CODE CSEG BASE + 451 451 0000D bs_S0098: + 452 452 0000D RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 453 453 0000F RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 454 454 00011 RAD00 movw ax,_@RTARG2 ;[INF] 2, 1 + 455 455 00013 RBD00 movw _@RTARG6,ax ;[INF] 2, 1 + 456 456 00015 D7 ret ;[INF] 1, 6 + 457 457 00016 es_S0098: + 458 458 + 459 459 ----- ROM_CODE CSEG BASE + 460 460 00016 bs_S0096: + 461 461 00016 RDA00 movw bc,_@RTARG6 ;[INF] 2, 1 + 462 462 00018 C3 push bc ;[INF] 1, 1 + 463 463 00019 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 464 464 0001B F6 clrw ax ;[INF] 1, 1 + 465 465 0001C RBD00 movw _@RTARG6,ax ;[INF] 2, 1 + 466 466 0001E RFD0000 call !@@lsmul ;[INF] 3, 3 + 467 467 00021 C0 pop ax ;[INF] 1, 1 + 468 468 00022 RBD00 movw _@RTARG6,ax ;[INF] 2, 1 + 469 469 00024 D7 ret ;[INF] 1, 6 + 470 470 00025 es_S0096: + 471 471 + 472 472 ; *** Sub-Routine Information *** + 473 473 ; + 474 474 ; $SUB bs_S0096 + 475 475 ; CODE SIZE= 15 bytes + 476 476 ; + 477 477 ; $SUB bs_F0097 + 478 478 ; CODE SIZE= 7 bytes + 479 479 ; + 480 480 ; $SUB bs_S0098 + 481 481 ; CODE SIZE= 9 bytes + 482 482 ; + 483 483 ; $SUB bs_S0099 + 484 484 ; CODE SIZE= 6 bytes + 485 485 + 486 486 ; End of Sub-Routines + 487 487 + 488 488 ; line 1 : /* ******************************************************** + 489 489 ; line 2 : + 490 490 ; line 3 : + 491 491 ; line 4 : + 492 492 ; line 5 : + 493 493 ; line 6 : ********************************************************* */ + 494 494 ; line 7 : #pragma MUL + 495 495 ; line 8 : #pragma BCD + 496 496 ; line 9 : + 497 497 ; line 10 : #include "incs.h" + 498 498 ; line 11 : #include + 499 499 ; line 12 : + 500 500 ; line 13 : #include "accero.h" + 501 501 ; line 14 : #include "pedometer.h" + 502 502 ; line 15 : + 503 503 ; line 16 : + 504 504 ; line 17 : static void hosu_increment(); + 505 505 ; line 18 : u16 get_long_hour(); + 506 506 ; line 19 : + 507 507 ; line 20 : + 508 508 ; line 21 : + 509 509 ; line 22 : extern u16 pool[]; + 510 510 ; line 23 : + 511 511 ; line 24 : + 512 512 ; line 25 : + 513 513 ; line 26 : /*========================================================= + 514 514 ; line 27 : 　歩数計 + 515 515 ; line 28 : ========================================================*/ + 516 516 ; line 29 : void pedometer() + 517 517 ; line 30 : { + 518 518 + 519 519 ----- ROM_CODE CSEG BASE + 520 520 00025 _pedometer: + 521 521 $DGL 1,29 + 522 522 00025 C7 push hl ;[INF] 1, 1 + 523 523 00026 2024 subw sp,#024H ;[INF] 2, 1 + 524 524 00028 FBF8FF movw hl,sp ;[INF] 3, 1 + 525 525 0002B ??bf_pedometer: + 526 526 ; line 31 : static s16 th_H = 15000; // 閾値。暫定。動的変更とかしたい… + 527 527 ; ので変数 + 528 528 ; line 32 : static s16 th_L = 11000; + 529 529 ; line 33 : static u16 acc_norm[3]; // 加速度の大きさのヒストリ。数字が大 + 530 530 ; きい方が古い + 531 531 ; line 34 : static u16 acc_norm_temp; + 532 532 ; line 35 : static u8 interval_hh; // 山-山間の時間。短過ぎたらはじく。 + 533 533 ; line 36 : static u8 time_l; // 前回の極小からの経過時間 + 534 534 ; line 37 : static u16 peak_l; // 谷の深さ + 535 535 ; line 38 : static u16 peak_h; // 山の高さ + 536 536 ; line 39 : static u16 norm_hist[TAP]; + 537 537 ; line 40 : + 538 538 ; line 41 : static u8 hist_indx; + 539 539 ; line 42 : static u8 t_rise; + 540 540 ; line 43 : + 541 541 ; line 44 : signed long filterd; + 542 542 ; line 45 : + 543 543 ; line 46 : u8 i; + 544 544 ; line 47 : + 545 545 ; line 48 : signed long temp1,temp2,temp3; + 546 546 ; line 49 : signed long temp4,temp5,temp6; + 547 547 ; line 50 : + 548 548 ; line 51 : u16 sx16 = abs( (u16)vreg_ctr[VREG_C_ACC_XH] * 256 + vreg_ct + 549 549 ; r[VREG_C_ACC_XL] ); + 550 550 $DGL 0,22 + 551 551 0002B R8F4600 mov a,!_vreg_ctr+70 ;[INF] 3, 1 + 552 552 0002E F0 clrb x ;[INF] 1, 1 + 553 553 0002F RF94500 mov c,!_vreg_ctr+69 ;[INF] 3, 1 + 554 554 00032 RFD0600 call !bs_F0097 ;[INF] 3, 3 + 555 555 00035 BC04 movw [hl+4],ax ; sx16 ;[INF] 2, 1 + 556 556 ; line 52 : u16 sy16 = abs( (u16)vreg_ctr[VREG_C_ACC_YH] * 256 + vreg_ct + 557 557 ; r[VREG_C_ACC_YL] ); + 558 558 $DGL 0,23 + 559 559 00037 R8F4800 mov a,!_vreg_ctr+72 ;[INF] 3, 1 + 560 560 0003A F0 clrb x ;[INF] 1, 1 + 561 561 0003B RF94700 mov c,!_vreg_ctr+71 ;[INF] 3, 1 + 562 562 0003E RFD0600 call !bs_F0097 ;[INF] 3, 3 + 563 563 00041 BC02 movw [hl+2],ax ; sy16 ;[INF] 2, 1 + 564 564 ; line 53 : u16 sz16 = abs( (u16)vreg_ctr[VREG_C_ACC_ZH] * 256 + vreg_ct + 565 565 ; r[VREG_C_ACC_ZL] ); + 566 566 $DGL 0,24 + 567 567 00043 R8F4A00 mov a,!_vreg_ctr+74 ;[INF] 3, 1 + 568 568 00046 F0 clrb x ;[INF] 1, 1 + 569 569 00047 RF94900 mov c,!_vreg_ctr+73 ;[INF] 3, 1 + 570 570 0004A RFD0600 call !bs_F0097 ;[INF] 3, 3 + 571 571 0004D BB movw [hl],ax ; sz16 ;[INF] 1, 1 + 572 572 ; line 54 : + 573 573 ; line 55 : // ベクトルのノルム + 574 574 ; line 56 : #ifdef _mcu_ + 575 575 ; line 57 : norm_hist[ hist_indx & TAP-1 ] = sqrt( (long)sx16 * ( sx16 / + 576 576 ; 2 ) + + 577 577 ; line 58 : (long)sy16 * ( sy16 / + 578 578 ; 2 ) + + 579 579 ; line 59 : (long)sz16 * ( sz16 / + 580 580 ; 2 ) + 581 581 ; line 60 : ); + 582 582 $DGL 0,31 + 583 583 0004E AC04 movw ax,[hl+4] ; sx16 ;[INF] 2, 1 + 584 584 00050 RFD0000 call !bs_S0099 ;[INF] 3, 3 + 585 585 00053 AC04 movw ax,[hl+4] ; sx16 ;[INF] 2, 1 + 586 586 00055 311E shrw ax,1 ;[INF] 2, 1 + 587 587 00057 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 588 588 00059 F6 clrw ax ;[INF] 1, 1 + 589 589 0005A RBD00 movw _@RTARG6,ax ;[INF] 2, 1 + 590 590 0005C RFD0000 call !@@lsmul ;[INF] 3, 3 + 591 591 0005F RFD0D00 call !bs_S0098 ;[INF] 3, 3 + 592 592 00062 AC02 movw ax,[hl+2] ; sy16 ;[INF] 2, 1 + 593 593 00064 RFD0000 call !bs_S0099 ;[INF] 3, 3 + 594 594 00067 AC02 movw ax,[hl+2] ; sy16 ;[INF] 2, 1 + 595 595 00069 311E shrw ax,1 ;[INF] 2, 1 + 596 596 0006B RDA00 movw bc,_@RTARG4 ;[INF] 2, 1 + 597 597 0006D C3 push bc ;[INF] 1, 1 + 598 598 0006E RFD1600 call !bs_S0096 ;[INF] 3, 3 + 599 599 00071 C0 pop ax ;[INF] 1, 1 + 600 600 00072 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 601 601 00074 RAD00 movw ax,_@RTARG6 ;[INF] 2, 1 + 602 602 00076 RFD0000 call !@@lsadd ;[INF] 3, 3 + 603 603 00079 RFD0D00 call !bs_S0098 ;[INF] 3, 3 + 604 604 0007C AB movw ax,[hl] ; sz16 ;[INF] 1, 1 + 605 605 0007D RFD0000 call !bs_S0099 ;[INF] 3, 3 + 606 606 00080 AB movw ax,[hl] ; sz16 ;[INF] 1, 1 + 607 607 00081 311E shrw ax,1 ;[INF] 2, 1 + 608 608 00083 RDA00 movw bc,_@RTARG4 ;[INF] 2, 1 + 609 609 00085 C3 push bc ;[INF] 1, 1 + 610 610 00086 RFD1600 call !bs_S0096 ;[INF] 3, 3 + 611 611 00089 C0 pop ax ;[INF] 1, 1 + 612 612 0008A RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 613 613 0008C RAD00 movw ax,_@RTARG6 ;[INF] 2, 1 + 614 614 0008E RFD0000 call !@@lsadd ;[INF] 3, 3 + 615 615 00091 RFD0000 call !@@lstof ;[INF] 3, 3 + 616 616 00094 RDA00 movw bc,_@RTARG2 ;[INF] 2, 1 + 617 617 00096 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 618 618 00098 RFC000000 call !!_sqrt ;[INF] 4, 3 + 619 619 0009C C3 push bc ;[INF] 1, 1 + 620 620 0009D C5 push de ;[INF] 1, 1 + 621 621 0009E R8F8E00 mov a,!?L0012 ; hist_indx ;[INF] 3, 1 + 622 622 000A1 5C3F and a,#03FH ; 63 ;[INF] 2, 1 + 623 623 000A3 F0 clrb x ;[INF] 1, 1 + 624 624 000A4 317E shrw ax,7 ;[INF] 2, 1 + 625 625 000A6 R040E00 addw ax,#loww (?L0011) ; norm_hist ;[INF] 3, 1 + 626 626 000A9 14 movw de,ax ;[INF] 1, 1 + 627 627 000AA C2 pop bc ;[INF] 1, 1 + 628 628 000AB C0 pop ax ;[INF] 1, 1 + 629 629 000AC RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 630 630 000AE 13 movw ax,bc ;[INF] 1, 1 + 631 631 000AF RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 632 632 000B1 R31720005 bt _@RTARG3.7,$?L0014 ;[INF] 4, 5 + 633 633 000B5 RFD0000 call !@@ftolu ;[INF] 3, 3 + 634 634 000B8 EF03 br $?L0015 ;[INF] 2, 3 + 635 635 000BA ?L0014: + 636 636 000BA RFD0000 call !@@ftols ;[INF] 3, 3 + 637 637 000BD ?L0015: + 638 638 000BD RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 639 639 000BF B9 movw [de],ax ;[INF] 1, 1 + 640 640 ; line 61 : #endif + 641 641 ; line 62 : + 642 642 ; line 63 : #ifdef _pc_ + 643 643 ; line 64 : norm_hist[ hist_indx & TAP-1 ] = normh * 256 + norml; + 644 644 ; line 65 : #endif + 645 645 ; line 66 : + 646 646 ; line 67 : hist_indx += 1; + 647 647 $DGL 0,38 + 648 648 000C0 RA08E00 inc !?L0012 ; hist_indx ;[INF] 3, 2 + 649 649 ; line 68 : + 650 650 ; line 69 : // ヒストリにフィルタを掛けて、今回の値を求める + 651 651 ; line 70 : filterd = 0; + 652 652 $DGL 0,41 + 653 653 000C3 F6 clrw ax ;[INF] 1, 1 + 654 654 000C4 BC20 movw [hl+32],ax ; filterd ;[INF] 2, 1 + 655 655 000C6 BC22 movw [hl+34],ax ; filterd ;[INF] 2, 1 + 656 656 ; line 71 : // for( i = 8; i != 55; i++ ) // 係数が０ばかりのため + 657 657 ; line 72 : for( i = 0; i != 46; i++ ) // 係数テーブルをいじりました。パ + 658 658 ; ラメータ調整時注意 + 659 659 $DGL 0,43 + 660 660 000C8 9C1F mov [hl+31],a ; i ;[INF] 2, 1 + 661 661 000CA ?L0016: + 662 662 000CA 8C1F mov a,[hl+31] ; i ;[INF] 2, 1 + 663 663 000CC 4C2E cmp a,#02EH ; 46 ;[INF] 2, 1 + 664 664 000CE DD3C bz $?L0017 ;[INF] 2, 4 + 665 665 ; line 73 : { + 666 666 000D0 ??bb00_pedometer: + 667 667 ; line 74 : filterd += (signed long)norm_hist[ ( hist_indx + i ) & T + 668 668 ; AP-1 ] * lpf_coeff[ i ]; + 669 669 $DGL 0,45 + 670 670 000D0 R8F8E00 mov a,!?L0012 ; hist_indx ;[INF] 3, 1 + 671 671 000D3 0E1F add a,[hl+31] ; i ;[INF] 2, 1 + 672 672 000D5 70 mov x,a ;[INF] 1, 1 + 673 673 000D6 F1 clrb a ;[INF] 1, 1 + 674 674 000D7 61DC rolc a,1 ;[INF] 2, 1 + 675 675 000D9 60 mov a,x ;[INF] 1, 1 + 676 676 000DA 5C3F and a,#03FH ; 63 ;[INF] 2, 1 + 677 677 000DC F0 clrb x ;[INF] 1, 1 + 678 678 000DD 317E shrw ax,7 ;[INF] 2, 1 + 679 679 000DF 12 movw bc,ax ;[INF] 1, 1 + 680 680 000E0 R790E00 movw ax,?L0011[bc] ; norm_hist ;[INF] 3, 1 + 681 681 000E3 RFD0000 call !bs_S0099 ;[INF] 3, 3 + 682 682 000E6 8C1F mov a,[hl+31] ; i ;[INF] 2, 1 + 683 683 000E8 73 mov b,a ;[INF] 1, 1 + 684 684 000E9 R090000 mov a,_lpf_coeff[b] ;[INF] 3, 1 + 685 685 000EC 318F sarw ax,8 ;[INF] 2, 1 + 686 686 000EE RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 687 687 000F0 70 mov x,a ;[INF] 1, 1 + 688 688 000F1 RBD00 movw _@RTARG6,ax ;[INF] 2, 1 + 689 689 000F3 RFD0000 call !@@lsmul ;[INF] 3, 3 + 690 690 000F6 AC20 movw ax,[hl+32] ; filterd ;[INF] 2, 1 + 691 691 000F8 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 692 692 000FA AC22 movw ax,[hl+34] ; filterd ;[INF] 2, 1 + 693 693 000FC RFD0000 call !@@lsadd ;[INF] 3, 3 + 694 694 000FF RAD00 movw ax,_@RTARG2 ;[INF] 2, 1 + 695 695 00101 BC22 movw [hl+34],ax ; filterd ;[INF] 2, 1 + 696 696 00103 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 697 697 00105 BC20 movw [hl+32],ax ; filterd ;[INF] 2, 1 + 698 698 00107 ??eb00_pedometer: + 699 699 ; line 75 : } + 700 700 $DGL 0,46 + 701 701 00107 61591F inc [hl+31] ; i ;[INF] 3, 2 + 702 702 0010A EFBE br $?L0016 ;[INF] 2, 3 + 703 703 0010C ?L0017: + 704 704 ; line 76 : + 705 705 ; line 77 : filterd += (4096)*512; + 706 706 ; line 78 : acc_norm_temp = (s16)( filterd /1024 & 0xFFFF ); // ←FIL_CO + 707 707 ; EFF_QUANTから正規化 + 708 708 $DGL 0,49 + 709 709 0010C AC20 movw ax,[hl+32] ; filterd ;[INF] 2, 1 + 710 710 0010E RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 711 711 00110 AC22 movw ax,[hl+34] ; filterd ;[INF] 2, 1 + 712 712 00112 RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 713 713 00114 RC9000004 movw _@RTARG4,#0400H ; 1024 ;[INF] 4, 1 + 714 714 00118 F6 clrw ax ;[INF] 1, 1 + 715 715 00119 RFD0000 call !@@lsdiv ;[INF] 3, 3 + 716 716 0011C RC900FFFF movw _@RTARG4,#0FFFFH ; -1 ;[INF] 4, 1 + 717 717 00120 F6 clrw ax ;[INF] 1, 1 + 718 718 00121 RFD0000 call !@@lsband ;[INF] 3, 3 + 719 719 00124 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 720 720 00126 RBF0600 movw !?L0006,ax ; acc_norm_temp ;[INF] 3, 1 + 721 721 ; line 79 : /* + 722 722 ; line 80 : if( acc_norm[0] < acc_norm_temp ) + 723 723 ; line 81 : { + 724 724 ; line 82 : t_rise += 1; + 725 725 ; line 83 : if( t_rise == 0 ) + 726 726 ; line 84 : t_rise == 254; + 727 727 ; line 85 : } + 728 728 ; line 86 : else + 729 729 ; line 87 : { + 730 730 ; line 88 : t_rise = 0; + 731 731 ; line 89 : } + 732 732 ; line 90 : */ + 733 733 ; line 91 : if( acc_norm[0] != acc_norm_temp ) + 734 734 $DGL 0,62 + 735 735 00129 RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 736 736 0012C R420600 cmpw ax,!?L0006 ; acc_norm_temp ;[INF] 3, 1 + 737 737 0012F DD12 bz $?L0019 ;[INF] 2, 4 + 738 738 ; line 92 : { + 739 739 00131 ??bb01_pedometer: + 740 740 ; line 93 : acc_norm[2] = acc_norm[1]; // ヒストリ + 741 741 $DGL 0,64 + 742 742 00131 RAF0200 movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + 743 743 00134 RBF0400 movw !?L0005+4,ax ; acc_norm ;[INF] 3, 1 + 744 744 ; line 94 : acc_norm[1] = acc_norm[0]; + 745 745 $DGL 0,65 + 746 746 00137 RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 747 747 0013A RBF0200 movw !?L0005+2,ax ; acc_norm ;[INF] 3, 1 + 748 748 ; line 95 : acc_norm[0] = acc_norm_temp; + 749 749 $DGL 0,66 + 750 750 0013D RAF0600 movw ax,!?L0006 ; acc_norm_temp ;[INF] 3, 1 + 751 751 00140 RBF0000 movw !?L0005,ax ; acc_norm ;[INF] 3, 1 + 752 752 00143 ??eb01_pedometer: + 753 753 ; line 96 : } + 754 754 00143 ?L0019: + 755 755 ; line 97 : + 756 756 ; line 98 : if( acc_norm[2] <= acc_norm[1] && acc_norm[1] > acc_norm[0] + 757 757 ; line 99 : && acc_norm[0] > th_H ) + 758 758 $DGL 0,70 + 759 759 00143 RAF0200 movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + 760 760 00146 R420400 cmpw ax,!?L0005+4 ; acc_norm ;[INF] 3, 1 + 761 761 00149 DC50 bc $?L0021 ;[INF] 2, 4 + 762 762 0014B RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 763 763 0014E R420200 cmpw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + 764 764 00151 DE48 bnc $?L0021 ;[INF] 2, 4 + 765 765 00153 RAF0000 movw ax,!?L0003 ; th_H ;[INF] 3, 1 + 766 766 00156 R420000 cmpw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 767 767 00159 DE40 bnc $?L0021 ;[INF] 2, 4 + 768 768 ; line 100 : // 極大で、閾値を超えていた + 769 769 ; line 101 : { + 770 770 0015B ??bb02_pedometer: + 771 771 ; line 102 : if( 21 < interval_hh ) + 772 772 $DGL 0,73 + 773 773 0015B R40080016 cmp !?L0007,#016H ; interval_hh,22 ;[INF] 4, 1 + 774 774 0015F DC1F bc $?L0023 ;[INF] 2, 4 + 775 775 ; line 103 : // 前回の極大からの間隔がほどよい + 776 776 ; line 104 : { + 777 777 00161 ??bb03_pedometer: + 778 778 ; line 105 : if(( interval_hh < 160 ) && ( time_l < interval_hh ) + 779 779 ; ) + 780 780 $DGL 0,76 + 781 781 00161 R400800A0 cmp !?L0007,#0A0H ; interval_hh,160 ;[INF] 4, 1 + 782 782 00165 DE16 bnc $?L0027 ;[INF] 2, 4 + 783 783 00167 R8F0900 mov a,!?L0008 ; time_l ;[INF] 3, 1 + 784 784 0016A R4F0800 cmp a,!?L0007 ; interval_hh ;[INF] 3, 1 + 785 785 0016D DE0E bnc $?L0027 ;[INF] 2, 4 + 786 786 ; line 106 : // 谷を挟んでいる + 787 787 ; line 107 : { + 788 788 0016F ??bb04_pedometer: + 789 789 ; line 108 : if( acc_norm[0] - peak_l > 4200 ){ + 790 790 $DGL 0,79 + 791 791 0016F RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 792 792 00172 R220A00 subw ax,!?L0009 ; peak_l ;[INF] 3, 1 + 793 793 00175 446910 cmpw ax,#01069H ; 4201 ;[INF] 3, 1 + 794 794 00178 61C8 skc ;[INF] 2, 1 + 795 795 0017A ??bb05_pedometer: + 796 796 ; line 109 : // 一歩増えました + 797 797 ; line 110 : hosu_increment(); + 798 798 $DGL 0,81 + 799 799 0017A RFDE401 call !_hosu_increment ;[INF] 3, 3 + 800 800 0017D ??eb05_pedometer: + 801 801 ; line 111 : } + 802 802 0017D ?L0027: + 803 803 ; line 112 : } + 804 804 0017D ??eb04_pedometer: + 805 805 ; line 113 : interval_hh = 0; + 806 806 $DGL 0,84 + 807 807 0017D RF50800 clrb !?L0007 ; interval_hh ;[INF] 3, 1 + 808 808 00180 ??eb03_pedometer: + 809 809 ; line 114 : } + 810 810 00180 ?L0023: + 811 811 ; line 115 : if( acc_norm[0] > 18000 ) + 812 812 $DGL 0,86 + 813 813 00180 RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 814 814 00183 445146 cmpw ax,#04651H ; 18001 ;[INF] 3, 1 + 815 815 00186 DC0B bc $?L0029 ;[INF] 2, 4 + 816 816 ; line 116 : { + 817 817 00188 ??bb06_pedometer: + 818 818 ; line 117 : th_L = acc_norm[0] - 10000; + 819 819 $DGL 0,88 + 820 820 00188 RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 821 821 0018B 241027 subw ax,#02710H ; 10000 ;[INF] 3, 1 + 822 822 0018E RBF0200 movw !?L0004,ax ; th_L ;[INF] 3, 1 + 823 823 00191 ??eb06_pedometer: + 824 824 ; line 118 : } + 825 825 $DGL 0,89 + 826 826 00191 EF19 br $?L0022 ;[INF] 2, 3 + 827 827 00193 ?L0029: + 828 828 ; line 119 : else + 829 829 ; line 120 : { + 830 830 00193 ??bb07_pedometer: + 831 831 ; line 121 : th_L = 11000; + 832 832 $DGL 0,92 + 833 833 00193 30F82A movw ax,#02AF8H ; 11000 ;[INF] 3, 1 + 834 834 00196 RBF0200 movw !?L0004,ax ; th_L ;[INF] 3, 1 + 835 835 00199 ??eb07_pedometer: + 836 836 ; line 122 : } + 837 837 ; line 123 : } + 838 838 $DGL 0,94 + 839 839 00199 ??eb02_pedometer: + 840 840 00199 EF11 br $?L0022 ;[INF] 2, 3 + 841 841 0019B ?L0021: + 842 842 ; line 124 : else + 843 843 ; line 125 : { + 844 844 0019B ??bb08_pedometer: + 845 845 ; line 126 : interval_hh += ( interval_hh != 255 ) ? 1: 0; // 飽和加算 + 846 846 ; って楽に書けたらいいのに + 847 847 $DGL 0,97 + 848 848 0019B R400800FF cmp !?L0007,#0FFH ; interval_hh,255 ;[INF] 4, 1 + 849 849 0019F DD03 bz $?L0031 ;[INF] 2, 4 + 850 850 001A1 E6 onew ax ;[INF] 1, 1 + 851 851 001A2 EF01 br $?L0032 ;[INF] 2, 3 + 852 852 001A4 ?L0031: + 853 853 001A4 F6 clrw ax ;[INF] 1, 1 + 854 854 001A5 ?L0032: + 855 855 001A5 R340800 movw de,#loww (?L0007) ; interval_hh ;[INF] 3, 1 + 856 856 001A8 89 mov a,[de] ;[INF] 1, 1 + 857 857 001A9 6108 add a,x ;[INF] 2, 1 + 858 858 001AB 99 mov [de],a ;[INF] 1, 1 + 859 859 001AC ??eb08_pedometer: + 860 860 ; line 127 : } + 861 861 001AC ?L0022: + 862 862 ; line 128 : + 863 863 ; line 129 : // (2) 直近の極小からの時間 + 864 864 ; line 130 : if( acc_norm[2] >= acc_norm[1] && acc_norm[1] < acc_norm[0] + 865 865 ; line 131 : && acc_norm[0] < th_L ) + 866 866 $DGL 0,102 + 867 867 001AC RAF0400 movw ax,!?L0005+4 ; acc_norm ;[INF] 3, 1 + 868 868 001AF R420200 cmpw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + 869 869 001B2 DC1B bc $?L0033 ;[INF] 2, 4 + 870 870 001B4 RAF0200 movw ax,!?L0005+2 ; acc_norm ;[INF] 3, 1 + 871 871 001B7 R420000 cmpw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 872 872 001BA DE13 bnc $?L0033 ;[INF] 2, 4 + 873 873 001BC RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 874 874 001BF R420200 cmpw ax,!?L0004 ; th_L ;[INF] 3, 1 + 875 875 001C2 DE0B bnc $?L0033 ;[INF] 2, 4 + 876 876 ; line 132 : { + 877 877 001C4 ??bb09_pedometer: + 878 878 ; line 133 : // 極小を検出 + 879 879 ; line 134 : time_l = 0; + 880 880 $DGL 0,105 + 881 881 001C4 RF50900 clrb !?L0008 ; time_l ;[INF] 3, 1 + 882 882 ; line 135 : peak_l = acc_norm[0]; + 883 883 $DGL 0,106 + 884 884 001C7 RAF0000 movw ax,!?L0005 ; acc_norm ;[INF] 3, 1 + 885 885 001CA RBF0A00 movw !?L0009,ax ; peak_l ;[INF] 3, 1 + 886 886 001CD ??eb09_pedometer: + 887 887 ; line 136 : } + 888 888 $DGL 0,107 + 889 889 001CD EF11 br $?L0034 ;[INF] 2, 3 + 890 890 001CF ?L0033: + 891 891 ; line 137 : else + 892 892 ; line 138 : { + 893 893 001CF ??bb0A_pedometer: + 894 894 ; line 139 : time_l += ( time_l != 255 ) ? 1: 0; + 895 895 $DGL 0,110 + 896 896 001CF R400900FF cmp !?L0008,#0FFH ; time_l,255 ;[INF] 4, 1 + 897 897 001D3 DD03 bz $?L0035 ;[INF] 2, 4 + 898 898 001D5 E6 onew ax ;[INF] 1, 1 + 899 899 001D6 EF01 br $?L0036 ;[INF] 2, 3 + 900 900 001D8 ?L0035: + 901 901 001D8 F6 clrw ax ;[INF] 1, 1 + 902 902 001D9 ?L0036: + 903 903 001D9 R340900 movw de,#loww (?L0008) ; time_l ;[INF] 3, 1 + 904 904 001DC 89 mov a,[de] ;[INF] 1, 1 + 905 905 001DD 6108 add a,x ;[INF] 2, 1 + 906 906 001DF 99 mov [de],a ;[INF] 1, 1 + 907 907 001E0 ??eb0A_pedometer: + 908 908 ; line 140 : } + 909 909 001E0 ?L0034: + 910 910 ; line 141 : + 911 911 ; line 142 : { + 912 912 001E0 ??bb0B_pedometer: + 913 913 001E0 ??eb0B_pedometer: + 914 914 ; line 143 : /* + 915 915 ; line 144 : static u8 i = 0; + 916 916 ; line 145 : + 917 917 ; line 146 : vreg_ctr[VREG_C_FREE_0] = i++; + 918 918 ; line 147 : + 919 919 ; line 148 : vreg_ctr[VREG_C_FREE_1] = (u8)( acc_norm[0] / 256 & 0x00 + 920 920 ; FF ); + 921 921 ; line 149 : vreg_ctr[VREG_C_FREE_2] = (u8)( acc_norm[0] & 0x00FF ); + 922 922 ; line 150 : + 923 923 ; line 151 : vreg_ctr[VREG_C_FREE_3] = (u8)( norm_hist[ hist_indx -1 + 924 924 ; & TAP-1 ] / 256 & 0xFF ); + 925 925 ; line 152 : vreg_ctr[VREG_C_FREE_4] = (u8)( norm_hist[ hist_indx -1 + 926 926 ; & TAP-1 ] & 0xFF ); + 927 927 ; line 153 : + 928 928 ; line 154 : vreg_ctr[VREG_C_FREE_5] = interval_hh; + 929 929 ; line 155 : vreg_ctr[VREG_C_FREE_6] = time_l; + 930 930 ; line 156 : + 931 931 ; line 157 : vreg_ctr[VREG_C_FREE_7] = vreg_ctr[ VREG_C_ACC_HOSU_L ]; + 932 932 ; line 158 : vreg_ctr[VREG_C_FREE_8] = (u8)( peak_l / 256 & 0x00FF ); + 933 933 ; line 159 : vreg_ctr[VREG_C_FREE_9] = (u8)( peak_l & 0x00FF ); + 934 934 ; line 160 : // vreg_ctr[VREG_C_FREE_A] = (u8)( norm_avg[0] / 256 & 0x + 935 935 ; 00FF ); + 936 936 ; line 161 : // vreg_ctr[VREG_C_FREE_B] = (u8)( norm_avg[0] & + 937 937 ; 0x00FF ); + 938 938 ; line 162 : */ + 939 939 ; line 163 : } + 940 940 ; line 164 : } + 941 941 $DGL 0,135 + 942 942 001E0 ??ef_pedometer: + 943 943 001E0 1024 addw sp,#024H ;[INF] 2, 1 + 944 944 001E2 C6 pop hl ;[INF] 1, 1 + 945 945 001E3 D7 ret ;[INF] 1, 6 + 946 946 001E4 ??ee_pedometer: + 947 947 ; line 165 : + 948 948 ; line 166 : + 949 949 ; line 167 : + 950 950 ; line 168 : /*========================================================= + 951 951 ; line 169 : 　歩数＋１ + 952 952 ; line 170 : 　　累積をインクリメント + 953 953 ; line 171 : 　履歴を更新 + 954 954 ; line 172 : ========================================================*/ + 955 955 ; line 173 : u8 p_record; + 956 956 ; line 174 : u8 last_hour = 0x23; // 履歴の最新は何時？ + 957 957 ; line 175 : u8 last_day = 0x30; + 958 958 ; line 176 : u8 last_month = 0x12; + 959 959 ; line 177 : u8 last_year = 0x99; + 960 960 ; line 178 : + 961 961 ; line 179 : #define HOSU_NODATA 0xFFFF + 962 962 ; line 180 : #define HOSU_MAX 0xFFFE + 963 963 ; line 181 : + 964 964 ; line 182 : static void hosu_increment() + 965 965 ; line 183 : { + 966 966 001E4 _hosu_increment: + 967 967 $DGL 1,107 + 968 968 001E4 C7 push hl ;[INF] 1, 1 + 969 969 001E5 2006 subw sp,#06H ;[INF] 2, 1 + 970 970 001E7 FBF8FF movw hl,sp ;[INF] 3, 1 + 971 971 001EA ??bf_hosu_increment: + 972 972 ; line 184 : static u16 last_hour_fny; + 973 973 ; line 185 : + 974 974 ; line 186 : // 累積の更新 // + 975 975 ; line 187 : // いろいろ失敗した... + 976 976 ; line 188 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_L ] == 0 ) + 977 977 $DGL 0,6 + 978 978 001EA RA04B00 inc !_vreg_ctr+75 ;[INF] 3, 2 + 979 979 001ED RD54B00 cmp0 !_vreg_ctr+75 ;[INF] 3, 1 + 980 980 001F0 DF1C bnz $?L0044 ;[INF] 2, 4 + 981 981 ; line 189 : { + 982 982 001F2 ??bb00_hosu_increment: + 983 983 ; line 190 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_M ] == 0 ) + 984 984 $DGL 0,8 + 985 985 001F2 RA04C00 inc !_vreg_ctr+76 ;[INF] 3, 2 + 986 986 001F5 RD54C00 cmp0 !_vreg_ctr+76 ;[INF] 3, 1 + 987 987 001F8 DF14 bnz $?L0044 ;[INF] 2, 4 + 988 988 ; line 191 : { + 989 989 001FA ??bb01_hosu_increment: + 990 990 ; line 192 : if( ++vreg_ctr[ VREG_C_ACC_HOSU_H ] == 0 ){ + 991 991 $DGL 0,10 + 992 992 001FA RA04D00 inc !_vreg_ctr+77 ;[INF] 3, 2 + 993 993 001FD RD54D00 cmp0 !_vreg_ctr+77 ;[INF] 3, 1 + 994 994 00200 DF0C bnz $?L0044 ;[INF] 2, 4 + 995 995 00202 ??bb02_hosu_increment: + 996 996 ; line 193 : vreg_ctr[ VREG_C_ACC_HOSU_L ] = 255; // カンスト + 997 997 ; orz + 998 998 $DGL 0,11 + 999 999 00202 RCF4B00FF mov !_vreg_ctr+75,#0FFH ; 255 ;[INF] 4, 1 + 1000 1000 ; line 194 : vreg_ctr[ VREG_C_ACC_HOSU_M ] = 255; + 1001 1001 $DGL 0,12 + 1002 1002 00206 RCF4C00FF mov !_vreg_ctr+76,#0FFH ; 255 ;[INF] 4, 1 + 1003 1003 ; line 195 : vreg_ctr[ VREG_C_ACC_HOSU_H ] = 255; + 1004 1004 $DGL 0,13 + 1005 1005 0020A RCF4D00FF mov !_vreg_ctr+77,#0FFH ; 255 ;[INF] 4, 1 + 1006 1006 0020E ??eb02_hosu_increment: + 1007 1007 ; line 196 : } + 1008 1008 0020E ?L0044: + 1009 1009 0020E ??eb01_hosu_increment: + 1010 1010 ; line 197 : } + 1011 1011 0020E ??eb00_hosu_increment: + 1012 1012 ; line 198 : } + 1013 1013 ; line 199 : + 1014 1014 ; line 200 : { + 1015 1015 0020E ??bb03_hosu_increment: + 1016 1016 ; line 201 : // 毎時履歴の更新 ///////////////////////////// + 1017 1017 ; line 202 : // 空白の時間を考慮する。１時間以上放置されたなど。 + 1018 1018 ; line 203 : u16 now_hour; + 1019 1019 ; line 204 : u8 now_year; + 1020 1020 ; line 205 : + 1021 1021 ; line 206 : // 時計を止める必要が有るので↓は一気に行って下さい + 1022 1022 ; line 207 : DI(); + 1023 1023 $DGL 0,25 + 1024 1024 0020E 717BFA di ;[INF] 3, 4 + 1025 1025 ; line 208 : RWAIT = 1; + 1026 1026 $DGL 0,26 + 1027 1027 00211 710A9E set1 RTCC1.0 ;[INF] 3, 2 + 1028 1028 ; line 209 : while( !RWST ){;} + 1029 1029 $DGL 0,27 + 1030 1030 00214 ?L0046: + 1031 1031 00214 31929E02 bt RTCC1.1,$?L0047 ;[INF] 4, 5 + 1032 1032 00218 ??bb04_hosu_increment: + 1033 1033 00218 ??eb04_hosu_increment: + 1034 1034 00218 EFFA br $?L0046 ;[INF] 2, 3 + 1035 1035 0021A ?L0047: + 1036 1036 ; line 210 : now_year = bcdtob( YEAR ); + 1037 1037 $DGL 0,28 + 1038 1038 0021A 8E98 mov a,YEAR ;[INF] 2, 1 + 1039 1039 0021C RFD0000 call !@@bcdtob ;[INF] 3, 3 + 1040 1040 0021F 9C03 mov [hl+3],a ; now_year ;[INF] 2, 1 + 1041 1041 ; line 211 : last_hour = HOUR; // 履歴読み出し時に使用。BCDのまま + 1042 1042 ; でよい + 1043 1043 $DGL 0,29 + 1044 1044 00221 8E94 mov a,HOUR ;[INF] 2, 1 + 1045 1045 00223 R9F0400 mov !_last_hour,a ;[INF] 3, 1 + 1046 1046 ; line 212 : last_day = DAY; + 1047 1047 $DGL 0,30 + 1048 1048 00226 8E96 mov a,DAY ;[INF] 2, 1 + 1049 1049 00228 R9F0500 mov !_last_day,a ;[INF] 3, 1 + 1050 1050 ; line 213 : last_month = MONTH; + 1051 1051 $DGL 0,31 + 1052 1052 0022B 8E97 mov a,MONTH ;[INF] 2, 1 + 1053 1053 0022D R9F0600 mov !_last_month,a ;[INF] 3, 1 + 1054 1054 ; line 214 : now_hour = get_long_hour(); + 1055 1055 $DGL 0,32 + 1056 1056 00230 RFD8A03 call !_get_long_hour ;[INF] 3, 3 + 1057 1057 00233 13 movw ax,bc ;[INF] 1, 1 + 1058 1058 00234 BC04 movw [hl+4],ax ; now_hour ;[INF] 2, 1 + 1059 1059 ; line 215 : // RWAIT = 0; ↑で行っています + 1060 1060 ; line 216 : // EI(); 〃 + 1061 1061 ; line 217 : + 1062 1062 ; line 218 : // 歩数計が止まっていた時間を考慮して必要なら進める // + 1063 1063 ; line 219 : if( last_year == now_year ) + 1064 1064 $DGL 0,37 + 1065 1065 00236 R8F0700 mov a,!_last_year ;[INF] 3, 1 + 1066 1066 00239 4E03 cmp a,[hl+3] ; now_year ;[INF] 2, 1 + 1067 1067 0023B DF12 bnz $?L0048 ;[INF] 2, 4 + 1068 1068 ; line 220 : { + 1069 1069 0023D ??bb05_hosu_increment: + 1070 1070 ; line 221 : if( now_hour > last_hour_fny ) + 1071 1071 $DGL 0,39 + 1072 1072 0023D RAF9200 movw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + 1073 1073 00240 614904 cmpw ax,[hl+4] ; now_hour ;[INF] 3, 1 + 1074 1074 00243 DE41 bnc $?L0056 ;[INF] 2, 4 + 1075 1075 ; line 222 : { + 1076 1076 00245 ??bb06_hosu_increment: + 1077 1077 ; line 223 : fill_hosu_hist_hours( now_hour - last_hour_fny ) + 1078 1078 ; ; + 1079 1079 $DGL 0,41 + 1080 1080 00245 AC04 movw ax,[hl+4] ; now_hour ;[INF] 2, 1 + 1081 1081 00247 R229200 subw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + 1082 1082 0024A RFDB902 call !_fill_hosu_hist_hours ;[INF] 3, 3 + 1083 1083 0024D ??eb06_hosu_increment: + 1084 1084 ; line 224 : } + 1085 1085 ; line 225 : } + 1086 1086 $DGL 0,43 + 1087 1087 0024D ??eb05_hosu_increment: + 1088 1088 0024D EF37 br $?L0056 ;[INF] 2, 3 + 1089 1089 0024F ?L0048: + 1090 1090 ; line 226 : else if( last_year == ( now_year -1 ) ) + 1091 1091 $DGL 0,44 + 1092 1092 0024F 8C03 mov a,[hl+3] ; now_year ;[INF] 2, 1 + 1093 1093 00251 318E shrw ax,8 ;[INF] 2, 1 + 1094 1094 00253 B1 decw ax ;[INF] 1, 1 + 1095 1095 00254 12 movw bc,ax ;[INF] 1, 1 + 1096 1096 00255 RD90700 mov x,!_last_year ;[INF] 3, 1 + 1097 1097 00258 F1 clrb a ;[INF] 1, 1 + 1098 1098 00259 43 cmpw ax,bc ;[INF] 1, 1 + 1099 1099 0025A DF1F bnz $?L0052 ;[INF] 2, 4 + 1100 1100 ; line 227 : { + 1101 1101 0025C ??bb07_hosu_increment: + 1102 1102 ; line 228 : // 年をまたいでいるとき + 1103 1103 ; line 229 : u16 temp_hours = ( ( 365 + (( now_year & 0x03 ) == + 1104 1104 ; 1 ? 1: 0 )) * 24 ) - last_hour_fny + now_hour; + 1105 1105 $DGL 0,47 + 1106 1106 0025C 8C03 mov a,[hl+3] ; now_year ;[INF] 2, 1 + 1107 1107 0025E 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 1108 1108 00260 91 dec a ;[INF] 1, 1 + 1109 1109 00261 DF03 bnz $?L0054 ;[INF] 2, 4 + 1110 1110 00263 E6 onew ax ;[INF] 1, 1 + 1111 1111 00264 EF01 br $?L0055 ;[INF] 2, 3 + 1112 1112 00266 ?L0054: + 1113 1113 00266 F6 clrw ax ;[INF] 1, 1 + 1114 1114 00267 ?L0055: + 1115 1115 00267 046D01 addw ax,#016DH ; 365 ;[INF] 3, 1 + 1116 1116 0026A 313D shlw ax,3 ;[INF] 2, 1 + 1117 1117 0026C 12 movw bc,ax ;[INF] 1, 1 + 1118 1118 0026D 01 addw ax,ax ;[INF] 1, 1 + 1119 1119 0026E 03 addw ax,bc ;[INF] 1, 1 + 1120 1120 0026F R229200 subw ax,!?L0039 ; last_hour_fny ;[INF] 3, 1 + 1121 1121 00272 610904 addw ax,[hl+4] ; now_hour ;[INF] 3, 1 + 1122 1122 00275 BB movw [hl],ax ; temp_hours ;[INF] 1, 1 + 1123 1123 ; line 230 : fill_hosu_hist_hours( temp_hours ); + 1124 1124 $DGL 0,48 + 1125 1125 00276 RFDB902 call !_fill_hosu_hist_hours ;[INF] 3, 3 + 1126 1126 00279 ??eb07_hosu_increment: + 1127 1127 ; line 231 : } + 1128 1128 $DGL 0,49 + 1129 1129 00279 EF0B br $?L0056 ;[INF] 2, 3 + 1130 1130 0027B ?L0052: + 1131 1131 ; line 232 : else if( last_year < now_year ) + 1132 1132 $DGL 0,50 + 1133 1133 0027B R8F0700 mov a,!_last_year ;[INF] 3, 1 + 1134 1134 0027E 4E03 cmp a,[hl+3] ; now_year ;[INF] 2, 1 + 1135 1135 00280 DE04 bnc $?L0056 ;[INF] 2, 4 + 1136 1136 ; line 233 : { + 1137 1137 00282 ??bb08_hosu_increment: + 1138 1138 ; line 234 : // 数年放置 + 1139 1139 ; line 235 : fill_hosu_hist_hours( 0 ); + 1140 1140 $DGL 0,53 + 1141 1141 00282 F6 clrw ax ;[INF] 1, 1 + 1142 1142 00283 RFDB902 call !_fill_hosu_hist_hours ;[INF] 3, 3 + 1143 1143 00286 ??eb08_hosu_increment: + 1144 1144 ; line 236 : } + 1145 1145 00286 ?L0056: + 1146 1146 ; line 237 : else + 1147 1147 ; line 238 : { + 1148 1148 00286 ??bb09_hosu_increment: + 1149 1149 00286 ??eb09_hosu_increment: + 1150 1150 ; line 239 : // カレンダーが巻き戻るなど + 1151 1151 ; line 240 : // ノーケアでよい + 1152 1152 ; line 241 : } + 1153 1153 ; line 242 : last_year = now_year; + 1154 1154 $DGL 0,60 + 1155 1155 00286 8C03 mov a,[hl+3] ; now_year ;[INF] 2, 1 + 1156 1156 00288 R9F0700 mov !_last_year,a ;[INF] 3, 1 + 1157 1157 ; line 243 : last_hour_fny = now_hour; + 1158 1158 $DGL 0,61 + 1159 1159 0028B AC04 movw ax,[hl+4] ; now_hour ;[INF] 2, 1 + 1160 1160 0028D RBF9200 movw !?L0039,ax ; last_hour_fny ;[INF] 3, 1 + 1161 1161 ; line 244 : + 1162 1162 ; line 245 : // 実際にインクリメント + 1163 1163 ; line 246 : if( pool[ p_record ] == HOSU_NODATA ) + 1164 1164 $DGL 0,64 + 1165 1165 00290 RD99000 mov x,!_p_record ;[INF] 3, 1 + 1166 1166 00293 F1 clrb a ;[INF] 1, 1 + 1167 1167 00294 01 addw ax,ax ;[INF] 1, 1 + 1168 1168 00295 R040000 addw ax,#loww (_pool) ;[INF] 3, 1 + 1169 1169 00298 14 movw de,ax ;[INF] 1, 1 + 1170 1170 00299 A9 movw ax,[de] ;[INF] 1, 1 + 1171 1171 0029A 44FFFF cmpw ax,#0FFFFH ; -1 ;[INF] 3, 1 + 1172 1172 0029D DF04 bnz $?L0058 ;[INF] 2, 4 + 1173 1173 ; line 247 : { + 1174 1174 0029F ??bb0A_hosu_increment: + 1175 1175 ; line 248 : pool[ p_record ] = 1; + 1176 1176 $DGL 0,66 + 1177 1177 0029F E6 onew ax ;[INF] 1, 1 + 1178 1178 002A0 B9 movw [de],ax ;[INF] 1, 1 + 1179 1179 002A1 ??eb0A_hosu_increment: + 1180 1180 ; line 249 : } + 1181 1181 $DGL 0,67 + 1182 1182 002A1 EF12 br $?L0060 ;[INF] 2, 3 + 1183 1183 002A3 ?L0058: + 1184 1184 ; line 250 : else if( pool[ p_record ] != HOSU_MAX ) + 1185 1185 $DGL 0,68 + 1186 1186 002A3 RD99000 mov x,!_p_record ;[INF] 3, 1 + 1187 1187 002A6 F1 clrb a ;[INF] 1, 1 + 1188 1188 002A7 01 addw ax,ax ;[INF] 1, 1 + 1189 1189 002A8 R040000 addw ax,#loww (_pool) ;[INF] 3, 1 + 1190 1190 002AB 14 movw de,ax ;[INF] 1, 1 + 1191 1191 002AC A9 movw ax,[de] ;[INF] 1, 1 + 1192 1192 002AD 44FEFF cmpw ax,#0FFFEH ; -2 ;[INF] 3, 1 + 1193 1193 002B0 DD03 bz $?L0060 ;[INF] 2, 4 + 1194 1194 ; line 251 : { + 1195 1195 002B2 ??bb0B_hosu_increment: + 1196 1196 ; line 252 : pool[ p_record ] += 1; + 1197 1197 $DGL 0,70 + 1198 1198 002B2 A9 movw ax,[de] ;[INF] 1, 1 + 1199 1199 002B3 A1 incw ax ;[INF] 1, 1 + 1200 1200 002B4 B9 movw [de],ax ;[INF] 1, 1 + 1201 1201 002B5 ??eb0B_hosu_increment: + 1202 1202 ; line 253 : } + 1203 1203 002B5 ?L0060: + 1204 1204 002B5 ??eb03_hosu_increment: + 1205 1205 ; line 254 : } + 1206 1206 ; line 255 : } + 1207 1207 $DGL 0,73 + 1208 1208 002B5 ??ef_hosu_increment: + 1209 1209 002B5 1006 addw sp,#06H ;[INF] 2, 1 + 1210 1210 002B7 C6 pop hl ;[INF] 1, 1 + 1211 1211 002B8 D7 ret ;[INF] 1, 6 + 1212 1212 002B9 ??ee_hosu_increment: + 1213 1213 ; line 256 : + 1214 1214 ; line 257 : + 1215 1215 ; line 258 : + 1216 1216 ; line 259 : /* ======================================================== + 1217 1217 ; line 260 : 空白の時間を適切に0にして、 + 1218 1218 ; line 261 : 今を含む１時間のデータを書く位置にポインタ？を進める + 1219 1219 ; line 262 : ======================================================== */ + 1220 1220 ; line 263 : void fill_hosu_hist_hours( u16 hours ) + 1221 1221 ; line 264 : { + 1222 1222 002B9 _fill_hosu_hist_hours: + 1223 1223 $DGL 1,168 + 1224 1224 002B9 C7 push hl ;[INF] 1, 1 + 1225 1225 002BA 16 movw hl,ax ;[INF] 1, 1 + 1226 1226 002BB ??bf_fill_hosu_hist_hours: + 1227 1227 ; line 265 : if( hours > 255 ) + 1228 1228 $DGL 0,2 + 1229 1229 002BB 17 movw ax,hl ;[INF] 1, 1 + 1230 1230 002BC 440001 cmpw ax,#0100H ; 256 ;[INF] 3, 1 + 1231 1231 002BF DC02 bc $?L0064 ;[INF] 2, 4 + 1232 1232 ; line 266 : { + 1233 1233 002C1 ??bb00_fill_hosu_hist_hours: + 1234 1234 ; line 267 : hours = 0; + 1235 1235 $DGL 0,4 + 1236 1236 002C1 F6 clrw ax ;[INF] 1, 1 + 1237 1237 002C2 16 movw hl,ax ;[INF] 1, 1 + 1238 1238 002C3 ??eb00_fill_hosu_hist_hours: + 1239 1239 ; line 268 : } + 1240 1240 002C3 ?L0064: + 1241 1241 ; line 269 : + 1242 1242 ; line 270 : // 空白の数時間の設定 + 1243 1243 ; line 271 : do + 1244 1244 ; line 272 : { + 1245 1245 002C3 ??bb01_fill_hosu_hist_hours: + 1246 1246 ; line 273 : p_record += 1; + 1247 1247 $DGL 0,10 + 1248 1248 002C3 RA09000 inc !_p_record ;[INF] 3, 2 + 1249 1249 ; line 274 : pool[ p_record ] = 0; + 1250 1250 $DGL 0,11 + 1251 1251 002C6 RF99000 mov c,!_p_record ;[INF] 3, 1 + 1252 1252 002C9 F3 clrb b ;[INF] 1, 1 + 1253 1253 002CA 311C shlw bc,1 ;[INF] 2, 1 + 1254 1254 002CC F6 clrw ax ;[INF] 1, 1 + 1255 1255 002CD R780000 movw _pool[bc],ax ;[INF] 3, 1 + 1256 1256 ; line 275 : hours -= 1; + 1257 1257 $DGL 0,12 + 1258 1258 002D0 B7 decw hl ;[INF] 1, 1 + 1259 1259 002D1 ??eb01_fill_hosu_hist_hours: + 1260 1260 ; line 276 : } + 1261 1261 ; line 277 : while( hours != 0 ); + 1262 1262 $DGL 0,14 + 1263 1263 002D1 F6 clrw ax ;[INF] 1, 1 + 1264 1264 002D2 47 cmpw ax,hl ;[INF] 1, 1 + 1265 1265 002D3 DFEE bnz $?L0064 ;[INF] 2, 4 + 1266 1266 ; line 278 : } + 1267 1267 $DGL 0,15 + 1268 1268 002D5 ??ef_fill_hosu_hist_hours: + 1269 1269 002D5 C6 pop hl ;[INF] 1, 1 + 1270 1270 002D6 D7 ret ;[INF] 1, 6 + 1271 1271 002D7 ??ee_fill_hosu_hist_hours: + 1272 1272 ; line 279 : + 1273 1273 ; line 280 : + 1274 1274 ; line 281 : + 1275 1275 ; line 282 : /* ======================================================== + 1276 1276 ; line 283 : 空白の時間を適切に0にして、 + 1277 1277 ; line 284 : 今を含む１時間のデータを書く位置にポインタ？を進める + 1278 1278 ; line 285 : ======================================================== */ + 1279 1279 ; line 286 : void clear_hosu_hist() + 1280 1280 ; line 287 : { + 1281 1281 002D7 _clear_hosu_hist: + 1282 1282 $DGL 1,183 + 1283 1283 002D7 C7 push hl ;[INF] 1, 1 + 1284 1284 002D8 ??bf_clear_hosu_hist: + 1285 1285 ; line 288 : u8 hours = 0; + 1286 1286 $DGL 0,2 + 1287 1287 002D8 5600 mov l,#00H ; 0 ;[INF] 2, 1 + 1288 1288 ; line 289 : // 空白の数時間の設定 + 1289 1289 ; line 290 : do + 1290 1290 002DA ?L0071: + 1291 1291 ; line 291 : { + 1292 1292 002DA ??bb00_clear_hosu_hist: + 1293 1293 ; line 292 : pool[ hours ] = 0xFFFF; + 1294 1294 $DGL 0,6 + 1295 1295 002DA 66 mov a,l ;[INF] 1, 1 + 1296 1296 002DB F0 clrb x ;[INF] 1, 1 + 1297 1297 002DC 317E shrw ax,7 ;[INF] 2, 1 + 1298 1298 002DE 12 movw bc,ax ;[INF] 1, 1 + 1299 1299 002DF F6 clrw ax ;[INF] 1, 1 + 1300 1300 002E0 B1 decw ax ;[INF] 1, 1 + 1301 1301 002E1 R780000 movw _pool[bc],ax ;[INF] 3, 1 + 1302 1302 ; line 293 : hours -= 1; + 1303 1303 $DGL 0,7 + 1304 1304 002E4 96 dec l ;[INF] 1, 1 + 1305 1305 002E5 ??eb00_clear_hosu_hist: + 1306 1306 ; line 294 : } + 1307 1307 ; line 295 : while( hours != 0 ); + 1308 1308 $DGL 0,9 + 1309 1309 002E5 66 mov a,l ;[INF] 1, 1 + 1310 1310 002E6 D1 cmp0 a ;[INF] 1, 1 + 1311 1311 002E7 DFF1 bnz $?L0071 ;[INF] 2, 4 + 1312 1312 ; line 296 : vreg_ctr[ VREG_C_ACC_HOSU_L ] = 0; + 1313 1313 $DGL 0,10 + 1314 1314 002E9 RF54B00 clrb !_vreg_ctr+75 ;[INF] 3, 1 + 1315 1315 ; line 297 : vreg_ctr[ VREG_C_ACC_HOSU_M ] = 0; + 1316 1316 $DGL 0,11 + 1317 1317 002EC RF54C00 clrb !_vreg_ctr+76 ;[INF] 3, 1 + 1318 1318 ; line 298 : vreg_ctr[ VREG_C_ACC_HOSU_H ] = 0; + 1319 1319 $DGL 0,12 + 1320 1320 002EF RF54D00 clrb !_vreg_ctr+77 ;[INF] 3, 1 + 1321 1321 ; line 299 : } + 1322 1322 $DGL 0,13 + 1323 1323 002F2 ??ef_clear_hosu_hist: + 1324 1324 002F2 C6 pop hl ;[INF] 1, 1 + 1325 1325 002F3 D7 ret ;[INF] 1, 6 + 1326 1326 002F4 ??ee_clear_hosu_hist: + 1327 1327 ; line 300 : + 1328 1328 ; line 301 : + 1329 1329 ; line 302 : extern u8 iic_burst_state; + 1330 1330 ; line 303 : bit record_read_msb_lsb; + 1331 1331 ; line 304 : + 1332 1332 ; line 305 : /* ======================================================== + 1333 1333 ; line 306 : 歩数計ヒストリ読み出しの後処理(初期化) + 1334 1334 ; line 307 : 読み出しポインタのクリア + 1335 1335 ; line 308 : ======================================================== */ + 1336 1336 ; line 309 : void hosu_read_end( ) + 1337 1337 ; line 310 : { + 1338 1338 002F4 _hosu_read_end: + 1339 1339 $DGL 1,194 + 1340 1340 002F4 ??bf_hosu_read_end: + 1341 1341 ; line 311 : record_read_msb_lsb = 0; + 1342 1342 $DGL 0,2 + 1343 1343 002F4 R710300 clr1 _record_read_msb_lsb ;[INF] 3, 2 + 1344 1344 ; line 312 : } + 1345 1345 $DGL 0,3 + 1346 1346 002F7 ??ef_hosu_read_end: + 1347 1347 002F7 D7 ret ;[INF] 1, 6 + 1348 1348 002F8 ??ee_hosu_read_end: + 1349 1349 ; line 313 : + 1350 1350 ; line 314 : + 1351 1351 ; line 315 : /* ======================================================== + 1352 1352 ; line 316 : 歩数計のヒストリを返す。 + 1353 1353 ; line 317 : １回呼ぶ度に、ヒストリの下位、上位、一時間遡って下位上位... + 1354 1354 ; line 318 : ======================================================== */ + 1355 1355 ; line 319 : u8 hosu_read( ) + 1356 1356 ; line 320 : { + 1357 1357 002F8 _hosu_read: + 1358 1358 $DGL 1,200 + 1359 1359 002F8 C7 push hl ;[INF] 1, 1 + 1360 1360 002F9 2004 subw sp,#04H ;[INF] 2, 1 + 1361 1361 002FB FBF8FF movw hl,sp ;[INF] 3, 1 + 1362 1362 002FE ??bf_hosu_read: + 1363 1363 ; line 321 : u8 dat; + 1364 1364 ; line 322 : u16 temp; + 1365 1365 ; line 323 : static u8 p_record_buffer; + 1366 1366 ; line 324 : + 1367 1367 ; line 325 : switch( iic_burst_state ){ + 1368 1368 $DGL 0,6 + 1369 1369 002FE RD90000 mov x,!_iic_burst_state ;[INF] 3, 1 + 1370 1370 00301 F1 clrb a ;[INF] 1, 1 + 1371 1371 00302 E7 onew bc ;[INF] 1, 1 + 1372 1372 00303 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 1373 1373 00306 DD11 bz $?L0080 ;[INF] 2, 4 + 1374 1374 00308 23 subw ax,bc ;[INF] 1, 1 + 1375 1375 00309 DD1E bz $?L0081 ;[INF] 2, 4 + 1376 1376 0030B 23 subw ax,bc ;[INF] 1, 1 + 1377 1377 0030C DD25 bz $?L0082 ;[INF] 2, 4 + 1378 1378 0030E 23 subw ax,bc ;[INF] 1, 1 + 1379 1379 0030F DD2C bz $?L0083 ;[INF] 2, 4 + 1380 1380 00311 23 subw ax,bc ;[INF] 1, 1 + 1381 1381 00312 DD37 bz $?L0084 ;[INF] 2, 4 + 1382 1382 00314 23 subw ax,bc ;[INF] 1, 1 + 1383 1383 00315 DD3C bz $?L0085 ;[INF] 2, 4 + 1384 1384 00317 EF42 br $?L0086 ;[INF] 2, 3 + 1385 1385 00319 ??bb00_hosu_read: + 1386 1386 ; line 326 : case( 0 ): + 1387 1387 00319 ?L0080: + 1388 1388 ; line 327 : p_record_buffer = p_record; + 1389 1389 $DGL 0,8 + 1390 1390 00319 R8F9000 mov a,!_p_record ;[INF] 3, 1 + 1391 1391 0031C R9F9400 mov !?L0078,a ; p_record_buffer ;[INF] 3, 1 + 1392 1392 ; line 328 : iic_burst_state += 1; + 1393 1393 $DGL 0,9 + 1394 1394 0031F RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1395 1395 ; line 329 : return( last_hour ); + 1396 1396 $DGL 0,10 + 1397 1397 00322 RD90400 mov x,!_last_hour ;[INF] 3, 1 + 1398 1398 00325 F1 clrb a ;[INF] 1, 1 + 1399 1399 00326 12 movw bc,ax ;[INF] 1, 1 + 1400 1400 00327 EF5D br $?L0079 ;[INF] 2, 3 + 1401 1401 ; line 330 : + 1402 1402 ; line 331 : case( 1 ): + 1403 1403 00329 ?L0081: + 1404 1404 ; line 332 : iic_burst_state += 1; + 1405 1405 $DGL 0,13 + 1406 1406 00329 RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1407 1407 ; line 333 : return( last_day ); + 1408 1408 $DGL 0,14 + 1409 1409 0032C RD90500 mov x,!_last_day ;[INF] 3, 1 + 1410 1410 0032F F1 clrb a ;[INF] 1, 1 + 1411 1411 00330 12 movw bc,ax ;[INF] 1, 1 + 1412 1412 00331 EF53 br $?L0079 ;[INF] 2, 3 + 1413 1413 ; line 334 : + 1414 1414 ; line 335 : case( 2 ): + 1415 1415 00333 ?L0082: + 1416 1416 ; line 336 : iic_burst_state += 1; + 1417 1417 $DGL 0,17 + 1418 1418 00333 RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1419 1419 ; line 337 : return( last_month ); + 1420 1420 $DGL 0,18 + 1421 1421 00336 RD90600 mov x,!_last_month ;[INF] 3, 1 + 1422 1422 00339 F1 clrb a ;[INF] 1, 1 + 1423 1423 0033A 12 movw bc,ax ;[INF] 1, 1 + 1424 1424 0033B EF49 br $?L0079 ;[INF] 2, 3 + 1425 1425 ; line 338 : + 1426 1426 ; line 339 : case( 3 ): + 1427 1427 0033D ?L0083: + 1428 1428 ; line 340 : iic_burst_state += 1; + 1429 1429 $DGL 0,21 + 1430 1430 0033D RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1431 1431 ; line 341 : return( btobcd(last_year) ); + 1432 1432 $DGL 0,22 + 1433 1433 00340 R8F0700 mov a,!_last_year ;[INF] 3, 1 + 1434 1434 00343 RFD0000 call !@@bbcd ;[INF] 3, 3 + 1435 1435 00346 318E shrw ax,8 ;[INF] 2, 1 + 1436 1436 00348 12 movw bc,ax ;[INF] 1, 1 + 1437 1437 00349 EF3B br $?L0079 ;[INF] 2, 3 + 1438 1438 ; line 342 : + 1439 1439 ; line 343 : case( 4 ): + 1440 1440 0034B ?L0084: + 1441 1441 ; line 344 : iic_burst_state += 1; + 1442 1442 $DGL 0,25 + 1443 1443 0034B RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1444 1444 ; line 345 : return( 0x55 ); // reserved dummy + 1445 1445 $DGL 0,26 + 1446 1446 0034E 325500 movw bc,#055H ; 85 ;[INF] 3, 1 + 1447 1447 00351 EF33 br $?L0079 ;[INF] 2, 3 + 1448 1448 ; line 346 : + 1449 1449 ; line 347 : case( 5 ): + 1450 1450 00353 ?L0085: + 1451 1451 ; line 348 : iic_burst_state += 1; + 1452 1452 $DGL 0,29 + 1453 1453 00353 RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 1454 1454 ; line 349 : return( 0xAA ); // reserved. dummy + 1455 1455 $DGL 0,30 + 1456 1456 00356 32AA00 movw bc,#0AAH ; 170 ;[INF] 3, 1 + 1457 1457 00359 EF2B br $?L0079 ;[INF] 2, 3 + 1458 1458 ; line 350 : + 1459 1459 ; line 351 : default: + 1460 1460 0035B ?L0086: + 1461 1461 ; line 352 : temp = pool[ p_record_buffer ]; + 1462 1462 $DGL 0,33 + 1463 1463 0035B RF99400 mov c,!?L0078 ; p_record_buffer ;[INF] 3, 1 + 1464 1464 0035E F3 clrb b ;[INF] 1, 1 + 1465 1465 0035F 311C shlw bc,1 ;[INF] 2, 1 + 1466 1466 00361 R790000 movw ax,_pool[bc] ;[INF] 3, 1 + 1467 1467 00364 BB movw [hl],ax ; temp ;[INF] 1, 1 + 1468 1468 ; line 353 : if( record_read_msb_lsb == 0 ) + 1469 1469 $DGL 0,34 + 1470 1470 00365 R31020005 bt _record_read_msb_lsb,$?L0089 ;[INF] 4, 5 + 1471 1471 ; line 354 : { + 1472 1472 00369 ??bb01_hosu_read: + 1473 1473 ; line 355 : dat = (u8)( temp & 0x00FF ); + 1474 1474 $DGL 0,36 + 1475 1475 00369 8B mov a,[hl] ; temp ;[INF] 1, 1 + 1476 1476 0036A 9C03 mov [hl+3],a ; dat ;[INF] 2, 1 + 1477 1477 0036C ??eb01_hosu_read: + 1478 1478 ; line 356 : } + 1479 1479 $DGL 0,37 + 1480 1480 0036C EF07 br $?L0090 ;[INF] 2, 3 + 1481 1481 0036E ?L0089: + 1482 1482 ; line 357 : else + 1483 1483 ; line 358 : { + 1484 1484 0036E ??bb02_hosu_read: + 1485 1485 ; line 359 : dat = (u8)(( temp >> 8 ) & 0x00FF ); + 1486 1486 $DGL 0,40 + 1487 1487 0036E 8C01 mov a,[hl+1] ; temp ;[INF] 2, 1 + 1488 1488 00370 9C03 mov [hl+3],a ; dat ;[INF] 2, 1 + 1489 1489 ; line 360 : p_record_buffer -= 1; + 1490 1490 $DGL 0,41 + 1491 1491 00372 RB09400 dec !?L0078 ; p_record_buffer ;[INF] 3, 2 + 1492 1492 00375 ??eb02_hosu_read: + 1493 1493 ; line 361 : } + 1494 1494 00375 ?L0090: + 1495 1495 ; line 362 : record_read_msb_lsb += 1; + 1496 1496 $DGL 0,43 + 1497 1497 00375 7180 set1 CY ;[INF] 2, 1 + 1498 1498 00377 R710700 xor1 CY,_record_read_msb_lsb ;[INF] 3, 1 + 1499 1499 0037A 61DC rolc a,1 ;[INF] 2, 1 + 1500 1500 0037C 61FB rorc a,1 ;[INF] 2, 1 + 1501 1501 0037E R710100 mov1 _record_read_msb_lsb,CY ;[INF] 3, 2 + 1502 1502 ; line 363 : return( dat ); + 1503 1503 $DGL 0,44 + 1504 1504 00381 8C03 mov a,[hl+3] ; dat ;[INF] 2, 1 + 1505 1505 00383 318E shrw ax,8 ;[INF] 2, 1 + 1506 1506 00385 12 movw bc,ax ;[INF] 1, 1 + 1507 1507 00386 ??eb00_hosu_read: + 1508 1508 ; line 364 : } + 1509 1509 00386 ?L0079: + 1510 1510 ; line 365 : } + 1511 1511 $DGL 0,46 + 1512 1512 00386 ??ef_hosu_read: + 1513 1513 00386 1004 addw sp,#04H ;[INF] 2, 1 + 1514 1514 00388 C6 pop hl ;[INF] 1, 1 + 1515 1515 00389 D7 ret ;[INF] 1, 6 + 1516 1516 0038A ??ee_hosu_read: + 1517 1517 ; line 366 : + 1518 1518 ; line 367 : + 1519 1519 ; line 368 : + 1520 1520 ; line 369 : /* ======================================================== + 1521 1521 ; line 370 : 今年の元旦からの経過時間(hour)を返す。 + 1522 1522 ; line 371 : 引数 無し + 1523 1523 ; line 372 : 返値 u16 long_hour + 1524 1524 ; line 373 : ======================================================== */ + 1525 1525 ; line 374 : static const u16 DAYS_FROM_HNY[] = { + 1526 1526 ; line 375 : 0, + 1527 1527 ; line 376 : 0, 31, 31+28, 59+31, 90+30, + 1528 1528 ; line 377 : 120+31, 151+30, 181+31, 212+31, 243+30, + 1529 1529 ; line 378 : 273+31, 304+30 }; + 1530 1530 ; line 379 : + 1531 1531 ; line 380 : u16 get_long_hour() + 1532 1532 ; line 381 : { + 1533 1533 0038A _get_long_hour: + 1534 1534 $DGL 1,223 + 1535 1535 0038A C7 push hl ;[INF] 1, 1 + 1536 1536 0038B 2006 subw sp,#06H ;[INF] 2, 1 + 1537 1537 0038D FBF8FF movw hl,sp ;[INF] 3, 1 + 1538 1538 00390 ??bf_get_long_hour: + 1539 1539 ; line 382 : u16 long_hour; + 1540 1540 ; line 383 : u8 year_hex; + 1541 1541 ; line 384 : u8 month_hex; + 1542 1542 ; line 385 : u8 day_hex; + 1543 1543 ; line 386 : u8 hour_hex; + 1544 1544 ; line 387 : + 1545 1545 ; line 388 : year_hex = bcdtob( YEAR ); + 1546 1546 $DGL 0,8 + 1547 1547 00390 8E98 mov a,YEAR ;[INF] 2, 1 + 1548 1548 00392 RFD0000 call !@@bcdtob ;[INF] 3, 3 + 1549 1549 00395 9C03 mov [hl+3],a ; year_hex ;[INF] 2, 1 + 1550 1550 ; line 389 : month_hex = bcdtob( MONTH ); + 1551 1551 $DGL 0,9 + 1552 1552 00397 8E97 mov a,MONTH ;[INF] 2, 1 + 1553 1553 00399 RFD0000 call !@@bcdtob ;[INF] 3, 3 + 1554 1554 0039C 9C02 mov [hl+2],a ; month_hex ;[INF] 2, 1 + 1555 1555 ; line 390 : day_hex = bcdtob( DAY ); + 1556 1556 $DGL 0,10 + 1557 1557 0039E 8E96 mov a,DAY ;[INF] 2, 1 + 1558 1558 003A0 RFD0000 call !@@bcdtob ;[INF] 3, 3 + 1559 1559 003A3 9C01 mov [hl+1],a ; day_hex ;[INF] 2, 1 + 1560 1560 ; line 391 : hour_hex = bcdtob( HOUR ); + 1561 1561 $DGL 0,11 + 1562 1562 003A5 8E94 mov a,HOUR ;[INF] 2, 1 + 1563 1563 003A7 RFD0000 call !@@bcdtob ;[INF] 3, 3 + 1564 1564 003AA 9B mov [hl],a ; hour_hex ;[INF] 1, 1 + 1565 1565 ; line 392 : + 1566 1566 ; line 393 : RWAIT = 0; + 1567 1567 $DGL 0,13 + 1568 1568 003AB 710B9E clr1 RTCC1.0 ;[INF] 3, 2 + 1569 1569 ; line 394 : EI(); + 1570 1570 $DGL 0,14 + 1571 1571 003AE 717AFA ei ;[INF] 3, 4 + 1572 1572 ; line 395 : + 1573 1573 ; line 396 : // まず日数の部分 + 1574 1574 ; line 397 : long_hour = DAYS_FROM_HNY[ month_hex ]; + 1575 1575 $DGL 0,17 + 1576 1576 003B1 8C02 mov a,[hl+2] ; month_hex ;[INF] 2, 1 + 1577 1577 003B3 F0 clrb x ;[INF] 1, 1 + 1578 1578 003B4 317E shrw ax,7 ;[INF] 2, 1 + 1579 1579 003B6 12 movw bc,ax ;[INF] 1, 1 + 1580 1580 003B7 R793000 movw ax,_DAYS_FROM_HNY[bc] ;[INF] 3, 1 + 1581 1581 003BA BC04 movw [hl+4],ax ; long_hour ;[INF] 2, 1 + 1582 1582 ; line 398 : if(( ( year_hex & 0x03 ) == 0 ) && ( ( 3 <= month_hex ) + 1583 1583 $DGL 0,18 + 1584 1584 003BC 8C03 mov a,[hl+3] ; year_hex ;[INF] 2, 1 + 1585 1585 003BE 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 1586 1586 003C0 D1 cmp0 a ;[INF] 1, 1 + 1587 1587 003C1 DF15 bnz $?L0093 ;[INF] 2, 4 + 1588 1588 003C3 8C02 mov a,[hl+2] ; month_hex ;[INF] 2, 1 + 1589 1589 003C5 4C03 cmp a,#03H ; 3 ;[INF] 2, 1 + 1590 1590 003C7 DE0C bnc $?L0095 ;[INF] 2, 4 + 1591 1591 ; line 399 : || (( 2 == month_hex ) + 1592 1592 ; && ( day_hex == 29 )) )) + 1593 1593 $DGL 0,19 + 1594 1594 003C9 8C02 mov a,[hl+2] ; month_hex ;[INF] 2, 1 + 1595 1595 003CB 4C02 cmp a,#02H ; 2 ;[INF] 2, 1 + 1596 1596 003CD DF09 bnz $?L0093 ;[INF] 2, 4 + 1597 1597 003CF 8C01 mov a,[hl+1] ; day_hex ;[INF] 2, 1 + 1598 1598 003D1 4C1D cmp a,#01DH ; 29 ;[INF] 2, 1 + 1599 1599 003D3 61F8 sknz ;[INF] 2, 1 + 1600 1600 003D5 ?L0095: + 1601 1601 ; line 400 : { + 1602 1602 003D5 ??bb00_get_long_hour: + 1603 1603 ; line 401 : // 閏年で、閏日より後 + 1604 1604 ; line 402 : long_hour += 1; + 1605 1605 $DGL 0,22 + 1606 1606 003D5 617904 incw [hl+4] ; long_hour ;[INF] 3, 2 + 1607 1607 003D8 ??eb00_get_long_hour: + 1608 1608 ; line 403 : } + 1609 1609 003D8 ?L0093: + 1610 1610 ; line 404 : long_hour += day_hex - 1; + 1611 1611 $DGL 0,24 + 1612 1612 003D8 8C01 mov a,[hl+1] ; day_hex ;[INF] 2, 1 + 1613 1613 003DA 318E shrw ax,8 ;[INF] 2, 1 + 1614 1614 003DC B1 decw ax ;[INF] 1, 1 + 1615 1615 003DD 610904 addw ax,[hl+4] ; long_hour ;[INF] 3, 1 + 1616 1616 003E0 BC04 movw [hl+4],ax ; long_hour ;[INF] 2, 1 + 1617 1617 ; line 405 : long_hour *= 24; // 日数→時間 + 1618 1618 $DGL 0,25 + 1619 1619 003E2 313D shlw ax,3 ;[INF] 2, 1 + 1620 1620 003E4 12 movw bc,ax ;[INF] 1, 1 + 1621 1621 003E5 01 addw ax,ax ;[INF] 1, 1 + 1622 1622 003E6 03 addw ax,bc ;[INF] 1, 1 + 1623 1623 003E7 BC04 movw [hl+4],ax ; long_hour ;[INF] 2, 1 + 1624 1624 ; line 406 : + 1625 1625 ; line 407 : long_hour += hour_hex; + 1626 1626 $DGL 0,27 + 1627 1627 003E9 8C04 mov a,[hl+4] ; long_hour ;[INF] 2, 1 + 1628 1628 003EB 0D add a,[hl] ; hour_hex ;[INF] 1, 1 + 1629 1629 003EC 70 mov x,a ;[INF] 1, 1 + 1630 1630 003ED 8C05 mov a,[hl+5] ; long_hour ;[INF] 2, 1 + 1631 1631 003EF 1C00 addc a,#00H ; 0 ;[INF] 2, 1 + 1632 1632 003F1 BC04 movw [hl+4],ax ; long_hour ;[INF] 2, 1 + 1633 1633 ; line 408 : + 1634 1634 ; line 409 : return( long_hour ); + 1635 1635 $DGL 0,29 + 1636 1636 003F3 12 movw bc,ax ;[INF] 1, 1 + 1637 1637 ; line 410 : } + 1638 1638 $DGL 0,30 + 1639 1639 003F4 ??ef_get_long_hour: + 1640 1640 003F4 1006 addw sp,#06H ;[INF] 2, 1 + 1641 1641 003F6 C6 pop hl ;[INF] 1, 1 + 1642 1642 003F7 D7 ret ;[INF] 1, 6 + 1643 1643 003F8 ??ee_get_long_hour: + 1644 1644 + 1645 1645 ----- @@CODEL CSEG + 1646 1646 + 1647 1647 ----- @@BASE CSEG BASE + 1648 1648 END + 1649 1649 + 1650 1650 + 1651 1651 ; *** Code Information *** + 1652 1652 ; + 1653 1653 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c + 1654 1654 ; + 1655 1655 ; $FUNC pedometer(30) + 1656 1656 ; void=(void) + 1657 1657 ; CODE SIZE= 447 bytes, CLOCK_SIZE= 435 clocks, STACK_SIZE= 50 bytes + 1658 1658 ; + 1659 1659 ; $CALL abs(51) + 1660 1660 ; bc=(int:ax) + 1661 1661 ; + 1662 1662 ; $CALL abs(52) + 1663 1663 ; bc=(int:ax) + 1664 1664 ; + 1665 1665 ; $CALL abs(53) + 1666 1666 ; bc=(int:ax) + 1667 1667 ; + 1668 1668 ; $CALL sqrt(60) + 1669 1669 ; bc,de=(double:ax,bc) + 1670 1670 ; + 1671 1671 ; $CALL hosu_increment(110) + 1672 1672 ; void=(void) + 1673 1673 ; + 1674 1674 ; $FUNC hosu_increment(183) + 1675 1675 ; void=(void) + 1676 1676 ; CODE SIZE= 213 bytes, CLOCK_SIZE= 166 clocks, STACK_SIZE= 12 bytes + 1677 1677 ; + 1678 1678 ; $CALL get_long_hour(214) + 1679 1679 ; bc=(void) + 1680 1680 ; + 1681 1681 ; $CALL fill_hosu_hist_hours(223) + 1682 1682 ; void=(unsigned short:ax) + 1683 1683 ; + 1684 1684 ; $CALL fill_hosu_hist_hours(230) + 1685 1685 ; void=(unsigned short:ax) + 1686 1686 ; + 1687 1687 ; $CALL fill_hosu_hist_hours(235) + 1688 1688 ; void=(unsigned short:ax) + 1689 1689 ; + 1690 1690 ; $FUNC fill_hosu_hist_hours(264) + 1691 1691 ; void=(unsigned short hours:ax) + 1692 1692 ; CODE SIZE= 30 bytes, CLOCK_SIZE= 31 clocks, STACK_SIZE= 2 bytes + 1693 1693 ; + 1694 1694 ; $FUNC clear_hosu_hist(287) + 1695 1695 ; void=(void) + 1696 1696 ; CODE SIZE= 29 bytes, CLOCK_SIZE= 26 clocks, STACK_SIZE= 2 bytes + 1697 1697 ; + 1698 1698 ; $FUNC hosu_read_end(310) + 1699 1699 ; void=(void) + 1700 1700 ; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes + 1701 1701 ; + 1702 1702 ; $FUNC hosu_read(320) + 1703 1703 ; bc=(void) + 1704 1704 ; CODE SIZE= 146 bytes, CLOCK_SIZE= 124 clocks, STACK_SIZE= 10 bytes + 1705 1705 ; + 1706 1706 ; $FUNC get_long_hour(381) + 1707 1707 ; bc=(void) + 1708 1708 ; CODE SIZE= 110 bytes, CLOCK_SIZE= 84 clocks, STACK_SIZE= 12 bytes + 1709 1709 + 1710 1710 ; Target chip : uPD79F0104 + 1711 1711 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.1 @@BITS +00000 0004AH @@CNST +00000 00008H @@R_INIT +00000 00008H @@INIT +00000 00096H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 003F8H ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/pedo_alg_thre_det2.rel b/branches/0.10(X3)/pedo_alg_thre_det2.rel new file mode 100644 index 0000000..27b1d08 Binary files /dev/null and b/branches/0.10(X3)/pedo_alg_thre_det2.rel differ diff --git a/branches/0.10(X3)/pedo_lpf_coeff.h b/branches/0.10(X3)/pedo_lpf_coeff.h new file mode 100644 index 0000000..f81d6c2 --- /dev/null +++ b/branches/0.10(X3)/pedo_lpf_coeff.h @@ -0,0 +1,84 @@ +#ifndef _pedo_coeff_h_ +#define _pedo_coeff_h_ + +// ========================================================= +#define TAP 64 +#define FIL_COEFF_QUANT 10 +const s8 lpf_coeff[]={ +/* +Window Function Algorithm LPF +Sampling Frequency = 100.0 +cutoff1 = 6.0000000 +Tap Count =64 +Kaiser Constant = 7.000000 +Quantized by 11 [bits] + */ +/* 0,// [0] + 0, + 0, + 0, + 0, + 0, + 0, + 0, +*/ + 1,// 8 + 2, + 2, + 3, + 3, + 2, + 0, + -2, + -5,// 16 + -9, + -13, + -16, + -16, + -13, + -6, + 4, + 18,// 24 + 37, + 56, + 77, + 95, + 110, + 119, + 122, + 119,// 32 + 110, + 95, + 77, + 56, + 37, + 18, + 4, + -6,// 40 + -13, + -16, + -16, + -13, + -9, + -5, + -2, + 0,// 48 + 2, + 3, + 3, + 2, + 2, + 1, +/* + 0, + 0,// 56 + 0, + 0, + 0, + 0, + 0, + 0, + 0 +*/ +}; +#endif diff --git a/branches/0.10(X3)/pedometer.h b/branches/0.10(X3)/pedometer.h new file mode 100644 index 0000000..1dd1d03 --- /dev/null +++ b/branches/0.10(X3)/pedometer.h @@ -0,0 +1,99 @@ +#ifndef _pedo_ +#define _pedo_ + + +void hosu_read_end( ); +u8 hosu_read( ); +void fill_hosu_hist_hours( u16 ); +void clear_hosu_hist(); + + +// ========================================================= +#define TAP 64 +#define FIL_COEFF_QUANT 10 +static const s8 lpf_coeff[]={ +/* +Window Function Algorithm LPF +Sampling Frequency = 100.0 +cutoff1 = 6.0000000 +Tap Count =64 +Kaiser Constant = 7.000000 +Quantized by 11 [bits] + */ +/* 0,// [0] + 0, + 0, + 0, + 0, + 0, + 0, + 0, +*/ + 1,// 8 + 2, + 2, + 3, + 3, + 2, + 0, + -2, + -5,// 16 + -9, + -13, + -16, + -16, + -13, + -6, + 4, + 18,// 24 + 37, + 56, + 77, + 95, + 110, + 119, + 122, + 119,// 32 + 110, + 95, + 77, + 56, + 37, + 18, + 4, + -6,// 40 + -13, + -16, + -16, + -13, + -9, + -5, + -2, + 0,// 48 + 2, + 3, + 3, + 2, + 2, + 1, +/* + 0, + 0,// 56 + 0, + 0, + 0, + 0, + 0, + 0, + 0 +*/ +}; +// */ + +// ========================================================= + +void pedometer(); +static void hosu_increment(); + + +#endif diff --git a/branches/0.10(X3)/pm.c b/branches/0.10(X3)/pm.c new file mode 100644 index 0000000..1cee974 --- /dev/null +++ b/branches/0.10(X3)/pm.c @@ -0,0 +1,930 @@ +/* ======================================================== + 対PMIC + 藤田＠開技 + nintendo + '08 Dec + ======================================================== */ +#pragma nop + +#include "incs.h" +#include "adc.h" +#include "led.h" +#include "pm.h" +#include "renge.h" + +#include "batt_params.h" + +#include +#include "fsl_user.h" +extern u16 pool[]; + +// ======================================================== + + +// ======================================================== +u8 raw_adc_temperature; +u8 rcomp; +float temp_co_up; +float temp_co_dn; + +// ======================================================== +static void PM_get_batt_left(); + + +/******************************************************//** + PMIC達の初期化 +\n 電池メーカー識別 +\n 電池残量ICのセット +\n バージョン情報の取得 +\n +\n 以下のピンは主にここで操作・監視されます。 +\n ・PM_BT_DET,_P + *********************************************************/ +#define swap_endian_16( x ) (unsigned int)( x << 8 | x >> 8 ) + +void PM_init( ) +{ + u8 temp; + u8 origParam[4]; + union{ + u16 _u16; // ↓でわかるように、little endian です。注意。 + struct{ + u8 lsb; + u8 msb; + }chars; + }dat_16; + + system_status.model = MODEL_JIKKI; + wait_ms( 150 ); + + // -1. なんかおかしい…　リセットをかけてみる + dat_16._u16 = swap_endian_16( 0x5400 ); // reset + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_COMMAND, 2, &dat_16 ); // こいつはNACKを返す + + // 0. バッテリ残量IC クイックスタート + dat_16._u16 = swap_endian_16( 0x4000 ); // quick start + if( iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_MODE, 2, &dat_16 ) != ERR_SUCCESS ) + { + vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; + system_status.model = MODEL_TS_BOARD; + } + else + { + // 1. ロック解除 + dat_16._u16 = swap_endian_16( 0x4057 ); // unlock key + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, &dat_16 ); + + // 2. 初期パラメータを一時保存 + iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, origParam ); + + // 3. 一時的にOCVを変更 + dat_16._u16 = swap_endian_16( 0xD4C0 ); // マジックナンバー的なもの。メーカー指定 + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &dat_16 ); + + // 4. 一時的にRCOMPを変更 + dat_16._u16 = swap_endian_16( 0xFF00 ); + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, &dat_16 ); + + // 電池メーカーの識別 + BT_DET_P = 1; + temp = ( u8 ) ( ( get_adc( ADC_SEL_BATT_DET ) >> 5 ) -1 ); // 識別値０の白箱の分、インデックス合わせ + BT_DET_P = 0; + + iic_mcu_set_wo_dma( ); + // 5.メーカー別パラメータのロード + switch ( temp ) + { + case( BT_VENDER_SHIROBAKO ): + system_status.model = MODEL_SHIROBAKO; + break; + + case( BT_VENDER_PANA ): + case( BT_VENDER_MAXELL ): + default: + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_BT_PARAM, 64, &BT_PARAM[0] ); + rcomp = BT_PANA_RCOMP; + temp_co_up = BT_PANA_TEMPCOUP; + temp_co_dn = BT_PANA_TEMPCODN; + break; + } + + // 6. 150ms以上待つ + wait_ms( 200 ); + + // 7. OCVに「とある値」を書く + dat_16._u16 = swap_endian_16( 0xD4C0 ); + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &dat_16 ); + + // 8. 150〜600ms待つ。600msは厳守 + wait_ms( 200 ); + + // 9. SOCを読む。ベリファイのため。 + temp = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC ); + + if( 0x6D == temp || temp == 0x6E || temp == 0x6F ){ + // カスタムモデル書き込みOK！ + }else{ + // 失敗だったらリトライするのか？ + } + + // 10.元のRCOMPとOCVを書き戻す + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, origParam ); + + // 11. ロック + dat_16._u16 = swap_endian_16( 0x0000 ); // lock key + iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, &dat_16 ); + + // おしまい // + } + + // 電池温度測定 + BT_TEMP_P = 1; // 電池温度監視スタート + raw_adc_temperature = get_adc( ADC_SEL_BATT_TEMP ); // 温度のtemp。 + renge_task_immed_add( PM_bt_temp_update ); + + // PMIC バージョン読み出し +// temp = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VER ); +// vreg_ctr[ VREG_C_PM_INFO ] = temp; +// デバッグ用は別にまとめた +} + + + + + + +/* ======================================================== + raw_adc_temperatureに入っている値を℃に変換するとともに、 + ・レジスタにセット + ・残量ICにセット + todo + ======================================================== */ +task_status_immed PM_bt_temp_update( ) +{ + static u8 count = 0; // たまにしか書きに行かない + + static u8 rawdat_old; + static s16 temperature; // todo + u16 newrcomp; + +/* + サーミスタ - 10kΩ分圧点の時、 + 常用温度では分圧比のカーブがほぼリニアで、 + 村田 T[℃] = 81.48 - 111.97 x ratio + TDK T = 81.406 - 111.81 x ratio +*/ + if( rawdat_old != raw_adc_temperature ){ + DBG_P_n = 1; + temperature = 81.45 - 111.9 * raw_adc_temperature/256.0; + vreg_ctr[VREG_C_BT_TEMP] = (u8)temperature; + DBG_P_n = 0; + } + + // 時々書きにゆく + if( count == 0 ) + { + DBG_P_n = 1; + if( vreg_ctr[VREG_C_BT_TEMP] > 20 ) + { + newrcomp = -( ( temperature - 20 ) * temp_co_up ); + } + else + { + newrcomp = -( ( temperature - 20 ) * temp_co_dn ); + } + newrcomp += rcomp; + + newrcomp = swap_endian_16( (u16)newrcomp ); + DBG_P_n = 0; + + if( iic_mcu_write + ( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, &newrcomp ) == ERR_SUCCESS ) + { + rawdat_old = raw_adc_temperature; + } + } + count += 1; + + return ( ERR_SUCCESS ); +} + + + +#ifdef _PMIC_TWL_ +u8 blset; +#endif + +#ifndef _PARRADIUM_ +/* ======================================================== + 液晶系の電源制御 + 　ステータスフラグはすぐに立ててしまう。 + 　不感応時間があるし、 + 起動失敗であれば電源が落ちる + 別のタスクで電源落ちは監視していて、ステータスもクリアする + ======================================================== */ +// BSR // +err PM_LCD_on( ) +{ + u8 rv; + + PM_VDDLCD_on( ); + + wait_ms( DELAY_PM_TSS_50B_AND_TCOM ); + + PM_TCOM_on( ); + + wait_ms( DELAY_PM_TCOM_TO_VCS ); + + PM_VCS_on( ); + + wait_ms( DELAY_PM_VCS_TO_BL ); +#ifdef _PM_BUG_ + iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0x4A ); // バグ持ちPMIC対策 +#endif + + rv = PM_chk_LDSW( ); + + if( rv != 0 ) + { + // 電源起動エラーなら電源も切れてしまう。ここではケアしない + vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; + set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); + + SND_DEPOP_DEACT; // 1でミュート + } + +#ifdef _PMIC_TWL_ + PM_TEG_LCD_dis( 0 ); + blset = ( PM_REG_BIT_BL_U | PM_REG_BIT_BL_L ); +#endif + return ( rv ); +} + +// BSR // +void PM_LCD_off() +{ + SND_DEPOP_ACT; + + // BLついてたら消す +#ifdef _PMIC_TWL_ + if( blset != 0 ) +#else + if( ( iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) & 0x03 ) != 0 ) +#endif + { + u8 tot; + + PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ); + vreg_ctr[VREG_C_STATUS] &= 0b10011111; + + if( (( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 ) + { + vreg_ctr[ VREG_C_IRQ3 ] |= ( ( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ); + IRQ0_neg; + tot = 0; + while( !IRQ0 && ( ++tot != 0 ) ){;} + IRQ0_ast; + } + vreg_ctr[VREG_C_COMMAND2] &= ~( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ); + } + +#ifdef _PMIC_TWL_ + PM_TEG_LCD_dis( 1 ); + blset = 0; +#endif + + PM_TCOM_VCS_off( ); + wait_ms( DELAY_PM_LCD_OFF ); + + PM_VDDLCD_off( ); // 残ってたの全部止めます。 + vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; + + + set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); +} + + + +/* ======================================================== +　バックライトの個別on/off +　現状から　on/off/維持　のフラグなので面倒 +　　例えば、BL on/on の状態で、on/onにしろと言われても、on/on割り込みを入れます。 +======================================================== */ +err PM_BL_set( u8 dat ) +{ +#ifndef _PMIC_TWL_ + u8 blset; +#endif + u8 intset = 0; + // RMWを行う + +#ifndef _PMIC_TWL_ + // Read + blset = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) ; +#endif + + // Modify + // ue + if(( dat & REG_BIT_CMD_BL_U_ON ) != 0 ) + { + blset |= PM_REG_BIT_BL_U; + intset |= REG_BIT_BL_U_ON; + } + else if(( dat & REG_BIT_CMD_BL_U_OFF ) != 0 ) + { + blset &= ~PM_REG_BIT_BL_U; + intset |= REG_BIT_BL_U_OFF; + } + + // shita + if(( dat & REG_BIT_CMD_BL_L_ON ) != 0 ) + { + blset |= PM_REG_BIT_BL_L; + intset |= REG_BIT_BL_L_ON; + } + else if(( dat & REG_BIT_CMD_BL_L_OFF ) != 0 ) + { + blset &= ~PM_REG_BIT_BL_L; + intset |= REG_BIT_BL_L_OFF; + } + +/* +SoCがPWMを出すようレジスタをセットしてから遅延が有るため、ステータスを先に +更新してしまう。 +// Write + iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); + if( blset != 0x00 ){ + wait_ms( 10 ); + } +*/ + vreg_ctr[VREG_C_STATUS] = (( vreg_ctr[VREG_C_STATUS] & 0b10011111 ) + | (( blset << 6 ) | ( blset << 4 )) & 0b01100000 ); + // PMICのBLのビットと、MCUのSTATUSレジスタのビット位置が逆なため入れ替え + + { + u8 tot; + + if( ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 ) + { + vreg_ctr[ VREG_C_IRQ3 ] |= ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ); + IRQ0_neg; + tot = 0; + while( !IRQ0 && ( ++tot != 0 ) ){;} // 割り込みを入れ直す + IRQ0_ast; + } + } + +// Write + if( blset != 0 ) // BLを付ける場合はウェイトを挟まないとPWMが来ておらず + /// シャットダウンすることがある + { + wait_ms( 10 ); + } + iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); + + return( ERR_SUCCESS ); // ここでは異常チェック不要 +} + + + +/* ======================================================== + 液晶の対向電圧の設定を行います。 + 仮想レジスタの内容を送るだけ + ======================================================== */ +err PM_LCD_vcom_set( ) +{ + u8 rv; + + rv = iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC1, vreg_ctr[VREG_C_VCOM_T] ); // がっかりなことに、PMICはバースト書き込み不可 + rv |= iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC2, vreg_ctr[VREG_C_VCOM_B] ); + return ( rv ); +} + + + +#else +// パラディウム上のSoCでチェックしたいとき、PMICも液晶もつながってないので +// 異常終了しないようにダミー関数にする +err PM_LCD_on( ) +{ + vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; + set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); + SND_DEPOP_DEACT; // 1でミュート + return ( ERR_SUCCESS ); +} + + +void PM_LCD_off( ) +{ + SND_DEPOP_ACT; + vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; + set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); +} + + +err PM_BL_set( u8 ) +{ + wait_ms( 10 ); + vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & ~( REG_BIT_BL_U | REG_BIT_BL_L ) + | ( command_bl_set & REG_BIT_CMD_BL_U_ON )? REG_BIT_BL_U + | ( command_bl_set & REG_BIT_CMD_BL_L_ON )? REG_BIT_BL_L + ); + return ( PM_chk_LDSW( ) ); +} + + +err PM_LCD_vcom_set( ) +{ + return ( ERR_SUCCESS ); +} + +#endif + + + +/* ======================================================== + ↑で、レジスタ書き込みから呼び出される時のため + 　I2Cの取り合いの関係でここから呼ぶ + ======================================================== */ +task_status_immed tski_vcom_set( ) +{ + PM_LCD_vcom_set( ); + return ( ERR_FINISED ); +} + + + +/* ======================================================== + シーケンスの通り電源を立ち上げてゆきます。 + 返値 0 最後まで正常に完了した。 + 1 ショートなどで電源があがりきらなかった + + 以下のピンは主にここで操作・監視されます。 + ・POW_CONT1,2 TEG電源のみ + ======================================================== */ +err PM_sys_pow_on( ) +{ +#ifdef _PMIC_CTR_ + u8 temp; + + // 電池温度測定 + while( ADCEN != 0 ) + {; + } + BT_TEMP_P = 1; + vreg_ctr[VREG_C_BT_TEMP] = get_adc( ADC_SEL_BATT_TEMP ); + BT_TEMP_P = 0; + PM_bt_temp_update( ); // 温度のtemp。　残量ICに行きます + + // 残量チェック + PM_get_batt_left(); // 先に、PM_init()が実行されている必要があります。(大丈夫) + // todo: batt remain -> volatage? + if( vreg_ctr[VREG_C_BT_REMAIN] < 0 ) + { + return ( 1 ); + } + + // 電源順次立ち上げ +// PM_reset_ast( ); 不要 PM_LDSW_onまかせ + RESET2_ast; + FCRAM_RST_ast; + + PM_LDSW_on( ); + + wait_ms( 1 ); +#ifdef _PM_BUG_ + iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0xCA ); // バグ持ちPMIC対策 OVP解除 +#endif + + wait_ms( DELAY_PM_TW_PWUP ); + + PM_VDD_on( ); + wait_ms( DELAY_PM_TW_PWUP ); + + PM_VDD50A_on( ); // 液晶電源ではなく、ledとかに使うものです + + wait_ms( DELAY_PM_TW_PWUP ); + + PM_VDD_normMode(); +#ifdef _PM_BUG_ + iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, 0x03 ); // バグ持ちPMIC対策 強制PWM +#endif + if( PM_chk_LDSW( ) == 0 ) + { + return ( ERR_ERR ); + } + FCRAM_RST_neg; + PM_reset_neg(); + RESET2_neg; +/* + wait_ms( 100 ); + { + // CODEC 不定レジスタ初期化 + u8 codec_reg_init[3] = { 0,0,0 }; + iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg_init ); + } +*/ + +#else + // TWL PMIC + u8 temp; + + // 電源投入 + PM_reset_ast(); + RESET2_ast; + FCRAM_RST_ast; + + PM_TEG_PWSW = 1; + wait_ms( 160 ); + PM_TEG_PWSW = 0; + + + // 残量確認 + temp = 99; + if( temp < 5 ) + { + return ( ERR_ERR ); + } + vreg_ctr[VREG_C_BT_REMAIN] = temp; + FCRAM_RST_neg; + PM_reset_neg(); + RESET2_neg; + wait_ms( 100 ); + if( !RESET1_n ) + { + // 起動失敗 + PM_reset_ast(); + RESET2_ast; + FCRAM_RST_ast; + return ( ERR_ERR ); + } +/* + { // CODEC 不定レジスタ初期化 + u8 codec_reg_init[3] = { 0,0,0 }; + iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg_init ); + } +*/ +#endif + + return ( ERR_SUCCESS ); +} + + + + + + + +/* ======================================================== + 電源OFFシーケンス + todo: 電源異常断の場合 + ======================================================== */ +err PM_sys_pow_off( ) +{ +#ifdef _PMIC_CTR_ +// PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ); +// PM_LCD_off( ); // TCOM,VCS OFF も消してきます。 + + PM_reset_ast( ); + RESET2_ast; + FCRAM_RST_ast; + + PM_off( ); + + PM_LDSW_off( ); +#else + + if( RESET1_n ) + { + PM_reset_ast(); + RESET2_ast; + FCRAM_RST_ast; + PM_TEG_PWSW = 1; + wait_ms( 250 ); + wait_ms( 250 ); + wait_ms( 250 ); + PM_TEG_PWSW = 0; + } + PM_reset_ast(); + RESET2_ast; + FCRAM_RST_ast; + +#endif + return ( ERR_SUCCESS ); +} + + + +/* ======================================================== + 電池の管理 + + 以下のピンは主にここで操作・監視されます。 + ・PM_BT_AUTH 現状、GPI in + ・PM_CHARGE_n CCIC /CHG in + ・PM_CHARGE_ERR_n /FLT in + ・PM_EXTDC_n /DOK INTP4 in + ・PM_CHARGE_EN_n /CEN out + + 以下の物は関係ありそうですが別のところで主に監視されています。 + ・LED_Pow R, B, Charge tsk_LED + ・BT_TEMP,_P tsk_ADC + + PM_EXTDCは割り込みメインにするかも + ======================================================== */ +#define INTERVAL_TSK_BATT 250 + +void tsk_batt( ) +{ + static u8 task_interval = 0; + static u8 charge_hys = 0; // ヒステリシスで上限下限を拡張するとき１ + static bit pm_extdc_old; + + if( task_interval-- != 0 ) + { + return; + } + else + { + task_interval = (u8)( INTERVAL_TSK_BATT / SYS_INTERVAL_TICK ); + } + + + // アダプタ？ // + if( pm_extdc_old != !PM_EXTDC_n ) + { + pm_extdc_old = !PM_EXTDC_n; + if( pm_extdc_old ) + { + set_bit( 1, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUPPLY ); + set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_CONNECT ); + } + else + { + set_bit( 0, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUPPLY ); + set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_DISC ); + } + } + + + // 充電 /////////////////////////// + // 温度付きヒステリシス + if( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) + { + charge_hys = 1; + } + + if( ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) + && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) + { + charge_hys = 0; + } + + if( ( ( charge_hys == 1 ) + && ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) + && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) + || + ( ( charge_hys == 0 ) + && ( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) ) ) + { +#ifndef _MODEL_WM0_ + BT_CHG_ENABLE(); // 温度範囲OKで充電再開 + } + else + { + BT_CHG_DISABLE(); // 温度危険！　充電停止 +#endif + } +#ifdef _MODEL_WM0_ +// CHG_ENABLEピンは /WL_RST に配線されているので +#endif + + // 充電 // + // →割り込み。miscの中でよろしくやってくれている。 + set_bit( !BT_CHG_n, vreg_ctr[VREG_C_STATUS], REG_BIT_BATT_CHARGE ); + LED_CHARGE = !BT_CHG_n ? 1 : 0; + + + // 電池残量 // + PM_get_batt_left(); + + // dubug monitor + + return; +} + + + + +/*========================================================= + extDC割り込み + 電源OFFから起こす（充電の温度監視のため）のみ + 普段はポーリング(pm) + =========================================================*/ +__interrupt void intp4_extdc( ) +{ + ; +} + + + +/*========================================================= + フタ開け閉め割り込み + 普段はポーング(misc) + =========================================================*/ +__interrupt void intp5_shell( ) +{ + ; +} + + +/*========================================================= + 旧PMICへのコマンド書き込み + =========================================================*/ +__interrupt void intp6_PM_irq( ) +{ + if( system_status.pwr_state == ON ) + { + EI(); + renge_task_immed_add( ntr_pmic_comm ); + } +} + + + +extern u8 temp_debug_3; + +/* ======================================================== + PMICからの割り込みを受けて、NTR PMIC互換レジスタからリード + ======================================================== */ +task_status_immed ntr_pmic_comm( ) +{ + static u8 reg_shadow; + u8 reg1_old; + u8 irq_work = 0; + + reg1_old = reg_shadow; + reg_shadow = iic_mcu_read_a_byte( IIC_SLA_CODEC, CODEC_REG_PM ); + if( iic_mcu_bus_status != ERR_SUCCESS ) + { + return ( ERR_FINISED ); + } + + DI( ); + + // バックライト 上 //////////////////////////////////// + if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_U ) != 0 ) + { + if( ( reg_shadow & REG_BIT_TWL_REQ_BL_U ) == 0 ) // 消えた + { +// irq_work = REG_BIT_TWL_BL_U_OFF; + set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_OFF ); + } + else + { +// irq_work = REG_BIT_TWL_BL_U_ON; + set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_ON ); + } + } + + // バックライト 下 + if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_L ) != 0 ) + { + if( ( reg_shadow & REG_BIT_TWL_REQ_BL_L ) == 0 ) // 消えた + { +// irq_work = REG_BIT_TWL_BL_L_OFF; + set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_OFF ); + } + else + { +// irq_work = REG_BIT_TWL_BL_L_ON; + set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_ON ); + } + } + +#if 0 + irq_work &= ~VREG_C_IRQ_MASK2; + // set_irq 相当品 + if( irq_work != 0 ) + { + u8 tot; + + DI(); + vreg_ctr[ VREG_C_IRQ2 ] |= irq_work; + EI(); + IRQ0_neg; // 一瞬上げてパルスを送り直す + tot = 0; + while( !IRQ0 && ( ++tot != 0 ) ){;} // O.Dなのでちゃんとあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) + IRQ0_ast; + } +#endif + +#if 0 + // バックライト設定 + // 勝手に消しておく + /// 今のところさらに細かくは分けないけど… + if( ( reg_shadow & ( REG_BIT_TWL_REQ_BL_U | REG_BIT_TWL_REQ_BL_U ) ) == 0 ) + { + vreg_ctr[ VREG_C_COMMAND2 ] = ( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_U_OFF ); + renge_task_immed_add( tski_PM_BL_set ); + } +#endif + + // offリクエスト ////////////////////////////////////// + if( ( reg_shadow & REG_BIT_TWL_REQ_OFF_REQ ) != 0 ) + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); + } + + // リセットリクエスト ///////////////////////////////// + if( ( reg_shadow & REG_BIT_TWL_REQ_RST_REQ ) != 0 ) + { + // CODECバグ回避 + // リセット単品でなかったら無視 +// codec 修正済↓ +// if( ( reg1_old ^ reg_shadow ) == REG_BIT_TWL_REQ_RST_REQ ) + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); + } + } + + // バックライトをマスクして書き戻す + EI( ); + if( ( reg_shadow & ( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_REQ_RST_REQ )) != 0 ) + { + reg_shadow &= ~( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_REQ_RST_REQ ); + iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_PM, reg_shadow ); + } + return ( ERR_FINISED ); +} + + + +/********************************************************** + 電池残量ICから残量を取得し、レジスタに書き込む。 + 　電池残量ICが無い・故障などの時はとりあえず残量99%とする。 + 　　　　　　　　↑は status_1で確認可能。電源投入時にチェックしています。 + 　PM_init()が実行されている必要があります。 +**********************************************************/ +static void PM_get_batt_left(){ + if(( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_GASGAUGE_ERR ) == 0 ) + { + // 電池残量の取得 + { + u8 temp[2]; + + iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC, 2, temp ); + + vreg_ctr[ VREG_C_BT_REMAIN ] = temp[0]; + vreg_ctr[ VREG_C_BT_REMAIN_FINE ] = temp[1]; + // todo 閾値を超えたら割り込み + } + + vreg_ctr[ VREG_C_BT_VOLTAGE ] = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_VCELL ); + } + else + { + vreg_ctr[ VREG_C_BT_REMAIN ] = 99; + } + + // PMIC-NTRに電池残量を教えてあげる + iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_BT, + ( vreg_ctr[ VREG_C_BT_REMAIN ] < 5 )? 1 : 0 ); // 1で電池切れ + +} + + + + + +/********************************************************** + command2 液晶系 +　 ラッパー的な物。ERR_SUCCESSしか返さないが… +**********************************************************/ +task_status_immed tski_PM_LCD_on() +{ + PM_LCD_on(); + return( ERR_SUCCESS ); +} + +task_status_immed tski_PM_LCD_off() +{ + PM_LCD_off(); + return( ERR_SUCCESS ); +} + +task_status_immed tski_PM_BL_set() +{ + u8 cmd_BL; // ↓volatileとか付けなくても大丈夫みたい + + do + { + cmd_BL = vreg_ctr[VREG_C_COMMAND2]; + PM_BL_set( cmd_BL ); // マスク済み + } + while( cmd_BL != vreg_ctr[VREG_C_COMMAND2] ); + vreg_ctr[VREG_C_COMMAND2] = 0; + + return( ERR_SUCCESS ); +} + + diff --git a/branches/0.10(X3)/pm.h b/branches/0.10(X3)/pm.h new file mode 100644 index 0000000..c6a68a8 --- /dev/null +++ b/branches/0.10(X3)/pm.h @@ -0,0 +1,177 @@ +#ifndef __PM__ +#define __PM__ + + +#define IIC_SLA_PMIC 0x84 +#define IIC_SLA_BT_GAUGE 0x6C + +#define VCOM_DEFAULT_T 92 +#define VCOM_DEFAULT_B 95 + +//========================================================= +enum PMIC_REG_ADRS +{ + PM_REG_ADRS_VER = 0x00, // verinfo など + PM_REG_ADRS_VDD_SYS, // システムが使用する電源 + PM_REG_ADRS_VDD_LCD, // 液晶電源 + PM_REG_ADRS_CONT, // /RESET1, LoadSwitch + PM_REG_ADRS_BL, // バックライト on/off + PM_REG_ADRS_POW_SAVE, // 省電力設定 + PM_REG_ADRS_POW_DAC1, + PM_REG_ADRS_POW_DAC2 +}; + +enum BT_GAUGE_REG_ADRS +{ + BT_GAUGE_REG_VCELL = 0x02, // それぞれ16ビットのため + BT_GAUGE_REG_SOC = 0x04, + BT_GAUGE_REG_MODE = 0x06, + BT_GAUGE_REG_VERSION = 0x08, + BT_GAUGE_REG_OCV = 0x0E, + BT_GAUGE_REG_RCOMP = 0x0C, + BT_GAUGE_REG_LOCK = 0x3E, + BT_GAUGE_REG_BT_PARAM = 0x40, + BT_GAUGE_REG_COMMAND = 0xFE +}; + +enum BT_VENDER +{ + BT_VENDER_SHIROBAKO = 0, + BT_VENDER_PANA = 3, + BT_VENDER_MAXELL = 7 +}; + + +//========================================================= +// CODEC上のPMIC互換レジスタ +#define CODEC_REG_PM 0x10 +#define CODEC_REG_BL 0x11 +#define CODEC_REG_BT 0x12 +//#define CODEC_REG_VOL 0x13 // ...都合により、adc.hで定義 + +// TWLがSPIでPMICに投げたコマンド +#define REG_BIT_TWL_REQ_OFF_REQ ( 1 << 6 ) +#define REG_BIT_TWL_REQ_RST_REQ ( 1 << 0 ) +#define REG_BIT_TWL_REQ_BL ( 3 << 2 ) + + + + +// 0x03 pw cnt3 +#define PM_REG_BIT_LDSW ( 1 << 0 ) +#define PM_REG_BIT_nRST1 ( 1 << 1 ) + +// 0x01 pw cnt1 +#define PM_REG_BIT_VDD 0x0F +#define PM_REG_BIT_VDD50A ( 1 << 4 ) + +// 0x02 pw cnt2 +#define PM_REG_BIT_VDDLCD 0x07 +#define PM_REG_BIT_LCD_VCS ( 0x01 << 4 ) +#define PM_REG_BIT_LCD_TCOM ( 0x01 << 3 ) + +// 0x04 bl cnt +#define PM_REG_BIT_BL_U 0x01 +#define PM_REG_BIT_BL_L 0x02 + + +// 0x05 pow save +#define PM_REG_BIT_VDD1P_1R15 0b00000000 +#define PM_REG_BIT_VDD1P_1R05 0b00001000 +#define PM_REG_BIT_VDD1P_0R90 0b00100000 +#define PM_REG_BIT_VDD_AUTO 0b00000111 +#define PM_REG_BIT_VDD_PWM 0b00000000 + + +#define DELAY_PM_TW_PWUP 16 +#define DELAY_PM_TSS_50B_AND_TCOM 17 +#define DELAY_PM_5V_TO_TCOM 17 +#define DELAY_PM_TCOM_TO_VCS 3 +#define DELAY_PM_VCS_TO_BL ( 17 + 5 ) +#define DELAY_PM_LCD_OFF ( 50 + 1 ) + + +//========================================================= +extern u8 raw_adc_temperature; + + +//========================================================= +err PM_sys_pow_on( ); +err PM_sys_pow_off( ); +err PM_bt_auth( ); +void PM_init( ); +err PM_LCD_vcom_set( ); + +err PM_LCD_on( ); +void PM_LCD_off( ); +err PM_BL_set( u8 ); + +task_status_immed PM_bt_temp_update( ); +task_status_immed tski_vcom_set( ); +task_status_immed tski_PM_LCD_on(); +task_status_immed tski_PM_LCD_off(); +task_status_immed tski_PM_BL_set(); + + +// 　これを呼ぶ前に、現在温度を教えておく必要があります。 +#define PM_reset() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT, 0x00 ) ) + + +//========================================================= + + +// 元栓 // +#define PM_LDSW_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT, PM_REG_BIT_LDSW )) +#define PM_LDSW_off() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT, 0 )) + + +// システム電源 // +#define PM_VDD_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_SYS, PM_REG_BIT_VDD )) +#define PM_VDD50A_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_SYS, ( PM_REG_BIT_VDD | PM_REG_BIT_VDD50A ))) +#define PM_VDD_off() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_SYS, 0 )) +#define PM_off() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_SYS, 0 )) + +#ifdef _MODEL_CTR_ +#define PM_VDD_normMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_1R15 | PM_REG_BIT_VDD_PWM )) +#define PM_VDD_ecoMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_0R90 | PM_REG_BIT_VDD_AUTO )) + +#else +// 本番チップ待ち +#ifdef _PM_BUG_ +#define PM_VDD_ecoMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_0R90 | PM_REG_BIT_VDD_AUTO )) +#define PM_VDD_normMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_1R10 | PM_REG_BIT_VDD_PWM )) + +#else +#define PM_VDD_ecoMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_1R05 | PM_REG_BIT_VDD_AUTO )) +#define PM_VDD_normMode() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_1R05 | PM_REG_BIT_VDD_PWM )) + +#endif +#endif + +// ほか // +#ifdef _PMIC_TWL_ +#define PM_reset_neg() { PM0.0 = 1; } +#define PM_reset_ast() { P0.0 = 0; PM0.0 = 0; } +#define PM_chk_LDSW() ( 1 ) +#else + +#define PM_reset_neg() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT, ( PM_REG_BIT_LDSW | PM_REG_BIT_nRST1 ))) +#define PM_reset_ast() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT, ( PM_REG_BIT_LDSW ))) +#define PM_chk_LDSW() ( iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_CONT ) & PM_REG_BIT_LDSW ) +// ↑ 0 だと異常 +#endif + + +// 液晶系電源 // +#define PM_VDDLCD_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_LCD, PM_REG_BIT_VDDLCD )) +#define PM_TCOM_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_LCD, ( PM_REG_BIT_VDDLCD | PM_REG_BIT_LCD_TCOM ))) +#define PM_VCS_on() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_LCD, ( PM_REG_BIT_VDDLCD | PM_REG_BIT_LCD_VCS | PM_REG_BIT_LCD_TCOM ))) +#define PM_TCOM_VCS_off() PM_VDDLCD_on() +#define PM_VDDLCD_off() ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VDD_LCD, 0 ) ) + +#define PM_set_BL( dat ) ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, dat ) ) +#define PM_set_adc1( dat ) ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC1, dat ) ) +#define PM_set_adc2( dat ) ( iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC2, dat ) ) + + +#endif // __PM__ diff --git a/branches/0.10(X3)/pm.prn b/branches/0.10(X3)/pm.prn new file mode 100644 index 0000000..08a256d --- /dev/null +++ b/branches/0.10(X3)/pm.prn @@ -0,0 +1,4013 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\pm.asm +Para-file: +In-file: inter_asm\pm.asm +Obj-file: pm.rel +Prn-file: pm.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no pm.c + 6 6 ; In-file : pm.c + 7 7 ; Asm-file : inter_asm\pm.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0217H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, pm.c + 18 18 $DGS MOD_NAM, pm, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 82 82 $DGS AUX_TAG, 01H, 06DH + 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 86 86 $DGS AUX_EOS, 041H, 01H + 87 87 $DGS LAB_SYM, bs_F0153, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_F0153, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS LAB_SYM, bs_F0154, U, U, 00H, 06H, 00H, 00H + 90 90 $DGS LAB_SYM, es_F0154, U, U, 00H, 06H, 00H, 00H + 91 91 $DGS LAB_SYM, bs_F0155, U, U, 00H, 06H, 00H, 00H + 92 92 $DGS LAB_SYM, es_F0155, U, U, 00H, 06H, 00H, 00H + 93 93 $DGS LAB_SYM, bs_F0151, U, U, 00H, 06H, 00H, 00H + 94 94 $DGS LAB_SYM, es_F0151, U, U, 00H, 06H, 00H, 00H + 95 95 $DGS LAB_SYM, bs_S0152, U, U, 00H, 06H, 00H, 00H + 96 96 $DGS LAB_SYM, es_S0152, U, U, 00H, 06H, 00H, 00H + 97 97 $DGS LAB_SYM, bs_F0149, U, U, 00H, 06H, 00H, 00H + 98 98 $DGS LAB_SYM, es_F0149, U, U, 00H, 06H, 00H, 00H + 99 99 $DGS LAB_SYM, bs_F0150, U, U, 00H, 06H, 00H, 00H + 100 100 $DGS LAB_SYM, es_F0150, U, U, 00H, 06H, 00H, 00H + 101 101 $DGS LAB_SYM, bs_F0146, U, U, 00H, 06H, 00H, 00H + 102 102 $DGS LAB_SYM, es_F0146, U, U, 00H, 06H, 00H, 00H + 103 103 $DGS LAB_SYM, bs_F0147, U, U, 00H, 06H, 00H, 00H + 104 104 $DGS LAB_SYM, es_F0147, U, U, 00H, 06H, 00H, 00H + 105 105 $DGS LAB_SYM, bs_F0148, U, U, 00H, 06H, 00H, 00H + 106 106 $DGS LAB_SYM, es_F0148, U, U, 00H, 06H, 00H, 00H + 107 107 $DGS LAB_SYM, bs_S0144, U, U, 00H, 06H, 00H, 00H + 108 108 $DGS LAB_SYM, es_S0144, U, U, 00H, 06H, 00H, 00H + 109 109 $DGS LAB_SYM, bs_F0145, U, U, 00H, 06H, 00H, 00H + 110 110 $DGS LAB_SYM, es_F0145, U, U, 00H, 06H, 00H, 00H + 111 111 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 112 112 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 113 113 $DGS STA_SYM, _BT_PARAM, U, U, 0500CH, 03H, 01H, 0FH + 114 114 $DGS AUX_STR, 00H, 00H, 01C0H, 07H, 040H, 00H, 00H, 00H + 115 115 $DGS STA_SYM, _BT_PANA_RCOMP, U, U, 0500CH, 03H, 00H, 00H + 116 116 $DGS STA_SYM, _BT_PANA_TEMPCOUP, U, U, 05006H, 03H, 00H, 00H + 117 117 $DGS STA_SYM, _BT_PANA_TEMPCODN, U, U, 05006H, 03H, 00H, 00H + 118 118 $DGS GLV_SYM, _PM_init, U, U, 01H, 026H, 01H, 02H + 119 119 $DGS AUX_FUN, 00H, U, U, 09AH, 00H, 00H + 120 120 $DGS BEG_FUN, ??bf_PM_init, U, U, 00H, 065H, 01H, 00H + 121 121 $DGS AUX_BEG, 02EH, 08H, 07CH + 122 122 $DGS AUT_VAR, _temp, 07H, 0FFFFH, 0CH, 01H, 00H, 00H + 123 123 $DGS AUT_VAR, _origParam, 03H, 0FFFFH, 0CH, 01H, 01H, 03H + 124 124 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H + 125 125 $DGS STR_STR, .7fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 126 126 $DGS AUX_TAG, 02H, 073H + 127 127 $DGS MEB_STR, _lsb, 00H, 0FFFFH, 0CH, 08H, 00H, 00H + 128 128 $DGS MEB_STR, _msb, 01H, 0FFFFH, 0CH, 08H, 00H, 00H + 129 129 $DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H + 130 130 $DGS AUX_EOS, 06DH, 02H + 131 131 $DGS UNI_TAG, .6fake, 00H, 0FFFEH, 09H, 0CH, 01H, 00H + 132 132 $DGS AUX_TAG, 02H, 07AH + 133 133 $DGS MEB_UNI, __u16, 00H, 0FFFFH, 0DH, 0BH, 00H, 00H + 134 134 $DGS MEB_UNI, _chars, 00H, 0FFFFH, 08H, 0BH, 01H, 00H + 135 135 $DGS AUX_STR, 06DH, 00H, 02H, 00H, 00H, 00H, 00H, 00H + 136 136 $DGS END_STR, .eos, 02H, 0FFFFH, 00H, 066H, 01H, 00H + 137 137 $DGS AUX_EOS, 073H, 02H + 138 138 $DGS AUT_VAR, _dat_16, 00H, 0FFFFH, 09H, 01H, 01H, 00H + 139 139 $DGS AUX_STR, 073H, 00H, 02H, 00H, 00H, 00H, 00H, 00H + 140 140 $DGS BEG_BLK, ??bb00_PM_init, U, U, 00H, 064H, 01H, 00H + 141 141 $DGS AUX_BEG, 016H, 00H, 080H + 142 142 $DGS END_BLK, ??eb00_PM_init, U, U, 00H, 064H, 01H, 00H + 143 143 $DGS AUX_END, 019H + 144 144 $DGS BEG_BLK, ??bb01_PM_init, U, U, 00H, 064H, 01H, 00H + 145 145 $DGS AUX_BEG, 01BH, 00H, 082H + 146 146 $DGS BEG_BLK, ??bb02_PM_init, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_BEG, 030H, 00H, 084H + 148 148 $DGS BEG_BLK, ??bb03_PM_init, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_BEG, 030H, 00H, 08AH + 150 150 $DGS END_BLK, ??eb03_PM_init, U, U, 00H, 064H, 01H, 00H + 151 151 $DGS AUX_END, 030H + 152 152 $DGS END_BLK, ??eb02_PM_init, U, U, 00H, 064H, 01H, 00H + 153 153 $DGS AUX_END, 030H + 154 154 $DGS BEG_BLK, ??bb04_PM_init, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_BEG, 033H, 00H, 08EH + 156 156 $DGS END_BLK, ??eb04_PM_init, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_END, 040H + 158 158 $DGS BEG_BLK, ??bb05_PM_init, U, U, 00H, 064H, 01H, 00H + 159 159 $DGS AUX_BEG, 04FH, 00H, 092H + 160 160 $DGS END_BLK, ??eb05_PM_init, U, U, 00H, 064H, 01H, 00H + 161 161 $DGS AUX_END, 051H + 162 162 $DGS BEG_BLK, ??bb06_PM_init, U, U, 00H, 064H, 01H, 00H + 163 163 $DGS AUX_BEG, 051H, 00H, 00H + 164 164 $DGS END_BLK, ??eb06_PM_init, U, U, 00H, 064H, 01H, 00H + 165 165 $DGS AUX_END, 053H + 166 166 $DGS END_BLK, ??eb01_PM_init, U, U, 00H, 064H, 01H, 00H + 167 167 $DGS AUX_END, 05DH + 168 168 $DGS END_FUN, ??ef_PM_init, U, U, 00H, 065H, 01H, 00H + 169 169 $DGS AUX_END, 068H + 170 170 $DGS GLV_SYM, _PM_bt_temp_update, U, U, 0AH, 026H, 01H, 02H + 171 171 $DGS AUX_FUN, 041H, U, U, 0B8H, 00H, 00H + 172 172 $DGS BEG_FUN, ??bf_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H + 173 173 $DGS AUX_BEG, 0A3H, 02H, 0A2H + 174 174 $DGS STA_SYM, _count, ?L0018, U, 0CH, 03H, 00H, 00H + 175 175 $DGS STA_SYM, _rawdat_old, ?L0019, U, 0CH, 03H, 00H, 00H + 176 176 $DGS STA_SYM, _temperature, ?L0020, U, 03H, 03H, 00H, 00H + 177 177 $DGS AUT_VAR, _newrcomp, 00H, 0FFFFH, 0DH, 01H, 00H, 00H + 178 178 $DGS BEG_BLK, ??bb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_BEG, 0EH, 00H, 0A6H + 180 180 $DGS END_BLK, ??eb00_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_END, 013H + 182 182 $DGS BEG_BLK, ??bb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 183 183 $DGS AUX_BEG, 017H, 00H, 0A8H + 184 184 $DGS BEG_BLK, ??bb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 185 185 $DGS AUX_BEG, 01AH, 00H, 0ACH + 186 186 $DGS END_BLK, ??eb02_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 187 187 $DGS AUX_END, 01CH + 188 188 $DGS BEG_BLK, ??bb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 189 189 $DGS AUX_BEG, 01EH, 00H, 0B0H + 190 190 $DGS END_BLK, ??eb03_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_END, 020H + 192 192 $DGS BEG_BLK, ??bb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_BEG, 028H, 00H, 00H + 194 194 $DGS END_BLK, ??eb04_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_END, 02AH + 196 196 $DGS END_BLK, ??eb01_PM_bt_temp_update, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_END, 02BH + 198 198 $DGS END_FUN, ??ef_PM_bt_temp_update, U, U, 00H, 065H, 01H, 00H + 199 199 $DGS AUX_END, 02FH + 200 200 $DGS GLV_SYM, _PM_LCD_on, U, U, 0CH, 026H, 01H, 02H + 201 201 $DGS AUX_FUN, 00H, U, U, 0C3H, 00H, 00H + 202 202 $DGS BEG_FUN, ??bf_PM_LCD_on, U, U, 00H, 065H, 01H, 00H + 203 203 $DGS AUX_BEG, 0E3H, 02H, 0BDH + 204 204 $DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 205 205 $DGS BEG_BLK, ??bb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_BEG, 016H, 00H, 00H + 207 207 $DGS END_BLK, ??eb00_PM_LCD_on, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_END, 01CH + 209 209 $DGS END_FUN, ??ef_PM_LCD_on, U, U, 00H, 065H, 01H, 00H + 210 210 $DGS AUX_END, 023H + 211 211 $DGS GLV_SYM, _PM_LCD_off, U, U, 01H, 026H, 01H, 02H + 212 212 $DGS AUX_FUN, 00H, U, U, 0DFH, 00H, 00H + 213 213 $DGS BEG_FUN, ??bf_PM_LCD_off, U, U, 00H, 065H, 01H, 00H + 214 214 $DGS AUX_BEG, 0109H, 02H, 0C7H + 215 215 $DGS BEG_BLK, ??bb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 216 216 $DGS AUX_BEG, 0AH, 00H, 0CBH + 217 217 $DGS REG_VAR, _tot, 06H, 0FFFFH, 010CH, 04H, 01H, 00H + 218 218 $DGS AUX_STR, 00H, 0BH, 01H, 00H, 00H, 00H, 00H, 00H + 219 219 $DGS BEG_BLK, ??bb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 220 220 $DGS AUX_BEG, 011H, 00H, 0CDH + 221 221 $DGS BEG_BLK, ??bb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 222 222 $DGS AUX_BEG, 013H, 00H, 0D1H + 223 223 $DGS END_BLK, ??eb02_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 224 224 $DGS AUX_END, 013H + 225 225 $DGS BEG_BLK, ??bb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 226 226 $DGS AUX_BEG, 015H, 00H, 0D5H + 227 227 $DGS END_BLK, ??eb03_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 228 228 $DGS AUX_END, 015H + 229 229 $DGS BEG_BLK, ??bb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 230 230 $DGS AUX_BEG, 016H, 00H, 00H + 231 231 $DGS END_BLK, ??eb04_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 232 232 $DGS AUX_END, 016H + 233 233 $DGS END_BLK, ??eb01_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 234 234 $DGS AUX_END, 017H + 235 235 $DGS END_BLK, ??eb00_PM_LCD_off, U, U, 00H, 064H, 01H, 00H + 236 236 $DGS AUX_END, 019H + 237 237 $DGS END_FUN, ??ef_PM_LCD_off, U, U, 00H, 065H, 01H, 00H + 238 238 $DGS AUX_END, 028H + 239 239 $DGS GLV_SYM, _PM_BL_set, U, U, 0CH, 026H, 01H, 02H + 240 240 $DGS AUX_FUN, 00H, U, U, 0112H, 00H, 00H + 241 241 $DGS BEG_FUN, ??bf_PM_BL_set, U, U, 00H, 065H, 01H, 00H + 242 242 $DGS AUX_BEG, 013AH, 06H, 0E6H + 243 243 $DGS FUN_ARG, _dat, 04H, 0FFFFH, 0CH, 09H, 00H, 00H + 244 244 $DGS AUT_VAR, _blset, 03H, 0FFFFH, 0CH, 01H, 00H, 00H + 245 245 $DGS AUT_VAR, _intset, 02H, 0FFFFH, 0CH, 01H, 00H, 00H + 246 246 $DGS BEG_BLK, ??bb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 247 247 $DGS AUX_BEG, 010H, 00H, 0EAH + 248 248 $DGS END_BLK, ??eb00_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 249 249 $DGS AUX_END, 013H + 250 250 $DGS BEG_BLK, ??bb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 251 251 $DGS AUX_BEG, 015H, 00H, 0EEH + 252 252 $DGS END_BLK, ??eb01_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 253 253 $DGS AUX_END, 018H + 254 254 $DGS BEG_BLK, ??bb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 255 255 $DGS AUX_BEG, 01CH, 00H, 0F2H + 256 256 $DGS END_BLK, ??eb02_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 257 257 $DGS AUX_END, 01FH + 258 258 $DGS BEG_BLK, ??bb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 259 259 $DGS AUX_BEG, 021H, 00H, 0F6H + 260 260 $DGS END_BLK, ??eb03_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 261 261 $DGS AUX_END, 024H + 262 262 $DGS BEG_BLK, ??bb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 263 263 $DGS AUX_BEG, 033H, 00H, 0FAH + 264 264 $DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 01H, 00H + 265 265 $DGS AUX_STR, 00H, 034H, 01H, 00H, 00H, 00H, 00H, 00H + 266 266 $DGS BEG_BLK, ??bb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 267 267 $DGS AUX_BEG, 037H, 00H, 0FCH + 268 268 $DGS BEG_BLK, ??bb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 269 269 $DGS AUX_BEG, 039H, 00H, 0100H + 270 270 $DGS END_BLK, ??eb06_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 271 271 $DGS AUX_END, 039H + 272 272 $DGS BEG_BLK, ??bb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 273 273 $DGS AUX_BEG, 03BH, 00H, 0104H + 274 274 $DGS END_BLK, ??eb07_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 275 275 $DGS AUX_END, 03BH + 276 276 $DGS BEG_BLK, ??bb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 277 277 $DGS AUX_BEG, 03CH, 00H, 010CH + 278 278 $DGS END_BLK, ??eb08_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 279 279 $DGS AUX_END, 03CH + 280 280 $DGS END_BLK, ??eb05_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 281 281 $DGS AUX_END, 03DH + 282 282 $DGS END_BLK, ??eb04_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 283 283 $DGS AUX_END, 03EH + 284 284 $DGS BEG_BLK, ??bb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 285 285 $DGS AUX_BEG, 043H, 00H, 00H + 286 286 $DGS END_BLK, ??eb09_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 287 287 $DGS AUX_END, 045H + 288 288 $DGS END_FUN, ??ef_PM_BL_set, U, U, 00H, 065H, 01H, 00H + 289 289 $DGS AUX_END, 049H + 290 290 $DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 026H, 01H, 02H + 291 291 $DGS AUX_FUN, 00H, U, U, 0119H, 00H, 00H + 292 292 $DGS BEG_FUN, ??bf_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H + 293 293 $DGS AUX_BEG, 018BH, 02H, 0119H + 294 294 $DGS REG_VAR, _rv, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 295 295 $DGS END_FUN, ??ef_PM_LCD_vcom_set, U, U, 00H, 065H, 01H, 00H + 296 296 $DGS AUX_END, 07H + 297 297 $DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 026H, 01H, 02H + 298 298 $DGS AUX_FUN, 041H, U, U, 011FH, 00H, 00H + 299 299 $DGS BEG_FUN, ??bf_tski_vcom_set, U, U, 00H, 065H, 01H, 00H + 300 300 $DGS AUX_BEG, 01C2H, 00H, 011FH + 301 301 $DGS END_FUN, ??ef_tski_vcom_set, U, U, 00H, 065H, 01H, 00H + 302 302 $DGS AUX_END, 04H + 303 303 $DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 026H, 01H, 02H + 304 304 $DGS AUX_FUN, 00H, U, U, 0142H, 00H, 00H + 305 305 $DGS BEG_FUN, ??bf_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H + 306 306 $DGS AUX_BEG, 01D2H, 02H, 0124H + 307 307 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 308 308 $DGS BEG_BLK, ??bb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 309 309 $DGS AUX_BEG, 07H, 00H, 0128H + 310 310 $DGS END_BLK, ??eb00_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 311 311 $DGS AUX_END, 08H + 312 312 $DGS BEG_BLK, ??bb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 313 313 $DGS AUX_BEG, 012H, 00H, 012CH + 314 314 $DGS END_BLK, ??eb01_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 315 315 $DGS AUX_END, 014H + 316 316 $DGS BEG_BLK, ??bb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 317 317 $DGS AUX_BEG, 018H, 00H, 0130H + 318 318 $DGS END_BLK, ??eb02_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 319 319 $DGS AUX_END, 018H + 320 320 $DGS BEG_BLK, ??bb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 321 321 $DGS AUX_BEG, 019H, 00H, 0134H + 322 322 $DGS END_BLK, ??eb03_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 323 323 $DGS AUX_END, 019H + 324 324 $DGS BEG_BLK, ??bb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 325 325 $DGS AUX_BEG, 030H, 00H, 0138H + 326 326 $DGS END_BLK, ??eb04_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 327 327 $DGS AUX_END, 032H + 328 328 $DGS BEG_BLK, ??bb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 329 329 $DGS AUX_BEG, 033H, 00H, 013CH + 330 330 $DGS END_BLK, ??eb05_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 331 331 $DGS AUX_END, 033H + 332 332 $DGS BEG_BLK, ??bb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 333 333 $DGS AUX_BEG, 035H, 00H, 00H + 334 334 $DGS END_BLK, ??eb06_PM_sys_pow_on, U, U, 00H, 064H, 01H, 00H + 335 335 $DGS AUX_END, 035H + 336 336 $DGS END_FUN, ??ef_PM_sys_pow_on, U, U, 00H, 065H, 01H, 00H + 337 337 $DGS AUX_END, 069H + 338 338 $DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 026H, 01H, 02H + 339 339 $DGS AUX_FUN, 00H, U, U, 0150H, 00H, 00H + 340 340 $DGS BEG_FUN, ??bf_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H + 341 341 $DGS AUX_BEG, 0247H, 00H, 0146H + 342 342 $DGS BEG_BLK, ??bb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H + 343 343 $DGS AUX_BEG, 07H, 00H, 014AH + 344 344 $DGS END_BLK, ??eb00_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H + 345 345 $DGS AUX_END, 07H + 346 346 $DGS BEG_BLK, ??bb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H + 347 347 $DGS AUX_BEG, 08H, 00H, 00H + 348 348 $DGS END_BLK, ??eb01_PM_sys_pow_off, U, U, 00H, 064H, 01H, 00H + 349 349 $DGS AUX_END, 08H + 350 350 $DGS END_FUN, ??ef_PM_sys_pow_off, U, U, 00H, 065H, 01H, 00H + 351 351 $DGS AUX_END, 020H + 352 352 $DGS GLV_SYM, _tsk_batt, U, U, 01H, 026H, 01H, 02H + 353 353 $DGS AUX_FUN, 00H, U, U, 01A1H, 00H, 00H + 354 354 $DGS BEG_FUN, ??bf_tsk_batt, U, U, 00H, 065H, 01H, 00H + 355 355 $DGS AUX_BEG, 027DH, 00H, 0157H + 356 356 $DGS STA_SYM, _task_interval, ?L0077, U, 0CH, 03H, 00H, 00H + 357 357 $DGS STA_SYM, _charge_hys, ?L0078, U, 0CH, 03H, 00H, 00H + 358 358 $DGS STA_SYM, _pm_extdc_old, ?L0079, U, 034CH, 028H, 00H, 00H + 359 359 $DGS BEG_BLK, ??bb00_tsk_batt, U, U, 00H, 064H, 01H, 00H + 360 360 $DGS AUX_BEG, 07H, 00H, 015BH + 361 361 $DGS END_BLK, ??eb00_tsk_batt, U, U, 00H, 064H, 01H, 00H + 362 362 $DGS AUX_END, 09H + 363 363 $DGS BEG_BLK, ??bb01_tsk_batt, U, U, 00H, 064H, 01H, 00H + 364 364 $DGS AUX_BEG, 0BH, 00H, 015FH + 365 365 $DGS END_BLK, ??eb01_tsk_batt, U, U, 00H, 064H, 01H, 00H + 366 366 $DGS AUX_END, 0DH + 367 367 $DGS BEG_BLK, ??bb02_tsk_batt, U, U, 00H, 064H, 01H, 00H + 368 368 $DGS AUX_BEG, 012H, 00H, 0161H + 369 369 $DGS BEG_BLK, ??bb03_tsk_batt, U, U, 00H, 064H, 01H, 00H + 370 370 $DGS AUX_BEG, 015H, 00H, 0163H + 371 371 $DGS BEG_BLK, ??bb04_tsk_batt, U, U, 00H, 064H, 01H, 00H + 372 372 $DGS AUX_BEG, 016H, 00H, 0165H + 373 373 $DGS BEG_BLK, ??bb05_tsk_batt, U, U, 00H, 064H, 01H, 00H + 374 374 $DGS AUX_BEG, 016H, 00H, 0169H + 375 375 $DGS END_BLK, ??eb05_tsk_batt, U, U, 00H, 064H, 01H, 00H + 376 376 $DGS AUX_END, 016H + 377 377 $DGS BEG_BLK, ??bb06_tsk_batt, U, U, 00H, 064H, 01H, 00H + 378 378 $DGS AUX_BEG, 016H, 00H, 0171H + 379 379 $DGS END_BLK, ??eb06_tsk_batt, U, U, 00H, 064H, 01H, 00H + 380 380 $DGS AUX_END, 016H + 381 381 $DGS END_BLK, ??eb04_tsk_batt, U, U, 00H, 064H, 01H, 00H + 382 382 $DGS AUX_END, 016H + 383 383 $DGS END_BLK, ??eb03_tsk_batt, U, U, 00H, 064H, 01H, 00H + 384 384 $DGS AUX_END, 018H + 385 385 $DGS BEG_BLK, ??bb07_tsk_batt, U, U, 00H, 064H, 01H, 00H + 386 386 $DGS AUX_BEG, 01AH, 00H, 0173H + 387 387 $DGS BEG_BLK, ??bb08_tsk_batt, U, U, 00H, 064H, 01H, 00H + 388 388 $DGS AUX_BEG, 01BH, 00H, 0175H + 389 389 $DGS BEG_BLK, ??bb09_tsk_batt, U, U, 00H, 064H, 01H, 00H + 390 390 $DGS AUX_BEG, 01BH, 00H, 0179H + 391 391 $DGS END_BLK, ??eb09_tsk_batt, U, U, 00H, 064H, 01H, 00H + 392 392 $DGS AUX_END, 01BH + 393 393 $DGS BEG_BLK, ??bb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H + 394 394 $DGS AUX_BEG, 01BH, 00H, 0183H + 395 395 $DGS END_BLK, ??eb0A_tsk_batt, U, U, 00H, 064H, 01H, 00H + 396 396 $DGS AUX_END, 01BH + 397 397 $DGS END_BLK, ??eb08_tsk_batt, U, U, 00H, 064H, 01H, 00H + 398 398 $DGS AUX_END, 01BH + 399 399 $DGS END_BLK, ??eb07_tsk_batt, U, U, 00H, 064H, 01H, 00H + 400 400 $DGS AUX_END, 01DH + 401 401 $DGS END_BLK, ??eb02_tsk_batt, U, U, 00H, 064H, 01H, 00H + 402 402 $DGS AUX_END, 01EH + 403 403 $DGS BEG_BLK, ??bb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H + 404 404 $DGS AUX_BEG, 024H, 00H, 0187H + 405 405 $DGS END_BLK, ??eb0B_tsk_batt, U, U, 00H, 064H, 01H, 00H + 406 406 $DGS AUX_END, 026H + 407 407 $DGS BEG_BLK, ??bb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H + 408 408 $DGS AUX_BEG, 02AH, 00H, 018BH + 409 409 $DGS END_BLK, ??eb0C_tsk_batt, U, U, 00H, 064H, 01H, 00H + 410 410 $DGS AUX_END, 02CH + 411 411 $DGS BEG_BLK, ??bb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H + 412 412 $DGS AUX_BEG, 034H, 00H, 018FH + 413 413 $DGS END_BLK, ??eb0D_tsk_batt, U, U, 00H, 064H, 01H, 00H + 414 414 $DGS AUX_END, 037H + 415 415 $DGS BEG_BLK, ??bb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H + 416 416 $DGS AUX_BEG, 039H, 00H, 0193H + 417 417 $DGS END_BLK, ??eb0E_tsk_batt, U, U, 00H, 064H, 01H, 00H + 418 418 $DGS AUX_END, 03CH + 419 419 $DGS BEG_BLK, ??bb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H + 420 420 $DGS AUX_BEG, 043H, 00H, 0195H + 421 421 $DGS BEG_BLK, ??bb10_tsk_batt, U, U, 00H, 064H, 01H, 00H + 422 422 $DGS AUX_BEG, 043H, 00H, 0199H + 423 423 $DGS END_BLK, ??eb10_tsk_batt, U, U, 00H, 064H, 01H, 00H + 424 424 $DGS AUX_END, 043H + 425 425 $DGS BEG_BLK, ??bb11_tsk_batt, U, U, 00H, 064H, 01H, 00H + 426 426 $DGS AUX_BEG, 043H, 00H, 00H + 427 427 $DGS END_BLK, ??eb11_tsk_batt, U, U, 00H, 064H, 01H, 00H + 428 428 $DGS AUX_END, 043H + 429 429 $DGS END_BLK, ??eb0F_tsk_batt, U, U, 00H, 064H, 01H, 00H + 430 430 $DGS AUX_END, 043H + 431 431 $DGS END_FUN, ??ef_tsk_batt, U, U, 00H, 065H, 01H, 00H + 432 432 $DGS AUX_END, 04DH + 433 433 $DGS GLV_SYM, _intp4_extdc, U, U, 0E001H, 026H, 01H, 02H + 434 434 $DGS AUX_FUN, 00H, U, U, 01A7H, 00H, 00H + 435 435 $DGS BEG_FUN, ??bf_intp4_extdc, U, U, 00H, 065H, 01H, 00H + 436 436 $DGS AUX_BEG, 02D4H, 00H, 01A7H + 437 437 $DGS END_FUN, ??ef_intp4_extdc, U, U, 00H, 065H, 01H, 00H + 438 438 $DGS AUX_END, 03H + 439 439 $DGS GLV_SYM, _intp5_shell, U, U, 0E001H, 026H, 01H, 02H + 440 440 $DGS AUX_FUN, 00H, U, U, 01ADH, 00H, 00H + 441 441 $DGS BEG_FUN, ??bf_intp5_shell, U, U, 00H, 065H, 01H, 00H + 442 442 $DGS AUX_BEG, 02DFH, 00H, 01ADH + 443 443 $DGS END_FUN, ??ef_intp5_shell, U, U, 00H, 065H, 01H, 00H + 444 444 $DGS AUX_END, 03H + 445 445 $DGS GLV_SYM, _intp6_PM_irq, U, U, 0E001H, 026H, 01H, 02H + 446 446 $DGS AUX_FUN, 00H, U, U, 01B7H, 00H, 00H + 447 447 $DGS BEG_FUN, ??bf_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H + 448 448 $DGS AUX_BEG, 02E8H, 016H, 01B1H + 449 449 $DGS BEG_BLK, ??bb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H + 450 450 $DGS AUX_BEG, 03H, 00H, 00H + 451 451 $DGS END_BLK, ??eb00_intp6_PM_irq, U, U, 00H, 064H, 01H, 00H + 452 452 $DGS AUX_END, 06H + 453 453 $DGS END_FUN, ??ef_intp6_PM_irq, U, U, 00H, 065H, 01H, 00H + 454 454 $DGS AUX_END, 07H + 455 455 $DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 026H, 01H, 02H + 456 456 $DGS AUX_FUN, 041H, U, U, 01ECH, 00H, 00H + 457 457 $DGS BEG_FUN, ??bf_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H + 458 458 $DGS AUX_BEG, 02F8H, 02H, 01BEH + 459 459 $DGS STA_SYM, _reg_shadow, ?L0112, U, 0CH, 03H, 00H, 00H + 460 460 $DGS REG_VAR, _reg1_old, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 461 461 $DGS REG_VAR, _irq_work, 07H, 0FFFFH, 010CH, 04H, 00H, 00H + 462 462 $DGS BEG_BLK, ??bb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 463 463 $DGS AUX_BEG, 09H, 00H, 01C2H + 464 464 $DGS END_BLK, ??eb00_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 465 465 $DGS AUX_END, 0BH + 466 466 $DGS BEG_BLK, ??bb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 467 467 $DGS AUX_BEG, 011H, 00H, 01C4H + 468 468 $DGS BEG_BLK, ??bb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 469 469 $DGS AUX_BEG, 013H, 00H, 01C8H + 470 470 $DGS END_BLK, ??eb02_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 471 471 $DGS AUX_END, 016H + 472 472 $DGS BEG_BLK, ??bb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 473 473 $DGS AUX_BEG, 018H, 00H, 01CEH + 474 474 $DGS END_BLK, ??eb03_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 475 475 $DGS AUX_END, 01BH + 476 476 $DGS END_BLK, ??eb01_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 477 477 $DGS AUX_END, 01CH + 478 478 $DGS BEG_BLK, ??bb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 479 479 $DGS AUX_BEG, 020H, 00H, 01D0H + 480 480 $DGS BEG_BLK, ??bb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 481 481 $DGS AUX_BEG, 022H, 00H, 01D4H + 482 482 $DGS END_BLK, ??eb05_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 483 483 $DGS AUX_END, 025H + 484 484 $DGS BEG_BLK, ??bb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 485 485 $DGS AUX_BEG, 027H, 00H, 01DAH + 486 486 $DGS END_BLK, ??eb06_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 487 487 $DGS AUX_END, 02AH + 488 488 $DGS END_BLK, ??eb04_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 489 489 $DGS AUX_END, 02BH + 490 490 $DGS BEG_BLK, ??bb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 491 491 $DGS AUX_BEG, 04BH, 00H, 01DEH + 492 492 $DGS END_BLK, ??eb07_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 493 493 $DGS AUX_END, 04DH + 494 494 $DGS BEG_BLK, ??bb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 495 495 $DGS AUX_BEG, 051H, 00H, 01E0H + 496 496 $DGS BEG_BLK, ??bb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 497 497 $DGS AUX_BEG, 056H, 00H, 01E6H + 498 498 $DGS END_BLK, ??eb09_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 499 499 $DGS AUX_END, 058H + 500 500 $DGS END_BLK, ??eb08_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 501 501 $DGS AUX_END, 059H + 502 502 $DGS BEG_BLK, ??bb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 503 503 $DGS AUX_BEG, 05EH, 00H, 00H + 504 504 $DGS END_BLK, ??eb0A_ntr_pmic_comm, U, U, 00H, 064H, 01H, 00H + 505 505 $DGS AUX_END, 061H + 506 506 $DGS END_FUN, ??ef_ntr_pmic_comm, U, U, 00H, 065H, 01H, 00H + 507 507 $DGS AUX_END, 063H + 508 508 $DGS STA_SYM, _PM_get_batt_left, U, U, 01H, 03H, 01H, 02H + 509 509 $DGS AUX_FUN, 00H, U, U, 0200H, 00H, 00H + 510 510 $DGS BEG_FUN, ??bf_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H + 511 511 $DGS AUX_BEG, 0364H, 02H, 01F0H + 512 512 $DGS BEG_BLK, ??bb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 513 513 $DGS AUX_BEG, 03H, 00H, 01F2H + 514 514 $DGS BEG_BLK, ??bb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 515 515 $DGS AUX_BEG, 05H, 00H, 01FAH + 516 516 $DGS AUT_VAR, _temp, 00H, 0FFFFH, 0CH, 01H, 01H, 03H + 517 517 $DGS AUX_STR, 00H, 06H, 02H, 02H, 00H, 00H, 00H, 00H + 518 518 $DGS END_BLK, ??eb01_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 519 519 $DGS AUX_END, 0DH + 520 520 $DGS END_BLK, ??eb00_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 521 521 $DGS AUX_END, 010H + 522 522 $DGS BEG_BLK, ??bb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 523 523 $DGS AUX_BEG, 012H, 00H, 00H + 524 524 $DGS END_BLK, ??eb02_PM_get_batt_left, U, U, 00H, 064H, 01H, 00H + 525 525 $DGS AUX_END, 014H + 526 526 $DGS END_FUN, ??ef_PM_get_batt_left, U, U, 00H, 065H, 01H, 00H + 527 527 $DGS AUX_END, 01AH + 528 528 $DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 026H, 01H, 02H + 529 529 $DGS AUX_FUN, 041H, U, U, 0206H, 00H, 00H + 530 530 $DGS BEG_FUN, ??bf_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H + 531 531 $DGS AUX_BEG, 0388H, 00H, 0206H + 532 532 $DGS END_FUN, ??ef_tski_PM_LCD_on, U, U, 00H, 065H, 01H, 00H + 533 533 $DGS AUX_END, 04H + 534 534 $DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 026H, 01H, 02H + 535 535 $DGS AUX_FUN, 041H, U, U, 020CH, 00H, 00H + 536 536 $DGS BEG_FUN, ??bf_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H + 537 537 $DGS AUX_BEG, 038EH, 00H, 020CH + 538 538 $DGS END_FUN, ??ef_tski_PM_LCD_off, U, U, 00H, 065H, 01H, 00H + 539 539 $DGS AUX_END, 04H + 540 540 $DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 026H, 01H, 02H + 541 541 $DGS AUX_FUN, 041H, U, U, 0217H, 00H, 00H + 542 542 $DGS BEG_FUN, ??bf_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H + 543 543 $DGS AUX_BEG, 0394H, 02H, 0211H + 544 544 $DGS REG_VAR, _cmd_BL, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 545 545 $DGS BEG_BLK, ??bb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 546 546 $DGS AUX_BEG, 05H, 00H, 00H + 547 547 $DGS END_BLK, ??eb00_tski_PM_BL_set, U, U, 00H, 064H, 01H, 00H + 548 548 $DGS AUX_END, 08H + 549 549 $DGS END_FUN, ??ef_tski_PM_BL_set, U, U, 00H, 065H, 01H, 00H + 550 550 $DGS AUX_END, 0DH + 551 551 $DGS GLV_SYM, _raw_adc_temperature, U, U, 0CH, 026H, 00H, 00H + 552 552 $DGS GLV_SYM, _rcomp, U, U, 0CH, 026H, 00H, 00H + 553 553 $DGS GLV_SYM, _temp_co_up, U, U, 06H, 026H, 00H, 00H + 554 554 $DGS GLV_SYM, _temp_co_dn, U, U, 06H, 026H, 00H, 00H + 555 555 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H + 556 556 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 557 557 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H + 558 558 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 559 559 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H + 560 560 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 561 561 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H + 562 562 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 563 563 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 564 564 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 565 565 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 566 566 $DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H + 567 567 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 568 568 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 569 569 $DGS GLV_SYM, _iic_mcu_read, U, U, 0CH, 02H, 01H, 02H + 570 570 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 571 571 $DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H + 572 572 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 573 573 $DGS GLV_SYM, _iic_mcu_busy, U, U, 0134CH, 02H, 00H, 00H + 574 574 $DGS GLV_SYM, _iic_mcu_wo_dma, U, U, 034CH, 02H, 00H, 00H + 575 575 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 576 576 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 577 577 $DGS GLV_SYM, @@lstof, U, U, 00H, 02H, 00H, 00H + 578 578 $DGS GLV_SYM, _@RTARG4, U, U, 00H, 02H, 00H, 00H + 579 579 $DGS GLV_SYM, @@fmul, U, U, 00H, 02H, 00H, 00H + 580 580 $DGS GLV_SYM, @@fdiv, U, U, 00H, 02H, 00H, 00H + 581 581 $DGS GLV_SYM, @@fsub, U, U, 00H, 02H, 00H, 00H + 582 582 $DGS GLV_SYM, @@ftols, U, U, 00H, 02H, 00H, 00H + 583 583 $DGS GLV_SYM, @@frev, U, U, 00H, 02H, 00H, 00H + 584 584 $DGS GLV_SYM, _@RTARG3, U, U, 00H, 02H, 00H, 00H + 585 585 $DGS GLV_SYM, @@ftolu, U, U, 00H, 02H, 00H, 00H + 586 586 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 587 587 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 588 588 $DGS GLV_SYM, _iic_mcu_bus_status, U, U, 0CH, 02H, 00H, 00H + 589 589 $DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H + 590 590 $DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H + 591 591 + 592 592 EXTRN _iic_mcu_write + 593 593 EXTRN _iic_mcu_write_a_byte + 594 594 EXTRN _wait_ms + 595 595 EXTRN _iic_mcu_read_a_byte + 596 596 EXTRN _vreg_ctr + 597 597 EXTRN _@RTARG0 + 598 598 EXTRN _@RTARG2 + 599 599 EXTRN _system_status + 600 600 EXTRN _iic_mcu_read + 601 601 EXTRN _get_adc + 602 602 EXTRN _renge_task_immed_add + 603 603 EXTRN @@lstof + 604 604 EXTRN _@RTARG4 + 605 605 EXTRN @@fmul + 606 606 EXTRN @@fdiv + 607 607 EXTRN @@fsub + 608 608 EXTRN @@ftols + 609 609 EXTRN @@frev + 610 610 EXTRN _@RTARG3 + 611 611 EXTRN @@ftolu + 612 612 EXTRN _set_irq + 613 613 EXTRN _@SEGAX + 614 614 EXTRN _@SEGDE + 615 615 EXTRN _iic_mcu_bus_status + 616 616 EXTBIT _iic_mcu_busy + 617 617 EXTBIT _iic_mcu_wo_dma + 618 618 PUBLIC _raw_adc_temperature + 619 619 PUBLIC _rcomp + 620 620 PUBLIC _temp_co_up + 621 621 PUBLIC _temp_co_dn + 622 622 PUBLIC _PM_init + 623 623 PUBLIC _PM_bt_temp_update + 624 624 PUBLIC _PM_LCD_on + 625 625 PUBLIC _PM_LCD_off + 626 626 PUBLIC _PM_BL_set + 627 627 PUBLIC _PM_LCD_vcom_set + 628 628 PUBLIC _tski_vcom_set + 629 629 PUBLIC _PM_sys_pow_on + 630 630 PUBLIC _PM_sys_pow_off + 631 631 PUBLIC _tsk_batt + 632 632 PUBLIC _intp4_extdc + 633 633 PUBLIC _intp5_shell + 634 634 PUBLIC _intp6_PM_irq + 635 635 PUBLIC _ntr_pmic_comm + 636 636 PUBLIC _tski_PM_LCD_on + 637 637 PUBLIC _tski_PM_LCD_off + 638 638 PUBLIC _tski_PM_BL_set + 639 639 + 640 640 ----- @@BITS BSEG + 641 641 00000.0 ?L0079 DBIT + 642 642 + 643 643 ----- @@CNST CSEG MIRRORP + 644 644 00000 01 _lpf_coeff: DB 01H ; 1 + 645 645 00001 02 DB 02H ; 2 + 646 646 00002 02 DB 02H ; 2 + 647 647 00003 03 DB 03H ; 3 + 648 648 00004 03 DB 03H ; 3 + 649 649 00005 02 DB 02H ; 2 + 650 650 00006 00 DB 00H ; 0 + 651 651 00007 FE DB 0FEH ; 254 + 652 652 00008 FB DB 0FBH ; 251 + 653 653 00009 F7 DB 0F7H ; 247 + 654 654 0000A F3 DB 0F3H ; 243 + 655 655 0000B F0 DB 0F0H ; 240 + 656 656 0000C F0 DB 0F0H ; 240 + 657 657 0000D F3 DB 0F3H ; 243 + 658 658 0000E FA DB 0FAH ; 250 + 659 659 0000F 04 DB 04H ; 4 + 660 660 00010 12 DB 012H ; 18 + 661 661 00011 25 DB 025H ; 37 + 662 662 00012 38 DB 038H ; 56 + 663 663 00013 4D DB 04DH ; 77 + 664 664 00014 5F DB 05FH ; 95 + 665 665 00015 6E DB 06EH ; 110 + 666 666 00016 77 DB 077H ; 119 + 667 667 00017 7A DB 07AH ; 122 + 668 668 00018 77 DB 077H ; 119 + 669 669 00019 6E DB 06EH ; 110 + 670 670 0001A 5F DB 05FH ; 95 + 671 671 0001B 4D DB 04DH ; 77 + 672 672 0001C 38 DB 038H ; 56 + 673 673 0001D 25 DB 025H ; 37 + 674 674 0001E 12 DB 012H ; 18 + 675 675 0001F 04 DB 04H ; 4 + 676 676 00020 FA DB 0FAH ; 250 + 677 677 00021 F3 DB 0F3H ; 243 + 678 678 00022 F0 DB 0F0H ; 240 + 679 679 00023 F0 DB 0F0H ; 240 + 680 680 00024 F3 DB 0F3H ; 243 + 681 681 00025 F7 DB 0F7H ; 247 + 682 682 00026 FB DB 0FBH ; 251 + 683 683 00027 FE DB 0FEH ; 254 + 684 684 00028 00 DB 00H ; 0 + 685 685 00029 02 DB 02H ; 2 + 686 686 0002A 03 DB 03H ; 3 + 687 687 0002B 03 DB 03H ; 3 + 688 688 0002C 02 DB 02H ; 2 + 689 689 0002D 02 DB 02H ; 2 + 690 690 0002E 01 DB 01H ; 1 + 691 691 0002F 00 _BT_PARAM: DB 00H ; 0 + 692 692 00030 00 DB 00H ; 0 + 693 693 00031 00 DB 00H ; 0 + 694 694 00032 00 DB 00H ; 0 + 695 695 00033 00 DB 00H ; 0 + 696 696 00034 00 DB 00H ; 0 + 697 697 00035 00 DB 00H ; 0 + 698 698 00036 00 DB 00H ; 0 + 699 699 00037 00 DB 00H ; 0 + 700 700 00038 00 DB 00H ; 0 + 701 701 00039 00 DB 00H ; 0 + 702 702 0003A 00 DB 00H ; 0 + 703 703 0003B 00 DB 00H ; 0 + 704 704 0003C 00 DB 00H ; 0 + 705 705 0003D 00 DB 00H ; 0 + 706 706 0003E 00 DB 00H ; 0 + 707 707 0003F 00 DB 00H ; 0 + 708 708 00040 00 DB 00H ; 0 + 709 709 00041 00 DB 00H ; 0 + 710 710 00042 00 DB 00H ; 0 + 711 711 00043 00 DB 00H ; 0 + 712 712 00044 00 DB 00H ; 0 + 713 713 00045 00 DB 00H ; 0 + 714 714 00046 00 DB 00H ; 0 + 715 715 00047 00 DB 00H ; 0 + 716 716 00048 00 DB 00H ; 0 + 717 717 00049 00 DB 00H ; 0 + 718 718 0004A 00 DB 00H ; 0 + 719 719 0004B 00 DB 00H ; 0 + 720 720 0004C 00 DB 00H ; 0 + 721 721 0004D 00 DB 00H ; 0 + 722 722 0004E 00 DB 00H ; 0 + 723 723 0004F 00 DB 00H ; 0 + 724 724 00050 00 DB 00H ; 0 + 725 725 00051 00 DB 00H ; 0 + 726 726 00052 00 DB 00H ; 0 + 727 727 00053 00 DB 00H ; 0 + 728 728 00054 00 DB 00H ; 0 + 729 729 00055 00 DB 00H ; 0 + 730 730 00056 00 DB 00H ; 0 + 731 731 00057 00 DB 00H ; 0 + 732 732 00058 00 DB 00H ; 0 + 733 733 00059 00 DB 00H ; 0 + 734 734 0005A 00 DB 00H ; 0 + 735 735 0005B 00 DB 00H ; 0 + 736 736 0005C 00 DB 00H ; 0 + 737 737 0005D 00 DB 00H ; 0 + 738 738 0005E 00 DB 00H ; 0 + 739 739 0005F 00 DB 00H ; 0 + 740 740 00060 00 DB 00H ; 0 + 741 741 00061 00 DB 00H ; 0 + 742 742 00062 00 DB 00H ; 0 + 743 743 00063 00 DB 00H ; 0 + 744 744 00064 00 DB 00H ; 0 + 745 745 00065 00 DB 00H ; 0 + 746 746 00066 00 DB 00H ; 0 + 747 747 00067 00 DB 00H ; 0 + 748 748 00068 00 DB 00H ; 0 + 749 749 00069 00 DB 00H ; 0 + 750 750 0006A 00 DB 00H ; 0 + 751 751 0006B 00 DB 00H ; 0 + 752 752 0006C 00 DB 00H ; 0 + 753 753 0006D 00 DB 00H ; 0 + 754 754 0006E 00 DB 00H ; 0 + 755 755 0006F 00 DB 00H ; 0 + 756 756 00070 00 DB 00H ; 0 + 757 757 00071 00 DB 00H ; 0 + 758 758 00072 00 DB 00H ; 0 + 759 759 00073 00 DB 00H ; 0 + 760 760 00074 00 DB 00H ; 0 + 761 761 00075 00 DB 00H ; 0 + 762 762 00076 00 DB 00H ; 0 + 763 763 00077 00 DB 00H ; 0 + 764 764 00078 00 DB 00H ; 0 + 765 765 00079 00 DB 00H ; 0 + 766 766 0007A 00 DB 00H ; 0 + 767 767 0007B 00 DB 00H ; 0 + 768 768 0007C 00 DB 00H ; 0 + 769 769 0007D 00 DB 00H ; 0 + 770 770 0007E 00 DB 00H ; 0 + 771 771 0007F 00 DB 00H ; 0 + 772 772 00080 00 DB 00H ; 0 + 773 773 00081 00 DB 00H ; 0 + 774 774 00082 00 DB 00H ; 0 + 775 775 00083 00 DB 00H ; 0 + 776 776 00084 00 DB 00H ; 0 + 777 777 00085 00 DB 00H ; 0 + 778 778 00086 00 DB 00H ; 0 + 779 779 00087 00 DB 00H ; 0 + 780 780 00088 00 DB 00H ; 0 + 781 781 00089 00 DB 00H ; 0 + 782 782 0008A 00 DB 00H ; 0 + 783 783 0008B 00 DB 00H ; 0 + 784 784 0008C 00 DB 00H ; 0 + 785 785 0008D 00 DB 00H ; 0 + 786 786 0008E 00 DB 00H ; 0 + 787 787 0008F 00 DB 00H ; 0 + 788 788 00090 00 DB 00H ; 0 + 789 789 00091 00 DB 00H ; 0 + 790 790 00092 00 DB 00H ; 0 + 791 791 00093 00 DB 00H ; 0 + 792 792 00094 00 DB 00H ; 0 + 793 793 00095 00 DB 00H ; 0 + 794 794 00096 00 DB 00H ; 0 + 795 795 00097 00 DB 00H ; 0 + 796 796 00098 00 DB 00H ; 0 + 797 797 00099 00 DB 00H ; 0 + 798 798 0009A 00 DB 00H ; 0 + 799 799 0009B 00 DB 00H ; 0 + 800 800 0009C 00 DB 00H ; 0 + 801 801 0009D 00 DB 00H ; 0 + 802 802 0009E 00 DB 00H ; 0 + 803 803 0009F 00 DB 00H ; 0 + 804 804 000A0 00 DB 00H ; 0 + 805 805 000A1 00 DB 00H ; 0 + 806 806 000A2 00 DB 00H ; 0 + 807 807 000A3 00 DB 00H ; 0 + 808 808 000A4 00 DB 00H ; 0 + 809 809 000A5 00 DB 00H ; 0 + 810 810 000A6 00 DB 00H ; 0 + 811 811 000A7 00 DB 00H ; 0 + 812 812 000A8 00 DB 00H ; 0 + 813 813 000A9 00 DB 00H ; 0 + 814 814 000AA 00 DB 00H ; 0 + 815 815 000AB 00 DB 00H ; 0 + 816 816 000AC 00 DB 00H ; 0 + 817 817 000AD 00 DB 00H ; 0 + 818 818 000AE 00 DB 00H ; 0 + 819 819 000AF 00 DB 00H ; 0 + 820 820 000B0 00 DB 00H ; 0 + 821 821 000B1 00 DB 00H ; 0 + 822 822 000B2 00 DB 00H ; 0 + 823 823 000B3 00 DB 00H ; 0 + 824 824 000B4 00 DB 00H ; 0 + 825 825 000B5 00 DB 00H ; 0 + 826 826 000B6 00 DB 00H ; 0 + 827 827 000B7 00 DB 00H ; 0 + 828 828 000B8 00 DB 00H ; 0 + 829 829 000B9 00 DB 00H ; 0 + 830 830 000BA 00 DB 00H ; 0 + 831 831 000BB 00 DB 00H ; 0 + 832 832 000BC 00 DB 00H ; 0 + 833 833 000BD 00 DB 00H ; 0 + 834 834 000BE 00 DB 00H ; 0 + 835 835 000BF 00 DB 00H ; 0 + 836 836 000C0 00 DB 00H ; 0 + 837 837 000C1 00 DB 00H ; 0 + 838 838 000C2 00 DB 00H ; 0 + 839 839 000C3 00 DB 00H ; 0 + 840 840 000C4 00 DB 00H ; 0 + 841 841 000C5 00 DB 00H ; 0 + 842 842 000C6 00 DB 00H ; 0 + 843 843 000C7 00 DB 00H ; 0 + 844 844 000C8 00 DB 00H ; 0 + 845 845 000C9 00 DB 00H ; 0 + 846 846 000CA 00 DB 00H ; 0 + 847 847 000CB 00 DB 00H ; 0 + 848 848 000CC 00 DB 00H ; 0 + 849 849 000CD 00 DB 00H ; 0 + 850 850 000CE 00 DB 00H ; 0 + 851 851 000CF 00 DB 00H ; 0 + 852 852 000D0 00 DB 00H ; 0 + 853 853 000D1 00 DB 00H ; 0 + 854 854 000D2 00 DB 00H ; 0 + 855 855 000D3 00 DB 00H ; 0 + 856 856 000D4 00 DB 00H ; 0 + 857 857 000D5 00 DB 00H ; 0 + 858 858 000D6 00 DB 00H ; 0 + 859 859 000D7 00 DB 00H ; 0 + 860 860 000D8 00 DB 00H ; 0 + 861 861 000D9 00 DB 00H ; 0 + 862 862 000DA 00 DB 00H ; 0 + 863 863 000DB 00 DB 00H ; 0 + 864 864 000DC 00 DB 00H ; 0 + 865 865 000DD 00 DB 00H ; 0 + 866 866 000DE 00 DB 00H ; 0 + 867 867 000DF 00 DB 00H ; 0 + 868 868 000E0 00 DB 00H ; 0 + 869 869 000E1 00 DB 00H ; 0 + 870 870 000E2 00 DB 00H ; 0 + 871 871 000E3 00 DB 00H ; 0 + 872 872 000E4 00 DB 00H ; 0 + 873 873 000E5 00 DB 00H ; 0 + 874 874 000E6 00 DB 00H ; 0 + 875 875 000E7 00 DB 00H ; 0 + 876 876 000E8 00 DB 00H ; 0 + 877 877 000E9 00 DB 00H ; 0 + 878 878 000EA 00 DB 00H ; 0 + 879 879 000EB 00 DB 00H ; 0 + 880 880 000EC 00 DB 00H ; 0 + 881 881 000ED 00 DB 00H ; 0 + 882 882 000EE 00 DB 00H ; 0 + 883 883 000EF 00 DB 00H ; 0 + 884 884 000F0 00 DB 00H ; 0 + 885 885 000F1 00 DB 00H ; 0 + 886 886 000F2 00 DB 00H ; 0 + 887 887 000F3 00 DB 00H ; 0 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00115 00 DB 00H ; 0 + 922 922 00116 00 DB 00H ; 0 + 923 923 00117 00 DB 00H ; 0 + 924 924 00118 00 DB 00H ; 0 + 925 925 00119 00 DB 00H ; 0 + 926 926 0011A 00 DB 00H ; 0 + 927 927 0011B 00 DB 00H ; 0 + 928 928 0011C 00 DB 00H ; 0 + 929 929 0011D 00 DB 00H ; 0 + 930 930 0011E 00 DB 00H ; 0 + 931 931 0011F 00 DB 00H ; 0 + 932 932 00120 00 DB 00H ; 0 + 933 933 00121 00 DB 00H ; 0 + 934 934 00122 00 DB 00H ; 0 + 935 935 00123 00 DB 00H ; 0 + 936 936 00124 00 DB 00H ; 0 + 937 937 00125 00 DB 00H ; 0 + 938 938 00126 00 DB 00H ; 0 + 939 939 00127 00 DB 00H ; 0 + 940 940 00128 00 DB 00H ; 0 + 941 941 00129 00 DB 00H ; 0 + 942 942 0012A 00 DB 00H ; 0 + 943 943 0012B 00 DB 00H ; 0 + 944 944 0012C 00 DB 00H ; 0 + 945 945 0012D 00 DB 00H ; 0 + 946 946 0012E 00 DB 00H ; 0 + 947 947 0012F AD DB 0ADH ; 173 + 948 948 00130 30 DB 030H ; 48 + 949 949 00131 AE DB 0AEH ; 174 + 950 950 00132 70 DB 070H ; 112 + 951 951 00133 B0 DB 0B0H ; 176 + 952 952 00134 00 DB 00H ; 0 + 953 953 00135 B3 DB 0B3H ; 179 + 954 954 00136 00 DB 00H ; 0 + 955 955 00137 B4 DB 0B4H ; 180 + 956 956 00138 70 DB 070H ; 112 + 957 957 00139 B5 DB 0B5H ; 181 + 958 958 0013A A0 DB 0A0H ; 160 + 959 959 0013B B7 DB 0B7H ; 183 + 960 960 0013C 80 DB 080H ; 128 + 961 961 0013D BA DB 0BAH ; 186 + 962 962 0013E 00 DB 00H ; 0 + 963 963 0013F BB DB 0BBH ; 187 + 964 964 00140 90 DB 090H ; 144 + 965 965 00141 BD DB 0BDH ; 189 + 966 966 00142 00 DB 00H ; 0 + 967 967 00143 BE DB 0BEH ; 190 + 968 968 00144 00 DB 00H ; 0 + 969 969 00145 BF DB 0BFH ; 191 + 970 970 00146 F0 DB 0F0H ; 240 + 971 971 00147 C3 DB 0C3H ; 195 + 972 972 00148 00 DB 00H ; 0 + 973 973 00149 C5 DB 0C5H ; 197 + 974 974 0014A C0 DB 0C0H ; 192 + 975 975 0014B C8 DB 0C8H ; 200 + 976 976 0014C 00 DB 00H ; 0 + 977 977 0014D CA DB 0CAH ; 202 + 978 978 0014E C0 DB 0C0H ; 192 + 979 979 0014F 04 DB 04H ; 4 + 980 980 00150 00 DB 00H ; 0 + 981 981 00151 12 DB 012H ; 18 + 982 982 00152 00 DB 00H ; 0 + 983 983 00153 0C DB 0CH ; 12 + 984 984 00154 10 DB 010H ; 16 + 985 985 00155 24 DB 024H ; 36 + 986 986 00156 00 DB 00H ; 0 + 987 987 00157 10 DB 010H ; 16 + 988 988 00158 D0 DB 0D0H ; 208 + 989 989 00159 1B DB 01BH ; 27 + 990 990 0015A F0 DB 0F0H ; 240 + 991 991 0015B 0A DB 0AH ; 10 + 992 992 0015C F0 DB 0F0H ; 240 + 993 993 0015D 08 DB 08H ; 8 + 994 994 0015E E0 DB 0E0H ; 224 + 995 995 0015F 0C DB 0CH ; 12 + 996 996 00160 F0 DB 0F0H ; 240 + 997 997 00161 08 DB 08H ; 8 + 998 998 00162 C0 DB 0C0H ; 192 + 999 999 00163 08 DB 08H ; 8 + 1000 1000 00164 B0 DB 0B0H ; 176 + 1001 1001 00165 07 DB 07H ; 7 + 1002 1002 00166 F0 DB 0F0H ; 240 + 1003 1003 00167 0B DB 0BH ; 11 + 1004 1004 00168 00 DB 00H ; 0 + 1005 1005 00169 05 DB 05H ; 5 + 1006 1006 0016A D0 DB 0D0H ; 208 + 1007 1007 0016B 02 DB 02H ; 2 + 1008 1008 0016C 00 DB 00H ; 0 + 1009 1009 0016D 09 DB 09H ; 9 + 1010 1010 0016E 00 DB 00H ; 0 + 1011 1011 0016F 00 DB 00H ; 0 + 1012 1012 00170 00 DB 00H ; 0 + 1013 1013 00171 00 DB 00H ; 0 + 1014 1014 00172 00 DB 00H ; 0 + 1015 1015 00173 00 DB 00H ; 0 + 1016 1016 00174 00 DB 00H ; 0 + 1017 1017 00175 00 DB 00H ; 0 + 1018 1018 00176 00 DB 00H ; 0 + 1019 1019 00177 00 DB 00H ; 0 + 1020 1020 00178 00 DB 00H ; 0 + 1021 1021 00179 00 DB 00H ; 0 + 1022 1022 0017A 00 DB 00H ; 0 + 1023 1023 0017B 00 DB 00H ; 0 + 1024 1024 0017C 00 DB 00H ; 0 + 1025 1025 0017D 00 DB 00H ; 0 + 1026 1026 0017E 00 DB 00H ; 0 + 1027 1027 0017F 00 DB 00H ; 0 + 1028 1028 00180 00 DB 00H ; 0 + 1029 1029 00181 00 DB 00H ; 0 + 1030 1030 00182 00 DB 00H ; 0 + 1031 1031 00183 00 DB 00H ; 0 + 1032 1032 00184 00 DB 00H ; 0 + 1033 1033 00185 00 DB 00H ; 0 + 1034 1034 00186 00 DB 00H ; 0 + 1035 1035 00187 00 DB 00H ; 0 + 1036 1036 00188 00 DB 00H ; 0 + 1037 1037 00189 00 DB 00H ; 0 + 1038 1038 0018A 00 DB 00H ; 0 + 1039 1039 0018B 00 DB 00H ; 0 + 1040 1040 0018C 00 DB 00H ; 0 + 1041 1041 0018D 00 DB 00H ; 0 + 1042 1042 0018E 00 DB 00H ; 0 + 1043 1043 0018F 00 DB 00H ; 0 + 1044 1044 00190 00 DB 00H ; 0 + 1045 1045 00191 00 DB 00H ; 0 + 1046 1046 00192 00 DB 00H ; 0 + 1047 1047 00193 00 DB 00H ; 0 + 1048 1048 00194 00 DB 00H ; 0 + 1049 1049 00195 00 DB 00H ; 0 + 1050 1050 00196 00 DB 00H ; 0 + 1051 1051 00197 00 DB 00H ; 0 + 1052 1052 00198 00 DB 00H ; 0 + 1053 1053 00199 00 DB 00H ; 0 + 1054 1054 0019A 00 DB 00H ; 0 + 1055 1055 0019B 00 DB 00H ; 0 + 1056 1056 0019C 00 DB 00H ; 0 + 1057 1057 0019D 00 DB 00H ; 0 + 1058 1058 0019E 00 DB 00H ; 0 + 1059 1059 0019F 00 DB 00H ; 0 + 1060 1060 001A0 00 DB 00H ; 0 + 1061 1061 001A1 00 DB 00H ; 0 + 1062 1062 001A2 00 DB 00H ; 0 + 1063 1063 001A3 00 DB 00H ; 0 + 1064 1064 001A4 00 DB 00H ; 0 + 1065 1065 001A5 00 DB 00H ; 0 + 1066 1066 001A6 00 DB 00H ; 0 + 1067 1067 001A7 00 DB 00H ; 0 + 1068 1068 001A8 00 DB 00H ; 0 + 1069 1069 001A9 00 DB 00H ; 0 + 1070 1070 001AA 00 DB 00H ; 0 + 1071 1071 001AB 00 DB 00H ; 0 + 1072 1072 001AC 00 DB 00H ; 0 + 1073 1073 001AD 00 DB 00H ; 0 + 1074 1074 001AE 00 DB 00H ; 0 + 1075 1075 001AF AD DB 0ADH ; 173 + 1076 1076 001B0 30 DB 030H ; 48 + 1077 1077 001B1 AE DB 0AEH ; 174 + 1078 1078 001B2 70 DB 070H ; 112 + 1079 1079 001B3 B0 DB 0B0H ; 176 + 1080 1080 001B4 00 DB 00H ; 0 + 1081 1081 001B5 B3 DB 0B3H ; 179 + 1082 1082 001B6 00 DB 00H ; 0 + 1083 1083 001B7 B4 DB 0B4H ; 180 + 1084 1084 001B8 70 DB 070H ; 112 + 1085 1085 001B9 B5 DB 0B5H ; 181 + 1086 1086 001BA A0 DB 0A0H ; 160 + 1087 1087 001BB B7 DB 0B7H ; 183 + 1088 1088 001BC 80 DB 080H ; 128 + 1089 1089 001BD BA DB 0BAH ; 186 + 1090 1090 001BE 00 DB 00H ; 0 + 1091 1091 001BF BB DB 0BBH ; 187 + 1092 1092 001C0 90 DB 090H ; 144 + 1093 1093 001C1 BD DB 0BDH ; 189 + 1094 1094 001C2 00 DB 00H ; 0 + 1095 1095 001C3 BE DB 0BEH ; 190 + 1096 1096 001C4 00 DB 00H ; 0 + 1097 1097 001C5 BF DB 0BFH ; 191 + 1098 1098 001C6 F0 DB 0F0H ; 240 + 1099 1099 001C7 C3 DB 0C3H ; 195 + 1100 1100 001C8 00 DB 00H ; 0 + 1101 1101 001C9 C5 DB 0C5H ; 197 + 1102 1102 001CA C0 DB 0C0H ; 192 + 1103 1103 001CB C8 DB 0C8H ; 200 + 1104 1104 001CC 00 DB 00H ; 0 + 1105 1105 001CD CA DB 0CAH ; 202 + 1106 1106 001CE C0 DB 0C0H ; 192 + 1107 1107 001CF 04 DB 04H ; 4 + 1108 1108 001D0 00 DB 00H ; 0 + 1109 1109 001D1 12 DB 012H ; 18 + 1110 1110 001D2 00 DB 00H ; 0 + 1111 1111 001D3 0C DB 0CH ; 12 + 1112 1112 001D4 10 DB 010H ; 16 + 1113 1113 001D5 24 DB 024H ; 36 + 1114 1114 001D6 00 DB 00H ; 0 + 1115 1115 001D7 10 DB 010H ; 16 + 1116 1116 001D8 D0 DB 0D0H ; 208 + 1117 1117 001D9 1B DB 01BH ; 27 + 1118 1118 001DA F0 DB 0F0H ; 240 + 1119 1119 001DB 0A DB 0AH ; 10 + 1120 1120 001DC F0 DB 0F0H ; 240 + 1121 1121 001DD 08 DB 08H ; 8 + 1122 1122 001DE E0 DB 0E0H ; 224 + 1123 1123 001DF 0C DB 0CH ; 12 + 1124 1124 001E0 F0 DB 0F0H ; 240 + 1125 1125 001E1 08 DB 08H ; 8 + 1126 1126 001E2 C0 DB 0C0H ; 192 + 1127 1127 001E3 08 DB 08H ; 8 + 1128 1128 001E4 B0 DB 0B0H ; 176 + 1129 1129 001E5 07 DB 07H ; 7 + 1130 1130 001E6 F0 DB 0F0H ; 240 + 1131 1131 001E7 0B DB 0BH ; 11 + 1132 1132 001E8 00 DB 00H ; 0 + 1133 1133 001E9 05 DB 05H ; 5 + 1134 1134 001EA D0 DB 0D0H ; 208 + 1135 1135 001EB 02 DB 02H ; 2 + 1136 1136 001EC 00 DB 00H ; 0 + 1137 1137 001ED 09 DB 09H ; 9 + 1138 1138 001EE 00 DB 00H ; 0 + 1139 1139 001EF 87 _BT_PANA_RCOMP: DB 087H ; 135 + 1140 1140 001F0 9A99993E _BT_PANA_TEMPCOUP: DW 0999AH,03E99H ; 1050253722 + 1141 1141 001F4 0000003F _BT_PANA_TEMPCODN: DW 00000H,03F00H ; 1056964608 + 1142 1142 + 1143 1143 ----- @@R_INIT CSEG UNIT64KP + 1144 1144 00000 00 DB 00H ; 0 + 1145 1145 00001 00 DB 00H ; 0 + 1146 1146 00002 00 DB 00H ; 0 + 1147 1147 00003 00 DB (1) + 1148 1148 + 1149 1149 ----- @@INIT DSEG BASEP + 1150 1150 00000 ?L0018: DS (1) + 1151 1151 00001 ?L0077: DS (1) + 1152 1152 00002 ?L0078: DS (1) + 1153 1153 00003 DS (1) + 1154 1154 + 1155 1155 ----- @@DATA DSEG BASEP + 1156 1156 00000 _raw_adc_temperature: DS (1) + 1157 1157 00001 _rcomp: DS (1) + 1158 1158 00002 _temp_co_up: DS (4) + 1159 1159 00006 _temp_co_dn: DS (4) + 1160 1160 0000A ?L0019: DS (1) + 1161 1161 0000B DS (1) + 1162 1162 0000C ?L0020: DS (2) + 1163 1163 0000E ?L0112: DS (1) + 1164 1164 0000F DS (1) + 1165 1165 + 1166 1166 ----- @@R_INIS CSEG UNIT64KP + 1167 1167 + 1168 1168 ----- @@INIS DSEG SADDRP + 1169 1169 + 1170 1170 ----- @@DATS DSEG SADDRP + 1171 1171 + 1172 1172 ----- @@CNSTL CSEG PAGE64KP + 1173 1173 + 1174 1174 ----- @@RLINIT CSEG UNIT64KP + 1175 1175 + 1176 1176 ----- @@INITL DSEG UNIT64KP + 1177 1177 + 1178 1178 ----- @@DATAL DSEG UNIT64KP + 1179 1179 + 1180 1180 ----- @@CALT CSEG CALLT0 + 1181 1181 + 1182 1182 ; Sub-Routines created by CC78K0R + 1183 1183 + 1184 1184 ----- ROM_CODE CSEG BASE + 1185 1185 00000 bs_F0153: + 1186 1186 00000 506C mov x,#06CH ; 108 ;[INF] 2, 1 + 1187 1187 00002 RED0000 br !_iic_mcu_write ;[INF] 3, 3 + 1188 1188 00005 es_F0153: + 1189 1189 + 1190 1190 ----- ROM_CODE CSEG BASE + 1191 1191 00005 bs_F0154: + 1192 1192 00005 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1193 1193 00007 RED0000 br !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1194 1194 0000A es_F0154: + 1195 1195 + 1196 1196 ----- ROM_CODE CSEG BASE + 1197 1197 0000A bs_F0155: + 1198 1198 0000A 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 1199 1199 0000D RED0000 br !_wait_ms ;[INF] 3, 3 + 1200 1200 00010 es_F0155: + 1201 1201 + 1202 1202 ----- ROM_CODE CSEG BASE + 1203 1203 00010 bs_F0151: + 1204 1204 00010 C1 push ax ;[INF] 1, 1 + 1205 1205 00011 506C mov x,#06CH ; 108 ;[INF] 2, 1 + 1206 1206 00013 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 1207 1207 00016 C0 pop ax ;[INF] 1, 1 + 1208 1208 00017 62 mov a,c ;[INF] 1, 1 + 1209 1209 00018 D7 ret ;[INF] 1, 6 + 1210 1210 00019 es_F0151: + 1211 1211 + 1212 1212 ----- ROM_CODE CSEG BASE + 1213 1213 00019 bs_S0152: + 1214 1214 00019 72 mov c,a ;[INF] 1, 1 + 1215 1215 0001A R341300 movw de,#loww (_vreg_ctr+19) ;[INF] 3, 1 + 1216 1216 0001D 89 mov a,[de] ;[INF] 1, 1 + 1217 1217 0001E 616A or a,c ;[INF] 2, 1 + 1218 1218 00020 99 mov [de],a ;[INF] 1, 1 + 1219 1219 00021 D7 ret ;[INF] 1, 6 + 1220 1220 00022 es_S0152: + 1221 1221 + 1222 1222 ----- ROM_CODE CSEG BASE + 1223 1223 00022 bs_F0149: + 1224 1224 00022 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1225 1225 00025 C1 push ax ;[INF] 1, 1 + 1226 1226 00026 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1227 1227 00028 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 1228 1228 0002B C0 pop ax ;[INF] 1, 1 + 1229 1229 0002C 62 mov a,c ;[INF] 1, 1 + 1230 1230 0002D D7 ret ;[INF] 1, 6 + 1231 1231 0002E es_F0149: + 1232 1232 + 1233 1233 ----- ROM_CODE CSEG BASE + 1234 1234 0002E bs_F0150: + 1235 1235 0002E C1 push ax ;[INF] 1, 1 + 1236 1236 0002F E6 onew ax ;[INF] 1, 1 + 1237 1237 00030 C1 push ax ;[INF] 1, 1 + 1238 1238 00031 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1239 1239 00033 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1240 1240 00036 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 1241 1241 00038 D7 ret ;[INF] 1, 6 + 1242 1242 00039 es_F0150: + 1243 1243 + 1244 1244 ----- ROM_CODE CSEG BASE + 1245 1245 00039 bs_F0146: + 1246 1246 00039 C1 push ax ;[INF] 1, 1 + 1247 1247 0003A E6 onew ax ;[INF] 1, 1 + 1248 1248 0003B A1 incw ax ;[INF] 1, 1 + 1249 1249 0003C C1 push ax ;[INF] 1, 1 + 1250 1250 0003D 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1251 1251 0003F RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1252 1252 00042 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 1253 1253 00044 D7 ret ;[INF] 1, 6 + 1254 1254 00045 es_F0146: + 1255 1255 + 1256 1256 ----- ROM_CODE CSEG BASE + 1257 1257 00045 bs_F0147: + 1258 1258 00045 300300 movw ax,#03H ; 3 ;[INF] 3, 1 + 1259 1259 00048 C1 push ax ;[INF] 1, 1 + 1260 1260 00049 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1261 1261 0004B RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 1262 1262 0004E C0 pop ax ;[INF] 1, 1 + 1263 1263 0004F 62 mov a,c ;[INF] 1, 1 + 1264 1264 00050 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 1265 1265 00052 D7 ret ;[INF] 1, 6 + 1266 1266 00053 es_F0147: + 1267 1267 + 1268 1268 ----- ROM_CODE CSEG BASE + 1269 1269 00053 bs_F0148: + 1270 1270 00053 E6 onew ax ;[INF] 1, 1 + 1271 1271 00054 C1 push ax ;[INF] 1, 1 + 1272 1272 00055 A1 incw ax ;[INF] 1, 1 + 1273 1273 00056 A1 incw ax ;[INF] 1, 1 + 1274 1274 00057 C1 push ax ;[INF] 1, 1 + 1275 1275 00058 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1276 1276 0005A RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1277 1277 0005D 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 1278 1278 0005F D7 ret ;[INF] 1, 6 + 1279 1279 00060 es_F0148: + 1280 1280 + 1281 1281 ----- ROM_CODE CSEG BASE + 1282 1282 00060 bs_S0144: + 1283 1283 00060 RAF0C00 movw ax,!?L0020 ; temperature ;[INF] 3, 1 + 1284 1284 00063 241400 subw ax,#014H ; 20 ;[INF] 3, 1 + 1285 1285 00066 12 movw bc,ax ;[INF] 1, 1 + 1286 1286 00067 31FF sarw ax,15 ;[INF] 2, 1 + 1287 1287 00069 33 xchw ax,bc ;[INF] 1, 1 + 1288 1288 0006A RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 1289 1289 0006C 13 movw ax,bc ;[INF] 1, 1 + 1290 1290 0006D RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 1291 1291 0006F D7 ret ;[INF] 1, 6 + 1292 1292 00070 es_S0144: + 1293 1293 + 1294 1294 ----- ROM_CODE CSEG BASE + 1295 1295 00070 bs_F0145: + 1296 1296 00070 300700 movw ax,#07H ; 7 ;[INF] 3, 1 + 1297 1297 00073 C1 push ax ;[INF] 1, 1 + 1298 1298 00074 E6 onew ax ;[INF] 1, 1 + 1299 1299 00075 A1 incw ax ;[INF] 1, 1 + 1300 1300 00076 C1 push ax ;[INF] 1, 1 + 1301 1301 00077 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1302 1302 00079 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1303 1303 0007C 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 1304 1304 0007E D7 ret ;[INF] 1, 6 + 1305 1305 0007F es_F0145: + 1306 1306 + 1307 1307 ; *** Sub-Routine Information *** + 1308 1308 ; + 1309 1309 ; $SUB bs_S0144 + 1310 1310 ; CODE SIZE= 16 bytes + 1311 1311 ; + 1312 1312 ; $SUB bs_F0145 + 1313 1313 ; CODE SIZE= 15 bytes + 1314 1314 ; + 1315 1315 ; $SUB bs_F0146 + 1316 1316 ; CODE SIZE= 12 bytes + 1317 1317 ; + 1318 1318 ; $SUB bs_F0147 + 1319 1319 ; CODE SIZE= 14 bytes + 1320 1320 ; + 1321 1321 ; $SUB bs_F0148 + 1322 1322 ; CODE SIZE= 13 bytes + 1323 1323 ; + 1324 1324 ; $SUB bs_F0149 + 1325 1325 ; CODE SIZE= 12 bytes + 1326 1326 ; + 1327 1327 ; $SUB bs_F0150 + 1328 1328 ; CODE SIZE= 11 bytes + 1329 1329 ; + 1330 1330 ; $SUB bs_F0151 + 1331 1331 ; CODE SIZE= 9 bytes + 1332 1332 ; + 1333 1333 ; $SUB bs_S0152 + 1334 1334 ; CODE SIZE= 9 bytes + 1335 1335 ; + 1336 1336 ; $SUB bs_F0153 + 1337 1337 ; CODE SIZE= 5 bytes + 1338 1338 ; + 1339 1339 ; $SUB bs_F0154 + 1340 1340 ; CODE SIZE= 5 bytes + 1341 1341 ; + 1342 1342 ; $SUB bs_F0155 + 1343 1343 ; CODE SIZE= 6 bytes + 1344 1344 + 1345 1345 ; End of Sub-Routines + 1346 1346 + 1347 1347 ; line 1 : /* ======================================================== + 1348 1348 ; line 2 : 対PMIC + 1349 1349 ; line 3 : 藤田＠開技 + 1350 1350 ; line 4 : nintendo + 1351 1351 ; line 5 : '08 Dec + 1352 1352 ; line 6 : ======================================================== */ + 1353 1353 ; line 7 : #pragma nop + 1354 1354 ; line 8 : + 1355 1355 ; line 9 : #include "incs.h" + 1356 1356 ; line 10 : #include "adc.h" + 1357 1357 ; line 11 : #include "led.h" + 1358 1358 ; line 12 : #include "pm.h" + 1359 1359 ; line 13 : #include "renge.h" + 1360 1360 ; line 14 : + 1361 1361 ; line 15 : #include "batt_params.h" + 1362 1362 ; line 16 : + 1363 1363 ; line 17 : #include + 1364 1364 ; line 18 : #include "fsl_user.h" + 1365 1365 ; line 19 : extern u16 pool[]; + 1366 1366 ; line 20 : + 1367 1367 ; line 21 : // ======================================================== + 1368 1368 ; line 22 : + 1369 1369 ; line 23 : + 1370 1370 ; line 24 : // ======================================================== + 1371 1371 ; line 25 : u8 raw_adc_temperature; + 1372 1372 ; line 26 : u8 rcomp; + 1373 1373 ; line 27 : float temp_co_up; + 1374 1374 ; line 28 : float temp_co_dn; + 1375 1375 ; line 29 : + 1376 1376 ; line 30 : // ======================================================== + 1377 1377 ; line 31 : static void PM_get_batt_left(); + 1378 1378 ; line 32 : + 1379 1379 ; line 33 : + 1380 1380 ; line 34 : /******************************************************//** + 1381 1381 ; line 35 : PMIC達の初期化 + 1382 1382 ; line 36 : \n 電池メーカー識別 + 1383 1383 ; line 37 : \n 電池残量ICのセット + 1384 1384 ; line 38 : \n バージョン情報の取得 + 1385 1385 ; line 39 : \n + 1386 1386 ; line 40 : \n 以下のピンは主にここで操作・監視されます。 + 1387 1387 ; line 41 : \n ・PM_BT_DET,_P + 1388 1388 ; line 42 : *********************************************************/ + 1389 1389 ; line 43 : #define swap_endian_16( x ) (unsigned int)( x << 8 | x >> 8 ) + 1390 1390 ; line 44 : + 1391 1391 ; line 45 : void PM_init( ) + 1392 1392 ; line 46 : { + 1393 1393 + 1394 1394 ----- ROM_CODE CSEG BASE + 1395 1395 0007F _PM_init: + 1396 1396 $DGL 1,102 + 1397 1397 0007F C7 push hl ;[INF] 1, 1 + 1398 1398 00080 2008 subw sp,#08H ;[INF] 2, 1 + 1399 1399 00082 FBF8FF movw hl,sp ;[INF] 3, 1 + 1400 1400 00085 ??bf_PM_init: + 1401 1401 ; line 47 : u8 temp; + 1402 1402 ; line 48 : u8 origParam[4]; + 1403 1403 ; line 49 : union{ + 1404 1404 ; line 50 : u16 _u16; // ↓でわかるように、little endi + 1405 1405 ; an です。注意。 + 1406 1406 ; line 51 : struct{ + 1407 1407 ; line 52 : u8 lsb; + 1408 1408 ; line 53 : u8 msb; + 1409 1409 ; line 54 : }chars; + 1410 1410 ; line 55 : }dat_16; + 1411 1411 ; line 56 : + 1412 1412 ; line 57 : system_status.model = MODEL_JIKKI; + 1413 1413 $DGL 0,12 + 1414 1414 00085 RF50300 clrb !_system_status+3 ;[INF] 3, 1 + 1415 1415 ; line 58 : wait_ms( 150 ); + 1416 1416 $DGL 0,13 + 1417 1417 00088 309600 movw ax,#096H ; 150 ;[INF] 3, 1 + 1418 1418 0008B RFD0000 call !_wait_ms ;[INF] 3, 3 + 1419 1419 ; line 59 : + 1420 1420 ; line 60 : // -1. なんかおかしい…　リセットをかけてみる + 1421 1421 ; line 61 : dat_16._u16 = swap_endian_16( 0x5400 ); // reset + 1422 1422 $DGL 0,16 + 1423 1423 0008E 305400 movw ax,#054H ; 84 ;[INF] 3, 1 + 1424 1424 00091 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1425 1425 ; line 62 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_COMMAND, 2, &d + 1426 1426 ; at_16 ); // こいつはNACKを返す + 1427 1427 $DGL 0,17 + 1428 1428 00092 17 movw ax,hl ;[INF] 1, 1 + 1429 1429 00093 C1 push ax ;[INF] 1, 1 + 1430 1430 00094 E6 onew ax ;[INF] 1, 1 + 1431 1431 00095 A1 incw ax ;[INF] 1, 1 + 1432 1432 00096 C1 push ax ;[INF] 1, 1 + 1433 1433 00097 50FE mov x,#0FEH ; 254 ;[INF] 2, 1 + 1434 1434 00099 C1 push ax ;[INF] 1, 1 + 1435 1435 0009A RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1436 1436 0009D 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1437 1437 ; line 63 : + 1438 1438 ; line 64 : // 0. バッテリ残量IC クイックスタート + 1439 1439 ; line 65 : dat_16._u16 = swap_endian_16( 0x4000 ); // quick start + 1440 1440 $DGL 0,20 + 1441 1441 0009F 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 1442 1442 000A2 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1443 1443 ; line 66 : if( iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_MODE, 2, & + 1444 1444 ; dat_16 ) != ERR_SUCCESS ) + 1445 1445 $DGL 0,21 + 1446 1446 000A3 17 movw ax,hl ;[INF] 1, 1 + 1447 1447 000A4 C1 push ax ;[INF] 1, 1 + 1448 1448 000A5 E6 onew ax ;[INF] 1, 1 + 1449 1449 000A6 A1 incw ax ;[INF] 1, 1 + 1450 1450 000A7 C1 push ax ;[INF] 1, 1 + 1451 1451 000A8 5006 mov x,#06H ; 6 ;[INF] 2, 1 + 1452 1452 000AA C1 push ax ;[INF] 1, 1 + 1453 1453 000AB RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1454 1454 000AE 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1455 1455 000B0 D2 cmp0 c ;[INF] 1, 1 + 1456 1456 000B1 DD0A bz $?L0003 ;[INF] 2, 4 + 1457 1457 ; line 67 : { + 1458 1458 000B3 ??bb00_PM_init: + 1459 1459 ; line 68 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; + 1460 1460 $DGL 0,23 + 1461 1461 000B3 R71000E00 set1 !_vreg_ctr+14.0 ;[INF] 4, 2 + 1462 1462 ; line 69 : system_status.model = MODEL_TS_BOARD; + 1463 1463 $DGL 0,24 + 1464 1464 000B7 RE50300 oneb !_system_status+3 ;[INF] 3, 1 + 1465 1465 000BA ??eb00_PM_init: + 1466 1466 ; line 70 : } + 1467 1467 $DGL 0,25 + 1468 1468 000BA REDB701 br !?L0004 ;[INF] 3, 3 + 1469 1469 000BD ?L0003: + 1470 1470 ; line 71 : else + 1471 1471 ; line 72 : { + 1472 1472 000BD ??bb01_PM_init: + 1473 1473 ; line 73 : // 1. ロック解除 + 1474 1474 ; line 74 : dat_16._u16 = swap_endian_16( 0x4057 ); // unlock key + 1475 1475 $DGL 0,29 + 1476 1476 000BD 304057 movw ax,#05740H ; 22336 ;[INF] 3, 1 + 1477 1477 000C0 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1478 1478 ; line 75 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, & + 1479 1479 ; dat_16 ); + 1480 1480 $DGL 0,30 + 1481 1481 000C1 17 movw ax,hl ;[INF] 1, 1 + 1482 1482 000C2 C1 push ax ;[INF] 1, 1 + 1483 1483 000C3 E6 onew ax ;[INF] 1, 1 + 1484 1484 000C4 A1 incw ax ;[INF] 1, 1 + 1485 1485 000C5 C1 push ax ;[INF] 1, 1 + 1486 1486 000C6 503E mov x,#03EH ; 62 ;[INF] 2, 1 + 1487 1487 000C8 C1 push ax ;[INF] 1, 1 + 1488 1488 000C9 RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1489 1489 000CC 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1490 1490 ; line 76 : + 1491 1491 ; line 77 : // 2. 初期パラメータを一時保存 + 1492 1492 ; line 78 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, o + 1493 1493 ; rigParam ); + 1494 1494 $DGL 0,33 + 1495 1495 000CE 17 movw ax,hl ;[INF] 1, 1 + 1496 1496 000CF 040300 addw ax,#03H ;[INF] 3, 1 + 1497 1497 000D2 C1 push ax ;[INF] 1, 1 + 1498 1498 000D3 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1499 1499 000D6 C1 push ax ;[INF] 1, 1 + 1500 1500 000D7 500C mov x,#0CH ; 12 ;[INF] 2, 1 + 1501 1501 000D9 C1 push ax ;[INF] 1, 1 + 1502 1502 000DA 506C mov x,#06CH ; 108 ;[INF] 2, 1 + 1503 1503 000DC RFD0000 call !_iic_mcu_read ;[INF] 3, 3 + 1504 1504 000DF 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1505 1505 ; line 79 : + 1506 1506 ; line 80 : // 3. 一時的にOCVを変更 + 1507 1507 ; line 81 : dat_16._u16 = swap_endian_16( 0xD4C0 ); // マジックナンバ + 1508 1508 ; ー的なもの。メーカー指定 + 1509 1509 $DGL 0,36 + 1510 1510 000E1 30D4C0 movw ax,#0C0D4H ; -16172 ;[INF] 3, 1 + 1511 1511 000E4 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1512 1512 ; line 82 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d + 1513 1513 ; at_16 ); + 1514 1514 $DGL 0,37 + 1515 1515 000E5 17 movw ax,hl ;[INF] 1, 1 + 1516 1516 000E6 C1 push ax ;[INF] 1, 1 + 1517 1517 000E7 E6 onew ax ;[INF] 1, 1 + 1518 1518 000E8 A1 incw ax ;[INF] 1, 1 + 1519 1519 000E9 C1 push ax ;[INF] 1, 1 + 1520 1520 000EA 500E mov x,#0EH ; 14 ;[INF] 2, 1 + 1521 1521 000EC C1 push ax ;[INF] 1, 1 + 1522 1522 000ED RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1523 1523 000F0 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1524 1524 ; line 83 : + 1525 1525 ; line 84 : // 4. 一時的にRCOMPを変更 + 1526 1526 ; line 85 : dat_16._u16 = swap_endian_16( 0xFF00 ); + 1527 1527 $DGL 0,40 + 1528 1528 000F2 F6 clrw ax ;[INF] 1, 1 + 1529 1529 000F3 90 dec x ;[INF] 1, 1 + 1530 1530 000F4 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1531 1531 ; line 86 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, + 1532 1532 ; &dat_16 ); + 1533 1533 $DGL 0,41 + 1534 1534 000F5 17 movw ax,hl ;[INF] 1, 1 + 1535 1535 000F6 C1 push ax ;[INF] 1, 1 + 1536 1536 000F7 E6 onew ax ;[INF] 1, 1 + 1537 1537 000F8 A1 incw ax ;[INF] 1, 1 + 1538 1538 000F9 C1 push ax ;[INF] 1, 1 + 1539 1539 000FA 500C mov x,#0CH ; 12 ;[INF] 2, 1 + 1540 1540 000FC C1 push ax ;[INF] 1, 1 + 1541 1541 000FD RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1542 1542 00100 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1543 1543 ; line 87 : + 1544 1544 ; line 88 : // 電池メーカーの識別 + 1545 1545 ; line 89 : BT_DET_P = 1; + 1546 1546 $DGL 0,44 + 1547 1547 00102 716201 set1 P1.6 ;[INF] 3, 2 + 1548 1548 ; line 90 : temp = ( u8 ) ( ( get_adc( ADC_SEL_BATT_DET ) >> 5 ) -1 + 1549 1549 ; ); // 識別値０の白箱の分、インデックス合わせ + 1550 1550 $DGL 0,45 + 1551 1551 00105 300900 movw ax,#09H ; 9 ;[INF] 3, 1 + 1552 1552 00108 RFD0000 call !_get_adc ;[INF] 3, 3 + 1553 1553 0010B 62 mov a,c ;[INF] 1, 1 + 1554 1554 0010C 31DE shrw ax,13 ;[INF] 2, 1 + 1555 1555 0010E B1 decw ax ;[INF] 1, 1 + 1556 1556 0010F 60 mov a,x ;[INF] 1, 1 + 1557 1557 00110 9C07 mov [hl+7],a ; temp ;[INF] 2, 1 + 1558 1558 ; line 91 : BT_DET_P = 0; + 1559 1559 $DGL 0,46 + 1560 1560 00112 716301 clr1 P1.6 ;[INF] 3, 2 + 1561 1561 ; line 92 : + 1562 1562 ; line 93 : iic_mcu_set_wo_dma( ); + 1563 1563 $DGL 0,48 + 1564 1564 00115 ??bb02_PM_init: + 1565 1565 00115 ?L0005: + 1566 1566 00115 R31040002 bf _iic_mcu_busy,$?L0006 ;[INF] 4, 5 + 1567 1567 00119 ??bb03_PM_init: + 1568 1568 00119 ??eb03_PM_init: + 1569 1569 00119 EFFA br $?L0005 ;[INF] 2, 3 + 1570 1570 0011B ?L0006: + 1571 1571 0011B R710200 set1 _iic_mcu_wo_dma ;[INF] 3, 2 + 1572 1572 0011E ??eb02_PM_init: + 1573 1573 ; line 94 : // 5.メーカー別パラメータのロード + 1574 1574 ; line 95 : switch ( temp ) + 1575 1575 $DGL 0,50 + 1576 1576 0011E 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1 + 1577 1577 00120 318E shrw ax,8 ;[INF] 2, 1 + 1578 1578 00122 F7 clrw bc ;[INF] 1, 1 + 1579 1579 00123 23 subw ax,bc ;[INF] 1, 1 + 1580 1580 00124 DD0A bz $?L0008 ;[INF] 2, 4 + 1581 1581 00126 240300 subw ax,#03H ; 3 ;[INF] 3, 1 + 1582 1582 00129 DD0B bz $?L0009 ;[INF] 2, 4 + 1583 1583 0012B 240400 subw ax,#04H ; 4 ;[INF] 3, 1 + 1584 1584 0012E EF06 br $?L0009 ;[INF] 2, 3 + 1585 1585 ; line 96 : { + 1586 1586 00130 ??bb04_PM_init: + 1587 1587 ; line 97 : case( BT_VENDER_SHIROBAKO ): + 1588 1588 00130 ?L0008: + 1589 1589 ; line 98 : system_status.model = MODEL_SHIROBAKO; + 1590 1590 $DGL 0,53 + 1591 1591 00130 RCF030002 mov !_system_status+3,#02H ; 2 ;[INF] 4, 1 + 1592 1592 ; line 99 : break; + 1593 1593 $DGL 0,54 + 1594 1594 00134 EF2E br $?L0007 ;[INF] 2, 3 + 1595 1595 ; line 100 : + 1596 1596 ; line 101 : case( BT_VENDER_PANA ): + 1597 1597 00136 ?L0009: + 1598 1598 ; line 102 : case( BT_VENDER_MAXELL ): + 1599 1599 ; line 103 : default: + 1600 1600 ; line 104 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_BT_PAR + 1601 1601 ; AM, 64, &BT_PARAM[0] ); + 1602 1602 $DGL 0,59 + 1603 1603 00136 R342F00 movw de,#loww (_BT_PARAM) ;[INF] 3, 1 + 1604 1604 00139 C5 push de ;[INF] 1, 1 + 1605 1605 0013A 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 1606 1606 0013D C1 push ax ;[INF] 1, 1 + 1607 1607 0013E C1 push ax ;[INF] 1, 1 + 1608 1608 0013F RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1609 1609 00142 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1610 1610 ; line 105 : rcomp = BT_PANA_RCOMP; + 1611 1611 $DGL 0,60 + 1612 1612 00144 R8FEF01 mov a,!_BT_PANA_RCOMP ;[INF] 3, 1 + 1613 1613 00147 R9F0100 mov !_rcomp,a ;[INF] 3, 1 + 1614 1614 ; line 106 : temp_co_up = BT_PANA_TEMPCOUP; + 1615 1615 $DGL 0,61 + 1616 1616 0014A RDBF201 movw bc,!_BT_PANA_TEMPCOUP+2 ;[INF] 3, 1 + 1617 1617 0014D RAFF001 movw ax,!_BT_PANA_TEMPCOUP ;[INF] 3, 1 + 1618 1618 00150 RBF0200 movw !_temp_co_up,ax ;[INF] 3, 1 + 1619 1619 00153 33 xchw ax,bc ;[INF] 1, 1 + 1620 1620 00154 RBF0400 movw !_temp_co_up+2,ax ;[INF] 3, 1 + 1621 1621 ; line 107 : temp_co_dn = BT_PANA_TEMPCODN; + 1622 1622 $DGL 0,62 + 1623 1623 00157 RDBF601 movw bc,!_BT_PANA_TEMPCODN+2 ;[INF] 3, 1 + 1624 1624 0015A RAFF401 movw ax,!_BT_PANA_TEMPCODN ;[INF] 3, 1 + 1625 1625 0015D RBF0600 movw !_temp_co_dn,ax ;[INF] 3, 1 + 1626 1626 00160 33 xchw ax,bc ;[INF] 1, 1 + 1627 1627 00161 RBF0800 movw !_temp_co_dn+2,ax ;[INF] 3, 1 + 1628 1628 ; line 108 : break; + 1629 1629 00164 ??eb04_PM_init: + 1630 1630 ; line 109 : } + 1631 1631 00164 ?L0007: + 1632 1632 ; line 110 : + 1633 1633 ; line 111 : // 6. 150ms以上待つ + 1634 1634 ; line 112 : wait_ms( 200 ); + 1635 1635 $DGL 0,67 + 1636 1636 00164 30C800 movw ax,#0C8H ; 200 ;[INF] 3, 1 + 1637 1637 00167 RFD0000 call !_wait_ms ;[INF] 3, 3 + 1638 1638 ; line 113 : + 1639 1639 ; line 114 : // 7. OCVに「とある値」を書く + 1640 1640 ; line 115 : dat_16._u16 = swap_endian_16( 0xD4C0 ); + 1641 1641 $DGL 0,70 + 1642 1642 0016A 30D4C0 movw ax,#0C0D4H ; -16172 ;[INF] 3, 1 + 1643 1643 0016D BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1644 1644 ; line 116 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_OCV, 2, &d + 1645 1645 ; at_16 ); + 1646 1646 $DGL 0,71 + 1647 1647 0016E 17 movw ax,hl ;[INF] 1, 1 + 1648 1648 0016F C1 push ax ;[INF] 1, 1 + 1649 1649 00170 E6 onew ax ;[INF] 1, 1 + 1650 1650 00171 A1 incw ax ;[INF] 1, 1 + 1651 1651 00172 C1 push ax ;[INF] 1, 1 + 1652 1652 00173 500E mov x,#0EH ; 14 ;[INF] 2, 1 + 1653 1653 00175 C1 push ax ;[INF] 1, 1 + 1654 1654 00176 RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1655 1655 00179 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1656 1656 ; line 117 : + 1657 1657 ; line 118 : // 8. 150〜600ms待つ。600msは厳守 + 1658 1658 ; line 119 : wait_ms( 200 ); + 1659 1659 $DGL 0,74 + 1660 1660 0017B 30C800 movw ax,#0C8H ; 200 ;[INF] 3, 1 + 1661 1661 0017E RFD0000 call !_wait_ms ;[INF] 3, 3 + 1662 1662 ; line 120 : + 1663 1663 ; line 121 : // 9. SOCを読む。ベリファイのため。 + 1664 1664 ; line 122 : temp = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R + 1665 1665 ; EG_SOC ); + 1666 1666 $DGL 0,77 + 1667 1667 00181 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1668 1668 00184 RFD1000 call !bs_F0151 ;[INF] 3, 3 + 1669 1669 00187 9C07 mov [hl+7],a ; temp ;[INF] 2, 1 + 1670 1670 ; line 123 : + 1671 1671 ; line 124 : if( 0x6D == temp || temp == 0x6E || temp == 0x6F ){ + 1672 1672 $DGL 0,79 + 1673 1673 00189 4C6D cmp a,#06DH ; 109 ;[INF] 2, 1 + 1674 1674 0018B DD0A bz $?L0015 ;[INF] 2, 4 + 1675 1675 0018D 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1 + 1676 1676 0018F 4C6E cmp a,#06EH ; 110 ;[INF] 2, 1 + 1677 1677 00191 DD04 bz $?L0015 ;[INF] 2, 4 + 1678 1678 00193 8C07 mov a,[hl+7] ; temp ;[INF] 2, 1 + 1679 1679 00195 4C6F cmp a,#06FH ; 111 ;[INF] 2, 1 + 1680 1680 00197 ?L0015: + 1681 1681 00197 ??bb05_PM_init: + 1682 1682 00197 ??eb05_PM_init: + 1683 1683 ; line 125 : // カスタムモデル書き込みOK！ + 1684 1684 ; line 126 : }else{ + 1685 1685 00197 ??bb06_PM_init: + 1686 1686 00197 ??eb06_PM_init: + 1687 1687 ; line 127 : // 失敗だったらリトライするのか？ + 1688 1688 ; line 128 : } + 1689 1689 ; line 129 : + 1690 1690 ; line 130 : // 10.元のRCOMPとOCVを書き戻す + 1691 1691 ; line 131 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, + 1692 1692 ; origParam ); + 1693 1693 $DGL 0,86 + 1694 1694 00197 17 movw ax,hl ;[INF] 1, 1 + 1695 1695 00198 040300 addw ax,#03H ;[INF] 3, 1 + 1696 1696 0019B C1 push ax ;[INF] 1, 1 + 1697 1697 0019C 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 1698 1698 0019F C1 push ax ;[INF] 1, 1 + 1699 1699 001A0 500C mov x,#0CH ; 12 ;[INF] 2, 1 + 1700 1700 001A2 C1 push ax ;[INF] 1, 1 + 1701 1701 001A3 RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1702 1702 001A6 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1703 1703 ; line 132 : + 1704 1704 ; line 133 : // 11. ロック + 1705 1705 ; line 134 : dat_16._u16 = swap_endian_16( 0x0000 ); // lock key + 1706 1706 $DGL 0,89 + 1707 1707 001A8 F6 clrw ax ;[INF] 1, 1 + 1708 1708 001A9 BB movw [hl],ax ; dat_16 ;[INF] 1, 1 + 1709 1709 ; line 135 : iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_LOCK, 2, & + 1710 1710 ; dat_16 ); + 1711 1711 $DGL 0,90 + 1712 1712 001AA 17 movw ax,hl ;[INF] 1, 1 + 1713 1713 001AB C1 push ax ;[INF] 1, 1 + 1714 1714 001AC E6 onew ax ;[INF] 1, 1 + 1715 1715 001AD A1 incw ax ;[INF] 1, 1 + 1716 1716 001AE C1 push ax ;[INF] 1, 1 + 1717 1717 001AF 503E mov x,#03EH ; 62 ;[INF] 2, 1 + 1718 1718 001B1 C1 push ax ;[INF] 1, 1 + 1719 1719 001B2 RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1720 1720 001B5 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1721 1721 001B7 ??eb01_PM_init: + 1722 1722 ; line 136 : + 1723 1723 ; line 137 : // おしまい // + 1724 1724 ; line 138 : } + 1725 1725 001B7 ?L0004: + 1726 1726 ; line 139 : + 1727 1727 ; line 140 : // 電池温度測定 + 1728 1728 ; line 141 : BT_TEMP_P = 1; // 電池温度監視スタート + 1729 1729 $DGL 0,96 + 1730 1730 001B7 717201 set1 P1.7 ;[INF] 3, 2 + 1731 1731 ; line 142 : raw_adc_temperature = get_adc( ADC_SEL_BATT_TEMP ); // 温度の + 1732 1732 ; temp。 + 1733 1733 $DGL 0,97 + 1734 1734 001BA 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 1735 1735 001BD RFD0000 call !_get_adc ;[INF] 3, 3 + 1736 1736 001C0 62 mov a,c ;[INF] 1, 1 + 1737 1737 001C1 R9F0000 mov !_raw_adc_temperature,a ;[INF] 3, 1 + 1738 1738 ; line 143 : renge_task_immed_add( PM_bt_temp_update ); + 1739 1739 $DGL 0,98 + 1740 1740 001C4 R30CE01 movw ax,#loww (_PM_bt_temp_update) ;[INF] 3, 1 + 1741 1741 001C7 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1742 1742 ; line 144 : + 1743 1743 ; line 145 : // PMIC バージョン読み出し + 1744 1744 ; line 146 : // temp = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VER + 1745 1745 ; ); + 1746 1746 ; line 147 : // vreg_ctr[ VREG_C_PM_INFO ] = temp; + 1747 1747 ; line 148 : // デバッグ用は別にまとめた + 1748 1748 ; line 149 : } + 1749 1749 $DGL 0,104 + 1750 1750 001CA ??ef_PM_init: + 1751 1751 001CA 1008 addw sp,#08H ;[INF] 2, 1 + 1752 1752 001CC C6 pop hl ;[INF] 1, 1 + 1753 1753 001CD D7 ret ;[INF] 1, 6 + 1754 1754 001CE ??ee_PM_init: + 1755 1755 ; line 150 : + 1756 1756 ; line 151 : + 1757 1757 ; line 152 : + 1758 1758 ; line 153 : + 1759 1759 ; line 154 : + 1760 1760 ; line 155 : + 1761 1761 ; line 156 : /* ======================================================== + 1762 1762 ; line 157 : raw_adc_temperatureに入っている値を℃に変換するとともに、 + 1763 1763 ; line 158 : ・レジスタにセット + 1764 1764 ; line 159 : ・残量ICにセット + 1765 1765 ; line 160 : todo + 1766 1766 ; line 161 : ======================================================== */ + 1767 1767 ; line 162 : task_status_immed PM_bt_temp_update( ) + 1768 1768 ; line 163 : { + 1769 1769 001CE _PM_bt_temp_update: + 1770 1770 $DGL 1,154 + 1771 1771 001CE C7 push hl ;[INF] 1, 1 + 1772 1772 001CF C1 push ax ;[INF] 1, 1 + 1773 1773 001D0 FBF8FF movw hl,sp ;[INF] 3, 1 + 1774 1774 001D3 ??bf_PM_bt_temp_update: + 1775 1775 ; line 164 : static u8 count = 0; // たまにしか書きに行かない + 1776 1776 ; line 165 : + 1777 1777 ; line 166 : static u8 rawdat_old; + 1778 1778 ; line 167 : static s16 temperature; // todo + 1779 1779 ; line 168 : u16 newrcomp; + 1780 1780 ; line 169 : + 1781 1781 ; line 170 : /* + 1782 1782 ; line 171 : サーミスタ - 10kΩ分圧点の時、 + 1783 1783 ; line 172 : 常用温度では分圧比のカーブがほぼリニアで、 + 1784 1784 ; line 173 : 村田 T[℃] = 81.48 - 111.97 x ratio + 1785 1785 ; line 174 : TDK T = 81.406 - 111.81 x ratio + 1786 1786 ; line 175 : */ + 1787 1787 ; line 176 : if( rawdat_old != raw_adc_temperature ){ + 1788 1788 $DGL 0,14 + 1789 1789 001D3 R8F0A00 mov a,!?L0019 ; rawdat_old ;[INF] 3, 1 + 1790 1790 001D6 R4F0000 cmp a,!_raw_adc_temperature ;[INF] 3, 1 + 1791 1791 001D9 DD47 bz $?L0021 ;[INF] 2, 4 + 1792 1792 001DB ??bb00_PM_bt_temp_update: + 1793 1793 ; line 177 : DBG_P_n = 1; + 1794 1794 $DGL 0,15 + 1795 1795 001DB 712202 set1 P2.2 ;[INF] 3, 2 + 1796 1796 ; line 178 : temperature = 81.45 - 111.9 * raw_adc_temperature/256.0; + 1797 1797 $DGL 0,16 + 1798 1798 001DE R8F0000 mov a,!_raw_adc_temperature ;[INF] 3, 1 + 1799 1799 001E1 318E shrw ax,8 ;[INF] 2, 1 + 1800 1800 001E3 F7 clrw bc ;[INF] 1, 1 + 1801 1801 001E4 RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 1802 1802 001E6 13 movw ax,bc ;[INF] 1, 1 + 1803 1803 001E7 RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 1804 1804 001E9 RFD0000 call !@@lstof ;[INF] 3, 3 + 1805 1805 001EC RC900CDCC movw _@RTARG4,#0CCCDH ; -13107 ;[INF] 4, 1 + 1806 1806 001F0 30DF42 movw ax,#042DFH ; 17119 ;[INF] 3, 1 + 1807 1807 001F3 RFD0000 call !@@fmul ;[INF] 3, 3 + 1808 1808 001F6 RC9000000 movw _@RTARG4,#00H ; 0 ;[INF] 4, 1 + 1809 1809 001FA 308043 movw ax,#04380H ; 17280 ;[INF] 3, 1 + 1810 1810 001FD RFD0000 call !@@fdiv ;[INF] 3, 3 + 1811 1811 00200 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 1812 1812 00202 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 1813 1813 00204 RAD00 movw ax,_@RTARG2 ;[INF] 2, 1 + 1814 1814 00206 RC90066E6 movw _@RTARG0,#0E666H ; -6554 ;[INF] 4, 1 + 1815 1815 0020A RC900A242 movw _@RTARG2,#042A2H ; 17058 ;[INF] 4, 1 + 1816 1816 0020E RFD0000 call !@@fsub ;[INF] 3, 3 + 1817 1817 00211 RFD0000 call !@@ftols ;[INF] 3, 3 + 1818 1818 00214 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 1819 1819 00216 RBF0C00 movw !?L0020,ax ; temperature ;[INF] 3, 1 + 1820 1820 ; line 179 : vreg_ctr[VREG_C_BT_TEMP] = (u8)temperature; + 1821 1821 $DGL 0,17 + 1822 1822 00219 R8F0C00 mov a,!?L0020 ; temperature ;[INF] 3, 1 + 1823 1823 0021C R9F0A00 mov !_vreg_ctr+10,a ;[INF] 3, 1 + 1824 1824 ; line 180 : DBG_P_n = 0; + 1825 1825 $DGL 0,18 + 1826 1826 0021F 712302 clr1 P2.2 ;[INF] 3, 2 + 1827 1827 00222 ??eb00_PM_bt_temp_update: + 1828 1828 ; line 181 : } + 1829 1829 00222 ?L0021: + 1830 1830 ; line 182 : + 1831 1831 ; line 183 : // 時々書きにゆく + 1832 1832 ; line 184 : if( count == 0 ) + 1833 1833 $DGL 0,22 + 1834 1834 00222 RD50000 cmp0 !?L0018 ; count ;[INF] 3, 1 + 1835 1835 00225 DF79 bnz $?L0031 ;[INF] 2, 4 + 1836 1836 ; line 185 : { + 1837 1837 00227 ??bb01_PM_bt_temp_update: + 1838 1838 ; line 186 : DBG_P_n = 1; + 1839 1839 $DGL 0,24 + 1840 1840 00227 712202 set1 P2.2 ;[INF] 3, 2 + 1841 1841 ; line 187 : if( vreg_ctr[VREG_C_BT_TEMP] > 20 ) + 1842 1842 $DGL 0,25 + 1843 1843 0022A R400A0015 cmp !_vreg_ctr+10,#015H ; 21 ;[INF] 4, 1 + 1844 1844 0022E DC25 bc $?L0025 ;[INF] 2, 4 + 1845 1845 ; line 188 : { + 1846 1846 00230 ??bb02_PM_bt_temp_update: + 1847 1847 ; line 189 : newrcomp = -( ( temperature - 20 ) * temp_co_up ); + 1848 1848 $DGL 0,27 + 1849 1849 00230 RFD6000 call !bs_S0144 ;[INF] 3, 3 + 1850 1850 00233 RFD0000 call !@@lstof ;[INF] 3, 3 + 1851 1851 00236 RAF0200 movw ax,!_temp_co_up ;[INF] 3, 1 + 1852 1852 00239 RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 1853 1853 0023B RAF0400 movw ax,!_temp_co_up+2 ;[INF] 3, 1 + 1854 1854 0023E RFD0000 call !@@fmul ;[INF] 3, 3 + 1855 1855 00241 RFD0000 call !@@frev ;[INF] 3, 3 + 1856 1856 00244 R31720005 bt _@RTARG3.7,$?L0027 ;[INF] 4, 5 + 1857 1857 00248 RFD0000 call !@@ftolu ;[INF] 3, 3 + 1858 1858 0024B EF03 br $?L0028 ;[INF] 2, 3 + 1859 1859 0024D ?L0027: + 1860 1860 0024D RFD0000 call !@@ftols ;[INF] 3, 3 + 1861 1861 00250 ?L0028: + 1862 1862 00250 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 1863 1863 00252 BB movw [hl],ax ; newrcomp ;[INF] 1, 1 + 1864 1864 00253 ??eb02_PM_bt_temp_update: + 1865 1865 ; line 190 : } + 1866 1866 $DGL 0,28 + 1867 1867 00253 EF23 br $?L0026 ;[INF] 2, 3 + 1868 1868 00255 ?L0025: + 1869 1869 ; line 191 : else + 1870 1870 ; line 192 : { + 1871 1871 00255 ??bb03_PM_bt_temp_update: + 1872 1872 ; line 193 : newrcomp = -( ( temperature - 20 ) * temp_co_dn ); + 1873 1873 $DGL 0,31 + 1874 1874 00255 RFD6000 call !bs_S0144 ;[INF] 3, 3 + 1875 1875 00258 RFD0000 call !@@lstof ;[INF] 3, 3 + 1876 1876 0025B RAF0600 movw ax,!_temp_co_dn ;[INF] 3, 1 + 1877 1877 0025E RBD00 movw _@RTARG4,ax ;[INF] 2, 1 + 1878 1878 00260 RAF0800 movw ax,!_temp_co_dn+2 ;[INF] 3, 1 + 1879 1879 00263 RFD0000 call !@@fmul ;[INF] 3, 3 + 1880 1880 00266 RFD0000 call !@@frev ;[INF] 3, 3 + 1881 1881 00269 R31720005 bt _@RTARG3.7,$?L0029 ;[INF] 4, 5 + 1882 1882 0026D RFD0000 call !@@ftolu ;[INF] 3, 3 + 1883 1883 00270 EF03 br $?L0030 ;[INF] 2, 3 + 1884 1884 00272 ?L0029: + 1885 1885 00272 RFD0000 call !@@ftols ;[INF] 3, 3 + 1886 1886 00275 ?L0030: + 1887 1887 00275 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 1888 1888 00277 BB movw [hl],ax ; newrcomp ;[INF] 1, 1 + 1889 1889 00278 ??eb03_PM_bt_temp_update: + 1890 1890 ; line 194 : } + 1891 1891 00278 ?L0026: + 1892 1892 ; line 195 : newrcomp += rcomp; + 1893 1893 $DGL 0,33 + 1894 1894 00278 RD90100 mov x,!_rcomp ;[INF] 3, 1 + 1895 1895 0027B F1 clrb a ;[INF] 1, 1 + 1896 1896 0027C 610900 addw ax,[hl+0] ; newrcomp ;[INF] 3, 1 + 1897 1897 0027F BB movw [hl],ax ; newrcomp ;[INF] 1, 1 + 1898 1898 ; line 196 : + 1899 1899 ; line 197 : newrcomp = swap_endian_16( (u16)newrcomp ); + 1900 1900 $DGL 0,35 + 1901 1901 00280 318D shlw ax,8 ;[INF] 2, 1 + 1902 1902 00282 08 xch a,x ;[INF] 1, 1 + 1903 1903 00283 6E01 or a,[hl+1] ; newrcomp ;[INF] 2, 1 + 1904 1904 00285 08 xch a,x ;[INF] 1, 1 + 1905 1905 00286 BB movw [hl],ax ; newrcomp ;[INF] 1, 1 + 1906 1906 ; line 198 : DBG_P_n = 0; + 1907 1907 $DGL 0,36 + 1908 1908 00287 712302 clr1 P2.2 ;[INF] 3, 2 + 1909 1909 ; line 199 : + 1910 1910 ; line 200 : if( iic_mcu_write + 1911 1911 ; line 201 : ( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 2, &newrcomp + 1912 1912 ; ) == ERR_SUCCESS ) + 1913 1913 $DGL 0,39 + 1914 1914 0028A 17 movw ax,hl ;[INF] 1, 1 + 1915 1915 0028B C1 push ax ;[INF] 1, 1 + 1916 1916 0028C E6 onew ax ;[INF] 1, 1 + 1917 1917 0028D A1 incw ax ;[INF] 1, 1 + 1918 1918 0028E C1 push ax ;[INF] 1, 1 + 1919 1919 0028F 500C mov x,#0CH ; 12 ;[INF] 2, 1 + 1920 1920 00291 C1 push ax ;[INF] 1, 1 + 1921 1921 00292 RFD0000 call !bs_F0153 ;[INF] 3, 3 + 1922 1922 00295 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 1923 1923 00297 D2 cmp0 c ;[INF] 1, 1 + 1924 1924 00298 DF06 bnz $?L0031 ;[INF] 2, 4 + 1925 1925 ; line 202 : { + 1926 1926 0029A ??bb04_PM_bt_temp_update: + 1927 1927 ; line 203 : rawdat_old = raw_adc_temperature; + 1928 1928 $DGL 0,41 + 1929 1929 0029A R8F0000 mov a,!_raw_adc_temperature ;[INF] 3, 1 + 1930 1930 0029D R9F0A00 mov !?L0019,a ; rawdat_old ;[INF] 3, 1 + 1931 1931 002A0 ??eb04_PM_bt_temp_update: + 1932 1932 ; line 204 : } + 1933 1933 002A0 ?L0031: + 1934 1934 002A0 ??eb01_PM_bt_temp_update: + 1935 1935 ; line 205 : } + 1936 1936 ; line 206 : count += 1; + 1937 1937 $DGL 0,44 + 1938 1938 002A0 RA00000 inc !?L0018 ; count ;[INF] 3, 2 + 1939 1939 ; line 207 : + 1940 1940 ; line 208 : return ( ERR_SUCCESS ); + 1941 1941 $DGL 0,46 + 1942 1942 002A3 F7 clrw bc ;[INF] 1, 1 + 1943 1943 ; line 209 : } + 1944 1944 $DGL 0,47 + 1945 1945 002A4 ??ef_PM_bt_temp_update: + 1946 1946 002A4 C0 pop ax ;[INF] 1, 1 + 1947 1947 002A5 C6 pop hl ;[INF] 1, 1 + 1948 1948 002A6 D7 ret ;[INF] 1, 6 + 1949 1949 002A7 ??ee_PM_bt_temp_update: + 1950 1950 ; line 210 : + 1951 1951 ; line 211 : + 1952 1952 ; line 212 : + 1953 1953 ; line 213 : #ifdef _PMIC_TWL_ + 1954 1954 ; line 214 : u8 blset; + 1955 1955 ; line 215 : #endif + 1956 1956 ; line 216 : + 1957 1957 ; line 217 : #ifndef _PARRADIUM_ + 1958 1958 ; line 218 : /* ======================================================== + 1959 1959 ; line 219 : 液晶系の電源制御 + 1960 1960 ; line 220 : 　ステータスフラグはすぐに立ててしまう。 + 1961 1961 ; line 221 : 　不感応時間があるし、 + 1962 1962 ; line 222 : 起動失敗であれば電源が落ちる + 1963 1963 ; line 223 : 別のタスクで電源落ちは監視していて、ステータスもクリアする + 1964 1964 ; line 224 : ======================================================== */ + 1965 1965 ; line 225 : // BSR // + 1966 1966 ; line 226 : err PM_LCD_on( ) + 1967 1967 ; line 227 : { + 1968 1968 002A7 _PM_LCD_on: + 1969 1969 $DGL 1,184 + 1970 1970 002A7 C7 push hl ;[INF] 1, 1 + 1971 1971 002A8 ??bf_PM_LCD_on: + 1972 1972 ; line 228 : u8 rv; + 1973 1973 ; line 229 : + 1974 1974 ; line 230 : PM_VDDLCD_on( ); + 1975 1975 $DGL 0,4 + 1976 1976 002A8 RFD7000 call !bs_F0145 ;[INF] 3, 3 + 1977 1977 ; line 231 : + 1978 1978 ; line 232 : wait_ms( DELAY_PM_TSS_50B_AND_TCOM ); + 1979 1979 $DGL 0,6 + 1980 1980 002AB 301100 movw ax,#011H ; 17 ;[INF] 3, 1 + 1981 1981 002AE RFD0000 call !_wait_ms ;[INF] 3, 3 + 1982 1982 ; line 233 : + 1983 1983 ; line 234 : PM_TCOM_on( ); + 1984 1984 $DGL 0,8 + 1985 1985 002B1 300F00 movw ax,#0FH ; 15 ;[INF] 3, 1 + 1986 1986 002B4 RFD3900 call !bs_F0146 ;[INF] 3, 3 + 1987 1987 ; line 235 : + 1988 1988 ; line 236 : wait_ms( DELAY_PM_TCOM_TO_VCS ); + 1989 1989 $DGL 0,10 + 1990 1990 002B7 300300 movw ax,#03H ; 3 ;[INF] 3, 1 + 1991 1991 002BA RFD0000 call !_wait_ms ;[INF] 3, 3 + 1992 1992 ; line 237 : + 1993 1993 ; line 238 : PM_VCS_on( ); + 1994 1994 $DGL 0,12 + 1995 1995 002BD 301F00 movw ax,#01FH ; 31 ;[INF] 3, 1 + 1996 1996 002C0 RFD3900 call !bs_F0146 ;[INF] 3, 3 + 1997 1997 ; line 239 : + 1998 1998 ; line 240 : wait_ms( DELAY_PM_VCS_TO_BL ); + 1999 1999 $DGL 0,14 + 2000 2000 002C3 301600 movw ax,#016H ; 22 ;[INF] 3, 1 + 2001 2001 002C6 RFD0000 call !_wait_ms ;[INF] 3, 3 + 2002 2002 ; line 241 : #ifdef _PM_BUG_ + 2003 2003 ; line 242 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0x4A ); // バグ持 + 2004 2004 ; ちPMIC対策 + 2005 2005 ; line 243 : #endif + 2006 2006 ; line 244 : + 2007 2007 ; line 245 : rv = PM_chk_LDSW( ); + 2008 2008 $DGL 0,19 + 2009 2009 002C9 RFD4500 call !bs_F0147 ;[INF] 3, 3 + 2010 2010 002CC 76 mov l,a ;[INF] 1, 1 + 2011 2011 ; line 246 : + 2012 2012 ; line 247 : if( rv != 0 ) + 2013 2013 $DGL 0,21 + 2014 2014 002CD D1 cmp0 a ;[INF] 1, 1 + 2015 2015 002CE DD0D bz $?L0035 ;[INF] 2, 4 + 2016 2016 ; line 248 : { + 2017 2017 002D0 ??bb00_PM_LCD_on: + 2018 2018 ; line 249 : // 電源起動エラーなら電源も切れてしまう。ここではケアしな + 2019 2019 ; い + 2020 2020 ; line 250 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; + 2021 2021 $DGL 0,24 + 2022 2022 002D0 R71700F00 set1 !_vreg_ctr+15.7 ;[INF] 4, 2 + 2023 2023 ; line 251 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); + 2024 2024 $DGL 0,25 + 2025 2025 002D4 E6 onew ax ;[INF] 1, 1 + 2026 2026 002D5 A1 incw ax ;[INF] 1, 1 + 2027 2027 002D6 C1 push ax ;[INF] 1, 1 + 2028 2028 002D7 5013 mov x,#013H ; 19 ;[INF] 2, 1 + 2029 2029 002D9 RFD0000 call !_set_irq ;[INF] 3, 3 + 2030 2030 002DC C0 pop ax ;[INF] 1, 1 + 2031 2031 ; line 252 : + 2032 2032 ; line 253 : SND_DEPOP_DEACT; // 1でミュート + 2033 2033 002DD ??eb00_PM_LCD_on: + 2034 2034 ; line 254 : } + 2035 2035 002DD ?L0035: + 2036 2036 ; line 255 : + 2037 2037 ; line 256 : #ifdef _PMIC_TWL_ + 2038 2038 ; line 257 : PM_TEG_LCD_dis( 0 ); + 2039 2039 ; line 258 : blset = ( PM_REG_BIT_BL_U | PM_REG_BIT_BL_L ); + 2040 2040 ; line 259 : #endif + 2041 2041 ; line 260 : return ( rv ); + 2042 2042 $DGL 0,34 + 2043 2043 002DD 17 movw ax,hl ;[INF] 1, 1 + 2044 2044 002DE F1 clrb a ;[INF] 1, 1 + 2045 2045 002DF 12 movw bc,ax ;[INF] 1, 1 + 2046 2046 ; line 261 : } + 2047 2047 $DGL 0,35 + 2048 2048 002E0 ??ef_PM_LCD_on: + 2049 2049 002E0 C6 pop hl ;[INF] 1, 1 + 2050 2050 002E1 D7 ret ;[INF] 1, 6 + 2051 2051 002E2 ??ee_PM_LCD_on: + 2052 2052 ; line 262 : + 2053 2053 ; line 263 : // BSR // + 2054 2054 ; line 264 : void PM_LCD_off() + 2055 2055 ; line 265 : { + 2056 2056 002E2 _PM_LCD_off: + 2057 2057 $DGL 1,195 + 2058 2058 002E2 C7 push hl ;[INF] 1, 1 + 2059 2059 002E3 ??bf_PM_LCD_off: + 2060 2060 ; line 266 : SND_DEPOP_ACT; + 2061 2061 ; line 267 : + 2062 2062 ; line 268 : // BLついてたら消す + 2063 2063 ; line 269 : #ifdef _PMIC_TWL_ + 2064 2064 ; line 270 : if( blset != 0 ) + 2065 2065 ; line 271 : #else + 2066 2066 ; line 272 : if( ( iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) & + 2067 2067 ; 0x03 ) != 0 ) + 2068 2068 $DGL 0,8 + 2069 2069 002E3 RFD2200 call !bs_F0149 ;[INF] 3, 3 + 2070 2070 002E6 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 2071 2071 002E8 D1 cmp0 a ;[INF] 1, 1 + 2072 2072 002E9 DD3C bz $?L0039 ;[INF] 2, 4 + 2073 2073 ; line 273 : #endif + 2074 2074 ; line 274 : { + 2075 2075 002EB ??bb00_PM_LCD_off: + 2076 2076 ; line 275 : u8 tot; + 2077 2077 ; line 276 : + 2078 2078 ; line 277 : PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ) + 2079 2079 ; ; + 2080 2080 $DGL 0,13 + 2081 2081 002EB 301400 movw ax,#014H ; 20 ;[INF] 3, 1 + 2082 2082 002EE RFD4203 call !_PM_BL_set ;[INF] 3, 3 + 2083 2083 ; line 278 : vreg_ctr[VREG_C_STATUS] &= 0b10011111; + 2084 2084 $DGL 0,14 + 2085 2085 002F1 R340F00 movw de,#loww (_vreg_ctr+15) ;[INF] 3, 1 + 2086 2086 002F4 89 mov a,[de] ;[INF] 1, 1 + 2087 2087 002F5 5C9F and a,#09FH ; 159 ;[INF] 2, 1 + 2088 2088 002F7 99 mov [de],a ;[INF] 1, 1 + 2089 2089 ; line 279 : + 2090 2090 ; line 280 : if( (( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr + 2091 2091 ; [ VREG_C_IRQ_MASK3 ] ) != 0 ) + 2092 2092 $DGL 0,16 + 2093 2093 002F8 8A0C mov a,[de+12] ;[INF] 2, 1 + 2094 2094 002FA 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1 + 2095 2095 002FC 50FF mov x,#0FFH ; 255 ;[INF] 2, 1 + 2096 2096 002FE 5C14 and a,#014H ; 20 ;[INF] 2, 1 + 2097 2097 00300 D1 cmp0 a ;[INF] 1, 1 + 2098 2098 00301 DD1D bz $?L0041 ;[INF] 2, 4 + 2099 2099 ; line 281 : { + 2100 2100 00303 ??bb01_PM_LCD_off: + 2101 2101 ; line 282 : vreg_ctr[ VREG_C_IRQ3 ] |= ( ( REG_BIT_BL_U_OFF | RE + 2102 2102 ; G_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ); + 2103 2103 $DGL 0,18 + 2104 2104 00303 8A0C mov a,[de+12] ;[INF] 2, 1 + 2105 2105 00305 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1 + 2106 2106 00307 5C14 and a,#014H ; 20 ;[INF] 2, 1 + 2107 2107 00309 RFD1900 call !bs_S0152 ;[INF] 3, 3 + 2108 2108 ; line 283 : IRQ0_neg; + 2109 2109 $DGL 0,19 + 2110 2110 0030C ??bb02_PM_LCD_off: + 2111 2111 0030C 716A27 set1 PM7.6 ;[INF] 3, 2 + 2112 2112 0030F ??eb02_PM_LCD_off: + 2113 2113 ; line 284 : tot = 0; + 2114 2114 $DGL 0,20 + 2115 2115 0030F 5600 mov l,#00H ; 0 ;[INF] 2, 1 + 2116 2116 ; line 285 : while( !IRQ0 && ( ++tot != 0 ) ){;} + 2117 2117 $DGL 0,21 + 2118 2118 00311 ?L0043: + 2119 2119 00311 31620705 bt P7.6,$?L0044 ;[INF] 4, 5 + 2120 2120 00315 86 inc l ;[INF] 1, 1 + 2121 2121 00316 66 mov a,l ;[INF] 1, 1 + 2122 2122 00317 D1 cmp0 a ;[INF] 1, 1 + 2123 2123 00318 DFF7 bnz $?L0043 ;[INF] 2, 4 + 2124 2124 0031A ??bb03_PM_LCD_off: + 2125 2125 0031A ??eb03_PM_LCD_off: + 2126 2126 0031A ?L0044: + 2127 2127 ; line 286 : IRQ0_ast; + 2128 2128 $DGL 0,22 + 2129 2129 0031A ??bb04_PM_LCD_off: + 2130 2130 0031A 716307 clr1 P7.6 ;[INF] 3, 2 + 2131 2131 0031D 716B27 clr1 PM7.6 ;[INF] 3, 2 + 2132 2132 00320 ??eb04_PM_LCD_off: + 2133 2133 00320 ??eb01_PM_LCD_off: + 2134 2134 ; line 287 : } + 2135 2135 00320 ?L0041: + 2136 2136 ; line 288 : vreg_ctr[VREG_C_COMMAND2] &= ~( REG_BIT_CMD_BL_U_OFF | R + 2137 2137 ; EG_BIT_CMD_BL_L_OFF ); + 2138 2138 $DGL 0,24 + 2139 2139 00320 R342200 movw de,#loww (_vreg_ctr+34) ;[INF] 3, 1 + 2140 2140 00323 89 mov a,[de] ;[INF] 1, 1 + 2141 2141 00324 5CEB and a,#0EBH ; 235 ;[INF] 2, 1 + 2142 2142 00326 99 mov [de],a ;[INF] 1, 1 + 2143 2143 00327 ??eb00_PM_LCD_off: + 2144 2144 ; line 289 : } + 2145 2145 00327 ?L0039: + 2146 2146 ; line 290 : + 2147 2147 ; line 291 : #ifdef _PMIC_TWL_ + 2148 2148 ; line 292 : PM_TEG_LCD_dis( 1 ); + 2149 2149 ; line 293 : blset = 0; + 2150 2150 ; line 294 : #endif + 2151 2151 ; line 295 : + 2152 2152 ; line 296 : PM_TCOM_VCS_off( ); + 2153 2153 $DGL 0,32 + 2154 2154 00327 RFD7000 call !bs_F0145 ;[INF] 3, 3 + 2155 2155 ; line 297 : wait_ms( DELAY_PM_LCD_OFF ); + 2156 2156 $DGL 0,33 + 2157 2157 0032A 303300 movw ax,#033H ; 51 ;[INF] 3, 1 + 2158 2158 0032D RFD0000 call !_wait_ms ;[INF] 3, 3 + 2159 2159 ; line 298 : + 2160 2160 ; line 299 : PM_VDDLCD_off( ); // 残ってたの全部止めます。 + 2161 2161 $DGL 0,35 + 2162 2162 00330 F6 clrw ax ;[INF] 1, 1 + 2163 2163 00331 RFD3900 call !bs_F0146 ;[INF] 3, 3 + 2164 2164 ; line 300 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; + 2165 2165 $DGL 0,36 + 2166 2166 00334 R71780F00 clr1 !_vreg_ctr+15.7 ;[INF] 4, 2 + 2167 2167 ; line 301 : + 2168 2168 ; line 302 : + 2169 2169 ; line 303 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); + 2170 2170 $DGL 0,39 + 2171 2171 00338 E6 onew ax ;[INF] 1, 1 + 2172 2172 00339 C1 push ax ;[INF] 1, 1 + 2173 2173 0033A 5013 mov x,#013H ; 19 ;[INF] 2, 1 + 2174 2174 0033C RFD0000 call !_set_irq ;[INF] 3, 3 + 2175 2175 0033F C0 pop ax ;[INF] 1, 1 + 2176 2176 ; line 304 : } + 2177 2177 $DGL 0,40 + 2178 2178 00340 ??ef_PM_LCD_off: + 2179 2179 00340 C6 pop hl ;[INF] 1, 1 + 2180 2180 00341 D7 ret ;[INF] 1, 6 + 2181 2181 00342 ??ee_PM_LCD_off: + 2182 2182 ; line 305 : + 2183 2183 ; line 306 : + 2184 2184 ; line 307 : + 2185 2185 ; line 308 : /* ======================================================== + 2186 2186 ; line 309 : 　バックライトの個別on/off + 2187 2187 ; line 310 : 　現状から　on/off/維持　のフラグなので面倒 + 2188 2188 ; line 311 : 　　例えば、BL on/on の状態で、on/onにしろと言われても、on/on割り + 2189 2189 ; 込みを入れます。 + 2190 2190 ; line 312 : ======================================================== */ + 2191 2191 ; line 313 : err PM_BL_set( u8 dat ) + 2192 2192 ; line 314 : { + 2193 2193 00342 _PM_BL_set: + 2194 2194 $DGL 1,223 + 2195 2195 00342 C7 push hl ;[INF] 1, 1 + 2196 2196 00343 C1 push ax ;[INF] 1, 1 + 2197 2197 00344 2004 subw sp,#04H ;[INF] 2, 1 + 2198 2198 00346 FBF8FF movw hl,sp ;[INF] 3, 1 + 2199 2199 00349 ??bf_PM_BL_set: + 2200 2200 ; line 315 : #ifndef _PMIC_TWL_ + 2201 2201 ; line 316 : u8 blset; + 2202 2202 ; line 317 : #endif + 2203 2203 ; line 318 : u8 intset = 0; + 2204 2204 $DGL 0,5 + 2205 2205 00349 CC0200 mov [hl+2],#00H ; intset,0 ;[INF] 3, 1 + 2206 2206 ; line 319 : // RMWを行う + 2207 2207 ; line 320 : + 2208 2208 ; line 321 : #ifndef _PMIC_TWL_ + 2209 2209 ; line 322 : // Read + 2210 2210 ; line 323 : blset = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL ) + 2211 2211 ; ; + 2212 2212 $DGL 0,10 + 2213 2213 0034C RFD2200 call !bs_F0149 ;[INF] 3, 3 + 2214 2214 0034F 9C03 mov [hl+3],a ; blset ;[INF] 2, 1 + 2215 2215 ; line 324 : #endif + 2216 2216 ; line 325 : + 2217 2217 ; line 326 : // Modify + 2218 2218 ; line 327 : // ue + 2219 2219 ; line 328 : if(( dat & REG_BIT_CMD_BL_U_ON ) != 0 ) + 2220 2220 $DGL 0,15 + 2221 2221 00351 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1 + 2222 2222 00353 5C20 and a,#020H ; 32 ;[INF] 2, 1 + 2223 2223 00355 D1 cmp0 a ;[INF] 1, 1 + 2224 2224 00356 DD0E bz $?L0047 ;[INF] 2, 4 + 2225 2225 ; line 329 : { + 2226 2226 00358 ??bb00_PM_BL_set: + 2227 2227 ; line 330 : blset |= PM_REG_BIT_BL_U; + 2228 2228 $DGL 0,17 + 2229 2229 00358 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2230 2230 0035A 6C01 or a,#01H ; 1 ;[INF] 2, 1 + 2231 2231 0035C 9C03 mov [hl+3],a ; blset ;[INF] 2, 1 + 2232 2232 ; line 331 : intset |= REG_BIT_BL_U_ON; + 2233 2233 $DGL 0,18 + 2234 2234 0035E 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1 + 2235 2235 00360 6C20 or a,#020H ; 32 ;[INF] 2, 1 + 2236 2236 00362 9C02 mov [hl+2],a ; intset ;[INF] 2, 1 + 2237 2237 00364 ??eb00_PM_BL_set: + 2238 2238 ; line 332 : } + 2239 2239 $DGL 0,19 + 2240 2240 00364 EF13 br $?L0049 ;[INF] 2, 3 + 2241 2241 00366 ?L0047: + 2242 2242 ; line 333 : else if(( dat & REG_BIT_CMD_BL_U_OFF ) != 0 ) + 2243 2243 $DGL 0,20 + 2244 2244 00366 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1 + 2245 2245 00368 5C10 and a,#010H ; 16 ;[INF] 2, 1 + 2246 2246 0036A D1 cmp0 a ;[INF] 1, 1 + 2247 2247 0036B DD0C bz $?L0049 ;[INF] 2, 4 + 2248 2248 ; line 334 : { + 2249 2249 0036D ??bb01_PM_BL_set: + 2250 2250 ; line 335 : blset &= ~PM_REG_BIT_BL_U; + 2251 2251 $DGL 0,22 + 2252 2252 0036D 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2253 2253 0036F 5CFE and a,#0FEH ; 254 ;[INF] 2, 1 + 2254 2254 00371 9C03 mov [hl+3],a ; blset ;[INF] 2, 1 + 2255 2255 ; line 336 : intset |= REG_BIT_BL_U_OFF; + 2256 2256 $DGL 0,23 + 2257 2257 00373 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1 + 2258 2258 00375 6C10 or a,#010H ; 16 ;[INF] 2, 1 + 2259 2259 00377 9C02 mov [hl+2],a ; intset ;[INF] 2, 1 + 2260 2260 00379 ??eb01_PM_BL_set: + 2261 2261 ; line 337 : } + 2262 2262 00379 ?L0049: + 2263 2263 ; line 338 : + 2264 2264 ; line 339 : // shita + 2265 2265 ; line 340 : if(( dat & REG_BIT_CMD_BL_L_ON ) != 0 ) + 2266 2266 $DGL 0,27 + 2267 2267 00379 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1 + 2268 2268 0037B 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 2269 2269 0037D D1 cmp0 a ;[INF] 1, 1 + 2270 2270 0037E DD0E bz $?L0051 ;[INF] 2, 4 + 2271 2271 ; line 341 : { + 2272 2272 00380 ??bb02_PM_BL_set: + 2273 2273 ; line 342 : blset |= PM_REG_BIT_BL_L; + 2274 2274 $DGL 0,29 + 2275 2275 00380 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2276 2276 00382 6C02 or a,#02H ; 2 ;[INF] 2, 1 + 2277 2277 00384 9C03 mov [hl+3],a ; blset ;[INF] 2, 1 + 2278 2278 ; line 343 : intset |= REG_BIT_BL_L_ON; + 2279 2279 $DGL 0,30 + 2280 2280 00386 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1 + 2281 2281 00388 6C08 or a,#08H ; 8 ;[INF] 2, 1 + 2282 2282 0038A 9C02 mov [hl+2],a ; intset ;[INF] 2, 1 + 2283 2283 0038C ??eb02_PM_BL_set: + 2284 2284 ; line 344 : } + 2285 2285 $DGL 0,31 + 2286 2286 0038C EF13 br $?L0053 ;[INF] 2, 3 + 2287 2287 0038E ?L0051: + 2288 2288 ; line 345 : else if(( dat & REG_BIT_CMD_BL_L_OFF ) != 0 ) + 2289 2289 $DGL 0,32 + 2290 2290 0038E 8C04 mov a,[hl+4] ; dat ;[INF] 2, 1 + 2291 2291 00390 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 2292 2292 00392 D1 cmp0 a ;[INF] 1, 1 + 2293 2293 00393 DD0C bz $?L0053 ;[INF] 2, 4 + 2294 2294 ; line 346 : { + 2295 2295 00395 ??bb03_PM_BL_set: + 2296 2296 ; line 347 : blset &= ~PM_REG_BIT_BL_L; + 2297 2297 $DGL 0,34 + 2298 2298 00395 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2299 2299 00397 5CFD and a,#0FDH ; 253 ;[INF] 2, 1 + 2300 2300 00399 9C03 mov [hl+3],a ; blset ;[INF] 2, 1 + 2301 2301 ; line 348 : intset |= REG_BIT_BL_L_OFF; + 2302 2302 $DGL 0,35 + 2303 2303 0039B 8C02 mov a,[hl+2] ; intset ;[INF] 2, 1 + 2304 2304 0039D 6C04 or a,#04H ; 4 ;[INF] 2, 1 + 2305 2305 0039F 9C02 mov [hl+2],a ; intset ;[INF] 2, 1 + 2306 2306 003A1 ??eb03_PM_BL_set: + 2307 2307 ; line 349 : } + 2308 2308 003A1 ?L0053: + 2309 2309 ; line 350 : + 2310 2310 ; line 351 : /* + 2311 2311 ; line 352 : SoCがPWMを出すようレジスタをセットしてから遅延が有るため、ステー + 2312 2312 ; タスを先に + 2313 2313 ; line 353 : 更新してしまう。 + 2314 2314 ; line 354 : // Write + 2315 2315 ; line 355 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); + 2316 2316 ; line 356 : if( blset != 0x00 ){ + 2317 2317 ; line 357 : wait_ms( 10 ); + 2318 2318 ; line 358 : } + 2319 2319 ; line 359 : */ + 2320 2320 ; line 360 : vreg_ctr[VREG_C_STATUS] = (( vreg_ctr[VREG_C_STATUS] & 0b100 + 2321 2321 ; 11111 ) + 2322 2322 ; line 361 : | (( blset << 6 ) | ( blset << 4 ) + 2323 2323 ; ) & 0b01100000 ); + 2324 2324 $DGL 0,48 + 2325 2325 003A1 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 2326 2326 003A4 5C9F and a,#09FH ; 159 ;[INF] 2, 1 + 2327 2327 003A6 72 mov c,a ;[INF] 1, 1 + 2328 2328 003A7 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2329 2329 003A9 318E shrw ax,8 ;[INF] 2, 1 + 2330 2330 003AB 316D shlw ax,6 ;[INF] 2, 1 + 2331 2331 003AD 14 movw de,ax ;[INF] 1, 1 + 2332 2332 003AE 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2333 2333 003B0 318E shrw ax,8 ;[INF] 2, 1 + 2334 2334 003B2 314D shlw ax,4 ;[INF] 2, 1 + 2335 2335 003B4 616D or a,d ;[INF] 2, 1 + 2336 2336 003B6 08 xch a,x ;[INF] 1, 1 + 2337 2337 003B7 616C or a,e ;[INF] 2, 1 + 2338 2338 003B9 5C60 and a,#060H ; 96 ;[INF] 2, 1 + 2339 2339 003BB 6162 or c,a ;[INF] 2, 1 + 2340 2340 003BD 62 mov a,c ;[INF] 1, 1 + 2341 2341 003BE R9F0F00 mov !_vreg_ctr+15,a ;[INF] 3, 1 + 2342 2342 ; line 362 : // PMICのBLのビットと、MCUのSTATUSレジスタのビット位置が逆な + 2343 2343 ; ため入れ替え + 2344 2344 ; line 363 : + 2345 2345 ; line 364 : { + 2346 2346 003C1 ??bb04_PM_BL_set: + 2347 2347 ; line 365 : u8 tot; + 2348 2348 ; line 366 : + 2349 2349 ; line 367 : if( ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 ) + 2350 2350 $DGL 0,54 + 2351 2351 003C1 R8F1B00 mov a,!_vreg_ctr+27 ;[INF] 3, 1 + 2352 2352 003C4 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1 + 2353 2353 003C6 50FF mov x,#0FFH ; 255 ;[INF] 2, 1 + 2354 2354 003C8 5E02 and a,[hl+2] ; intset ;[INF] 2, 1 + 2355 2355 003CA D1 cmp0 a ;[INF] 1, 1 + 2356 2356 003CB DD22 bz $?L0055 ;[INF] 2, 4 + 2357 2357 ; line 368 : { + 2358 2358 003CD ??bb05_PM_BL_set: + 2359 2359 ; line 369 : vreg_ctr[ VREG_C_IRQ3 ] |= ( intset & ~vreg_ctr[ VRE + 2360 2360 ; G_C_IRQ_MASK3 ] ); + 2361 2361 $DGL 0,56 + 2362 2362 003CD R8F1B00 mov a,!_vreg_ctr+27 ;[INF] 3, 1 + 2363 2363 003D0 7CFF xor a,#0FFH ; 255 ;[INF] 2, 1 + 2364 2364 003D2 5E02 and a,[hl+2] ; intset ;[INF] 2, 1 + 2365 2365 003D4 RFD1900 call !bs_S0152 ;[INF] 3, 3 + 2366 2366 ; line 370 : IRQ0_neg; + 2367 2367 $DGL 0,57 + 2368 2368 003D7 ??bb06_PM_BL_set: + 2369 2369 003D7 716A27 set1 PM7.6 ;[INF] 3, 2 + 2370 2370 003DA ??eb06_PM_BL_set: + 2371 2371 ; line 371 : tot = 0; + 2372 2372 $DGL 0,58 + 2373 2373 003DA CC0100 mov [hl+1],#00H ; tot,0 ;[INF] 3, 1 + 2374 2374 ; line 372 : while( !IRQ0 && ( ++tot != 0 ) ){;} // 割り込みを入 + 2375 2375 ; れ直す + 2376 2376 $DGL 0,59 + 2377 2377 003DD ?L0057: + 2378 2378 003DD 31620708 bt P7.6,$?L0058 ;[INF] 4, 5 + 2379 2379 003E1 615901 inc [hl+1] ; tot ;[INF] 3, 2 + 2380 2380 003E4 8C01 mov a,[hl+1] ; tot ;[INF] 2, 1 + 2381 2381 003E6 D1 cmp0 a ;[INF] 1, 1 + 2382 2382 003E7 DFF4 bnz $?L0057 ;[INF] 2, 4 + 2383 2383 003E9 ??bb07_PM_BL_set: + 2384 2384 003E9 ??eb07_PM_BL_set: + 2385 2385 003E9 ?L0058: + 2386 2386 ; line 373 : IRQ0_ast; + 2387 2387 $DGL 0,60 + 2388 2388 003E9 ??bb08_PM_BL_set: + 2389 2389 003E9 716307 clr1 P7.6 ;[INF] 3, 2 + 2390 2390 003EC 716B27 clr1 PM7.6 ;[INF] 3, 2 + 2391 2391 003EF ??eb08_PM_BL_set: + 2392 2392 003EF ??eb05_PM_BL_set: + 2393 2393 ; line 374 : } + 2394 2394 003EF ?L0055: + 2395 2395 003EF ??eb04_PM_BL_set: + 2396 2396 ; line 375 : } + 2397 2397 ; line 376 : + 2398 2398 ; line 377 : // Write + 2399 2399 ; line 378 : if( blset != 0 ) // BLを付ける場合はウェイトを挟まないとPWM + 2400 2400 ; が来ておらず + 2401 2401 $DGL 0,65 + 2402 2402 003EF 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2403 2403 003F1 D1 cmp0 a ;[INF] 1, 1 + 2404 2404 003F2 DD06 bz $?L0059 ;[INF] 2, 4 + 2405 2405 ; line 379 : /// シャットダウンすることがある + 2406 2406 ; line 380 : { + 2407 2407 003F4 ??bb09_PM_BL_set: + 2408 2408 ; line 381 : wait_ms( 10 ); + 2409 2409 $DGL 0,68 + 2410 2410 003F4 300A00 movw ax,#0AH ; 10 ;[INF] 3, 1 + 2411 2411 003F7 RFD0000 call !_wait_ms ;[INF] 3, 3 + 2412 2412 003FA ??eb09_PM_BL_set: + 2413 2413 ; line 382 : } + 2414 2414 003FA ?L0059: + 2415 2415 ; line 383 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, blset ); + 2416 2416 $DGL 0,70 + 2417 2417 003FA 8C03 mov a,[hl+3] ; blset ;[INF] 2, 1 + 2418 2418 003FC 318E shrw ax,8 ;[INF] 2, 1 + 2419 2419 003FE C1 push ax ;[INF] 1, 1 + 2420 2420 003FF 5004 mov x,#04H ; 4 ;[INF] 2, 1 + 2421 2421 00401 C1 push ax ;[INF] 1, 1 + 2422 2422 00402 RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2423 2423 00405 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2424 2424 ; line 384 : + 2425 2425 ; line 385 : return( ERR_SUCCESS ); // ここでは異常チェック不要 + 2426 2426 $DGL 0,72 + 2427 2427 00407 F7 clrw bc ;[INF] 1, 1 + 2428 2428 ; line 386 : } + 2429 2429 $DGL 0,73 + 2430 2430 00408 ??ef_PM_BL_set: + 2431 2431 00408 1006 addw sp,#06H ;[INF] 2, 1 + 2432 2432 0040A C6 pop hl ;[INF] 1, 1 + 2433 2433 0040B D7 ret ;[INF] 1, 6 + 2434 2434 0040C ??ee_PM_BL_set: + 2435 2435 ; line 387 : + 2436 2436 ; line 388 : + 2437 2437 ; line 389 : + 2438 2438 ; line 390 : /* ======================================================== + 2439 2439 ; line 391 : 液晶の対向電圧の設定を行います。 + 2440 2440 ; line 392 : 仮想レジスタの内容を送るだけ + 2441 2441 ; line 393 : ======================================================== */ + 2442 2442 ; line 394 : err PM_LCD_vcom_set( ) + 2443 2443 ; line 395 : { + 2444 2444 0040C _PM_LCD_vcom_set: + 2445 2445 $DGL 1,274 + 2446 2446 0040C C7 push hl ;[INF] 1, 1 + 2447 2447 0040D ??bf_PM_LCD_vcom_set: + 2448 2448 ; line 396 : u8 rv; + 2449 2449 ; line 397 : + 2450 2450 ; line 398 : rv = iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DAC + 2451 2451 ; 1, vreg_ctr[VREG_C_VCOM_T] ); // がっかりなことに、PMICはバース + 2452 2452 ; ト書き込み不可 + 2453 2453 $DGL 0,4 + 2454 2454 0040D RD90300 mov x,!_vreg_ctr+3 ;[INF] 3, 1 + 2455 2455 00410 F1 clrb a ;[INF] 1, 1 + 2456 2456 00411 C1 push ax ;[INF] 1, 1 + 2457 2457 00412 5006 mov x,#06H ; 6 ;[INF] 2, 1 + 2458 2458 00414 C1 push ax ;[INF] 1, 1 + 2459 2459 00415 RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2460 2460 00418 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2461 2461 0041A 62 mov a,c ;[INF] 1, 1 + 2462 2462 0041B 76 mov l,a ;[INF] 1, 1 + 2463 2463 ; line 399 : rv |= iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_DA + 2464 2464 ; C2, vreg_ctr[VREG_C_VCOM_B] ); + 2465 2465 $DGL 0,5 + 2466 2466 0041C RD90400 mov x,!_vreg_ctr+4 ;[INF] 3, 1 + 2467 2467 0041F F1 clrb a ;[INF] 1, 1 + 2468 2468 00420 C1 push ax ;[INF] 1, 1 + 2469 2469 00421 5007 mov x,#07H ; 7 ;[INF] 2, 1 + 2470 2470 00423 C1 push ax ;[INF] 1, 1 + 2471 2471 00424 RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2472 2472 00427 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2473 2473 00429 62 mov a,c ;[INF] 1, 1 + 2474 2474 0042A 6166 or l,a ;[INF] 2, 1 + 2475 2475 ; line 400 : return ( rv ); + 2476 2476 $DGL 0,6 + 2477 2477 0042C 17 movw ax,hl ;[INF] 1, 1 + 2478 2478 0042D F1 clrb a ;[INF] 1, 1 + 2479 2479 0042E 12 movw bc,ax ;[INF] 1, 1 + 2480 2480 ; line 401 : } + 2481 2481 $DGL 0,7 + 2482 2482 0042F ??ef_PM_LCD_vcom_set: + 2483 2483 0042F C6 pop hl ;[INF] 1, 1 + 2484 2484 00430 D7 ret ;[INF] 1, 6 + 2485 2485 00431 ??ee_PM_LCD_vcom_set: + 2486 2486 ; line 402 : + 2487 2487 ; line 403 : + 2488 2488 ; line 404 : + 2489 2489 ; line 405 : #else + 2490 2490 ; line 406 : // パラディウム上のSoCでチェックしたいとき、PMICも液晶もつながっ + 2491 2491 ; てないので + 2492 2492 ; line 407 : // 異常終了しないようにダミー関数にする + 2493 2493 ; line 408 : err PM_LCD_on( ) + 2494 2494 ; line 409 : { + 2495 2495 ; line 410 : vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW; + 2496 2496 ; line 411 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON ); + 2497 2497 ; line 412 : SND_DEPOP_DEACT; // 1でミュート + 2498 2498 ; line 413 : return ( ERR_SUCCESS ); + 2499 2499 ; line 414 : } + 2500 2500 ; line 415 : + 2501 2501 ; line 416 : + 2502 2502 ; line 417 : void PM_LCD_off( ) + 2503 2503 ; line 418 : { + 2504 2504 ; line 419 : SND_DEPOP_ACT; + 2505 2505 ; line 420 : vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW; + 2506 2506 ; line 421 : set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF ); + 2507 2507 ; line 422 : } + 2508 2508 ; line 423 : + 2509 2509 ; line 424 : + 2510 2510 ; line 425 : err PM_BL_set( u8 ) + 2511 2511 ; line 426 : { + 2512 2512 ; line 427 : wait_ms( 10 ); + 2513 2513 ; line 428 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & ~( + 2514 2514 ; REG_BIT_BL_U | REG_BIT_BL_L ) + 2515 2515 ; line 429 : | ( command_bl_set & REG_BIT_CMD_BL_U_ON )? REG_BIT_BL_U + 2516 2516 ; line 430 : | ( command_bl_set & REG_BIT_CMD_BL_L_ON )? REG_BIT_BL_L + 2517 2517 ; line 431 : ); + 2518 2518 ; line 432 : return ( PM_chk_LDSW( ) ); + 2519 2519 ; line 433 : } + 2520 2520 ; line 434 : + 2521 2521 ; line 435 : + 2522 2522 ; line 436 : err PM_LCD_vcom_set( ) + 2523 2523 ; line 437 : { + 2524 2524 ; line 438 : return ( ERR_SUCCESS ); + 2525 2525 ; line 439 : } + 2526 2526 ; line 440 : + 2527 2527 ; line 441 : #endif + 2528 2528 ; line 442 : + 2529 2529 ; line 443 : + 2530 2530 ; line 444 : + 2531 2531 ; line 445 : /* ======================================================== + 2532 2532 ; line 446 : ↑で、レジスタ書き込みから呼び出される時のため + 2533 2533 ; line 447 : 　I2Cの取り合いの関係でここから呼ぶ + 2534 2534 ; line 448 : ======================================================== */ + 2535 2535 ; line 449 : task_status_immed tski_vcom_set( ) + 2536 2536 ; line 450 : { + 2537 2537 00431 _tski_vcom_set: + 2538 2538 $DGL 1,281 + 2539 2539 00431 ??bf_tski_vcom_set: + 2540 2540 ; line 451 : PM_LCD_vcom_set( ); + 2541 2541 $DGL 0,2 + 2542 2542 00431 RFD0C04 call !_PM_LCD_vcom_set ;[INF] 3, 3 + 2543 2543 ; line 452 : return ( ERR_FINISED ); + 2544 2544 $DGL 0,3 + 2545 2545 00434 F7 clrw bc ;[INF] 1, 1 + 2546 2546 ; line 453 : } + 2547 2547 $DGL 0,4 + 2548 2548 00435 ??ef_tski_vcom_set: + 2549 2549 00435 D7 ret ;[INF] 1, 6 + 2550 2550 00436 ??ee_tski_vcom_set: + 2551 2551 ; line 454 : + 2552 2552 ; line 455 : + 2553 2553 ; line 456 : + 2554 2554 ; line 457 : /* ======================================================== + 2555 2555 ; line 458 : シーケンスの通り電源を立ち上げてゆきます。 + 2556 2556 ; line 459 : 返値 0 最後まで正常に完了した。 + 2557 2557 ; line 460 : 1 ショートなどで電源があがりきらなかった + 2558 2558 ; line 461 : + 2559 2559 ; line 462 : 以下のピンは主にここで操作・監視されます。 + 2560 2560 ; line 463 : ・POW_CONT1,2 TEG電源のみ + 2561 2561 ; line 464 : ======================================================== */ + 2562 2562 ; line 465 : err PM_sys_pow_on( ) + 2563 2563 ; line 466 : { + 2564 2564 00436 _PM_sys_pow_on: + 2565 2565 $DGL 1,287 + 2566 2566 00436 C7 push hl ;[INF] 1, 1 + 2567 2567 00437 ??bf_PM_sys_pow_on: + 2568 2568 ; line 467 : #ifdef _PMIC_CTR_ + 2569 2569 ; line 468 : u8 temp; + 2570 2570 ; line 469 : + 2571 2571 ; line 470 : // 電池温度測定 + 2572 2572 ; line 471 : while( ADCEN != 0 ) + 2573 2573 $DGL 0,6 + 2574 2574 00437 ?L0067: + 2575 2575 00437 C7 push hl ;[INF] 1, 1 + 2576 2576 00438 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1 + 2577 2577 0043B 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 + 2578 2578 0043D C6 pop hl ;[INF] 1, 1 + 2579 2579 0043E DCF7 bc $?L0067 ;[INF] 2, 4 + 2580 2580 ; line 472 : {; + 2581 2581 00440 ??bb00_PM_sys_pow_on: + 2582 2582 00440 ??eb00_PM_sys_pow_on: + 2583 2583 ; line 473 : } + 2584 2584 ; line 474 : BT_TEMP_P = 1; + 2585 2585 $DGL 0,9 + 2586 2586 00440 717201 set1 P1.7 ;[INF] 3, 2 + 2587 2587 ; line 475 : vreg_ctr[VREG_C_BT_TEMP] = get_adc( ADC_SEL_BATT_TEMP ); + 2588 2588 $DGL 0,10 + 2589 2589 00443 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 2590 2590 00446 RFD0000 call !_get_adc ;[INF] 3, 3 + 2591 2591 00449 62 mov a,c ;[INF] 1, 1 + 2592 2592 0044A R9F0A00 mov !_vreg_ctr+10,a ;[INF] 3, 1 + 2593 2593 ; line 476 : BT_TEMP_P = 0; + 2594 2594 $DGL 0,11 + 2595 2595 0044D 717301 clr1 P1.7 ;[INF] 3, 2 + 2596 2596 ; line 477 : PM_bt_temp_update( ); // 温度のtemp。　残量ICに行きます + 2597 2597 $DGL 0,12 + 2598 2598 00450 RFDCE01 call !_PM_bt_temp_update ;[INF] 3, 3 + 2599 2599 ; line 478 : + 2600 2600 ; line 479 : // 残量チェック + 2601 2601 ; line 480 : PM_get_batt_left(); // 先に、PM_init()が実行されてい + 2602 2602 ; る必要があります。(大丈夫) + 2603 2603 $DGL 0,15 + 2604 2604 00453 RFD2106 call !_PM_get_batt_left ;[INF] 3, 3 + 2605 2605 ; line 481 : // todo: batt remain -> volatage? + 2606 2606 ; line 482 : if( vreg_ctr[VREG_C_BT_REMAIN] < 0 ) + 2607 2607 $DGL 0,17 + 2608 2608 00456 RD50B00 cmp0 !_vreg_ctr+11 ;[INF] 3, 1 + 2609 2609 00459 DE03 bnc $?L0069 ;[INF] 2, 4 + 2610 2610 ; line 483 : { + 2611 2611 0045B ??bb01_PM_sys_pow_on: + 2612 2612 ; line 484 : return ( 1 ); + 2613 2613 $DGL 0,19 + 2614 2614 0045B E7 onew bc ;[INF] 1, 1 + 2615 2615 0045C EF49 br $?L0066 ;[INF] 2, 3 + 2616 2616 0045E ??eb01_PM_sys_pow_on: + 2617 2617 ; line 485 : } + 2618 2618 0045E ?L0069: + 2619 2619 ; line 486 : + 2620 2620 ; line 487 : // 電源順次立ち上げ + 2621 2621 ; line 488 : // PM_reset_ast( ); 不要 PM_LDSW_onまかせ + 2622 2622 ; line 489 : RESET2_ast; + 2623 2623 $DGL 0,24 + 2624 2624 0045E ??bb02_PM_sys_pow_on: + 2625 2625 0045E 711300 clr1 P0.1 ;[INF] 3, 2 + 2626 2626 00461 711B20 clr1 PM0.1 ;[INF] 3, 2 + 2627 2627 00464 ??eb02_PM_sys_pow_on: + 2628 2628 ; line 490 : FCRAM_RST_ast; + 2629 2629 $DGL 0,25 + 2630 2630 00464 ??bb03_PM_sys_pow_on: + 2631 2631 00464 710303 clr1 P3.0 ;[INF] 3, 2 + 2632 2632 00467 ??eb03_PM_sys_pow_on: + 2633 2633 ; line 491 : + 2634 2634 ; line 492 : PM_LDSW_on( ); + 2635 2635 $DGL 0,27 + 2636 2636 00467 RFD5300 call !bs_F0148 ;[INF] 3, 3 + 2637 2637 ; line 493 : + 2638 2638 ; line 494 : wait_ms( 1 ); + 2639 2639 $DGL 0,29 + 2640 2640 0046A E6 onew ax ;[INF] 1, 1 + 2641 2641 0046B RFD0000 call !_wait_ms ;[INF] 3, 3 + 2642 2642 ; line 495 : #ifdef _PM_BUG_ + 2643 2643 ; line 496 : iic_mcu_write_a_byte( IIC_SLA_PMIC, 0x22, 0xCA ); // バグ持 + 2644 2644 ; ちPMIC対策 OVP解除 + 2645 2645 ; line 497 : #endif + 2646 2646 ; line 498 : + 2647 2647 ; line 499 : wait_ms( DELAY_PM_TW_PWUP ); + 2648 2648 $DGL 0,34 + 2649 2649 0046E RFD0A00 call !bs_F0155 ;[INF] 3, 3 + 2650 2650 ; line 500 : + 2651 2651 ; line 501 : PM_VDD_on( ); + 2652 2652 $DGL 0,36 + 2653 2653 00471 300F00 movw ax,#0FH ; 15 ;[INF] 3, 1 + 2654 2654 00474 RFD2E00 call !bs_F0150 ;[INF] 3, 3 + 2655 2655 ; line 502 : wait_ms( DELAY_PM_TW_PWUP ); + 2656 2656 $DGL 0,37 + 2657 2657 00477 RFD0A00 call !bs_F0155 ;[INF] 3, 3 + 2658 2658 ; line 503 : + 2659 2659 ; line 504 : PM_VDD50A_on( ); // 液晶電源ではなく、ledとかに使うものです + 2660 2660 $DGL 0,39 + 2661 2661 0047A 301F00 movw ax,#01FH ; 31 ;[INF] 3, 1 + 2662 2662 0047D RFD2E00 call !bs_F0150 ;[INF] 3, 3 + 2663 2663 ; line 505 : + 2664 2664 ; line 506 : wait_ms( DELAY_PM_TW_PWUP ); + 2665 2665 $DGL 0,41 + 2666 2666 00480 RFD0A00 call !bs_F0155 ;[INF] 3, 3 + 2667 2667 ; line 507 : + 2668 2668 ; line 508 : PM_VDD_normMode(); + 2669 2669 $DGL 0,43 + 2670 2670 00483 F6 clrw ax ;[INF] 1, 1 + 2671 2671 00484 C1 push ax ;[INF] 1, 1 + 2672 2672 00485 5005 mov x,#05H ; 5 ;[INF] 2, 1 + 2673 2673 00487 C1 push ax ;[INF] 1, 1 + 2674 2674 00488 RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2675 2675 0048B 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2676 2676 ; line 509 : #ifdef _PM_BUG_ + 2677 2677 ; line 510 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_POW_SAVE, 0x + 2678 2678 ; 03 ); // バグ持ちPMIC対策 強制PWM + 2679 2679 ; line 511 : #endif + 2680 2680 ; line 512 : if( PM_chk_LDSW( ) == 0 ) + 2681 2681 $DGL 0,47 + 2682 2682 0048D RFD4500 call !bs_F0147 ;[INF] 3, 3 + 2683 2683 00490 D1 cmp0 a ;[INF] 1, 1 + 2684 2684 00491 DF03 bnz $?L0071 ;[INF] 2, 4 + 2685 2685 ; line 513 : { + 2686 2686 00493 ??bb04_PM_sys_pow_on: + 2687 2687 ; line 514 : return ( ERR_ERR ); + 2688 2688 $DGL 0,49 + 2689 2689 00493 E7 onew bc ;[INF] 1, 1 + 2690 2690 00494 EF11 br $?L0066 ;[INF] 2, 3 + 2691 2691 00496 ??eb04_PM_sys_pow_on: + 2692 2692 ; line 515 : } + 2693 2693 00496 ?L0071: + 2694 2694 ; line 516 : FCRAM_RST_neg; + 2695 2695 $DGL 0,51 + 2696 2696 00496 ??bb05_PM_sys_pow_on: + 2697 2697 00496 710203 set1 P3.0 ;[INF] 3, 2 + 2698 2698 00499 ??eb05_PM_sys_pow_on: + 2699 2699 ; line 517 : PM_reset_neg(); + 2700 2700 $DGL 0,52 + 2701 2701 00499 300300 movw ax,#03H ; 3 ;[INF] 3, 1 + 2702 2702 0049C C1 push ax ;[INF] 1, 1 + 2703 2703 0049D C1 push ax ;[INF] 1, 1 + 2704 2704 0049E RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2705 2705 004A1 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2706 2706 ; line 518 : RESET2_neg; + 2707 2707 $DGL 0,53 + 2708 2708 004A3 ??bb06_PM_sys_pow_on: + 2709 2709 004A3 711A20 set1 PM0.1 ;[INF] 3, 2 + 2710 2710 004A6 ??eb06_PM_sys_pow_on: + 2711 2711 ; line 519 : /* + 2712 2712 ; line 520 : wait_ms( 100 ); + 2713 2713 ; line 521 : { + 2714 2714 ; line 522 : // CODEC 不定レジスタ初期化 + 2715 2715 ; line 523 : u8 codec_reg_init[3] = { 0,0,0 }; + 2716 2716 ; line 524 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg + 2717 2717 ; _init ); + 2718 2718 ; line 525 : } + 2719 2719 ; line 526 : */ + 2720 2720 ; line 527 : + 2721 2721 ; line 528 : #else + 2722 2722 ; line 529 : // TWL PMIC + 2723 2723 ; line 530 : u8 temp; + 2724 2724 ; line 531 : + 2725 2725 ; line 532 : // 電源投入 + 2726 2726 ; line 533 : PM_reset_ast(); + 2727 2727 ; line 534 : RESET2_ast; + 2728 2728 ; line 535 : FCRAM_RST_ast; + 2729 2729 ; line 536 : + 2730 2730 ; line 537 : PM_TEG_PWSW = 1; + 2731 2731 ; line 538 : wait_ms( 160 ); + 2732 2732 ; line 539 : PM_TEG_PWSW = 0; + 2733 2733 ; line 540 : + 2734 2734 ; line 541 : + 2735 2735 ; line 542 : // 残量確認 + 2736 2736 ; line 543 : temp = 99; + 2737 2737 ; line 544 : if( temp < 5 ) + 2738 2738 ; line 545 : { + 2739 2739 ; line 546 : return ( ERR_ERR ); + 2740 2740 ; line 547 : } + 2741 2741 ; line 548 : vreg_ctr[VREG_C_BT_REMAIN] = temp; + 2742 2742 ; line 549 : FCRAM_RST_neg; + 2743 2743 ; line 550 : PM_reset_neg(); + 2744 2744 ; line 551 : RESET2_neg; + 2745 2745 ; line 552 : wait_ms( 100 ); + 2746 2746 ; line 553 : if( !RESET1_n ) + 2747 2747 ; line 554 : { + 2748 2748 ; line 555 : // 起動失敗 + 2749 2749 ; line 556 : PM_reset_ast(); + 2750 2750 ; line 557 : RESET2_ast; + 2751 2751 ; line 558 : FCRAM_RST_ast; + 2752 2752 ; line 559 : return ( ERR_ERR ); + 2753 2753 ; line 560 : } + 2754 2754 ; line 561 : /* + 2755 2755 ; line 562 : { // CODEC 不定レジスタ初期化 + 2756 2756 ; line 563 : u8 codec_reg_init[3] = { 0,0,0 }; + 2757 2757 ; line 564 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg + 2758 2758 ; _init ); + 2759 2759 ; line 565 : } + 2760 2760 ; line 566 : */ + 2761 2761 ; line 567 : #endif + 2762 2762 ; line 568 : + 2763 2763 ; line 569 : return ( ERR_SUCCESS ); + 2764 2764 $DGL 0,104 + 2765 2765 004A6 F7 clrw bc ;[INF] 1, 1 + 2766 2766 ; line 570 : } + 2767 2767 004A7 ?L0066: + 2768 2768 $DGL 0,105 + 2769 2769 004A7 ??ef_PM_sys_pow_on: + 2770 2770 004A7 C6 pop hl ;[INF] 1, 1 + 2771 2771 004A8 D7 ret ;[INF] 1, 6 + 2772 2772 004A9 ??ee_PM_sys_pow_on: + 2773 2773 ; line 571 : + 2774 2774 ; line 572 : + 2775 2775 ; line 573 : + 2776 2776 ; line 574 : + 2777 2777 ; line 575 : + 2778 2778 ; line 576 : + 2779 2779 ; line 577 : + 2780 2780 ; line 578 : /* ======================================================== + 2781 2781 ; line 579 : 電源OFFシーケンス + 2782 2782 ; line 580 : todo: 電源異常断の場合 + 2783 2783 ; line 581 : ======================================================== */ + 2784 2784 ; line 582 : err PM_sys_pow_off( ) + 2785 2785 ; line 583 : { + 2786 2786 004A9 _PM_sys_pow_off: + 2787 2787 $DGL 1,322 + 2788 2788 004A9 ??bf_PM_sys_pow_off: + 2789 2789 ; line 584 : #ifdef _PMIC_CTR_ + 2790 2790 ; line 585 : // PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF ); + 2791 2791 ; line 586 : // PM_LCD_off( ); // TCOM,VCS OFF も消してき + 2792 2792 ; ます。 + 2793 2793 ; line 587 : + 2794 2794 ; line 588 : PM_reset_ast( ); + 2795 2795 $DGL 0,6 + 2796 2796 004A9 RFD5300 call !bs_F0148 ;[INF] 3, 3 + 2797 2797 ; line 589 : RESET2_ast; + 2798 2798 $DGL 0,7 + 2799 2799 004AC ??bb00_PM_sys_pow_off: + 2800 2800 004AC 711300 clr1 P0.1 ;[INF] 3, 2 + 2801 2801 004AF 711B20 clr1 PM0.1 ;[INF] 3, 2 + 2802 2802 004B2 ??eb00_PM_sys_pow_off: + 2803 2803 ; line 590 : FCRAM_RST_ast; + 2804 2804 $DGL 0,8 + 2805 2805 004B2 ??bb01_PM_sys_pow_off: + 2806 2806 004B2 710303 clr1 P3.0 ;[INF] 3, 2 + 2807 2807 004B5 ??eb01_PM_sys_pow_off: + 2808 2808 ; line 591 : + 2809 2809 ; line 592 : PM_off( ); + 2810 2810 $DGL 0,10 + 2811 2811 004B5 F6 clrw ax ;[INF] 1, 1 + 2812 2812 004B6 RFD2E00 call !bs_F0150 ;[INF] 3, 3 + 2813 2813 ; line 593 : + 2814 2814 ; line 594 : PM_LDSW_off( ); + 2815 2815 $DGL 0,12 + 2816 2816 004B9 F6 clrw ax ;[INF] 1, 1 + 2817 2817 004BA C1 push ax ;[INF] 1, 1 + 2818 2818 004BB 5003 mov x,#03H ; 3 ;[INF] 2, 1 + 2819 2819 004BD C1 push ax ;[INF] 1, 1 + 2820 2820 004BE RFD0500 call !bs_F0154 ;[INF] 3, 3 + 2821 2821 004C1 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 2822 2822 ; line 595 : #else + 2823 2823 ; line 596 : + 2824 2824 ; line 597 : if( RESET1_n ) + 2825 2825 ; line 598 : { + 2826 2826 ; line 599 : PM_reset_ast(); + 2827 2827 ; line 600 : RESET2_ast; + 2828 2828 ; line 601 : FCRAM_RST_ast; + 2829 2829 ; line 602 : PM_TEG_PWSW = 1; + 2830 2830 ; line 603 : wait_ms( 250 ); + 2831 2831 ; line 604 : wait_ms( 250 ); + 2832 2832 ; line 605 : wait_ms( 250 ); + 2833 2833 ; line 606 : PM_TEG_PWSW = 0; + 2834 2834 ; line 607 : } + 2835 2835 ; line 608 : PM_reset_ast(); + 2836 2836 ; line 609 : RESET2_ast; + 2837 2837 ; line 610 : FCRAM_RST_ast; + 2838 2838 ; line 611 : + 2839 2839 ; line 612 : #endif + 2840 2840 ; line 613 : return ( ERR_SUCCESS ); + 2841 2841 $DGL 0,31 + 2842 2842 004C3 F7 clrw bc ;[INF] 1, 1 + 2843 2843 ; line 614 : } + 2844 2844 $DGL 0,32 + 2845 2845 004C4 ??ef_PM_sys_pow_off: + 2846 2846 004C4 D7 ret ;[INF] 1, 6 + 2847 2847 004C5 ??ee_PM_sys_pow_off: + 2848 2848 ; line 615 : + 2849 2849 ; line 616 : + 2850 2850 ; line 617 : + 2851 2851 ; line 618 : /* ======================================================== + 2852 2852 ; line 619 : 電池の管理 + 2853 2853 ; line 620 : + 2854 2854 ; line 621 : 以下のピンは主にここで操作・監視されます。 + 2855 2855 ; line 622 : ・PM_BT_AUTH 現状、GPI in + 2856 2856 ; line 623 : ・PM_CHARGE_n CCIC /CHG in + 2857 2857 ; line 624 : ・PM_CHARGE_ERR_n /FLT in + 2858 2858 ; line 625 : ・PM_EXTDC_n /DOK INTP4 in + 2859 2859 ; line 626 : ・PM_CHARGE_EN_n /CEN out + 2860 2860 ; line 627 : + 2861 2861 ; line 628 : 以下の物は関係ありそうですが別のところで主に監視されています。 + 2862 2862 ; line 629 : ・LED_Pow R, B, Charge tsk_LED + 2863 2863 ; line 630 : ・BT_TEMP,_P tsk_ADC + 2864 2864 ; line 631 : + 2865 2865 ; line 632 : PM_EXTDCは割り込みメインにするかも + 2866 2866 ; line 633 : ======================================================== */ + 2867 2867 ; line 634 : #define INTERVAL_TSK_BATT 250 + 2868 2868 ; line 635 : + 2869 2869 ; line 636 : void tsk_batt( ) + 2870 2870 ; line 637 : { + 2871 2871 004C5 _tsk_batt: + 2872 2872 $DGL 1,336 + 2873 2873 004C5 ??bf_tsk_batt: + 2874 2874 ; line 638 : static u8 task_interval = 0; + 2875 2875 ; line 639 : static u8 charge_hys = 0; // ヒステリシスで上限下限を拡張す + 2876 2876 ; るとき１ + 2877 2877 ; line 640 : static bit pm_extdc_old; + 2878 2878 ; line 641 : + 2879 2879 ; line 642 : if( task_interval-- != 0 ) + 2880 2880 $DGL 0,6 + 2881 2881 004C5 R8F0100 mov a,!?L0077 ; task_interval ;[INF] 3, 1 + 2882 2882 004C8 RB00100 dec !?L0077 ; task_interval ;[INF] 3, 2 + 2883 2883 004CB D1 cmp0 a ;[INF] 1, 1 + 2884 2884 004CC 61E8 skz ;[INF] 2, 1 + 2885 2885 004CE RED6C05 br !?L0076 ;[INF] 3, 3 + 2886 2886 ; line 643 : { + 2887 2887 004D1 ??bb00_tsk_batt: + 2888 2888 ; line 644 : return; + 2889 2889 004D1 ??eb00_tsk_batt: + 2890 2890 ; line 645 : } + 2891 2891 ; line 646 : else + 2892 2892 ; line 647 : { + 2893 2893 004D1 ??bb01_tsk_batt: + 2894 2894 ; line 648 : task_interval = (u8)( INTERVAL_TSK_BATT / SYS_INTERVAL_T + 2895 2895 ; ICK ); + 2896 2896 $DGL 0,12 + 2897 2897 004D1 RCF010080 mov !?L0077,#080H ; task_interval,128 ;[INF] 4, 1 + 2898 2898 004D5 ??eb01_tsk_batt: + 2899 2899 ; line 649 : } + 2900 2900 ; line 650 : + 2901 2901 ; line 651 : + 2902 2902 ; line 652 : // アダプタ？ // + 2903 2903 ; line 653 : if( pm_extdc_old != !PM_EXTDC_n ) + 2904 2904 $DGL 0,17 + 2905 2905 004D5 710407 mov1 CY,P7.0 ;[INF] 3, 1 + 2906 2906 004D8 E6 onew ax ;[INF] 1, 1 + 2907 2907 004D9 6130 subc x,a ;[INF] 2, 1 + 2908 2908 004DB 12 movw bc,ax ;[INF] 1, 1 + 2909 2909 004DC F6 clrw ax ;[INF] 1, 1 + 2910 2910 004DD R710400 mov1 CY,?L0079 ;[INF] 3, 1 + 2911 2911 004E0 6110 addc x,a ;[INF] 2, 1 + 2912 2912 004E2 43 cmpw ax,bc ;[INF] 1, 1 + 2913 2913 004E3 DD2B bz $?L0085 ;[INF] 2, 4 + 2914 2914 ; line 654 : { + 2915 2915 004E5 ??bb02_tsk_batt: + 2916 2916 ; line 655 : pm_extdc_old = !PM_EXTDC_n; + 2917 2917 $DGL 0,19 + 2918 2918 004E5 710407 mov1 CY,P7.0 ;[INF] 3, 1 + 2919 2919 004E8 E6 onew ax ;[INF] 1, 1 + 2920 2920 004E9 6130 subc x,a ;[INF] 2, 1 + 2921 2921 004EB 60 mov a,x ;[INF] 1, 1 + 2922 2922 004EC 61FB rorc a,1 ;[INF] 2, 1 + 2923 2923 004EE R710100 mov1 ?L0079,CY ;[INF] 3, 2 + 2924 2924 ; line 656 : if( pm_extdc_old ) + 2925 2925 $DGL 0,20 + 2926 2926 004F1 R3104000F bf ?L0079,$?L0088 ;[INF] 4, 5 + 2927 2927 ; line 657 : { + 2928 2928 004F5 ??bb03_tsk_batt: + 2929 2929 ; line 658 : set_bit( 1, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP + 2930 2930 ; PLY ); + 2931 2931 $DGL 0,22 + 2932 2932 004F5 ??bb04_tsk_batt: + 2933 2933 004F5 ??bb05_tsk_batt: + 2934 2934 004F5 R71300F00 set1 !_vreg_ctr+15.3 ;[INF] 4, 2 + 2935 2935 004F9 ??eb05_tsk_batt: + 2936 2936 004F9 ??bb06_tsk_batt: + 2937 2937 004F9 ??eb06_tsk_batt: + 2938 2938 ; line 659 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_CONNECT ); + 2939 2939 $DGL 0,23 + 2940 2940 004F9 ??eb04_tsk_batt: + 2941 2941 004F9 E6 onew ax ;[INF] 1, 1 + 2942 2942 004FA A1 incw ax ;[INF] 1, 1 + 2943 2943 004FB C1 push ax ;[INF] 1, 1 + 2944 2944 004FC 5011 mov x,#011H ; 17 ;[INF] 2, 1 + 2945 2945 004FE RFD0000 call !_set_irq ;[INF] 3, 3 + 2946 2946 00501 C0 pop ax ;[INF] 1, 1 + 2947 2947 00502 ??eb03_tsk_batt: + 2948 2948 ; line 660 : } + 2949 2949 $DGL 0,24 + 2950 2950 00502 EF0C br $?L0085 ;[INF] 2, 3 + 2951 2951 ; line 661 : else + 2952 2952 ; line 662 : { + 2953 2953 00504 ??bb07_tsk_batt: + 2954 2954 ; line 663 : set_bit( 0, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUP + 2955 2955 ; PLY ); + 2956 2956 $DGL 0,27 + 2957 2957 00504 ??bb08_tsk_batt: + 2958 2958 00504 ??bb09_tsk_batt: + 2959 2959 00504 ??eb09_tsk_batt: + 2960 2960 00504 ?L0088: + 2961 2961 00504 ??bb0A_tsk_batt: + 2962 2962 00504 R71380F00 clr1 !_vreg_ctr+15.3 ;[INF] 4, 2 + 2963 2963 00508 ??eb0A_tsk_batt: + 2964 2964 00508 ??eb08_tsk_batt: + 2965 2965 ; line 664 : set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_DISC ); + 2966 2966 $DGL 0,28 + 2967 2967 00508 E6 onew ax ;[INF] 1, 1 + 2968 2968 00509 C1 push ax ;[INF] 1, 1 + 2969 2969 0050A 5011 mov x,#011H ; 17 ;[INF] 2, 1 + 2970 2970 0050C RFD0000 call !_set_irq ;[INF] 3, 3 + 2971 2971 0050F C0 pop ax ;[INF] 1, 1 + 2972 2972 00510 ??eb07_tsk_batt: + 2973 2973 ; line 665 : } + 2974 2974 00510 ?L0085: + 2975 2975 00510 ??eb02_tsk_batt: + 2976 2976 ; line 666 : } + 2977 2977 ; line 667 : + 2978 2978 ; line 668 : + 2979 2979 ; line 669 : // 充電 /////////////////////////// + 2980 2980 ; line 670 : // 温度付きヒステリシス + 2981 2981 ; line 671 : if( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) + 2982 2982 $DGL 0,35 + 2983 2983 00510 R400A0036 cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1 + 2984 2984 00514 61D8 sknc ;[INF] 2, 1 + 2985 2985 ; line 672 : { + 2986 2986 00516 ??bb0B_tsk_batt: + 2987 2987 ; line 673 : charge_hys = 1; + 2988 2988 $DGL 0,37 + 2989 2989 00516 RE50200 oneb !?L0078 ; charge_hys ;[INF] 3, 1 + 2990 2990 00519 ??eb0B_tsk_batt: + 2991 2991 ; line 674 : } + 2992 2992 00519 ?L0090: + 2993 2993 ; line 675 : + 2994 2994 ; line 676 : if( ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) + 2995 2995 ; line 677 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) + 2996 2996 $DGL 0,41 + 2997 2997 00519 R400A0002 cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1 + 2998 2998 0051D DC09 bc $?L0092 ;[INF] 2, 4 + 2999 2999 0051F R400A002C cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1 + 3000 3000 00523 61D8 sknc ;[INF] 2, 1 + 3001 3001 ; line 678 : { + 3002 3002 00525 ??bb0C_tsk_batt: + 3003 3003 ; line 679 : charge_hys = 0; + 3004 3004 $DGL 0,43 + 3005 3005 00525 RF50200 clrb !?L0078 ; charge_hys ;[INF] 3, 1 + 3006 3006 00528 ??eb0C_tsk_batt: + 3007 3007 ; line 680 : } + 3008 3008 00528 ?L0092: + 3009 3009 ; line 681 : + 3010 3010 ; line 682 : if( ( ( charge_hys == 1 ) + 3011 3011 ; line 683 : && ( 1 < vreg_ctr[VREG_C_BT_TEMP] ) + 3012 3012 ; line 684 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x2C ) ) + 3013 3013 ; line 685 : || + 3014 3014 $DGL 0,49 + 3015 3015 00528 R40020001 cmp !?L0078,#01H ; charge_hys,1 ;[INF] 4, 1 + 3016 3016 0052C DF0C bnz $?L0097 ;[INF] 2, 4 + 3017 3017 0052E R400A0002 cmp !_vreg_ctr+10,#02H ; 2 ;[INF] 4, 1 + 3018 3018 00532 DC06 bc $?L0097 ;[INF] 2, 4 + 3019 3019 00534 R400A002C cmp !_vreg_ctr+10,#02CH ; 44 ;[INF] 4, 1 + 3020 3020 00538 DC0B bc $?L0096 ;[INF] 2, 4 + 3021 3021 0053A ?L0097: + 3022 3022 ; line 686 : ( ( charge_hys == 0 ) + 3023 3023 $DGL 0,50 + 3024 3024 0053A RD50200 cmp0 !?L0078 ; charge_hys ;[INF] 3, 1 + 3025 3025 0053D DF0B bnz $?L0094 ;[INF] 2, 4 + 3026 3026 ; line 687 : && ( vreg_ctr[VREG_C_BT_TEMP] < 0x36 ) ) ) + 3027 3027 $DGL 0,51 + 3028 3028 0053F R400A0036 cmp !_vreg_ctr+10,#036H ; 54 ;[INF] 4, 1 + 3029 3029 00543 DE05 bnc $?L0094 ;[INF] 2, 4 + 3030 3030 00545 ?L0096: + 3031 3031 ; line 688 : { + 3032 3032 00545 ??bb0D_tsk_batt: + 3033 3033 ; line 689 : #ifndef _MODEL_WM0_ + 3034 3034 ; line 690 : BT_CHG_ENABLE(); // 温度範囲OKで充電再開 + 3035 3035 $DGL 0,54 + 3036 3036 00545 713304 clr1 P4.3 ;[INF] 3, 2 + 3037 3037 00548 ??eb0D_tsk_batt: + 3038 3038 ; line 691 : } + 3039 3039 $DGL 0,55 + 3040 3040 00548 EF03 br $?L0095 ;[INF] 2, 3 + 3041 3041 0054A ?L0094: + 3042 3042 ; line 692 : else + 3043 3043 ; line 693 : { + 3044 3044 0054A ??bb0E_tsk_batt: + 3045 3045 ; line 694 : BT_CHG_DISABLE(); // 温度危険！　充電停止 + 3046 3046 $DGL 0,58 + 3047 3047 0054A 713204 set1 P4.3 ;[INF] 3, 2 + 3048 3048 0054D ??eb0E_tsk_batt: + 3049 3049 ; line 695 : #endif + 3050 3050 ; line 696 : } + 3051 3051 0054D ?L0095: + 3052 3052 ; line 697 : #ifdef _MODEL_WM0_ + 3053 3053 ; line 698 : // CHG_ENABLEピンは /WL_RST に配線されているので + 3054 3054 ; line 699 : #endif + 3055 3055 ; line 700 : + 3056 3056 ; line 701 : // 充電 // + 3057 3057 ; line 702 : // →割り込み。miscの中でよろしくやってくれている。 + 3058 3058 ; line 703 : set_bit( !BT_CHG_n, vreg_ctr[VREG_C_STATUS], REG_BIT_BATT_CH + 3059 3059 ; ARGE ); + 3060 3060 $DGL 0,67 + 3061 3061 0054D ??bb0F_tsk_batt: + 3062 3062 0054D 31120506 bt P5.1,$?L0098 ;[INF] 4, 5 + 3063 3063 00551 ??bb10_tsk_batt: + 3064 3064 00551 R71400F00 set1 !_vreg_ctr+15.4 ;[INF] 4, 2 + 3065 3065 00555 ??eb10_tsk_batt: + 3066 3066 00555 EF04 br $?L0099 ;[INF] 2, 3 + 3067 3067 00557 ?L0098: + 3068 3068 00557 ??bb11_tsk_batt: + 3069 3069 00557 R71480F00 clr1 !_vreg_ctr+15.4 ;[INF] 4, 2 + 3070 3070 0055B ??eb11_tsk_batt: + 3071 3071 0055B ?L0099: + 3072 3072 0055B ??eb0F_tsk_batt: + 3073 3073 ; line 704 : LED_CHARGE = !BT_CHG_n ? 1 : 0; + 3074 3074 $DGL 0,68 + 3075 3075 0055B 31120503 bt P5.1,$?L0100 ;[INF] 4, 5 + 3076 3076 0055F E6 onew ax ;[INF] 1, 1 + 3077 3077 00560 EF01 br $?L0101 ;[INF] 2, 3 + 3078 3078 00562 ?L0100: + 3079 3079 00562 F6 clrw ax ;[INF] 1, 1 + 3080 3080 00563 ?L0101: + 3081 3081 00563 60 mov a,x ;[INF] 1, 1 + 3082 3082 00564 61FB rorc a,1 ;[INF] 2, 1 + 3083 3083 00566 714102 mov1 P2.4,CY ;[INF] 3, 2 + 3084 3084 ; line 705 : + 3085 3085 ; line 706 : + 3086 3086 ; line 707 : // 電池残量 // + 3087 3087 ; line 708 : PM_get_batt_left(); + 3088 3088 $DGL 0,72 + 3089 3089 00569 RFD2106 call !_PM_get_batt_left ;[INF] 3, 3 + 3090 3090 ; line 709 : + 3091 3091 ; line 710 : // dubug monitor + 3092 3092 ; line 711 : + 3093 3093 ; line 712 : return; + 3094 3094 ; line 713 : } + 3095 3095 0056C ?L0076: + 3096 3096 $DGL 0,77 + 3097 3097 0056C ??ef_tsk_batt: + 3098 3098 0056C D7 ret ;[INF] 1, 6 + 3099 3099 0056D ??ee_tsk_batt: + 3100 3100 ; line 714 : + 3101 3101 ; line 715 : + 3102 3102 ; line 716 : + 3103 3103 ; line 717 : + 3104 3104 ; line 718 : /*========================================================= + 3105 3105 ; line 719 : extDC割り込み + 3106 3106 ; line 720 : 電源OFFから起こす（充電の温度監視のため）のみ + 3107 3107 ; line 721 : 普段はポーリング(pm) + 3108 3108 ; line 722 : =========================================================*/ + 3109 3109 ; line 723 : __interrupt void intp4_extdc( ) + 3110 3110 ; line 724 : { + 3111 3111 + 3112 3112 ----- @@BASE CSEG BASE + 3113 3113 00000 _intp4_extdc: + 3114 3114 $DGL 1,417 + 3115 3115 00000 ??bf_intp4_extdc: + 3116 3116 ; line 725 : ; + 3117 3117 ; line 726 : } + 3118 3118 $DGL 0,3 + 3119 3119 00000 ??ef_intp4_extdc: + 3120 3120 00000 61FC reti ;[INF] 2, 6 + 3121 3121 00002 ??ee_intp4_extdc: + 3122 3122 ; line 727 : + 3123 3123 ; line 728 : + 3124 3124 ; line 729 : + 3125 3125 ; line 730 : /*========================================================= + 3126 3126 ; line 731 : フタ開け閉め割り込み + 3127 3127 ; line 732 : 普段はポーング(misc) + 3128 3128 ; line 733 : =========================================================*/ + 3129 3129 ; line 734 : __interrupt void intp5_shell( ) + 3130 3130 ; line 735 : { + 3131 3131 00002 _intp5_shell: + 3132 3132 $DGL 1,423 + 3133 3133 00002 ??bf_intp5_shell: + 3134 3134 ; line 736 : ; + 3135 3135 ; line 737 : } + 3136 3136 $DGL 0,3 + 3137 3137 00002 ??ef_intp5_shell: + 3138 3138 00002 61FC reti ;[INF] 2, 6 + 3139 3139 00004 ??ee_intp5_shell: + 3140 3140 ; line 738 : + 3141 3141 ; line 739 : + 3142 3142 ; line 740 : /*========================================================= + 3143 3143 ; line 741 : 旧PMICへのコマンド書き込み + 3144 3144 ; line 742 : =========================================================*/ + 3145 3145 ; line 743 : __interrupt void intp6_PM_irq( ) + 3146 3146 ; line 744 : { + 3147 3147 00004 _intp6_PM_irq: + 3148 3148 $DGL 1,429 + 3149 3149 00004 C1 push ax ;[INF] 1, 1 + 3150 3150 00005 C3 push bc ;[INF] 1, 1 + 3151 3151 00006 C5 push de ;[INF] 1, 1 + 3152 3152 00007 C7 push hl ;[INF] 1, 1 + 3153 3153 00008 520C mov c,#0CH ;[INF] 2, 1 + 3154 3154 0000A 92 dec c ;[INF] 1, 1 + 3155 3155 0000B 92 dec c ;[INF] 1, 1 + 3156 3156 0000C R690000 movw ax,_@SEGAX[c] ;[INF] 3, 1 + 3157 3157 0000F C1 push ax ;[INF] 1, 1 + 3158 3158 00010 DFF8 bnz $$-6 ;[INF] 2, 4 + 3159 3159 00012 8EFD mov a,ES ;[INF] 2, 1 + 3160 3160 00014 70 mov x,a ;[INF] 1, 1 + 3161 3161 00015 8EFC mov a,CS ;[INF] 2, 1 + 3162 3162 00017 C1 push ax ;[INF] 1, 1 + 3163 3163 00018 ??bf_intp6_PM_irq: + 3164 3164 ; line 745 : if( system_status.pwr_state == ON ) + 3165 3165 $DGL 0,2 + 3166 3166 00018 R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 3167 3167 0001C DF09 bnz $?L0108 ;[INF] 2, 4 + 3168 3168 ; line 746 : { + 3169 3169 0001E ??bb00_intp6_PM_irq: + 3170 3170 ; line 747 : EI(); + 3171 3171 $DGL 0,4 + 3172 3172 0001E 717AFA ei ;[INF] 3, 4 + 3173 3173 ; line 748 : renge_task_immed_add( ntr_pmic_comm ); + 3174 3174 $DGL 0,5 + 3175 3175 00021 R306D05 movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1 + 3176 3176 00024 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 3177 3177 00027 ??eb00_intp6_PM_irq: + 3178 3178 ; line 749 : } + 3179 3179 00027 ?L0108: + 3180 3180 ; line 750 : } + 3181 3181 $DGL 0,7 + 3182 3182 00027 ??ef_intp6_PM_irq: + 3183 3183 00027 C0 pop ax ;[INF] 1, 1 + 3184 3184 00028 9EFC mov CS,a ;[INF] 2, 1 + 3185 3185 0002A 60 mov a,x ;[INF] 1, 1 + 3186 3186 0002B 9EFD mov ES,a ;[INF] 2, 1 + 3187 3187 0002D R340000 movw de,#_@SEGAX ;[INF] 3, 1 + 3188 3188 00030 5206 mov c,#06H ;[INF] 2, 1 + 3189 3189 00032 C0 pop ax ;[INF] 1, 1 + 3190 3190 00033 B9 movw [de],ax ;[INF] 1, 1 + 3191 3191 00034 A5 incw de ;[INF] 1, 1 + 3192 3192 00035 A5 incw de ;[INF] 1, 1 + 3193 3193 00036 92 dec c ;[INF] 1, 1 + 3194 3194 00037 DFF9 bnz $$-5 ;[INF] 2, 4 + 3195 3195 00039 C6 pop hl ;[INF] 1, 1 + 3196 3196 0003A C4 pop de ;[INF] 1, 1 + 3197 3197 0003B C2 pop bc ;[INF] 1, 1 + 3198 3198 0003C C0 pop ax ;[INF] 1, 1 + 3199 3199 0003D 61FC reti ;[INF] 2, 6 + 3200 3200 0003F ??ee_intp6_PM_irq: + 3201 3201 ; line 751 : + 3202 3202 ; line 752 : + 3203 3203 ; line 753 : + 3204 3204 ; line 754 : extern u8 temp_debug_3; + 3205 3205 ; line 755 : + 3206 3206 ; line 756 : /* ======================================================== + 3207 3207 ; line 757 : PMICからの割り込みを受けて、NTR PMIC互換レジスタからリード + 3208 3208 ; line 758 : ======================================================== */ + 3209 3209 ; line 759 : task_status_immed ntr_pmic_comm( ) + 3210 3210 ; line 760 : { + 3211 3211 + 3212 3212 ----- ROM_CODE CSEG BASE + 3213 3213 0056D _ntr_pmic_comm: + 3214 3214 $DGL 1,439 + 3215 3215 0056D C7 push hl ;[INF] 1, 1 + 3216 3216 0056E ??bf_ntr_pmic_comm: + 3217 3217 ; line 761 : static u8 reg_shadow; + 3218 3218 ; line 762 : u8 reg1_old; + 3219 3219 ; line 763 : u8 irq_work = 0; + 3220 3220 $DGL 0,4 + 3221 3221 0056E 5700 mov h,#00H ; 0 ;[INF] 2, 1 + 3222 3222 ; line 764 : + 3223 3223 ; line 765 : reg1_old = reg_shadow; + 3224 3224 $DGL 0,6 + 3225 3225 00570 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3226 3226 00573 76 mov l,a ;[INF] 1, 1 + 3227 3227 ; line 766 : reg_shadow = iic_mcu_read_a_byte( IIC_SLA_CODEC, CODEC_REG_P + 3228 3228 ; M ); + 3229 3229 $DGL 0,7 + 3230 3230 00574 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 3231 3231 00577 C1 push ax ;[INF] 1, 1 + 3232 3232 00578 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1 + 3233 3233 0057A RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 3234 3234 0057D C0 pop ax ;[INF] 1, 1 + 3235 3235 0057E 62 mov a,c ;[INF] 1, 1 + 3236 3236 0057F R9F0E00 mov !?L0112,a ; reg_shadow ;[INF] 3, 1 + 3237 3237 ; line 767 : if( iic_mcu_bus_status != ERR_SUCCESS ) + 3238 3238 $DGL 0,8 + 3239 3239 00582 RD50000 cmp0 !_iic_mcu_bus_status ;[INF] 3, 1 + 3240 3240 00585 DD04 bz $?L0113 ;[INF] 2, 4 + 3241 3241 ; line 768 : { + 3242 3242 00587 ??bb00_ntr_pmic_comm: + 3243 3243 ; line 769 : return ( ERR_FINISED ); + 3244 3244 $DGL 0,10 + 3245 3245 00587 F7 clrw bc ;[INF] 1, 1 + 3246 3246 00588 RED1F06 br !?L0111 ;[INF] 3, 3 + 3247 3247 0058B ??eb00_ntr_pmic_comm: + 3248 3248 ; line 770 : } + 3249 3249 0058B ?L0113: + 3250 3250 ; line 771 : + 3251 3251 ; line 772 : DI( ); + 3252 3252 $DGL 0,13 + 3253 3253 0058B 717BFA di ;[INF] 3, 4 + 3254 3254 ; line 773 : + 3255 3255 ; line 774 : // バックライト 上 //////////////////////////////////// + 3256 3256 ; line 775 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_U ) != + 3257 3257 ; 0 ) + 3258 3258 $DGL 0,16 + 3259 3259 0058E 66 mov a,l ;[INF] 1, 1 + 3260 3260 0058F R7F0E00 xor a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3261 3261 00592 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 3262 3262 00594 D1 cmp0 a ;[INF] 1, 1 + 3263 3263 00595 DD1E bz $?L0118 ;[INF] 2, 4 + 3264 3264 ; line 776 : { + 3265 3265 00597 ??bb01_ntr_pmic_comm: + 3266 3266 ; line 777 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_U ) == 0 ) + 3267 3267 ; // 消えた + 3268 3268 $DGL 0,18 + 3269 3269 00597 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3270 3270 0059A 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 3271 3271 0059C D1 cmp0 a ;[INF] 1, 1 + 3272 3272 0059D DF0C bnz $?L0117 ;[INF] 2, 4 + 3273 3273 ; line 778 : { + 3274 3274 0059F ??bb02_ntr_pmic_comm: + 3275 3275 ; line 779 : // irq_work = REG_BIT_TWL_BL_U_OFF; + 3276 3276 ; line 780 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_OFF ); + 3277 3277 $DGL 0,21 + 3278 3278 0059F 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 3279 3279 005A2 C1 push ax ;[INF] 1, 1 + 3280 3280 005A3 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3281 3281 005A5 RFD0000 call !_set_irq ;[INF] 3, 3 + 3282 3282 005A8 C0 pop ax ;[INF] 1, 1 + 3283 3283 005A9 ??eb02_ntr_pmic_comm: + 3284 3284 ; line 781 : } + 3285 3285 $DGL 0,22 + 3286 3286 005A9 EF0A br $?L0118 ;[INF] 2, 3 + 3287 3287 005AB ?L0117: + 3288 3288 ; line 782 : else + 3289 3289 ; line 783 : { + 3290 3290 005AB ??bb03_ntr_pmic_comm: + 3291 3291 ; line 784 : // irq_work = REG_BIT_TWL_BL_U_ON; + 3292 3292 ; line 785 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_U_ON ); + 3293 3293 $DGL 0,26 + 3294 3294 005AB 302000 movw ax,#020H ; 32 ;[INF] 3, 1 + 3295 3295 005AE C1 push ax ;[INF] 1, 1 + 3296 3296 005AF 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3297 3297 005B1 RFD0000 call !_set_irq ;[INF] 3, 3 + 3298 3298 005B4 C0 pop ax ;[INF] 1, 1 + 3299 3299 005B5 ??eb03_ntr_pmic_comm: + 3300 3300 ; line 786 : } + 3301 3301 005B5 ?L0118: + 3302 3302 005B5 ??eb01_ntr_pmic_comm: + 3303 3303 ; line 787 : } + 3304 3304 ; line 788 : + 3305 3305 ; line 789 : // バックライト 下 + 3306 3306 ; line 790 : if( ( ( reg1_old ^ reg_shadow ) & REG_BIT_TWL_REQ_BL_L ) != + 3307 3307 ; 0 ) + 3308 3308 $DGL 0,31 + 3309 3309 005B5 66 mov a,l ;[INF] 1, 1 + 3310 3310 005B6 R7F0E00 xor a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3311 3311 005B9 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 3312 3312 005BB D1 cmp0 a ;[INF] 1, 1 + 3313 3313 005BC DD1E bz $?L0122 ;[INF] 2, 4 + 3314 3314 ; line 791 : { + 3315 3315 005BE ??bb04_ntr_pmic_comm: + 3316 3316 ; line 792 : if( ( reg_shadow & REG_BIT_TWL_REQ_BL_L ) == 0 ) + 3317 3317 ; // 消えた + 3318 3318 $DGL 0,33 + 3319 3319 005BE R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3320 3320 005C1 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 3321 3321 005C3 D1 cmp0 a ;[INF] 1, 1 + 3322 3322 005C4 DF0C bnz $?L0121 ;[INF] 2, 4 + 3323 3323 ; line 793 : { + 3324 3324 005C6 ??bb05_ntr_pmic_comm: + 3325 3325 ; line 794 : // irq_work = REG_BIT_TWL_BL_L_OFF; + 3326 3326 ; line 795 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_OFF ); + 3327 3327 $DGL 0,36 + 3328 3328 005C6 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 3329 3329 005C9 C1 push ax ;[INF] 1, 1 + 3330 3330 005CA 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3331 3331 005CC RFD0000 call !_set_irq ;[INF] 3, 3 + 3332 3332 005CF C0 pop ax ;[INF] 1, 1 + 3333 3333 005D0 ??eb05_ntr_pmic_comm: + 3334 3334 ; line 796 : } + 3335 3335 $DGL 0,37 + 3336 3336 005D0 EF0A br $?L0122 ;[INF] 2, 3 + 3337 3337 005D2 ?L0121: + 3338 3338 ; line 797 : else + 3339 3339 ; line 798 : { + 3340 3340 005D2 ??bb06_ntr_pmic_comm: + 3341 3341 ; line 799 : // irq_work = REG_BIT_TWL_BL_L_ON; + 3342 3342 ; line 800 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_BL_L_ON ); + 3343 3343 $DGL 0,41 + 3344 3344 005D2 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 3345 3345 005D5 C1 push ax ;[INF] 1, 1 + 3346 3346 005D6 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3347 3347 005D8 RFD0000 call !_set_irq ;[INF] 3, 3 + 3348 3348 005DB C0 pop ax ;[INF] 1, 1 + 3349 3349 005DC ??eb06_ntr_pmic_comm: + 3350 3350 ; line 801 : } + 3351 3351 005DC ?L0122: + 3352 3352 005DC ??eb04_ntr_pmic_comm: + 3353 3353 ; line 802 : } + 3354 3354 ; line 803 : + 3355 3355 ; line 804 : #if 0 + 3356 3356 ; line 805 : irq_work &= ~VREG_C_IRQ_MASK2; + 3357 3357 ; line 806 : // set_irq 相当品 + 3358 3358 ; line 807 : if( irq_work != 0 ) + 3359 3359 ; line 808 : { + 3360 3360 ; line 809 : u8 tot; + 3361 3361 ; line 810 : + 3362 3362 ; line 811 : DI(); + 3363 3363 ; line 812 : vreg_ctr[ VREG_C_IRQ2 ] |= irq_work; + 3364 3364 ; line 813 : EI(); + 3365 3365 ; line 814 : IRQ0_neg; // 一瞬上げてパルスを送り直す + 3366 3366 ; line 815 : tot = 0; + 3367 3367 ; line 816 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.Dなのでちゃんと + 3368 3368 ; あがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) + 3369 3369 ; line 817 : IRQ0_ast; + 3370 3370 ; line 818 : } + 3371 3371 ; line 819 : #endif + 3372 3372 ; line 820 : + 3373 3373 ; line 821 : #if 0 + 3374 3374 ; line 822 : // バックライト設定 + 3375 3375 ; line 823 : // 勝手に消しておく + 3376 3376 ; line 824 : /// 今のところさらに細かくは分けないけど… + 3377 3377 ; line 825 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_BL_U | REG_BIT_TWL_REQ_ + 3378 3378 ; BL_U ) ) == 0 ) + 3379 3379 ; line 826 : { + 3380 3380 ; line 827 : vreg_ctr[ VREG_C_COMMAND2 ] = ( REG_BIT_CMD_BL_U_OFF | R + 3381 3381 ; EG_BIT_CMD_BL_U_OFF ); + 3382 3382 ; line 828 : renge_task_immed_add( tski_PM_BL_set ); + 3383 3383 ; line 829 : } + 3384 3384 ; line 830 : #endif + 3385 3385 ; line 831 : + 3386 3386 ; line 832 : // offリクエスト ////////////////////////////////////// + 3387 3387 ; line 833 : if( ( reg_shadow & REG_BIT_TWL_REQ_OFF_REQ ) != 0 ) + 3388 3388 $DGL 0,74 + 3389 3389 005DC R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3390 3390 005DF 5C40 and a,#040H ; 64 ;[INF] 2, 1 + 3391 3391 005E1 D1 cmp0 a ;[INF] 1, 1 + 3392 3392 005E2 DD09 bz $?L0123 ;[INF] 2, 4 + 3393 3393 ; line 834 : { + 3394 3394 005E4 ??bb07_ntr_pmic_comm: + 3395 3395 ; line 835 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); + 3396 3396 $DGL 0,76 + 3397 3397 005E4 E6 onew ax ;[INF] 1, 1 + 3398 3398 005E5 A1 incw ax ;[INF] 1, 1 + 3399 3399 005E6 C1 push ax ;[INF] 1, 1 + 3400 3400 005E7 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3401 3401 005E9 RFD0000 call !_set_irq ;[INF] 3, 3 + 3402 3402 005EC C0 pop ax ;[INF] 1, 1 + 3403 3403 005ED ??eb07_ntr_pmic_comm: + 3404 3404 ; line 836 : } + 3405 3405 005ED ?L0123: + 3406 3406 ; line 837 : + 3407 3407 ; line 838 : // リセットリクエスト ///////////////////////////////// + 3408 3408 ; line 839 : if( ( reg_shadow & REG_BIT_TWL_REQ_RST_REQ ) != 0 ) + 3409 3409 $DGL 0,80 + 3410 3410 005ED R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3411 3411 005F0 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 3412 3412 005F2 D1 cmp0 a ;[INF] 1, 1 + 3413 3413 005F3 DD08 bz $?L0125 ;[INF] 2, 4 + 3414 3414 ; line 840 : { + 3415 3415 005F5 ??bb08_ntr_pmic_comm: + 3416 3416 ; line 841 : // CODECバグ回避 + 3417 3417 ; line 842 : // リセット単品でなかったら無視 + 3418 3418 ; line 843 : // codec 修正済↓ + 3419 3419 ; line 844 : // if( ( reg1_old ^ reg_shadow ) == REG_BIT_TWL_REQ_RST_R + 3420 3420 ; EQ ) + 3421 3421 ; line 845 : { + 3422 3422 005F5 ??bb09_ntr_pmic_comm: + 3423 3423 ; line 846 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); + 3424 3424 $DGL 0,87 + 3425 3425 005F5 E6 onew ax ;[INF] 1, 1 + 3426 3426 005F6 C1 push ax ;[INF] 1, 1 + 3427 3427 005F7 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3428 3428 005F9 RFD0000 call !_set_irq ;[INF] 3, 3 + 3429 3429 005FC C0 pop ax ;[INF] 1, 1 + 3430 3430 005FD ??eb09_ntr_pmic_comm: + 3431 3431 ; line 847 : } + 3432 3432 005FD ??eb08_ntr_pmic_comm: + 3433 3433 ; line 848 : } + 3434 3434 005FD ?L0125: + 3435 3435 ; line 849 : + 3436 3436 ; line 850 : // バックライトをマスクして書き戻す + 3437 3437 ; line 851 : EI( ); + 3438 3438 $DGL 0,92 + 3439 3439 005FD 717AFA ei ;[INF] 3, 4 + 3440 3440 ; line 852 : if( ( reg_shadow & ( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R + 3441 3441 ; EQ_RST_REQ )) != 0 ) + 3442 3442 $DGL 0,93 + 3443 3443 00600 R8F0E00 mov a,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3444 3444 00603 5C41 and a,#041H ; 65 ;[INF] 2, 1 + 3445 3445 00605 D1 cmp0 a ;[INF] 1, 1 + 3446 3446 00606 DD16 bz $?L0127 ;[INF] 2, 4 + 3447 3447 ; line 853 : { + 3448 3448 00608 ??bb0A_ntr_pmic_comm: + 3449 3449 ; line 854 : reg_shadow &= ~( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_R + 3450 3450 ; EQ_RST_REQ ); + 3451 3451 $DGL 0,95 + 3452 3452 00608 R340E00 movw de,#loww (?L0112) ; reg_shadow ;[INF] 3, 1 + 3453 3453 0060B 89 mov a,[de] ;[INF] 1, 1 + 3454 3454 0060C 5CBE and a,#0BEH ; 190 ;[INF] 2, 1 + 3455 3455 0060E 99 mov [de],a ;[INF] 1, 1 + 3456 3456 ; line 855 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_PM, reg_s + 3457 3457 ; hadow ); + 3458 3458 $DGL 0,96 + 3459 3459 0060F RD90E00 mov x,!?L0112 ; reg_shadow ;[INF] 3, 1 + 3460 3460 00612 F1 clrb a ;[INF] 1, 1 + 3461 3461 00613 C1 push ax ;[INF] 1, 1 + 3462 3462 00614 5010 mov x,#010H ; 16 ;[INF] 2, 1 + 3463 3463 00616 C1 push ax ;[INF] 1, 1 + 3464 3464 00617 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1 + 3465 3465 00619 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 3466 3466 0061C 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 3467 3467 0061E ??eb0A_ntr_pmic_comm: + 3468 3468 ; line 856 : } + 3469 3469 0061E ?L0127: + 3470 3470 ; line 857 : return ( ERR_FINISED ); + 3471 3471 $DGL 0,98 + 3472 3472 0061E F7 clrw bc ;[INF] 1, 1 + 3473 3473 ; line 858 : } + 3474 3474 0061F ?L0111: + 3475 3475 $DGL 0,99 + 3476 3476 0061F ??ef_ntr_pmic_comm: + 3477 3477 0061F C6 pop hl ;[INF] 1, 1 + 3478 3478 00620 D7 ret ;[INF] 1, 6 + 3479 3479 00621 ??ee_ntr_pmic_comm: + 3480 3480 ; line 859 : + 3481 3481 ; line 860 : + 3482 3482 ; line 861 : + 3483 3483 ; line 862 : /********************************************************** + 3484 3484 ; line 863 : 電池残量ICから残量を取得し、レジスタに書き込む。 + 3485 3485 ; line 864 : 　電池残量ICが無い・故障などの時はとりあえず残量99%とする。 + 3486 3486 ; line 865 : 　　　　　　　　↑は status_1で確認可能。電源投入時にチェックし + 3487 3487 ; ています。 + 3488 3488 ; line 866 : 　PM_init()が実行されている必要があります。 + 3489 3489 ; line 867 : **********************************************************/ + 3490 3490 ; line 868 : static void PM_get_batt_left(){ + 3491 3491 00621 _PM_get_batt_left: + 3492 3492 $DGL 1,492 + 3493 3493 00621 C7 push hl ;[INF] 1, 1 + 3494 3494 00622 C1 push ax ;[INF] 1, 1 + 3495 3495 00623 FBF8FF movw hl,sp ;[INF] 3, 1 + 3496 3496 00626 ??bf_PM_get_batt_left: + 3497 3497 ; line 869 : if(( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_GASGAUGE_ERR ) == + 3498 3498 ; 0 ) + 3499 3499 $DGL 0,2 + 3500 3500 00626 R8F0E00 mov a,!_vreg_ctr+14 ;[INF] 3, 1 + 3501 3501 00629 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 3502 3502 0062B D1 cmp0 a ;[INF] 1, 1 + 3503 3503 0062C DF22 bnz $?L0131 ;[INF] 2, 4 + 3504 3504 ; line 870 : { + 3505 3505 0062E ??bb00_PM_get_batt_left: + 3506 3506 ; line 871 : // 電池残量の取得 + 3507 3507 ; line 872 : { + 3508 3508 0062E ??bb01_PM_get_batt_left: + 3509 3509 ; line 873 : u8 temp[2]; + 3510 3510 ; line 874 : + 3511 3511 ; line 875 : iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC, 2, + 3512 3512 ; temp ); + 3513 3513 $DGL 0,8 + 3514 3514 0062E 17 movw ax,hl ;[INF] 1, 1 + 3515 3515 0062F C1 push ax ;[INF] 1, 1 + 3516 3516 00630 E6 onew ax ;[INF] 1, 1 + 3517 3517 00631 A1 incw ax ;[INF] 1, 1 + 3518 3518 00632 C1 push ax ;[INF] 1, 1 + 3519 3519 00633 A1 incw ax ;[INF] 1, 1 + 3520 3520 00634 A1 incw ax ;[INF] 1, 1 + 3521 3521 00635 C1 push ax ;[INF] 1, 1 + 3522 3522 00636 506C mov x,#06CH ; 108 ;[INF] 2, 1 + 3523 3523 00638 RFD0000 call !_iic_mcu_read ;[INF] 3, 3 + 3524 3524 0063B 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 3525 3525 ; line 876 : + 3526 3526 ; line 877 : vreg_ctr[ VREG_C_BT_REMAIN ] = temp[0]; + 3527 3527 $DGL 0,10 + 3528 3528 0063D 8B mov a,[hl] ; temp ;[INF] 1, 1 + 3529 3529 0063E R9F0B00 mov !_vreg_ctr+11,a ;[INF] 3, 1 + 3530 3530 ; line 878 : vreg_ctr[ VREG_C_BT_REMAIN_FINE ] = temp[1]; + 3531 3531 $DGL 0,11 + 3532 3532 00641 8C01 mov a,[hl+1] ; temp ;[INF] 2, 1 + 3533 3533 00643 R9F0C00 mov !_vreg_ctr+12,a ;[INF] 3, 1 + 3534 3534 00646 ??eb01_PM_get_batt_left: + 3535 3535 ; line 879 : // todo 閾値を超えたら割り込み + 3536 3536 ; line 880 : } + 3537 3537 ; line 881 : + 3538 3538 ; line 882 : vreg_ctr[ VREG_C_BT_VOLTAGE ] = iic_mcu_read_a_byte( IIC + 3539 3539 ; _SLA_BT_GAUGE, BT_GAUGE_REG_VCELL ); + 3540 3540 $DGL 0,15 + 3541 3541 00646 E6 onew ax ;[INF] 1, 1 + 3542 3542 00647 A1 incw ax ;[INF] 1, 1 + 3543 3543 00648 RFD1000 call !bs_F0151 ;[INF] 3, 3 + 3544 3544 0064B R9F0D00 mov !_vreg_ctr+13,a ;[INF] 3, 1 + 3545 3545 0064E ??eb00_PM_get_batt_left: + 3546 3546 ; line 883 : } + 3547 3547 $DGL 0,16 + 3548 3548 0064E EF04 br $?L0132 ;[INF] 2, 3 + 3549 3549 00650 ?L0131: + 3550 3550 ; line 884 : else + 3551 3551 ; line 885 : { + 3552 3552 00650 ??bb02_PM_get_batt_left: + 3553 3553 ; line 886 : vreg_ctr[ VREG_C_BT_REMAIN ] = 99; + 3554 3554 $DGL 0,19 + 3555 3555 00650 RCF0B0063 mov !_vreg_ctr+11,#063H ; 99 ;[INF] 4, 1 + 3556 3556 00654 ??eb02_PM_get_batt_left: + 3557 3557 ; line 887 : } + 3558 3558 00654 ?L0132: + 3559 3559 ; line 888 : + 3560 3560 ; line 889 : // PMIC-NTRに電池残量を教えてあげる + 3561 3561 ; line 890 : iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_BT, + 3562 3562 ; line 891 : ( vreg_ctr[ VREG_C_BT_REMAIN ] < 5 )? + 3563 3563 ; 1 : 0 ); // 1で電池切れ + 3564 3564 $DGL 0,24 + 3565 3565 00654 R400B0005 cmp !_vreg_ctr+11,#05H ; 5 ;[INF] 4, 1 + 3566 3566 00658 DE03 bnc $?L0133 ;[INF] 2, 4 + 3567 3567 0065A E6 onew ax ;[INF] 1, 1 + 3568 3568 0065B EF01 br $?L0134 ;[INF] 2, 3 + 3569 3569 0065D ?L0133: + 3570 3570 0065D F6 clrw ax ;[INF] 1, 1 + 3571 3571 0065E ?L0134: + 3572 3572 0065E F1 clrb a ;[INF] 1, 1 + 3573 3573 0065F C1 push ax ;[INF] 1, 1 + 3574 3574 00660 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 3575 3575 00662 C1 push ax ;[INF] 1, 1 + 3576 3576 00663 50A4 mov x,#0A4H ; 164 ;[INF] 2, 1 + 3577 3577 00665 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 3578 3578 00668 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 3579 3579 ; line 892 : + 3580 3580 ; line 893 : } + 3581 3581 $DGL 0,26 + 3582 3582 0066A ??ef_PM_get_batt_left: + 3583 3583 0066A C0 pop ax ;[INF] 1, 1 + 3584 3584 0066B C6 pop hl ;[INF] 1, 1 + 3585 3585 0066C D7 ret ;[INF] 1, 6 + 3586 3586 0066D ??ee_PM_get_batt_left: + 3587 3587 ; line 894 : + 3588 3588 ; line 895 : + 3589 3589 ; line 896 : + 3590 3590 ; line 897 : + 3591 3591 ; line 898 : + 3592 3592 ; line 899 : /********************************************************** + 3593 3593 ; line 900 : command2 液晶系 + 3594 3594 ; line 901 : 　 ラッパー的な物。ERR_SUCCESSしか返さないが… + 3595 3595 ; line 902 : **********************************************************/ + 3596 3596 ; line 903 : task_status_immed tski_PM_LCD_on() + 3597 3597 ; line 904 : { + 3598 3598 0066D _tski_PM_LCD_on: + 3599 3599 $DGL 1,512 + 3600 3600 0066D ??bf_tski_PM_LCD_on: + 3601 3601 ; line 905 : PM_LCD_on(); + 3602 3602 $DGL 0,2 + 3603 3603 0066D RFDA702 call !_PM_LCD_on ;[INF] 3, 3 + 3604 3604 ; line 906 : return( ERR_SUCCESS ); + 3605 3605 $DGL 0,3 + 3606 3606 00670 F7 clrw bc ;[INF] 1, 1 + 3607 3607 ; line 907 : } + 3608 3608 $DGL 0,4 + 3609 3609 00671 ??ef_tski_PM_LCD_on: + 3610 3610 00671 D7 ret ;[INF] 1, 6 + 3611 3611 00672 ??ee_tski_PM_LCD_on: + 3612 3612 ; line 908 : + 3613 3613 ; line 909 : task_status_immed tski_PM_LCD_off() + 3614 3614 ; line 910 : { + 3615 3615 00672 _tski_PM_LCD_off: + 3616 3616 $DGL 1,518 + 3617 3617 00672 ??bf_tski_PM_LCD_off: + 3618 3618 ; line 911 : PM_LCD_off(); + 3619 3619 $DGL 0,2 + 3620 3620 00672 RFDE202 call !_PM_LCD_off ;[INF] 3, 3 + 3621 3621 ; line 912 : return( ERR_SUCCESS ); + 3622 3622 $DGL 0,3 + 3623 3623 00675 F7 clrw bc ;[INF] 1, 1 + 3624 3624 ; line 913 : } + 3625 3625 $DGL 0,4 + 3626 3626 00676 ??ef_tski_PM_LCD_off: + 3627 3627 00676 D7 ret ;[INF] 1, 6 + 3628 3628 00677 ??ee_tski_PM_LCD_off: + 3629 3629 ; line 914 : + 3630 3630 ; line 915 : task_status_immed tski_PM_BL_set() + 3631 3631 ; line 916 : { + 3632 3632 00677 _tski_PM_BL_set: + 3633 3633 $DGL 1,524 + 3634 3634 00677 C7 push hl ;[INF] 1, 1 + 3635 3635 00678 ??bf_tski_PM_BL_set: + 3636 3636 ; line 917 : u8 cmd_BL; // ↓volatileとか付けなくても大丈 + 3637 3637 ; 夫みたい + 3638 3638 ; line 918 : + 3639 3639 ; line 919 : do + 3640 3640 00678 ?L0141: + 3641 3641 ; line 920 : { + 3642 3642 00678 ??bb00_tski_PM_BL_set: + 3643 3643 ; line 921 : cmd_BL = vreg_ctr[VREG_C_COMMAND2]; + 3644 3644 $DGL 0,6 + 3645 3645 00678 R8F2200 mov a,!_vreg_ctr+34 ;[INF] 3, 1 + 3646 3646 0067B 76 mov l,a ;[INF] 1, 1 + 3647 3647 ; line 922 : PM_BL_set( cmd_BL ); // マスク済み + 3648 3648 $DGL 0,7 + 3649 3649 0067C 17 movw ax,hl ;[INF] 1, 1 + 3650 3650 0067D F1 clrb a ;[INF] 1, 1 + 3651 3651 0067E RFD4203 call !_PM_BL_set ;[INF] 3, 3 + 3652 3652 00681 ??eb00_tski_PM_BL_set: + 3653 3653 ; line 923 : } + 3654 3654 ; line 924 : while( cmd_BL != vreg_ctr[VREG_C_COMMAND2] ); + 3655 3655 $DGL 0,9 + 3656 3656 00681 66 mov a,l ;[INF] 1, 1 + 3657 3657 00682 R4F2200 cmp a,!_vreg_ctr+34 ;[INF] 3, 1 + 3658 3658 00685 DFF1 bnz $?L0141 ;[INF] 2, 4 + 3659 3659 ; line 925 : vreg_ctr[VREG_C_COMMAND2] = 0; + 3660 3660 $DGL 0,10 + 3661 3661 00687 RF52200 clrb !_vreg_ctr+34 ;[INF] 3, 1 + 3662 3662 ; line 926 : + 3663 3663 ; line 927 : return( ERR_SUCCESS ); + 3664 3664 $DGL 0,12 + 3665 3665 0068A F7 clrw bc ;[INF] 1, 1 + 3666 3666 ; line 928 : } + 3667 3667 $DGL 0,13 + 3668 3668 0068B ??ef_tski_PM_BL_set: + 3669 3669 0068B C6 pop hl ;[INF] 1, 1 + 3670 3670 0068C D7 ret ;[INF] 1, 6 + 3671 3671 0068D ??ee_tski_PM_BL_set: + 3672 3672 + 3673 3673 ----- @@CODEL CSEG + 3674 3674 END + 3675 3675 + 3676 3676 + 3677 3677 ; *** Code Information *** + 3678 3678 ; + 3679 3679 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c + 3680 3680 ; + 3681 3681 ; $FUNC PM_init(46) + 3682 3682 ; void=(void) + 3683 3683 ; CODE SIZE= 335 bytes, CLOCK_SIZE= 294 clocks, STACK_SIZE= 20 bytes + 3684 3684 ; + 3685 3685 ; $CALL wait_ms(58) + 3686 3686 ; void=(int:ax) + 3687 3687 ; + 3688 3688 ; $CALL iic_mcu_write(62) + 3689 3689 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3690 3690 ; + 3691 3691 ; $CALL iic_mcu_write(66) + 3692 3692 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3693 3693 ; + 3694 3694 ; $CALL iic_mcu_write(75) + 3695 3695 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3696 3696 ; + 3697 3697 ; $CALL iic_mcu_read(78) + 3698 3698 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3699 3699 ; + 3700 3700 ; $CALL iic_mcu_write(82) + 3701 3701 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3702 3702 ; + 3703 3703 ; $CALL iic_mcu_write(86) + 3704 3704 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3705 3705 ; + 3706 3706 ; $CALL get_adc(90) + 3707 3707 ; bc=(int:ax) + 3708 3708 ; + 3709 3709 ; $CALL iic_mcu_write(104) + 3710 3710 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3711 3711 ; + 3712 3712 ; $CALL wait_ms(112) + 3713 3713 ; void=(int:ax) + 3714 3714 ; + 3715 3715 ; $CALL iic_mcu_write(116) + 3716 3716 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3717 3717 ; + 3718 3718 ; $CALL wait_ms(119) + 3719 3719 ; void=(int:ax) + 3720 3720 ; + 3721 3721 ; $CALL iic_mcu_read_a_byte(122) + 3722 3722 ; bc=(int:ax, int:[sp+4]) + 3723 3723 ; + 3724 3724 ; $CALL iic_mcu_write(131) + 3725 3725 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3726 3726 ; + 3727 3727 ; $CALL iic_mcu_write(135) + 3728 3728 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3729 3729 ; + 3730 3730 ; $CALL get_adc(142) + 3731 3731 ; bc=(int:ax) + 3732 3732 ; + 3733 3733 ; $CALL renge_task_immed_add(143) + 3734 3734 ; bc=(pointer:ax) + 3735 3735 ; + 3736 3736 ; $FUNC PM_bt_temp_update(163) + 3737 3737 ; bc=(void) + 3738 3738 ; CODE SIZE= 217 bytes, CLOCK_SIZE= 196 clocks, STACK_SIZE= 14 bytes + 3739 3739 ; + 3740 3740 ; $CALL iic_mcu_write(201) + 3741 3741 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3742 3742 ; + 3743 3743 ; $FUNC PM_LCD_on(227) + 3744 3744 ; bc=(void) + 3745 3745 ; CODE SIZE= 59 bytes, CLOCK_SIZE= 114 clocks, STACK_SIZE= 14 bytes + 3746 3746 ; + 3747 3747 ; $CALL iic_mcu_write_a_byte(230) + 3748 3748 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3749 3749 ; + 3750 3750 ; $CALL wait_ms(232) + 3751 3751 ; void=(int:ax) + 3752 3752 ; + 3753 3753 ; $CALL iic_mcu_write_a_byte(234) + 3754 3754 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3755 3755 ; + 3756 3756 ; $CALL wait_ms(236) + 3757 3757 ; void=(int:ax) + 3758 3758 ; + 3759 3759 ; $CALL iic_mcu_write_a_byte(238) + 3760 3760 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3761 3761 ; + 3762 3762 ; $CALL wait_ms(240) + 3763 3763 ; void=(int:ax) + 3764 3764 ; + 3765 3765 ; $CALL iic_mcu_read_a_byte(245) + 3766 3766 ; bc=(int:ax, int:[sp+4]) + 3767 3767 ; + 3768 3768 ; $CALL set_irq(251) + 3769 3769 ; void=(int:ax, int:[sp+4]) + 3770 3770 ; + 3771 3771 ; $FUNC PM_LCD_off(265) + 3772 3772 ; void=(void) + 3773 3773 ; CODE SIZE= 96 bytes, CLOCK_SIZE= 139 clocks, STACK_SIZE= 14 bytes + 3774 3774 ; + 3775 3775 ; $CALL iic_mcu_read_a_byte(272) + 3776 3776 ; bc=(int:ax, int:[sp+4]) + 3777 3777 ; + 3778 3778 ; $CALL PM_BL_set(277) + 3779 3779 ; bc=(int:ax) + 3780 3780 ; + 3781 3781 ; $CALL iic_mcu_write_a_byte(296) + 3782 3782 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3783 3783 ; + 3784 3784 ; $CALL wait_ms(297) + 3785 3785 ; void=(int:ax) + 3786 3786 ; + 3787 3787 ; $CALL iic_mcu_write_a_byte(299) + 3788 3788 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3789 3789 ; + 3790 3790 ; $CALL set_irq(303) + 3791 3791 ; void=(int:ax, int:[sp+4]) + 3792 3792 ; + 3793 3793 ; $FUNC PM_BL_set(314) + 3794 3794 ; bc=(unsigned char dat:x) + 3795 3795 ; CODE SIZE= 202 bytes, CLOCK_SIZE= 176 clocks, STACK_SIZE= 18 bytes + 3796 3796 ; + 3797 3797 ; $CALL iic_mcu_read_a_byte(323) + 3798 3798 ; bc=(int:ax, int:[sp+4]) + 3799 3799 ; + 3800 3800 ; $CALL wait_ms(381) + 3801 3801 ; void=(int:ax) + 3802 3802 ; + 3803 3803 ; $CALL iic_mcu_write_a_byte(383) + 3804 3804 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3805 3805 ; + 3806 3806 ; $FUNC PM_LCD_vcom_set(395) + 3807 3807 ; bc=(void) + 3808 3808 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 41 clocks, STACK_SIZE= 10 bytes + 3809 3809 ; + 3810 3810 ; $CALL iic_mcu_write_a_byte(398) + 3811 3811 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3812 3812 ; + 3813 3813 ; $CALL iic_mcu_write_a_byte(399) + 3814 3814 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3815 3815 ; + 3816 3816 ; $FUNC tski_vcom_set(450) + 3817 3817 ; bc=(void) + 3818 3818 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes + 3819 3819 ; + 3820 3820 ; $CALL PM_LCD_vcom_set(451) + 3821 3821 ; bc=(void) + 3822 3822 ; + 3823 3823 ; $FUNC PM_sys_pow_on(466) + 3824 3824 ; bc=(void) + 3825 3825 ; CODE SIZE= 115 bytes, CLOCK_SIZE= 182 clocks, STACK_SIZE= 14 bytes + 3826 3826 ; + 3827 3827 ; $CALL get_adc(475) + 3828 3828 ; bc=(int:ax) + 3829 3829 ; + 3830 3830 ; $CALL PM_bt_temp_update(477) + 3831 3831 ; bc=(void) + 3832 3832 ; + 3833 3833 ; $CALL PM_get_batt_left(480) + 3834 3834 ; void=(void) + 3835 3835 ; + 3836 3836 ; $CALL iic_mcu_write_a_byte(492) + 3837 3837 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3838 3838 ; + 3839 3839 ; $CALL wait_ms(494) + 3840 3840 ; void=(int:ax) + 3841 3841 ; + 3842 3842 ; $CALL wait_ms(499) + 3843 3843 ; void=(int:ax) + 3844 3844 ; + 3845 3845 ; $CALL iic_mcu_write_a_byte(501) + 3846 3846 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3847 3847 ; + 3848 3848 ; $CALL wait_ms(502) + 3849 3849 ; void=(int:ax) + 3850 3850 ; + 3851 3851 ; $CALL iic_mcu_write_a_byte(504) + 3852 3852 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3853 3853 ; + 3854 3854 ; $CALL wait_ms(506) + 3855 3855 ; void=(int:ax) + 3856 3856 ; + 3857 3857 ; $CALL iic_mcu_write_a_byte(508) + 3858 3858 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3859 3859 ; + 3860 3860 ; $CALL iic_mcu_read_a_byte(512) + 3861 3861 ; bc=(int:ax, int:[sp+4]) + 3862 3862 ; + 3863 3863 ; $CALL iic_mcu_write_a_byte(517) + 3864 3864 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3865 3865 ; + 3866 3866 ; $FUNC PM_sys_pow_off(583) + 3867 3867 ; bc=(void) + 3868 3868 ; CODE SIZE= 28 bytes, CLOCK_SIZE= 62 clocks, STACK_SIZE= 12 bytes + 3869 3869 ; + 3870 3870 ; $CALL iic_mcu_write_a_byte(588) + 3871 3871 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3872 3872 ; + 3873 3873 ; $CALL iic_mcu_write_a_byte(592) + 3874 3874 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3875 3875 ; + 3876 3876 ; $CALL iic_mcu_write_a_byte(594) + 3877 3877 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3878 3878 ; + 3879 3879 ; $FUNC tsk_batt(637) + 3880 3880 ; void=(void) + 3881 3881 ; CODE SIZE= 168 bytes, CLOCK_SIZE= 133 clocks, STACK_SIZE= 6 bytes + 3882 3882 ; + 3883 3883 ; $CALL set_irq(659) + 3884 3884 ; void=(int:ax, int:[sp+4]) + 3885 3885 ; + 3886 3886 ; $CALL set_irq(664) + 3887 3887 ; void=(int:ax, int:[sp+4]) + 3888 3888 ; + 3889 3889 ; $CALL PM_get_batt_left(708) + 3890 3890 ; void=(void) + 3891 3891 ; + 3892 3892 ; $FUNC intp4_extdc(724) + 3893 3893 ; void=(void) + 3894 3894 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes + 3895 3895 ; + 3896 3896 ; $FUNC intp5_shell(735) + 3897 3897 ; void=(void) + 3898 3898 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes + 3899 3899 ; + 3900 3900 ; $FUNC intp6_PM_irq(744) + 3901 3901 ; void=(void) + 3902 3902 ; CODE SIZE= 59 bytes, CLOCK_SIZE= 55 clocks, STACK_SIZE= 26 bytes + 3903 3903 ; + 3904 3904 ; $CALL renge_task_immed_add(748) + 3905 3905 ; bc=(pointer:ax) + 3906 3906 ; + 3907 3907 ; $FUNC ntr_pmic_comm(760) + 3908 3908 ; bc=(void) + 3909 3909 ; CODE SIZE= 180 bytes, CLOCK_SIZE= 152 clocks, STACK_SIZE= 10 bytes + 3910 3910 ; + 3911 3911 ; $CALL iic_mcu_read_a_byte(766) + 3912 3912 ; bc=(int:ax, int:[sp+4]) + 3913 3913 ; + 3914 3914 ; $CALL set_irq(780) + 3915 3915 ; void=(int:ax, int:[sp+4]) + 3916 3916 ; + 3917 3917 ; $CALL set_irq(785) + 3918 3918 ; void=(int:ax, int:[sp+4]) + 3919 3919 ; + 3920 3920 ; $CALL set_irq(795) + 3921 3921 ; void=(int:ax, int:[sp+4]) + 3922 3922 ; + 3923 3923 ; $CALL set_irq(800) + 3924 3924 ; void=(int:ax, int:[sp+4]) + 3925 3925 ; + 3926 3926 ; $CALL set_irq(835) + 3927 3927 ; void=(int:ax, int:[sp+4]) + 3928 3928 ; + 3929 3929 ; $CALL set_irq(846) + 3930 3930 ; void=(int:ax, int:[sp+4]) + 3931 3931 ; + 3932 3932 ; $CALL iic_mcu_write_a_byte(855) + 3933 3933 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3934 3934 ; + 3935 3935 ; $FUNC PM_get_batt_left(868) + 3936 3936 ; void=(void) + 3937 3937 ; CODE SIZE= 76 bytes, CLOCK_SIZE= 77 clocks, STACK_SIZE= 14 bytes + 3938 3938 ; + 3939 3939 ; $CALL iic_mcu_read(875) + 3940 3940 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 3941 3941 ; + 3942 3942 ; $CALL iic_mcu_read_a_byte(882) + 3943 3943 ; bc=(int:ax, int:[sp+4]) + 3944 3944 ; + 3945 3945 ; $CALL iic_mcu_write_a_byte(891) + 3946 3946 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 3947 3947 ; + 3948 3948 ; $FUNC tski_PM_LCD_on(904) + 3949 3949 ; bc=(void) + 3950 3950 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes + 3951 3951 ; + 3952 3952 ; $CALL PM_LCD_on(905) + 3953 3953 ; bc=(void) + 3954 3954 ; + 3955 3955 ; $FUNC tski_PM_LCD_off(910) + 3956 3956 ; bc=(void) + 3957 3957 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes + 3958 3958 ; + 3959 3959 ; $CALL PM_LCD_off(911) + 3960 3960 ; void=(void) + 3961 3961 ; + 3962 3962 ; $FUNC tski_PM_BL_set(916) + 3963 3963 ; bc=(void) + 3964 3964 ; CODE SIZE= 22 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 6 bytes + 3965 3965 ; + 3966 3966 ; $CALL PM_BL_set(922) + 3967 3967 ; bc=(int:ax) + 3968 3968 + 3969 3969 ; Target chip : uPD79F0104 + 3970 3970 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.1 @@BITS +00000 001F8H @@CNST +00000 00004H @@R_INIT +00000 00004H @@INIT +00000 00010H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0068DH ROM_CODE +00000 0003FH @@BASE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/pm.rel b/branches/0.10(X3)/pm.rel new file mode 100644 index 0000000..7fac2ee Binary files /dev/null and b/branches/0.10(X3)/pm.rel differ diff --git a/branches/0.10(X3)/pool.h b/branches/0.10(X3)/pool.h new file mode 100644 index 0000000..bc7e991 --- /dev/null +++ b/branches/0.10(X3)/pool.h @@ -0,0 +1,23 @@ +#ifndef _pool_h_ +#define _pool_h_ + + +#include "pedometer.h" + +#define VREG_C_FREE_SIZE 24 + +// 空いてるメモリ +typedef struct { + unsigned short pedo_log[ PEDOMETER_LOG_SIZE ]; + unsigned char vreg_c_free[ VREG_C_FREE_SIZE ]; +}st_vreg_c_ext; + +typedef union{ + st_vreg_c_ext vreg_c_ext; + u8 self_update_work[ 256 ]; // 256以上はまとめ書きできない +}uni_pool; + +extern uni_pool pool; + + +#endif diff --git a/branches/0.10(X3)/reboot.c b/branches/0.10(X3)/reboot.c new file mode 100644 index 0000000..2d19e8c --- /dev/null +++ b/branches/0.10(X3)/reboot.c @@ -0,0 +1,24 @@ +/********************************************************//* + + むりやりリブート + + ファイル中にインラインアセンブラがあると、 + そのモジュール全部最適化が聞かなくなるため追い出した + + **********************************************************/ +#pragma SFR + +#include "incs_loader.h" + + +void my_reboot(){ +#asm + + MOV PSW,#06H ; ダミーのPSWをセット + MOVW AX,#000d0h ; リセットのベクタ値を取り込んでいます。 + PUSH PSW + PUSH AX ; これでRETIのためのスタックを準備 + RETI ; これでリセット・ベクタに分岐 + +#endasm +} diff --git a/branches/0.10(X3)/reboot.h b/branches/0.10(X3)/reboot.h new file mode 100644 index 0000000..c20e11e --- /dev/null +++ b/branches/0.10(X3)/reboot.h @@ -0,0 +1,6 @@ +#ifndef __MYREBOOT__ +#define __MYREBOOT__ + +void my_reboot(); + +#endif diff --git a/branches/0.10(X3)/reboot.prn b/branches/0.10(X3)/reboot.prn new file mode 100644 index 0000000..9ca387a --- /dev/null +++ b/branches/0.10(X3)/reboot.prn @@ -0,0 +1,177 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\reboot.asm +Para-file: +In-file: inter_asm\reboot.asm +Obj-file: reboot.rel +Prn-file: reboot.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no reboot.c + 6 6 ; In-file : reboot.c + 7 7 ; Asm-file : inter_asm\reboot.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, reboot.c + 18 18 $DGS MOD_NAM, reboot, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS GLV_SYM, _my_reboot, U, U, 01H, 026H, 01H, 02H + 36 36 $DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H + 37 37 $DGS BEG_FUN, ??bf_my_reboot, U, U, 00H, 065H, 01H, 00H + 38 38 $DGS AUX_BEG, 0EH, 00H, 019H + 39 39 $DGS END_FUN, ??ef_my_reboot, U, U, 00H, 065H, 01H, 00H + 40 40 $DGS AUX_END, 0BH + 41 41 + 42 42 PUBLIC _my_reboot + 43 43 + 44 44 ----- @@BITS BSEG + 45 45 + 46 46 ----- @@CNST CSEG MIRRORP + 47 47 + 48 48 ----- @@R_INIT CSEG UNIT64KP + 49 49 + 50 50 ----- @@INIT DSEG BASEP + 51 51 + 52 52 ----- @@DATA DSEG BASEP + 53 53 + 54 54 ----- @@R_INIS CSEG UNIT64KP + 55 55 + 56 56 ----- @@INIS DSEG SADDRP + 57 57 + 58 58 ----- @@DATS DSEG SADDRP + 59 59 + 60 60 ----- LDR_CNSL CSEG PAGE64KP + 61 61 + 62 62 ----- @@RLINIT CSEG UNIT64KP + 63 63 + 64 64 ----- @@INITL DSEG UNIT64KP + 65 65 + 66 66 ----- @@DATAL DSEG UNIT64KP + 67 67 + 68 68 ----- @@CALT CSEG CALLT0 + 69 69 + 70 70 ; line 1 : /********************************************************//* + 71 71 ; line 2 : + 72 72 ; line 3 : むりやりリブート + 73 73 ; line 4 : + 74 74 ; line 5 : ファイル中にインラインアセンブラがあると、 + 75 75 ; line 6 : そのモジュール全部最適化が聞かなくなるため追い出した + 76 76 ; line 7 : + 77 77 ; line 8 : **********************************************************/ + 78 78 ; line 9 : #pragma SFR + 79 79 ; line 10 : + 80 80 ; line 11 : #include "incs_loader.h" + 81 81 ; line 12 : + 82 82 ; line 13 : + 83 83 ; line 14 : void my_reboot(){ + 84 84 + 85 85 ----- LDR_CODE CSEG BASE + 86 86 00000 _my_reboot: + 87 87 $DGL 1,19 + 88 88 00000 ??bf_my_reboot: + 89 89 ; line 15 : #asm + 90 90 + 91 91 $DGL 0,4 + 92 92 00000 CEFA06 MOV PSW,#06H ; ダミーのPSWをセット + 93 93 $DGL 0,5 + 94 94 00003 30D000 MOVW AX,#000d0h ; リセットのベクタ値を取り込んでいます。 + 95 95 $DGL 0,6 + 96 96 00006 61DD PUSH PSW + 97 97 $DGL 0,7 + 98 98 00008 C1 PUSH AX ; これでRETIのためのスタックを準備 + 99 99 $DGL 0,8 + 100 100 00009 61FC RETI ; これでリセット・ベクタに分岐 + 101 101 + 102 102 ; line 16 : + 103 103 ; line 17 : MOV PSW,#06H ; ダミーのPSWをセット + 104 104 ; line 18 : MOVW AX,#000d0h ; リセットのベクタ値を取り + 105 105 ; 込んでいます。 + 106 106 ; line 19 : PUSH PSW + 107 107 ; line 20 : PUSH AX ; これでRETIのためのスタック + 108 108 ; を準備 + 109 109 ; line 21 : RETI ; これでリセット・ベクタに分 + 110 110 ; 岐 + 111 111 ; line 22 : + 112 112 ; line 23 : #endasm + 113 113 ; line 24 : } + 114 114 $DGL 0,11 + 115 115 0000B ??ef_my_reboot: + 116 116 0000B D7 ret ;[INF] 1, 6 + 117 117 0000C ??ee_my_reboot: + 118 118 + 119 119 ----- LDR_CODL CSEG + 120 120 + 121 121 ----- @@BASE CSEG BASE + 122 122 END + 123 123 + 124 124 + 125 125 ; *** Code Information *** + 126 126 ; + 127 127 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c + 128 128 ; + 129 129 ; $FUNC my_reboot(14) + 130 130 ; void=(void) + 131 131 ; CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes + 132 132 + 133 133 ; Target chip : uPD79F0104 + 134 134 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00000H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00000H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H LDR_CNSL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0000CH LDR_CODE +00000 00000H LDR_CODL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/reboot.rel b/branches/0.10(X3)/reboot.rel new file mode 100644 index 0000000..abf6e8f Binary files /dev/null and b/branches/0.10(X3)/reboot.rel differ diff --git a/branches/0.10(X3)/renge.prn b/branches/0.10(X3)/renge.prn new file mode 100644 index 0000000..9a25577 --- /dev/null +++ b/branches/0.10(X3)/renge.prn @@ -0,0 +1,1408 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\renge.asm +Para-file: +In-file: inter_asm\renge.asm +Obj-file: renge.rel +Prn-file: renge.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no renge\renge.c + 6 6 ; In-file : renge\renge.c + 7 7 ; Asm-file : inter_asm\renge.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0EEH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, renge.c + 18 18 $DGS MOD_NAM, renge, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, .1fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 019H + 37 37 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 40 40 $DGS AUX_EOS, 013H, 01H + 41 41 $DGS LAB_SYM, bs_S0096, U, U, 00H, 06H, 00H, 00H + 42 42 $DGS LAB_SYM, es_S0096, U, U, 00H, 06H, 00H, 00H + 43 43 $DGS LAB_SYM, bs_S0094, U, U, 00H, 06H, 00H, 00H + 44 44 $DGS LAB_SYM, es_S0094, U, U, 00H, 06H, 00H, 00H + 45 45 $DGS LAB_SYM, bs_S0095, U, U, 00H, 06H, 00H, 00H + 46 46 $DGS LAB_SYM, es_S0095, U, U, 00H, 06H, 00H, 00H + 47 47 $DGS STA_SYM, _tasks, U, U, 01H, 03H, 01H, 027H + 48 48 $DGS AUX_STR, 00H, 00H, 016H, 0BH, 00H, 00H, 00H, 04H + 49 49 $DGS GLV_SYM, _renge_init, U, U, 01H, 026H, 01H, 02H + 50 50 $DGS AUX_FUN, 00H, U, U, 027H, 00H, 00H + 51 51 $DGS BEG_FUN, ??bf_renge_init, U, U, 00H, 065H, 01H, 00H + 52 52 $DGS AUX_BEG, 035H, 00H, 027H + 53 53 $DGS END_FUN, ??ef_renge_init, U, U, 00H, 065H, 01H, 00H + 54 54 $DGS AUX_END, 09H + 55 55 $DGS GLV_SYM, _renge_task_interval_run, U, U, 0CH, 026H, 01H, 02H + 56 56 $DGS AUX_FUN, 00H, U, U, 036H, 00H, 00H + 57 57 $DGS BEG_FUN, ??bf_renge_task_interval_run, U, U, 00H, 065H, 01H, 00H + 58 58 $DGS AUX_BEG, 051H, 02H, 02CH + 59 59 $DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 60 60 $DGS BEG_BLK, ??bb00_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H + 61 61 $DGS AUX_BEG, 07H, 00H, 02EH + 62 62 $DGS BEG_BLK, ??bb01_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H + 63 63 $DGS AUX_BEG, 0BH, 00H, 00H + 64 64 $DGS END_BLK, ??eb01_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H + 65 65 $DGS AUX_END, 0FH + 66 66 $DGS END_BLK, ??eb00_renge_task_interval_run, U, U, 00H, 064H, 01H, 00H + 67 67 $DGS AUX_END, 010H + 68 68 $DGS END_FUN, ??ef_renge_task_interval_run, U, U, 00H, 065H, 01H, 00H + 69 69 $DGS AUX_END, 012H + 70 70 $DGS STA_SYM, _renge_task_immed_init, U, U, 01H, 03H, 01H, 02H + 71 71 $DGS AUX_FUN, 00H, U, U, 041H, 00H, 00H + 72 72 $DGS BEG_FUN, ??bf_renge_task_immed_init, U, U, 00H, 065H, 01H, 00H + 73 73 $DGS AUX_BEG, 075H, 02H, 03BH + 74 74 $DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 75 75 $DGS BEG_BLK, ??bb00_renge_task_immed_init, U, U, 00H, 064H, 01H, 00H + 76 76 $DGS AUX_BEG, 04H, 00H, 00H + 77 77 $DGS END_BLK, ??eb00_renge_task_immed_init, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_END, 06H + 79 79 $DGS END_FUN, ??ef_renge_task_immed_init, U, U, 00H, 065H, 01H, 00H + 80 80 $DGS AUX_END, 07H + 81 81 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 026H, 01H, 02H + 82 82 $DGS AUX_FUN, 00H, U, U, 062H, 00H, 00H + 83 83 $DGS BEG_FUN, ??bf_renge_task_immed_add, U, U, 00H, 065H, 01H, 00H + 84 84 $DGS AUX_BEG, 083H, 04H, 048H + 85 85 $DGS FUN_ARG, _new_task, 02H, 0FFFFH, 01H, 09H, 01H, 01H + 86 86 $DGS AUX_STR, 00H, 00H, 02H, 00H, 00H, 00H, 00H, 01H + 87 87 $DGS AUT_VAR, _i, 01H, 0FFFFH, 0CH, 01H, 00H, 00H + 88 88 $DGS BEG_BLK, ??bb00_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 89 89 $DGS AUX_BEG, 08H, 00H, 04AH + 90 90 $DGS BEG_BLK, ??bb01_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 91 91 $DGS AUX_BEG, 0AH, 00H, 04CH + 92 92 $DGS BEG_BLK, ??bb02_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 93 93 $DGS AUX_BEG, 0DH, 00H, 052H + 94 94 $DGS END_BLK, ??eb02_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 95 95 $DGS AUX_END, 011H + 96 96 $DGS END_BLK, ??eb01_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 97 97 $DGS AUX_END, 012H + 98 98 $DGS BEG_BLK, ??bb03_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 99 99 $DGS AUX_BEG, 014H, 00H, 054H + 100 100 $DGS BEG_BLK, ??bb04_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 101 101 $DGS AUX_BEG, 019H, 00H, 056H + 102 102 $DGS BEG_BLK, ??bb05_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_BEG, 01BH, 00H, 00H + 104 104 $DGS END_BLK, ??eb05_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_END, 01EH + 106 106 $DGS END_BLK, ??eb04_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 107 107 $DGS AUX_END, 01FH + 108 108 $DGS END_BLK, ??eb03_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_END, 022H + 110 110 $DGS END_BLK, ??eb00_renge_task_immed_add, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_END, 023H + 112 112 $DGS END_FUN, ??ef_renge_task_immed_add, U, U, 00H, 065H, 01H, 00H + 113 113 $DGS AUX_END, 027H + 114 114 $DGS GLV_SYM, _renge_task_immed_run, U, U, 0CH, 026H, 01H, 02H + 115 115 $DGS AUX_FUN, 00H, U, U, 0DEH, 00H, 00H + 116 116 $DGS BEG_FUN, ??bf_renge_task_immed_run, U, U, 00H, 065H, 01H, 00H + 117 117 $DGS AUX_BEG, 0B0H, 04H, 068H + 118 118 $DGS AUT_VAR, _list_id, 03H, 0FFFFH, 0CH, 01H, 00H, 00H + 119 119 $DGS AUT_VAR, _last_task_id, 02H, 0FFFFH, 0CH, 01H, 00H, 00H + 120 120 $DGS BEG_BLK, ??bb00_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_BEG, 05H, 00H, 06AH + 122 122 $DGS BEG_BLK, ??bb01_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 123 123 $DGS AUX_BEG, 07H, 00H, 06CH + 124 124 $DGS BEG_BLK, ??bb02_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 125 125 $DGS AUX_BEG, 08H, 00H, 06EH + 126 126 $DGS BEG_BLK, ??bb03_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 127 127 $DGS AUX_BEG, 0BH, 00H, 072H + 128 128 $DGS END_BLK, ??eb03_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 129 129 $DGS AUX_END, 011H + 130 130 $DGS BEG_BLK, ??bb04_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 131 131 $DGS AUX_BEG, 014H, 00H, 074H + 132 132 $DGS BEG_BLK, ??bb05_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 133 133 $DGS AUX_BEG, 016H, 00H, 07CH + 134 134 $DGS END_BLK, ??eb05_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 135 135 $DGS AUX_END, 018H + 136 136 $DGS END_BLK, ??eb04_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 137 137 $DGS AUX_END, 01AH + 138 138 $DGS END_BLK, ??eb02_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 139 139 $DGS AUX_END, 01BH + 140 140 $DGS BEG_BLK, ??bb06_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 141 141 $DGS AUX_BEG, 01EH, 00H, 07EH + 142 142 $DGS BEG_BLK, ??bb07_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 143 143 $DGS AUX_BEG, 021H, 00H, 080H + 144 144 $DGS BEG_BLK, ??bb08_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 145 145 $DGS AUX_BEG, 023H, 00H, 08AH + 146 146 $DGS END_BLK, ??eb08_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_END, 025H + 148 148 $DGS END_BLK, ??eb07_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_END, 026H + 150 150 $DGS END_BLK, ??eb06_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 151 151 $DGS AUX_END, 028H + 152 152 $DGS END_BLK, ??eb01_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 153 153 $DGS AUX_END, 02AH + 154 154 $DGS BEG_BLK, ??bb09_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_BEG, 02DH, 00H, 08CH + 156 156 $DGS BEG_BLK, ??bb0A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_BEG, 02FH, 00H, 092H + 158 158 $DGS AUT_VAR, _i, 01H, 0FFFFH, 0CH, 01H, 01H, 00H + 159 159 $DGS AUX_STR, 00H, 030H, 01H, 00H, 00H, 00H, 00H, 00H + 160 160 $DGS AUT_VAR, _j, 00H, 0FFFFH, 0CH, 01H, 01H, 00H + 161 161 $DGS AUX_STR, 00H, 030H, 01H, 00H, 00H, 00H, 00H, 00H + 162 162 $DGS BEG_BLK, ??bb0B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 163 163 $DGS AUX_BEG, 033H, 00H, 096H + 164 164 $DGS END_BLK, ??eb0B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 165 165 $DGS AUX_END, 035H + 166 166 $DGS BEG_BLK, ??bb0C_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 167 167 $DGS AUX_BEG, 03CH, 00H, 098H + 168 168 $DGS BEG_BLK, ??bb0D_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 169 169 $DGS AUX_BEG, 03FH, 00H, 09AH + 170 170 $DGS BEG_BLK, ??bb0E_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 171 171 $DGS AUX_BEG, 041H, 00H, 09CH + 172 172 $DGS BEG_BLK, ??bb0F_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 173 173 $DGS AUX_BEG, 044H, 00H, 0A0H + 174 174 $DGS END_BLK, ??eb0F_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_END, 046H + 176 176 $DGS BEG_BLK, ??bb10_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_BEG, 04BH, 00H, 0A2H + 178 178 $DGS BEG_BLK, ??bb11_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_BEG, 04DH, 00H, 0AAH + 180 180 $DGS END_BLK, ??eb11_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_END, 04FH + 182 182 $DGS END_BLK, ??eb10_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 183 183 $DGS AUX_END, 050H + 184 184 $DGS END_BLK, ??eb0E_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 185 185 $DGS AUX_END, 054H + 186 186 $DGS BEG_BLK, ??bb12_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 187 187 $DGS AUX_BEG, 056H, 00H, 0B0H + 188 188 $DGS END_BLK, ??eb12_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 189 189 $DGS AUX_END, 05BH + 190 190 $DGS END_BLK, ??eb0D_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_END, 05CH + 192 192 $DGS BEG_BLK, ??bb13_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_BEG, 05EH, 00H, 0B2H + 194 194 $DGS BEG_BLK, ??bb14_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_BEG, 062H, 00H, 0B8H + 196 196 $DGS END_BLK, ??eb14_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_END, 065H + 198 198 $DGS END_BLK, ??eb13_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 199 199 $DGS AUX_END, 068H + 200 200 $DGS BEG_BLK, ??bb15_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 201 201 $DGS AUX_BEG, 06BH, 00H, 0BEH + 202 202 $DGS END_BLK, ??eb15_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 203 203 $DGS AUX_END, 071H + 204 204 $DGS END_BLK, ??eb0C_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 205 205 $DGS AUX_END, 072H + 206 206 $DGS BEG_BLK, ??bb16_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 207 207 $DGS AUX_BEG, 077H, 00H, 0C0H + 208 208 $DGS BEG_BLK, ??bb17_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 209 209 $DGS AUX_BEG, 079H, 00H, 0C2H + 210 210 $DGS BEG_BLK, ??bb18_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 211 211 $DGS AUX_BEG, 07EH, 00H, 0C4H + 212 212 $DGS BEG_BLK, ??bb19_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 213 213 $DGS AUX_BEG, 080H, 00H, 0CCH + 214 214 $DGS END_BLK, ??eb19_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 215 215 $DGS AUX_END, 082H + 216 216 $DGS END_BLK, ??eb18_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 217 217 $DGS AUX_END, 083H + 218 218 $DGS END_BLK, ??eb17_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 219 219 $DGS AUX_END, 087H + 220 220 $DGS BEG_BLK, ??bb1A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 221 221 $DGS AUX_BEG, 089H, 00H, 0D8H + 222 222 $DGS END_BLK, ??eb1A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 223 223 $DGS AUX_END, 08BH + 224 224 $DGS END_BLK, ??eb16_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 225 225 $DGS AUX_END, 08CH + 226 226 $DGS END_BLK, ??eb0A_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 227 227 $DGS AUX_END, 08EH + 228 228 $DGS END_BLK, ??eb09_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 229 229 $DGS AUX_END, 08FH + 230 230 $DGS END_BLK, ??eb00_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 231 231 $DGS AUX_END, 090H + 232 232 $DGS BEG_BLK, ??bb1B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 233 233 $DGS AUX_BEG, 098H, 00H, 00H + 234 234 $DGS END_BLK, ??eb1B_renge_task_immed_run, U, U, 00H, 064H, 01H, 00H + 235 235 $DGS AUX_END, 09BH + 236 236 $DGS END_FUN, ??ef_renge_task_immed_run, U, U, 00H, 065H, 01H, 00H + 237 237 $DGS AUX_END, 09EH + 238 238 $DGS GLV_SYM, _wait_ms, U, U, 01H, 026H, 01H, 02H + 239 239 $DGS AUX_FUN, 00H, U, U, 0EEH, 00H, 00H + 240 240 $DGS BEG_FUN, ??bf_wait_ms, U, U, 00H, 065H, 01H, 00H + 241 241 $DGS AUX_BEG, 0157H, 04H, 0E4H + 242 242 $DGS FUN_ARG, _ms, 02H, 0FFFFH, 0CH, 09H, 00H, 00H + 243 243 $DGS AUT_VAR, _fine, 00H, 0FFFFH, 0DH, 01H, 00H, 00H + 244 244 $DGS BEG_BLK, ??bb00_wait_ms, U, U, 00H, 064H, 01H, 00H + 245 245 $DGS AUX_BEG, 06H, 00H, 0E6H + 246 246 $DGS BEG_BLK, ??bb01_wait_ms, U, U, 00H, 064H, 01H, 00H + 247 247 $DGS AUX_BEG, 0DH, 00H, 00H + 248 248 $DGS END_BLK, ??eb01_wait_ms, U, U, 00H, 064H, 01H, 00H + 249 249 $DGS AUX_END, 0FH + 250 250 $DGS END_BLK, ??eb00_wait_ms, U, U, 00H, 064H, 01H, 00H + 251 251 $DGS AUX_END, 010H + 252 252 $DGS END_FUN, ??ef_wait_ms, U, U, 00H, 065H, 01H, 00H + 253 253 $DGS AUX_END, 011H + 254 254 $DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 027H, 00H, 00H + 255 255 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 027H, 00H, 00H + 256 256 $DGS GLV_SYM, _renge_task_immediate_not_empty, U, U, 034CH, 027H, 00H, 00H + 257 257 $DGS GLV_SYM, _system_time, U, U, 0CH, 026H, 00H, 00H + 258 258 $DGS GLV_SYM, _tasks_immed, U, U, 0AH, 026H, 01H, 027H + 259 259 $DGS AUX_STR, 013H, 00H, 010H, 08H, 00H, 00H, 00H, 04H + 260 260 $DGS GLV_SYM, _tsk_sw, U, U, 01H, 02H, 01H, 02H + 261 261 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 262 262 $DGS GLV_SYM, _tsk_adc, U, U, 01H, 02H, 01H, 02H + 263 263 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 264 264 $DGS GLV_SYM, _tsk_batt, U, U, 01H, 02H, 01H, 02H + 265 265 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 266 266 $DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 02H, 01H, 02H + 267 267 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 268 268 $DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 02H, 01H, 02H + 269 269 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 270 270 $DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 02H, 01H, 02H + 271 271 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 272 272 $DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 02H, 01H, 02H + 273 273 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 274 274 $DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 02H, 01H, 02H + 275 275 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 276 276 $DGS GLV_SYM, _tsk_debug, U, U, 01H, 02H, 01H, 02H + 277 277 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 278 278 $DGS GLV_SYM, _tsk_debug2, U, U, 01H, 02H, 01H, 02H + 279 279 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 280 280 $DGS GLV_SYM, _tsk_sys, U, U, 01H, 02H, 01H, 02H + 281 281 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 282 282 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H + 283 283 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 284 284 + 285 285 EXTRN _tsk_sw + 286 286 EXTRN _tsk_adc + 287 287 EXTRN _tsk_batt + 288 288 EXTRN _tsk_led_pow + 289 289 EXTRN _tsk_led_wifi + 290 290 EXTRN _tsk_led_notify + 291 291 EXTRN _tsk_led_cam + 292 292 EXTRN _tsk_misc_stat + 293 293 EXTRN _tsk_debug + 294 294 EXTRN _tsk_debug2 + 295 295 EXTRN _tsk_sys + 296 296 EXTRN _WDT_Restart + 297 297 PUBLIC _renge_flg_interval + 298 298 PUBLIC _renge_task_interval_run_force + 299 299 PUBLIC _renge_task_immediate_not_empty + 300 300 PUBLIC _system_time + 301 301 PUBLIC _tasks_immed + 302 302 PUBLIC _renge_init + 303 303 PUBLIC _renge_task_interval_run + 304 304 PUBLIC _renge_task_immed_add + 305 305 PUBLIC _renge_task_immed_run + 306 306 PUBLIC _wait_ms + 307 307 + 308 308 ----- @@BITS BSEG + 309 309 00000.0 _renge_flg_interval DBIT + 310 310 00000.1 _renge_task_interval_run_force DBIT + 311 311 00000.2 _renge_task_immediate_not_empty DBIT + 312 312 + 313 313 ----- @@CNST CSEG MIRRORP + 314 314 + 315 315 ----- @@R_INIT CSEG UNIT64KP + 316 316 00000 R0000 DW loww (_tsk_sw) + 317 317 00002 R0000 DW loww (_tsk_adc) + 318 318 00004 R0000 DW loww (_tsk_batt) + 319 319 00006 R0000 DW loww (_tsk_led_pow) + 320 320 00008 R0000 DW loww (_tsk_led_wifi) + 321 321 0000A R0000 DW loww (_tsk_led_notify) + 322 322 0000C R0000 DW loww (_tsk_led_cam) + 323 323 0000E R0000 DW loww (_tsk_misc_stat) + 324 324 00010 R0000 DW loww (_tsk_debug) + 325 325 00012 R0000 DW loww (_tsk_debug2) + 326 326 00014 R0000 DW loww (_tsk_sys) + 327 327 + 328 328 ----- @@INIT DSEG BASEP + 329 329 00000 _tasks: DS (22) + 330 330 + 331 331 ----- @@DATA DSEG BASEP + 332 332 00000 _system_time: DS (1) + 333 333 00001 DS (1) + 334 334 00002 _tasks_immed: DS (16) + 335 335 + 336 336 ----- @@R_INIS CSEG UNIT64KP + 337 337 + 338 338 ----- @@INIS DSEG SADDRP + 339 339 + 340 340 ----- @@DATS DSEG SADDRP + 341 341 + 342 342 ----- @@CNSTL CSEG PAGE64KP + 343 343 + 344 344 ----- @@RLINIT CSEG UNIT64KP + 345 345 + 346 346 ----- @@INITL DSEG UNIT64KP + 347 347 + 348 348 ----- @@DATAL DSEG UNIT64KP + 349 349 + 350 350 ----- @@CALT CSEG CALLT0 + 351 351 + 352 352 ; Sub-Routines created by CC78K0R + 353 353 + 354 354 ----- ROM_CODE CSEG BASE + 355 355 00000 bs_S0096: + 356 356 00000 F0 clrb x ;[INF] 1, 1 + 357 357 00001 317E shrw ax,7 ;[INF] 2, 1 + 358 358 00003 12 movw bc,ax ;[INF] 1, 1 + 359 359 00004 E6 onew ax ;[INF] 1, 1 + 360 360 00005 R780200 movw _tasks_immed[bc],ax ;[INF] 3, 1 + 361 361 00008 D7 ret ;[INF] 1, 6 + 362 362 00009 es_S0096: + 363 363 + 364 364 ----- ROM_CODE CSEG BASE + 365 365 00009 bs_S0094: + 366 366 00009 8C01 mov a,[hl+1] ;[INF] 2, 1 + 367 367 0000B F0 clrb x ;[INF] 1, 1 + 368 368 0000C 317E shrw ax,7 ;[INF] 2, 1 + 369 369 0000E R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 370 370 00011 14 movw de,ax ;[INF] 1, 1 + 371 371 00012 A9 movw ax,[de] ;[INF] 1, 1 + 372 372 00013 6168 or a,x ;[INF] 2, 1 + 373 373 00015 D7 ret ;[INF] 1, 6 + 374 374 00016 es_S0094: + 375 375 + 376 376 ----- ROM_CODE CSEG BASE + 377 377 00016 bs_S0095: + 378 378 00016 8C03 mov a,[hl+3] ;[INF] 2, 1 + 379 379 00018 F0 clrb x ;[INF] 1, 1 + 380 380 00019 317E shrw ax,7 ;[INF] 2, 1 + 381 381 0001B R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 382 382 0001E 14 movw de,ax ;[INF] 1, 1 + 383 383 0001F A9 movw ax,[de] ;[INF] 1, 1 + 384 384 00020 6168 or a,x ;[INF] 2, 1 + 385 385 00022 D7 ret ;[INF] 1, 6 + 386 386 00023 es_S0095: + 387 387 + 388 388 ; *** Sub-Routine Information *** + 389 389 ; + 390 390 ; $SUB bs_S0094 + 391 391 ; CODE SIZE= 13 bytes + 392 392 ; + 393 393 ; $SUB bs_S0095 + 394 394 ; CODE SIZE= 13 bytes + 395 395 ; + 396 396 ; $SUB bs_S0096 + 397 397 ; CODE SIZE= 9 bytes + 398 398 + 399 399 ; End of Sub-Routines + 400 400 + 401 401 ; line 1 : #pragma section @@CODE ROM_CODE + 402 402 ; line 2 : #pragma nop + 403 403 ; line 3 : #pragma ei + 404 404 ; line 4 : #pragma di + 405 405 ; line 5 : #pragma sfr + 406 406 ; line 6 : + 407 407 ; line 7 : /*************************************************************** + 408 408 ; *************** + 409 409 ; line 8 : タスクシステム？ + 410 410 ; line 9 : なるほど、iTRONにはコンフィギュレータがあるはずだ。 + 411 411 ; line 10 : →作りました + 412 412 ; line 11 : ctr_mcu_config.rb 参照。 task_config.hが作成されます。 + 413 413 ; line 12 : *************************************************************** + 414 414 ; **************/ + 415 415 ; line 13 : #include "renge.h" + 416 416 ; line 14 : #include "renge_task_intval.h" + 417 417 ; line 15 : #include "renge_task_immediate.h" + 418 418 ; line 16 : #include "..\WDT.h" + 419 419 ; line 17 : #include "..\config.h" + 420 420 ; line 18 : #include "..\user_define.h" + 421 421 ; line 19 : + 422 422 ; line 20 : + 423 423 ; line 21 : #define _renge_test_ + 424 424 ; line 22 : + 425 425 ; line 23 : //************************************************************** + 426 426 ; **************** + 427 427 ; line 24 : bit renge_flg_interval; + 428 428 ; line 25 : bit renge_task_interval_run_force; + 429 429 ; line 26 : bit renge_task_immediate_not_empty; + 430 430 ; line 27 : + 431 431 ; line 28 : u8 system_time; + 432 432 ; line 29 : + 433 433 ; line 30 : + 434 434 ; line 31 : + 435 435 ; line 32 : #include "..\bsr_system.h" + 436 436 ; line 33 : extern system_status_ system_status; + 437 437 ; line 34 : + 438 438 ; line 35 : + 439 439 ; line 36 : + 440 440 ; line 37 : //************************************************************** + 441 441 ; **************** + 442 442 ; line 38 : static void renge_task_immed_init(); + 443 443 ; line 39 : static void renge_task_immed_del(); + 444 444 ; line 40 : + 445 445 ; line 41 : + 446 446 ; line 42 : + 447 447 ; line 43 : //************************************************************** + 448 448 ; **************** + 449 449 ; line 44 : task_status_immed ( *tasks_immed[ TASK_IMMED_RUN_LIST_MAX ] )(); + 450 450 ; line 45 : + 451 451 ; line 46 : + 452 452 ; line 47 : + 453 453 ; line 48 : /*************************************************************** + 454 454 ; *************** + 455 455 ; line 49 : 初期化 + 456 456 ; line 50 : ・タスクシステムの動的部分の初期化 + 457 457 ; line 51 : ・インターバルタイマ + 458 458 ; line 52 : *************************************************************** + 459 459 ; **************/ + 460 460 ; line 53 : void renge_init(){ + 461 461 + 462 462 ----- ROM_CODE CSEG BASE + 463 463 00023 _renge_init: + 464 464 $DGL 1,33 + 465 465 00023 ??bf_renge_init: + 466 466 ; line 54 : renge_task_immed_init(); + 467 467 $DGL 0,2 + 468 468 00023 RED5100 br !_renge_task_immed_init ;[INF] 3, 3 + 469 469 00026 ??ef_renge_init: + 470 470 00026 ??ee_renge_init: + 471 471 ; line 55 : /* + 472 472 ; line 56 : イベントタイマのセットなど + 473 473 ; line 57 : 今回はRTCを流用しているのでコメントアウト + 474 474 ; line 58 : #define renge_tick 19xxxxxxx [ms] + 475 475 ; line 59 : renge_interval_init(); → RTC_init(); + 476 476 ; line 60 : */ + 477 477 ; line 61 : } + 478 478 ; line 62 : + 479 479 ; line 63 : + 480 480 ; line 64 : + 481 481 ; line 65 : /*************************************************************** + 482 482 ; *************** + 483 483 ; line 66 : システムチックを進める + 484 484 ; line 67 : *************************************************************** + 485 485 ; **************/ + 486 486 ; line 68 : /* + 487 487 ; line 69 : void renge_interval(){ + 488 488 ; line 70 : // RTCがやってくれる + 489 489 ; line 71 : →__interrupt void int_rtc_int(); + 490 490 ; line 72 : } + 491 491 ; line 73 : */ + 492 492 ; line 74 : + 493 493 ; line 75 : + 494 494 ; line 76 : + 495 495 ; line 77 : /*************************************************************** + 496 496 ; *************** + 497 497 ; line 78 : コンパイル時に決まっている、インターバル起動のタスク + 498 498 ; line 79 : そのうち、逐次起動と混ぜるかもしれない。 + 499 499 ; line 80 : *************************************************************** + 500 500 ; **************/ + 501 501 ; line 81 : err renge_task_interval_run(){ + 502 502 00026 _renge_task_interval_run: + 503 503 $DGL 1,39 + 504 504 00026 C7 push hl ;[INF] 1, 1 + 505 505 00027 ??bf_renge_task_interval_run: + 506 506 ; line 82 : u8 i; + 507 507 ; line 83 : + 508 508 ; line 84 : // インターバル起動 + 509 509 ; line 85 : if(( renge_flg_interval == 1 ) + 510 510 ; line 86 : || ( renge_task_interval_run_force != 0 )) // todo 統合 + 511 511 $DGL 0,6 + 512 512 00027 R31020004 bt _renge_flg_interval,$?L0007 ;[INF] 4, 5 + 513 513 0002B R3114001F bf _renge_task_interval_run_force,$?L0009 ;[INF] 4, 5 + 514 514 0002F ?L0007: + 515 515 ; line 87 : { + 516 516 0002F ??bb00_renge_task_interval_run: + 517 517 ; line 88 : renge_task_interval_run_force = 0; + 518 518 $DGL 0,8 + 519 519 0002F R711300 clr1 _renge_task_interval_run_force ;[INF] 3, 2 + 520 520 ; line 89 : renge_flg_interval = 0; + 521 521 $DGL 0,9 + 522 522 00032 R710300 clr1 _renge_flg_interval ;[INF] 3, 2 + 523 523 ; line 90 : for( i = 0; i != TSK_LAST; i += 1 ) + 524 524 $DGL 0,10 + 525 525 00035 5600 mov l,#00H ; 0 ;[INF] 2, 1 + 526 526 00037 ?L0008: + 527 527 00037 66 mov a,l ;[INF] 1, 1 + 528 528 00038 4C0B cmp a,#0BH ; 11 ;[INF] 2, 1 + 529 529 0003A DD12 bz $?L0009 ;[INF] 2, 4 + 530 530 ; line 91 : { + 531 531 0003C ??bb01_renge_task_interval_run: + 532 532 ; line 92 : tasks[ i ](); + 533 533 $DGL 0,12 + 534 534 0003C 72 mov c,a ;[INF] 1, 1 + 535 535 0003D F3 clrb b ;[INF] 1, 1 + 536 536 0003E 311C shlw bc,1 ;[INF] 2, 1 + 537 537 00040 R790000 movw ax,_tasks[bc] ;[INF] 3, 1 + 538 538 00043 CEFC00 mov CS,#00H ; 0 ;[INF] 3, 1 + 539 539 00046 61CA call ax ;[INF] 2, 3 + 540 540 ; line 93 : // 逐次起動タスクがあったら起動しておく + 541 541 ; line 94 : renge_task_immed_run(); + 542 542 $DGL 0,14 + 543 543 00048 RFDA800 call !_renge_task_immed_run ;[INF] 3, 3 + 544 544 0004B ??eb01_renge_task_interval_run: + 545 545 ; line 95 : } + 546 546 $DGL 0,15 + 547 547 0004B 86 inc l ;[INF] 1, 1 + 548 548 0004C EFE9 br $?L0008 ;[INF] 2, 3 + 549 549 0004E ?L0009: + 550 550 0004E ??eb00_renge_task_interval_run: + 551 551 ; line 96 : } + 552 552 ; line 97 : return( ERR_SUCCESS ); + 553 553 $DGL 0,17 + 554 554 0004E F7 clrw bc ;[INF] 1, 1 + 555 555 ; line 98 : } + 556 556 $DGL 0,18 + 557 557 0004F ??ef_renge_task_interval_run: + 558 558 0004F C6 pop hl ;[INF] 1, 1 + 559 559 00050 D7 ret ;[INF] 1, 6 + 560 560 00051 ??ee_renge_task_interval_run: + 561 561 ; line 99 : + 562 562 ; line 100 : + 563 563 ; line 101 : + 564 564 ; line 102 : /*************************************************************** + 565 565 ; ************** + 566 566 ; line 103 : ■逐一起動タスク■ + 567 567 ; line 104 : + 568 568 ; line 105 : ●task_immed を返す関数。 + 569 569 ; line 106 : ●システムtick、何らかの割り込み（I2C通信完了など）で + 570 570 ; line 107 : スリープから復帰したタイミングで実行されます。 + 571 571 ; line 108 : + 572 572 ; line 109 : ■返値　ERR_FINISED　タスクを削除 + 573 573 ; line 110 : 　　　　それ以外 次のタイミングでまた実行 + 574 574 ; line 111 : + 575 575 ; line 112 : *************************************************************** + 576 576 ; **************/ + 577 577 ; line 113 : + 578 578 ; line 114 : + 579 579 ; line 115 : /************************************** + 580 580 ; line 116 : **************************************/ + 581 581 ; line 117 : void renge_task_immed_init(){ + 582 582 00051 _renge_task_immed_init: + 583 583 $DGL 1,54 + 584 584 00051 C7 push hl ;[INF] 1, 1 + 585 585 00052 ??bf_renge_task_immed_init: + 586 586 ; line 118 : u8 i; + 587 587 ; line 119 : + 588 588 ; line 120 : for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i++ ){ + 589 589 $DGL 0,4 + 590 590 00052 5600 mov l,#00H ; 0 ;[INF] 2, 1 + 591 591 00054 ?L0013: + 592 592 00054 66 mov a,l ;[INF] 1, 1 + 593 593 00055 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 594 594 00057 DE0B bnc $?L0014 ;[INF] 2, 4 + 595 595 00059 ??bb00_renge_task_immed_init: + 596 596 ; line 121 : tasks_immed[ i ] = TSK_IMM_EMPTY_; + 597 597 $DGL 0,5 + 598 598 00059 F0 clrb x ;[INF] 1, 1 + 599 599 0005A 317E shrw ax,7 ;[INF] 2, 1 + 600 600 0005C 12 movw bc,ax ;[INF] 1, 1 + 601 601 0005D F6 clrw ax ;[INF] 1, 1 + 602 602 0005E R780200 movw _tasks_immed[bc],ax ;[INF] 3, 1 + 603 603 00061 ??eb00_renge_task_immed_init: + 604 604 ; line 122 : } + 605 605 $DGL 0,6 + 606 606 00061 86 inc l ;[INF] 1, 1 + 607 607 00062 EFF0 br $?L0013 ;[INF] 2, 3 + 608 608 00064 ?L0014: + 609 609 ; line 123 : } + 610 610 $DGL 0,7 + 611 611 00064 ??ef_renge_task_immed_init: + 612 612 00064 C6 pop hl ;[INF] 1, 1 + 613 613 00065 D7 ret ;[INF] 1, 6 + 614 614 00066 ??ee_renge_task_immed_init: + 615 615 ; line 124 : + 616 616 ; line 125 : + 617 617 ; line 126 : + 618 618 ; line 127 : /************************************** + 619 619 ; line 128 : 逐次実行タスクの登録 + 620 620 ; line 129 : 割り込み禁止 36us → + 621 621 ; line 130 : **************************************/ + 622 622 ; line 131 : err renge_task_immed_add( task_status* new_task ){ + 623 623 00066 _renge_task_immed_add: + 624 624 $DGL 1,65 + 625 625 00066 C7 push hl ;[INF] 1, 1 + 626 626 00067 C1 push ax ;[INF] 1, 1 + 627 627 00068 C1 push ax ;[INF] 1, 1 + 628 628 00069 FBF8FF movw hl,sp ;[INF] 3, 1 + 629 629 0006C ??bf_renge_task_immed_add: + 630 630 ; line 132 : u8 i; + 631 631 ; line 133 : + 632 632 ; line 134 : // リストの空きの先頭に登録 + 633 633 ; line 135 : // 削除したばかりのタスクは、削除マーク(TSK_IMM_DELETED_)とな + 634 634 ; り、空きとは明示的に区別される + 635 635 ; line 136 : // 重複登録を避ける + 636 636 ; line 137 : for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) + 637 637 $DGL 0,7 + 638 638 0006C CC0100 mov [hl+1],#00H ; i,0 ;[INF] 3, 1 + 639 639 0006F ?L0018: + 640 640 0006F 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 641 641 00071 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 642 642 00073 DE2D bnc $?L0019 ;[INF] 2, 4 + 643 643 ; line 138 : { + 644 644 00075 ??bb00_renge_task_immed_add: + 645 645 ; line 139 : if( tasks_immed[ i ] != TSK_IMM_EMPTY_ ) + 646 646 $DGL 0,9 + 647 647 00075 RFD0900 call !bs_S0094 ;[INF] 3, 3 + 648 648 00078 DD0A bz $?L0021 ;[INF] 2, 4 + 649 649 ; line 140 : { + 650 650 0007A ??bb01_renge_task_immed_add: + 651 651 ; line 141 : // 重複登録チェック + 652 652 ; line 142 : if( tasks_immed[ i ] == new_task ) + 653 653 $DGL 0,12 + 654 654 0007A A9 movw ax,[de] ;[INF] 1, 1 + 655 655 0007B 614902 cmpw ax,[hl+2] ; new_task ;[INF] 3, 1 + 656 656 0007E DF1D bnz $?L0022 ;[INF] 2, 4 + 657 657 ; line 143 : { + 658 658 00080 ??bb02_renge_task_immed_add: + 659 659 ; line 144 : // 重複登録はしない + 660 660 ; line 145 : NOP(); + 661 661 $DGL 0,15 + 662 662 00080 00 nop ;[INF] 1, 1 + 663 663 ; line 146 : return( ERR_ERR ); + 664 664 $DGL 0,16 + 665 665 00081 E7 onew bc ;[INF] 1, 1 + 666 666 00082 EF20 br $?L0017 ;[INF] 2, 3 + 667 667 00084 ??eb02_renge_task_immed_add: + 668 668 ; line 147 : } + 669 669 ; line 148 : } + 670 670 00084 ??eb01_renge_task_immed_add: + 671 671 00084 ?L0021: + 672 672 ; line 149 : else + 673 673 ; line 150 : { + 674 674 00084 ??bb03_renge_task_immed_add: + 675 675 ; line 151 : // 空きを見つけた + 676 676 ; line 152 : // もたもたしているうちに割り込み等から割り込まれるの + 677 677 ; を考慮 + 678 678 ; line 153 : // 滅多にないはずだが + 679 679 ; line 154 : for( ; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) + 680 680 $DGL 0,24 + 681 681 00084 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 682 682 00086 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 683 683 00088 DE10 bnc $?L0026 ;[INF] 2, 4 + 684 684 ; line 155 : { + 685 685 0008A ??bb04_renge_task_immed_add: + 686 686 ; line 156 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + 687 687 $DGL 0,26 + 688 688 0008A RFD0900 call !bs_S0094 ;[INF] 3, 3 + 689 689 0008D DF06 bnz $?L0028 ;[INF] 2, 4 + 690 690 ; line 157 : { + 691 691 0008F ??bb05_renge_task_immed_add: + 692 692 ; line 158 : tasks_immed[ i ] = new_task; + 693 693 $DGL 0,28 + 694 694 0008F AC02 movw ax,[hl+2] ; new_task ;[INF] 2, 1 + 695 695 00091 B9 movw [de],ax ;[INF] 1, 1 + 696 696 ; line 159 : return( ERR_SUCCESS ); + 697 697 $DGL 0,29 + 698 698 00092 F7 clrw bc ;[INF] 1, 1 + 699 699 00093 EF0F br $?L0017 ;[INF] 2, 3 + 700 700 00095 ??eb05_renge_task_immed_add: + 701 701 ; line 160 : } + 702 702 00095 ?L0028: + 703 703 00095 ??eb04_renge_task_immed_add: + 704 704 ; line 161 : } + 705 705 $DGL 0,31 + 706 706 00095 615901 inc [hl+1] ; i ;[INF] 3, 2 + 707 707 00098 EFEA br $?L0021 ;[INF] 2, 3 + 708 708 0009A ?L0026: + 709 709 ; line 162 : // 割り込まれてタスク登録できなくなった + 710 710 ; line 163 : return( ERR_ERR ); + 711 711 $DGL 0,33 + 712 712 0009A E7 onew bc ;[INF] 1, 1 + 713 713 0009B EF07 br $?L0017 ;[INF] 2, 3 + 714 714 0009D ??eb03_renge_task_immed_add: + 715 715 ; line 164 : } + 716 716 0009D ?L0022: + 717 717 0009D ??eb00_renge_task_immed_add: + 718 718 ; line 165 : } + 719 719 $DGL 0,35 + 720 720 0009D 615901 inc [hl+1] ; i ;[INF] 3, 2 + 721 721 000A0 EFCD br $?L0018 ;[INF] 2, 3 + 722 722 000A2 ?L0019: + 723 723 ; line 166 : // タスク登録しすぎ(無いはず + 724 724 ; line 167 : NOP(); // デバッガで捕まえるため + 725 725 $DGL 0,37 + 726 726 000A2 00 nop ;[INF] 1, 1 + 727 727 ; line 168 : return( ERR_ERR ); + 728 728 $DGL 0,38 + 729 729 000A3 E7 onew bc ;[INF] 1, 1 + 730 730 ; line 169 : } + 731 731 000A4 ?L0017: + 732 732 $DGL 0,39 + 733 733 000A4 ??ef_renge_task_immed_add: + 734 734 000A4 1004 addw sp,#04H ;[INF] 2, 1 + 735 735 000A6 C6 pop hl ;[INF] 1, 1 + 736 736 000A7 D7 ret ;[INF] 1, 6 + 737 737 000A8 ??ee_renge_task_immed_add: + 738 738 ; line 170 : + 739 739 ; line 171 : + 740 740 ; line 172 : + 741 741 ; line 173 : /************************************** + 742 742 ; line 174 : 逐次実行タスクの実行 + 743 743 ; line 175 : **************************************/ + 744 744 ; line 176 : err renge_task_immed_run(){ + 745 745 000A8 _renge_task_immed_run: + 746 746 $DGL 1,98 + 747 747 000A8 C7 push hl ;[INF] 1, 1 + 748 748 000A9 2004 subw sp,#04H ;[INF] 2, 1 + 749 749 000AB FBF8FF movw hl,sp ;[INF] 3, 1 + 750 750 000AE ??bf_renge_task_immed_run: + 751 751 ; line 177 : u8 list_id; + 752 752 ; line 178 : u8 last_task_id; + 753 753 ; line 179 : + 754 754 ; line 180 : do{ + 755 755 000AE ??bb00_renge_task_immed_run: + 756 756 ; line 181 : last_task_id = 0xFF; + 757 757 $DGL 0,6 + 758 758 000AE CC02FF mov [hl+2],#0FFH ; last_task_id,255 ;[INF] 3, 1 + 759 759 ; line 182 : for( list_id = 0; list_id < TASK_IMMED_RUN_LIST_MAX; list_ + 760 760 ; id += 1 ){ + 761 761 $DGL 0,7 + 762 762 000B1 CC0300 mov [hl+3],#00H ; list_id,0 ;[INF] 3, 1 + 763 763 000B4 ?L0035: + 764 764 000B4 8C03 mov a,[hl+3] ; list_id ;[INF] 2, 1 + 765 765 000B6 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 766 766 000B8 DE42 bnc $?L0036 ;[INF] 2, 4 + 767 767 000BA ??bb01_renge_task_immed_run: + 768 768 ; line 183 : if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ){ + 769 769 $DGL 0,8 + 770 770 000BA RFD1600 call !bs_S0095 ;[INF] 3, 3 + 771 771 000BD DD24 bz $?L0038 ;[INF] 2, 4 + 772 772 000BF ??bb02_renge_task_immed_run: + 773 773 ; line 184 : #ifdef _renge_test_ + 774 774 ; line 185 : if( tasks_immed[ list_id ] == TSK_IMM_DELETED_ ) + 775 775 $DGL 0,10 + 776 776 000BF A9 movw ax,[de] ;[INF] 1, 1 + 777 777 000C0 E7 onew bc ;[INF] 1, 1 + 778 778 000C1 43 cmpw ax,bc ;[INF] 1, 1 + 779 779 000C2 DF03 bnz $?L0040 ;[INF] 2, 4 + 780 780 ; line 186 : { + 781 781 000C4 ??bb03_renge_task_immed_run: + 782 782 ; line 187 : NOP(); + 783 783 $DGL 0,12 + 784 784 000C4 00 nop ;[INF] 1, 1 + 785 785 000C5 ??eb03_renge_task_immed_run: + 786 786 ; line 188 : // タスク管理の不備 + 787 787 ; line 189 : // 存在しないタスクを実行しようとした + 788 788 ; line 190 : // タスクの削除後の処理がまずい + 789 789 ; line 191 : // 予期しないタイミングで immed_run が呼ばれた + 790 790 ; line 192 : } + 791 791 $DGL 0,17 + 792 792 000C5 EF30 br $?L0039 ;[INF] 2, 3 + 793 793 000C7 ?L0040: + 794 794 ; line 193 : else + 795 795 ; line 194 : #endif + 796 796 ; line 195 : { + 797 797 000C7 ??bb04_renge_task_immed_run: + 798 798 ; line 196 : if( tasks_immed[ list_id ]() == ERR_SUCCESS ) + 799 799 $DGL 0,21 + 800 800 000C7 8C03 mov a,[hl+3] ; list_id ;[INF] 2, 1 + 801 801 000C9 72 mov c,a ;[INF] 1, 1 + 802 802 000CA F3 clrb b ;[INF] 1, 1 + 803 803 000CB 311C shlw bc,1 ;[INF] 2, 1 + 804 804 000CD R790200 movw ax,_tasks_immed[bc] ;[INF] 3, 1 + 805 805 000D0 CEFC00 mov CS,#00H ; 0 ;[INF] 3, 1 + 806 806 000D3 61CA call ax ;[INF] 2, 3 + 807 807 000D5 D2 cmp0 c ;[INF] 1, 1 + 808 808 000D6 DF05 bnz $?L0042 ;[INF] 2, 4 + 809 809 ; line 197 : { + 810 810 000D8 ??bb05_renge_task_immed_run: + 811 811 ; line 198 : tasks_immed[ list_id ] = TSK_IMM_DELETED_; + 812 812 $DGL 0,23 + 813 813 000D8 8C03 mov a,[hl+3] ; list_id ;[INF] 2, 1 + 814 814 000DA RFD0000 call !bs_S0096 ;[INF] 3, 3 + 815 815 000DD ??eb05_renge_task_immed_run: + 816 816 ; line 199 : } + 817 817 000DD ?L0042: + 818 818 ; line 200 : last_task_id = list_id; + 819 819 $DGL 0,25 + 820 820 000DD 8C03 mov a,[hl+3] ; list_id ;[INF] 2, 1 + 821 821 000DF 9C02 mov [hl+2],a ; last_task_id ;[INF] 2, 1 + 822 822 000E1 ??eb04_renge_task_immed_run: + 823 823 ; line 201 : } + 824 824 ; line 202 : } + 825 825 $DGL 0,27 + 826 826 000E1 ??eb02_renge_task_immed_run: + 827 827 000E1 EF14 br $?L0039 ;[INF] 2, 3 + 828 828 000E3 ?L0038: + 829 829 ; line 203 : #ifdef _renge_test_ + 830 830 ; line 204 : else + 831 831 ; line 205 : { + 832 832 000E3 ??bb06_renge_task_immed_run: + 833 833 ; line 206 : list_id += 1; + 834 834 $DGL 0,31 + 835 835 000E3 615903 inc [hl+3] ; list_id ;[INF] 3, 2 + 836 836 ; line 207 : for( ; list_id < TASK_IMMED_RUN_LIST_MAX; list_id+ + 837 837 ; + ) + 838 838 $DGL 0,32 + 839 839 000E6 ?L0044: + 840 840 000E6 8C03 mov a,[hl+3] ; list_id ;[INF] 2, 1 + 841 841 000E8 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 842 842 000EA DE10 bnc $?L0036 ;[INF] 2, 4 + 843 843 ; line 208 : { + 844 844 000EC ??bb07_renge_task_immed_run: + 845 845 ; line 209 : if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ) + 846 846 $DGL 0,34 + 847 847 000EC RFD1600 call !bs_S0095 ;[INF] 3, 3 + 848 848 000EF 61E8 skz ;[INF] 2, 1 + 849 849 ; line 210 : { + 850 850 000F1 ??bb08_renge_task_immed_run: + 851 851 ; line 211 : NOP(); // ? + 852 852 $DGL 0,36 + 853 853 000F1 00 nop ;[INF] 1, 1 + 854 854 000F2 ??eb08_renge_task_immed_run: + 855 855 ; line 212 : } + 856 856 000F2 ?L0047: + 857 857 000F2 ??eb07_renge_task_immed_run: + 858 858 ; line 213 : } + 859 859 $DGL 0,38 + 860 860 000F2 615903 inc [hl+3] ; list_id ;[INF] 3, 2 + 861 861 000F5 EFEF br $?L0044 ;[INF] 2, 3 + 862 862 ; line 214 : break; + 863 863 000F7 ??eb06_renge_task_immed_run: + 864 864 ; line 215 : } + 865 865 000F7 ?L0039: + 866 866 000F7 ??eb01_renge_task_immed_run: + 867 867 ; line 216 : #endif + 868 868 ; line 217 : } + 869 869 $DGL 0,42 + 870 870 000F7 615903 inc [hl+3] ; list_id ;[INF] 3, 2 + 871 871 000FA EFB8 br $?L0035 ;[INF] 2, 3 + 872 872 000FC ?L0036: + 873 873 ; line 218 : + 874 874 ; line 219 : // タスク削除 + 875 875 ; line 220 : { + 876 876 000FC ??bb09_renge_task_immed_run: + 877 877 ; line 221 : if( last_task_id != 0xFF ) + 878 878 $DGL 0,46 + 879 879 000FC 8C02 mov a,[hl+2] ; last_task_id ;[INF] 2, 1 + 880 880 000FE 81 inc a ;[INF] 1, 1 + 881 881 000FF 61F8 sknz ;[INF] 2, 1 + 882 882 00101 REDF001 br !?L0049 ;[INF] 3, 3 + 883 883 ; line 222 : { + 884 884 00104 ??bb0A_renge_task_immed_run: + 885 885 ; line 223 : u8 i,j; + 886 886 ; line 224 : + 887 887 ; line 225 : #ifdef _renge_test_ + 888 888 ; line 226 : if ( tasks_immed[ 1 ] != 0 ){ + 889 889 $DGL 0,51 + 890 890 00104 F6 clrw ax ;[INF] 1, 1 + 891 891 00105 R420400 cmpw ax,!_tasks_immed+2 ;[INF] 3, 1 + 892 892 00108 61E8 skz ;[INF] 2, 1 + 893 893 0010A ??bb0B_renge_task_immed_run: + 894 894 ; line 227 : NOP(); + 895 895 $DGL 0,52 + 896 896 0010A 00 nop ;[INF] 1, 1 + 897 897 0010B ??eb0B_renge_task_immed_run: + 898 898 ; line 228 : } + 899 899 0010B ?L0051: + 900 900 ; line 229 : #endif + 901 901 ; line 230 : // リスト前詰め + 902 902 ; line 231 : + 903 903 ; line 232 : i = 0; // 前詰め後リストの最後尾 + 904 904 $DGL 0,57 + 905 905 0010B CC0100 mov [hl+1],#00H ; i,0 ;[INF] 3, 1 + 906 906 ; line 233 : j = 1; // リストの後ろの方のタスクを探す + 907 907 $DGL 0,58 + 908 908 0010E CC0001 mov [hl+0],#01H ; j,1 ;[INF] 3, 1 + 909 909 ; line 234 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + 910 910 $DGL 0,59 + 911 911 00111 ?L0053: + 912 912 00111 8B mov a,[hl] ; j ;[INF] 1, 1 + 913 913 00112 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 914 914 00114 61C8 skc ;[INF] 2, 1 + 915 915 00116 REDA501 br !?L0054 ;[INF] 3, 3 + 916 916 ; line 235 : { + 917 917 00119 ??bb0C_renge_task_immed_run: + 918 918 ; line 236 : DI(); + 919 919 $DGL 0,61 + 920 920 00119 717BFA di ;[INF] 3, 4 + 921 921 ; line 237 : if( tasks_immed[ i ] == TSK_IMM_DELETED_ ) + 922 922 $DGL 0,62 + 923 923 0011C 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 924 924 0011E F0 clrb x ;[INF] 1, 1 + 925 925 0011F 317E shrw ax,7 ;[INF] 2, 1 + 926 926 00121 12 movw bc,ax ;[INF] 1, 1 + 927 927 00122 R790200 movw ax,_tasks_immed[bc] ;[INF] 3, 1 + 928 928 00125 E7 onew bc ;[INF] 1, 1 + 929 929 00126 43 cmpw ax,bc ;[INF] 1, 1 + 930 930 00127 DF62 bnz $?L0056 ;[INF] 2, 4 + 931 931 ; line 238 : { + 932 932 00129 ??bb0D_renge_task_immed_run: + 933 933 ; line 239 : if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) + 934 934 $DGL 0,64 + 935 935 00129 8B mov a,[hl] ; j ;[INF] 1, 1 + 936 936 0012A F0 clrb x ;[INF] 1, 1 + 937 937 0012B 317E shrw ax,7 ;[INF] 2, 1 + 938 938 0012D R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 939 939 00130 14 movw de,ax ;[INF] 1, 1 + 940 940 00131 A9 movw ax,[de] ;[INF] 1, 1 + 941 941 00132 6168 or a,x ;[INF] 2, 1 + 942 942 00134 DF34 bnz $?L0058 ;[INF] 2, 4 + 943 943 ; line 240 : { + 944 944 00136 ??bb0E_renge_task_immed_run: + 945 945 ; line 241 : // リストの最後だった + 946 946 ; line 242 : for( ; i < j ; i += 1 ) + 947 947 $DGL 0,67 + 948 948 00136 ?L0060: + 949 949 00136 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 950 950 00138 4D cmp a,[hl] ; j ;[INF] 1, 1 + 951 951 00139 DE0F bnc $?L0061 ;[INF] 2, 4 + 952 952 ; line 243 : { + 953 953 0013B ??bb0F_renge_task_immed_run: + 954 954 ; line 244 : tasks_immed[ i ] = TSK_IMM_EMPTY_; + 955 955 $DGL 0,69 + 956 956 0013B 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 957 957 0013D F0 clrb x ;[INF] 1, 1 + 958 958 0013E 317E shrw ax,7 ;[INF] 2, 1 + 959 959 00140 12 movw bc,ax ;[INF] 1, 1 + 960 960 00141 F6 clrw ax ;[INF] 1, 1 + 961 961 00142 R780200 movw _tasks_immed[bc],ax ;[INF] 3, 1 + 962 962 00145 ??eb0F_renge_task_immed_run: + 963 963 ; line 245 : } + 964 964 $DGL 0,70 + 965 965 00145 615901 inc [hl+1] ; i ;[INF] 3, 2 + 966 966 00148 EFEC br $?L0060 ;[INF] 2, 3 + 967 967 0014A ?L0061: + 968 968 ; line 246 : #ifdef _renge_test_ + 969 969 ; line 247 : /// ほんと? + 970 970 ; line 248 : j += 1; + 971 971 $DGL 0,73 + 972 972 0014A 615900 inc [hl+0] ; j ;[INF] 3, 2 + 973 973 ; line 249 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j+ + 974 974 ; + ) + 975 975 $DGL 0,74 + 976 976 0014D ?L0063: + 977 977 0014D 8B mov a,[hl] ; j ;[INF] 1, 1 + 978 978 0014E 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 979 979 00150 DE13 bnc $?L0064 ;[INF] 2, 4 + 980 980 ; line 250 : { + 981 981 00152 ??bb10_renge_task_immed_run: + 982 982 ; line 251 : if( tasks_immed[ j ] != TSK_IMM_EM + 983 983 ; PTY_ ) + 984 984 $DGL 0,76 + 985 985 00152 8B mov a,[hl] ; j ;[INF] 1, 1 + 986 986 00153 F0 clrb x ;[INF] 1, 1 + 987 987 00154 317E shrw ax,7 ;[INF] 2, 1 + 988 988 00156 R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 989 989 00159 14 movw de,ax ;[INF] 1, 1 + 990 990 0015A A9 movw ax,[de] ;[INF] 1, 1 + 991 991 0015B 6168 or a,x ;[INF] 2, 1 + 992 992 0015D 61E8 skz ;[INF] 2, 1 + 993 993 ; line 252 : { + 994 994 0015F ??bb11_renge_task_immed_run: + 995 995 ; line 253 : NOP(); // ? + 996 996 $DGL 0,78 + 997 997 0015F 00 nop ;[INF] 1, 1 + 998 998 00160 ??eb11_renge_task_immed_run: + 999 999 ; line 254 : } + 1000 1000 00160 ?L0066: + 1001 1001 ; line 255 : } + 1002 1002 $DGL 0,80 + 1003 1003 00160 ??eb10_renge_task_immed_run: + 1004 1004 00160 615900 inc [hl+0] ; j ;[INF] 3, 2 + 1005 1005 00163 EFE8 br $?L0063 ;[INF] 2, 3 + 1006 1006 00165 ?L0064: + 1007 1007 ; line 256 : #endif + 1008 1008 ; line 257 : EI(); + 1009 1009 $DGL 0,82 + 1010 1010 00165 717AFA ei ;[INF] 3, 4 + 1011 1011 ; line 258 : break; + 1012 1012 $DGL 0,83 + 1013 1013 00168 EF3B br $?L0054 ;[INF] 2, 3 + 1014 1014 0016A ??eb0E_renge_task_immed_run: + 1015 1015 ; line 259 : } + 1016 1016 0016A ?L0058: + 1017 1017 ; line 260 : if( tasks_immed[ j ] != TSK_IMM_DELETED_ ) + 1018 1018 $DGL 0,85 + 1019 1019 0016A 8B mov a,[hl] ; j ;[INF] 1, 1 + 1020 1020 0016B F0 clrb x ;[INF] 1, 1 + 1021 1021 0016C 317E shrw ax,7 ;[INF] 2, 1 + 1022 1022 0016E R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 1023 1023 00171 14 movw de,ax ;[INF] 1, 1 + 1024 1024 00172 A9 movw ax,[de] ;[INF] 1, 1 + 1025 1025 00173 E7 onew bc ;[INF] 1, 1 + 1026 1026 00174 43 cmpw ax,bc ;[INF] 1, 1 + 1027 1027 00175 DD1D bz $?L0057 ;[INF] 2, 4 + 1028 1028 ; line 261 : { + 1029 1029 00177 ??bb12_renge_task_immed_run: + 1030 1030 ; line 262 : // 探索隊が前詰めすべきタスクを見つけた + 1031 1031 ; line 263 : tasks_immed[ i ] = tasks_immed[ j ]; + 1032 1032 $DGL 0,88 + 1033 1033 00177 A9 movw ax,[de] ;[INF] 1, 1 + 1034 1034 00178 12 movw bc,ax ;[INF] 1, 1 + 1035 1035 00179 8C01 mov a,[hl+1] ; i ;[INF] 2, 1 + 1036 1036 0017B F0 clrb x ;[INF] 1, 1 + 1037 1037 0017C 317E shrw ax,7 ;[INF] 2, 1 + 1038 1038 0017E 33 xchw ax,bc ;[INF] 1, 1 + 1039 1039 0017F R780200 movw _tasks_immed[bc],ax ;[INF] 3, 1 + 1040 1040 ; line 264 : tasks_immed[ j ] = TSK_IMM_DELETED_; + 1041 1041 $DGL 0,89 + 1042 1042 00182 8B mov a,[hl] ; j ;[INF] 1, 1 + 1043 1043 00183 RFD0000 call !bs_S0096 ;[INF] 3, 3 + 1044 1044 ; line 265 : i += 1; + 1045 1045 $DGL 0,90 + 1046 1046 00186 615901 inc [hl+1] ; i ;[INF] 3, 2 + 1047 1047 00189 ??eb12_renge_task_immed_run: + 1048 1048 ; line 266 : } + 1049 1049 ; line 267 : } + 1050 1050 $DGL 0,92 + 1051 1051 00189 ??eb0D_renge_task_immed_run: + 1052 1052 00189 EF09 br $?L0057 ;[INF] 2, 3 + 1053 1053 0018B ?L0056: + 1054 1054 ; line 268 : else + 1055 1055 ; line 269 : { + 1056 1056 0018B ??bb13_renge_task_immed_run: + 1057 1057 ; line 270 : #ifdef _renge_test_ + 1058 1058 ; line 271 : // タスクが滞留 + 1059 1059 ; line 272 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + 1060 1060 $DGL 0,97 + 1061 1061 0018B RFD0900 call !bs_S0094 ;[INF] 3, 3 + 1062 1062 0018E 61F8 sknz ;[INF] 2, 1 + 1063 1063 ; line 273 : { + 1064 1064 00190 ??bb14_renge_task_immed_run: + 1065 1065 ; line 274 : NOP(); + 1066 1066 $DGL 0,99 + 1067 1067 00190 00 nop ;[INF] 1, 1 + 1068 1068 00191 ??eb14_renge_task_immed_run: + 1069 1069 ; line 275 : // そんなはずない + 1070 1070 ; line 276 : } + 1071 1071 00191 ?L0070: + 1072 1072 ; line 277 : #endif + 1073 1073 ; line 278 : i += 1; + 1074 1074 $DGL 0,103 + 1075 1075 00191 615901 inc [hl+1] ; i ;[INF] 3, 2 + 1076 1076 00194 ??eb13_renge_task_immed_run: + 1077 1077 ; line 279 : } + 1078 1078 00194 ?L0057: + 1079 1079 ; line 280 : EI(); + 1080 1080 $DGL 0,105 + 1081 1081 00194 717AFA ei ;[INF] 3, 4 + 1082 1082 ; line 281 : if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + 1083 1083 $DGL 0,106 + 1084 1084 00197 RFD0900 call !bs_S0094 ;[INF] 3, 3 + 1085 1085 0019A DF03 bnz $?L0072 ;[INF] 2, 4 + 1086 1086 ; line 282 : { + 1087 1087 0019C ??bb15_renge_task_immed_run: + 1088 1088 ; line 283 : #ifdef _renge_test_ + 1089 1089 ; line 284 : NOP(); + 1090 1090 $DGL 0,109 + 1091 1091 0019C 00 nop ;[INF] 1, 1 + 1092 1092 ; line 285 : #endif + 1093 1093 ; line 286 : break; + 1094 1094 $DGL 0,111 + 1095 1095 0019D EF06 br $?L0054 ;[INF] 2, 3 + 1096 1096 0019F ??eb15_renge_task_immed_run: + 1097 1097 ; line 287 : // リストの最後だった + 1098 1098 ; line 288 : } + 1099 1099 0019F ?L0072: + 1100 1100 0019F ??eb0C_renge_task_immed_run: + 1101 1101 ; line 289 : } + 1102 1102 $DGL 0,114 + 1103 1103 0019F 615900 inc [hl+0] ; j ;[INF] 3, 2 + 1104 1104 001A2 RED1101 br !?L0053 ;[INF] 3, 3 + 1105 1105 001A5 ?L0054: + 1106 1106 ; line 290 : DI(); + 1107 1107 $DGL 0,115 + 1108 1108 001A5 717BFA di ;[INF] 3, 4 + 1109 1109 ; line 291 : + 1110 1110 ; line 292 : // ここまでで完全に前詰めされている + 1111 1111 ; line 293 : for( j = 0; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + 1112 1112 $DGL 0,118 + 1113 1113 001A8 CC0000 mov [hl+0],#00H ; j,0 ;[INF] 3, 1 + 1114 1114 001AB ?L0074: + 1115 1115 001AB 8B mov a,[hl] ; j ;[INF] 1, 1 + 1116 1116 001AC 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 1117 1117 001AE DE3D bnc $?L0075 ;[INF] 2, 4 + 1118 1118 ; line 294 : { + 1119 1119 001B0 ??bb16_renge_task_immed_run: + 1120 1120 ; line 295 : if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) + 1121 1121 $DGL 0,120 + 1122 1122 001B0 8B mov a,[hl] ; j ;[INF] 1, 1 + 1123 1123 001B1 F0 clrb x ;[INF] 1, 1 + 1124 1124 001B2 317E shrw ax,7 ;[INF] 2, 1 + 1125 1125 001B4 R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 1126 1126 001B7 14 movw de,ax ;[INF] 1, 1 + 1127 1127 001B8 A9 movw ax,[de] ;[INF] 1, 1 + 1128 1128 001B9 6168 or a,x ;[INF] 2, 1 + 1129 1129 001BB DF1C bnz $?L0077 ;[INF] 2, 4 + 1130 1130 ; line 296 : { + 1131 1131 001BD ??bb17_renge_task_immed_run: + 1132 1132 ; line 297 : #ifdef _renge_test_ + 1133 1133 ; line 298 : NOP(); + 1134 1134 $DGL 0,123 + 1135 1135 001BD 00 nop ;[INF] 1, 1 + 1136 1136 ; line 299 : j += 1; + 1137 1137 $DGL 0,124 + 1138 1138 001BE 615900 inc [hl+0] ; j ;[INF] 3, 2 + 1139 1139 ; line 300 : for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + 1140 1140 $DGL 0,125 + 1141 1141 001C1 ?L0079: + 1142 1142 001C1 8B mov a,[hl] ; j ;[INF] 1, 1 + 1143 1143 001C2 4C08 cmp a,#08H ; 8 ;[INF] 2, 1 + 1144 1144 001C4 DE27 bnc $?L0075 ;[INF] 2, 4 + 1145 1145 ; line 301 : { + 1146 1146 001C6 ??bb18_renge_task_immed_run: + 1147 1147 ; line 302 : if( tasks_immed[ j ] != TSK_IMM_EMPTY_ + 1148 1148 ; ) + 1149 1149 $DGL 0,127 + 1150 1150 001C6 8B mov a,[hl] ; j ;[INF] 1, 1 + 1151 1151 001C7 F0 clrb x ;[INF] 1, 1 + 1152 1152 001C8 317E shrw ax,7 ;[INF] 2, 1 + 1153 1153 001CA R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 1154 1154 001CD 14 movw de,ax ;[INF] 1, 1 + 1155 1155 001CE A9 movw ax,[de] ;[INF] 1, 1 + 1156 1156 001CF 6168 or a,x ;[INF] 2, 1 + 1157 1157 001D1 61E8 skz ;[INF] 2, 1 + 1158 1158 ; line 303 : { + 1159 1159 001D3 ??bb19_renge_task_immed_run: + 1160 1160 ; line 304 : NOP(); // ? + 1161 1161 $DGL 0,129 + 1162 1162 001D3 00 nop ;[INF] 1, 1 + 1163 1163 001D4 ??eb19_renge_task_immed_run: + 1164 1164 ; line 305 : } + 1165 1165 001D4 ?L0082: + 1166 1166 001D4 ??eb18_renge_task_immed_run: + 1167 1167 ; line 306 : } + 1168 1168 $DGL 0,131 + 1169 1169 001D4 615900 inc [hl+0] ; j ;[INF] 3, 2 + 1170 1170 001D7 EFE8 br $?L0079 ;[INF] 2, 3 + 1171 1171 ; line 307 : #endif + 1172 1172 ; line 308 : break; + 1173 1173 001D9 ??eb17_renge_task_immed_run: + 1174 1174 ; line 309 : // リストの最後 + 1175 1175 ; line 310 : } + 1176 1176 001D9 ?L0077: + 1177 1177 ; line 311 : if( tasks_immed[ j ] == TSK_IMM_DELETED_ ) + 1178 1178 $DGL 0,136 + 1179 1179 001D9 8B mov a,[hl] ; j ;[INF] 1, 1 + 1180 1180 001DA F0 clrb x ;[INF] 1, 1 + 1181 1181 001DB 317E shrw ax,7 ;[INF] 2, 1 + 1182 1182 001DD R040200 addw ax,#loww (_tasks_immed) ;[INF] 3, 1 + 1183 1183 001E0 14 movw de,ax ;[INF] 1, 1 + 1184 1184 001E1 A9 movw ax,[de] ;[INF] 1, 1 + 1185 1185 001E2 E7 onew bc ;[INF] 1, 1 + 1186 1186 001E3 43 cmpw ax,bc ;[INF] 1, 1 + 1187 1187 001E4 DF02 bnz $?L0084 ;[INF] 2, 4 + 1188 1188 ; line 312 : { + 1189 1189 001E6 ??bb1A_renge_task_immed_run: + 1190 1190 ; line 313 : tasks_immed[ j ] = TSK_IMM_EMPTY_; + 1191 1191 $DGL 0,138 + 1192 1192 001E6 F6 clrw ax ;[INF] 1, 1 + 1193 1193 001E7 B9 movw [de],ax ;[INF] 1, 1 + 1194 1194 001E8 ??eb1A_renge_task_immed_run: + 1195 1195 ; line 314 : } + 1196 1196 001E8 ?L0084: + 1197 1197 001E8 ??eb16_renge_task_immed_run: + 1198 1198 ; line 315 : } + 1199 1199 $DGL 0,140 + 1200 1200 001E8 615900 inc [hl+0] ; j ;[INF] 3, 2 + 1201 1201 001EB EFBE br $?L0074 ;[INF] 2, 3 + 1202 1202 001ED ?L0075: + 1203 1203 ; line 316 : EI(); + 1204 1204 $DGL 0,141 + 1205 1205 001ED 717AFA ei ;[INF] 3, 4 + 1206 1206 001F0 ??eb0A_renge_task_immed_run: + 1207 1207 ; line 317 : } + 1208 1208 001F0 ?L0049: + 1209 1209 001F0 ??eb09_renge_task_immed_run: + 1210 1210 ; line 318 : } + 1211 1211 001F0 ??eb00_renge_task_immed_run: + 1212 1212 ; line 319 : } + 1213 1213 ; line 320 : #if 0 + 1214 1214 ; line 321 : while( last_task_id != 0xFF ); // タスクが残っていたら延々再実 + 1215 1215 ; 行 + 1216 1216 ; line 322 : #else + 1217 1217 ; line 323 : while( 0 ); + 1218 1218 ; line 324 : #endif + 1219 1219 ; line 325 : + 1220 1220 ; line 326 : if( last_task_id != 0xFF ) + 1221 1221 $DGL 0,151 + 1222 1222 001F0 8C02 mov a,[hl+2] ; last_task_id ;[INF] 2, 1 + 1223 1223 001F2 81 inc a ;[INF] 1, 1 + 1224 1224 001F3 DD03 bz $?L0086 ;[INF] 2, 4 + 1225 1225 ; line 327 : { + 1226 1226 001F5 ??bb1B_renge_task_immed_run: + 1227 1227 ; line 328 : // まだタスクが残ってる（また呼んでね） + 1228 1228 ; line 329 : return( ERR_ERR ); + 1229 1229 $DGL 0,154 + 1230 1230 001F5 E7 onew bc ;[INF] 1, 1 + 1231 1231 001F6 EF01 br $?L0031 ;[INF] 2, 3 + 1232 1232 001F8 ??eb1B_renge_task_immed_run: + 1233 1233 ; line 330 : } + 1234 1234 001F8 ?L0086: + 1235 1235 ; line 331 : + 1236 1236 ; line 332 : return( ERR_SUCCESS ); + 1237 1237 $DGL 0,157 + 1238 1238 001F8 F7 clrw bc ;[INF] 1, 1 + 1239 1239 ; line 333 : } + 1240 1240 001F9 ?L0031: + 1241 1241 $DGL 0,158 + 1242 1242 001F9 ??ef_renge_task_immed_run: + 1243 1243 001F9 1004 addw sp,#04H ;[INF] 2, 1 + 1244 1244 001FB C6 pop hl ;[INF] 1, 1 + 1245 1245 001FC D7 ret ;[INF] 1, 6 + 1246 1246 001FD ??ee_renge_task_immed_run: + 1247 1247 ; line 334 : + 1248 1248 ; line 335 : + 1249 1249 ; line 336 : + 1250 1250 ; line 337 : /*************************************************************** + 1251 1251 ; *************** + 1252 1252 ; line 338 : 単位は ms + 1253 1253 ; line 339 : NOPを回すだけ、指定時間CPUを *占有します* 。 + 1254 1254 ; line 340 : 割り込みとか入るとその分遅れます。 + 1255 1255 ; line 341 : 少し誤差あります。 + 1256 1256 ; line 342 : *************************************************************** + 1257 1257 ; **************/ + 1258 1258 ; line 343 : void wait_ms( u8 ms ){ + 1259 1259 001FD _wait_ms: + 1260 1260 $DGL 1,222 + 1261 1261 001FD C7 push hl ;[INF] 1, 1 + 1262 1262 001FE C1 push ax ;[INF] 1, 1 + 1263 1263 001FF C1 push ax ;[INF] 1, 1 + 1264 1264 00200 FBF8FF movw hl,sp ;[INF] 3, 1 + 1265 1265 00203 ??bf_wait_ms: + 1266 1266 ; line 344 : u16 fine; + 1267 1267 ; line 345 : + 1268 1268 ; line 346 : WDT_Restart(); + 1269 1269 $DGL 0,4 + 1270 1270 00203 RFD0000 call !_WDT_Restart ;[INF] 3, 3 + 1271 1271 ; line 347 : // まだ適当です！ + 1272 1272 ; line 348 : while( ms != 0 ){ + 1273 1273 $DGL 0,6 + 1274 1274 00206 ?L0090: + 1275 1275 00206 8C02 mov a,[hl+2] ; ms ;[INF] 2, 1 + 1276 1276 00208 D1 cmp0 a ;[INF] 1, 1 + 1277 1277 00209 DD12 bz $?L0091 ;[INF] 2, 4 + 1278 1278 0020B ??bb00_wait_ms: + 1279 1279 ; line 349 : ms--; + 1280 1280 $DGL 0,7 + 1281 1281 0020B 616902 dec [hl+2] ; ms ;[INF] 3, 2 + 1282 1282 ; line 350 : #ifdef _OVERCLOCK_ + 1283 1283 ; line 351 : fine = 860; + 1284 1284 $DGL 0,9 + 1285 1285 0020E 305C03 movw ax,#035CH ; 860 ;[INF] 3, 1 + 1286 1286 00211 BB movw [hl],ax ; fine ;[INF] 1, 1 + 1287 1287 ; line 352 : #else + 1288 1288 ; line 353 : fine = 430; + 1289 1289 ; line 354 : #endif + 1290 1290 ; line 355 : while( fine != 0 ){ + 1291 1291 $DGL 0,13 + 1292 1292 00212 ?L0092: + 1293 1293 00212 F6 clrw ax ;[INF] 1, 1 + 1294 1294 00213 614900 cmpw ax,[hl+0] ; fine ;[INF] 3, 1 + 1295 1295 00216 DDEE bz $?L0090 ;[INF] 2, 4 + 1296 1296 00218 ??bb01_wait_ms: + 1297 1297 ; line 356 : fine -= 1; + 1298 1298 $DGL 0,14 + 1299 1299 00218 618900 decw [hl+0] ; fine ;[INF] 3, 2 + 1300 1300 0021B ??eb01_wait_ms: + 1301 1301 ; line 357 : } + 1302 1302 $DGL 0,15 + 1303 1303 0021B EFF5 br $?L0092 ;[INF] 2, 3 + 1304 1304 0021D ??eb00_wait_ms: + 1305 1305 ; line 358 : } + 1306 1306 0021D ?L0091: + 1307 1307 ; line 359 : } + 1308 1308 $DGL 0,17 + 1309 1309 0021D ??ef_wait_ms: + 1310 1310 0021D 1004 addw sp,#04H ;[INF] 2, 1 + 1311 1311 0021F C6 pop hl ;[INF] 1, 1 + 1312 1312 00220 D7 ret ;[INF] 1, 6 + 1313 1313 00221 ??ee_wait_ms: + 1314 1314 + 1315 1315 ----- @@CODEL CSEG + 1316 1316 + 1317 1317 ----- @@BASE CSEG BASE + 1318 1318 END + 1319 1319 + 1320 1320 + 1321 1321 ; *** Code Information *** + 1322 1322 ; + 1323 1323 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c + 1324 1324 ; + 1325 1325 ; $FUNC renge_init(53) + 1326 1326 ; void=(void) + 1327 1327 ; CODE SIZE= 3 bytes, CLOCK_SIZE= 3 clocks, STACK_SIZE= 0 bytes + 1328 1328 ; + 1329 1329 ; $CALL renge_task_immed_init(54) + 1330 1330 ; void=(void) + 1331 1331 ; + 1332 1332 ; $FUNC renge_task_interval_run(81) + 1333 1333 ; bc=(void) + 1334 1334 ; CODE SIZE= 43 bytes, CLOCK_SIZE= 45 clocks, STACK_SIZE= 6 bytes + 1335 1335 ; + 1336 1336 ; $CALL (92) + 1337 1337 ; void=(void) + 1338 1338 ; + 1339 1339 ; $CALL renge_task_immed_run(94) + 1340 1340 ; bc=(void) + 1341 1341 ; + 1342 1342 ; $FUNC renge_task_immed_init(117) + 1343 1343 ; void=(void) + 1344 1344 ; CODE SIZE= 21 bytes, CLOCK_SIZE= 24 clocks, STACK_SIZE= 2 bytes + 1345 1345 ; + 1346 1346 ; $FUNC renge_task_immed_add(131) + 1347 1347 ; bc=(pointer new_task:ax) + 1348 1348 ; CODE SIZE= 66 bytes, CLOCK_SIZE= 98 clocks, STACK_SIZE= 10 bytes + 1349 1349 ; + 1350 1350 ; $FUNC renge_task_immed_run(176) + 1351 1351 ; bc=(void) + 1352 1352 ; CODE SIZE= 341 bytes, CLOCK_SIZE= 381 clocks, STACK_SIZE= 10 bytes + 1353 1353 ; + 1354 1354 ; $CALL (196) + 1355 1355 ; bc=(void) + 1356 1356 ; + 1357 1357 ; $FUNC wait_ms(343) + 1358 1358 ; void=(unsigned char ms:x) + 1359 1359 ; CODE SIZE= 36 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 10 bytes + 1360 1360 ; + 1361 1361 ; $CALL WDT_Restart(346) + 1362 1362 ; void=(void) + 1363 1363 + 1364 1364 ; Target chip : uPD79F0104 + 1365 1365 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.3 @@BITS +00000 00000H @@CNST +00000 00016H @@R_INIT +00000 00016H @@INIT +00000 00012H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00221H ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/renge.rel b/branches/0.10(X3)/renge.rel new file mode 100644 index 0000000..8abae1b Binary files /dev/null and b/branches/0.10(X3)/renge.rel differ diff --git a/branches/0.10(X3)/renge/renge.c b/branches/0.10(X3)/renge/renge.c new file mode 100644 index 0000000..a646dcd --- /dev/null +++ b/branches/0.10(X3)/renge/renge.c @@ -0,0 +1,359 @@ +#pragma section @@CODE ROM_CODE +#pragma nop +#pragma ei +#pragma di +#pragma sfr + +/****************************************************************************** + タスクシステム？ + なるほど、iTRONにはコンフィギュレータがあるはずだ。 + →作りました + ctr_mcu_config.rb 参照。 task_config.hが作成されます。 + *****************************************************************************/ +#include "renge.h" +#include "renge_task_intval.h" +#include "renge_task_immediate.h" +#include "..\WDT.h" +#include "..\config.h" +#include "..\user_define.h" + + +#define _renge_test_ + +//****************************************************************************** +bit renge_flg_interval; +bit renge_task_interval_run_force; +bit renge_task_immediate_not_empty; + +u8 system_time; + + + +#include "..\bsr_system.h" +extern system_status_ system_status; + + + +//****************************************************************************** +static void renge_task_immed_init(); +static void renge_task_immed_del(); + + + +//****************************************************************************** +task_status_immed ( *tasks_immed[ TASK_IMMED_RUN_LIST_MAX ] )(); + + + +/****************************************************************************** + 初期化 +・タスクシステムの動的部分の初期化 +・インターバルタイマ + *****************************************************************************/ +void renge_init(){ + renge_task_immed_init(); + /* + イベントタイマのセットなど + 今回はRTCを流用しているのでコメントアウト + #define renge_tick 19xxxxxxx [ms] + renge_interval_init(); → RTC_init(); + */ +} + + + +/****************************************************************************** + システムチックを進める + *****************************************************************************/ +/* +void renge_interval(){ +// RTCがやってくれる +→__interrupt void int_rtc_int(); +} +*/ + + + +/****************************************************************************** + コンパイル時に決まっている、インターバル起動のタスク + そのうち、逐次起動と混ぜるかもしれない。 + *****************************************************************************/ +err renge_task_interval_run(){ + u8 i; + + // インターバル起動 + if(( renge_flg_interval == 1 ) + || ( renge_task_interval_run_force != 0 )) // todo 統合 + { + renge_task_interval_run_force = 0; + renge_flg_interval = 0; + for( i = 0; i != TSK_LAST; i += 1 ) + { + tasks[ i ](); + // 逐次起動タスクがあったら起動しておく + renge_task_immed_run(); + } + } + return( ERR_SUCCESS ); +} + + + +/***************************************************************************** + ■逐一起動タスク■ + + ●task_immed を返す関数。 + ●システムtick、何らかの割り込み（I2C通信完了など）で + スリープから復帰したタイミングで実行されます。 + +■返値　ERR_FINISED　タスクを削除 +　　　　それ以外 次のタイミングでまた実行 + + *****************************************************************************/ + + +/************************************** + **************************************/ +void renge_task_immed_init(){ + u8 i; + + for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i++ ){ + tasks_immed[ i ] = TSK_IMM_EMPTY_; + } +} + + + +/************************************** + 逐次実行タスクの登録 + 割り込み禁止 36us → + **************************************/ +err renge_task_immed_add( task_status* new_task ){ + u8 i; + + // リストの空きの先頭に登録 + // 削除したばかりのタスクは、削除マーク(TSK_IMM_DELETED_)となり、空きとは明示的に区別される + // 重複登録を避ける + for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) + { + if( tasks_immed[ i ] != TSK_IMM_EMPTY_ ) + { + // 重複登録チェック + if( tasks_immed[ i ] == new_task ) + { + // 重複登録はしない + NOP(); + return( ERR_ERR ); + } + } + else + { + // 空きを見つけた + // もたもたしているうちに割り込み等から割り込まれるのを考慮 + // 滅多にないはずだが + for( ; i < TASK_IMMED_RUN_LIST_MAX; i += 1 ) + { + if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + { + tasks_immed[ i ] = new_task; + return( ERR_SUCCESS ); + } + } + // 割り込まれてタスク登録できなくなった + return( ERR_ERR ); + } + } + // タスク登録しすぎ(無いはず + NOP(); // デバッガで捕まえるため + return( ERR_ERR ); +} + + + +/************************************** + 逐次実行タスクの実行 + **************************************/ +err renge_task_immed_run(){ + u8 list_id; + u8 last_task_id; + + do{ + last_task_id = 0xFF; + for( list_id = 0; list_id < TASK_IMMED_RUN_LIST_MAX; list_id += 1 ){ + if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ){ +#ifdef _renge_test_ + if( tasks_immed[ list_id ] == TSK_IMM_DELETED_ ) + { + NOP(); + // タスク管理の不備 + // 存在しないタスクを実行しようとした + // タスクの削除後の処理がまずい + // 予期しないタイミングで immed_run が呼ばれた + } + else +#endif + { + if( tasks_immed[ list_id ]() == ERR_SUCCESS ) + { + tasks_immed[ list_id ] = TSK_IMM_DELETED_; + } + last_task_id = list_id; + } + } +#ifdef _renge_test_ + else + { + list_id += 1; + for( ; list_id < TASK_IMMED_RUN_LIST_MAX; list_id++ ) + { + if( tasks_immed[ list_id ] != TSK_IMM_EMPTY_ ) + { + NOP(); // ? + } + } + break; + } +#endif + } + + // タスク削除 + { + if( last_task_id != 0xFF ) + { + u8 i,j; + +#ifdef _renge_test_ + if ( tasks_immed[ 1 ] != 0 ){ + NOP(); + } +#endif + // リスト前詰め + + i = 0; // 前詰め後リストの最後尾 + j = 1; // リストの後ろの方のタスクを探す + for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + { + DI(); + if( tasks_immed[ i ] == TSK_IMM_DELETED_ ) + { + if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) + { + // リストの最後だった + for( ; i < j ; i += 1 ) + { + tasks_immed[ i ] = TSK_IMM_EMPTY_; + } +#ifdef _renge_test_ + /// ほんと? + j += 1; + for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + { + if( tasks_immed[ j ] != TSK_IMM_EMPTY_ ) + { + NOP(); // ? + } + } +#endif + EI(); + break; + } + if( tasks_immed[ j ] != TSK_IMM_DELETED_ ) + { + // 探索隊が前詰めすべきタスクを見つけた + tasks_immed[ i ] = tasks_immed[ j ]; + tasks_immed[ j ] = TSK_IMM_DELETED_; + i += 1; + } + } + else + { +#ifdef _renge_test_ + // タスクが滞留 + if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + { + NOP(); + // そんなはずない + } +#endif + i += 1; + } + EI(); + if( tasks_immed[ i ] == TSK_IMM_EMPTY_ ) + { +#ifdef _renge_test_ + NOP(); +#endif + break; + // リストの最後だった + } + } + DI(); + + // ここまでで完全に前詰めされている + for( j = 0; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + { + if( tasks_immed[ j ] == TSK_IMM_EMPTY_ ) + { +#ifdef _renge_test_ + NOP(); + j += 1; + for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ ) + { + if( tasks_immed[ j ] != TSK_IMM_EMPTY_ ) + { + NOP(); // ? + } + } +#endif + break; + // リストの最後 + } + if( tasks_immed[ j ] == TSK_IMM_DELETED_ ) + { + tasks_immed[ j ] = TSK_IMM_EMPTY_; + } + } + EI(); + } + } + } +#if 0 + while( last_task_id != 0xFF ); // タスクが残っていたら延々再実行 +#else + while( 0 ); +#endif + + if( last_task_id != 0xFF ) + { + // まだタスクが残ってる（また呼んでね） + return( ERR_ERR ); + } + + return( ERR_SUCCESS ); +} + + + +/****************************************************************************** + 単位は ms + NOPを回すだけ、指定時間CPUを *占有します* 。 + 割り込みとか入るとその分遅れます。 + 少し誤差あります。 + *****************************************************************************/ +void wait_ms( u8 ms ){ + u16 fine; + + WDT_Restart(); + // まだ適当です！ + while( ms != 0 ){ + ms--; +#ifdef _OVERCLOCK_ + fine = 860; +#else + fine = 430; +#endif + while( fine != 0 ){ + fine -= 1; + } + } +} diff --git a/branches/0.10(X3)/renge/renge.h b/branches/0.10(X3)/renge/renge.h new file mode 100644 index 0000000..2c1b5bc --- /dev/null +++ b/branches/0.10(X3)/renge/renge.h @@ -0,0 +1,32 @@ +#ifndef __renge__ +#define __renge__ + +//****************************************************************************** + + + +//****************************************************************************** +#include "renge_defs.h" +#include "renge_task_immediate.h" +// #include "renge_task_interval_run.h" // 外から強制起動禁止！ + + +//****************************************************************************** +void renge_init(); +void renge_task_immed_init(); +err renge_task_immed_run(); +err renge_task_immed_add( task_immed ); +// static err renge_task_immed_del( u8 ); + +void wait_ms( u8 ); + + + +//****************************************************************************** +err renge_task_interval_run(); +extern bit renge_task_interval_run_force; +extern bit renge_flg_interval; + +extern u8 system_time; + +#endif diff --git a/branches/0.10(X3)/renge/renge_defs.h b/branches/0.10(X3)/renge/renge_defs.h new file mode 100644 index 0000000..bf0bb48 --- /dev/null +++ b/branches/0.10(X3)/renge/renge_defs.h @@ -0,0 +1,56 @@ +#ifndef __renge_defs__ +#define __renge_defs__ +/****************************************************************************** + Renge Ver.0 (2009/04/09) + 2009- 7k4jhl R.Fujita @ RED.nintendo + + OSにはほど遠い、簡易的なタスクシステム。 + Range の Typo ではないです。レンゲです。 + + なんと レンゲ は俗称で日本名は ゲンゲ + 小さいけど役に立つ役草です。 + 大きく育ってね！ + ******************************************************************************/ + +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef signed short s16; + +typedef unsigned char err; + + + +// ************************************ +#define SYS_INTERVAL_TICK 1.953 + + + +// ************************************ +typedef enum{ + ERR_SUCCESS = 0, + ERR_ERR +}ERR; + + +typedef enum{ + ERR_FINISED = 0, + ERR_CONTINUE +}IMMED_TASK_ERR; + + + +/************************************** + インターバル起動 + *************************************/ +typedef void task_status; + + +/************************************** + 逐一起動のタスクリスト + 廃止になるかもしれないが + *************************************/ +typedef IMMED_TASK_ERR task_status_immed; + + +#endif diff --git a/branches/0.10(X3)/renge/renge_task_config.rb b/branches/0.10(X3)/renge/renge_task_config.rb new file mode 100755 index 0000000..4da03da --- /dev/null +++ b/branches/0.10(X3)/renge/renge_task_config.rb @@ -0,0 +1,60 @@ +#!/usr/bin/ruby -Ks + +tasklist = Array.new + + +if( ARGV[0] == nil ) + printf( "既定ファイル renge_tasks.txt を使用します" ) + datfile = "renge_tasks.txt" +else + datfile = ARGV[0] +end + +if( !File.exist?( datfile ) ) + printf("設定ファイルが見つかりません。") + exit( 1 ) +end + + +setting = File.open( datfile ) + +setting.each{|dat| + dat.chomp! + if( dat != nil ) + tasklist << dat + end +} + +tasklist.each{|dat| + printf( "\n%s" , dat ) +} +printf( "\n----------\nタスク数 %d \n", tasklist.size ) + + +#----- 静的タスクの列挙 ------------------------------------------------------- +conf = File.new( "renge_task_intval.h", "w+" ) + +conf << "/*スクリプトによる自動生成です。手動で書き換えない方がよいです*/\n\n" +conf << "#ifndef __renge_task__\n#define __renge_task__\n\n" +conf << "#include \"renge_defs.h\"\n\n" + +conf << "enum {\n " +tasklist.each{|dat| + conf << "TSK_" << dat.upcase << ", " +} +conf << "TSK_LAST \n };\n\n" + + +tasklist.each{|dat| + conf << "extern void tsk_" << dat << "();\n" +} +conf << "\n" + +conf << "static const task_status ( *tasks[ TSK_LAST ] )() = {\n" +tasklist.each{|dat| + conf << " tsk_" << dat << ",\n" +} +conf << " };\n" + + +conf << "\n\n#endif\n" diff --git a/branches/0.10(X3)/renge/renge_task_immediate.h b/branches/0.10(X3)/renge/renge_task_immediate.h new file mode 100644 index 0000000..0eab45c --- /dev/null +++ b/branches/0.10(X3)/renge/renge_task_immediate.h @@ -0,0 +1,26 @@ +#ifndef __tasks__ +#define __tasks__ + +#include "renge_defs.h" + +// ************************************* +#define TASK_IMMED_RUN_LIST_MAX 8 + + +extern task_status_immed do_command0( ); +extern task_status_immed ntr_pmic_comm(); +extern task_status_immed acc_read(); +extern task_status_immed acc_write(); +extern task_status_immed tski_mcu_info_read(); +//extern task_status_immed acc_hosu_set(); +extern task_status_immed tski_mcu_reset(); + + + +// ************************************* +#define TSK_IMM_EMPTY_ ( void * )( 0x0000 ) +#define TSK_IMM_DELETED_ ( void * )( 0x0001 ) + + + +#endif diff --git a/branches/0.10(X3)/renge/renge_task_intval.h b/branches/0.10(X3)/renge/renge_task_intval.h new file mode 100644 index 0000000..1e444c0 --- /dev/null +++ b/branches/0.10(X3)/renge/renge_task_intval.h @@ -0,0 +1,39 @@ +/*スクリプトによる自動生成です。手動で書き換えない方がよいです*/ + +#ifndef __renge_task__ +#define __renge_task__ + +#include "renge_defs.h" + +enum { + TSK_SW, TSK_ADC, TSK_BATT, TSK_LED_POW, TSK_LED_WIFI, TSK_LED_NOTIFY, TSK_LED_CAM, TSK_MISC_STAT, TSK_DEBUG, TSK_DEBUG2, TSK_SYS, TSK_LAST + }; + +extern void tsk_sw(); +extern void tsk_adc(); +extern void tsk_batt(); +extern void tsk_led_pow(); +extern void tsk_led_wifi(); +extern void tsk_led_notify(); +extern void tsk_led_cam(); +extern void tsk_misc_stat(); +extern void tsk_debug(); +extern void tsk_debug2(); +extern void tsk_sys(); + +static const task_status ( *tasks[ TSK_LAST ] )() = { + tsk_sw, + tsk_adc, + tsk_batt, + tsk_led_pow, + tsk_led_wifi, + tsk_led_notify, + tsk_led_cam, + tsk_misc_stat, + tsk_debug, + tsk_debug2, + tsk_sys, + }; + + +#endif diff --git a/branches/0.10(X3)/renge/renge_tasks.txt b/branches/0.10(X3)/renge/renge_tasks.txt new file mode 100644 index 0000000..79ad5bd --- /dev/null +++ b/branches/0.10(X3)/renge/renge_tasks.txt @@ -0,0 +1,11 @@ +sw +adc +batt +led_pow +led_wifi +led_notify +led_cam +misc_stat +debug +debug2 +sys diff --git a/branches/0.10(X3)/rtc.c b/branches/0.10(X3)/rtc.c new file mode 100644 index 0000000..fd0f60d --- /dev/null +++ b/branches/0.10(X3)/rtc.c @@ -0,0 +1,180 @@ +/* ======================================================== + RTC + ======================================================== */ +#pragma sfr +#pragma inline + + +#include "incs.h" + + + +// ======================================================== +u8 rtc_work[7]; +bit rtc_lock; +bit rtc_dirty; +bit rtc_alarm_dirty; + +/* ======================================================== + ペリフェラルの初期化 + レジスタの電池交換ビットのセット + ======================================================== */ +void RTC_init( void ) +{ + + if( !RTCEN ) // ビットが立っていたらリブート + { + RTCEN = 1; // モジュールON + + // RTC設定 + RTCC0 = 0b00001000; /* 動作停止、24時間制、32k出力「まだなし」、定周期割り込みなし */ + RTCC1 = 0b11000000; /* アラーム割り込み有効＆動作開始 */ + RTCC2 = 0b10000000; /* インターバル:32k/2^6=2ms、RTCDIV出力なし */ + + SEC = 0x00; + MIN = 0x00; + HOUR = 0x15; + DAY = 0x01; + WEEK = 0x00; + MONTH = 0x11; + YEAR = 0x09; + + ALARMWW = 0x7F; + + vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT; + } + // 割り込み設定 + RTCIF = 0; + RTCIIF = 0; + RTCMK = 1; /* 割り込み(定周期)禁止 */ + RTCIMK = 0; /* 割り込み(アラーム&インターバル)許可 */ + + RTCE = 1; /* 動作開始 */ + + RWAIT = 1; + while( !RWST ) + {; + } + RWAIT = 0; + + rtc_lock = 0; + rtc_dirty = 0; + rtc_alarm_dirty = 0; +} + + + +/* ======================================================== + RTC アラーム割り込み + 2^6/fXT（1.953125 ms） + ======================================================== */ +__interrupt void int_rtc( ) +{ + // 日付も指定日で + if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY ) + && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH ) + && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) ) + { + if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) == 0 ) + { + vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM; + IRQ0_ast; + // マスクをしてあったら、電源を入れません + if(( system_status.pwr_state == BT_CHARGE ) || + ( system_status.pwr_state == OFF )) + { + system_status.poweron_reason = RTC_ALARM; + } + } + } +} + + + +/* ======================================================== + RTC のリード + レジスタは、sec,min,hour,week,day,month,year の順 + ======================================================== */ +void rtc_buf_reflesh( ) +{ + if( rtc_lock == 0 ) + { + rtc_lock = 1; + RWAIT = 1; + while( !RWST ) + {; + } + + memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 ); + RWAIT = 0; +// renge_task_immed_add( tski_rtc_close ); + } +} + + + +/* ======================================================== + RTC のライト + set_rtc_close と対で使って下さい。 + こいつはバッファにコピーするだけで、 + 実際にRTCにセットするのはset_rtc_close()です。 + ======================================================== */ +void set_rtc( u8 adrs, u8 data ) +{ + if( rtc_dirty == 0 ) + { + rtc_dirty = 1; + memcpy( rtc_work, &SEC, 7 ); +// renge_task_immed_add( tski_rtc_close ); // I2C終了時に行う + } + rtc_work[adrs] = data; +} + + + +/* ======================================================== + 必要ならば、RTCレジスタの更新 + ======================================================== */ +// task_status_immed tski_rtc_close(){ +void rtc_unlock( ) +{ + // リードロック +// if( rtc_lock != 0 ){ + rtc_lock = 0; +// } + + // ライトロック + if( rtc_dirty != 0 ) + { + rtc_dirty = 0; + RWAIT = 1; + while( !RWST ) + {; + } + memcpy( &SEC, rtc_work, 7 ); + RWAIT = 0; + } + + // アラームセット + if( rtc_alarm_dirty ) + { + WALE = 0; + ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN]; + ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR]; + rtc_dirty = 0; + WALE = 1; + } +} + + + + + +/* ======================================================== + RTC システムチックタイマ割り込みベクタ + 2^6/fXT（1.953125 ms） + ======================================================== */ +__interrupt void int_rtc_int( ) +{ + renge_flg_interval = 1; +} diff --git a/branches/0.10(X3)/rtc.h b/branches/0.10(X3)/rtc.h new file mode 100644 index 0000000..cd1a0f7 --- /dev/null +++ b/branches/0.10(X3)/rtc.h @@ -0,0 +1,21 @@ +#ifndef __rtc_h__ +#define __rtc_h__ + + +void RTC_init( void ); +void rtc_buf_reflesh( ); +void set_rtc( ); + +//task_status_immed tski_rtc_close(); +void rtc_unlock( ); + +// ------------------------------------ +#define RTC_32k_on() { RCLOE0 = 1; } +#define RTC_32k_off() { RCLOE0 = 0; } + + +// ------------------------------------ +extern bit rtc_alarm_dirty; + + +#endif diff --git a/branches/0.10(X3)/rtc.prn b/branches/0.10(X3)/rtc.prn new file mode 100644 index 0000000..affdb00 --- /dev/null +++ b/branches/0.10(X3)/rtc.prn @@ -0,0 +1,803 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\rtc.asm +Para-file: +In-file: inter_asm\rtc.asm +Obj-file: rtc.rel +Prn-file: rtc.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no rtc.c + 6 6 ; In-file : rtc.c + 7 7 ; Asm-file : inter_asm\rtc.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, rtc.c + 18 18 $DGS MOD_NAM, rtc, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 82 82 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 83 83 $DGS GLV_SYM, _RTC_init, U, U, 01H, 026H, 01H, 02H + 84 84 $DGS AUX_FUN, 00H, U, U, 051H, 00H, 00H + 85 85 $DGS BEG_FUN, ??bf_RTC_init, U, U, 00H, 065H, 01H, 00H + 86 86 $DGS AUX_BEG, 017H, 02H, 047H + 87 87 $DGS BEG_BLK, ??bb00_RTC_init, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_BEG, 04H, 00H, 04BH + 89 89 $DGS END_BLK, ??eb00_RTC_init, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_END, 017H + 91 91 $DGS BEG_BLK, ??bb01_RTC_init, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_BEG, 022H, 00H, 00H + 93 93 $DGS END_BLK, ??eb01_RTC_init, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_END, 023H + 95 95 $DGS END_FUN, ??ef_RTC_init, U, U, 00H, 065H, 01H, 00H + 96 96 $DGS AUX_END, 029H + 97 97 $DGS GLV_SYM, _int_rtc, U, U, 0E001H, 026H, 01H, 02H + 98 98 $DGS AUX_FUN, 00H, U, U, 067H, 00H, 00H + 99 99 $DGS BEG_FUN, ??bf_int_rtc, U, U, 00H, 065H, 01H, 00H + 100 100 $DGS AUX_BEG, 048H, 02H, 055H + 101 101 $DGS BEG_BLK, ??bb00_int_rtc, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_BEG, 06H, 00H, 057H + 103 103 $DGS BEG_BLK, ??bb01_int_rtc, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_BEG, 08H, 00H, 059H + 105 105 $DGS BEG_BLK, ??bb02_int_rtc, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_BEG, 0AH, 00H, 05DH + 107 107 $DGS END_BLK, ??eb02_int_rtc, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_END, 0AH + 109 109 $DGS BEG_BLK, ??bb03_int_rtc, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_BEG, 0EH, 00H, 00H + 111 111 $DGS END_BLK, ??eb03_int_rtc, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_END, 010H + 113 113 $DGS END_BLK, ??eb01_int_rtc, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_END, 011H + 115 115 $DGS END_BLK, ??eb00_int_rtc, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_END, 012H + 117 117 $DGS END_FUN, ??ef_int_rtc, U, U, 00H, 065H, 01H, 00H + 118 118 $DGS AUX_END, 013H + 119 119 $DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 026H, 01H, 02H + 120 120 $DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H + 121 121 $DGS BEG_FUN, ??bf_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H + 122 122 $DGS AUX_BEG, 063H, 02H, 06BH + 123 123 $DGS BEG_BLK, ??bb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H + 124 124 $DGS AUX_BEG, 03H, 00H, 06DH + 125 125 $DGS BEG_BLK, ??bb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_BEG, 07H, 00H, 00H + 127 127 $DGS END_BLK, ??eb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_END, 08H + 129 129 $DGS END_BLK, ??eb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_END, 0DH + 131 131 $DGS END_FUN, ??ef_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H + 132 132 $DGS AUX_END, 0EH + 133 133 $DGS GLV_SYM, _set_rtc, U, U, 01H, 026H, 01H, 02H + 134 134 $DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H + 135 135 $DGS BEG_FUN, ??bf_set_rtc, U, U, 00H, 065H, 01H, 00H + 136 136 $DGS AUX_BEG, 07BH, 02H, 07BH + 137 137 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 138 138 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H + 139 139 $DGS BEG_BLK, ??bb00_set_rtc, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_BEG, 03H, 00H, 00H + 141 141 $DGS END_BLK, ??eb00_set_rtc, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_END, 07H + 143 143 $DGS END_FUN, ??ef_set_rtc, U, U, 00H, 065H, 01H, 00H + 144 144 $DGS AUX_END, 09H + 145 145 $DGS GLV_SYM, _rtc_unlock, U, U, 01H, 026H, 01H, 02H + 146 146 $DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H + 147 147 $DGS BEG_FUN, ??bf_rtc_unlock, U, U, 00H, 065H, 01H, 00H + 148 148 $DGS AUX_BEG, 08CH, 02H, 085H + 149 149 $DGS BEG_BLK, ??bb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_BEG, 09H, 00H, 087H + 151 151 $DGS BEG_BLK, ??bb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 152 152 $DGS AUX_BEG, 0DH, 00H, 08DH + 153 153 $DGS END_BLK, ??eb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_END, 0EH + 155 155 $DGS END_BLK, ??eb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_END, 011H + 157 157 $DGS BEG_BLK, ??bb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_BEG, 015H, 00H, 00H + 159 159 $DGS END_BLK, ??eb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_END, 01BH + 161 161 $DGS END_FUN, ??ef_rtc_unlock, U, U, 00H, 065H, 01H, 00H + 162 162 $DGS AUX_END, 01CH + 163 163 $DGS GLV_SYM, _int_rtc_int, U, U, 0E001H, 026H, 01H, 02H + 164 164 $DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H + 165 165 $DGS BEG_FUN, ??bf_int_rtc_int, U, U, 00H, 065H, 01H, 00H + 166 166 $DGS AUX_BEG, 0B2H, 00H, 099H + 167 167 $DGS END_FUN, ??ef_int_rtc_int, U, U, 00H, 065H, 01H, 00H + 168 168 $DGS AUX_END, 03H + 169 169 $DGS GLV_SYM, _rtc_work, U, U, 0CH, 026H, 01H, 03H + 170 170 $DGS AUX_STR, 00H, 00H, 07H, 07H, 00H, 00H, 00H, 00H + 171 171 $DGS GLV_SYM, _rtc_lock, U, U, 034CH, 027H, 00H, 00H + 172 172 $DGS GLV_SYM, _rtc_dirty, U, U, 034CH, 027H, 00H, 00H + 173 173 $DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 027H, 00H, 00H + 174 174 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 175 175 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 176 176 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 177 177 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 178 178 $DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 02H, 00H, 00H + 179 179 + 180 180 EXTRN _vreg_ctr + 181 181 EXTRN _system_status + 182 182 EXTBIT _renge_flg_interval + 183 183 PUBLIC _rtc_work + 184 184 PUBLIC _rtc_lock + 185 185 PUBLIC _rtc_dirty + 186 186 PUBLIC _rtc_alarm_dirty + 187 187 PUBLIC _RTC_init + 188 188 PUBLIC _int_rtc + 189 189 PUBLIC _rtc_buf_reflesh + 190 190 PUBLIC _set_rtc + 191 191 PUBLIC _rtc_unlock + 192 192 PUBLIC _int_rtc_int + 193 193 + 194 194 ----- @@BITS BSEG + 195 195 00000.0 _rtc_lock DBIT + 196 196 00000.1 _rtc_dirty DBIT + 197 197 00000.2 _rtc_alarm_dirty DBIT + 198 198 + 199 199 ----- @@CNST CSEG MIRRORP + 200 200 00000 01 _lpf_coeff: DB 01H ; 1 + 201 201 00001 02 DB 02H ; 2 + 202 202 00002 02 DB 02H ; 2 + 203 203 00003 03 DB 03H ; 3 + 204 204 00004 03 DB 03H ; 3 + 205 205 00005 02 DB 02H ; 2 + 206 206 00006 00 DB 00H ; 0 + 207 207 00007 FE DB 0FEH ; 254 + 208 208 00008 FB DB 0FBH ; 251 + 209 209 00009 F7 DB 0F7H ; 247 + 210 210 0000A F3 DB 0F3H ; 243 + 211 211 0000B F0 DB 0F0H ; 240 + 212 212 0000C F0 DB 0F0H ; 240 + 213 213 0000D F3 DB 0F3H ; 243 + 214 214 0000E FA DB 0FAH ; 250 + 215 215 0000F 04 DB 04H ; 4 + 216 216 00010 12 DB 012H ; 18 + 217 217 00011 25 DB 025H ; 37 + 218 218 00012 38 DB 038H ; 56 + 219 219 00013 4D DB 04DH ; 77 + 220 220 00014 5F DB 05FH ; 95 + 221 221 00015 6E DB 06EH ; 110 + 222 222 00016 77 DB 077H ; 119 + 223 223 00017 7A DB 07AH ; 122 + 224 224 00018 77 DB 077H ; 119 + 225 225 00019 6E DB 06EH ; 110 + 226 226 0001A 5F DB 05FH ; 95 + 227 227 0001B 4D DB 04DH ; 77 + 228 228 0001C 38 DB 038H ; 56 + 229 229 0001D 25 DB 025H ; 37 + 230 230 0001E 12 DB 012H ; 18 + 231 231 0001F 04 DB 04H ; 4 + 232 232 00020 FA DB 0FAH ; 250 + 233 233 00021 F3 DB 0F3H ; 243 + 234 234 00022 F0 DB 0F0H ; 240 + 235 235 00023 F0 DB 0F0H ; 240 + 236 236 00024 F3 DB 0F3H ; 243 + 237 237 00025 F7 DB 0F7H ; 247 + 238 238 00026 FB DB 0FBH ; 251 + 239 239 00027 FE DB 0FEH ; 254 + 240 240 00028 00 DB 00H ; 0 + 241 241 00029 02 DB 02H ; 2 + 242 242 0002A 03 DB 03H ; 3 + 243 243 0002B 03 DB 03H ; 3 + 244 244 0002C 02 DB 02H ; 2 + 245 245 0002D 02 DB 02H ; 2 + 246 246 0002E 01 DB 01H ; 1 + 247 247 0002F 00 DB (1) + 248 248 + 249 249 ----- @@R_INIT CSEG UNIT64KP + 250 250 + 251 251 ----- @@INIT DSEG BASEP + 252 252 + 253 253 ----- @@DATA DSEG BASEP + 254 254 00000 _rtc_work: DS (7) + 255 255 00007 DS (1) + 256 256 + 257 257 ----- @@R_INIS CSEG UNIT64KP + 258 258 + 259 259 ----- @@INIS DSEG SADDRP + 260 260 + 261 261 ----- @@DATS DSEG SADDRP + 262 262 + 263 263 ----- @@CNSTL CSEG PAGE64KP + 264 264 + 265 265 ----- @@RLINIT CSEG UNIT64KP + 266 266 + 267 267 ----- @@INITL DSEG UNIT64KP + 268 268 + 269 269 ----- @@DATAL DSEG UNIT64KP + 270 270 + 271 271 ----- @@CALT CSEG CALLT0 + 272 272 + 273 273 ; line 1 : /* ======================================================== + 274 274 ; line 2 : RTC + 275 275 ; line 3 : ======================================================== */ + 276 276 ; line 4 : #pragma sfr + 277 277 ; line 5 : #pragma inline + 278 278 ; line 6 : + 279 279 ; line 7 : + 280 280 ; line 8 : #include "incs.h" + 281 281 ; line 9 : + 282 282 ; line 10 : + 283 283 ; line 11 : + 284 284 ; line 12 : // ======================================================== + 285 285 ; line 13 : u8 rtc_work[7]; + 286 286 ; line 14 : bit rtc_lock; + 287 287 ; line 15 : bit rtc_dirty; + 288 288 ; line 16 : bit rtc_alarm_dirty; + 289 289 ; line 17 : + 290 290 ; line 18 : /* ======================================================== + 291 291 ; line 19 : ペリフェラルの初期化 + 292 292 ; line 20 : レジスタの電池交換ビットのセット + 293 293 ; line 21 : ======================================================== */ + 294 294 ; line 22 : void RTC_init( void ) + 295 295 ; line 23 : { + 296 296 + 297 297 ----- ROM_CODE CSEG BASE + 298 298 00000 _RTC_init: + 299 299 $DGL 1,67 + 300 300 00000 C7 push hl ;[INF] 1, 1 + 301 301 00001 ??bf_RTC_init: + 302 302 ; line 24 : + 303 303 ; line 25 : if( !RTCEN ) // ビットが立っていたらリブート + 304 304 $DGL 0,3 + 305 305 00001 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1 + 306 306 00004 71F4 mov1 CY,[hl].7 ;[INF] 2, 1 + 307 307 00006 DC29 bc $?L0003 ;[INF] 2, 4 + 308 308 ; line 26 : { + 309 309 00008 ??bb00_RTC_init: + 310 310 ; line 27 : RTCEN = 1; // モジュールON + 311 311 $DGL 0,5 + 312 312 00008 7170F000 set1 !PER0.7 ;[INF] 4, 2 + 313 313 ; line 28 : + 314 314 ; line 29 : // RTC設定 + 315 315 ; line 30 : RTCC0 = 0b00001000; /* 動作停止、24時間制、32k出力「ま + 316 316 ; だなし」、定周期割り込みなし */ + 317 317 $DGL 0,8 + 318 318 0000C CE9D08 mov RTCC0,#08H ; 8 ;[INF] 3, 1 + 319 319 ; line 31 : RTCC1 = 0b11000000; /* アラーム割り込み有効＆動作開始 + 320 320 ; */ + 321 321 $DGL 0,9 + 322 322 0000F CE9EC0 mov RTCC1,#0C0H ; 192 ;[INF] 3, 1 + 323 323 ; line 32 : RTCC2 = 0b10000000; /* インターバル:32k/2^6=2ms、RTCD + 324 324 ; IV出力なし */ + 325 325 $DGL 0,10 + 326 326 00012 CE9F80 mov RTCC2,#080H ; 128 ;[INF] 3, 1 + 327 327 ; line 33 : + 328 328 ; line 34 : SEC = 0x00; + 329 329 $DGL 0,12 + 330 330 00015 F592FF clrb !SEC ;[INF] 3, 1 + 331 331 ; line 35 : MIN = 0x00; + 332 332 $DGL 0,13 + 333 333 00018 F593FF clrb !MIN ;[INF] 3, 1 + 334 334 ; line 36 : HOUR = 0x15; + 335 335 $DGL 0,14 + 336 336 0001B CE9415 mov HOUR,#015H ; 21 ;[INF] 3, 1 + 337 337 ; line 37 : DAY = 0x01; + 338 338 $DGL 0,15 + 339 339 0001E E596FF oneb !DAY ;[INF] 3, 1 + 340 340 ; line 38 : WEEK = 0x00; + 341 341 $DGL 0,16 + 342 342 00021 F595FF clrb !WEEK ;[INF] 3, 1 + 343 343 ; line 39 : MONTH = 0x11; + 344 344 $DGL 0,17 + 345 345 00024 CE9711 mov MONTH,#011H ; 17 ;[INF] 3, 1 + 346 346 ; line 40 : YEAR = 0x09; + 347 347 $DGL 0,18 + 348 348 00027 CE9809 mov YEAR,#09H ; 9 ;[INF] 3, 1 + 349 349 ; line 41 : + 350 350 ; line 42 : ALARMWW = 0x7F; + 351 351 $DGL 0,20 + 352 352 0002A CE9C7F mov ALARMWW,#07FH ; 127 ;[INF] 3, 1 + 353 353 ; line 43 : + 354 354 ; line 44 : vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT; + 355 355 $DGL 0,22 + 356 356 0002D R71000200 set1 !_vreg_ctr+2.0 ;[INF] 4, 2 + 357 357 00031 ??eb00_RTC_init: + 358 358 ; line 45 : } + 359 359 00031 ?L0003: + 360 360 ; line 46 : // 割り込み設定 + 361 361 ; line 47 : RTCIF = 0; + 362 362 $DGL 0,25 + 363 363 00031 711BE3 clr1 IF1H.1 ;[INF] 3, 2 + 364 364 ; line 48 : RTCIIF = 0; + 365 365 $DGL 0,26 + 366 366 00034 712BE3 clr1 IF1H.2 ;[INF] 3, 2 + 367 367 ; line 49 : RTCMK = 1; /* 割り込み(定周期)禁止 */ + 368 368 $DGL 0,27 + 369 369 00037 711AE7 set1 MK1H.1 ;[INF] 3, 2 + 370 370 ; line 50 : RTCIMK = 0; /* 割り込み(アラーム&インターバル + 371 371 ; )許可 */ + 372 372 $DGL 0,28 + 373 373 0003A 712BE7 clr1 MK1H.2 ;[INF] 3, 2 + 374 374 ; line 51 : + 375 375 ; line 52 : RTCE = 1; /* 動作開始 */ + 376 376 $DGL 0,30 + 377 377 0003D 717A9D set1 RTCC0.7 ;[INF] 3, 2 + 378 378 ; line 53 : + 379 379 ; line 54 : RWAIT = 1; + 380 380 $DGL 0,32 + 381 381 00040 710A9E set1 RTCC1.0 ;[INF] 3, 2 + 382 382 ; line 55 : while( !RWST ) + 383 383 $DGL 0,33 + 384 384 00043 ?L0005: + 385 385 00043 31929E02 bt RTCC1.1,$?L0006 ;[INF] 4, 5 + 386 386 ; line 56 : {; + 387 387 00047 ??bb01_RTC_init: + 388 388 00047 ??eb01_RTC_init: + 389 389 ; line 57 : } + 390 390 $DGL 0,35 + 391 391 00047 EFFA br $?L0005 ;[INF] 2, 3 + 392 392 00049 ?L0006: + 393 393 ; line 58 : RWAIT = 0; + 394 394 $DGL 0,36 + 395 395 00049 710B9E clr1 RTCC1.0 ;[INF] 3, 2 + 396 396 ; line 59 : + 397 397 ; line 60 : rtc_lock = 0; + 398 398 $DGL 0,38 + 399 399 0004C R710300 clr1 _rtc_lock ;[INF] 3, 2 + 400 400 ; line 61 : rtc_dirty = 0; + 401 401 $DGL 0,39 + 402 402 0004F R711300 clr1 _rtc_dirty ;[INF] 3, 2 + 403 403 ; line 62 : rtc_alarm_dirty = 0; + 404 404 $DGL 0,40 + 405 405 00052 R712300 clr1 _rtc_alarm_dirty ;[INF] 3, 2 + 406 406 ; line 63 : } + 407 407 $DGL 0,41 + 408 408 00055 ??ef_RTC_init: + 409 409 00055 C6 pop hl ;[INF] 1, 1 + 410 410 00056 D7 ret ;[INF] 1, 6 + 411 411 00057 ??ee_RTC_init: + 412 412 ; line 64 : + 413 413 ; line 65 : + 414 414 ; line 66 : + 415 415 ; line 67 : /* ======================================================== + 416 416 ; line 68 : RTC アラーム割り込み + 417 417 ; line 69 : 2^6/fXT（1.953125 ms） + 418 418 ; line 70 : ======================================================== */ + 419 419 ; line 71 : __interrupt void int_rtc( ) + 420 420 ; line 72 : { + 421 421 + 422 422 ----- @@BASE CSEG BASE + 423 423 00000 _int_rtc: + 424 424 $DGL 1,81 + 425 425 00000 C1 push ax ;[INF] 1, 1 + 426 426 00001 ??bf_int_rtc: + 427 427 ; line 73 : // 日付も指定日で + 428 428 ; line 74 : if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY ) + 429 429 ; line 75 : && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH ) + 430 430 ; line 76 : && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) ) + 431 431 $DGL 0,5 + 432 432 00001 R8F3A00 mov a,!_vreg_ctr+58 ;[INF] 3, 1 + 433 433 00004 4F96FF cmp a,!DAY ;[INF] 3, 1 + 434 434 00007 DF32 bnz $?L0013 ;[INF] 2, 4 + 435 435 00009 R8F3B00 mov a,!_vreg_ctr+59 ;[INF] 3, 1 + 436 436 0000C 4F97FF cmp a,!MONTH ;[INF] 3, 1 + 437 437 0000F DF2A bnz $?L0013 ;[INF] 2, 4 + 438 438 00011 R8F3C00 mov a,!_vreg_ctr+60 ;[INF] 3, 1 + 439 439 00014 4F98FF cmp a,!YEAR ;[INF] 3, 1 + 440 440 00017 DF22 bnz $?L0013 ;[INF] 2, 4 + 441 441 ; line 77 : { + 442 442 00019 ??bb00_int_rtc: + 443 443 ; line 78 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) = + 444 444 ; = 0 ) + 445 445 $DGL 0,7 + 446 446 00019 R8F1900 mov a,!_vreg_ctr+25 ;[INF] 3, 1 + 447 447 0001C 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 448 448 0001E D1 cmp0 a ;[INF] 1, 1 + 449 449 0001F DF1A bnz $?L0013 ;[INF] 2, 4 + 450 450 ; line 79 : { + 451 451 00021 ??bb01_int_rtc: + 452 452 ; line 80 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM; + 453 453 $DGL 0,9 + 454 454 00021 R71201100 set1 !_vreg_ctr+17.2 ;[INF] 4, 2 + 455 455 ; line 81 : IRQ0_ast; + 456 456 $DGL 0,10 + 457 457 00025 ??bb02_int_rtc: + 458 458 00025 716307 clr1 P7.6 ;[INF] 3, 2 + 459 459 00028 716B27 clr1 PM7.6 ;[INF] 3, 2 + 460 460 0002B ??eb02_int_rtc: + 461 461 ; line 82 : // マスクをしてあったら、電源を入れません + 462 462 ; line 83 : if(( system_status.pwr_state == BT_CHARGE ) || + 463 463 $DGL 0,12 + 464 464 0002B R40000006 cmp !_system_status,#06H ; 6 ;[INF] 4, 1 + 465 465 0002F DD06 bz $?L0015 ;[INF] 2, 4 + 466 466 ; line 84 : ( system_status.pwr_state == OFF )) + 467 467 $DGL 0,13 + 468 468 00031 R40000001 cmp !_system_status,#01H ; 1 ;[INF] 4, 1 + 469 469 00035 61F8 sknz ;[INF] 2, 1 + 470 470 00037 ?L0015: + 471 471 ; line 85 : { + 472 472 00037 ??bb03_int_rtc: + 473 473 ; line 86 : system_status.poweron_reason = RTC_ALARM; + 474 474 $DGL 0,15 + 475 475 00037 RCF010002 mov !_system_status+1,#02H ; 2 ;[INF] 4, 1 + 476 476 0003B ??eb03_int_rtc: + 477 477 ; line 87 : } + 478 478 0003B ?L0013: + 479 479 0003B ??eb01_int_rtc: + 480 480 ; line 88 : } + 481 481 0003B ??eb00_int_rtc: + 482 482 ; line 89 : } + 483 483 ; line 90 : } + 484 484 $DGL 0,19 + 485 485 0003B ??ef_int_rtc: + 486 486 0003B C0 pop ax ;[INF] 1, 1 + 487 487 0003C 61FC reti ;[INF] 2, 6 + 488 488 0003E ??ee_int_rtc: + 489 489 ; line 91 : + 490 490 ; line 92 : + 491 491 ; line 93 : + 492 492 ; line 94 : /* ======================================================== + 493 493 ; line 95 : RTC のリード + 494 494 ; line 96 : レジスタは、sec,min,hour,week,day,month,year の順 + 495 495 ; line 97 : ======================================================== */ + 496 496 ; line 98 : void rtc_buf_reflesh( ) + 497 497 ; line 99 : { + 498 498 + 499 499 ----- ROM_CODE CSEG BASE + 500 500 00057 _rtc_buf_reflesh: + 501 501 $DGL 1,103 + 502 502 00057 C7 push hl ;[INF] 1, 1 + 503 503 00058 ??bf_rtc_buf_reflesh: + 504 504 ; line 100 : if( rtc_lock == 0 ) + 505 505 $DGL 0,2 + 506 506 00058 R3102001E bt _rtc_lock,$?L0018 ;[INF] 4, 5 + 507 507 ; line 101 : { + 508 508 0005C ??bb00_rtc_buf_reflesh: + 509 509 ; line 102 : rtc_lock = 1; + 510 510 $DGL 0,4 + 511 511 0005C R710200 set1 _rtc_lock ;[INF] 3, 2 + 512 512 ; line 103 : RWAIT = 1; + 513 513 $DGL 0,5 + 514 514 0005F 710A9E set1 RTCC1.0 ;[INF] 3, 2 + 515 515 ; line 104 : while( !RWST ) + 516 516 $DGL 0,6 + 517 517 00062 ?L0020: + 518 518 00062 31929E02 bt RTCC1.1,$?L0021 ;[INF] 4, 5 + 519 519 ; line 105 : {; + 520 520 00066 ??bb01_rtc_buf_reflesh: + 521 521 00066 ??eb01_rtc_buf_reflesh: + 522 522 ; line 106 : } + 523 523 $DGL 0,8 + 524 524 00066 EFFA br $?L0020 ;[INF] 2, 3 + 525 525 00068 ?L0021: + 526 526 ; line 107 : + 527 527 ; line 108 : memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 ); + 528 528 $DGL 0,10 + 529 529 00068 R343000 movw de,#loww (_vreg_ctr+48) ;[INF] 3, 1 + 530 530 0006B 3692FF movw hl,#0FF92H ; -110 ;[INF] 3, 1 + 531 531 0006E 5207 mov c,#07H ; 7 ;[INF] 2, 1 + 532 532 00070 ?L0022: + 533 533 00070 8B mov a,[hl] ;[INF] 1, 1 + 534 534 00071 99 mov [de],a ;[INF] 1, 1 + 535 535 00072 A5 incw de ;[INF] 1, 1 + 536 536 00073 A7 incw hl ;[INF] 1, 1 + 537 537 00074 92 dec c ;[INF] 1, 1 + 538 538 00075 DFF9 bnz $?L0022 ;[INF] 2, 4 + 539 539 ; line 109 : RWAIT = 0; + 540 540 $DGL 0,11 + 541 541 00077 710B9E clr1 RTCC1.0 ;[INF] 3, 2 + 542 542 0007A ??eb00_rtc_buf_reflesh: + 543 543 ; line 110 : // renge_task_immed_add( tski_rtc_close ); + 544 544 ; line 111 : } + 545 545 0007A ?L0018: + 546 546 ; line 112 : } + 547 547 $DGL 0,14 + 548 548 0007A ??ef_rtc_buf_reflesh: + 549 549 0007A C6 pop hl ;[INF] 1, 1 + 550 550 0007B D7 ret ;[INF] 1, 6 + 551 551 0007C ??ee_rtc_buf_reflesh: + 552 552 ; line 113 : + 553 553 ; line 114 : + 554 554 ; line 115 : + 555 555 ; line 116 : /* ======================================================== + 556 556 ; line 117 : RTC のライト + 557 557 ; line 118 : set_rtc_close と対で使って下さい。 + 558 558 ; line 119 : こいつはバッファにコピーするだけで、 + 559 559 ; line 120 : 実際にRTCにセットするのはset_rtc_close()です。 + 560 560 ; line 121 : ======================================================== */ + 561 561 ; line 122 : void set_rtc( u8 adrs, u8 data ) + 562 562 ; line 123 : { + 563 563 0007C _set_rtc: + 564 564 $DGL 1,117 + 565 565 0007C C7 push hl ;[INF] 1, 1 + 566 566 0007D 8806 mov a,[sp+6] ;[INF] 2, 1 + 567 567 0007F 16 movw hl,ax ;[INF] 1, 1 + 568 568 00080 ??bf_set_rtc: + 569 569 ; line 124 : if( rtc_dirty == 0 ) + 570 570 $DGL 0,2 + 571 571 00080 R31120015 bt _rtc_dirty,$?L0026 ;[INF] 4, 5 + 572 572 ; line 125 : { + 573 573 00084 ??bb00_set_rtc: + 574 574 ; line 126 : rtc_dirty = 1; + 575 575 $DGL 0,4 + 576 576 00084 R711200 set1 _rtc_dirty ;[INF] 3, 2 + 577 577 ; line 127 : memcpy( rtc_work, &SEC, 7 ); + 578 578 $DGL 0,5 + 579 579 00087 C7 push hl ;[INF] 1, 1 + 580 580 00088 R340000 movw de,#loww (_rtc_work) ;[INF] 3, 1 + 581 581 0008B 3092FF movw ax,#0FF92H ; -110 ;[INF] 3, 1 + 582 582 0008E 16 movw hl,ax ;[INF] 1, 1 + 583 583 0008F 5207 mov c,#07H ; 7 ;[INF] 2, 1 + 584 584 00091 ?L0028: + 585 585 00091 8B mov a,[hl] ;[INF] 1, 1 + 586 586 00092 99 mov [de],a ;[INF] 1, 1 + 587 587 00093 A5 incw de ;[INF] 1, 1 + 588 588 00094 A7 incw hl ;[INF] 1, 1 + 589 589 00095 92 dec c ;[INF] 1, 1 + 590 590 00096 DFF9 bnz $?L0028 ;[INF] 2, 4 + 591 591 00098 C6 pop hl ;[INF] 1, 1 + 592 592 00099 ??eb00_set_rtc: + 593 593 ; line 128 : // renge_task_immed_add( tski_rtc_close ); // I2C終了時に行う + 594 594 ; line 129 : } + 595 595 00099 ?L0026: + 596 596 ; line 130 : rtc_work[adrs] = data; + 597 597 $DGL 0,8 + 598 598 00099 66 mov a,l ;[INF] 1, 1 + 599 599 0009A 73 mov b,a ;[INF] 1, 1 + 600 600 0009B 67 mov a,h ;[INF] 1, 1 + 601 601 0009C R180000 mov _rtc_work[b],a ;[INF] 3, 1 + 602 602 ; line 131 : } + 603 603 $DGL 0,9 + 604 604 0009F ??ef_set_rtc: + 605 605 0009F C6 pop hl ;[INF] 1, 1 + 606 606 000A0 D7 ret ;[INF] 1, 6 + 607 607 000A1 ??ee_set_rtc: + 608 608 ; line 132 : + 609 609 ; line 133 : + 610 610 ; line 134 : + 611 611 ; line 135 : /* ======================================================== + 612 612 ; line 136 : 必要ならば、RTCレジスタの更新 + 613 613 ; line 137 : ======================================================== */ + 614 614 ; line 138 : // task_status_immed tski_rtc_close(){ + 615 615 ; line 139 : void rtc_unlock( ) + 616 616 ; line 140 : { + 617 617 000A1 _rtc_unlock: + 618 618 $DGL 1,129 + 619 619 000A1 C7 push hl ;[INF] 1, 1 + 620 620 000A2 ??bf_rtc_unlock: + 621 621 ; line 141 : // リードロック + 622 622 ; line 142 : // if( rtc_lock != 0 ){ + 623 623 ; line 143 : rtc_lock = 0; + 624 624 $DGL 0,4 + 625 625 000A2 R710300 clr1 _rtc_lock ;[INF] 3, 2 + 626 626 ; line 144 : // } + 627 627 ; line 145 : + 628 628 ; line 146 : // ライトロック + 629 629 ; line 147 : if( rtc_dirty != 0 ) + 630 630 $DGL 0,8 + 631 631 000A5 R3114001E bf _rtc_dirty,$?L0032 ;[INF] 4, 5 + 632 632 ; line 148 : { + 633 633 000A9 ??bb00_rtc_unlock: + 634 634 ; line 149 : rtc_dirty = 0; + 635 635 $DGL 0,10 + 636 636 000A9 R711300 clr1 _rtc_dirty ;[INF] 3, 2 + 637 637 ; line 150 : RWAIT = 1; + 638 638 $DGL 0,11 + 639 639 000AC 710A9E set1 RTCC1.0 ;[INF] 3, 2 + 640 640 ; line 151 : while( !RWST ) + 641 641 $DGL 0,12 + 642 642 000AF ?L0034: + 643 643 000AF 31929E02 bt RTCC1.1,$?L0035 ;[INF] 4, 5 + 644 644 ; line 152 : {; + 645 645 000B3 ??bb01_rtc_unlock: + 646 646 000B3 ??eb01_rtc_unlock: + 647 647 ; line 153 : } + 648 648 $DGL 0,14 + 649 649 000B3 EFFA br $?L0034 ;[INF] 2, 3 + 650 650 000B5 ?L0035: + 651 651 ; line 154 : memcpy( &SEC, rtc_work, 7 ); + 652 652 $DGL 0,15 + 653 653 000B5 3492FF movw de,#0FF92H ; -110 ;[INF] 3, 1 + 654 654 000B8 R360000 movw hl,#loww (_rtc_work) ;[INF] 3, 1 + 655 655 000BB 5207 mov c,#07H ; 7 ;[INF] 2, 1 + 656 656 000BD ?L0036: + 657 657 000BD 8B mov a,[hl] ;[INF] 1, 1 + 658 658 000BE 99 mov [de],a ;[INF] 1, 1 + 659 659 000BF A5 incw de ;[INF] 1, 1 + 660 660 000C0 A7 incw hl ;[INF] 1, 1 + 661 661 000C1 92 dec c ;[INF] 1, 1 + 662 662 000C2 DFF9 bnz $?L0036 ;[INF] 2, 4 + 663 663 ; line 155 : RWAIT = 0; + 664 664 $DGL 0,16 + 665 665 000C4 710B9E clr1 RTCC1.0 ;[INF] 3, 2 + 666 666 000C7 ??eb00_rtc_unlock: + 667 667 ; line 156 : } + 668 668 000C7 ?L0032: + 669 669 ; line 157 : + 670 670 ; line 158 : // アラームセット + 671 671 ; line 159 : if( rtc_alarm_dirty ) + 672 672 $DGL 0,20 + 673 673 000C7 R31240013 bf _rtc_alarm_dirty,$?L0038 ;[INF] 4, 5 + 674 674 ; line 160 : { + 675 675 000CB ??bb02_rtc_unlock: + 676 676 ; line 161 : WALE = 0; + 677 677 $DGL 0,22 + 678 678 000CB 717B9E clr1 RTCC1.7 ;[INF] 3, 2 + 679 679 ; line 162 : ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN]; + 680 680 $DGL 0,23 + 681 681 000CE R8F3800 mov a,!_vreg_ctr+56 ;[INF] 3, 1 + 682 682 000D1 9E9A mov ALARMWM,a ;[INF] 2, 1 + 683 683 ; line 163 : ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR]; + 684 684 $DGL 0,24 + 685 685 000D3 R8F3900 mov a,!_vreg_ctr+57 ;[INF] 3, 1 + 686 686 000D6 9E9B mov ALARMWH,a ;[INF] 2, 1 + 687 687 ; line 164 : rtc_dirty = 0; + 688 688 $DGL 0,25 + 689 689 000D8 R711300 clr1 _rtc_dirty ;[INF] 3, 2 + 690 690 ; line 165 : WALE = 1; + 691 691 $DGL 0,26 + 692 692 000DB 717A9E set1 RTCC1.7 ;[INF] 3, 2 + 693 693 000DE ??eb02_rtc_unlock: + 694 694 ; line 166 : } + 695 695 000DE ?L0038: + 696 696 ; line 167 : } + 697 697 $DGL 0,28 + 698 698 000DE ??ef_rtc_unlock: + 699 699 000DE C6 pop hl ;[INF] 1, 1 + 700 700 000DF D7 ret ;[INF] 1, 6 + 701 701 000E0 ??ee_rtc_unlock: + 702 702 ; line 168 : + 703 703 ; line 169 : + 704 704 ; line 170 : + 705 705 ; line 171 : + 706 706 ; line 172 : + 707 707 ; line 173 : /* ======================================================== + 708 708 ; line 174 : RTC システムチックタイマ割り込みベクタ + 709 709 ; line 175 : 2^6/fXT（1.953125 ms） + 710 710 ; line 176 : ======================================================== */ + 711 711 ; line 177 : __interrupt void int_rtc_int( ) + 712 712 ; line 178 : { + 713 713 + 714 714 ----- @@BASE CSEG BASE + 715 715 0003E _int_rtc_int: + 716 716 $DGL 1,147 + 717 717 0003E ??bf_int_rtc_int: + 718 718 ; line 179 : renge_flg_interval = 1; + 719 719 $DGL 0,2 + 720 720 0003E R710200 set1 _renge_flg_interval ;[INF] 3, 2 + 721 721 ; line 180 : } + 722 722 $DGL 0,3 + 723 723 00041 ??ef_int_rtc_int: + 724 724 00041 61FC reti ;[INF] 2, 6 + 725 725 00043 ??ee_int_rtc_int: + 726 726 + 727 727 ----- @@CODEL CSEG + 728 728 END + 729 729 + 730 730 + 731 731 ; *** Code Information *** + 732 732 ; + 733 733 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c + 734 734 ; + 735 735 ; $FUNC RTC_init(23) + 736 736 ; void=(void) + 737 737 ; CODE SIZE= 87 bytes, CLOCK_SIZE= 57 clocks, STACK_SIZE= 2 bytes + 738 738 ; + 739 739 ; $FUNC int_rtc(72) + 740 740 ; void=(void) + 741 741 ; CODE SIZE= 62 bytes, CLOCK_SIZE= 47 clocks, STACK_SIZE= 2 bytes + 742 742 ; + 743 743 ; $FUNC rtc_buf_reflesh(99) + 744 744 ; void=(void) + 745 745 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 2 bytes + 746 746 ; + 747 747 ; $FUNC set_rtc(123) + 748 748 ; void=(unsigned char adrs:x, unsigned char data:[sp+6]) + 749 749 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 4 bytes + 750 750 ; + 751 751 ; $FUNC rtc_unlock(140) + 752 752 ; void=(void) + 753 753 ; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 2 bytes + 754 754 ; + 755 755 ; $FUNC int_rtc_int(178) + 756 756 ; void=(void) + 757 757 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes + 758 758 + 759 759 ; Target chip : uPD79F0104 + 760 760 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.3 @@BITS +00000 00030H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00008H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 000E0H ROM_CODE +00000 00043H @@BASE +00000 00000H @@CODEL + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/rtc.rel b/branches/0.10(X3)/rtc.rel new file mode 100644 index 0000000..aa78c87 Binary files /dev/null and b/branches/0.10(X3)/rtc.rel differ diff --git a/branches/0.10(X3)/self_flash.c b/branches/0.10(X3)/self_flash.c new file mode 100644 index 0000000..3407eb5 --- /dev/null +++ b/branches/0.10(X3)/self_flash.c @@ -0,0 +1,402 @@ +/* ======================================================== + 自己アップデータ + ======================================================== */ +#pragma SFR +#pragma di +#pragma ei +#pragma nop +#pragma stop +#pragma halt + + +#include "incs_loader.h" + +#include +#include "fsl_user.h" +#include "i2c_ctr.h" + + + +// ======================================================== +const u8 fsl_fx_MHz_u08 = 8; +const u8 fsl_low_voltage_u08 = 1; + + +// 自己フラッシュパラメータ +#define SAM_BLOCK_SIZE 1024 +#define SELF_UPDATE_BUFF_SIZE 256 +#define SELF_UPDATE_SPLIT_WRITE_NUM ( SAM_BLOCK_SIZE / SELF_UPDATE_BUFF_SIZE ) +#define SAM_WORD_SIZE 4 + +// ↓ブロック番号（1ブロック＝1kB） +#define INACTIVE_BOOTSECT_TOP 4 +#define FIRM_TOP 8 +#define FIRM_SIZE 12 +#define UPDATE_BLOCK_LAST ( FIRM_TOP + FIRM_SIZE - 1 ) + + +#ifdef _MCU_BSR_ + + +#define ACKD ACKD1 +#define ACKE ACKE1 +#define COI COI1 +#define IICAEN IICA1EN +#define IICAPR0 IICAPR10 +#define IICRSV IICRSV1 +#define IICA IICA1 +#define IICAIF IICAIF1 +#define IICAMK IICAMK1 +#define IICAPR1 IICAPR11 +#define IICCTL0 IICCTL01 +#define IICE IICE1 +#define IICF IICF1 +#define IICS IICS1 +#define IICWH IICWH1 +#define IICWL IICWL1 +#define LREL LREL1 +#define SPD SPD1 +#define SPIE SPIE1 +#define STCEN STCEN1 +#define STD STD1 +#define SVA SVA1 +#define WREL WREL1 +#define WTIM WTIM1 +#endif + + + +// ======================================================== +static void FSL_Open( void ); +static void FSL_Close( void ); +err firm_restore( ); + +static err my_FSL_Init(); +static err firm_duplicate( __far u8 * p_rom, u8 block_dest ); + + + +// ======================================================== +extern u16 pool[]; + + +// 0.D以降 新アップデータ向け +#define N_MGC_L 0x1FF6 +#define N_MGC_T 0x4FF6 + + + +/* ======================================================== + I2Cで受信して、 + 書き込み、 + チェックOK　→　新ファームに切り替えて再起動 + 　　　　NG　→　旧（現）ファームに戻して再起動 + （この関数からは戻りません） + ======================================================== */ +err firm_update( ) +{ + u8 target_block; + u8 split_write_count; // ブロックへちまちま書き込むカウンタ + + // 書き替え前準備 ///////////////////////////////////// + my_FSL_Init(); + + /* ファームのバックアップ + 0x2000 - 0x4FFF を + 0x5000 - 0x7FFF (ブロック 20 - 31) にコピー + */ + firm_duplicate( ( __far u8 * ) 0x2000, + ( 0x5000 / 0x0400 ) ); + + // 全ブロック削除 ///////////////////////////////////// + // 電源断を判定するため、最初に全クラスタ消去する + //（新ファームが書かれるところに残ってる、以前のファームのフッタを消したい） + for( target_block = INACTIVE_BOOTSECT_TOP; + target_block <= UPDATE_BLOCK_LAST; + target_block += 1 ) + { + FSL_Erase( target_block ); + } + + // 書き替え /////////////////////////////////////////// + // ●ストップコンディションが来るまで続ける + // ●終わったら、スタートアップルーチンに飛ぶ + for( target_block = INACTIVE_BOOTSECT_TOP; + target_block <= UPDATE_BLOCK_LAST; + target_block += 1 ) + { + // 新ファーム領域削除 + FSL_Erase( target_block ); + + // 分割書き込み + for( split_write_count = 0; + ( ( split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM ) + && ( !SPD ) ); + split_write_count += 1 ) + { + u8* p_buffer = pool; + u8 buffer_fill = 0; + + WDT_Restart( ); + + // I2Cから書き込みデータをバッファにためる + do + { + while( !IICAIF && !SPD ){;} + IICAIF = 0; + *p_buffer = IICA; + WREL = 1; + p_buffer += 1; + buffer_fill += 1; + } + while( ( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE ) && !SPD ); + + // 書き込み + // 最後だと、ゴミをパディングするが別にかまわない + if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOCK_SIZE + + + split_write_count * + SELF_UPDATE_BUFF_SIZE ), + ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE / SAM_WORD_SIZE ) ) + + != FSL_OK ) + { + // 書き込み後のチェックエラー + // リブートののち、リストア +// FSL_ForceReset(); // リセット + FSL_SwapBootCluster( ); +// FSL_Close( ); + return ( ERR_ERR ); + } + + } + // 1ブロック書き込み完了。内部ベリファイを行う + if( FSL_IVerify( target_block ) != FSL_OK ){ + // todo 再度消去→書き込み ベリファイを繰り返すだけじゃダメでした... + NOP(); + } + + if( SPD ) + { + break; + } + } + + LREL = 1; + + // 書き込んだファームのチェック // + { + u8 i; + u8 comp = 0; + + // ローダーのマジックと、本文の末尾のマジックは同じか確認 + for( i = 0; i < sizeof( __TIME__ ); i++ ) + { + comp += ( *( u8 * ) ( N_MGC_L + i ) == *( u8 * ) ( N_MGC_T + i ) ) ? 0 : 1; + } + if( comp == 0 ) + { + FSL_InvertBootFlag( ); + FSL_SwapBootCluster( ); // リセットせずに頭から。FSL_Closeは不要 + // FSL_ForceReset(); // リセット + // FSL_SwapActiveBootCluster(); // ←スワップされてしまうので、続けられず暴走！ + // 戻ってこない // + } + else + { + // データエラー + // リブートののち、リストア +// FSL_ForceReset(); // リセット + FSL_SwapBootCluster( ); +// FSL_Close( ); + // 戻ってこない // + } + } +} + + + + +/* ======================================================== + 　■ファームをバックアップ領域からリストアします。 + 　チェック後、最後の最後でブートスワップするので、 +　ここではブートスワップは不要です。 + + ======================================================== */ +err firm_restore( ) +{ + my_FSL_Init(); + + /* ファームのリストア + 0x4800 - 0x7FFF (ブロック 18 - 27) から + 0x2000 - 0x47FF (ブロック 8 - 17) へコピー + */ + firm_duplicate( ( __far u8 * ) 0x5000, + FIRM_TOP ); + + // todo + // 　リストア失敗したら、LEDちかちかとかさせて、サービス送りにしてもらう + + // リブート + // スワップは不要です！ + FSL_SwapBootCluster(); +// FSL_ForceReset( ); + return ( ERR_SUCCESS ); +} + + + + +// ======================================================== +static void FSL_Open( void ) +{ + /* save the configuration of the interrupt controller and set */ +#ifdef FSL_INT_BACKUP + fsl_MK0L_bak_u08 = MK0L; /* if (interrupt backup required) */ + fsl_MK0H_bak_u08 = MK0H; /* { */ + fsl_MK1L_bak_u08 = MK1L; /* */ + fsl_MK1H_bak_u08 = MK1H; /* save interrupt controller */ + fsl_MK2L_bak_u08 = MK2L; /* configuration */ + fsl_MK2H_bak_u08 = MK2H; /* */ + MK0L = FSL_MK0L_MASK; /* */ + MK0H = FSL_MK0H_MASK; /* */ + MK1L = FSL_MK1L_MASK; /* prepare interrupt controller */ + MK1H = FSL_MK1H_MASK; /* for selfprogramming */ + MK2L = FSL_MK2L_MASK; /* */ + MK2H = FSL_MK2H_MASK; /* } */ +#endif + + // 何か前準備？ + // todo DMAを止める + while( DST1 ){;} + DEN1 = 0; + + MK0 = 0xFFFF; + MK1 = 0xFFFF; + MK2 = 0xFFFF; + + FSL_FLMD0_HIGH; // フラッシュ書き替え許可 +} + + + +/*----------------------------------------------------------------------------------------------*/ +/* leave the "user room" and restore previous conditions */ +/*----------------------------------------------------------------------------------------------*/ +static void FSL_Close( void ) +{ + // 何か後始末？ + + FSL_FLMD0_LOW; // フラッシュライトプロテクト + +#ifdef FSL_INT_BACKUP + MK0L = fsl_MK0L_bak_u08; /* do{ */ + MK0H = fsl_MK0H_bak_u08; /* restore interrupt controller */ + MK1L = fsl_MK1L_bak_u08; /* configuration */ + MK1H = fsl_MK1H_bak_u08; /* */ + MK2L = fsl_MK2L_bak_u08; /* */ + MK2H = fsl_MK2H_bak_u08; /* } */ +#endif +} + + + +/* ======================================================== +　マイコン内でファームをコピーします。 + __far u8 * p_rom コピー元の先頭アドレス + block_dest コピー先の先頭ブロック + + コピー先に書けるようにmy_FSL_Initをあらかじめ実行する必要があります。 + ======================================================== */ +static err firm_duplicate( __far u8 * p_rom, + u8 block_dest ) +{ + u8 target_block; + u8 split_write_count; // ブロックへちまちま書き込むカウンタ + + // 書き込み先ブロックの数だけ繰り返す + for( target_block = block_dest; + target_block < block_dest + FIRM_SIZE; + target_block += 1 ) + { + WDT_Restart( ); + // ブロック消去 + while( FSL_BlankCheck( target_block ) != FSL_OK ) + { + FSL_Erase( target_block ); + } + + // 分割書き込み分繰り返す + for( split_write_count = 0; + split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM; + split_write_count += 1 ) + { + u8 buffer_fill; + u8* p_buff; + + // 書き込みデータをバッファにためる + buffer_fill = 0; + p_buff = pool; + do + { + *p_buff = *p_rom; + p_rom += 1; + p_buff += 1; + buffer_fill +=1; + } + while( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE ); + + // 書き込み + if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOCK_SIZE + + + split_write_count * + SELF_UPDATE_BUFF_SIZE ), + ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE / SAM_WORD_SIZE ) ) + != FSL_OK ) + { + FSL_Close( ); + return ( ERR_ERR ); + } + } + + // 1ブロック書き込み完了。内部電圧チェックを行う + while( FSL_IVerify( target_block ) != FSL_OK ){ + // todo + ; + } + } + return( ERR_SUCCESS ); + +} + + + +/* ======================================================== + ======================================================== */ +static err my_FSL_Init() +{ + RTCE = 0; + + // 書き替え前準備 // + DI( ); + FSL_Open( ); // 割り込み禁止など + + FSL_Init( pool ); // ライブラリ初期化。割り込み中断考慮せず + FSL_ModeCheck( ); // ライトプロテクトチェック。失敗することを考慮せず + + return( ERR_SUCCESS ); +} + + +task_status_immed tski_mcu_reset() +{ + // 普通に再起動 + my_FSL_Init(); + FSL_Close( ); +// FSL_SwapBootCluster(); + FSL_ForceReset(); // リセット + + // 保険？ // + WDTE = 0xAA; // WDTで再起動（テスト向け） + return( ERR_SUCCESS ); // no reach +} diff --git a/branches/0.10(X3)/self_flash.h b/branches/0.10(X3)/self_flash.h new file mode 100644 index 0000000..768565e --- /dev/null +++ b/branches/0.10(X3)/self_flash.h @@ -0,0 +1,9 @@ +#ifndef _self_flash_h_ +#define _self_flash_h_ + + +void firm_update(); + + +#endif + diff --git a/branches/0.10(X3)/self_flash.prn b/branches/0.10(X3)/self_flash.prn new file mode 100644 index 0000000..f01000c --- /dev/null +++ b/branches/0.10(X3)/self_flash.prn @@ -0,0 +1,1353 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\self_flash.asm +Para-file: +In-file: inter_asm\self_flash.asm +Obj-file: self_flash.rel +Prn-file: self_flash.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no self_flash.c + 6 6 ; In-file : self_flash.c + 7 7 ; Asm-file : inter_asm\self_flash.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0B4H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, self_flash.c + 18 18 $DGS MOD_NAM, self_flash, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 019H + 37 37 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 40 40 $DGS AUX_EOS, 013H, 01H + 41 41 $DGS LAB_SYM, bs_F0064, U, U, 00H, 06H, 00H, 00H + 42 42 $DGS LAB_SYM, es_F0064, U, U, 00H, 06H, 00H, 00H + 43 43 $DGS LAB_SYM, bs_S0062, U, U, 00H, 06H, 00H, 00H + 44 44 $DGS LAB_SYM, es_S0062, U, U, 00H, 06H, 00H, 00H + 45 45 $DGS LAB_SYM, bs_F0063, U, U, 00H, 06H, 00H, 00H + 46 46 $DGS LAB_SYM, es_F0063, U, U, 00H, 06H, 00H, 00H + 47 47 $DGS LAB_SYM, bs_F0061, U, U, 00H, 06H, 00H, 00H + 48 48 $DGS LAB_SYM, es_F0061, U, U, 00H, 06H, 00H, 00H + 49 49 $DGS LAB_SYM, bs_S0060, U, U, 00H, 06H, 00H, 00H + 50 50 $DGS LAB_SYM, es_S0060, U, U, 00H, 06H, 00H, 00H + 51 51 $DGS GLV_SYM, _firm_update, U, U, 0CH, 026H, 01H, 02H + 52 52 $DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H + 53 53 $DGS BEG_FUN, ??bf_firm_update, U, U, 00H, 065H, 01H, 00H + 54 54 $DGS AUX_BEG, 061H, 06H, 029H + 55 55 $DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H + 56 56 $DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H + 57 57 $DGS BEG_BLK, ??bb00_firm_update, U, U, 00H, 064H, 01H, 00H + 58 58 $DGS AUX_BEG, 015H, 00H, 02DH + 59 59 $DGS END_BLK, ??eb00_firm_update, U, U, 00H, 064H, 01H, 00H + 60 60 $DGS AUX_END, 017H + 61 61 $DGS BEG_BLK, ??bb01_firm_update, U, U, 00H, 064H, 01H, 00H + 62 62 $DGS AUX_BEG, 01FH, 00H, 02FH + 63 63 $DGS BEG_BLK, ??bb02_firm_update, U, U, 00H, 064H, 01H, 00H + 64 64 $DGS AUX_BEG, 028H, 00H, 035H + 65 65 $DGS AUT_VAR, _p_buffer, 02H, 0FFFFH, 0CH, 01H, 01H, 01H + 66 66 $DGS AUX_STR, 00H, 029H, 02H, 00H, 00H, 00H, 00H, 01H + 67 67 $DGS AUT_VAR, _buffer_fill, 01H, 0FFFFH, 0CH, 01H, 01H, 00H + 68 68 $DGS AUX_STR, 00H, 02AH, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BEG_BLK, ??bb03_firm_update, U, U, 00H, 064H, 01H, 00H + 70 70 $DGS AUX_BEG, 030H, 00H, 037H + 71 71 $DGS BEG_BLK, ??bb04_firm_update, U, U, 00H, 064H, 01H, 00H + 72 72 $DGS AUX_BEG, 031H, 00H, 03DH + 73 73 $DGS END_BLK, ??eb04_firm_update, U, U, 00H, 064H, 01H, 00H + 74 74 $DGS AUX_END, 031H + 75 75 $DGS END_BLK, ??eb03_firm_update, U, U, 00H, 064H, 01H, 00H + 76 76 $DGS AUX_END, 037H + 77 77 $DGS BEG_BLK, ??bb05_firm_update, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_BEG, 043H, 00H, 043H + 79 79 $DGS END_BLK, ??eb05_firm_update, U, U, 00H, 064H, 01H, 00H + 80 80 $DGS AUX_END, 04AH + 81 81 $DGS END_BLK, ??eb02_firm_update, U, U, 00H, 064H, 01H, 00H + 82 82 $DGS AUX_END, 04CH + 83 83 $DGS BEG_BLK, ??bb06_firm_update, U, U, 00H, 064H, 01H, 00H + 84 84 $DGS AUX_BEG, 04EH, 00H, 047H + 85 85 $DGS END_BLK, ??eb06_firm_update, U, U, 00H, 064H, 01H, 00H + 86 86 $DGS AUX_END, 051H + 87 87 $DGS BEG_BLK, ??bb07_firm_update, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_BEG, 054H, 00H, 04DH + 89 89 $DGS END_BLK, ??eb07_firm_update, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_END, 056H + 91 91 $DGS END_BLK, ??eb01_firm_update, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_END, 057H + 93 93 $DGS BEG_BLK, ??bb08_firm_update, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_BEG, 05CH, 00H, 053H + 95 95 $DGS AUT_VAR, _i, 03H, 0FFFFH, 0CH, 01H, 01H, 00H + 96 96 $DGS AUX_STR, 00H, 05DH, 01H, 00H, 00H, 00H, 00H, 00H + 97 97 $DGS AUT_VAR, _comp, 02H, 0FFFFH, 0CH, 01H, 01H, 00H + 98 98 $DGS AUX_STR, 00H, 05EH, 01H, 00H, 00H, 00H, 00H, 00H + 99 99 $DGS BEG_BLK, ??bb09_firm_update, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_BEG, 062H, 00H, 057H + 101 101 $DGS END_BLK, ??eb09_firm_update, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_END, 064H + 103 103 $DGS BEG_BLK, ??bb0A_firm_update, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_BEG, 066H, 00H, 05BH + 105 105 $DGS END_BLK, ??eb0A_firm_update, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_END, 06CH + 107 107 $DGS BEG_BLK, ??bb0B_firm_update, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_BEG, 06EH, 00H, 00H + 109 109 $DGS END_BLK, ??eb0B_firm_update, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_END, 075H + 111 111 $DGS END_BLK, ??eb08_firm_update, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_END, 076H + 113 113 $DGS END_FUN, ??ef_firm_update, U, U, 00H, 065H, 01H, 00H + 114 114 $DGS AUX_END, 077H + 115 115 $DGS GLV_SYM, _firm_restore, U, U, 0CH, 026H, 01H, 02H + 116 116 $DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H + 117 117 $DGS BEG_FUN, ??bf_firm_restore, U, U, 00H, 065H, 01H, 00H + 118 118 $DGS AUX_BEG, 0E3H, 00H, 069H + 119 119 $DGS END_FUN, ??ef_firm_restore, U, U, 00H, 065H, 01H, 00H + 120 120 $DGS AUX_END, 013H + 121 121 $DGS STA_SYM, _FSL_Open, U, U, 01H, 03H, 01H, 02H + 122 122 $DGS AUX_FUN, 00H, U, U, 077H, 00H, 00H + 123 123 $DGS BEG_FUN, ??bf_FSL_Open, U, U, 00H, 065H, 01H, 00H + 124 124 $DGS AUX_BEG, 0FCH, 00H, 06DH + 125 125 $DGS BEG_BLK, ??bb00_FSL_Open, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_BEG, 014H, 00H, 071H + 127 127 $DGS END_BLK, ??eb00_FSL_Open, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_END, 014H + 129 129 $DGS BEG_BLK, ??bb01_FSL_Open, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_BEG, 01BH, 00H, 00H + 131 131 $DGS END_BLK, ??eb01_FSL_Open, U, U, 00H, 064H, 01H, 00H + 132 132 $DGS AUX_END, 01BH + 133 133 $DGS END_FUN, ??ef_FSL_Open, U, U, 00H, 065H, 01H, 00H + 134 134 $DGS AUX_END, 01CH + 135 135 $DGS STA_SYM, _FSL_Close, U, U, 01H, 03H, 01H, 02H + 136 136 $DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H + 137 137 $DGS BEG_FUN, ??bf_FSL_Close, U, U, 00H, 065H, 01H, 00H + 138 138 $DGS AUX_BEG, 011FH, 00H, 07BH + 139 139 $DGS BEG_BLK, ??bb00_FSL_Close, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_BEG, 04H, 00H, 00H + 141 141 $DGS END_BLK, ??eb00_FSL_Close, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_END, 04H + 143 143 $DGS END_FUN, ??ef_FSL_Close, U, U, 00H, 065H, 01H, 00H + 144 144 $DGS AUX_END, 0EH + 145 145 $DGS STA_SYM, _firm_duplicate, U, U, 0CH, 03H, 01H, 02H + 146 146 $DGS AUX_FUN, 00H, U, U, 0A8H, 00H, 00H + 147 147 $DGS BEG_FUN, ??bf_firm_duplicate, U, U, 00H, 065H, 01H, 00H + 148 148 $DGS AUX_BEG, 0139H, 0AH, 08AH + 149 149 $DGS FUN_ARG, _p_rom, 06H, 0FFFFH, 0CH, 09H, 01H, 01H + 150 150 $DGS AUX_STR, 00H, 00H, 04H, 00H, 00H, 00H, 00H, 02H + 151 151 $DGS FUN_ARG, _block_dest, 010H, 0FFFFH, 0CH, 09H, 00H, 00H + 152 152 $DGS AUT_VAR, _target_block, 05H, 0FFFFH, 0CH, 01H, 00H, 00H + 153 153 $DGS AUT_VAR, _split_write_count, 04H, 0FFFFH, 0CH, 01H, 00H, 00H + 154 154 $DGS BEG_BLK, ??bb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_BEG, 09H, 00H, 08CH + 156 156 $DGS BEG_BLK, ??bb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_BEG, 0DH, 00H, 090H + 158 158 $DGS END_BLK, ??eb01_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 159 159 $DGS AUX_END, 0FH + 160 160 $DGS BEG_BLK, ??bb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 161 161 $DGS AUX_BEG, 015H, 00H, 096H + 162 162 $DGS AUT_VAR, _buffer_fill, 03H, 0FFFFH, 0CH, 01H, 01H, 00H + 163 163 $DGS AUX_STR, 00H, 016H, 01H, 00H, 00H, 00H, 00H, 00H + 164 164 $DGS AUT_VAR, _p_buff, 00H, 0FFFFH, 0CH, 01H, 01H, 01H + 165 165 $DGS AUX_STR, 00H, 017H, 02H, 00H, 00H, 00H, 00H, 01H + 166 166 $DGS BEG_BLK, ??bb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 167 167 $DGS AUX_BEG, 01DH, 00H, 09AH + 168 168 $DGS END_BLK, ??eb03_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 169 169 $DGS AUX_END, 022H + 170 170 $DGS BEG_BLK, ??bb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 171 171 $DGS AUX_BEG, 02CH, 00H, 0A0H + 172 172 $DGS END_BLK, ??eb04_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 173 173 $DGS AUX_END, 02FH + 174 174 $DGS END_BLK, ??eb02_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_END, 030H + 176 176 $DGS BEG_BLK, ??bb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_BEG, 033H, 00H, 00H + 178 178 $DGS END_BLK, ??eb05_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_END, 036H + 180 180 $DGS END_BLK, ??eb00_firm_duplicate, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_END, 037H + 182 182 $DGS END_FUN, ??ef_firm_duplicate, U, U, 00H, 065H, 01H, 00H + 183 183 $DGS AUX_END, 03AH + 184 184 $DGS STA_SYM, _my_FSL_Init, U, U, 0CH, 03H, 01H, 02H + 185 185 $DGS AUX_FUN, 00H, U, U, 0AEH, 00H, 00H + 186 186 $DGS BEG_FUN, ??bf_my_FSL_Init, U, U, 00H, 065H, 01H, 00H + 187 187 $DGS AUX_BEG, 0179H, 00H, 0AEH + 188 188 $DGS END_FUN, ??ef_my_FSL_Init, U, U, 00H, 065H, 01H, 00H + 189 189 $DGS AUX_END, 0CH + 190 190 $DGS GLV_SYM, _tski_mcu_reset, U, U, 0AH, 026H, 01H, 02H + 191 191 $DGS AUX_FUN, 013H, U, U, 0B4H, 00H, 00H + 192 192 $DGS BEG_FUN, ??bf_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H + 193 193 $DGS AUX_BEG, 0188H, 00H, 0B4H + 194 194 $DGS END_FUN, ??ef_tski_mcu_reset, U, U, 00H, 065H, 01H, 00H + 195 195 $DGS AUX_END, 0BH + 196 196 $DGS GLV_SYM, _fsl_fx_MHz_u08, U, U, 0500CH, 026H, 00H, 00H + 197 197 $DGS GLV_SYM, _fsl_low_voltage_u08, U, U, 0500CH, 026H, 00H, 00H + 198 198 $DGS GLV_SYM, _FSL_Erase, U, U, 0CH, 02H, 01H, 02H + 199 199 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 200 200 $DGS GLV_SYM, _FSL_IVerify, U, U, 0CH, 02H, 01H, 02H + 201 201 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 202 202 $DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H + 203 203 $DGS GLV_SYM, _@RTARG2, U, U, 00H, 02H, 00H, 00H + 204 204 $DGS GLV_SYM, _FSL_Write, U, U, 0CH, 02H, 01H, 02H + 205 205 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 206 206 $DGS GLV_SYM, _pool, U, U, 0DH, 02H, 01H, 03H + 207 207 $DGS AUX_STR, 00H, 00H, 02H, 01H, 00H, 00H, 00H, 00H + 208 208 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H + 209 209 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 210 210 $DGS GLV_SYM, _FSL_SwapBootCluster, U, U, 01H, 02H, 01H, 02H + 211 211 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 212 212 $DGS GLV_SYM, _FSL_InvertBootFlag, U, U, 0CH, 02H, 01H, 02H + 213 213 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 214 214 $DGS GLV_SYM, @@iscmp, U, U, 00H, 02H, 00H, 00H + 215 215 $DGS GLV_SYM, _FSL_BlankCheck, U, U, 0CH, 02H, 01H, 02H + 216 216 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 217 217 $DGS GLV_SYM, _FSL_Init, U, U, 0CH, 02H, 01H, 02H + 218 218 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 219 219 $DGS GLV_SYM, _FSL_ModeCheck, U, U, 0CH, 02H, 01H, 02H + 220 220 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 221 221 $DGS GLV_SYM, _FSL_ForceReset, U, U, 01H, 02H, 01H, 02H + 222 222 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 223 223 + 224 224 EXTRN _FSL_Erase + 225 225 EXTRN _FSL_IVerify + 226 226 EXTRN _@RTARG0 + 227 227 EXTRN _@RTARG2 + 228 228 EXTRN _FSL_Write + 229 229 EXTRN _pool + 230 230 EXTRN _WDT_Restart + 231 231 EXTRN _FSL_SwapBootCluster + 232 232 EXTRN _FSL_InvertBootFlag + 233 233 EXTRN @@iscmp + 234 234 EXTRN _FSL_BlankCheck + 235 235 EXTRN _FSL_Init + 236 236 EXTRN _FSL_ModeCheck + 237 237 EXTRN _FSL_ForceReset + 238 238 PUBLIC _fsl_fx_MHz_u08 + 239 239 PUBLIC _fsl_low_voltage_u08 + 240 240 PUBLIC _firm_update + 241 241 PUBLIC _firm_restore + 242 242 PUBLIC _tski_mcu_reset + 243 243 + 244 244 ----- @@BITS BSEG + 245 245 + 246 246 ----- @@CNST CSEG MIRRORP + 247 247 00000 08 _fsl_fx_MHz_u08: DB 08H ; 8 + 248 248 00001 01 _fsl_low_voltage_u08: DB 01H ; 1 + 249 249 + 250 250 ----- @@R_INIT CSEG UNIT64KP + 251 251 + 252 252 ----- @@INIT DSEG BASEP + 253 253 + 254 254 ----- @@DATA DSEG BASEP + 255 255 + 256 256 ----- @@R_INIS CSEG UNIT64KP + 257 257 + 258 258 ----- @@INIS DSEG SADDRP + 259 259 + 260 260 ----- @@DATS DSEG SADDRP + 261 261 + 262 262 ----- LDR_CNSL CSEG PAGE64KP + 263 263 + 264 264 ----- @@RLINIT CSEG UNIT64KP + 265 265 + 266 266 ----- @@INITL DSEG UNIT64KP + 267 267 + 268 268 ----- @@DATAL DSEG UNIT64KP + 269 269 + 270 270 ----- @@CALT CSEG CALLT0 + 271 271 + 272 272 ; Sub-Routines created by CC78K0R + 273 273 + 274 274 ----- LDR_CODE CSEG BASE + 275 275 00000 bs_F0064: + 276 276 00000 8C05 mov a,[hl+5] ;[INF] 2, 1 + 277 277 00002 318E shrw ax,8 ;[INF] 2, 1 + 278 278 00004 RED0000 br !_FSL_Erase ;[INF] 3, 3 + 279 279 00007 es_F0064: + 280 280 + 281 281 ----- LDR_CODE CSEG BASE + 282 282 00007 bs_S0062: + 283 283 00007 C7 push hl ;[INF] 1, 1 + 284 284 00008 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 285 285 0000B 7184 mov1 CY,[hl].0 ;[INF] 2, 1 + 286 286 0000D C6 pop hl ;[INF] 1, 1 + 287 287 0000E D7 ret ;[INF] 1, 6 + 288 288 0000F es_S0062: + 289 289 + 290 290 ----- LDR_CODE CSEG BASE + 291 291 0000F bs_F0063: + 292 292 0000F 8C05 mov a,[hl+5] ;[INF] 2, 1 + 293 293 00011 318E shrw ax,8 ;[INF] 2, 1 + 294 294 00013 RFD0000 call !_FSL_IVerify ;[INF] 3, 3 + 295 295 00016 D2 cmp0 c ;[INF] 1, 1 + 296 296 00017 D7 ret ;[INF] 1, 6 + 297 297 00018 es_F0063: + 298 298 + 299 299 ----- LDR_CODE CSEG BASE + 300 300 00018 bs_F0061: + 301 301 00018 RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 302 302 0001A 31FF sarw ax,15 ;[INF] 2, 1 + 303 303 0001C RBD00 movw _@RTARG2,ax ;[INF] 2, 1 + 304 304 0001E RDA00 movw bc,_@RTARG2 ;[INF] 2, 1 + 305 305 00020 RAD00 movw ax,_@RTARG0 ;[INF] 2, 1 + 306 306 00022 RED0000 br !_FSL_Write ;[INF] 3, 3 + 307 307 00025 es_F0061: + 308 308 + 309 309 ----- LDR_CODE CSEG BASE + 310 310 00025 bs_S0060: + 311 311 00025 8C05 mov a,[hl+5] ;[INF] 2, 1 + 312 312 00027 318E shrw ax,8 ;[INF] 2, 1 + 313 313 00029 31AD shlw ax,10 ;[INF] 2, 1 + 314 314 0002B 12 movw bc,ax ;[INF] 1, 1 + 315 315 0002C 8C04 mov a,[hl+4] ;[INF] 2, 1 + 316 316 0002E 318E shrw ax,8 ;[INF] 2, 1 + 317 317 00030 318D shlw ax,8 ;[INF] 2, 1 + 318 318 00032 03 addw ax,bc ;[INF] 1, 1 + 319 319 00033 D7 ret ;[INF] 1, 6 + 320 320 00034 es_S0060: + 321 321 + 322 322 ; *** Sub-Routine Information *** + 323 323 ; + 324 324 ; $SUB bs_S0060 + 325 325 ; CODE SIZE= 15 bytes + 326 326 ; + 327 327 ; $SUB bs_F0061 + 328 328 ; CODE SIZE= 13 bytes + 329 329 ; + 330 330 ; $SUB bs_S0062 + 331 331 ; CODE SIZE= 8 bytes + 332 332 ; + 333 333 ; $SUB bs_F0063 + 334 334 ; CODE SIZE= 9 bytes + 335 335 ; + 336 336 ; $SUB bs_F0064 + 337 337 ; CODE SIZE= 7 bytes + 338 338 + 339 339 ; End of Sub-Routines + 340 340 + 341 341 ; line 1 : /* ======================================================== + 342 342 ; line 2 : 自己アップデータ + 343 343 ; line 3 : ======================================================== */ + 344 344 ; line 4 : #pragma SFR + 345 345 ; line 5 : #pragma di + 346 346 ; line 6 : #pragma ei + 347 347 ; line 7 : #pragma nop + 348 348 ; line 8 : #pragma stop + 349 349 ; line 9 : #pragma halt + 350 350 ; line 10 : + 351 351 ; line 11 : + 352 352 ; line 12 : #include "incs_loader.h" + 353 353 ; line 13 : + 354 354 ; line 14 : #include + 355 355 ; line 15 : #include "fsl_user.h" + 356 356 ; line 16 : #include "i2c_ctr.h" + 357 357 ; line 17 : + 358 358 ; line 18 : + 359 359 ; line 19 : + 360 360 ; line 20 : // ======================================================== + 361 361 ; line 21 : const u8 fsl_fx_MHz_u08 = 8; + 362 362 ; line 22 : const u8 fsl_low_voltage_u08 = 1; + 363 363 ; line 23 : + 364 364 ; line 24 : + 365 365 ; line 25 : // 自己フラッシュパラメータ + 366 366 ; line 26 : #define SAM_BLOCK_SIZE 1024 + 367 367 ; line 27 : #define SELF_UPDATE_BUFF_SIZE 256 + 368 368 ; line 28 : #define SELF_UPDATE_SPLIT_WRITE_NUM ( SAM_BLOCK_SIZE / SELF_U + 369 369 ; PDATE_BUFF_SIZE ) + 370 370 ; line 29 : #define SAM_WORD_SIZE 4 + 371 371 ; line 30 : + 372 372 ; line 31 : // ↓ブロック番号（1ブロック＝ + 373 373 ; 1kB） + 374 374 ; line 32 : #define INACTIVE_BOOTSECT_TOP 4 + 375 375 ; line 33 : #define FIRM_TOP 8 + 376 376 ; line 34 : #define FIRM_SIZE 12 + 377 377 ; line 35 : #define UPDATE_BLOCK_LAST ( FIRM_TOP + FIRM_SIZE - 1 + 378 378 ; ) + 379 379 ; line 36 : + 380 380 ; line 37 : + 381 381 ; line 38 : #ifdef _MCU_BSR_ + 382 382 ; line 39 : + 383 383 ; line 40 : + 384 384 ; line 41 : #define ACKD ACKD1 + 385 385 ; line 42 : #define ACKE ACKE1 + 386 386 ; line 43 : #define COI COI1 + 387 387 ; line 44 : #define IICAEN IICA1EN + 388 388 ; line 45 : #define IICAPR0 IICAPR10 + 389 389 ; line 46 : #define IICRSV IICRSV1 + 390 390 ; line 47 : #define IICA IICA1 + 391 391 ; line 48 : #define IICAIF IICAIF1 + 392 392 ; line 49 : #define IICAMK IICAMK1 + 393 393 ; line 50 : #define IICAPR1 IICAPR11 + 394 394 ; line 51 : #define IICCTL0 IICCTL01 + 395 395 ; line 52 : #define IICE IICE1 + 396 396 ; line 53 : #define IICF IICF1 + 397 397 ; line 54 : #define IICS IICS1 + 398 398 ; line 55 : #define IICWH IICWH1 + 399 399 ; line 56 : #define IICWL IICWL1 + 400 400 ; line 57 : #define LREL LREL1 + 401 401 ; line 58 : #define SPD SPD1 + 402 402 ; line 59 : #define SPIE SPIE1 + 403 403 ; line 60 : #define STCEN STCEN1 + 404 404 ; line 61 : #define STD STD1 + 405 405 ; line 62 : #define SVA SVA1 + 406 406 ; line 63 : #define WREL WREL1 + 407 407 ; line 64 : #define WTIM WTIM1 + 408 408 ; line 65 : #endif + 409 409 ; line 66 : + 410 410 ; line 67 : + 411 411 ; line 68 : + 412 412 ; line 69 : // ======================================================== + 413 413 ; line 70 : static void FSL_Open( void ); + 414 414 ; line 71 : static void FSL_Close( void ); + 415 415 ; line 72 : err firm_restore( ); + 416 416 ; line 73 : + 417 417 ; line 74 : static err my_FSL_Init(); + 418 418 ; line 75 : static err firm_duplicate( __far u8 * p_rom, u8 block_dest ); + 419 419 ; line 76 : + 420 420 ; line 77 : + 421 421 ; line 78 : + 422 422 ; line 79 : // ======================================================== + 423 423 ; line 80 : extern u16 pool[]; + 424 424 ; line 81 : + 425 425 ; line 82 : + 426 426 ; line 83 : // 0.D以降 新アップデータ向け + 427 427 ; line 84 : #define N_MGC_L 0x1FF6 + 428 428 ; line 85 : #define N_MGC_T 0x4FF6 + 429 429 ; line 86 : + 430 430 ; line 87 : + 431 431 ; line 88 : + 432 432 ; line 89 : /* ======================================================== + 433 433 ; line 90 : I2Cで受信して、 + 434 434 ; line 91 : 書き込み、 + 435 435 ; line 92 : チェックOK　→　新ファームに切り替えて再起動 + 436 436 ; line 93 : 　　　　NG　→　旧（現）ファームに戻して再起動 + 437 437 ; line 94 : （この関数からは戻りません） + 438 438 ; line 95 : ======================================================== */ + 439 439 ; line 96 : err firm_update( ) + 440 440 ; line 97 : { + 441 441 + 442 442 ----- LDR_CODE CSEG BASE + 443 443 00034 _firm_update: + 444 444 $DGL 1,35 + 445 445 00034 C7 push hl ;[INF] 1, 1 + 446 446 00035 2006 subw sp,#06H ;[INF] 2, 1 + 447 447 00037 FBF8FF movw hl,sp ;[INF] 3, 1 + 448 448 0003A ??bf_firm_update: + 449 449 ; line 98 : u8 target_block; + 450 450 ; line 99 : u8 split_write_count; // ブロックへちまちま書き込むカウ + 451 451 ; ンタ + 452 452 ; line 100 : + 453 453 ; line 101 : // 書き替え前準備 ///////////////////////////////////// + 454 454 ; line 102 : my_FSL_Init(); + 455 455 $DGL 0,6 + 456 456 0003A RFDD001 call !_my_FSL_Init ;[INF] 3, 3 + 457 457 ; line 103 : + 458 458 ; line 104 : /* ファームのバックアップ + 459 459 ; line 105 : 0x2000 - 0x4FFF を + 460 460 ; line 106 : 0x5000 - 0x7FFF (ブロック 20 - 31) にコピー + 461 461 ; line 107 : */ + 462 462 ; line 108 : firm_duplicate( ( __far u8 * ) 0x2000, + 463 463 ; line 109 : ( 0x5000 / 0x0400 ) ); + 464 464 $DGL 0,13 + 465 465 0003D 301400 movw ax,#014H ; 20 ;[INF] 3, 1 + 466 466 00040 C1 push ax ;[INF] 1, 1 + 467 467 00041 300020 movw ax,#02000H ; 8192 ;[INF] 3, 1 + 468 468 00044 F7 clrw bc ;[INF] 1, 1 + 469 469 00045 RFD4801 call !_firm_duplicate ;[INF] 3, 3 + 470 470 00048 C0 pop ax ;[INF] 1, 1 + 471 471 ; line 110 : + 472 472 ; line 111 : // 全ブロック削除 ///////////////////////////////////// + 473 473 ; line 112 : // 電源断を判定するため、最初に全クラスタ消去する + 474 474 ; line 113 : //（新ファームが書かれるところに残ってる、以前のファームのフ + 475 475 ; ッタを消したい） + 476 476 ; line 114 : for( target_block = INACTIVE_BOOTSECT_TOP; + 477 477 $DGL 0,18 + 478 478 00049 CC0504 mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1 + 479 479 0004C ?L0003: + 480 480 ; line 115 : target_block <= UPDATE_BLOCK_LAST; + 481 481 $DGL 0,19 + 482 482 0004C 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1 + 483 483 0004E 4C14 cmp a,#014H ; 20 ;[INF] 2, 1 + 484 484 00050 DE08 bnc $?L0004 ;[INF] 2, 4 + 485 485 ; line 116 : target_block += 1 ) + 486 486 ; line 117 : { + 487 487 00052 ??bb00_firm_update: + 488 488 ; line 118 : FSL_Erase( target_block ); + 489 489 $DGL 0,22 + 490 490 00052 RFD0000 call !bs_F0064 ;[INF] 3, 3 + 491 491 00055 ??eb00_firm_update: + 492 492 ; line 119 : } + 493 493 $DGL 0,23 + 494 494 00055 615905 inc [hl+5] ; target_block ;[INF] 3, 2 + 495 495 00058 EFF2 br $?L0003 ;[INF] 2, 3 + 496 496 0005A ?L0004: + 497 497 ; line 120 : + 498 498 ; line 121 : // 書き替え /////////////////////////////////////////// + 499 499 ; line 122 : // ●ストップコンディションが来るまで続ける + 500 500 ; line 123 : // ●終わったら、スタートアップルーチンに飛ぶ + 501 501 ; line 124 : for( target_block = INACTIVE_BOOTSECT_TOP; + 502 502 $DGL 0,28 + 503 503 0005A CC0504 mov [hl+5],#04H ; target_block,4 ;[INF] 3, 1 + 504 504 0005D ?L0006: + 505 505 ; line 125 : target_block <= UPDATE_BLOCK_LAST; + 506 506 $DGL 0,29 + 507 507 0005D 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1 + 508 508 0005F 4C14 cmp a,#014H ; 20 ;[INF] 2, 1 + 509 509 00061 DE6C bnc $?L0007 ;[INF] 2, 4 + 510 510 ; line 126 : target_block += 1 ) + 511 511 ; line 127 : { + 512 512 00063 ??bb01_firm_update: + 513 513 ; line 128 : // 新ファーム領域削除 + 514 514 ; line 129 : FSL_Erase( target_block ); + 515 515 $DGL 0,33 + 516 516 00063 RFD0000 call !bs_F0064 ;[INF] 3, 3 + 517 517 ; line 130 : + 518 518 ; line 131 : // 分割書き込み + 519 519 ; line 132 : for( split_write_count = 0; + 520 520 $DGL 0,36 + 521 521 00066 CC0400 mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1 + 522 522 00069 ?L0009: + 523 523 ; line 133 : ( ( split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM + 524 524 ; ) + 525 525 ; line 134 : && ( !SPD ) ); + 526 526 $DGL 0,38 + 527 527 00069 8C04 mov a,[hl+4] ; split_write_count ;[INF] 2, 1 + 528 528 0006B 4C04 cmp a,#04H ; 4 ;[INF] 2, 1 + 529 529 0006D DE50 bnc $?L0010 ;[INF] 2, 4 + 530 530 0006F RFD0700 call !bs_S0062 ;[INF] 3, 3 + 531 531 00072 DC4B bc $?L0010 ;[INF] 2, 4 + 532 532 ; line 135 : split_write_count += 1 ) + 533 533 ; line 136 : { + 534 534 00074 ??bb02_firm_update: + 535 535 ; line 137 : u8* p_buffer = pool; + 536 536 $DGL 0,41 + 537 537 00074 R300000 movw ax,#loww (_pool) ;[INF] 3, 1 + 538 538 00077 BC02 movw [hl+2],ax ; p_buffer ;[INF] 2, 1 + 539 539 ; line 138 : u8 buffer_fill = 0; + 540 540 $DGL 0,42 + 541 541 00079 CC0100 mov [hl+1],#00H ; buffer_fill,0 ;[INF] 3, 1 + 542 542 ; line 139 : + 543 543 ; line 140 : WDT_Restart( ); + 544 544 $DGL 0,44 + 545 545 0007C RFD0000 call !_WDT_Restart ;[INF] 3, 3 + 546 546 ; line 141 : + 547 547 ; line 142 : // I2Cから書き込みデータをバッファにためる + 548 548 ; line 143 : do + 549 549 0007F ?L0012: + 550 550 ; line 144 : { + 551 551 0007F ??bb03_firm_update: + 552 552 ; line 145 : while( !IICAIF && !SPD ){;} + 553 553 $DGL 0,49 + 554 554 0007F 31B2D105 bt IF2H.3,$?L0016 ;[INF] 4, 5 + 555 555 00083 RFD0700 call !bs_S0062 ;[INF] 3, 3 + 556 556 00086 DEF7 bnc $?L0012 ;[INF] 2, 4 + 557 557 00088 ??bb04_firm_update: + 558 558 00088 ??eb04_firm_update: + 559 559 00088 ?L0016: + 560 560 ; line 146 : IICAIF = 0; + 561 561 $DGL 0,50 + 562 562 00088 713BD1 clr1 IF2H.3 ;[INF] 3, 2 + 563 563 ; line 147 : *p_buffer = IICA; + 564 564 $DGL 0,51 + 565 565 0008B AC02 movw ax,[hl+2] ; p_buffer ;[INF] 2, 1 + 566 566 0008D 14 movw de,ax ;[INF] 1, 1 + 567 567 0008E 8F4005 mov a,!IICA1 ;[INF] 3, 1 + 568 568 00091 99 mov [de],a ;[INF] 1, 1 + 569 569 ; line 148 : WREL = 1; + 570 570 $DGL 0,52 + 571 571 00092 71505005 set1 !IICCTL01.5 ;[INF] 4, 2 + 572 572 ; line 149 : p_buffer += 1; + 573 573 $DGL 0,53 + 574 574 00096 617902 incw [hl+2] ; p_buffer ;[INF] 3, 2 + 575 575 ; line 150 : buffer_fill += 1; + 576 576 $DGL 0,54 + 577 577 00099 615901 inc [hl+1] ; buffer_fill ;[INF] 3, 2 + 578 578 0009C ??eb03_firm_update: + 579 579 ; line 151 : } + 580 580 ; line 152 : while( ( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE + 581 581 ; ) && !SPD ); + 582 582 $DGL 0,56 + 583 583 0009C 8C01 mov a,[hl+1] ; buffer_fill ;[INF] 2, 1 + 584 584 0009E D1 cmp0 a ;[INF] 1, 1 + 585 585 0009F DD05 bz $?L0017 ;[INF] 2, 4 + 586 586 000A1 RFD0700 call !bs_S0062 ;[INF] 3, 3 + 587 587 000A4 DED9 bnc $?L0012 ;[INF] 2, 4 + 588 588 000A6 ?L0017: + 589 589 ; line 153 : + 590 590 ; line 154 : // 書き込み + 591 591 ; line 155 : // 最後だと、ゴミをパディングするが別にかまわない + 592 592 ; line 156 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC + 593 593 ; K_SIZE + 594 594 ; line 157 : + + 595 595 ; line 158 : split_write_count * + 596 596 ; line 159 : SELF_UPDATE_BUFF_SIZE + 597 597 ; ), + 598 598 ; line 160 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE + 599 599 ; / SAM_WORD_SIZE ) ) + 600 600 ; line 161 : + 601 601 ; line 162 : != FSL_OK ) + 602 602 $DGL 0,66 + 603 603 000A6 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 604 604 000A9 C1 push ax ;[INF] 1, 1 + 605 605 000AA RFD2500 call !bs_S0060 ;[INF] 3, 3 + 606 606 000AD RFD1800 call !bs_F0061 ;[INF] 3, 3 + 607 607 000B0 C0 pop ax ;[INF] 1, 1 + 608 608 000B1 D2 cmp0 c ;[INF] 1, 1 + 609 609 000B2 DD06 bz $?L0018 ;[INF] 2, 4 + 610 610 ; line 163 : { + 611 611 000B4 ??bb05_firm_update: + 612 612 ; line 164 : // 書き込み後のチェックエラー + 613 613 ; line 165 : // リブートののち、リストア + 614 614 ; line 166 : // FSL_ForceReset(); // リセット + 615 615 ; line 167 : FSL_SwapBootCluster( ); + 616 616 $DGL 0,71 + 617 617 000B4 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3 + 618 618 ; line 168 : // FSL_Close( ); + 619 619 ; line 169 : return ( ERR_ERR ); + 620 620 $DGL 0,73 + 621 621 000B7 E7 onew bc ;[INF] 1, 1 + 622 622 000B8 EF59 br $?L0030 ;[INF] 2, 3 + 623 623 000BA ??eb05_firm_update: + 624 624 ; line 170 : } + 625 625 000BA ?L0018: + 626 626 000BA ??eb02_firm_update: + 627 627 ; line 171 : + 628 628 ; line 172 : } + 629 629 $DGL 0,76 + 630 630 000BA 615904 inc [hl+4] ; split_write_count ;[INF] 3, 2 + 631 631 000BD EFAA br $?L0009 ;[INF] 2, 3 + 632 632 000BF ?L0010: + 633 633 ; line 173 : // 1ブロック書き込み完了。内部ベリファイを行う + 634 634 ; line 174 : if( FSL_IVerify( target_block ) != FSL_OK ){ + 635 635 $DGL 0,78 + 636 636 000BF RFD0F00 call !bs_F0063 ;[INF] 3, 3 + 637 637 000C2 61E8 skz ;[INF] 2, 1 + 638 638 000C4 ??bb06_firm_update: + 639 639 ; line 175 : // todo 再度消去→書き込み ベリファイを繰り返すだけじ + 640 640 ; ゃダメでした... + 641 641 ; line 176 : NOP(); + 642 642 $DGL 0,80 + 643 643 000C4 00 nop ;[INF] 1, 1 + 644 644 000C5 ??eb06_firm_update: + 645 645 ; line 177 : } + 646 646 000C5 ?L0020: + 647 647 ; line 178 : + 648 648 ; line 179 : if( SPD ) + 649 649 $DGL 0,83 + 650 650 000C5 RFD0700 call !bs_S0062 ;[INF] 3, 3 + 651 651 000C8 DC05 bc $?L0007 ;[INF] 2, 4 + 652 652 ; line 180 : { + 653 653 000CA ??bb07_firm_update: + 654 654 ; line 181 : break; + 655 655 000CA ??eb07_firm_update: + 656 656 ; line 182 : } + 657 657 000CA ??eb01_firm_update: + 658 658 ; line 183 : } + 659 659 $DGL 0,87 + 660 660 000CA 615905 inc [hl+5] ; target_block ;[INF] 3, 2 + 661 661 000CD EF8E br $?L0006 ;[INF] 2, 3 + 662 662 000CF ?L0007: + 663 663 ; line 184 : + 664 664 ; line 185 : LREL = 1; + 665 665 $DGL 0,89 + 666 666 000CF 71605005 set1 !IICCTL01.6 ;[INF] 4, 2 + 667 667 ; line 186 : + 668 668 ; line 187 : // 書き込んだファームのチェック // + 669 669 ; line 188 : { + 670 670 000D3 ??bb08_firm_update: + 671 671 ; line 189 : u8 i; + 672 672 ; line 190 : u8 comp = 0; + 673 673 $DGL 0,94 + 674 674 000D3 CC0200 mov [hl+2],#00H ; comp,0 ;[INF] 3, 1 + 675 675 ; line 191 : + 676 676 ; line 192 : // ローダーのマジックと、本文の末尾のマジックは同じか確認 + 677 677 ; line 193 : for( i = 0; i < sizeof( __TIME__ ); i++ ) + 678 678 $DGL 0,97 + 679 679 000D6 CC0300 mov [hl+3],#00H ; i,0 ;[INF] 3, 1 + 680 680 000D9 ?L0024: + 681 681 000D9 8C03 mov a,[hl+3] ; i ;[INF] 2, 1 + 682 682 000DB 4C09 cmp a,#09H ; 9 ;[INF] 2, 1 + 683 683 000DD DE24 bnc $?L0025 ;[INF] 2, 4 + 684 684 ; line 194 : { + 685 685 000DF ??bb09_firm_update: + 686 686 ; line 195 : comp += ( *( u8 * ) ( N_MGC_L + i ) == *( u8 * ) ( N + 687 687 ; _MGC_T + i ) ) ? 0 : 1; + 688 688 $DGL 0,99 + 689 689 000DF 8C03 mov a,[hl+3] ; i ;[INF] 2, 1 + 690 690 000E1 318E shrw ax,8 ;[INF] 2, 1 + 691 691 000E3 12 movw bc,ax ;[INF] 1, 1 + 692 692 000E4 49F61F mov a,8182[bc] ;[INF] 3, 1 + 693 693 000E7 72 mov c,a ;[INF] 1, 1 + 694 694 000E8 8C03 mov a,[hl+3] ; i ;[INF] 2, 1 + 695 695 000EA 318E shrw ax,8 ;[INF] 2, 1 + 696 696 000EC 04F64F addw ax,#04FF6H ; 20470 ;[INF] 3, 1 + 697 697 000EF 14 movw de,ax ;[INF] 1, 1 + 698 698 000F0 89 mov a,[de] ;[INF] 1, 1 + 699 699 000F1 6142 cmp c,a ;[INF] 2, 1 + 700 700 000F3 DF03 bnz $?L0027 ;[INF] 2, 4 + 701 701 000F5 F6 clrw ax ;[INF] 1, 1 + 702 702 000F6 EF01 br $?L0028 ;[INF] 2, 3 + 703 703 000F8 ?L0027: + 704 704 000F8 E6 onew ax ;[INF] 1, 1 + 705 705 000F9 ?L0028: + 706 706 000F9 60 mov a,x ;[INF] 1, 1 + 707 707 000FA 0E02 add a,[hl+2] ; comp ;[INF] 2, 1 + 708 708 000FC 9C02 mov [hl+2],a ; comp ;[INF] 2, 1 + 709 709 000FE ??eb09_firm_update: + 710 710 ; line 196 : } + 711 711 $DGL 0,100 + 712 712 000FE 615903 inc [hl+3] ; i ;[INF] 3, 2 + 713 713 00101 EFD6 br $?L0024 ;[INF] 2, 3 + 714 714 00103 ?L0025: + 715 715 ; line 197 : if( comp == 0 ) + 716 716 $DGL 0,101 + 717 717 00103 8C02 mov a,[hl+2] ; comp ;[INF] 2, 1 + 718 718 00105 D1 cmp0 a ;[INF] 1, 1 + 719 719 00106 DF08 bnz $?L0029 ;[INF] 2, 4 + 720 720 ; line 198 : { + 721 721 00108 ??bb0A_firm_update: + 722 722 ; line 199 : FSL_InvertBootFlag( ); + 723 723 $DGL 0,103 + 724 724 00108 RFD0000 call !_FSL_InvertBootFlag ;[INF] 3, 3 + 725 725 ; line 200 : FSL_SwapBootCluster( ); // リセットせずに頭から。F + 726 726 ; SL_Closeは不要 + 727 727 $DGL 0,104 + 728 728 0010B RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3 + 729 729 0010E ??eb0A_firm_update: + 730 730 ; line 201 : // FSL_ForceReset(); // リセット + 731 731 ; line 202 : // FSL_SwapActiveBootCluster(); // ←スワップされてし + 732 732 ; まうので、続けられず暴走！ + 733 733 ; line 203 : // 戻ってこない // + 734 734 ; line 204 : } + 735 735 $DGL 0,108 + 736 736 0010E EF03 br $?L0030 ;[INF] 2, 3 + 737 737 00110 ?L0029: + 738 738 ; line 205 : else + 739 739 ; line 206 : { + 740 740 00110 ??bb0B_firm_update: + 741 741 ; line 207 : // データエラー + 742 742 ; line 208 : // リブートののち、リストア + 743 743 ; line 209 : // FSL_ForceReset(); // リセット + 744 744 ; line 210 : FSL_SwapBootCluster( ); + 745 745 $DGL 0,114 + 746 746 00110 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3 + 747 747 00113 ??eb0B_firm_update: + 748 748 ; line 211 : // FSL_Close( ); + 749 749 ; line 212 : // 戻ってこない // + 750 750 ; line 213 : } + 751 751 00113 ?L0030: + 752 752 00113 ??eb08_firm_update: + 753 753 ; line 214 : } + 754 754 ; line 215 : } + 755 755 $DGL 0,119 + 756 756 00113 ??ef_firm_update: + 757 757 00113 1006 addw sp,#06H ;[INF] 2, 1 + 758 758 00115 C6 pop hl ;[INF] 1, 1 + 759 759 00116 D7 ret ;[INF] 1, 6 + 760 760 00117 ??ee_firm_update: + 761 761 ; line 216 : + 762 762 ; line 217 : + 763 763 ; line 218 : + 764 764 ; line 219 : + 765 765 ; line 220 : /* ======================================================== + 766 766 ; line 221 : 　■ファームをバックアップ領域からリストアします。 + 767 767 ; line 222 : 　チェック後、最後の最後でブートスワップするので、 + 768 768 ; line 223 : 　ここではブートスワップは不要です。 + 769 769 ; line 224 : + 770 770 ; line 225 : ======================================================== */ + 771 771 ; line 226 : err firm_restore( ) + 772 772 ; line 227 : { + 773 773 00117 _firm_restore: + 774 774 $DGL 1,99 + 775 775 00117 ??bf_firm_restore: + 776 776 ; line 228 : my_FSL_Init(); + 777 777 $DGL 0,2 + 778 778 00117 RFDD001 call !_my_FSL_Init ;[INF] 3, 3 + 779 779 ; line 229 : + 780 780 ; line 230 : /* ファームのリストア + 781 781 ; line 231 : 0x4800 - 0x7FFF (ブロック 18 - 27) から + 782 782 ; line 232 : 0x2000 - 0x47FF (ブロック 8 - 17) へコピー + 783 783 ; line 233 : */ + 784 784 ; line 234 : firm_duplicate( ( __far u8 * ) 0x5000, + 785 785 ; line 235 : FIRM_TOP ); + 786 786 $DGL 0,9 + 787 787 0011A 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 788 788 0011D C1 push ax ;[INF] 1, 1 + 789 789 0011E 300050 movw ax,#05000H ; 20480 ;[INF] 3, 1 + 790 790 00121 F7 clrw bc ;[INF] 1, 1 + 791 791 00122 RFD4801 call !_firm_duplicate ;[INF] 3, 3 + 792 792 00125 C0 pop ax ;[INF] 1, 1 + 793 793 ; line 236 : + 794 794 ; line 237 : // todo + 795 795 ; line 238 : // 　リストア失敗したら、LEDちかちかとかさせて、サービス送 + 796 796 ; りにしてもらう + 797 797 ; line 239 : + 798 798 ; line 240 : // リブート + 799 799 ; line 241 : // スワップは不要です！ + 800 800 ; line 242 : FSL_SwapBootCluster(); + 801 801 $DGL 0,16 + 802 802 00126 RFD0000 call !_FSL_SwapBootCluster ;[INF] 3, 3 + 803 803 ; line 243 : // FSL_ForceReset( ); + 804 804 ; line 244 : return ( ERR_SUCCESS ); + 805 805 $DGL 0,18 + 806 806 00129 F7 clrw bc ;[INF] 1, 1 + 807 807 ; line 245 : } + 808 808 $DGL 0,19 + 809 809 0012A ??ef_firm_restore: + 810 810 0012A D7 ret ;[INF] 1, 6 + 811 811 0012B ??ee_firm_restore: + 812 812 ; line 246 : + 813 813 ; line 247 : + 814 814 ; line 248 : + 815 815 ; line 249 : + 816 816 ; line 250 : // ======================================================== + 817 817 ; line 251 : static void FSL_Open( void ) + 818 818 ; line 252 : { + 819 819 0012B _FSL_Open: + 820 820 $DGL 1,105 + 821 821 0012B ??bf_FSL_Open: + 822 822 ; line 253 : /* save the configuration of the interrupt controller and se + 823 823 ; t */ + 824 824 ; line 254 : #ifdef FSL_INT_BACKUP + 825 825 ; line 255 : fsl_MK0L_bak_u08 = MK0L; /* if (interrupt backup required + 826 826 ; ) */ + 827 827 ; line 256 : fsl_MK0H_bak_u08 = MK0H; /* { + 828 828 ; */ + 829 829 ; line 257 : fsl_MK1L_bak_u08 = MK1L; /* + 830 830 ; */ + 831 831 ; line 258 : fsl_MK1H_bak_u08 = MK1H; /* save interrupt control + 832 832 ; ler */ + 833 833 ; line 259 : fsl_MK2L_bak_u08 = MK2L; /* configuration + 834 834 ; */ + 835 835 ; line 260 : fsl_MK2H_bak_u08 = MK2H; /* + 836 836 ; */ + 837 837 ; line 261 : MK0L = FSL_MK0L_MASK; /* + 838 838 ; */ + 839 839 ; line 262 : MK0H = FSL_MK0H_MASK; /* + 840 840 ; */ + 841 841 ; line 263 : MK1L = FSL_MK1L_MASK; /* prepare interrupt cont + 842 842 ; roller */ + 843 843 ; line 264 : MK1H = FSL_MK1H_MASK; /* for selfprogramming + 844 844 ; */ + 845 845 ; line 265 : MK2L = FSL_MK2L_MASK; /* + 846 846 ; */ + 847 847 ; line 266 : MK2H = FSL_MK2H_MASK; /* } + 848 848 ; */ + 849 849 ; line 267 : #endif + 850 850 ; line 268 : + 851 851 ; line 269 : // 何か前準備？ + 852 852 ; line 270 : // todo DMAを止める + 853 853 ; line 271 : while( DST1 ){;} + 854 854 $DGL 0,20 + 855 855 0012B ?L0035: + 856 856 0012B 3184BD02 bf DRC1.0,$?L0036 ;[INF] 4, 5 + 857 857 0012F ??bb00_FSL_Open: + 858 858 0012F ??eb00_FSL_Open: + 859 859 0012F EFFA br $?L0035 ;[INF] 2, 3 + 860 860 00131 ?L0036: + 861 861 ; line 272 : DEN1 = 0; + 862 862 $DGL 0,21 + 863 863 00131 717BBD clr1 DRC1.7 ;[INF] 3, 2 + 864 864 ; line 273 : + 865 865 ; line 274 : MK0 = 0xFFFF; + 866 866 $DGL 0,23 + 867 867 00134 CBE4FFFF movw MK0,#0FFFFH ; -1 ;[INF] 4, 1 + 868 868 ; line 275 : MK1 = 0xFFFF; + 869 869 $DGL 0,24 + 870 870 00138 CBE6FFFF movw MK1,#0FFFFH ; -1 ;[INF] 4, 1 + 871 871 ; line 276 : MK2 = 0xFFFF; + 872 872 $DGL 0,25 + 873 873 0013C CBD4FFFF movw MK2,#0FFFFH ; -1 ;[INF] 4, 1 + 874 874 ; line 277 : + 875 875 ; line 278 : FSL_FLMD0_HIGH; // フラッシュ書き替え許可 + 876 876 $DGL 0,27 + 877 877 00140 ??bb01_FSL_Open: + 878 878 00140 717ABE set1 BECTL.7 ;[INF] 3, 2 + 879 879 00143 ??eb01_FSL_Open: + 880 880 ; line 279 : } + 881 881 $DGL 0,28 + 882 882 00143 ??ef_FSL_Open: + 883 883 00143 D7 ret ;[INF] 1, 6 + 884 884 00144 ??ee_FSL_Open: + 885 885 ; line 280 : + 886 886 ; line 281 : + 887 887 ; line 282 : + 888 888 ; line 283 : /*-------------------------------------------------------------- + 889 889 ; --------------------------------*/ + 890 890 ; line 284 : /* leave the "user room" and restore previous conditions + 891 891 ; */ + 892 892 ; line 285 : /*-------------------------------------------------------------- + 893 893 ; --------------------------------*/ + 894 894 ; line 286 : static void FSL_Close( void ) + 895 895 ; line 287 : { + 896 896 00144 _FSL_Close: + 897 897 $DGL 1,119 + 898 898 00144 ??bf_FSL_Close: + 899 899 ; line 288 : // 何か後始末？ + 900 900 ; line 289 : + 901 901 ; line 290 : FSL_FLMD0_LOW; // フラッシュライトプロテクト + 902 902 $DGL 0,4 + 903 903 00144 ??bb00_FSL_Close: + 904 904 00144 717BBE clr1 BECTL.7 ;[INF] 3, 2 + 905 905 00147 ??eb00_FSL_Close: + 906 906 ; line 291 : + 907 907 ; line 292 : #ifdef FSL_INT_BACKUP + 908 908 ; line 293 : MK0L = fsl_MK0L_bak_u08; /* do{ + 909 909 ; */ + 910 910 ; line 294 : MK0H = fsl_MK0H_bak_u08; /* restore interrupt cont + 911 911 ; roller */ + 912 912 ; line 295 : MK1L = fsl_MK1L_bak_u08; /* configuration + 913 913 ; */ + 914 914 ; line 296 : MK1H = fsl_MK1H_bak_u08; /* + 915 915 ; */ + 916 916 ; line 297 : MK2L = fsl_MK2L_bak_u08; /* + 917 917 ; */ + 918 918 ; line 298 : MK2H = fsl_MK2H_bak_u08; /* } + 919 919 ; */ + 920 920 ; line 299 : #endif + 921 921 ; line 300 : } + 922 922 $DGL 0,14 + 923 923 00147 ??ef_FSL_Close: + 924 924 00147 D7 ret ;[INF] 1, 6 + 925 925 00148 ??ee_FSL_Close: + 926 926 ; line 301 : + 927 927 ; line 302 : + 928 928 ; line 303 : + 929 929 ; line 304 : /* ======================================================== + 930 930 ; line 305 : 　マイコン内でファームをコピーします。 + 931 931 ; line 306 : __far u8 * p_rom コピー元の先頭アドレス + 932 932 ; line 307 : block_dest コピー先の先頭ブロック + 933 933 ; line 308 : + 934 934 ; line 309 : コピー先に書けるようにmy_FSL_Initをあらかじめ実行する必要があり + 935 935 ; ます。 + 936 936 ; line 310 : ======================================================== */ + 937 937 ; line 311 : static err firm_duplicate( __far u8 * p_rom, + 938 938 ; line 312 : u8 block_dest ) + 939 939 ; line 313 : { + 940 940 00148 _firm_duplicate: + 941 941 $DGL 1,129 + 942 942 00148 C7 push hl ;[INF] 1, 1 + 943 943 00149 C3 push bc ;[INF] 1, 1 + 944 944 0014A C1 push ax ;[INF] 1, 1 + 945 945 0014B 2006 subw sp,#06H ;[INF] 2, 1 + 946 946 0014D FBF8FF movw hl,sp ;[INF] 3, 1 + 947 947 00150 ??bf_firm_duplicate: + 948 948 ; line 314 : u8 target_block; + 949 949 ; line 315 : u8 split_write_count; // ブロックへちまちま書き込むカウ + 950 950 ; ンタ + 951 951 ; line 316 : + 952 952 ; line 317 : // 書き込み先ブロックの数だけ繰り返す + 953 953 ; line 318 : for( target_block = block_dest; + 954 954 $DGL 0,6 + 955 955 00150 8C10 mov a,[hl+16] ; block_dest ;[INF] 2, 1 + 956 956 00152 9C05 mov [hl+5],a ; target_block ;[INF] 2, 1 + 957 957 00154 ?L0041: + 958 958 ; line 319 : target_block < block_dest + FIRM_SIZE; + 959 959 $DGL 0,7 + 960 960 00154 8C10 mov a,[hl+16] ; block_dest ;[INF] 2, 1 + 961 961 00156 318E shrw ax,8 ;[INF] 2, 1 + 962 962 00158 040C00 addw ax,#0CH ; 12 ;[INF] 3, 1 + 963 963 0015B 12 movw bc,ax ;[INF] 1, 1 + 964 964 0015C 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1 + 965 965 0015E 318E shrw ax,8 ;[INF] 2, 1 + 966 966 00160 RBD00 movw _@RTARG0,ax ;[INF] 2, 1 + 967 967 00162 13 movw ax,bc ;[INF] 1, 1 + 968 968 00163 RFD0000 call !@@iscmp ;[INF] 3, 3 + 969 969 00166 DE63 bnc $?L0042 ;[INF] 2, 4 + 970 970 ; line 320 : target_block += 1 ) + 971 971 ; line 321 : { + 972 972 00168 ??bb00_firm_duplicate: + 973 973 ; line 322 : WDT_Restart( ); + 974 974 $DGL 0,10 + 975 975 00168 RFD0000 call !_WDT_Restart ;[INF] 3, 3 + 976 976 ; line 323 : // ブロック消去 + 977 977 ; line 324 : while( FSL_BlankCheck( target_block ) != FSL_OK ) + 978 978 $DGL 0,12 + 979 979 0016B ?L0044: + 980 980 0016B 8C05 mov a,[hl+5] ; target_block ;[INF] 2, 1 + 981 981 0016D 318E shrw ax,8 ;[INF] 2, 1 + 982 982 0016F RFD0000 call !_FSL_BlankCheck ;[INF] 3, 3 + 983 983 00172 D2 cmp0 c ;[INF] 1, 1 + 984 984 00173 DD05 bz $?L0045 ;[INF] 2, 4 + 985 985 ; line 325 : { + 986 986 00175 ??bb01_firm_duplicate: + 987 987 ; line 326 : FSL_Erase( target_block ); + 988 988 $DGL 0,14 + 989 989 00175 RFD0000 call !bs_F0064 ;[INF] 3, 3 + 990 990 00178 ??eb01_firm_duplicate: + 991 991 ; line 327 : } + 992 992 $DGL 0,15 + 993 993 00178 EFF1 br $?L0044 ;[INF] 2, 3 + 994 994 0017A ?L0045: + 995 995 ; line 328 : + 996 996 ; line 329 : // 分割書き込み分繰り返す + 997 997 ; line 330 : for( split_write_count = 0; + 998 998 $DGL 0,18 + 999 999 0017A CC0400 mov [hl+4],#00H ; split_write_count,0 ;[INF] 3, 1 + 1000 1000 0017D ?L0046: + 1001 1001 ; line 331 : split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM; + 1002 1002 $DGL 0,19 + 1003 1003 0017D 8C04 mov a,[hl+4] ; split_write_count ;[INF] 2, 1 + 1004 1004 0017F 4C04 cmp a,#04H ; 4 ;[INF] 2, 1 + 1005 1005 00181 DE3E bnc $?L0047 ;[INF] 2, 4 + 1006 1006 ; line 332 : split_write_count += 1 ) + 1007 1007 ; line 333 : { + 1008 1008 00183 ??bb02_firm_duplicate: + 1009 1009 ; line 334 : u8 buffer_fill; + 1010 1010 ; line 335 : u8* p_buff; + 1011 1011 ; line 336 : + 1012 1012 ; line 337 : // 書き込みデータをバッファにためる + 1013 1013 ; line 338 : buffer_fill = 0; + 1014 1014 $DGL 0,26 + 1015 1015 00183 CC0300 mov [hl+3],#00H ; buffer_fill,0 ;[INF] 3, 1 + 1016 1016 ; line 339 : p_buff = pool; + 1017 1017 $DGL 0,27 + 1018 1018 00186 R300000 movw ax,#loww (_pool) ;[INF] 3, 1 + 1019 1019 00189 BB movw [hl],ax ; p_buff ;[INF] 1, 1 + 1020 1020 ; line 340 : do + 1021 1021 0018A ?L0049: + 1022 1022 ; line 341 : { + 1023 1023 0018A ??bb03_firm_duplicate: + 1024 1024 ; line 342 : *p_buff = *p_rom; + 1025 1025 $DGL 0,30 + 1026 1026 0018A AC06 movw ax,[hl+6] ; p_rom ;[INF] 2, 1 + 1027 1027 0018C 14 movw de,ax ;[INF] 1, 1 + 1028 1028 0018D 8C08 mov a,[hl+8] ; p_rom ;[INF] 2, 1 + 1029 1029 0018F 9EFD mov ES,a ;[INF] 2, 1 + 1030 1030 00191 1189 mov a,ES:[de] ;[INF] 2, 2 + 1031 1031 00193 72 mov c,a ;[INF] 1, 1 + 1032 1032 00194 AB movw ax,[hl] ; p_buff ;[INF] 1, 1 + 1033 1033 00195 14 movw de,ax ;[INF] 1, 1 + 1034 1034 00196 62 mov a,c ;[INF] 1, 1 + 1035 1035 00197 99 mov [de],a ;[INF] 1, 1 + 1036 1036 ; line 343 : p_rom += 1; + 1037 1037 $DGL 0,31 + 1038 1038 00198 AC06 movw ax,[hl+6] ; p_rom ;[INF] 2, 1 + 1039 1039 0019A A1 incw ax ;[INF] 1, 1 + 1040 1040 0019B BC06 movw [hl+6],ax ; p_rom ;[INF] 2, 1 + 1041 1041 ; line 344 : p_buff += 1; + 1042 1042 $DGL 0,32 + 1043 1043 0019D 617900 incw [hl+0] ; p_buff ;[INF] 3, 2 + 1044 1044 ; line 345 : buffer_fill +=1; + 1045 1045 $DGL 0,33 + 1046 1046 001A0 615903 inc [hl+3] ; buffer_fill ;[INF] 3, 2 + 1047 1047 001A3 ??eb03_firm_duplicate: + 1048 1048 ; line 346 : } + 1049 1049 ; line 347 : while( buffer_fill != ( u8 ) SELF_UPDATE_BUFF_SIZE ) + 1050 1050 ; ; + 1051 1051 $DGL 0,35 + 1052 1052 001A3 8C03 mov a,[hl+3] ; buffer_fill ;[INF] 2, 1 + 1053 1053 001A5 D1 cmp0 a ;[INF] 1, 1 + 1054 1054 001A6 DFE2 bnz $?L0049 ;[INF] 2, 4 + 1055 1055 ; line 348 : + 1056 1056 ; line 349 : // 書き込み + 1057 1057 ; line 350 : if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOC + 1058 1058 ; K_SIZE + 1059 1059 ; line 351 : + + 1060 1060 ; line 352 : split_write_count * + 1061 1061 ; line 353 : SELF_UPDATE_BUFF_SIZE + 1062 1062 ; ), + 1063 1063 ; line 354 : ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE + 1064 1064 ; / SAM_WORD_SIZE ) ) + 1065 1065 ; line 355 : != FSL_OK ) + 1066 1066 $DGL 0,43 + 1067 1067 001A8 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 1068 1068 001AB C1 push ax ;[INF] 1, 1 + 1069 1069 001AC RFD2500 call !bs_S0060 ;[INF] 3, 3 + 1070 1070 001AF RFD1800 call !bs_F0061 ;[INF] 3, 3 + 1071 1071 001B2 C0 pop ax ;[INF] 1, 1 + 1072 1072 001B3 D2 cmp0 c ;[INF] 1, 1 + 1073 1073 001B4 DD06 bz $?L0052 ;[INF] 2, 4 + 1074 1074 ; line 356 : { + 1075 1075 001B6 ??bb04_firm_duplicate: + 1076 1076 ; line 357 : FSL_Close( ); + 1077 1077 $DGL 0,45 + 1078 1078 001B6 RFD4401 call !_FSL_Close ;[INF] 3, 3 + 1079 1079 ; line 358 : return ( ERR_ERR ); + 1080 1080 $DGL 0,46 + 1081 1081 001B9 E7 onew bc ;[INF] 1, 1 + 1082 1082 001BA EF10 br $?L0040 ;[INF] 2, 3 + 1083 1083 001BC ??eb04_firm_duplicate: + 1084 1084 ; line 359 : } + 1085 1085 001BC ?L0052: + 1086 1086 001BC ??eb02_firm_duplicate: + 1087 1087 ; line 360 : } + 1088 1088 $DGL 0,48 + 1089 1089 001BC 615904 inc [hl+4] ; split_write_count ;[INF] 3, 2 + 1090 1090 001BF EFBC br $?L0046 ;[INF] 2, 3 + 1091 1091 001C1 ?L0047: + 1092 1092 ; line 361 : + 1093 1093 ; line 362 : // 1ブロック書き込み完了。内部電圧チェックを行う + 1094 1094 ; line 363 : while( FSL_IVerify( target_block ) != FSL_OK ){ + 1095 1095 $DGL 0,51 + 1096 1096 001C1 RFD0F00 call !bs_F0063 ;[INF] 3, 3 + 1097 1097 001C4 DFFB bnz $?L0047 ;[INF] 2, 4 + 1098 1098 001C6 ??bb05_firm_duplicate: + 1099 1099 ; line 364 : // todo + 1100 1100 ; line 365 : ; + 1101 1101 001C6 ??eb05_firm_duplicate: + 1102 1102 ; line 366 : } + 1103 1103 001C6 ??eb00_firm_duplicate: + 1104 1104 ; line 367 : } + 1105 1105 $DGL 0,55 + 1106 1106 001C6 615905 inc [hl+5] ; target_block ;[INF] 3, 2 + 1107 1107 001C9 EF89 br $?L0041 ;[INF] 2, 3 + 1108 1108 001CB ?L0042: + 1109 1109 ; line 368 : return( ERR_SUCCESS ); + 1110 1110 $DGL 0,56 + 1111 1111 001CB F7 clrw bc ;[INF] 1, 1 + 1112 1112 ; line 369 : + 1113 1113 ; line 370 : } + 1114 1114 001CC ?L0040: + 1115 1115 $DGL 0,58 + 1116 1116 001CC ??ef_firm_duplicate: + 1117 1117 001CC 100A addw sp,#0AH ;[INF] 2, 1 + 1118 1118 001CE C6 pop hl ;[INF] 1, 1 + 1119 1119 001CF D7 ret ;[INF] 1, 6 + 1120 1120 001D0 ??ee_firm_duplicate: + 1121 1121 ; line 371 : + 1122 1122 ; line 372 : + 1123 1123 ; line 373 : + 1124 1124 ; line 374 : /* ======================================================== + 1125 1125 ; line 375 : ======================================================== */ + 1126 1126 ; line 376 : static err my_FSL_Init() + 1127 1127 ; line 377 : { + 1128 1128 001D0 _my_FSL_Init: + 1129 1129 $DGL 1,168 + 1130 1130 001D0 ??bf_my_FSL_Init: + 1131 1131 ; line 378 : RTCE = 0; + 1132 1132 $DGL 0,2 + 1133 1133 001D0 717B9D clr1 RTCC0.7 ;[INF] 3, 2 + 1134 1134 ; line 379 : + 1135 1135 ; line 380 : // 書き替え前準備 // + 1136 1136 ; line 381 : DI( ); + 1137 1137 $DGL 0,5 + 1138 1138 001D3 717BFA di ;[INF] 3, 4 + 1139 1139 ; line 382 : FSL_Open( ); // 割り込み禁止など + 1140 1140 $DGL 0,6 + 1141 1141 001D6 RFD2B01 call !_FSL_Open ;[INF] 3, 3 + 1142 1142 ; line 383 : + 1143 1143 ; line 384 : FSL_Init( pool ); // ライブラリ初期化。割り込み中断考慮 + 1144 1144 ; せず + 1145 1145 $DGL 0,8 + 1146 1146 001D9 R300000 movw ax,#loww (_pool) ;[INF] 3, 1 + 1147 1147 001DC RFD0000 call !_FSL_Init ;[INF] 3, 3 + 1148 1148 ; line 385 : FSL_ModeCheck( ); // ライトプロテクトチェック。失敗するこ + 1149 1149 ; とを考慮せず + 1150 1150 $DGL 0,9 + 1151 1151 001DF RFD0000 call !_FSL_ModeCheck ;[INF] 3, 3 + 1152 1152 ; line 386 : + 1153 1153 ; line 387 : return( ERR_SUCCESS ); + 1154 1154 $DGL 0,11 + 1155 1155 001E2 F7 clrw bc ;[INF] 1, 1 + 1156 1156 ; line 388 : } + 1157 1157 $DGL 0,12 + 1158 1158 001E3 ??ef_my_FSL_Init: + 1159 1159 001E3 D7 ret ;[INF] 1, 6 + 1160 1160 001E4 ??ee_my_FSL_Init: + 1161 1161 ; line 389 : + 1162 1162 ; line 390 : + 1163 1163 ; line 391 : task_status_immed tski_mcu_reset() + 1164 1164 ; line 392 : { + 1165 1165 001E4 _tski_mcu_reset: + 1166 1166 $DGL 1,174 + 1167 1167 001E4 ??bf_tski_mcu_reset: + 1168 1168 ; line 393 : // 普通に再起動 + 1169 1169 ; line 394 : my_FSL_Init(); + 1170 1170 $DGL 0,3 + 1171 1171 001E4 RFDD001 call !_my_FSL_Init ;[INF] 3, 3 + 1172 1172 ; line 395 : FSL_Close( ); + 1173 1173 $DGL 0,4 + 1174 1174 001E7 RFD4401 call !_FSL_Close ;[INF] 3, 3 + 1175 1175 ; line 396 : // FSL_SwapBootCluster(); + 1176 1176 ; line 397 : FSL_ForceReset(); // リセット + 1177 1177 $DGL 0,6 + 1178 1178 001EA RFD0000 call !_FSL_ForceReset ;[INF] 3, 3 + 1179 1179 ; line 398 : + 1180 1180 ; line 399 : // 保険？ // + 1181 1181 ; line 400 : WDTE = 0xAA; // WDTで再起動（テスト向け） + 1182 1182 $DGL 0,9 + 1183 1183 001ED CEABAA mov WDTE,#0AAH ; 170 ;[INF] 3, 1 + 1184 1184 ; line 401 : return( ERR_SUCCESS ); // no reach + 1185 1185 $DGL 0,10 + 1186 1186 001F0 F7 clrw bc ;[INF] 1, 1 + 1187 1187 ; line 402 : } + 1188 1188 $DGL 0,11 + 1189 1189 001F1 ??ef_tski_mcu_reset: + 1190 1190 001F1 D7 ret ;[INF] 1, 6 + 1191 1191 001F2 ??ee_tski_mcu_reset: + 1192 1192 + 1193 1193 ----- LDR_CODL CSEG + 1194 1194 + 1195 1195 ----- @@BASE CSEG BASE + 1196 1196 END + 1197 1197 + 1198 1198 + 1199 1199 ; *** Code Information *** + 1200 1200 ; + 1201 1201 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c + 1202 1202 ; + 1203 1203 ; $FUNC firm_update(97) + 1204 1204 ; bc=(void) + 1205 1205 ; CODE SIZE= 227 bytes, CLOCK_SIZE= 287 clocks, STACK_SIZE= 16 bytes + 1206 1206 ; + 1207 1207 ; $CALL my_FSL_Init(102) + 1208 1208 ; bc=(void) + 1209 1209 ; + 1210 1210 ; $CALL firm_duplicate(109) + 1211 1211 ; bc=(pointer:ax,bc, int:[sp+4]) + 1212 1212 ; + 1213 1213 ; $CALL FSL_Erase(118) + 1214 1214 ; bc=(unsigned int:ax) + 1215 1215 ; + 1216 1216 ; $CALL FSL_Erase(129) + 1217 1217 ; bc=(unsigned int:ax) + 1218 1218 ; + 1219 1219 ; $CALL WDT_Restart(140) + 1220 1220 ; void=(void) + 1221 1221 ; + 1222 1222 ; $CALL FSL_Write(162) + 1223 1223 ; bc=(unsigned long:ax,bc, int:[sp+4]) + 1224 1224 ; + 1225 1225 ; $CALL FSL_SwapBootCluster(167) + 1226 1226 ; void=(void) + 1227 1227 ; + 1228 1228 ; $CALL FSL_IVerify(174) + 1229 1229 ; bc=(unsigned int:ax) + 1230 1230 ; + 1231 1231 ; $CALL FSL_InvertBootFlag(199) + 1232 1232 ; bc=(void) + 1233 1233 ; + 1234 1234 ; $CALL FSL_SwapBootCluster(200) + 1235 1235 ; void=(void) + 1236 1236 ; + 1237 1237 ; $CALL FSL_SwapBootCluster(210) + 1238 1238 ; void=(void) + 1239 1239 ; + 1240 1240 ; $FUNC firm_restore(227) + 1241 1241 ; bc=(void) + 1242 1242 ; CODE SIZE= 20 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 6 bytes + 1243 1243 ; + 1244 1244 ; $CALL my_FSL_Init(228) + 1245 1245 ; bc=(void) + 1246 1246 ; + 1247 1247 ; $CALL firm_duplicate(235) + 1248 1248 ; bc=(pointer:ax,bc, int:[sp+4]) + 1249 1249 ; + 1250 1250 ; $CALL FSL_SwapBootCluster(242) + 1251 1251 ; void=(void) + 1252 1252 ; + 1253 1253 ; $FUNC FSL_Open(252) + 1254 1254 ; void=(void) + 1255 1255 ; CODE SIZE= 25 bytes, CLOCK_SIZE= 21 clocks, STACK_SIZE= 0 bytes + 1256 1256 ; + 1257 1257 ; $FUNC FSL_Close(287) + 1258 1258 ; void=(void) + 1259 1259 ; CODE SIZE= 4 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes + 1260 1260 ; + 1261 1261 ; $FUNC firm_duplicate(313) + 1262 1262 ; bc=(pointer p_rom:ax,bc, unsigned char block_dest:[sp+4]) + 1263 1263 ; CODE SIZE= 136 bytes, CLOCK_SIZE= 161 clocks, STACK_SIZE= 20 bytes + 1264 1264 ; + 1265 1265 ; $CALL WDT_Restart(322) + 1266 1266 ; void=(void) + 1267 1267 ; + 1268 1268 ; $CALL FSL_BlankCheck(324) + 1269 1269 ; bc=(unsigned int:ax) + 1270 1270 ; + 1271 1271 ; $CALL FSL_Erase(326) + 1272 1272 ; bc=(unsigned int:ax) + 1273 1273 ; + 1274 1274 ; $CALL FSL_Write(355) + 1275 1275 ; bc=(unsigned long:ax,bc, int:[sp+4]) + 1276 1276 ; + 1277 1277 ; $CALL FSL_Close(357) + 1278 1278 ; void=(void) + 1279 1279 ; + 1280 1280 ; $CALL FSL_IVerify(363) + 1281 1281 ; bc=(unsigned int:ax) + 1282 1282 ; + 1283 1283 ; $FUNC my_FSL_Init(377) + 1284 1284 ; bc=(void) + 1285 1285 ; CODE SIZE= 20 bytes, CLOCK_SIZE= 23 clocks, STACK_SIZE= 4 bytes + 1286 1286 ; + 1287 1287 ; $CALL FSL_Open(382) + 1288 1288 ; void=(void) + 1289 1289 ; + 1290 1290 ; $CALL FSL_Init(384) + 1291 1291 ; bc=(pointer:ax) + 1292 1292 ; + 1293 1293 ; $CALL FSL_ModeCheck(385) + 1294 1294 ; bc=(void) + 1295 1295 ; + 1296 1296 ; $FUNC tski_mcu_reset(392) + 1297 1297 ; bc=(void) + 1298 1298 ; CODE SIZE= 14 bytes, CLOCK_SIZE= 17 clocks, STACK_SIZE= 4 bytes + 1299 1299 ; + 1300 1300 ; $CALL my_FSL_Init(394) + 1301 1301 ; bc=(void) + 1302 1302 ; + 1303 1303 ; $CALL FSL_Close(395) + 1304 1304 ; void=(void) + 1305 1305 ; + 1306 1306 ; $CALL FSL_ForceReset(397) + 1307 1307 ; void=(void) + 1308 1308 + 1309 1309 ; Target chip : uPD79F0104 + 1310 1310 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00002H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00000H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H LDR_CNSL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 001F2H LDR_CODE +00000 00000H LDR_CODL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/self_flash.rel b/branches/0.10(X3)/self_flash.rel new file mode 100644 index 0000000..802e73b Binary files /dev/null and b/branches/0.10(X3)/self_flash.rel differ diff --git a/branches/0.10(X3)/sw.c b/branches/0.10(X3)/sw.c new file mode 100644 index 0000000..ea60fdf --- /dev/null +++ b/branches/0.10(X3)/sw.c @@ -0,0 +1,189 @@ +#pragma SFR +#pragma NOP +#pragma HALT +#pragma STOP + +#include "incs.h" + +#include "i2c_twl.h" +#include "i2c_ctr.h" +#include "led.h" +#include "accero.h" +#include "pm.h" +#include "rtc.h" + + + +//========================================================= +#define INTERVAL_TSK_SW 16 +#define CLICK_THRESHOLD 1 +#define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW ) + + + +//========================================================= +u8 SW_pow_count, SW_home_count, SW_wifi_count; +bit SW_pow_mask, SW_home_mask, SW_wifi_mask; + +bit SW_HOME_n; + + +//========================================================= +// 押した時間を数える。押しっぱなしでも0に戻らない +// maskが非0の時は、一度離すまで無視する +#define count_sw_n( sw, counter, mask ) \ + { \ + if( sw ){ \ + mask = 0; \ + counter = 0; \ + }else{ \ + if( mask != 0 ){ \ + counter = 0; \ + }else{ \ + counter += 1; \ + if( counter == 0 ) counter = 255; \ + } \ + } \ + } + + + +/* ======================================================== + スイッチの監視 + 　チャタリングをはねたり、長押しや、押したトリガなどの検出など + ======================================================== */ +void tsk_sw( ) +{ + static u8 cnt_force_off = 0; + static u8 task_interval = 0; + + switch ( system_status.pwr_state ) + { + case ( OFF_TRIG ): + SW_pow_count = 0; + SW_wifi_count = 0; + SW_home_count = 0; + cnt_force_off = 0; + break; + + case ( ON_TRIG ): + // 電源投入 + SW_pow_mask = 1; + SW_home_mask = 1; + SW_wifi_mask = 1; + break; + } + + if( task_interval-- != 0 ) + { + return; + } + else + { + task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TICK ); + } + + + switch ( system_status.pwr_state ) + { + case ( ON ): + case ( SLEEP ): + case ( BT_CHARGE ): + case ( OFF ): + // 電源スイッチの監視 // + if( SW_POW_n ) + { + if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_count <= HOLD_THREASHOLD ) ) + { +#ifdef _SW_HOME_ENABLE_ + set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK ); +#else + set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); +#endif + } + } + else if( SW_pow_count == HOLD_THREASHOLD ) + { +#ifdef _SW_HOME_ENABLE_ + set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD ); +#else + set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); +#endif + } + else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) ) + { // todo + vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED; + system_status.pwr_state = OFF_TRIG; + renge_task_interval_run_force = 1; + } + + // 電源OFF割り込みを入れたが… + if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0 ) + { + cnt_force_off += 1; + if( cnt_force_off >= 13 ) + { // …返事がない。強制的に切る。 + vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED; + system_status.pwr_state = OFF_TRIG; + renge_task_interval_run_force = 1; + } + } + else + { + cnt_force_off = 0; + } + + // HOME スイッチ // + switch( system_status.model ) + { +#ifdef _MODEL_CTR_ + case( MODEL_JIKKI ): + SW_HOME_n = SW_HOME_n_JIKKI; + break; +#endif + case( MODEL_TS_BOARD ): + case( MODEL_SHIROBAKO ): + SW_HOME_n = SW_HOME_n_TSBOARD; + break; + default: + SW_HOME_n = 1; + } + + if( SW_HOME_n ) + { + if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home_count <= HOLD_THREASHOLD ) ) + { + set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); + } + } + else if( SW_home_count == HOLD_THREASHOLD ) + { + set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); + } + + // wifi sw // + if( SW_wifi_count == CLICK_THRESHOLD ) + { + set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK ); + } + + break; + } + + // ボタン押し時間のカウント +/* +if( ( system_status.pwr_state == ON ) + || ( system_status.pwr_state == OFF ) + || ( system_status.pwr_state == BT_CHARGE ) ) + */ + + { + count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask ); +#ifdef _SW_HOME_ENABLE_ + count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask ); +#endif + count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask ); + } + + return; +} diff --git a/branches/0.10(X3)/sw.h b/branches/0.10(X3)/sw.h new file mode 100644 index 0000000..f3bea21 --- /dev/null +++ b/branches/0.10(X3)/sw.h @@ -0,0 +1,7 @@ +#ifndef _sw_ +#define _sw_ + +extern u8 SW_pow_count, SW_home_count, SW_wifi_count; +extern bit SW_pow_mask, SW_home_mask, SW_wifi_mask; + +#endif diff --git a/branches/0.10(X3)/sw.prn b/branches/0.10(X3)/sw.prn new file mode 100644 index 0000000..9343454 --- /dev/null +++ b/branches/0.10(X3)/sw.prn @@ -0,0 +1,902 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\sw.asm +Para-file: +In-file: inter_asm\sw.asm +Obj-file: sw.rel +Prn-file: sw.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no sw.c + 6 6 ; In-file : sw.c + 7 7 ; Asm-file : inter_asm\sw.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0CDH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, sw.c + 18 18 $DGS MOD_NAM, sw, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H + 82 82 $DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H + 83 83 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 84 84 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 85 85 $DGS GLV_SYM, _tsk_sw, U, U, 01H, 026H, 01H, 02H + 86 86 $DGS AUX_FUN, 00H, U, U, 0CDH, 00H, 00H + 87 87 $DGS BEG_FUN, ??bf_tsk_sw, U, U, 00H, 065H, 01H, 00H + 88 88 $DGS AUX_BEG, 038H, 02H, 04BH + 89 89 $DGS STA_SYM, _cnt_force_off, ?L0003, U, 0CH, 03H, 00H, 00H + 90 90 $DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H + 91 91 $DGS BEG_BLK, ??bb00_tsk_sw, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_BEG, 06H, 00H, 04FH + 93 93 $DGS END_BLK, ??eb00_tsk_sw, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_END, 014H + 95 95 $DGS BEG_BLK, ??bb01_tsk_sw, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_BEG, 017H, 00H, 053H + 97 97 $DGS END_BLK, ??eb01_tsk_sw, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_END, 019H + 99 99 $DGS BEG_BLK, ??bb02_tsk_sw, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_BEG, 01BH, 00H, 057H + 101 101 $DGS END_BLK, ??eb02_tsk_sw, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_END, 01DH + 103 103 $DGS BEG_BLK, ??bb03_tsk_sw, U, U, 00H, 064H, 01H, 00H + 104 104 $DGS AUX_BEG, 021H, 00H, 059H + 105 105 $DGS BEG_BLK, ??bb04_tsk_sw, U, U, 00H, 064H, 01H, 00H + 106 106 $DGS AUX_BEG, 028H, 00H, 05BH + 107 107 $DGS BEG_BLK, ??bb05_tsk_sw, U, U, 00H, 064H, 01H, 00H + 108 108 $DGS AUX_BEG, 02AH, 00H, 061H + 109 109 $DGS END_BLK, ??eb05_tsk_sw, U, U, 00H, 064H, 01H, 00H + 110 110 $DGS AUX_END, 030H + 111 111 $DGS END_BLK, ??eb04_tsk_sw, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_END, 031H + 113 113 $DGS BEG_BLK, ??bb06_tsk_sw, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_BEG, 033H, 00H, 065H + 115 115 $DGS END_BLK, ??eb06_tsk_sw, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_END, 039H + 117 117 $DGS BEG_BLK, ??bb07_tsk_sw, U, U, 00H, 064H, 01H, 00H + 118 118 $DGS AUX_BEG, 03BH, 00H, 069H + 119 119 $DGS END_BLK, ??eb07_tsk_sw, U, U, 00H, 064H, 01H, 00H + 120 120 $DGS AUX_END, 03FH + 121 121 $DGS BEG_BLK, ??bb08_tsk_sw, U, U, 00H, 064H, 01H, 00H + 122 122 $DGS AUX_BEG, 043H, 00H, 06BH + 123 123 $DGS BEG_BLK, ??bb09_tsk_sw, U, U, 00H, 064H, 01H, 00H + 124 124 $DGS AUX_BEG, 046H, 00H, 071H + 125 125 $DGS END_BLK, ??eb09_tsk_sw, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_END, 04AH + 127 127 $DGS END_BLK, ??eb08_tsk_sw, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_END, 04BH + 129 129 $DGS BEG_BLK, ??bb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_BEG, 04DH, 00H, 075H + 131 131 $DGS END_BLK, ??eb0A_tsk_sw, U, U, 00H, 064H, 01H, 00H + 132 132 $DGS AUX_END, 04FH + 133 133 $DGS BEG_BLK, ??bb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H + 134 134 $DGS AUX_BEG, 053H, 00H, 079H + 135 135 $DGS END_BLK, ??eb0B_tsk_sw, U, U, 00H, 064H, 01H, 00H + 136 136 $DGS AUX_END, 05FH + 137 137 $DGS BEG_BLK, ??bb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_BEG, 062H, 00H, 07BH + 139 139 $DGS BEG_BLK, ??bb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H + 140 140 $DGS AUX_BEG, 064H, 00H, 081H + 141 141 $DGS END_BLK, ??eb0D_tsk_sw, U, U, 00H, 064H, 01H, 00H + 142 142 $DGS AUX_END, 066H + 143 143 $DGS END_BLK, ??eb0C_tsk_sw, U, U, 00H, 064H, 01H, 00H + 144 144 $DGS AUX_END, 067H + 145 145 $DGS BEG_BLK, ??bb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H + 146 146 $DGS AUX_BEG, 069H, 00H, 085H + 147 147 $DGS END_BLK, ??eb0E_tsk_sw, U, U, 00H, 064H, 01H, 00H + 148 148 $DGS AUX_END, 06BH + 149 149 $DGS BEG_BLK, ??bb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H + 150 150 $DGS AUX_BEG, 06FH, 00H, 08BH + 151 151 $DGS END_BLK, ??eb0F_tsk_sw, U, U, 00H, 064H, 01H, 00H + 152 152 $DGS AUX_END, 071H + 153 153 $DGS END_BLK, ??eb03_tsk_sw, U, U, 00H, 064H, 01H, 00H + 154 154 $DGS AUX_END, 074H + 155 155 $DGS BEG_BLK, ??bb10_tsk_sw, U, U, 00H, 064H, 01H, 00H + 156 156 $DGS AUX_BEG, 07DH, 00H, 08DH + 157 157 $DGS BEG_BLK, ??bb11_tsk_sw, U, U, 00H, 064H, 01H, 00H + 158 158 $DGS AUX_BEG, 07EH, 00H, 08FH + 159 159 $DGS BEG_BLK, ??bb12_tsk_sw, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_BEG, 07EH, 00H, 093H + 161 161 $DGS END_BLK, ??eb12_tsk_sw, U, U, 00H, 064H, 01H, 00H + 162 162 $DGS AUX_END, 07EH + 163 163 $DGS BEG_BLK, ??bb13_tsk_sw, U, U, 00H, 064H, 01H, 00H + 164 164 $DGS AUX_BEG, 07EH, 00H, 095H + 165 165 $DGS BEG_BLK, ??bb14_tsk_sw, U, U, 00H, 064H, 01H, 00H + 166 166 $DGS AUX_BEG, 07EH, 00H, 099H + 167 167 $DGS END_BLK, ??eb14_tsk_sw, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_END, 07EH + 169 169 $DGS BEG_BLK, ??bb15_tsk_sw, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_BEG, 07EH, 00H, 0A1H + 171 171 $DGS END_BLK, ??eb15_tsk_sw, U, U, 00H, 064H, 01H, 00H + 172 172 $DGS AUX_END, 07EH + 173 173 $DGS END_BLK, ??eb13_tsk_sw, U, U, 00H, 064H, 01H, 00H + 174 174 $DGS AUX_END, 07EH + 175 175 $DGS END_BLK, ??eb11_tsk_sw, U, U, 00H, 064H, 01H, 00H + 176 176 $DGS AUX_END, 07EH + 177 177 $DGS BEG_BLK, ??bb16_tsk_sw, U, U, 00H, 064H, 01H, 00H + 178 178 $DGS AUX_BEG, 080H, 00H, 0A3H + 179 179 $DGS BEG_BLK, ??bb17_tsk_sw, U, U, 00H, 064H, 01H, 00H + 180 180 $DGS AUX_BEG, 080H, 00H, 0A7H + 181 181 $DGS END_BLK, ??eb17_tsk_sw, U, U, 00H, 064H, 01H, 00H + 182 182 $DGS AUX_END, 080H + 183 183 $DGS BEG_BLK, ??bb18_tsk_sw, U, U, 00H, 064H, 01H, 00H + 184 184 $DGS AUX_BEG, 080H, 00H, 0A9H + 185 185 $DGS BEG_BLK, ??bb19_tsk_sw, U, U, 00H, 064H, 01H, 00H + 186 186 $DGS AUX_BEG, 080H, 00H, 0ADH + 187 187 $DGS END_BLK, ??eb19_tsk_sw, U, U, 00H, 064H, 01H, 00H + 188 188 $DGS AUX_END, 080H + 189 189 $DGS BEG_BLK, ??bb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H + 190 190 $DGS AUX_BEG, 080H, 00H, 0B5H + 191 191 $DGS END_BLK, ??eb1A_tsk_sw, U, U, 00H, 064H, 01H, 00H + 192 192 $DGS AUX_END, 080H + 193 193 $DGS END_BLK, ??eb18_tsk_sw, U, U, 00H, 064H, 01H, 00H + 194 194 $DGS AUX_END, 080H + 195 195 $DGS END_BLK, ??eb16_tsk_sw, U, U, 00H, 064H, 01H, 00H + 196 196 $DGS AUX_END, 080H + 197 197 $DGS BEG_BLK, ??bb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H + 198 198 $DGS AUX_BEG, 082H, 00H, 0B7H + 199 199 $DGS BEG_BLK, ??bb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H + 200 200 $DGS AUX_BEG, 082H, 00H, 0BBH + 201 201 $DGS END_BLK, ??eb1C_tsk_sw, U, U, 00H, 064H, 01H, 00H + 202 202 $DGS AUX_END, 082H + 203 203 $DGS BEG_BLK, ??bb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H + 204 204 $DGS AUX_BEG, 082H, 00H, 0BDH + 205 205 $DGS BEG_BLK, ??bb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_BEG, 082H, 00H, 0C1H + 207 207 $DGS END_BLK, ??eb1E_tsk_sw, U, U, 00H, 064H, 01H, 00H + 208 208 $DGS AUX_END, 082H + 209 209 $DGS BEG_BLK, ??bb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H + 210 210 $DGS AUX_BEG, 082H, 00H, 00H + 211 211 $DGS END_BLK, ??eb1F_tsk_sw, U, U, 00H, 064H, 01H, 00H + 212 212 $DGS AUX_END, 082H + 213 213 $DGS END_BLK, ??eb1D_tsk_sw, U, U, 00H, 064H, 01H, 00H + 214 214 $DGS AUX_END, 082H + 215 215 $DGS END_BLK, ??eb1B_tsk_sw, U, U, 00H, 064H, 01H, 00H + 216 216 $DGS AUX_END, 082H + 217 217 $DGS END_BLK, ??eb10_tsk_sw, U, U, 00H, 064H, 01H, 00H + 218 218 $DGS AUX_END, 083H + 219 219 $DGS END_FUN, ??ef_tsk_sw, U, U, 00H, 065H, 01H, 00H + 220 220 $DGS AUX_END, 086H + 221 221 $DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 026H, 00H, 00H + 222 222 $DGS GLV_SYM, _SW_home_count, U, U, 0CH, 026H, 00H, 00H + 223 223 $DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 026H, 00H, 00H + 224 224 $DGS GLV_SYM, _SW_pow_mask, U, U, 034CH, 027H, 00H, 00H + 225 225 $DGS GLV_SYM, _SW_home_mask, U, U, 034CH, 027H, 00H, 00H + 226 226 $DGS GLV_SYM, _SW_wifi_mask, U, U, 034CH, 027H, 00H, 00H + 227 227 $DGS GLV_SYM, _SW_HOME_n, U, U, 034CH, 027H, 00H, 00H + 228 228 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 229 229 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 230 230 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 231 231 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 232 232 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 233 233 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 234 234 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H + 235 235 + 236 236 EXTRN _set_irq + 237 237 EXTRN _system_status + 238 238 EXTRN _vreg_ctr + 239 239 EXTBIT _renge_task_interval_run_force + 240 240 PUBLIC _SW_pow_count + 241 241 PUBLIC _SW_home_count + 242 242 PUBLIC _SW_wifi_count + 243 243 PUBLIC _SW_pow_mask + 244 244 PUBLIC _SW_home_mask + 245 245 PUBLIC _SW_wifi_mask + 246 246 PUBLIC _SW_HOME_n + 247 247 PUBLIC _tsk_sw + 248 248 + 249 249 ----- @@BITS BSEG + 250 250 00000.0 _SW_pow_mask DBIT + 251 251 00000.1 _SW_home_mask DBIT + 252 252 00000.2 _SW_wifi_mask DBIT + 253 253 00000.3 _SW_HOME_n DBIT + 254 254 + 255 255 ----- @@CNST CSEG MIRRORP + 256 256 00000 01 _lpf_coeff: DB 01H ; 1 + 257 257 00001 02 DB 02H ; 2 + 258 258 00002 02 DB 02H ; 2 + 259 259 00003 03 DB 03H ; 3 + 260 260 00004 03 DB 03H ; 3 + 261 261 00005 02 DB 02H ; 2 + 262 262 00006 00 DB 00H ; 0 + 263 263 00007 FE DB 0FEH ; 254 + 264 264 00008 FB DB 0FBH ; 251 + 265 265 00009 F7 DB 0F7H ; 247 + 266 266 0000A F3 DB 0F3H ; 243 + 267 267 0000B F0 DB 0F0H ; 240 + 268 268 0000C F0 DB 0F0H ; 240 + 269 269 0000D F3 DB 0F3H ; 243 + 270 270 0000E FA DB 0FAH ; 250 + 271 271 0000F 04 DB 04H ; 4 + 272 272 00010 12 DB 012H ; 18 + 273 273 00011 25 DB 025H ; 37 + 274 274 00012 38 DB 038H ; 56 + 275 275 00013 4D DB 04DH ; 77 + 276 276 00014 5F DB 05FH ; 95 + 277 277 00015 6E DB 06EH ; 110 + 278 278 00016 77 DB 077H ; 119 + 279 279 00017 7A DB 07AH ; 122 + 280 280 00018 77 DB 077H ; 119 + 281 281 00019 6E DB 06EH ; 110 + 282 282 0001A 5F DB 05FH ; 95 + 283 283 0001B 4D DB 04DH ; 77 + 284 284 0001C 38 DB 038H ; 56 + 285 285 0001D 25 DB 025H ; 37 + 286 286 0001E 12 DB 012H ; 18 + 287 287 0001F 04 DB 04H ; 4 + 288 288 00020 FA DB 0FAH ; 250 + 289 289 00021 F3 DB 0F3H ; 243 + 290 290 00022 F0 DB 0F0H ; 240 + 291 291 00023 F0 DB 0F0H ; 240 + 292 292 00024 F3 DB 0F3H ; 243 + 293 293 00025 F7 DB 0F7H ; 247 + 294 294 00026 FB DB 0FBH ; 251 + 295 295 00027 FE DB 0FEH ; 254 + 296 296 00028 00 DB 00H ; 0 + 297 297 00029 02 DB 02H ; 2 + 298 298 0002A 03 DB 03H ; 3 + 299 299 0002B 03 DB 03H ; 3 + 300 300 0002C 02 DB 02H ; 2 + 301 301 0002D 02 DB 02H ; 2 + 302 302 0002E 01 DB 01H ; 1 + 303 303 0002F 00 DB (1) + 304 304 + 305 305 ----- @@R_INIT CSEG UNIT64KP + 306 306 00000 00 DB 00H ; 0 + 307 307 00001 00 DB 00H ; 0 + 308 308 + 309 309 ----- @@INIT DSEG BASEP + 310 310 00000 ?L0003: DS (1) + 311 311 00001 ?L0004: DS (1) + 312 312 + 313 313 ----- @@DATA DSEG BASEP + 314 314 00000 _SW_pow_count: DS (1) + 315 315 00001 _SW_home_count: DS (1) + 316 316 00002 _SW_wifi_count: DS (1) + 317 317 00003 DS (1) + 318 318 + 319 319 ----- @@R_INIS CSEG UNIT64KP + 320 320 + 321 321 ----- @@INIS DSEG SADDRP + 322 322 + 323 323 ----- @@DATS DSEG SADDRP + 324 324 + 325 325 ----- @@CNSTL CSEG PAGE64KP + 326 326 + 327 327 ----- @@RLINIT CSEG UNIT64KP + 328 328 + 329 329 ----- @@INITL DSEG UNIT64KP + 330 330 + 331 331 ----- @@DATAL DSEG UNIT64KP + 332 332 + 333 333 ----- @@CALT CSEG CALLT0 + 334 334 + 335 335 ; Sub-Routines created by CC78K0R + 336 336 + 337 337 ----- ROM_CODE CSEG BASE + 338 338 00000 bs_F0060: + 339 339 00000 C1 push ax ;[INF] 1, 1 + 340 340 00001 5010 mov x,#010H ; 16 ;[INF] 2, 1 + 341 341 00003 RFD0000 call !_set_irq ;[INF] 3, 3 + 342 342 00006 C0 pop ax ;[INF] 1, 1 + 343 343 00007 D7 ret ;[INF] 1, 6 + 344 344 00008 es_F0060: + 345 345 + 346 346 ; *** Sub-Routine Information *** + 347 347 ; + 348 348 ; $SUB bs_F0060 + 349 349 ; CODE SIZE= 8 bytes + 350 350 + 351 351 ; End of Sub-Routines + 352 352 + 353 353 ; line 1 : #pragma SFR + 354 354 ; line 2 : #pragma NOP + 355 355 ; line 3 : #pragma HALT + 356 356 ; line 4 : #pragma STOP + 357 357 ; line 5 : + 358 358 ; line 6 : #include "incs.h" + 359 359 ; line 7 : + 360 360 ; line 8 : #include "i2c_twl.h" + 361 361 ; line 9 : #include "i2c_ctr.h" + 362 362 ; line 10 : #include "led.h" + 363 363 ; line 11 : #include "accero.h" + 364 364 ; line 12 : #include "pm.h" + 365 365 ; line 13 : #include "rtc.h" + 366 366 ; line 14 : + 367 367 ; line 15 : + 368 368 ; line 16 : + 369 369 ; line 17 : //========================================================= + 370 370 ; line 18 : #define INTERVAL_TSK_SW 16 + 371 371 ; line 19 : #define CLICK_THRESHOLD 1 + 372 372 ; line 20 : #define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW ) + 373 373 ; line 21 : + 374 374 ; line 22 : + 375 375 ; line 23 : + 376 376 ; line 24 : //========================================================= + 377 377 ; line 25 : u8 SW_pow_count, SW_home_count, SW_wifi_count; + 378 378 ; line 26 : bit SW_pow_mask, SW_home_mask, SW_wifi_mask; + 379 379 ; line 27 : + 380 380 ; line 28 : bit SW_HOME_n; + 381 381 ; line 29 : + 382 382 ; line 30 : + 383 383 ; line 31 : //========================================================= + 384 384 ; line 32 : // 押した時間を数える。押しっぱなしでも0に戻らない + 385 385 ; line 33 : // maskが非0の時は、一度離すまで無視する + 386 386 ; line 34 : #define count_sw_n( sw, counter, mask ) \ + 387 387 ; line 35 : { \ + 388 388 ; line 36 : if( sw ){ \ + 389 389 ; line 37 : mask = 0; \ + 390 390 ; line 38 : counter = 0; \ + 391 391 ; line 39 : }else{ \ + 392 392 ; line 40 : if( mask != 0 ){ \ + 393 393 ; line 41 : counter = 0; \ + 394 394 ; line 42 : }else{ \ + 395 395 ; line 43 : counter += 1; \ + 396 396 ; line 44 : if( counter == 0 ) counter = 255; \ + 397 397 ; line 45 : } \ + 398 398 ; line 46 : } \ + 399 399 ; line 47 : } + 400 400 ; line 48 : + 401 401 ; line 49 : + 402 402 ; line 50 : + 403 403 ; line 51 : /* ======================================================== + 404 404 ; line 52 : スイッチの監視 + 405 405 ; line 53 : 　チャタリングをはねたり、長押しや、押したトリガなどの検出など + 406 406 ; line 54 : ======================================================== */ + 407 407 ; line 55 : void tsk_sw( ) + 408 408 ; line 56 : { + 409 409 + 410 410 ----- ROM_CODE CSEG BASE + 411 411 00008 _tsk_sw: + 412 412 $DGL 1,69 + 413 413 00008 C7 push hl ;[INF] 1, 1 + 414 414 00009 ??bf_tsk_sw: + 415 415 ; line 57 : static u8 cnt_force_off = 0; + 416 416 ; line 58 : static u8 task_interval = 0; + 417 417 ; line 59 : + 418 418 ; line 60 : switch ( system_status.pwr_state ) + 419 419 $DGL 0,5 + 420 420 00009 R8F0000 mov a,!_system_status ;[INF] 3, 1 + 421 421 0000C 318F sarw ax,8 ;[INF] 2, 1 + 422 422 0000E F7 clrw bc ;[INF] 1, 1 + 423 423 0000F 23 subw ax,bc ;[INF] 1, 1 + 424 424 00010 DD07 bz $?L0006 ;[INF] 2, 4 + 425 425 00012 240200 subw ax,#02H ; 2 ;[INF] 3, 1 + 426 426 00015 DD10 bz $?L0007 ;[INF] 2, 4 + 427 427 00017 EF17 br $?L0005 ;[INF] 2, 3 + 428 428 ; line 61 : { + 429 429 00019 ??bb00_tsk_sw: + 430 430 ; line 62 : case ( OFF_TRIG ): + 431 431 00019 ?L0006: + 432 432 ; line 63 : SW_pow_count = 0; + 433 433 $DGL 0,8 + 434 434 00019 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 + 435 435 ; line 64 : SW_wifi_count = 0; + 436 436 $DGL 0,9 + 437 437 0001C RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 + 438 438 ; line 65 : SW_home_count = 0; + 439 439 $DGL 0,10 + 440 440 0001F RF50100 clrb !_SW_home_count ;[INF] 3, 1 + 441 441 ; line 66 : cnt_force_off = 0; + 442 442 $DGL 0,11 + 443 443 00022 RF50000 clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 + 444 444 ; line 67 : break; + 445 445 $DGL 0,12 + 446 446 00025 EF09 br $?L0005 ;[INF] 2, 3 + 447 447 ; line 68 : + 448 448 ; line 69 : case ( ON_TRIG ): + 449 449 00027 ?L0007: + 450 450 ; line 70 : // 電源投入 + 451 451 ; line 71 : SW_pow_mask = 1; + 452 452 $DGL 0,16 + 453 453 00027 R710200 set1 _SW_pow_mask ;[INF] 3, 2 + 454 454 ; line 72 : SW_home_mask = 1; + 455 455 $DGL 0,17 + 456 456 0002A R711200 set1 _SW_home_mask ;[INF] 3, 2 + 457 457 ; line 73 : SW_wifi_mask = 1; + 458 458 $DGL 0,18 + 459 459 0002D R712200 set1 _SW_wifi_mask ;[INF] 3, 2 + 460 460 ; line 74 : break; + 461 461 00030 ??eb00_tsk_sw: + 462 462 ; line 75 : } + 463 463 00030 ?L0005: + 464 464 ; line 76 : + 465 465 ; line 77 : if( task_interval-- != 0 ) + 466 466 $DGL 0,22 + 467 467 00030 R8F0100 mov a,!?L0004 ; task_interval ;[INF] 3, 1 + 468 468 00033 RB00100 dec !?L0004 ; task_interval ;[INF] 3, 2 + 469 469 00036 D1 cmp0 a ;[INF] 1, 1 + 470 470 00037 61E8 skz ;[INF] 2, 1 + 471 471 00039 RED6501 br !?L0058 ;[INF] 3, 3 + 472 472 ; line 78 : { + 473 473 0003C ??bb01_tsk_sw: + 474 474 ; line 79 : return; + 475 475 0003C ??eb01_tsk_sw: + 476 476 ; line 80 : } + 477 477 ; line 81 : else + 478 478 ; line 82 : { + 479 479 0003C ??bb02_tsk_sw: + 480 480 ; line 83 : task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TIC + 481 481 ; K ); + 482 482 $DGL 0,28 + 483 483 0003C RCF010008 mov !?L0004,#08H ; task_interval,8 ;[INF] 4, 1 + 484 484 00040 ??eb02_tsk_sw: + 485 485 ; line 84 : } + 486 486 ; line 85 : + 487 487 ; line 86 : + 488 488 ; line 87 : switch ( system_status.pwr_state ) + 489 489 $DGL 0,32 + 490 490 00040 R8F0000 mov a,!_system_status ;[INF] 3, 1 + 491 491 00043 318F sarw ax,8 ;[INF] 2, 1 + 492 492 00045 E7 onew bc ;[INF] 1, 1 + 493 493 00046 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 494 494 00049 23 subw ax,bc ;[INF] 1, 1 + 495 495 0004A DD0A bz $?L0013 ;[INF] 2, 4 + 496 496 0004C 25 subw ax,de ;[INF] 1, 1 + 497 497 0004D DD07 bz $?L0013 ;[INF] 2, 4 + 498 498 0004F 25 subw ax,de ;[INF] 1, 1 + 499 499 00050 23 subw ax,bc ;[INF] 1, 1 + 500 500 00051 61F3 sknh ;[INF] 2, 1 + 501 501 00053 RED0201 br !?L0012 ;[INF] 3, 3 + 502 502 ; line 88 : { + 503 503 00056 ??bb03_tsk_sw: + 504 504 ; line 89 : case ( ON ): + 505 505 00056 ?L0013: + 506 506 ; line 90 : case ( SLEEP ): + 507 507 ; line 91 : case ( BT_CHARGE ): + 508 508 ; line 92 : case ( OFF ): + 509 509 ; line 93 : // 電源スイッチの監視 // + 510 510 ; line 94 : if( SW_POW_n ) + 511 511 $DGL 0,39 + 512 512 00056 31340712 bf P7.3,$?L0016 ;[INF] 4, 5 + 513 513 ; line 95 : { + 514 514 0005A ??bb04_tsk_sw: + 515 515 ; line 96 : if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_c + 516 516 ; ount <= HOLD_THREASHOLD ) ) + 517 517 $DGL 0,41 + 518 518 0005A R40000002 cmp !_SW_pow_count,#02H ; 2 ;[INF] 4, 1 + 519 519 0005E DC29 bc $?L0022 ;[INF] 2, 4 + 520 520 00060 R40000026 cmp !_SW_pow_count,#026H ; 38 ;[INF] 4, 1 + 521 521 00064 DE23 bnc $?L0022 ;[INF] 2, 4 + 522 522 ; line 97 : { + 523 523 00066 ??bb05_tsk_sw: + 524 524 ; line 98 : #ifdef _SW_HOME_ENABLE_ + 525 525 ; line 99 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK ); + 526 526 $DGL 0,44 + 527 527 00066 E6 onew ax ;[INF] 1, 1 + 528 528 00067 RFD0000 call !bs_F0060 ;[INF] 3, 3 + 529 529 0006A ??eb05_tsk_sw: + 530 530 ; line 100 : #else + 531 531 ; line 101 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); + 532 532 ; line 102 : #endif + 533 533 ; line 103 : } + 534 534 ; line 104 : } + 535 535 $DGL 0,49 + 536 536 0006A ??eb04_tsk_sw: + 537 537 0006A EF1D br $?L0022 ;[INF] 2, 3 + 538 538 0006C ?L0016: + 539 539 ; line 105 : else if( SW_pow_count == HOLD_THREASHOLD ) + 540 540 $DGL 0,50 + 541 541 0006C R40000025 cmp !_SW_pow_count,#025H ; 37 ;[INF] 4, 1 + 542 542 00070 DF07 bnz $?L0020 ;[INF] 2, 4 + 543 543 ; line 106 : { + 544 544 00072 ??bb06_tsk_sw: + 545 545 ; line 107 : #ifdef _SW_HOME_ENABLE_ + 546 546 ; line 108 : set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD ); + 547 547 $DGL 0,53 + 548 548 00072 E6 onew ax ;[INF] 1, 1 + 549 549 00073 A1 incw ax ;[INF] 1, 1 + 550 550 00074 RFD0000 call !bs_F0060 ;[INF] 3, 3 + 551 551 00077 ??eb06_tsk_sw: + 552 552 ; line 109 : #else + 553 553 ; line 110 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); + 554 554 ; line 111 : #endif + 555 555 ; line 112 : } + 556 556 $DGL 0,57 + 557 557 00077 EF10 br $?L0022 ;[INF] 2, 3 + 558 558 00079 ?L0020: + 559 559 ; line 113 : else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) ) + 560 560 $DGL 0,58 + 561 561 00079 R40000094 cmp !_SW_pow_count,#094H ; 148 ;[INF] 4, 1 + 562 562 0007D DF0A bnz $?L0022 ;[INF] 2, 4 + 563 563 ; line 114 : { // todo + 564 564 0007F ??bb07_tsk_sw: + 565 565 ; line 115 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED; + 566 566 $DGL 0,60 + 567 567 0007F RCF290004 mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 + 568 568 ; line 116 : system_status.pwr_state = OFF_TRIG; + 569 569 $DGL 0,61 + 570 570 00083 RF50000 clrb !_system_status ;[INF] 3, 1 + 571 571 ; line 117 : renge_task_interval_run_force = 1; + 572 572 $DGL 0,62 + 573 573 00086 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 574 574 00089 ??eb07_tsk_sw: + 575 575 ; line 118 : } + 576 576 00089 ?L0022: + 577 577 ; line 119 : + 578 578 ; line 120 : // 電源OFF割り込みを入れたが… + 579 579 ; line 121 : if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0 + 580 580 ; ) + 581 581 $DGL 0,66 + 582 582 00089 R8F1000 mov a,!_vreg_ctr+16 ;[INF] 3, 1 + 583 583 0008C 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 584 584 0008E D1 cmp0 a ;[INF] 1, 1 + 585 585 0008F DD15 bz $?L0024 ;[INF] 2, 4 + 586 586 ; line 122 : { + 587 587 00091 ??bb08_tsk_sw: + 588 588 ; line 123 : cnt_force_off += 1; + 589 589 $DGL 0,68 + 590 590 00091 RA00000 inc !?L0003 ; cnt_force_off ;[INF] 3, 2 + 591 591 ; line 124 : if( cnt_force_off >= 13 ) + 592 592 $DGL 0,69 + 593 593 00094 R4000000D cmp !?L0003,#0DH ; cnt_force_off,13 ;[INF] 4, 1 + 594 594 00098 DC0F bc $?L0025 ;[INF] 2, 4 + 595 595 ; line 125 : { // …返事がない。強制的に切る。 + 596 596 0009A ??bb09_tsk_sw: + 597 597 ; line 126 : vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RE + 598 598 ; D; + 599 599 $DGL 0,71 + 600 600 0009A RCF290004 mov !_vreg_ctr+41,#04H ; 4 ;[INF] 4, 1 + 601 601 ; line 127 : system_status.pwr_state = OFF_TRIG; + 602 602 $DGL 0,72 + 603 603 0009E RF50000 clrb !_system_status ;[INF] 3, 1 + 604 604 ; line 128 : renge_task_interval_run_force = 1; + 605 605 $DGL 0,73 + 606 606 000A1 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 607 607 000A4 ??eb09_tsk_sw: + 608 608 ; line 129 : } + 609 609 ; line 130 : } + 610 610 $DGL 0,75 + 611 611 000A4 ??eb08_tsk_sw: + 612 612 000A4 EF03 br $?L0025 ;[INF] 2, 3 + 613 613 000A6 ?L0024: + 614 614 ; line 131 : else + 615 615 ; line 132 : { + 616 616 000A6 ??bb0A_tsk_sw: + 617 617 ; line 133 : cnt_force_off = 0; + 618 618 $DGL 0,78 + 619 619 000A6 RF50000 clrb !?L0003 ; cnt_force_off ;[INF] 3, 1 + 620 620 000A9 ??eb0A_tsk_sw: + 621 621 ; line 134 : } + 622 622 000A9 ?L0025: + 623 623 ; line 135 : + 624 624 ; line 136 : // HOME スイッチ // + 625 625 ; line 137 : switch( system_status.model ) + 626 626 $DGL 0,82 + 627 627 000A9 R8F0300 mov a,!_system_status+3 ;[INF] 3, 1 + 628 628 000AC 318F sarw ax,8 ;[INF] 2, 1 + 629 629 000AE E7 onew bc ;[INF] 1, 1 + 630 630 000AF 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 631 631 000B2 DD07 bz $?L0029 ;[INF] 2, 4 + 632 632 000B4 B1 decw ax ;[INF] 1, 1 + 633 633 000B5 23 subw ax,bc ;[INF] 1, 1 + 634 634 000B6 61D30C bnh $?L0030 ;[INF] 3, 4 + 635 635 000B9 EF12 br $?L0031 ;[INF] 2, 3 + 636 636 ; line 138 : { + 637 637 000BB ??bb0B_tsk_sw: + 638 638 ; line 139 : #ifdef _MODEL_CTR_ + 639 639 ; line 140 : case( MODEL_JIKKI ): + 640 640 000BB ?L0029: + 641 641 ; line 141 : SW_HOME_n = SW_HOME_n_JIKKI; + 642 642 $DGL 0,86 + 643 643 000BB 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 + 644 644 000BE 71C4 mov1 CY,[hl].4 ;[INF] 2, 1 + 645 645 000C0 R713100 mov1 _SW_HOME_n,CY ;[INF] 3, 2 + 646 646 ; line 142 : break; + 647 647 $DGL 0,87 + 648 648 000C3 EF0B br $?L0028 ;[INF] 2, 3 + 649 649 ; line 143 : #endif + 650 650 ; line 144 : case( MODEL_TS_BOARD ): + 651 651 000C5 ?L0030: + 652 652 ; line 145 : case( MODEL_SHIROBAKO ): + 653 653 ; line 146 : SW_HOME_n = SW_HOME_n_TSBOARD; + 654 654 $DGL 0,91 + 655 655 000C5 710402 mov1 CY,P2.0 ;[INF] 3, 1 + 656 656 000C8 R713100 mov1 _SW_HOME_n,CY ;[INF] 3, 2 + 657 657 ; line 147 : break; + 658 658 $DGL 0,92 + 659 659 000CB EF03 br $?L0028 ;[INF] 2, 3 + 660 660 ; line 148 : default: + 661 661 000CD ?L0031: + 662 662 ; line 149 : SW_HOME_n = 1; + 663 663 $DGL 0,94 + 664 664 000CD R713200 set1 _SW_HOME_n ;[INF] 3, 2 + 665 665 000D0 ??eb0B_tsk_sw: + 666 666 ; line 150 : } + 667 667 000D0 ?L0028: + 668 668 ; line 151 : + 669 669 ; line 152 : if( SW_HOME_n ) + 670 670 $DGL 0,97 + 671 671 000D0 R31340014 bf _SW_HOME_n,$?L0034 ;[INF] 4, 5 + 672 672 ; line 153 : { + 673 673 000D4 ??bb0C_tsk_sw: + 674 674 ; line 154 : if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home + 675 675 ; _count <= HOLD_THREASHOLD ) ) + 676 676 $DGL 0,99 + 677 677 000D4 R40010002 cmp !_SW_home_count,#02H ; 2 ;[INF] 4, 1 + 678 678 000D8 DC1A bc $?L0038 ;[INF] 2, 4 + 679 679 000DA R40010026 cmp !_SW_home_count,#026H ; 38 ;[INF] 4, 1 + 680 680 000DE DE14 bnc $?L0038 ;[INF] 2, 4 + 681 681 ; line 155 : { + 682 682 000E0 ??bb0D_tsk_sw: + 683 683 ; line 156 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK ); + 684 684 $DGL 0,101 + 685 685 000E0 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 686 686 000E3 RFD0000 call !bs_F0060 ;[INF] 3, 3 + 687 687 000E6 ??eb0D_tsk_sw: + 688 688 ; line 157 : } + 689 689 ; line 158 : } + 690 690 $DGL 0,103 + 691 691 000E6 ??eb0C_tsk_sw: + 692 692 000E6 EF0C br $?L0038 ;[INF] 2, 3 + 693 693 000E8 ?L0034: + 694 694 ; line 159 : else if( SW_home_count == HOLD_THREASHOLD ) + 695 695 $DGL 0,104 + 696 696 000E8 R40010025 cmp !_SW_home_count,#025H ; 37 ;[INF] 4, 1 + 697 697 000EC DF06 bnz $?L0038 ;[INF] 2, 4 + 698 698 ; line 160 : { + 699 699 000EE ??bb0E_tsk_sw: + 700 700 ; line 161 : set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD ); + 701 701 $DGL 0,106 + 702 702 000EE 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 703 703 000F1 RFD0000 call !bs_F0060 ;[INF] 3, 3 + 704 704 000F4 ??eb0E_tsk_sw: + 705 705 ; line 162 : } + 706 706 000F4 ?L0038: + 707 707 ; line 163 : + 708 708 ; line 164 : // wifi sw // + 709 709 ; line 165 : if( SW_wifi_count == CLICK_THRESHOLD ) + 710 710 $DGL 0,110 + 711 711 000F4 R40020001 cmp !_SW_wifi_count,#01H ; 1 ;[INF] 4, 1 + 712 712 000F8 DF08 bnz $?L0012 ;[INF] 2, 4 + 713 713 ; line 166 : { + 714 714 000FA ??bb0F_tsk_sw: + 715 715 ; line 167 : set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK ); + 716 716 $DGL 0,112 + 717 717 000FA 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 718 718 000FD C1 push ax ;[INF] 1, 1 + 719 719 000FE RFD0000 call !_set_irq ;[INF] 3, 3 + 720 720 00101 C0 pop ax ;[INF] 1, 1 + 721 721 00102 ??eb0F_tsk_sw: + 722 722 ; line 168 : } + 723 723 ; line 169 : + 724 724 ; line 170 : break; + 725 725 00102 ??eb03_tsk_sw: + 726 726 ; line 171 : } + 727 727 00102 ?L0012: + 728 728 ; line 172 : + 729 729 ; line 173 : // ボタン押し時間のカウント + 730 730 ; line 174 : /* + 731 731 ; line 175 : if( ( system_status.pwr_state == ON ) + 732 732 ; line 176 : || ( system_status.pwr_state == OFF ) + 733 733 ; line 177 : || ( system_status.pwr_state == BT_CHARGE ) ) + 734 734 ; line 178 : */ + 735 735 ; line 179 : + 736 736 ; line 180 : { + 737 737 00102 ??bb10_tsk_sw: + 738 738 ; line 181 : count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask ); + 739 739 $DGL 0,126 + 740 740 00102 ??bb11_tsk_sw: + 741 741 00102 31340708 bf P7.3,$?L0042 ;[INF] 4, 5 + 742 742 00106 ??bb12_tsk_sw: + 743 743 00106 R710300 clr1 _SW_pow_mask ;[INF] 3, 2 + 744 744 00109 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 + 745 745 0010C ??eb12_tsk_sw: + 746 746 0010C EF15 br $?L0046 ;[INF] 2, 3 + 747 747 0010E ?L0042: + 748 748 0010E ??bb13_tsk_sw: + 749 749 0010E R31040005 bf _SW_pow_mask,$?L0044 ;[INF] 4, 5 + 750 750 00112 ??bb14_tsk_sw: + 751 751 00112 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 + 752 752 00115 ??eb14_tsk_sw: + 753 753 00115 EF0C br $?L0046 ;[INF] 2, 3 + 754 754 00117 ?L0044: + 755 755 00117 ??bb15_tsk_sw: + 756 756 00117 RA00000 inc !_SW_pow_count ;[INF] 3, 2 + 757 757 0011A RD50000 cmp0 !_SW_pow_count ;[INF] 3, 1 + 758 758 0011D 61F8 sknz ;[INF] 2, 1 + 759 759 0011F RCF0000FF mov !_SW_pow_count,#0FFH ; 255 ;[INF] 4, 1 + 760 760 00123 ?L0046: + 761 761 00123 ??eb15_tsk_sw: + 762 762 00123 ??eb13_tsk_sw: + 763 763 00123 ??eb11_tsk_sw: + 764 764 ; line 182 : #ifdef _SW_HOME_ENABLE_ + 765 765 ; line 183 : count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask ); + 766 766 $DGL 0,128 + 767 767 00123 ??bb16_tsk_sw: + 768 768 00123 R31340008 bf _SW_HOME_n,$?L0048 ;[INF] 4, 5 + 769 769 00127 ??bb17_tsk_sw: + 770 770 00127 R711300 clr1 _SW_home_mask ;[INF] 3, 2 + 771 771 0012A RF50100 clrb !_SW_home_count ;[INF] 3, 1 + 772 772 0012D ??eb17_tsk_sw: + 773 773 0012D EF15 br $?L0052 ;[INF] 2, 3 + 774 774 0012F ?L0048: + 775 775 0012F ??bb18_tsk_sw: + 776 776 0012F R31140005 bf _SW_home_mask,$?L0050 ;[INF] 4, 5 + 777 777 00133 ??bb19_tsk_sw: + 778 778 00133 RF50100 clrb !_SW_home_count ;[INF] 3, 1 + 779 779 00136 ??eb19_tsk_sw: + 780 780 00136 EF0C br $?L0052 ;[INF] 2, 3 + 781 781 00138 ?L0050: + 782 782 00138 ??bb1A_tsk_sw: + 783 783 00138 RA00100 inc !_SW_home_count ;[INF] 3, 2 + 784 784 0013B RD50100 cmp0 !_SW_home_count ;[INF] 3, 1 + 785 785 0013E 61F8 sknz ;[INF] 2, 1 + 786 786 00140 RCF0100FF mov !_SW_home_count,#0FFH ; 255 ;[INF] 4, 1 + 787 787 00144 ?L0052: + 788 788 00144 ??eb1A_tsk_sw: + 789 789 00144 ??eb18_tsk_sw: + 790 790 00144 ??eb16_tsk_sw: + 791 791 ; line 184 : #endif + 792 792 ; line 185 : count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask ); + 793 793 $DGL 0,130 + 794 794 00144 ??bb1B_tsk_sw: + 795 795 00144 31440708 bf P7.4,$?L0054 ;[INF] 4, 5 + 796 796 00148 ??bb1C_tsk_sw: + 797 797 00148 R712300 clr1 _SW_wifi_mask ;[INF] 3, 2 + 798 798 0014B RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 + 799 799 0014E ??eb1C_tsk_sw: + 800 800 0014E EF15 br $?L0058 ;[INF] 2, 3 + 801 801 00150 ?L0054: + 802 802 00150 ??bb1D_tsk_sw: + 803 803 00150 R31240005 bf _SW_wifi_mask,$?L0056 ;[INF] 4, 5 + 804 804 00154 ??bb1E_tsk_sw: + 805 805 00154 RF50200 clrb !_SW_wifi_count ;[INF] 3, 1 + 806 806 00157 ??eb1E_tsk_sw: + 807 807 00157 EF0C br $?L0058 ;[INF] 2, 3 + 808 808 00159 ?L0056: + 809 809 00159 ??bb1F_tsk_sw: + 810 810 00159 RA00200 inc !_SW_wifi_count ;[INF] 3, 2 + 811 811 0015C RD50200 cmp0 !_SW_wifi_count ;[INF] 3, 1 + 812 812 0015F 61F8 sknz ;[INF] 2, 1 + 813 813 00161 RCF0200FF mov !_SW_wifi_count,#0FFH ; 255 ;[INF] 4, 1 + 814 814 00165 ?L0058: + 815 815 00165 ??eb1F_tsk_sw: + 816 816 00165 ??eb1D_tsk_sw: + 817 817 00165 ??eb1B_tsk_sw: + 818 818 00165 ??eb10_tsk_sw: + 819 819 ; line 186 : } + 820 820 ; line 187 : + 821 821 ; line 188 : return; + 822 822 ; line 189 : } + 823 823 $DGL 0,134 + 824 824 00165 ??ef_tsk_sw: + 825 825 00165 C6 pop hl ;[INF] 1, 1 + 826 826 00166 D7 ret ;[INF] 1, 6 + 827 827 00167 ??ee_tsk_sw: + 828 828 + 829 829 ----- @@CODEL CSEG + 830 830 + 831 831 ----- @@BASE CSEG BASE + 832 832 END + 833 833 + 834 834 + 835 835 ; *** Code Information *** + 836 836 ; + 837 837 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c + 838 838 ; + 839 839 ; $FUNC tsk_sw(56) + 840 840 ; void=(void) + 841 841 ; CODE SIZE= 351 bytes, CLOCK_SIZE= 329 clocks, STACK_SIZE= 12 bytes + 842 842 ; + 843 843 ; $CALL set_irq(99) + 844 844 ; void=(int:ax, int:[sp+4]) + 845 845 ; + 846 846 ; $CALL set_irq(108) + 847 847 ; void=(int:ax, int:[sp+4]) + 848 848 ; + 849 849 ; $CALL set_irq(156) + 850 850 ; void=(int:ax, int:[sp+4]) + 851 851 ; + 852 852 ; $CALL set_irq(161) + 853 853 ; void=(int:ax, int:[sp+4]) + 854 854 ; + 855 855 ; $CALL set_irq(167) + 856 856 ; void=(int:ax, int:[sp+4]) + 857 857 + 858 858 ; Target chip : uPD79F0104 + 859 859 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.4 @@BITS +00000 00030H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00004H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00167H ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/sw.rel b/branches/0.10(X3)/sw.rel new file mode 100644 index 0000000..4fe142d Binary files /dev/null and b/branches/0.10(X3)/sw.rel differ diff --git a/branches/0.10(X3)/task_debug.c b/branches/0.10(X3)/task_debug.c new file mode 100644 index 0000000..75d3e41 --- /dev/null +++ b/branches/0.10(X3)/task_debug.c @@ -0,0 +1,110 @@ +#pragma SFR +#pragma NOP +#pragma HALT +#pragma STOP + +#include "incs.h" +#include "renge.h" +#include "pm.h" + +#include "accero.h" + + +/* ======================================================== + ======================================================== */ +void tsk_debug( ) +{ + u8 temp; + static u8 count = 0; + static u8 task_interval; + + if( system_status.pwr_state == ON_TRIG ){ + +#ifdef _MODEL_WM0_ + PM_CHG_TIMEOUT_DISABLE(); // /WL_RST に配線されています +#endif +#ifndef _MODEL_CTR_ + iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 ); // ACR←0x80 揮発モードへ +#endif + + /* + temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO ); + count += 1; + iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, count ); + iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count ); + */ + } + return; +} + +u8 temp_debug_3; + +void tsk_debug2( ) +{ + u8 str[4]; + + if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) ) + { +/* + str[3] = vreg_ctr[ VREG_C_FREE0 ]; + str[2] = vreg_ctr[ VREG_C_FREE1 ]; + str[1] = vreg_ctr[ VREG_C_STATUS ]; + str[0] = vreg_ctr[ VREG_C_RTC_SEC ]; +*/ + str[3] = vreg_ctr[ VREG_C_SND_VOL ]; + str[2] = vreg_ctr[ VREG_C_TUNE ]; + str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ]; + str[0] = SEC; + +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VREG_C_IRQ1 ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_C_SND_VOL ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_TUNE ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VREG_C_ACC_ZH ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VREG_C_TUNE ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VREG_C_SND_VOL ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_C_STATUS ] ); +// iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VREG_C_ACC_ZH ] ); + + iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] ); + } + return; +} + + + +#if 0 +/* ======================================================== + タスクひな形 + ======================================================== */ +task_interval tsk_hina( ) +{ + switch ( system_status.pwr_state ) + { + case OFF: + case ON_TRIG: + case ON: + case SLEEP_TRIG: + case SLEEP: + case OFF_TRIG: + default: + } + + return ( 次の起 ・ｮまでのシ ・X ・e ・ tick ・・); // 毎 tic 呼ばれることになります +} + + +// ポインタで何かもらうのは危険な気がしてきた +/* このように使う + renge_task_immed_add( タスク関数へのポインタ ); +*/ +task_status_immed tsk_imm_hina( u8 * arg ) +{ + return ( ERR_FINISED ); + // ERR_FINISED タスクを削除 + // ERR_CONTINUE 次になんか割り込みなり、ユーザー操作なり、システムチックが + // 来たときに再度実行 +} + + +#endif diff --git a/branches/0.10(X3)/task_debug.prn b/branches/0.10(X3)/task_debug.prn new file mode 100644 index 0000000..7480aad --- /dev/null +++ b/branches/0.10(X3)/task_debug.prn @@ -0,0 +1,412 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_debug.asm +Para-file: +In-file: inter_asm\task_debug.asm +Obj-file: task_debug.rel +Prn-file: task_debug.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_debug.c + 6 6 ; In-file : task_debug.c + 7 7 ; Asm-file : inter_asm\task_debug.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 05CH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, task_debug.c + 18 18 $DGS MOD_NAM, task_debug, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 82 82 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 83 83 $DGS GLV_SYM, _tsk_debug, U, U, 01H, 026H, 01H, 02H + 84 84 $DGS AUX_FUN, 00H, U, U, 050H, 00H, 00H + 85 85 $DGS BEG_FUN, ??bf_tsk_debug, U, U, 00H, 065H, 01H, 00H + 86 86 $DGS AUX_BEG, 010H, 02H, 04AH + 87 87 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 88 88 $DGS STA_SYM, _count, ?L0003, U, 0CH, 03H, 00H, 00H + 89 89 $DGS STA_SYM, _task_interval, ?L0004, U, 0CH, 03H, 00H, 00H + 90 90 $DGS BEG_BLK, ??bb00_tsk_debug, U, U, 00H, 064H, 01H, 00H + 91 91 $DGS AUX_BEG, 06H, 00H, 00H + 92 92 $DGS END_BLK, ??eb00_tsk_debug, U, U, 00H, 064H, 01H, 00H + 93 93 $DGS AUX_END, 015H + 94 94 $DGS END_FUN, ??ef_tsk_debug, U, U, 00H, 065H, 01H, 00H + 95 95 $DGS AUX_END, 017H + 96 96 $DGS GLV_SYM, _tsk_debug2, U, U, 01H, 026H, 01H, 02H + 97 97 $DGS AUX_FUN, 00H, U, U, 05CH, 00H, 00H + 98 98 $DGS BEG_FUN, ??bf_tsk_debug2, U, U, 00H, 065H, 01H, 00H + 99 99 $DGS AUX_BEG, 02BH, 04H, 056H + 100 100 $DGS AUT_VAR, _str, 00H, 0FFFFH, 0CH, 01H, 01H, 03H + 101 101 $DGS AUX_STR, 00H, 00H, 04H, 04H, 00H, 00H, 00H, 00H + 102 102 $DGS BEG_BLK, ??bb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_BEG, 05H, 00H, 00H + 104 104 $DGS END_BLK, ??eb00_tsk_debug2, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_END, 01CH + 106 106 $DGS END_FUN, ??ef_tsk_debug2, U, U, 00H, 065H, 01H, 00H + 107 107 $DGS AUX_END, 01EH + 108 108 $DGS GLV_SYM, _temp_debug_3, U, U, 0CH, 026H, 00H, 00H + 109 109 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 110 110 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 111 111 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 112 112 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 113 113 $DGS GLV_SYM, _iic_mcu_write, U, U, 0CH, 02H, 01H, 02H + 114 114 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 115 115 + 116 116 EXTRN _system_status + 117 117 EXTRN _vreg_ctr + 118 118 EXTRN _iic_mcu_write + 119 119 PUBLIC _tsk_debug + 120 120 PUBLIC _temp_debug_3 + 121 121 PUBLIC _tsk_debug2 + 122 122 + 123 123 ----- @@BITS BSEG + 124 124 + 125 125 ----- @@CNST CSEG MIRRORP + 126 126 00000 01 _lpf_coeff: DB 01H ; 1 + 127 127 00001 02 DB 02H ; 2 + 128 128 00002 02 DB 02H ; 2 + 129 129 00003 03 DB 03H ; 3 + 130 130 00004 03 DB 03H ; 3 + 131 131 00005 02 DB 02H ; 2 + 132 132 00006 00 DB 00H ; 0 + 133 133 00007 FE DB 0FEH ; 254 + 134 134 00008 FB DB 0FBH ; 251 + 135 135 00009 F7 DB 0F7H ; 247 + 136 136 0000A F3 DB 0F3H ; 243 + 137 137 0000B F0 DB 0F0H ; 240 + 138 138 0000C F0 DB 0F0H ; 240 + 139 139 0000D F3 DB 0F3H ; 243 + 140 140 0000E FA DB 0FAH ; 250 + 141 141 0000F 04 DB 04H ; 4 + 142 142 00010 12 DB 012H ; 18 + 143 143 00011 25 DB 025H ; 37 + 144 144 00012 38 DB 038H ; 56 + 145 145 00013 4D DB 04DH ; 77 + 146 146 00014 5F DB 05FH ; 95 + 147 147 00015 6E DB 06EH ; 110 + 148 148 00016 77 DB 077H ; 119 + 149 149 00017 7A DB 07AH ; 122 + 150 150 00018 77 DB 077H ; 119 + 151 151 00019 6E DB 06EH ; 110 + 152 152 0001A 5F DB 05FH ; 95 + 153 153 0001B 4D DB 04DH ; 77 + 154 154 0001C 38 DB 038H ; 56 + 155 155 0001D 25 DB 025H ; 37 + 156 156 0001E 12 DB 012H ; 18 + 157 157 0001F 04 DB 04H ; 4 + 158 158 00020 FA DB 0FAH ; 250 + 159 159 00021 F3 DB 0F3H ; 243 + 160 160 00022 F0 DB 0F0H ; 240 + 161 161 00023 F0 DB 0F0H ; 240 + 162 162 00024 F3 DB 0F3H ; 243 + 163 163 00025 F7 DB 0F7H ; 247 + 164 164 00026 FB DB 0FBH ; 251 + 165 165 00027 FE DB 0FEH ; 254 + 166 166 00028 00 DB 00H ; 0 + 167 167 00029 02 DB 02H ; 2 + 168 168 0002A 03 DB 03H ; 3 + 169 169 0002B 03 DB 03H ; 3 + 170 170 0002C 02 DB 02H ; 2 + 171 171 0002D 02 DB 02H ; 2 + 172 172 0002E 01 DB 01H ; 1 + 173 173 0002F 00 DB (1) + 174 174 + 175 175 ----- @@R_INIT CSEG UNIT64KP + 176 176 00000 00 DB 00H ; 0 + 177 177 00001 00 DB (1) + 178 178 + 179 179 ----- @@INIT DSEG BASEP + 180 180 00000 ?L0003: DS (1) + 181 181 00001 DS (1) + 182 182 + 183 183 ----- @@DATA DSEG BASEP + 184 184 00000 ?L0004: DS (1) + 185 185 00001 _temp_debug_3: DS (1) + 186 186 + 187 187 ----- @@R_INIS CSEG UNIT64KP + 188 188 + 189 189 ----- @@INIS DSEG SADDRP + 190 190 + 191 191 ----- @@DATS DSEG SADDRP + 192 192 + 193 193 ----- @@CNSTL CSEG PAGE64KP + 194 194 + 195 195 ----- @@RLINIT CSEG UNIT64KP + 196 196 + 197 197 ----- @@INITL DSEG UNIT64KP + 198 198 + 199 199 ----- @@DATAL DSEG UNIT64KP + 200 200 + 201 201 ----- @@CALT CSEG CALLT0 + 202 202 + 203 203 ; line 1 : #pragma SFR + 204 204 ; line 2 : #pragma NOP + 205 205 ; line 3 : #pragma HALT + 206 206 ; line 4 : #pragma STOP + 207 207 ; line 5 : + 208 208 ; line 6 : #include "incs.h" + 209 209 ; line 7 : #include "renge.h" + 210 210 ; line 8 : #include "pm.h" + 211 211 ; line 9 : + 212 212 ; line 10 : #include "accero.h" + 213 213 ; line 11 : + 214 214 ; line 12 : + 215 215 ; line 13 : /* ======================================================== + 216 216 ; line 14 : ======================================================== */ + 217 217 ; line 15 : void tsk_debug( ) + 218 218 ; line 16 : { + 219 219 + 220 220 ----- ROM_CODE CSEG BASE + 221 221 00000 _tsk_debug: + 222 222 $DGL 1,67 + 223 223 00000 C7 push hl ;[INF] 1, 1 + 224 224 00001 ??bf_tsk_debug: + 225 225 ; line 17 : u8 temp; + 226 226 ; line 18 : static u8 count = 0; + 227 227 ; line 19 : static u8 task_interval; + 228 228 ; line 20 : + 229 229 ; line 21 : if( system_status.pwr_state == ON_TRIG ){ + 230 230 $DGL 0,6 + 231 231 00001 R40000002 cmp !_system_status,#02H ; 2 ;[INF] 4, 1 + 232 232 00005 ??bb00_tsk_debug: + 233 233 00005 ??eb00_tsk_debug: + 234 234 ; line 22 : + 235 235 ; line 23 : #ifdef _MODEL_WM0_ + 236 236 ; line 24 : PM_CHG_TIMEOUT_DISABLE(); // + 237 237 ; /WL_RST に配線されています + 238 238 ; line 25 : #endif + 239 239 ; line 26 : #ifndef _MODEL_CTR_ + 240 240 ; line 27 : iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 ); // + 241 241 ; ACR←0x80 揮発モードへ + 242 242 ; line 28 : #endif + 243 243 ; line 29 : + 244 244 ; line 30 : /* + 245 245 ; line 31 : temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_ + 246 246 ; DO ); + 247 247 ; line 32 : count += 1; + 248 248 ; line 33 : iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, co + 249 249 ; unt ); + 250 250 ; line 34 : iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count ); + 251 251 ; line 35 : */ + 252 252 ; line 36 : } + 253 253 ; line 37 : return; + 254 254 ; line 38 : } + 255 255 $DGL 0,23 + 256 256 00005 ??ef_tsk_debug: + 257 257 00005 C6 pop hl ;[INF] 1, 1 + 258 258 00006 D7 ret ;[INF] 1, 6 + 259 259 00007 ??ee_tsk_debug: + 260 260 ; line 39 : + 261 261 ; line 40 : u8 temp_debug_3; + 262 262 ; line 41 : + 263 263 ; line 42 : void tsk_debug2( ) + 264 264 ; line 43 : { + 265 265 00007 _tsk_debug2: + 266 266 $DGL 1,80 + 267 267 00007 C7 push hl ;[INF] 1, 1 + 268 268 00008 2004 subw sp,#04H ;[INF] 2, 1 + 269 269 0000A FBF8FF movw hl,sp ;[INF] 3, 1 + 270 270 0000D ??bf_tsk_debug2: + 271 271 ; line 44 : u8 str[4]; + 272 272 ; line 45 : + 273 273 ; line 46 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr + 274 274 ; _state == SLEEP ) ) + 275 275 $DGL 0,4 + 276 276 0000D R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 277 277 00011 DD06 bz $?L0011 ;[INF] 2, 4 + 278 278 00013 R40000005 cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + 279 279 00017 DF21 bnz $?L0009 ;[INF] 2, 4 + 280 280 00019 ?L0011: + 281 281 ; line 47 : { + 282 282 00019 ??bb00_tsk_debug2: + 283 283 ; line 48 : /* + 284 284 ; line 49 : str[3] = vreg_ctr[ VREG_C_FREE0 ]; + 285 285 ; line 50 : str[2] = vreg_ctr[ VREG_C_FREE1 ]; + 286 286 ; line 51 : str[1] = vreg_ctr[ VREG_C_STATUS ]; + 287 287 ; line 52 : str[0] = vreg_ctr[ VREG_C_RTC_SEC ]; + 288 288 ; line 53 : */ + 289 289 ; line 54 : str[3] = vreg_ctr[ VREG_C_SND_VOL ]; + 290 290 $DGL 0,12 + 291 291 00019 R8F0900 mov a,!_vreg_ctr+9 ;[INF] 3, 1 + 292 292 0001C 9C03 mov [hl+3],a ; str ;[INF] 2, 1 + 293 293 ; line 55 : str[2] = vreg_ctr[ VREG_C_TUNE ]; + 294 294 $DGL 0,13 + 295 295 0001E R8F0800 mov a,!_vreg_ctr+8 ;[INF] 3, 1 + 296 296 00021 9C02 mov [hl+2],a ; str ;[INF] 2, 1 + 297 297 ; line 56 : str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ]; + 298 298 $DGL 0,14 + 299 299 00023 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 300 300 00026 9C01 mov [hl+1],a ; str ;[INF] 2, 1 + 301 301 ; line 57 : str[0] = SEC; + 302 302 $DGL 0,15 + 303 303 00028 8E92 mov a,SEC ;[INF] 2, 1 + 304 304 0002A 9B mov [hl],a ; str ;[INF] 1, 1 + 305 305 ; line 58 : + 306 306 ; line 59 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR + 307 307 ; EG_C_IRQ1 ] ); + 308 308 ; line 60 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura ); + 309 309 ; line 61 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR + 310 310 ; EG_C_SND_VOL ] ); + 311 311 ; line 62 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR + 312 312 ; EG_TUNE ] ); + 313 313 ; line 63 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR + 314 314 ; EG_C_ACC_ZH ] ); + 315 315 ; line 64 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VR + 316 316 ; EG_C_TUNE ] ); + 317 317 ; line 65 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR + 318 318 ; EG_C_SND_VOL ] ); + 319 319 ; line 66 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR + 320 320 ; EG_C_STATUS ] ); + 321 321 ; line 67 : // iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR + 322 322 ; EG_C_ACC_ZH ] ); + 323 323 ; line 68 : + 324 324 ; line 69 : iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] ); + 325 325 $DGL 0,27 + 326 326 0002B 17 movw ax,hl ;[INF] 1, 1 + 327 327 0002C C1 push ax ;[INF] 1, 1 + 328 328 0002D 300400 movw ax,#04H ; 4 ;[INF] 3, 1 + 329 329 00030 C1 push ax ;[INF] 1, 1 + 330 330 00031 F6 clrw ax ;[INF] 1, 1 + 331 331 00032 C1 push ax ;[INF] 1, 1 + 332 332 00033 5044 mov x,#044H ; 68 ;[INF] 2, 1 + 333 333 00035 RFD0000 call !_iic_mcu_write ;[INF] 3, 3 + 334 334 00038 1006 addw sp,#06H ; 6 ;[INF] 2, 1 + 335 335 0003A ??eb00_tsk_debug2: + 336 336 ; line 70 : } + 337 337 0003A ?L0009: + 338 338 ; line 71 : return; + 339 339 ; line 72 : } + 340 340 $DGL 0,30 + 341 341 0003A ??ef_tsk_debug2: + 342 342 0003A 1004 addw sp,#04H ;[INF] 2, 1 + 343 343 0003C C6 pop hl ;[INF] 1, 1 + 344 344 0003D D7 ret ;[INF] 1, 6 + 345 345 0003E ??ee_tsk_debug2: + 346 346 + 347 347 ----- @@CODEL CSEG + 348 348 + 349 349 ----- @@BASE CSEG BASE + 350 350 END + 351 351 + 352 352 + 353 353 ; *** Code Information *** + 354 354 ; + 355 355 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c + 356 356 ; + 357 357 ; $FUNC tsk_debug(16) + 358 358 ; void=(void) + 359 359 ; CODE SIZE= 7 bytes, CLOCK_SIZE= 9 clocks, STACK_SIZE= 2 bytes + 360 360 ; + 361 361 ; $FUNC tsk_debug2(43) + 362 362 ; void=(void) + 363 363 ; CODE SIZE= 55 bytes, CLOCK_SIZE= 40 clocks, STACK_SIZE= 16 bytes + 364 364 ; + 365 365 ; $CALL iic_mcu_write(69) + 366 366 ; bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8]) + 367 367 + 368 368 ; Target chip : uPD79F0104 + 369 369 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00002H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0003EH ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/task_debug.rel b/branches/0.10(X3)/task_debug.rel new file mode 100644 index 0000000..c422156 Binary files /dev/null and b/branches/0.10(X3)/task_debug.rel differ diff --git a/branches/0.10(X3)/task_misc.c b/branches/0.10(X3)/task_misc.c new file mode 100644 index 0000000..7d379e9 --- /dev/null +++ b/branches/0.10(X3)/task_misc.c @@ -0,0 +1,276 @@ +#pragma SFR +#pragma NOP +#pragma HALT +#pragma STOP + +#include "incs.h" +#include "renge.h" +#include "pm.h" + +#include "accero.h" +#include "adc.h" +#include "i2c_mcu.h" + + +#ifdef _MCU_BSR_ +#define ACKD ACKD1 +#define ACKE ACKE1 +#define COI COI1 +#define IICAEN IICA1EN +#define IICRSV IICRSV1 +#define IICA IICA1 +#define IICAIF IICAIF1 +#define IICAMK IICAMK1 +#define IICAPR0 IICAPR11 +#define IICAPR1 IICAPR01 +#define IICCTL0 IICCTL10 +#define IICE IICE1 +#define IICF IICF1 +#define IICS IICS1 +#define IICWH IICWH1 +#define IICWL IICWL1 +#define LREL LREL1 +#define SPD SPD1 +#define SPIE SPIE1 +#define STCEN STCEN1 +#define STD STD1 +#define SVA SVA1 +#define WREL WREL1 +#define WTIM WTIM1 +#define TRC TRC1 +#define SMC SMC1 +#define DFC DFC1 +#endif + + + +// ======================================================== +#define INTERVAL_TSK_MISC_STAT 4 + + +/* ======================================================== + ステータスレジスタなど + ======================================================== */ +void tsk_misc_stat( ) +{ + static u8 interval_task_misc_stat = 0; + static u8 state_old; // ステータス変化検出→割り込み の為 +#ifdef _BL_INDEPENDENT_ + static u8 state2_old; +#endif + u8 diff; + + if( interval_task_misc_stat != 0 ) + { + interval_task_misc_stat -= 1; + return; + } + else + { + interval_task_misc_stat = ( INTERVAL_TSK_MISC_STAT / SYS_INTERVAL_TICK ); + } + + set_bit( SHELL_OPEN, vreg_ctr[VREG_C_STATUS], REG_BIT_ST_SHELL_OPEN ); + + // ステータスレジスタ関係 → 割り込み // + if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) ) + { + // pm.c で、その場で行います。 + // REG_BIT_LCD_ON/OFF + // REG_BIT_BL_ON/OFF + // REG_BIT_BT_DC_CONNECT/DISC + + + diff = vreg_ctr[VREG_C_STATUS] ^ state_old; + if( diff != 0 ) + { + state_old = vreg_ctr[VREG_C_STATUS]; + + if( diff & REG_BIT_BATT_CHARGE ) + { + // 充電状態に以下略 + if( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARGE ) + { + set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_START ); + } + else + { + set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_STOP ); + } + } + + if( diff & REG_BIT_ST_SHELL_OPEN ) + { + // 蓋の開け閉め + if( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_OPEN ) + { + set_irq( VREG_C_IRQ0, REG_BIT_SHELL_OPEN ); + } + else + { + set_irq( VREG_C_IRQ0, REG_BIT_SHELL_CLOSE ); + } + } + } + + +//#ifdef _MCU_KE3_ + // KE3では必須です。 + /* ======================================================== + 加速度センサ割り込みピンがオリジナルマイコンには無いので + ポーリングする。 + 歩数計用 + BSRマイコンはaccero.cで割り込みルーチンからタスク登録します。 + ======================================================== */ + // 割り込みの取りこぼし？ + if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) + { + if( ACC_VALID ) + { + if( renge_task_immed_add( tsk_cbk_accero ) == ERR_SUCCESS ){ + NOP(); + } + } + } +//#endif + + // 割り込みの取りこぼし？ + if( !PM_IRQ_n ){ + renge_task_immed_add( ntr_pmic_comm ); + NOP(); + } + } + return; +} + + + + + +/* ======================================================== + 逐一起動タスク + ======================================================== */ + +/* ======================================================== + COMMANDレジスタへの書き込み +　 0なら呼ばれません。ケア不要 + ======================================================== */ +task_status_immed do_command0( ) +{ + // command0 本体電源など + if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BIT_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) != 0x00 ) + { + if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ ) + { + system_status.pwr_state = OFF_TRIG; + } + else + { + if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ ) + { + PM_reset_ast( ); + RESET2_ast; + FCRAM_RST_ast; + } + if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_REQ ) + { + FCRAM_RST_ast; + } + else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_REQ ) + { + RESET2_ast; + } + wait_ms( 5 ); + FCRAM_RST_neg; + PM_reset_neg(); + RESET2_neg; +/* + // CODEC 不定レジスタ初期化 + wait_ms( 100 ); + { + u8 codec_reg_init[3] = { 0,0,0 }; + iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, codec_reg_init ); + } +*/ + } + } + + vreg_ctr[VREG_C_COMMAND0] = 0; + return ( ERR_FINISED ); +} + + + +/* ======================================================== +　互換向け、TWLアプリへの割り込み + 仮想レジスタの書き込み時に行います。 + ======================================================== */ +// task_status_immed do_command1( ) + + +extern u8 iic_burst_state; +/* ======================================================== +　デバッグ用にいろいろ読んできます。 +　返値はデータそのもの + ======================================================== */ +task_status_immed tski_mcu_info_read() +{ + u8 temp; + + + if( SPD ) + { + goto end; + } + + if( STD ) + { + SPIE = 1; + } + + if( IICAIF == 0 ) + { + return( ERR_CONTINUE ); + } + else + { + IICAIF = 0; + } + + switch( iic_burst_state++ ){ + case( 0 ): // 本体種類識別 + IICA = (u8)system_status.model; + break; + + case( 1 ): // IICがなにかエラーでも知らない。00かFFならエラーの可能性が高い + IICA = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VER ); + break; + + case( 2 ): // 電池メーカーの識別 + BT_DET_P = 1; + IICA = ( u8 ) ( get_adc( ADC_SEL_BATT_DET ) >> 5 ); + BT_DET_P = 0; + break; + + case( 3 ): // ガスゲージバージョン + IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_VERSION ); + break; + + case( 4 ): // LSB + IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_VERSION + 1 ); + break; + + default: + goto end; + } + return( ERR_CONTINUE ); + +end: + LREL = 1; + SPIE = 0; + IICAMK = 0; + iic_burst_state = 0; + return( ERR_FINISED ); +} + + diff --git a/branches/0.10(X3)/task_misc.prn b/branches/0.10(X3)/task_misc.prn new file mode 100644 index 0000000..25347b3 --- /dev/null +++ b/branches/0.10(X3)/task_misc.prn @@ -0,0 +1,1164 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_misc.asm +Para-file: +In-file: inter_asm\task_misc.asm +Obj-file: task_misc.rel +Prn-file: task_misc.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_misc.c + 6 6 ; In-file : task_misc.c + 7 7 ; Asm-file : inter_asm\task_misc.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0EAH, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, task_misc.c + 18 18 $DGS MOD_NAM, task_misc, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 82 82 $DGS AUX_TAG, 01H, 047H + 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 86 86 $DGS AUX_EOS, 041H, 01H + 87 87 $DGS LAB_SYM, bs_F0060, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_F0060, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 91 91 $DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 026H, 01H, 02H + 92 92 $DGS AUX_FUN, 00H, U, U, 098H, 00H, 00H + 93 93 $DGS BEG_FUN, ??bf_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H + 94 94 $DGS AUX_BEG, 037H, 02H, 052H + 95 95 $DGS STA_SYM, _interval_task_misc_stat, ?L0003, U, 0CH, 03H, 00H, 00H + 96 96 $DGS STA_SYM, _state_old, ?L0004, U, 0CH, 03H, 00H, 00H + 97 97 $DGS REG_VAR, _diff, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 98 98 $DGS BEG_BLK, ??bb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 99 99 $DGS AUX_BEG, 0AH, 00H, 056H + 100 100 $DGS END_BLK, ??eb00_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 101 101 $DGS AUX_END, 0DH + 102 102 $DGS BEG_BLK, ??bb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_BEG, 0FH, 00H, 05AH + 104 104 $DGS END_BLK, ??eb01_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_END, 011H + 106 106 $DGS BEG_BLK, ??bb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 107 107 $DGS AUX_BEG, 013H, 00H, 05CH + 108 108 $DGS BEG_BLK, ??bb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_BEG, 013H, 00H, 060H + 110 110 $DGS END_BLK, ??eb03_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_END, 013H + 112 112 $DGS BEG_BLK, ??bb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 113 113 $DGS AUX_BEG, 013H, 00H, 066H + 114 114 $DGS END_BLK, ??eb04_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 115 115 $DGS AUX_END, 013H + 116 116 $DGS END_BLK, ??eb02_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 117 117 $DGS AUX_END, 013H + 118 118 $DGS BEG_BLK, ??bb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 119 119 $DGS AUX_BEG, 017H, 00H, 068H + 120 120 $DGS BEG_BLK, ??bb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_BEG, 020H, 00H, 06AH + 122 122 $DGS BEG_BLK, ??bb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 123 123 $DGS AUX_BEG, 024H, 00H, 06CH + 124 124 $DGS BEG_BLK, ??bb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 125 125 $DGS AUX_BEG, 027H, 00H, 070H + 126 126 $DGS END_BLK, ??eb08_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 127 127 $DGS AUX_END, 029H + 128 128 $DGS BEG_BLK, ??bb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 129 129 $DGS AUX_BEG, 02BH, 00H, 076H + 130 130 $DGS END_BLK, ??eb09_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 131 131 $DGS AUX_END, 02DH + 132 132 $DGS END_BLK, ??eb07_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 133 133 $DGS AUX_END, 02EH + 134 134 $DGS BEG_BLK, ??bb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 135 135 $DGS AUX_BEG, 031H, 00H, 078H + 136 136 $DGS BEG_BLK, ??bb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 137 137 $DGS AUX_BEG, 034H, 00H, 07CH + 138 138 $DGS END_BLK, ??eb0B_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 139 139 $DGS AUX_END, 036H + 140 140 $DGS BEG_BLK, ??bb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 141 141 $DGS AUX_BEG, 038H, 00H, 084H + 142 142 $DGS END_BLK, ??eb0C_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 143 143 $DGS AUX_END, 03AH + 144 144 $DGS END_BLK, ??eb0A_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 145 145 $DGS AUX_END, 03BH + 146 146 $DGS END_BLK, ??eb06_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_END, 03CH + 148 148 $DGS BEG_BLK, ??bb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_BEG, 049H, 00H, 086H + 150 150 $DGS BEG_BLK, ??bb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 151 151 $DGS AUX_BEG, 04BH, 00H, 088H + 152 152 $DGS BEG_BLK, ??bb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 153 153 $DGS AUX_BEG, 04CH, 00H, 090H + 154 154 $DGS END_BLK, ??eb0F_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_END, 04EH + 156 156 $DGS END_BLK, ??eb0E_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_END, 04FH + 158 158 $DGS END_BLK, ??eb0D_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 159 159 $DGS AUX_END, 050H + 160 160 $DGS BEG_BLK, ??bb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 161 161 $DGS AUX_BEG, 054H, 00H, 00H + 162 162 $DGS END_BLK, ??eb10_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 163 163 $DGS AUX_END, 057H + 164 164 $DGS END_BLK, ??eb05_tsk_misc_stat, U, U, 00H, 064H, 01H, 00H + 165 165 $DGS AUX_END, 058H + 166 166 $DGS END_FUN, ??ef_tsk_misc_stat, U, U, 00H, 065H, 01H, 00H + 167 167 $DGS AUX_END, 05AH + 168 168 $DGS GLV_SYM, _do_command0, U, U, 0AH, 026H, 01H, 02H + 169 169 $DGS AUX_FUN, 041H, U, U, 0CEH, 00H, 00H + 170 170 $DGS BEG_FUN, ??bf_do_command0, U, U, 00H, 065H, 01H, 00H + 171 171 $DGS AUX_BEG, 09FH, 00H, 09CH + 172 172 $DGS BEG_BLK, ??bb00_do_command0, U, U, 00H, 064H, 01H, 00H + 173 173 $DGS AUX_BEG, 04H, 00H, 09EH + 174 174 $DGS BEG_BLK, ??bb01_do_command0, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_BEG, 06H, 00H, 0A2H + 176 176 $DGS END_BLK, ??eb01_do_command0, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_END, 08H + 178 178 $DGS BEG_BLK, ??bb02_do_command0, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_BEG, 0AH, 00H, 0A4H + 180 180 $DGS BEG_BLK, ??bb03_do_command0, U, U, 00H, 064H, 01H, 00H + 181 181 $DGS AUX_BEG, 0CH, 00H, 0A6H + 182 182 $DGS BEG_BLK, ??bb04_do_command0, U, U, 00H, 064H, 01H, 00H + 183 183 $DGS AUX_BEG, 0EH, 00H, 0AAH + 184 184 $DGS END_BLK, ??eb04_do_command0, U, U, 00H, 064H, 01H, 00H + 185 185 $DGS AUX_END, 0EH + 186 186 $DGS BEG_BLK, ??bb05_do_command0, U, U, 00H, 064H, 01H, 00H + 187 187 $DGS AUX_BEG, 0FH, 00H, 0B0H + 188 188 $DGS END_BLK, ??eb05_do_command0, U, U, 00H, 064H, 01H, 00H + 189 189 $DGS AUX_END, 0FH + 190 190 $DGS END_BLK, ??eb03_do_command0, U, U, 00H, 064H, 01H, 00H + 191 191 $DGS AUX_END, 010H + 192 192 $DGS BEG_BLK, ??bb06_do_command0, U, U, 00H, 064H, 01H, 00H + 193 193 $DGS AUX_BEG, 012H, 00H, 0B2H + 194 194 $DGS BEG_BLK, ??bb07_do_command0, U, U, 00H, 064H, 01H, 00H + 195 195 $DGS AUX_BEG, 013H, 00H, 0B8H + 196 196 $DGS END_BLK, ??eb07_do_command0, U, U, 00H, 064H, 01H, 00H + 197 197 $DGS AUX_END, 013H + 198 198 $DGS END_BLK, ??eb06_do_command0, U, U, 00H, 064H, 01H, 00H + 199 199 $DGS AUX_END, 014H + 200 200 $DGS BEG_BLK, ??bb08_do_command0, U, U, 00H, 064H, 01H, 00H + 201 201 $DGS AUX_BEG, 016H, 00H, 0BAH + 202 202 $DGS BEG_BLK, ??bb09_do_command0, U, U, 00H, 064H, 01H, 00H + 203 203 $DGS AUX_BEG, 017H, 00H, 0C0H + 204 204 $DGS END_BLK, ??eb09_do_command0, U, U, 00H, 064H, 01H, 00H + 205 205 $DGS AUX_END, 017H + 206 206 $DGS END_BLK, ??eb08_do_command0, U, U, 00H, 064H, 01H, 00H + 207 207 $DGS AUX_END, 018H + 208 208 $DGS BEG_BLK, ??bb0A_do_command0, U, U, 00H, 064H, 01H, 00H + 209 209 $DGS AUX_BEG, 01AH, 00H, 0C4H + 210 210 $DGS END_BLK, ??eb0A_do_command0, U, U, 00H, 064H, 01H, 00H + 211 211 $DGS AUX_END, 01AH + 212 212 $DGS BEG_BLK, ??bb0B_do_command0, U, U, 00H, 064H, 01H, 00H + 213 213 $DGS AUX_BEG, 01CH, 00H, 00H + 214 214 $DGS END_BLK, ??eb0B_do_command0, U, U, 00H, 064H, 01H, 00H + 215 215 $DGS AUX_END, 01CH + 216 216 $DGS END_BLK, ??eb02_do_command0, U, U, 00H, 064H, 01H, 00H + 217 217 $DGS AUX_END, 025H + 218 218 $DGS END_BLK, ??eb00_do_command0, U, U, 00H, 064H, 01H, 00H + 219 219 $DGS AUX_END, 026H + 220 220 $DGS END_FUN, ??ef_do_command0, U, U, 00H, 065H, 01H, 00H + 221 221 $DGS AUX_END, 02AH + 222 222 $DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 026H, 01H, 02H + 223 223 $DGS AUX_FUN, 041H, U, U, 0EAH, 00H, 00H + 224 224 $DGS BEG_FUN, ??bf_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H + 225 225 $DGS AUX_BEG, 0D9H, 02H, 0D3H + 226 226 $DGS REG_VAR, _temp, 06H, 0FFFFH, 010CH, 04H, 00H, 00H + 227 227 $DGS BEG_BLK, ??bb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 228 228 $DGS AUX_BEG, 06H, 00H, 0D7H + 229 229 $DGS END_BLK, ??eb00_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 230 230 $DGS AUX_END, 08H + 231 231 $DGS BEG_BLK, ??bb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 232 232 $DGS AUX_BEG, 0BH, 00H, 0DBH + 233 233 $DGS END_BLK, ??eb01_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 234 234 $DGS AUX_END, 0DH + 235 235 $DGS BEG_BLK, ??bb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 236 236 $DGS AUX_BEG, 010H, 00H, 0DFH + 237 237 $DGS END_BLK, ??eb02_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 238 238 $DGS AUX_END, 012H + 239 239 $DGS BEG_BLK, ??bb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 240 240 $DGS AUX_BEG, 014H, 00H, 0E3H + 241 241 $DGS END_BLK, ??eb03_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 242 242 $DGS AUX_END, 016H + 243 243 $DGS BEG_BLK, ??bb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 244 244 $DGS AUX_BEG, 018H, 00H, 00H + 245 245 $DGS END_BLK, ??eb04_tski_mcu_info_read, U, U, 00H, 064H, 01H, 00H + 246 246 $DGS AUX_END, 031H + 247 247 $DGS LAB_SYM, _end, ?L0046, U, 00H, 06H, 00H, 00H + 248 248 $DGS END_FUN, ??ef_tski_mcu_info_read, U, U, 00H, 065H, 01H, 00H + 249 249 $DGS AUX_END, 03AH + 250 250 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H + 251 251 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 252 252 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 253 253 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 254 254 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 255 255 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 256 256 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 257 257 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 258 258 $DGS GLV_SYM, _tsk_cbk_accero, U, U, 0AH, 02H, 01H, 02H + 259 259 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H + 260 260 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 261 261 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 262 262 $DGS GLV_SYM, _ntr_pmic_comm, U, U, 0AH, 02H, 01H, 02H + 263 263 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H + 264 264 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H + 265 265 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 266 266 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H + 267 267 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 268 268 $DGS GLV_SYM, _iic_burst_state, U, U, 0CH, 02H, 00H, 00H + 269 269 $DGS GLV_SYM, _get_adc, U, U, 0CH, 02H, 01H, 02H + 270 270 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 271 271 + 272 272 EXTRN _iic_mcu_read_a_byte + 273 273 EXTRN _vreg_ctr + 274 274 EXTRN _system_status + 275 275 EXTRN _set_irq + 276 276 EXTRN _tsk_cbk_accero + 277 277 EXTRN _renge_task_immed_add + 278 278 EXTRN _ntr_pmic_comm + 279 279 EXTRN _iic_mcu_write_a_byte + 280 280 EXTRN _wait_ms + 281 281 EXTRN _iic_burst_state + 282 282 EXTRN _get_adc + 283 283 PUBLIC _tsk_misc_stat + 284 284 PUBLIC _do_command0 + 285 285 PUBLIC _tski_mcu_info_read + 286 286 + 287 287 ----- @@BITS BSEG + 288 288 + 289 289 ----- @@CNST CSEG MIRRORP + 290 290 00000 01 _lpf_coeff: DB 01H ; 1 + 291 291 00001 02 DB 02H ; 2 + 292 292 00002 02 DB 02H ; 2 + 293 293 00003 03 DB 03H ; 3 + 294 294 00004 03 DB 03H ; 3 + 295 295 00005 02 DB 02H ; 2 + 296 296 00006 00 DB 00H ; 0 + 297 297 00007 FE DB 0FEH ; 254 + 298 298 00008 FB DB 0FBH ; 251 + 299 299 00009 F7 DB 0F7H ; 247 + 300 300 0000A F3 DB 0F3H ; 243 + 301 301 0000B F0 DB 0F0H ; 240 + 302 302 0000C F0 DB 0F0H ; 240 + 303 303 0000D F3 DB 0F3H ; 243 + 304 304 0000E FA DB 0FAH ; 250 + 305 305 0000F 04 DB 04H ; 4 + 306 306 00010 12 DB 012H ; 18 + 307 307 00011 25 DB 025H ; 37 + 308 308 00012 38 DB 038H ; 56 + 309 309 00013 4D DB 04DH ; 77 + 310 310 00014 5F DB 05FH ; 95 + 311 311 00015 6E DB 06EH ; 110 + 312 312 00016 77 DB 077H ; 119 + 313 313 00017 7A DB 07AH ; 122 + 314 314 00018 77 DB 077H ; 119 + 315 315 00019 6E DB 06EH ; 110 + 316 316 0001A 5F DB 05FH ; 95 + 317 317 0001B 4D DB 04DH ; 77 + 318 318 0001C 38 DB 038H ; 56 + 319 319 0001D 25 DB 025H ; 37 + 320 320 0001E 12 DB 012H ; 18 + 321 321 0001F 04 DB 04H ; 4 + 322 322 00020 FA DB 0FAH ; 250 + 323 323 00021 F3 DB 0F3H ; 243 + 324 324 00022 F0 DB 0F0H ; 240 + 325 325 00023 F0 DB 0F0H ; 240 + 326 326 00024 F3 DB 0F3H ; 243 + 327 327 00025 F7 DB 0F7H ; 247 + 328 328 00026 FB DB 0FBH ; 251 + 329 329 00027 FE DB 0FEH ; 254 + 330 330 00028 00 DB 00H ; 0 + 331 331 00029 02 DB 02H ; 2 + 332 332 0002A 03 DB 03H ; 3 + 333 333 0002B 03 DB 03H ; 3 + 334 334 0002C 02 DB 02H ; 2 + 335 335 0002D 02 DB 02H ; 2 + 336 336 0002E 01 DB 01H ; 1 + 337 337 0002F 00 DB (1) + 338 338 + 339 339 ----- @@R_INIT CSEG UNIT64KP + 340 340 00000 00 DB 00H ; 0 + 341 341 00001 00 DB (1) + 342 342 + 343 343 ----- @@INIT DSEG BASEP + 344 344 00000 ?L0003: DS (1) + 345 345 00001 DS (1) + 346 346 + 347 347 ----- @@DATA DSEG BASEP + 348 348 00000 ?L0004: DS (1) + 349 349 00001 DS (1) + 350 350 + 351 351 ----- @@R_INIS CSEG UNIT64KP + 352 352 + 353 353 ----- @@INIS DSEG SADDRP + 354 354 + 355 355 ----- @@DATS DSEG SADDRP + 356 356 + 357 357 ----- @@CNSTL CSEG PAGE64KP + 358 358 + 359 359 ----- @@RLINIT CSEG UNIT64KP + 360 360 + 361 361 ----- @@INITL DSEG UNIT64KP + 362 362 + 363 363 ----- @@DATAL DSEG UNIT64KP + 364 364 + 365 365 ----- @@CALT CSEG CALLT0 + 366 366 + 367 367 ; Sub-Routines created by CC78K0R + 368 368 + 369 369 ----- ROM_CODE CSEG BASE + 370 370 00000 bs_F0060: + 371 371 00000 C1 push ax ;[INF] 1, 1 + 372 372 00001 506C mov x,#06CH ; 108 ;[INF] 2, 1 + 373 373 00003 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 374 374 00006 C0 pop ax ;[INF] 1, 1 + 375 375 00007 62 mov a,c ;[INF] 1, 1 + 376 376 00008 9F4005 mov !IICA1,a ;[INF] 3, 1 + 377 377 0000B D7 ret ;[INF] 1, 6 + 378 378 0000C es_F0060: + 379 379 + 380 380 ; *** Sub-Routine Information *** + 381 381 ; + 382 382 ; $SUB bs_F0060 + 383 383 ; CODE SIZE= 12 bytes + 384 384 + 385 385 ; End of Sub-Routines + 386 386 + 387 387 ; line 1 : #pragma SFR + 388 388 ; line 2 : #pragma NOP + 389 389 ; line 3 : #pragma HALT + 390 390 ; line 4 : #pragma STOP + 391 391 ; line 5 : + 392 392 ; line 6 : #include "incs.h" + 393 393 ; line 7 : #include "renge.h" + 394 394 ; line 8 : #include "pm.h" + 395 395 ; line 9 : + 396 396 ; line 10 : #include "accero.h" + 397 397 ; line 11 : #include "adc.h" + 398 398 ; line 12 : #include "i2c_mcu.h" + 399 399 ; line 13 : + 400 400 ; line 14 : + 401 401 ; line 15 : #ifdef _MCU_BSR_ + 402 402 ; line 16 : #define ACKD ACKD1 + 403 403 ; line 17 : #define ACKE ACKE1 + 404 404 ; line 18 : #define COI COI1 + 405 405 ; line 19 : #define IICAEN IICA1EN + 406 406 ; line 20 : #define IICRSV IICRSV1 + 407 407 ; line 21 : #define IICA IICA1 + 408 408 ; line 22 : #define IICAIF IICAIF1 + 409 409 ; line 23 : #define IICAMK IICAMK1 + 410 410 ; line 24 : #define IICAPR0 IICAPR11 + 411 411 ; line 25 : #define IICAPR1 IICAPR01 + 412 412 ; line 26 : #define IICCTL0 IICCTL10 + 413 413 ; line 27 : #define IICE IICE1 + 414 414 ; line 28 : #define IICF IICF1 + 415 415 ; line 29 : #define IICS IICS1 + 416 416 ; line 30 : #define IICWH IICWH1 + 417 417 ; line 31 : #define IICWL IICWL1 + 418 418 ; line 32 : #define LREL LREL1 + 419 419 ; line 33 : #define SPD SPD1 + 420 420 ; line 34 : #define SPIE SPIE1 + 421 421 ; line 35 : #define STCEN STCEN1 + 422 422 ; line 36 : #define STD STD1 + 423 423 ; line 37 : #define SVA SVA1 + 424 424 ; line 38 : #define WREL WREL1 + 425 425 ; line 39 : #define WTIM WTIM1 + 426 426 ; line 40 : #define TRC TRC1 + 427 427 ; line 41 : #define SMC SMC1 + 428 428 ; line 42 : #define DFC DFC1 + 429 429 ; line 43 : #endif + 430 430 ; line 44 : + 431 431 ; line 45 : + 432 432 ; line 46 : + 433 433 ; line 47 : // ======================================================== + 434 434 ; line 48 : #define INTERVAL_TSK_MISC_STAT 4 + 435 435 ; line 49 : + 436 436 ; line 50 : + 437 437 ; line 51 : /* ======================================================== + 438 438 ; line 52 : ステータスレジスタなど + 439 439 ; line 53 : ======================================================== */ + 440 440 ; line 54 : void tsk_misc_stat( ) + 441 441 ; line 55 : { + 442 442 + 443 443 ----- ROM_CODE CSEG BASE + 444 444 0000C _tsk_misc_stat: + 445 445 $DGL 1,75 + 446 446 0000C C7 push hl ;[INF] 1, 1 + 447 447 0000D ??bf_tsk_misc_stat: + 448 448 ; line 56 : static u8 interval_task_misc_stat = 0; + 449 449 ; line 57 : static u8 state_old; // ステータス変化検出→割り込み + 450 450 ; の為 + 451 451 ; line 58 : #ifdef _BL_INDEPENDENT_ + 452 452 ; line 59 : static u8 state2_old; + 453 453 ; line 60 : #endif + 454 454 ; line 61 : u8 diff; + 455 455 ; line 62 : + 456 456 ; line 63 : if( interval_task_misc_stat != 0 ) + 457 457 $DGL 0,9 + 458 458 0000D RD50000 cmp0 !?L0003 ; interval_task_misc_stat ;[INF] 3, 1 + 459 459 00010 DD06 bz $?L0005 ;[INF] 2, 4 + 460 460 ; line 64 : { + 461 461 00012 ??bb00_tsk_misc_stat: + 462 462 ; line 65 : interval_task_misc_stat -= 1; + 463 463 $DGL 0,11 + 464 464 00012 RB00000 dec !?L0003 ; interval_task_misc_stat ;[INF] 3, 2 + 465 465 ; line 66 : return; + 466 466 $DGL 0,12 + 467 467 00015 REDB700 br !?L0028 ;[INF] 3, 3 + 468 468 00018 ??eb00_tsk_misc_stat: + 469 469 ; line 67 : } + 470 470 00018 ?L0005: + 471 471 ; line 68 : else + 472 472 ; line 69 : { + 473 473 00018 ??bb01_tsk_misc_stat: + 474 474 ; line 70 : interval_task_misc_stat = ( INTERVAL_TSK_MISC_STAT / SYS + 475 475 ; _INTERVAL_TICK ); + 476 476 $DGL 0,16 + 477 477 00018 RCF000002 mov !?L0003,#02H ; interval_task_misc_stat,2 ;[INF] 4, 1 + 478 478 0001C ??eb01_tsk_misc_stat: + 479 479 ; line 71 : } + 480 480 ; line 72 : + 481 481 ; line 73 : set_bit( SHELL_OPEN, vreg_ctr[VREG_C_STATUS], REG_BIT_ST_SHE + 482 482 ; LL_OPEN ); + 483 483 $DGL 0,19 + 484 484 0001C ??bb02_tsk_misc_stat: + 485 485 0001C 31140706 bf P7.1,$?L0007 ;[INF] 4, 5 + 486 486 00020 ??bb03_tsk_misc_stat: + 487 487 00020 R71100F00 set1 !_vreg_ctr+15.1 ;[INF] 4, 2 + 488 488 00024 ??eb03_tsk_misc_stat: + 489 489 00024 EF04 br $?L0008 ;[INF] 2, 3 + 490 490 00026 ?L0007: + 491 491 00026 ??bb04_tsk_misc_stat: + 492 492 00026 R71180F00 clr1 !_vreg_ctr+15.1 ;[INF] 4, 2 + 493 493 0002A ??eb04_tsk_misc_stat: + 494 494 0002A ?L0008: + 495 495 0002A ??eb02_tsk_misc_stat: + 496 496 ; line 74 : + 497 497 ; line 75 : // ステータスレジスタ関係 → 割り込み // + 498 498 ; line 76 : if( ( system_status.pwr_state == ON ) || ( system_status.pwr + 499 499 ; _state == SLEEP ) ) + 500 500 $DGL 0,22 + 501 501 0002A R40000003 cmp !_system_status,#03H ; 3 ;[INF] 4, 1 + 502 502 0002E DD09 bz $?L0011 ;[INF] 2, 4 + 503 503 00030 R40000005 cmp !_system_status,#05H ; 5 ;[INF] 4, 1 + 504 504 00034 61E8 skz ;[INF] 2, 1 + 505 505 00036 REDB700 br !?L0028 ;[INF] 3, 3 + 506 506 00039 ?L0011: + 507 507 ; line 77 : { + 508 508 00039 ??bb05_tsk_misc_stat: + 509 509 ; line 78 : // pm.c で、その場で行います。 + 510 510 ; line 79 : // REG_BIT_LCD_ON/OFF + 511 511 ; line 80 : // REG_BIT_BL_ON/OFF + 512 512 ; line 81 : // REG_BIT_BT_DC_CONNECT/DISC + 513 513 ; line 82 : + 514 514 ; line 83 : + 515 515 ; line 84 : diff = vreg_ctr[VREG_C_STATUS] ^ state_old; + 516 516 $DGL 0,30 + 517 517 00039 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 518 518 0003C R7F0000 xor a,!?L0004 ; state_old ;[INF] 3, 1 + 519 519 0003F 76 mov l,a ;[INF] 1, 1 + 520 520 ; line 85 : if( diff != 0 ) + 521 521 $DGL 0,31 + 522 522 00040 D1 cmp0 a ;[INF] 1, 1 + 523 523 00041 DD4E bz $?L0021 ;[INF] 2, 4 + 524 524 ; line 86 : { + 525 525 00043 ??bb06_tsk_misc_stat: + 526 526 ; line 87 : state_old = vreg_ctr[VREG_C_STATUS]; + 527 527 $DGL 0,33 + 528 528 00043 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 529 529 00046 R9F0000 mov !?L0004,a ; state_old ;[INF] 3, 1 + 530 530 ; line 88 : + 531 531 ; line 89 : if( diff & REG_BIT_BATT_CHARGE ) + 532 532 $DGL 0,35 + 533 533 00049 66 mov a,l ;[INF] 1, 1 + 534 534 0004A 5C10 and a,#010H ; 16 ;[INF] 2, 1 + 535 535 0004C D1 cmp0 a ;[INF] 1, 1 + 536 536 0004D DD1E bz $?L0017 ;[INF] 2, 4 + 537 537 ; line 90 : { + 538 538 0004F ??bb07_tsk_misc_stat: + 539 539 ; line 91 : // 充電状態に以下略 + 540 540 ; line 92 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARG + 541 541 ; E ) + 542 542 $DGL 0,38 + 543 543 0004F R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 544 544 00052 5C10 and a,#010H ; 16 ;[INF] 2, 1 + 545 545 00054 D1 cmp0 a ;[INF] 1, 1 + 546 546 00055 DD0C bz $?L0016 ;[INF] 2, 4 + 547 547 ; line 93 : { + 548 548 00057 ??bb08_tsk_misc_stat: + 549 549 ; line 94 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_START ) + 550 550 ; ; + 551 551 $DGL 0,40 + 552 552 00057 308000 movw ax,#080H ; 128 ;[INF] 3, 1 + 553 553 0005A C1 push ax ;[INF] 1, 1 + 554 554 0005B 5011 mov x,#011H ; 17 ;[INF] 2, 1 + 555 555 0005D RFD0000 call !_set_irq ;[INF] 3, 3 + 556 556 00060 C0 pop ax ;[INF] 1, 1 + 557 557 00061 ??eb08_tsk_misc_stat: + 558 558 ; line 95 : } + 559 559 $DGL 0,41 + 560 560 00061 EF0A br $?L0017 ;[INF] 2, 3 + 561 561 00063 ?L0016: + 562 562 ; line 96 : else + 563 563 ; line 97 : { + 564 564 00063 ??bb09_tsk_misc_stat: + 565 565 ; line 98 : set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_STOP ); + 566 566 $DGL 0,44 + 567 567 00063 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 568 568 00066 C1 push ax ;[INF] 1, 1 + 569 569 00067 5011 mov x,#011H ; 17 ;[INF] 2, 1 + 570 570 00069 RFD0000 call !_set_irq ;[INF] 3, 3 + 571 571 0006C C0 pop ax ;[INF] 1, 1 + 572 572 0006D ??eb09_tsk_misc_stat: + 573 573 ; line 99 : } + 574 574 0006D ?L0017: + 575 575 0006D ??eb07_tsk_misc_stat: + 576 576 ; line 100 : } + 577 577 ; line 101 : + 578 578 ; line 102 : if( diff & REG_BIT_ST_SHELL_OPEN ) + 579 579 $DGL 0,48 + 580 580 0006D 66 mov a,l ;[INF] 1, 1 + 581 581 0006E 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 582 582 00070 D1 cmp0 a ;[INF] 1, 1 + 583 583 00071 DD1E bz $?L0021 ;[INF] 2, 4 + 584 584 ; line 103 : { + 585 585 00073 ??bb0A_tsk_misc_stat: + 586 586 ; line 104 : // 蓋の開け閉め + 587 587 ; line 105 : if( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_O + 588 588 ; PEN ) + 589 589 $DGL 0,51 + 590 590 00073 R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 591 591 00076 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 592 592 00078 D1 cmp0 a ;[INF] 1, 1 + 593 593 00079 DD0C bz $?L0020 ;[INF] 2, 4 + 594 594 ; line 106 : { + 595 595 0007B ??bb0B_tsk_misc_stat: + 596 596 ; line 107 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_OPEN ); + 597 597 $DGL 0,53 + 598 598 0007B 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 599 599 0007E C1 push ax ;[INF] 1, 1 + 600 600 0007F 5010 mov x,#010H ; 16 ;[INF] 2, 1 + 601 601 00081 RFD0000 call !_set_irq ;[INF] 3, 3 + 602 602 00084 C0 pop ax ;[INF] 1, 1 + 603 603 00085 ??eb0B_tsk_misc_stat: + 604 604 ; line 108 : } + 605 605 $DGL 0,54 + 606 606 00085 EF0A br $?L0021 ;[INF] 2, 3 + 607 607 00087 ?L0020: + 608 608 ; line 109 : else + 609 609 ; line 110 : { + 610 610 00087 ??bb0C_tsk_misc_stat: + 611 611 ; line 111 : set_irq( VREG_C_IRQ0, REG_BIT_SHELL_CLOSE ); + 612 612 $DGL 0,57 + 613 613 00087 302000 movw ax,#020H ; 32 ;[INF] 3, 1 + 614 614 0008A C1 push ax ;[INF] 1, 1 + 615 615 0008B 5010 mov x,#010H ; 16 ;[INF] 2, 1 + 616 616 0008D RFD0000 call !_set_irq ;[INF] 3, 3 + 617 617 00090 C0 pop ax ;[INF] 1, 1 + 618 618 00091 ??eb0C_tsk_misc_stat: + 619 619 ; line 112 : } + 620 620 00091 ?L0021: + 621 621 00091 ??eb0A_tsk_misc_stat: + 622 622 ; line 113 : } + 623 623 00091 ??eb06_tsk_misc_stat: + 624 624 ; line 114 : } + 625 625 ; line 115 : + 626 626 ; line 116 : + 627 627 ; line 117 : //#ifdef _MCU_KE3_ + 628 628 ; line 118 : // KE3では必須です。 + 629 629 ; line 119 : /* ===================================================== + 630 630 ; === + 631 631 ; line 120 : 加速度センサ割り込みピンがオリジナルマイコンには無いの + 632 632 ; で + 633 633 ; line 121 : ポーリングする。 + 634 634 ; line 122 : 歩数計用 + 635 635 ; line 123 : BSRマイコンはaccero.cで割り込みルーチンからタスク登録 + 636 636 ; します。 + 637 637 ; line 124 : ===================================================== + 638 638 ; === */ + 639 639 ; line 125 : // 割り込みの取りこぼし？ + 640 640 ; line 126 : if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 ) + 641 641 $DGL 0,72 + 642 642 00091 R8F4000 mov a,!_vreg_ctr+64 ;[INF] 3, 1 + 643 643 00094 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 644 644 00096 D1 cmp0 a ;[INF] 1, 1 + 645 645 00097 DD13 bz $?L0026 ;[INF] 2, 4 + 646 646 ; line 127 : { + 647 647 00099 ??bb0D_tsk_misc_stat: + 648 648 ; line 128 : if( ACC_VALID ) + 649 649 $DGL 0,74 + 650 650 00099 C7 push hl ;[INF] 1, 1 + 651 651 0009A 361005 movw hl,#0510H ; 1296 ;[INF] 3, 1 + 652 652 0009D 71D4 mov1 CY,[hl].5 ;[INF] 2, 1 + 653 653 0009F C6 pop hl ;[INF] 1, 1 + 654 654 000A0 DE0A bnc $?L0026 ;[INF] 2, 4 + 655 655 ; line 129 : { + 656 656 000A2 ??bb0E_tsk_misc_stat: + 657 657 ; line 130 : if( renge_task_immed_add( tsk_cbk_accero ) == ER + 658 658 ; R_SUCCESS ){ + 659 659 $DGL 0,76 + 660 660 000A2 R300000 movw ax,#loww (_tsk_cbk_accero) ;[INF] 3, 1 + 661 661 000A5 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 662 662 000A8 D2 cmp0 c ;[INF] 1, 1 + 663 663 000A9 61F8 sknz ;[INF] 2, 1 + 664 664 000AB ??bb0F_tsk_misc_stat: + 665 665 ; line 131 : NOP(); + 666 666 $DGL 0,77 + 667 667 000AB 00 nop ;[INF] 1, 1 + 668 668 000AC ??eb0F_tsk_misc_stat: + 669 669 ; line 132 : } + 670 670 000AC ?L0026: + 671 671 000AC ??eb0E_tsk_misc_stat: + 672 672 ; line 133 : } + 673 673 000AC ??eb0D_tsk_misc_stat: + 674 674 ; line 134 : } + 675 675 ; line 135 : //#endif + 676 676 ; line 136 : + 677 677 ; line 137 : // 割り込みの取りこぼし？ + 678 678 ; line 138 : if( !PM_IRQ_n ){ + 679 679 $DGL 0,84 + 680 680 000AC 31220707 bt P7.2,$?L0028 ;[INF] 4, 5 + 681 681 000B0 ??bb10_tsk_misc_stat: + 682 682 ; line 139 : renge_task_immed_add( ntr_pmic_comm ); + 683 683 $DGL 0,85 + 684 684 000B0 R300000 movw ax,#loww (_ntr_pmic_comm) ;[INF] 3, 1 + 685 685 000B3 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 686 686 ; line 140 : NOP(); + 687 687 $DGL 0,86 + 688 688 000B6 00 nop ;[INF] 1, 1 + 689 689 000B7 ??eb10_tsk_misc_stat: + 690 690 ; line 141 : } + 691 691 000B7 ?L0028: + 692 692 000B7 ??eb05_tsk_misc_stat: + 693 693 ; line 142 : } + 694 694 ; line 143 : return; + 695 695 ; line 144 : } + 696 696 $DGL 0,90 + 697 697 000B7 ??ef_tsk_misc_stat: + 698 698 000B7 C6 pop hl ;[INF] 1, 1 + 699 699 000B8 D7 ret ;[INF] 1, 6 + 700 700 000B9 ??ee_tsk_misc_stat: + 701 701 ; line 145 : + 702 702 ; line 146 : + 703 703 ; line 147 : + 704 704 ; line 148 : + 705 705 ; line 149 : + 706 706 ; line 150 : /* ======================================================== + 707 707 ; line 151 : 逐一起動タスク + 708 708 ; line 152 : ======================================================== */ + 709 709 ; line 153 : + 710 710 ; line 154 : /* ======================================================== + 711 711 ; line 155 : COMMANDレジスタへの書き込み + 712 712 ; line 156 : 　 0なら呼ばれません。ケア不要 + 713 713 ; line 157 : ======================================================== */ + 714 714 ; line 158 : task_status_immed do_command0( ) + 715 715 ; line 159 : { + 716 716 000B9 _do_command0: + 717 717 $DGL 1,152 + 718 718 000B9 ??bf_do_command0: + 719 719 ; line 160 : // command0 本体電源など + 720 720 ; line 161 : if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BI + 721 721 ; T_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) ! + 722 722 ; = 0x00 ) + 723 723 $DGL 0,3 + 724 724 000B9 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 + 725 725 000BC 5C0F and a,#0FH ; 15 ;[INF] 2, 1 + 726 726 000BE D1 cmp0 a ;[INF] 1, 1 + 727 727 000BF DD5D bz $?L0035 ;[INF] 2, 4 + 728 728 ; line 162 : { + 729 729 000C1 ??bb00_do_command0: + 730 730 ; line 163 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ ) + 731 731 $DGL 0,5 + 732 732 000C1 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 + 733 733 000C4 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 734 734 000C6 D1 cmp0 a ;[INF] 1, 1 + 735 735 000C7 DD05 bz $?L0034 ;[INF] 2, 4 + 736 736 ; line 164 : { + 737 737 000C9 ??bb01_do_command0: + 738 738 ; line 165 : system_status.pwr_state = OFF_TRIG; + 739 739 $DGL 0,7 + 740 740 000C9 RF50000 clrb !_system_status ;[INF] 3, 1 + 741 741 000CC ??eb01_do_command0: + 742 742 ; line 166 : } + 743 743 $DGL 0,8 + 744 744 000CC EF50 br $?L0035 ;[INF] 2, 3 + 745 745 000CE ?L0034: + 746 746 ; line 167 : else + 747 747 ; line 168 : { + 748 748 000CE ??bb02_do_command0: + 749 749 ; line 169 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ ) + 750 750 $DGL 0,11 + 751 751 000CE R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 + 752 752 000D1 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 753 753 000D3 D1 cmp0 a ;[INF] 1, 1 + 754 754 000D4 DD15 bz $?L0036 ;[INF] 2, 4 + 755 755 ; line 170 : { + 756 756 000D6 ??bb03_do_command0: + 757 757 ; line 171 : PM_reset_ast( ); + 758 758 $DGL 0,13 + 759 759 000D6 E6 onew ax ;[INF] 1, 1 + 760 760 000D7 C1 push ax ;[INF] 1, 1 + 761 761 000D8 A1 incw ax ;[INF] 1, 1 + 762 762 000D9 A1 incw ax ;[INF] 1, 1 + 763 763 000DA C1 push ax ;[INF] 1, 1 + 764 764 000DB 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 765 765 000DD RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 766 766 000E0 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 767 767 ; line 172 : RESET2_ast; + 768 768 $DGL 0,14 + 769 769 000E2 ??bb04_do_command0: + 770 770 000E2 711300 clr1 P0.1 ;[INF] 3, 2 + 771 771 000E5 711B20 clr1 PM0.1 ;[INF] 3, 2 + 772 772 000E8 ??eb04_do_command0: + 773 773 ; line 173 : FCRAM_RST_ast; + 774 774 $DGL 0,15 + 775 775 000E8 ??bb05_do_command0: + 776 776 000E8 710303 clr1 P3.0 ;[INF] 3, 2 + 777 777 000EB ??eb05_do_command0: + 778 778 000EB ??eb03_do_command0: + 779 779 ; line 174 : } + 780 780 000EB ?L0036: + 781 781 ; line 175 : if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_ + 782 782 ; REQ ) + 783 783 $DGL 0,17 + 784 784 000EB R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 + 785 785 000EE 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 786 786 000F0 D1 cmp0 a ;[INF] 1, 1 + 787 787 000F1 DD05 bz $?L0038 ;[INF] 2, 4 + 788 788 ; line 176 : { + 789 789 000F3 ??bb06_do_command0: + 790 790 ; line 177 : FCRAM_RST_ast; + 791 791 $DGL 0,19 + 792 792 000F3 ??bb07_do_command0: + 793 793 000F3 710303 clr1 P3.0 ;[INF] 3, 2 + 794 794 000F6 ??eb07_do_command0: + 795 795 000F6 ??eb06_do_command0: + 796 796 ; line 178 : } + 797 797 $DGL 0,20 + 798 798 000F6 EF0E br $?L0040 ;[INF] 2, 3 + 799 799 000F8 ?L0038: + 800 800 ; line 179 : else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_ + 801 801 ; REQ ) + 802 802 $DGL 0,21 + 803 803 000F8 R8F2000 mov a,!_vreg_ctr+32 ;[INF] 3, 1 + 804 804 000FB 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 805 805 000FD D1 cmp0 a ;[INF] 1, 1 + 806 806 000FE DD06 bz $?L0040 ;[INF] 2, 4 + 807 807 ; line 180 : { + 808 808 00100 ??bb08_do_command0: + 809 809 ; line 181 : RESET2_ast; + 810 810 $DGL 0,23 + 811 811 00100 ??bb09_do_command0: + 812 812 00100 711300 clr1 P0.1 ;[INF] 3, 2 + 813 813 00103 711B20 clr1 PM0.1 ;[INF] 3, 2 + 814 814 00106 ??eb09_do_command0: + 815 815 00106 ??eb08_do_command0: + 816 816 ; line 182 : } + 817 817 00106 ?L0040: + 818 818 ; line 183 : wait_ms( 5 ); + 819 819 $DGL 0,25 + 820 820 00106 300500 movw ax,#05H ; 5 ;[INF] 3, 1 + 821 821 00109 RFD0000 call !_wait_ms ;[INF] 3, 3 + 822 822 ; line 184 : FCRAM_RST_neg; + 823 823 $DGL 0,26 + 824 824 0010C ??bb0A_do_command0: + 825 825 0010C 710203 set1 P3.0 ;[INF] 3, 2 + 826 826 0010F ??eb0A_do_command0: + 827 827 ; line 185 : PM_reset_neg(); + 828 828 $DGL 0,27 + 829 829 0010F 300300 movw ax,#03H ; 3 ;[INF] 3, 1 + 830 830 00112 C1 push ax ;[INF] 1, 1 + 831 831 00113 C1 push ax ;[INF] 1, 1 + 832 832 00114 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 833 833 00116 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 834 834 00119 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 835 835 ; line 186 : RESET2_neg; + 836 836 $DGL 0,28 + 837 837 0011B ??bb0B_do_command0: + 838 838 0011B 711A20 set1 PM0.1 ;[INF] 3, 2 + 839 839 0011E ??eb0B_do_command0: + 840 840 0011E ??eb02_do_command0: + 841 841 ; line 187 : /* + 842 842 ; line 188 : // CODEC 不定レジスタ初期化 + 843 843 ; line 189 : wait_ms( 100 ); + 844 844 ; line 190 : { + 845 845 ; line 191 : u8 codec_reg_init[3] = { 0,0,0 }; + 846 846 ; line 192 : iic_mcu_write( IIC_SLA_CODEC, CODEC_REG_PM, 3, c + 847 847 ; odec_reg_init ); + 848 848 ; line 193 : } + 849 849 ; line 194 : */ + 850 850 ; line 195 : } + 851 851 0011E ?L0035: + 852 852 0011E ??eb00_do_command0: + 853 853 ; line 196 : } + 854 854 ; line 197 : + 855 855 ; line 198 : vreg_ctr[VREG_C_COMMAND0] = 0; + 856 856 $DGL 0,40 + 857 857 0011E RF52000 clrb !_vreg_ctr+32 ;[INF] 3, 1 + 858 858 ; line 199 : return ( ERR_FINISED ); + 859 859 $DGL 0,41 + 860 860 00121 F7 clrw bc ;[INF] 1, 1 + 861 861 ; line 200 : } + 862 862 $DGL 0,42 + 863 863 00122 ??ef_do_command0: + 864 864 00122 D7 ret ;[INF] 1, 6 + 865 865 00123 ??ee_do_command0: + 866 866 ; line 201 : + 867 867 ; line 202 : + 868 868 ; line 203 : + 869 869 ; line 204 : /* ======================================================== + 870 870 ; line 205 : 　互換向け、TWLアプリへの割り込み + 871 871 ; line 206 : 仮想レジスタの書き込み時に行います。 + 872 872 ; line 207 : ======================================================== */ + 873 873 ; line 208 : // task_status_immed do_command1( ) + 874 874 ; line 209 : + 875 875 ; line 210 : + 876 876 ; line 211 : extern u8 iic_burst_state; + 877 877 ; line 212 : /* ======================================================== + 878 878 ; line 213 : 　デバッグ用にいろいろ読んできます。 + 879 879 ; line 214 : 　返値はデータそのもの + 880 880 ; line 215 : ======================================================== */ + 881 881 ; line 216 : task_status_immed tski_mcu_info_read() + 882 882 ; line 217 : { + 883 883 00123 _tski_mcu_info_read: + 884 884 $DGL 1,206 + 885 885 00123 C7 push hl ;[INF] 1, 1 + 886 886 00124 ??bf_tski_mcu_info_read: + 887 887 ; line 218 : u8 temp; + 888 888 ; line 219 : + 889 889 ; line 220 : + 890 890 ; line 221 : if( SPD ) + 891 891 $DGL 0,5 + 892 892 00124 C7 push hl ;[INF] 1, 1 + 893 893 00125 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 894 894 00128 7184 mov1 CY,[hl].0 ;[INF] 2, 1 + 895 895 0012A C6 pop hl ;[INF] 1, 1 + 896 896 0012B DC6E bc $?L0046 ;[INF] 2, 4 + 897 897 ; line 222 : { + 898 898 0012D ??bb00_tski_mcu_info_read: + 899 899 ; line 223 : goto end; + 900 900 0012D ??eb00_tski_mcu_info_read: + 901 901 ; line 224 : } + 902 902 ; line 225 : + 903 903 ; line 226 : if( STD ) + 904 904 $DGL 0,10 + 905 905 0012D C7 push hl ;[INF] 1, 1 + 906 906 0012E 364105 movw hl,#0541H ; 1345 ;[INF] 3, 1 + 907 907 00131 7194 mov1 CY,[hl].1 ;[INF] 2, 1 + 908 908 00133 C6 pop hl ;[INF] 1, 1 + 909 909 00134 61D8 sknc ;[INF] 2, 1 + 910 910 ; line 227 : { + 911 911 00136 ??bb01_tski_mcu_info_read: + 912 912 ; line 228 : SPIE = 1; + 913 913 $DGL 0,12 + 914 914 00136 71405005 set1 !IICCTL01.4 ;[INF] 4, 2 + 915 915 0013A ??eb01_tski_mcu_info_read: + 916 916 ; line 229 : } + 917 917 0013A ?L0047: + 918 918 ; line 230 : + 919 919 ; line 231 : if( IICAIF == 0 ) + 920 920 $DGL 0,15 + 921 921 0013A 31B2D103 bt IF2H.3,$?L0049 ;[INF] 4, 5 + 922 922 ; line 232 : { + 923 923 0013E ??bb02_tski_mcu_info_read: + 924 924 ; line 233 : return( ERR_CONTINUE ); + 925 925 $DGL 0,17 + 926 926 0013E E7 onew bc ;[INF] 1, 1 + 927 927 0013F EF69 br $?L0043 ;[INF] 2, 3 + 928 928 00141 ??eb02_tski_mcu_info_read: + 929 929 ; line 234 : } + 930 930 00141 ?L0049: + 931 931 ; line 235 : else + 932 932 ; line 236 : { + 933 933 00141 ??bb03_tski_mcu_info_read: + 934 934 ; line 237 : IICAIF = 0; + 935 935 $DGL 0,21 + 936 936 00141 713BD1 clr1 IF2H.3 ;[INF] 3, 2 + 937 937 00144 ??eb03_tski_mcu_info_read: + 938 938 ; line 238 : } + 939 939 ; line 239 : + 940 940 ; line 240 : switch( iic_burst_state++ ){ + 941 941 $DGL 0,24 + 942 942 00144 R8F0000 mov a,!_iic_burst_state ;[INF] 3, 1 + 943 943 00147 RA00000 inc !_iic_burst_state ;[INF] 3, 2 + 944 944 0014A 318E shrw ax,8 ;[INF] 2, 1 + 945 945 0014C E7 onew bc ;[INF] 1, 1 + 946 946 0014D 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 947 947 00150 DD0E bz $?L0052 ;[INF] 2, 4 + 948 948 00152 23 subw ax,bc ;[INF] 1, 1 + 949 949 00153 DD13 bz $?L0053 ;[INF] 2, 4 + 950 950 00155 23 subw ax,bc ;[INF] 1, 1 + 951 951 00156 DD1E bz $?L0054 ;[INF] 2, 4 + 952 952 00158 23 subw ax,bc ;[INF] 1, 1 + 953 953 00159 DD2F bz $?L0055 ;[INF] 2, 4 + 954 954 0015B 23 subw ax,bc ;[INF] 1, 1 + 955 955 0015C DD34 bz $?L0056 ;[INF] 2, 4 + 956 956 0015E EF3B br $?L0046 ;[INF] 2, 3 + 957 957 00160 ??bb04_tski_mcu_info_read: + 958 958 ; line 241 : case( 0 ): // 本体種類識別 + 959 959 00160 ?L0052: + 960 960 ; line 242 : IICA = (u8)system_status.model; + 961 961 $DGL 0,26 + 962 962 00160 R8F0300 mov a,!_system_status+3 ;[INF] 3, 1 + 963 963 00163 9F4005 mov !IICA1,a ;[INF] 3, 1 + 964 964 ; line 243 : break; + 965 965 $DGL 0,27 + 966 966 00166 EF30 br $?L0051 ;[INF] 2, 3 + 967 967 ; line 244 : + 968 968 ; line 245 : case( 1 ): // IICがなにかエラーでも知らない。00かFFな + 969 969 ; らエラーの可能性が高い + 970 970 00168 ?L0053: + 971 971 ; line 246 : IICA = iic_mcu_read_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_VE + 972 972 ; R ); + 973 973 $DGL 0,30 + 974 974 00168 F6 clrw ax ;[INF] 1, 1 + 975 975 00169 C1 push ax ;[INF] 1, 1 + 976 976 0016A 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 977 977 0016C RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 978 978 0016F C0 pop ax ;[INF] 1, 1 + 979 979 00170 62 mov a,c ;[INF] 1, 1 + 980 980 00171 9F4005 mov !IICA1,a ;[INF] 3, 1 + 981 981 ; line 247 : break; + 982 982 $DGL 0,31 + 983 983 00174 EF22 br $?L0051 ;[INF] 2, 3 + 984 984 ; line 248 : + 985 985 ; line 249 : case( 2 ): // 電池メーカーの識別 + 986 986 00176 ?L0054: + 987 987 ; line 250 : BT_DET_P = 1; + 988 988 $DGL 0,34 + 989 989 00176 716201 set1 P1.6 ;[INF] 3, 2 + 990 990 ; line 251 : IICA = ( u8 ) ( get_adc( ADC_SEL_BATT_DET ) >> 5 ); + 991 991 $DGL 0,35 + 992 992 00179 300900 movw ax,#09H ; 9 ;[INF] 3, 1 + 993 993 0017C RFD0000 call !_get_adc ;[INF] 3, 3 + 994 994 0017F 62 mov a,c ;[INF] 1, 1 + 995 995 00180 315A shr a,5 ;[INF] 2, 1 + 996 996 00182 9F4005 mov !IICA1,a ;[INF] 3, 1 + 997 997 ; line 252 : BT_DET_P = 0; + 998 998 $DGL 0,36 + 999 999 00185 716301 clr1 P1.6 ;[INF] 3, 2 + 1000 1000 ; line 253 : break; + 1001 1001 $DGL 0,37 + 1002 1002 00188 EF0E br $?L0051 ;[INF] 2, 3 + 1003 1003 ; line 254 : + 1004 1004 ; line 255 : case( 3 ): // ガスゲージバージョン + 1005 1005 0018A ?L0055: + 1006 1006 ; line 256 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R + 1007 1007 ; EG_VERSION ); + 1008 1008 $DGL 0,40 + 1009 1009 0018A 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 1010 1010 0018D RFD0000 call !bs_F0060 ;[INF] 3, 3 + 1011 1011 ; line 257 : break; + 1012 1012 $DGL 0,41 + 1013 1013 00190 EF06 br $?L0051 ;[INF] 2, 3 + 1014 1014 ; line 258 : + 1015 1015 ; line 259 : case( 4 ): // LSB + 1016 1016 00192 ?L0056: + 1017 1017 ; line 260 : IICA = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_R + 1018 1018 ; EG_VERSION + 1 ); + 1019 1019 $DGL 0,44 + 1020 1020 00192 300900 movw ax,#09H ; 9 ;[INF] 3, 1 + 1021 1021 00195 RFD0000 call !bs_F0060 ;[INF] 3, 3 + 1022 1022 ; line 261 : break; + 1023 1023 ; line 262 : + 1024 1024 ; line 263 : default: + 1025 1025 ; line 264 : goto end; + 1026 1026 00198 ??eb04_tski_mcu_info_read: + 1027 1027 ; line 265 : } + 1028 1028 00198 ?L0051: + 1029 1029 ; line 266 : return( ERR_CONTINUE ); + 1030 1030 $DGL 0,50 + 1031 1031 00198 E7 onew bc ;[INF] 1, 1 + 1032 1032 00199 EF0F br $?L0043 ;[INF] 2, 3 + 1033 1033 ; line 267 : + 1034 1034 ; line 268 : end: + 1035 1035 0019B ?L0046: + 1036 1036 ; line 269 : LREL = 1; + 1037 1037 $DGL 0,53 + 1038 1038 0019B 71605005 set1 !IICCTL01.6 ;[INF] 4, 2 + 1039 1039 ; line 270 : SPIE = 0; + 1040 1040 $DGL 0,54 + 1041 1041 0019F 71485005 clr1 !IICCTL01.4 ;[INF] 4, 2 + 1042 1042 ; line 271 : IICAMK = 0; + 1043 1043 $DGL 0,55 + 1044 1044 001A3 713BD5 clr1 MK2H.3 ;[INF] 3, 2 + 1045 1045 ; line 272 : iic_burst_state = 0; + 1046 1046 $DGL 0,56 + 1047 1047 001A6 RF50000 clrb !_iic_burst_state ;[INF] 3, 1 + 1048 1048 ; line 273 : return( ERR_FINISED ); + 1049 1049 $DGL 0,57 + 1050 1050 001A9 F7 clrw bc ;[INF] 1, 1 + 1051 1051 ; line 274 : } + 1052 1052 001AA ?L0043: + 1053 1053 $DGL 0,58 + 1054 1054 001AA ??ef_tski_mcu_info_read: + 1055 1055 001AA C6 pop hl ;[INF] 1, 1 + 1056 1056 001AB D7 ret ;[INF] 1, 6 + 1057 1057 001AC ??ee_tski_mcu_info_read: + 1058 1058 + 1059 1059 ----- @@CODEL CSEG + 1060 1060 + 1061 1061 ----- @@BASE CSEG BASE + 1062 1062 END + 1063 1063 + 1064 1064 + 1065 1065 ; *** Code Information *** + 1066 1066 ; + 1067 1067 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c + 1068 1068 ; + 1069 1069 ; $FUNC tsk_misc_stat(55) + 1070 1070 ; void=(void) + 1071 1071 ; CODE SIZE= 173 bytes, CLOCK_SIZE= 145 clocks, STACK_SIZE= 8 bytes + 1072 1072 ; + 1073 1073 ; $CALL set_irq(94) + 1074 1074 ; void=(int:ax, int:[sp+4]) + 1075 1075 ; + 1076 1076 ; $CALL set_irq(98) + 1077 1077 ; void=(int:ax, int:[sp+4]) + 1078 1078 ; + 1079 1079 ; $CALL set_irq(107) + 1080 1080 ; void=(int:ax, int:[sp+4]) + 1081 1081 ; + 1082 1082 ; $CALL set_irq(111) + 1083 1083 ; void=(int:ax, int:[sp+4]) + 1084 1084 ; + 1085 1085 ; $CALL renge_task_immed_add(130) + 1086 1086 ; bc=(pointer:ax) + 1087 1087 ; + 1088 1088 ; $CALL renge_task_immed_add(139) + 1089 1089 ; bc=(pointer:ax) + 1090 1090 ; + 1091 1091 ; $FUNC do_command0(159) + 1092 1092 ; bc=(void) + 1093 1093 ; CODE SIZE= 106 bytes, CLOCK_SIZE= 88 clocks, STACK_SIZE= 8 bytes + 1094 1094 ; + 1095 1095 ; $CALL iic_mcu_write_a_byte(171) + 1096 1096 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1097 1097 ; + 1098 1098 ; $CALL wait_ms(183) + 1099 1099 ; void=(int:ax) + 1100 1100 ; + 1101 1101 ; $CALL iic_mcu_write_a_byte(185) + 1102 1102 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1103 1103 ; + 1104 1104 ; $FUNC tski_mcu_info_read(217) + 1105 1105 ; bc=(void) + 1106 1106 ; CODE SIZE= 137 bytes, CLOCK_SIZE= 149 clocks, STACK_SIZE= 12 bytes + 1107 1107 ; + 1108 1108 ; $CALL iic_mcu_read_a_byte(246) + 1109 1109 ; bc=(int:ax, int:[sp+4]) + 1110 1110 ; + 1111 1111 ; $CALL get_adc(251) + 1112 1112 ; bc=(int:ax) + 1113 1113 ; + 1114 1114 ; $CALL iic_mcu_read_a_byte(256) + 1115 1115 ; bc=(int:ax, int:[sp+4]) + 1116 1116 ; + 1117 1117 ; $CALL iic_mcu_read_a_byte(260) + 1118 1118 ; bc=(int:ax, int:[sp+4]) + 1119 1119 + 1120 1120 ; Target chip : uPD79F0104 + 1121 1121 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00002H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 001ACH ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/task_misc.rel b/branches/0.10(X3)/task_misc.rel new file mode 100644 index 0000000..6946f9d Binary files /dev/null and b/branches/0.10(X3)/task_misc.rel differ diff --git a/branches/0.10(X3)/task_sys.c b/branches/0.10(X3)/task_sys.c new file mode 100644 index 0000000..8c754f4 --- /dev/null +++ b/branches/0.10(X3)/task_sys.c @@ -0,0 +1,388 @@ +#pragma SFR +#pragma NOP +#pragma HALT +#pragma STOP + +#include "incs.h" + +#include "i2c_twl.h" +#include "i2c_ctr.h" +#include "led.h" +#include "accero.h" +#include "pm.h" +#include "rtc.h" +#include "sw.h" +#include "adc.h" + + + +//========================================================= +static void chk_emergencyExit(); + + + +//========================================================= + + + +/* ======================================================== + マイコン内部で必要なもの +・省電力に入れる + 　system_status.pwr_state == OFF_TRIG で、このタスクが呼ばれると、 + 省電力モードに入ります + ======================================================== */ +void tsk_sys( ) +{ + static u8 timeout = 0; + + switch ( system_status.pwr_state ) + { + case OFF: //------------------------------------------------------- + // スイッチ操作などで割り込みが発生し、スリープが解除されるとここに来ます。 + +#ifndef _PARRADIUM_ + switch ( system_status.poweron_reason ) + { + default: + // スイッチで電源on + + if( SW_pow_count != 0 ) + { + timeout = 0; + } + else + { + timeout += 1; + } + if( timeout > 127 ) + { + system_status.pwr_state = OFF_TRIG; // スイッチはノイズだった。寝る。 + renge_task_interval_run_force = 1; + return; + } + + if( SW_pow_count < 3 ) + { + // もう少しスイッチの様子を見る + return; + } + // 電源投入 + system_status.poweron_reason = PWSW; + break; + + case ( RTC_ALARM ): + break; + } + + timeout = 0; + + // 電源投入 // + iic_mcu_start( ); + + // ↓で電池残量ICの起動待ちウェイトなどがあります。 + PM_init( ); // 電池残量ICの設定 + + if( PM_sys_pow_on( ) != ERR_SUCCESS ) + { // 電源起動不可エラー + renge_task_interval_run_force = 1; + iic_mcu_stop( ); + system_status.pwr_state = OFF_TRIG; + return; + } + PM_CHG_TIMEOUT_ENABLE(); +// IRQ0_active; + +#else + vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; + system_status.poweron_reason = PWSW; +#endif // _PARADDIUM_ + + PM_LCD_vcom_set( ); // LCDの対向電圧値など書き込み +#ifdef _PMIC_TWL_ + PM_TEG_LCD_dis( 0 ); +#endif + + if( system_status.poweron_reason == PWSW ) + { + // 電源ボタンでのonの時は、LEDを点灯させる + vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; + } + else + { + // とりあえず、LED消灯状態で起動させる + vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; + // todo? + } + system_status.pwr_state = ON_TRIG; + // ここまで来ると、電源投入確定 + break; + + case ON_TRIG: //------------------------------------------------------- + + LED_init( ); + + PU7 = 0b00011101; // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_EXTDC_n + + IIC_ctr_Init( ); + if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT_RESET ) +/* + if( vreg_ctr[ VREG_C_IRQ0 ] + | vreg_ctr[ VREG_C_IRQ0 ] + | vreg_ctr[ VREG_C_IRQ0 ] + | vreg_ctr[ VREG_C_IRQ0 ] +*/ + != 0 ) + { + set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); + } + IIC_twl_Init( ); + RTC_32k_on( ); + + KRM = 0b00000000; + + system_status.poweron_reason = NONE; + renge_task_interval_run_force = 1; + + MK0 = INT_MSK0_RSV; + MK1 = INT_MSK1_RSV; +#ifdef _MCU_BSR_ +// MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT_MSK2_CODEC_PMIRQ ); +// PMK21 = 0; // wifi 使わない + PMK6 = 0; // pm_irq +#else + MK2L = ~INT_MSK2_WIFI_TX_KE3; +#endif + + system_status.reboot = 0; + system_status.pwr_state = ON; + break; + + case ON: //--------------------------------------------- + // PMICによる強制電源断チェック + // デバッガがreset1をアサートすることもある。そのときは全部リセット + chk_emergencyExit(); + + // SLP監視 + if( SLP_REQ ){ + system_status.pwr_state = SLEEP_TRIG; + renge_task_interval_run_force = 1; + } + break; + + case SLEEP_TRIG: //------------------------------------- + PM_VDD_ecoMode(); + system_status.pwr_state = SLEEP; + break; + + case SLEEP: //------------------------------------------ + chk_emergencyExit(); + // スリープから復帰 + if( !SLP_REQ ){ + PM_VDD_normMode(); + wait_ms( 5 ); // tdly_sw + +#ifdef _MODEL_CTR_ + SLP_ACK = 1; + NOP(); // 適当ウェイト + NOP(); + NOP(); + NOP(); + SLP_ACK = 0; +#endif + + system_status.pwr_state = ON_TRIG; + renge_task_interval_run_force = 1; + } + + break; + + case OFF_TRIG: //--------------------------------------- + // LED消灯を待つ + vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; + if(( LED_duty_pow_H != 0 ) || ( LED_duty_pow_L != 0 )) + { + return; + } + + PM_CHG_TIMEOUT_ENABLE(); + LED_stop( ); + IIC_ctr_Stop( ); + IIC_twl_Stop( ); + RTC_32k_off(); + + vreg_ctr[VREG_C_IRQ0] = 0; + vreg_ctr[VREG_C_IRQ1] = 0; + vreg_ctr[VREG_C_IRQ2] = 0; + vreg_ctr[VREG_C_IRQ3] = 0; + +// 電源オン条件の割り込みセット +// PWSW KR3 押すとL +// BG24 KR4 +// ふた開け INTP5 閉じるとL +// ACアダプタ INTP4 アダプタありでL +// RTC + +#ifdef _PMIC_TWL_ + PM_TEG_LCD_dis( 1 ); +#endif +// IRQ0_deactive; + // pullup_off(); ↓ + { + PU5 = 0b00000011; // PM_CHG,PM_CHGERR + PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC + } + + PM_sys_pow_off( ); + + KRM = ( KR_SW_POW ); // Mask ではなく、Modeなのだそうだ。紛らわしい + // intp20系は後ほど + MK0 = ~( INT_MSK0_EXTDC ); + MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCALARM | INT_MSK1_RTCINTVAL ); + MK2L = 0b11111111; + + IF0 = 0; + IF1 = 0; + IF2 = 0; + + timeout = 0; + + system_status.pwr_state = BT_CHARGE; + SW_pow_count = 0; + SW_wifi_count = 0; + // no break // + + case BT_CHARGE: + if( !PM_EXTDC_n ) + { + // アダプタ有り：充電温度監視 + BT_TEMP_P = 1; + + // 電源on？ + if( ( SW_pow_count > 3 ) || ( SW_wifi_count > 3 ) + || ( system_status.poweron_reason == RTC_ALARM ) ) + { + system_status.pwr_state = OFF; // 若干抵抗有るが... + renge_task_interval_run_force = 1; + KRMK = 1; + return; + } + return; + } + else + { + // 省電力へ移行 + BT_TEMP_P = 0; + while( RWST ) + {;} + + iic_mcu_stop( ); + + // 割り込み待ちで寝る // + RTCIMK = 1; +#ifndef _PARRADIUM_ + +#ifdef _MCU_BSR_ + CKC = 0b00001001; + OSMC = 0x00; +#endif + STOP( ); +#ifdef _MCU_BSR_ + OSMC = 0x01; + CKC = 0b00001000; +#endif + +#endif + RTCIMK = 0; + // 起きる // + + // 起きる条件は + // ・KeyReturn割り込み（電源ボたん） + // ・RTCアラーム + // ・アダプタ挿抜 + system_status.pwr_state = OFF; // + renge_task_interval_run_force = 1; + KRMK = 1; + return; + } + + default: + while( 1 ) + { + NOP( ); + // あり得ないステート + } + + } +} + + + +/*******************************************************//** + PMICが電源異常で止めたか確認 + **********************************************************/ +static void chk_emergencyExit(){ +#ifndef _PARRADIUM_ + static state; + + if( !RESET1_n ) + { + if( PM_chk_LDSW( ) == 0 ) + { + // PMICが異常終了判断をした + system_status.pwr_state = OFF_TRIG; + renge_task_interval_run_force = 1; + } + else + { + if( state == 0 ) + { + state = 1; + // デバッガなりがリセットをかけた + iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, 0 ); + vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & 0b10011111 ); + vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ; + renge_task_immed_add( do_command0 ); + } + } + } + else + { + state = 0; + } +#endif +} + + + + + +/* ======================================================== + CPUからのスリープ要求 + 　ポーリングにしました。 + ======================================================== */ + /* +__interrupt void intp0_slp( ) +{ // SLP + if( SLP_REQ ){ + system_status.pwr_state = SLEEP_TRIG; + }else{ + system_status.pwr_state = ON_TRIG; + if( PM_BL_set() != ERR_SUCCESS ){ + renge_task_interval_run_force = 1; + iic_mcu_stop(); + system_status.pwr_state = OFF_TRIG; + } + } + renge_task_interval_run_force = 1; +} + */ + + + +/*******************************************************//** + 全く意味ないですが、気分的な物で... + **********************************************************/ +task_status_immed tski_firm_update(){ + firm_update(); + return( ERR_SUCCESS ); +} diff --git a/branches/0.10(X3)/task_sys.prn b/branches/0.10(X3)/task_sys.prn new file mode 100644 index 0000000..f3f16de --- /dev/null +++ b/branches/0.10(X3)/task_sys.prn @@ -0,0 +1,1363 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_sys.asm +Para-file: +In-file: inter_asm\task_sys.asm +Obj-file: task_sys.rel +Prn-file: task_sys.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_sys.c + 6 6 ; In-file : task_sys.c + 7 7 ; Asm-file : inter_asm\task_sys.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0C7H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, task_sys.c + 18 18 $DGS MOD_NAM, task_sys, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 01EH + 37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H + 44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 45 45 $DGS AUX_EOS, 013H, 01H + 46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 47 47 $DGS AUX_TAG, 01H, 025H + 48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 52 52 $DGS AUX_EOS, 01EH, 01H + 53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 54 54 $DGS AUX_TAG, 01H, 02FH + 55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H + 58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H + 59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H + 60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H + 61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 62 62 $DGS AUX_EOS, 025H, 01H + 63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H + 64 64 $DGS AUX_TAG, 04H, 041H + 65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H + 66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H + 68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H + 70 70 $DGS AUX_BIT, 00H, 01H + 71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H + 72 72 $DGS AUX_BIT, 00H, 01H + 73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H + 74 74 $DGS AUX_BIT, 00H, 01H + 75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H + 76 76 $DGS AUX_BIT, 00H, 01H + 77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H + 78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H + 79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H + 80 80 $DGS AUX_EOS, 02FH, 04H + 81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 82 82 $DGS AUX_TAG, 01H, 047H + 83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 86 86 $DGS AUX_EOS, 041H, 01H + 87 87 $DGS LAB_SYM, bs_F0057, U, U, 00H, 06H, 00H, 00H + 88 88 $DGS LAB_SYM, es_F0057, U, U, 00H, 06H, 00H, 00H + 89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 91 91 $DGS GLV_SYM, _tsk_sys, U, U, 01H, 026H, 01H, 02H + 92 92 $DGS AUX_FUN, 00H, U, U, 0A6H, 00H, 00H + 93 93 $DGS BEG_FUN, ??bf_tsk_sys, U, U, 00H, 065H, 01H, 00H + 94 94 $DGS AUX_BEG, 023H, 00H, 050H + 95 95 $DGS STA_SYM, _timeout, ?L0003, U, 0CH, 03H, 00H, 00H + 96 96 $DGS BEG_BLK, ??bb00_tsk_sys, U, U, 00H, 064H, 01H, 00H + 97 97 $DGS AUX_BEG, 05H, 00H, 052H + 98 98 $DGS BEG_BLK, ??bb01_tsk_sys, U, U, 00H, 064H, 01H, 00H + 99 99 $DGS AUX_BEG, 0BH, 00H, 054H + 100 100 $DGS BEG_BLK, ??bb02_tsk_sys, U, U, 00H, 064H, 01H, 00H + 101 101 $DGS AUX_BEG, 010H, 00H, 058H + 102 102 $DGS END_BLK, ??eb02_tsk_sys, U, U, 00H, 064H, 01H, 00H + 103 103 $DGS AUX_END, 012H + 104 104 $DGS BEG_BLK, ??bb03_tsk_sys, U, U, 00H, 064H, 01H, 00H + 105 105 $DGS AUX_BEG, 014H, 00H, 05CH + 106 106 $DGS END_BLK, ??eb03_tsk_sys, U, U, 00H, 064H, 01H, 00H + 107 107 $DGS AUX_END, 016H + 108 108 $DGS BEG_BLK, ??bb04_tsk_sys, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_BEG, 018H, 00H, 060H + 110 110 $DGS END_BLK, ??eb04_tsk_sys, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_END, 01CH + 112 112 $DGS BEG_BLK, ??bb05_tsk_sys, U, U, 00H, 064H, 01H, 00H + 113 113 $DGS AUX_BEG, 01FH, 00H, 066H + 114 114 $DGS END_BLK, ??eb05_tsk_sys, U, U, 00H, 064H, 01H, 00H + 115 115 $DGS AUX_END, 022H + 116 116 $DGS END_BLK, ??eb01_tsk_sys, U, U, 00H, 064H, 01H, 00H + 117 117 $DGS AUX_END, 029H + 118 118 $DGS BEG_BLK, ??bb06_tsk_sys, U, U, 00H, 064H, 01H, 00H + 119 119 $DGS AUX_BEG, 034H, 00H, 06AH + 120 120 $DGS END_BLK, ??eb06_tsk_sys, U, U, 00H, 064H, 01H, 00H + 121 121 $DGS AUX_END, 039H + 122 122 $DGS BEG_BLK, ??bb07_tsk_sys, U, U, 00H, 064H, 01H, 00H + 123 123 $DGS AUX_BEG, 048H, 00H, 06EH + 124 124 $DGS END_BLK, ??eb07_tsk_sys, U, U, 00H, 064H, 01H, 00H + 125 125 $DGS AUX_END, 04BH + 126 126 $DGS BEG_BLK, ??bb08_tsk_sys, U, U, 00H, 064H, 01H, 00H + 127 127 $DGS AUX_BEG, 04DH, 00H, 072H + 128 128 $DGS END_BLK, ??eb08_tsk_sys, U, U, 00H, 064H, 01H, 00H + 129 129 $DGS AUX_END, 051H + 130 130 $DGS BEG_BLK, ??bb09_tsk_sys, U, U, 00H, 064H, 01H, 00H + 131 131 $DGS AUX_BEG, 065H, 00H, 076H + 132 132 $DGS END_BLK, ??eb09_tsk_sys, U, U, 00H, 064H, 01H, 00H + 133 133 $DGS AUX_END, 067H + 134 134 $DGS BEG_BLK, ??bb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H + 135 135 $DGS AUX_BEG, 069H, 00H, 07AH + 136 136 $DGS END_BLK, ??eb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H + 137 137 $DGS AUX_END, 069H + 138 138 $DGS BEG_BLK, ??bb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H + 139 139 $DGS AUX_BEG, 084H, 00H, 07EH + 140 140 $DGS END_BLK, ??eb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H + 141 141 $DGS AUX_END, 087H + 142 142 $DGS BEG_BLK, ??bb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H + 143 143 $DGS AUX_BEG, 092H, 00H, 082H + 144 144 $DGS END_BLK, ??eb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H + 145 145 $DGS AUX_END, 0A1H + 146 146 $DGS BEG_BLK, ??bb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_BEG, 0A9H, 00H, 086H + 148 148 $DGS END_BLK, ??eb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_END, 0ABH + 150 150 $DGS BEG_BLK, ??bb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H + 151 151 $DGS AUX_BEG, 0B1H, 00H, 08AH + 152 152 $DGS END_BLK, ??eb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H + 153 153 $DGS AUX_END, 0B1H + 154 154 $DGS BEG_BLK, ??bb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H + 155 155 $DGS AUX_BEG, 0C4H, 00H, 08EH + 156 156 $DGS END_BLK, ??eb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H + 157 157 $DGS AUX_END, 0C7H + 158 158 $DGS BEG_BLK, ??bb10_tsk_sys, U, U, 00H, 064H, 01H, 00H + 159 159 $DGS AUX_BEG, 0DEH, 00H, 090H + 160 160 $DGS BEG_BLK, ??bb11_tsk_sys, U, U, 00H, 064H, 01H, 00H + 161 161 $DGS AUX_BEG, 0E5H, 00H, 096H + 162 162 $DGS END_BLK, ??eb11_tsk_sys, U, U, 00H, 064H, 01H, 00H + 163 163 $DGS AUX_END, 0EAH + 164 164 $DGS END_BLK, ??eb10_tsk_sys, U, U, 00H, 064H, 01H, 00H + 165 165 $DGS AUX_END, 0ECH + 166 166 $DGS BEG_BLK, ??bb12_tsk_sys, U, U, 00H, 064H, 01H, 00H + 167 167 $DGS AUX_BEG, 0EEH, 00H, 098H + 168 168 $DGS BEG_BLK, ??bb13_tsk_sys, U, U, 00H, 064H, 01H, 00H + 169 169 $DGS AUX_BEG, 0F2H, 00H, 09EH + 170 170 $DGS END_BLK, ??eb13_tsk_sys, U, U, 00H, 064H, 01H, 00H + 171 171 $DGS AUX_END, 0F2H + 172 172 $DGS END_BLK, ??eb12_tsk_sys, U, U, 00H, 064H, 01H, 00H + 173 173 $DGS AUX_END, 0110H + 174 174 $DGS BEG_BLK, ??bb14_tsk_sys, U, U, 00H, 064H, 01H, 00H + 175 175 $DGS AUX_BEG, 0114H, 00H, 00H + 176 176 $DGS END_BLK, ??eb14_tsk_sys, U, U, 00H, 064H, 01H, 00H + 177 177 $DGS AUX_END, 0117H + 178 178 $DGS END_BLK, ??eb00_tsk_sys, U, U, 00H, 064H, 01H, 00H + 179 179 $DGS AUX_END, 0119H + 180 180 $DGS END_FUN, ??ef_tsk_sys, U, U, 00H, 065H, 01H, 00H + 181 181 $DGS AUX_END, 011AH + 182 182 $DGS STA_SYM, _chk_emergencyExit, U, U, 01H, 03H, 01H, 02H + 183 183 $DGS AUX_FUN, 00H, U, U, 0C1H, 00H, 00H + 184 184 $DGS BEG_FUN, ??bf_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H + 185 185 $DGS AUX_BEG, 0143H, 00H, 0ABH + 186 186 $DGS STA_SYM, _state, ?L0048, U, 04H, 03H, 00H, 00H + 187 187 $DGS BEG_BLK, ??bb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 188 188 $DGS AUX_BEG, 06H, 00H, 0ADH + 189 189 $DGS BEG_BLK, ??bb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 190 190 $DGS AUX_BEG, 08H, 00H, 0B1H + 191 191 $DGS END_BLK, ??eb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 192 192 $DGS AUX_END, 0CH + 193 193 $DGS BEG_BLK, ??bb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 194 194 $DGS AUX_BEG, 0EH, 00H, 0B3H + 195 195 $DGS BEG_BLK, ??bb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 196 196 $DGS AUX_BEG, 010H, 00H, 0BBH + 197 197 $DGS END_BLK, ??eb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 198 198 $DGS AUX_END, 017H + 199 199 $DGS END_BLK, ??eb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 200 200 $DGS AUX_END, 018H + 201 201 $DGS END_BLK, ??eb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 202 202 $DGS AUX_END, 019H + 203 203 $DGS BEG_BLK, ??bb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 204 204 $DGS AUX_BEG, 01BH, 00H, 00H + 205 205 $DGS END_BLK, ??eb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H + 206 206 $DGS AUX_END, 01DH + 207 207 $DGS END_FUN, ??ef_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H + 208 208 $DGS AUX_END, 01FH + 209 209 $DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 026H, 01H, 02H + 210 210 $DGS AUX_FUN, 041H, U, U, 0C7H, 00H, 00H + 211 211 $DGS BEG_FUN, ??bf_tski_firm_update, U, U, 00H, 065H, 01H, 00H + 212 212 $DGS AUX_BEG, 0181H, 00H, 0C7H + 213 213 $DGS END_FUN, ??ef_tski_firm_update, U, U, 00H, 065H, 01H, 00H + 214 214 $DGS AUX_END, 04H + 215 215 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H + 216 216 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 217 217 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H + 218 218 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H + 219 219 $DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 02H, 00H, 00H + 220 220 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H + 221 221 $DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H + 222 222 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 223 223 $DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H + 224 224 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 225 225 $DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 02H, 01H, 02H + 226 226 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 227 227 $DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 02H, 01H, 02H + 228 228 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 229 229 $DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 02H, 01H, 02H + 230 230 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 231 231 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 232 232 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 233 233 $DGS GLV_SYM, _LED_init, U, U, 01H, 02H, 01H, 02H + 234 234 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 235 235 $DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 02H, 01H, 02H + 236 236 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 237 237 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 238 238 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 239 239 $DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 02H, 01H, 02H + 240 240 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 241 241 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H + 242 242 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 243 243 $DGS GLV_SYM, _LED_stop, U, U, 01H, 02H, 01H, 02H + 244 244 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 245 245 $DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 02H, 01H, 02H + 246 246 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 247 247 $DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 02H, 01H, 02H + 248 248 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 249 249 $DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 02H, 01H, 02H + 250 250 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 251 251 $DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 02H, 00H, 00H + 252 252 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H + 253 253 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 254 254 $DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H + 255 255 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H + 256 256 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 257 257 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 258 258 $DGS GLV_SYM, _firm_update, U, U, 0CH, 02H, 01H, 02H + 259 259 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 260 260 + 261 261 EXTRN _iic_mcu_write_a_byte + 262 262 EXTRN _system_status + 263 263 EXTRN _SW_pow_count + 264 264 EXTRN _iic_mcu_start + 265 265 EXTRN _PM_init + 266 266 EXTRN _PM_sys_pow_on + 267 267 EXTRN _iic_mcu_stop + 268 268 EXTRN _PM_LCD_vcom_set + 269 269 EXTRN _vreg_ctr + 270 270 EXTRN _LED_init + 271 271 EXTRN _IIC_ctr_Init + 272 272 EXTRN _set_irq + 273 273 EXTRN _IIC_twl_Init + 274 274 EXTRN _wait_ms + 275 275 EXTRN _LED_stop + 276 276 EXTRN _IIC_ctr_Stop + 277 277 EXTRN _IIC_twl_Stop + 278 278 EXTRN _PM_sys_pow_off + 279 279 EXTRN _SW_wifi_count + 280 280 EXTRN _iic_mcu_read_a_byte + 281 281 EXTRN _do_command0 + 282 282 EXTRN _renge_task_immed_add + 283 283 EXTRN _firm_update + 284 284 EXTBIT _renge_task_interval_run_force + 285 285 PUBLIC _tsk_sys + 286 286 PUBLIC _tski_firm_update + 287 287 + 288 288 ----- @@BITS BSEG + 289 289 + 290 290 ----- @@CNST CSEG MIRRORP + 291 291 00000 01 _lpf_coeff: DB 01H ; 1 + 292 292 00001 02 DB 02H ; 2 + 293 293 00002 02 DB 02H ; 2 + 294 294 00003 03 DB 03H ; 3 + 295 295 00004 03 DB 03H ; 3 + 296 296 00005 02 DB 02H ; 2 + 297 297 00006 00 DB 00H ; 0 + 298 298 00007 FE DB 0FEH ; 254 + 299 299 00008 FB DB 0FBH ; 251 + 300 300 00009 F7 DB 0F7H ; 247 + 301 301 0000A F3 DB 0F3H ; 243 + 302 302 0000B F0 DB 0F0H ; 240 + 303 303 0000C F0 DB 0F0H ; 240 + 304 304 0000D F3 DB 0F3H ; 243 + 305 305 0000E FA DB 0FAH ; 250 + 306 306 0000F 04 DB 04H ; 4 + 307 307 00010 12 DB 012H ; 18 + 308 308 00011 25 DB 025H ; 37 + 309 309 00012 38 DB 038H ; 56 + 310 310 00013 4D DB 04DH ; 77 + 311 311 00014 5F DB 05FH ; 95 + 312 312 00015 6E DB 06EH ; 110 + 313 313 00016 77 DB 077H ; 119 + 314 314 00017 7A DB 07AH ; 122 + 315 315 00018 77 DB 077H ; 119 + 316 316 00019 6E DB 06EH ; 110 + 317 317 0001A 5F DB 05FH ; 95 + 318 318 0001B 4D DB 04DH ; 77 + 319 319 0001C 38 DB 038H ; 56 + 320 320 0001D 25 DB 025H ; 37 + 321 321 0001E 12 DB 012H ; 18 + 322 322 0001F 04 DB 04H ; 4 + 323 323 00020 FA DB 0FAH ; 250 + 324 324 00021 F3 DB 0F3H ; 243 + 325 325 00022 F0 DB 0F0H ; 240 + 326 326 00023 F0 DB 0F0H ; 240 + 327 327 00024 F3 DB 0F3H ; 243 + 328 328 00025 F7 DB 0F7H ; 247 + 329 329 00026 FB DB 0FBH ; 251 + 330 330 00027 FE DB 0FEH ; 254 + 331 331 00028 00 DB 00H ; 0 + 332 332 00029 02 DB 02H ; 2 + 333 333 0002A 03 DB 03H ; 3 + 334 334 0002B 03 DB 03H ; 3 + 335 335 0002C 02 DB 02H ; 2 + 336 336 0002D 02 DB 02H ; 2 + 337 337 0002E 01 DB 01H ; 1 + 338 338 0002F 00 DB (1) + 339 339 + 340 340 ----- @@R_INIT CSEG UNIT64KP + 341 341 00000 00 DB 00H ; 0 + 342 342 00001 00 DB (1) + 343 343 + 344 344 ----- @@INIT DSEG BASEP + 345 345 00000 ?L0003: DS (1) + 346 346 00001 DS (1) + 347 347 + 348 348 ----- @@DATA DSEG BASEP + 349 349 00000 ?L0048: DS (2) + 350 350 + 351 351 ----- @@R_INIS CSEG UNIT64KP + 352 352 + 353 353 ----- @@INIS DSEG SADDRP + 354 354 + 355 355 ----- @@DATS DSEG SADDRP + 356 356 + 357 357 ----- @@CNSTL CSEG PAGE64KP + 358 358 + 359 359 ----- @@RLINIT CSEG UNIT64KP + 360 360 + 361 361 ----- @@INITL DSEG UNIT64KP + 362 362 + 363 363 ----- @@DATAL DSEG UNIT64KP + 364 364 + 365 365 ----- @@CALT CSEG CALLT0 + 366 366 + 367 367 ; Sub-Routines created by CC78K0R + 368 368 + 369 369 ----- ROM_CODE CSEG BASE + 370 370 00000 bs_F0057: + 371 371 00000 C1 push ax ;[INF] 1, 1 + 372 372 00001 5005 mov x,#05H ; 5 ;[INF] 2, 1 + 373 373 00003 C1 push ax ;[INF] 1, 1 + 374 374 00004 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 375 375 00006 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 376 376 00009 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 377 377 0000B D7 ret ;[INF] 1, 6 + 378 378 0000C es_F0057: + 379 379 + 380 380 ; *** Sub-Routine Information *** + 381 381 ; + 382 382 ; $SUB bs_F0057 + 383 383 ; CODE SIZE= 12 bytes + 384 384 + 385 385 ; End of Sub-Routines + 386 386 + 387 387 ; line 1 : #pragma SFR + 388 388 ; line 2 : #pragma NOP + 389 389 ; line 3 : #pragma HALT + 390 390 ; line 4 : #pragma STOP + 391 391 ; line 5 : + 392 392 ; line 6 : #include "incs.h" + 393 393 ; line 7 : + 394 394 ; line 8 : #include "i2c_twl.h" + 395 395 ; line 9 : #include "i2c_ctr.h" + 396 396 ; line 10 : #include "led.h" + 397 397 ; line 11 : #include "accero.h" + 398 398 ; line 12 : #include "pm.h" + 399 399 ; line 13 : #include "rtc.h" + 400 400 ; line 14 : #include "sw.h" + 401 401 ; line 15 : #include "adc.h" + 402 402 ; line 16 : + 403 403 ; line 17 : + 404 404 ; line 18 : + 405 405 ; line 19 : //========================================================= + 406 406 ; line 20 : static void chk_emergencyExit(); + 407 407 ; line 21 : + 408 408 ; line 22 : + 409 409 ; line 23 : + 410 410 ; line 24 : //========================================================= + 411 411 ; line 25 : + 412 412 ; line 26 : + 413 413 ; line 27 : + 414 414 ; line 28 : /* ======================================================== + 415 415 ; line 29 : マイコン内部で必要なもの + 416 416 ; line 30 : ・省電力に入れる + 417 417 ; line 31 : 　system_status.pwr_state == OFF_TRIG で、このタスクが呼ばれる + 418 418 ; と、 + 419 419 ; line 32 : 省電力モードに入ります + 420 420 ; line 33 : ======================================================== */ + 421 421 ; line 34 : void tsk_sys( ) + 422 422 ; line 35 : { + 423 423 + 424 424 ----- ROM_CODE CSEG BASE + 425 425 0000C _tsk_sys: + 426 426 $DGL 1,75 + 427 427 0000C ??bf_tsk_sys: + 428 428 ; line 36 : static u8 timeout = 0; + 429 429 ; line 37 : + 430 430 ; line 38 : switch ( system_status.pwr_state ) + 431 431 $DGL 0,4 + 432 432 0000C R8F0000 mov a,!_system_status ;[INF] 3, 1 + 433 433 0000F 318F sarw ax,8 ;[INF] 2, 1 + 434 434 00011 E7 onew bc ;[INF] 1, 1 + 435 435 00012 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 436 436 00015 61F8 sknz ;[INF] 2, 1 + 437 437 00017 RED1701 br !?L0010 ;[INF] 3, 3 + 438 438 0001A 23 subw ax,bc ;[INF] 1, 1 + 439 439 0001B DD1E bz $?L0005 ;[INF] 2, 4 + 440 440 0001D 23 subw ax,bc ;[INF] 1, 1 + 441 441 0001E DD7B bz $?L0006 ;[INF] 2, 4 + 442 442 00020 23 subw ax,bc ;[INF] 1, 1 + 443 443 00021 61F8 sknz ;[INF] 2, 1 + 444 444 00023 REDDA00 br !?L0007 ;[INF] 3, 3 + 445 445 00026 23 subw ax,bc ;[INF] 1, 1 + 446 446 00027 61F8 sknz ;[INF] 2, 1 + 447 447 00029 REDE900 br !?L0008 ;[INF] 3, 3 + 448 448 0002C 23 subw ax,bc ;[INF] 1, 1 + 449 449 0002D 61F8 sknz ;[INF] 2, 1 + 450 450 0002F REDF400 br !?L0009 ;[INF] 3, 3 + 451 451 00032 23 subw ax,bc ;[INF] 1, 1 + 452 452 00033 61F8 sknz ;[INF] 2, 1 + 453 453 00035 RED6C01 br !?L0011 ;[INF] 3, 3 + 454 454 00038 REDB901 br !?L0038 ;[INF] 3, 3 + 455 455 ; line 39 : { + 456 456 0003B ??bb00_tsk_sys: + 457 457 ; line 40 : case OFF: //------------------------------- + 458 458 ; ------------------------ + 459 459 0003B ?L0005: + 460 460 ; line 41 : // スイッチ操作などで割り込みが発生し、スリープが解除され + 461 461 ; るとここに来ます。 + 462 462 ; line 42 : + 463 463 ; line 43 : #ifndef _PARRADIUM_ + 464 464 ; line 44 : switch ( system_status.poweron_reason ) + 465 465 $DGL 0,10 + 466 466 0003B R8F0100 mov a,!_system_status+1 ;[INF] 3, 1 + 467 467 0003E 318F sarw ax,8 ;[INF] 2, 1 + 468 468 00040 240200 subw ax,#02H ; 2 ;[INF] 3, 1 + 469 469 00043 DD26 bz $?L0015 ;[INF] 2, 4 + 470 470 ; line 45 : { + 471 471 00045 ??bb01_tsk_sys: + 472 472 ; line 46 : default: + 473 473 ; line 47 : // スイッチで電源on + 474 474 ; line 48 : + 475 475 ; line 49 : if( SW_pow_count != 0 ) + 476 476 $DGL 0,15 + 477 477 00045 RD50000 cmp0 !_SW_pow_count ;[INF] 3, 1 + 478 478 00048 DD05 bz $?L0018 ;[INF] 2, 4 + 479 479 ; line 50 : { + 480 480 0004A ??bb02_tsk_sys: + 481 481 ; line 51 : timeout = 0; + 482 482 $DGL 0,17 + 483 483 0004A RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1 + 484 484 0004D ??eb02_tsk_sys: + 485 485 ; line 52 : } + 486 486 $DGL 0,18 + 487 487 0004D EF03 br $?L0019 ;[INF] 2, 3 + 488 488 0004F ?L0018: + 489 489 ; line 53 : else + 490 490 ; line 54 : { + 491 491 0004F ??bb03_tsk_sys: + 492 492 ; line 55 : timeout += 1; + 493 493 $DGL 0,21 + 494 494 0004F RA00000 inc !?L0003 ; timeout ;[INF] 3, 2 + 495 495 00052 ??eb03_tsk_sys: + 496 496 ; line 56 : } + 497 497 00052 ?L0019: + 498 498 ; line 57 : if( timeout > 127 ) + 499 499 $DGL 0,23 + 500 500 00052 R8F0000 mov a,!?L0003 ; timeout ;[INF] 3, 1 + 501 501 00055 01 addw ax,ax ;[INF] 1, 1 + 502 502 00056 DE07 bnc $?L0020 ;[INF] 2, 4 + 503 503 ; line 58 : { + 504 504 00058 ??bb04_tsk_sys: + 505 505 ; line 59 : system_status.pwr_state = OFF_TRIG; // スイッ + 506 506 ; チはノイズだった。寝る。 + 507 507 $DGL 0,25 + 508 508 00058 RF50000 clrb !_system_status ;[INF] 3, 1 + 509 509 ; line 60 : renge_task_interval_run_force = 1; + 510 510 $DGL 0,26 + 511 511 0005B R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 512 512 ; line 61 : return; + 513 513 $DGL 0,27 + 514 514 0005E D7 ret ;[INF] 1, 6 + 515 515 0005F ??eb04_tsk_sys: + 516 516 ; line 62 : } + 517 517 0005F ?L0020: + 518 518 ; line 63 : + 519 519 ; line 64 : if( SW_pow_count < 3 ) + 520 520 $DGL 0,30 + 521 521 0005F R40000003 cmp !_SW_pow_count,#03H ; 3 ;[INF] 4, 1 + 522 522 00063 61D8 sknc ;[INF] 2, 1 + 523 523 00065 REDBC01 br !?L0004 ;[INF] 3, 3 + 524 524 ; line 65 : { + 525 525 00068 ??bb05_tsk_sys: + 526 526 ; line 66 : // もう少しスイッチの様子を見る + 527 527 ; line 67 : return; + 528 528 00068 ??eb05_tsk_sys: + 529 529 ; line 68 : } + 530 530 ; line 69 : // 電源投入 + 531 531 ; line 70 : system_status.poweron_reason = PWSW; + 532 532 $DGL 0,36 + 533 533 00068 RE50100 oneb !_system_status+1 ;[INF] 3, 1 + 534 534 ; line 71 : break; + 535 535 ; line 72 : + 536 536 ; line 73 : case ( RTC_ALARM ): + 537 537 ; line 74 : break; + 538 538 0006B ??eb01_tsk_sys: + 539 539 ; line 75 : } + 540 540 0006B ?L0015: + 541 541 ; line 76 : + 542 542 ; line 77 : timeout = 0; + 543 543 $DGL 0,43 + 544 544 0006B RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1 + 545 545 ; line 78 : + 546 546 ; line 79 : // 電源投入 // + 547 547 ; line 80 : iic_mcu_start( ); + 548 548 $DGL 0,46 + 549 549 0006E RFD0000 call !_iic_mcu_start ;[INF] 3, 3 + 550 550 ; line 81 : + 551 551 ; line 82 : // ↓で電池残量ICの起動待ちウェイトなどがあります。 + 552 552 ; line 83 : PM_init( ); // 電池残量ICの設定 + 553 553 $DGL 0,49 + 554 554 00071 RFD0000 call !_PM_init ;[INF] 3, 3 + 555 555 ; line 84 : + 556 556 ; line 85 : if( PM_sys_pow_on( ) != ERR_SUCCESS ) + 557 557 $DGL 0,51 + 558 558 00074 RFD0000 call !_PM_sys_pow_on ;[INF] 3, 3 + 559 559 00077 D2 cmp0 c ;[INF] 1, 1 + 560 560 00078 DD0A bz $?L0024 ;[INF] 2, 4 + 561 561 ; line 86 : { // 電源起動不可エラー + 562 562 0007A ??bb06_tsk_sys: + 563 563 ; line 87 : renge_task_interval_run_force = 1; + 564 564 $DGL 0,53 + 565 565 0007A R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 566 566 ; line 88 : iic_mcu_stop( ); + 567 567 $DGL 0,54 + 568 568 0007D RFD0000 call !_iic_mcu_stop ;[INF] 3, 3 + 569 569 ; line 89 : system_status.pwr_state = OFF_TRIG; + 570 570 $DGL 0,55 + 571 571 00080 RF50000 clrb !_system_status ;[INF] 3, 1 + 572 572 ; line 90 : return; + 573 573 $DGL 0,56 + 574 574 00083 D7 ret ;[INF] 1, 6 + 575 575 00084 ??eb06_tsk_sys: + 576 576 ; line 91 : } + 577 577 00084 ?L0024: + 578 578 ; line 92 : PM_CHG_TIMEOUT_ENABLE(); + 579 579 ; line 93 : // IRQ0_active; + 580 580 ; line 94 : + 581 581 ; line 95 : #else + 582 582 ; line 96 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR; + 583 583 ; line 97 : system_status.poweron_reason = PWSW; + 584 584 ; line 98 : #endif // _PARADDIUM_ + 585 585 ; line 99 : + 586 586 ; line 100 : PM_LCD_vcom_set( ); // LCDの対向電圧値など書き込み + 587 587 $DGL 0,66 + 588 588 00084 RFD0000 call !_PM_LCD_vcom_set ;[INF] 3, 3 + 589 589 ; line 101 : #ifdef _PMIC_TWL_ + 590 590 ; line 102 : PM_TEG_LCD_dis( 0 ); + 591 591 ; line 103 : #endif + 592 592 ; line 104 : + 593 593 ; line 105 : if( system_status.poweron_reason == PWSW ) + 594 594 $DGL 0,71 + 595 595 00087 R40010001 cmp !_system_status+1,#01H ; 1 ;[INF] 4, 1 + 596 596 0008B DF05 bnz $?L0026 ;[INF] 2, 4 + 597 597 ; line 106 : { + 598 598 0008D ??bb07_tsk_sys: + 599 599 ; line 107 : // 電源ボタンでのonの時は、LEDを点灯させる + 600 600 ; line 108 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO; + 601 601 $DGL 0,74 + 602 602 0008D RF52900 clrb !_vreg_ctr+41 ;[INF] 3, 1 + 603 603 00090 ??eb07_tsk_sys: + 604 604 ; line 109 : } + 605 605 $DGL 0,75 + 606 606 00090 EF04 br $?L0027 ;[INF] 2, 3 + 607 607 00092 ?L0026: + 608 608 ; line 110 : else + 609 609 ; line 111 : { + 610 610 00092 ??bb08_tsk_sys: + 611 611 ; line 112 : // とりあえず、LED消灯状態で起動させる + 612 612 ; line 113 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; + 613 613 $DGL 0,79 + 614 614 00092 RCF290003 mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1 + 615 615 00096 ??eb08_tsk_sys: + 616 616 ; line 114 : // todo? + 617 617 ; line 115 : } + 618 618 00096 ?L0027: + 619 619 ; line 116 : system_status.pwr_state = ON_TRIG; + 620 620 $DGL 0,82 + 621 621 00096 RCF000002 mov !_system_status,#02H ; 2 ;[INF] 4, 1 + 622 622 ; line 117 : // ここまで来ると、電源投入確定 + 623 623 ; line 118 : break; + 624 624 $DGL 0,84 + 625 625 0009A D7 ret ;[INF] 1, 6 + 626 626 ; line 119 : + 627 627 ; line 120 : case ON_TRIG: //------------------------------- + 628 628 ; ------------------------ + 629 629 0009B ?L0006: + 630 630 ; line 121 : + 631 631 ; line 122 : LED_init( ); + 632 632 $DGL 0,88 + 633 633 0009B RFD0000 call !_LED_init ;[INF] 3, 3 + 634 634 ; line 123 : + 635 635 ; line 124 : PU7 = 0b00011101; // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_ + 636 636 ; EXTDC_n + 637 637 $DGL 0,90 + 638 638 0009E CF37001D mov !PU7,#01DH ; 29 ;[INF] 4, 1 + 639 639 ; line 125 : + 640 640 ; line 126 : IIC_ctr_Init( ); + 641 641 $DGL 0,92 + 642 642 000A2 RFD0000 call !_IIC_ctr_Init ;[INF] 3, 3 + 643 643 ; line 127 : if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT + 644 644 ; _RESET ) + 645 645 ; line 128 : /* + 646 646 ; line 129 : if( vreg_ctr[ VREG_C_IRQ0 ] + 647 647 ; line 130 : | vreg_ctr[ VREG_C_IRQ0 ] + 648 648 ; line 131 : | vreg_ctr[ VREG_C_IRQ0 ] + 649 649 ; line 132 : | vreg_ctr[ VREG_C_IRQ0 ] + 650 650 ; line 133 : */ + 651 651 ; line 134 : != 0 ) + 652 652 $DGL 0,100 + 653 653 000A5 R8F0200 mov a,!_vreg_ctr+2 ;[INF] 3, 1 + 654 654 000A8 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 655 655 000AA D1 cmp0 a ;[INF] 1, 1 + 656 656 000AB DD0A bz $?L0028 ;[INF] 2, 4 + 657 657 ; line 135 : { + 658 658 000AD ??bb09_tsk_sys: + 659 659 ; line 136 : set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET ); + 660 660 $DGL 0,102 + 661 661 000AD 308000 movw ax,#080H ; 128 ;[INF] 3, 1 + 662 662 000B0 C1 push ax ;[INF] 1, 1 + 663 663 000B1 5010 mov x,#010H ; 16 ;[INF] 2, 1 + 664 664 000B3 RFD0000 call !_set_irq ;[INF] 3, 3 + 665 665 000B6 C0 pop ax ;[INF] 1, 1 + 666 666 000B7 ??eb09_tsk_sys: + 667 667 ; line 137 : } + 668 668 000B7 ?L0028: + 669 669 ; line 138 : IIC_twl_Init( ); + 670 670 $DGL 0,104 + 671 671 000B7 RFD0000 call !_IIC_twl_Init ;[INF] 3, 3 + 672 672 ; line 139 : RTC_32k_on( ); + 673 673 $DGL 0,105 + 674 674 000BA ??bb0A_tsk_sys: + 675 675 000BA 714A9D set1 RTCC0.4 ;[INF] 3, 2 + 676 676 000BD ??eb0A_tsk_sys: + 677 677 ; line 140 : + 678 678 ; line 141 : KRM = 0b00000000; + 679 679 $DGL 0,107 + 680 680 000BD F537FF clrb !KRM ;[INF] 3, 1 + 681 681 ; line 142 : + 682 682 ; line 143 : system_status.poweron_reason = NONE; + 683 683 $DGL 0,109 + 684 684 000C0 RF50100 clrb !_system_status+1 ;[INF] 3, 1 + 685 685 ; line 144 : renge_task_interval_run_force = 1; + 686 686 $DGL 0,110 + 687 687 000C3 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 688 688 ; line 145 : + 689 689 ; line 146 : MK0 = INT_MSK0_RSV; + 690 690 $DGL 0,112 + 691 691 000C6 CBE43FEF movw MK0,#0EF3FH ; -4289 ;[INF] 4, 1 + 692 692 ; line 147 : MK1 = INT_MSK1_RSV; + 693 693 $DGL 0,113 + 694 694 000CA CBE6F6F0 movw MK1,#0F0F6H ; -3850 ;[INF] 4, 1 + 695 695 ; line 148 : #ifdef _MCU_BSR_ + 696 696 ; line 149 : // MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT + 697 697 ; _MSK2_CODEC_PMIRQ ); + 698 698 ; line 150 : // PMK21 = 0; // wifi 使わない + 699 699 ; line 151 : PMK6 = 0; // pm_irq + 700 700 $DGL 0,117 + 701 701 000CE 713BD4 clr1 MK2L.3 ;[INF] 3, 2 + 702 702 ; line 152 : #else + 703 703 ; line 153 : MK2L = ~INT_MSK2_WIFI_TX_KE3; + 704 704 ; line 154 : #endif + 705 705 ; line 155 : + 706 706 ; line 156 : system_status.reboot = 0; + 707 707 $DGL 0,122 + 708 708 000D1 R71380200 clr1 !_system_status+2.3 ;[INF] 4, 2 + 709 709 ; line 157 : system_status.pwr_state = ON; + 710 710 $DGL 0,123 + 711 711 000D5 RCF000003 mov !_system_status,#03H ; 3 ;[INF] 4, 1 + 712 712 ; line 158 : break; + 713 713 $DGL 0,124 + 714 714 000D9 D7 ret ;[INF] 1, 6 + 715 715 ; line 159 : + 716 716 ; line 160 : case ON: //------------------------------- + 717 717 ; -------------- + 718 718 000DA ?L0007: + 719 719 ; line 161 : // PMICによる強制電源断チェック + 720 720 ; line 162 : // デバッガがreset1をアサートすることもある。そのときは全 + 721 721 ; 部リセット + 722 722 ; line 163 : chk_emergencyExit(); + 723 723 $DGL 0,129 + 724 724 000DA RFDBD01 call !_chk_emergencyExit ;[INF] 3, 3 + 725 725 ; line 164 : + 726 726 ; line 165 : // SLP監視 + 727 727 ; line 166 : if( SLP_REQ ){ + 728 728 $DGL 0,132 + 729 729 000DD 31040C07 bf P12.0,$?L0030 ;[INF] 4, 5 + 730 730 000E1 ??bb0B_tsk_sys: + 731 731 ; line 167 : system_status.pwr_state = SLEEP_TRIG; + 732 732 $DGL 0,133 + 733 733 000E1 RCF000004 mov !_system_status,#04H ; 4 ;[INF] 4, 1 + 734 734 ; line 168 : renge_task_interval_run_force = 1; + 735 735 $DGL 0,134 + 736 736 000E5 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 737 737 000E8 ??eb0B_tsk_sys: + 738 738 ; line 169 : } + 739 739 000E8 ?L0030: + 740 740 ; line 170 : break; + 741 741 $DGL 0,136 + 742 742 000E8 D7 ret ;[INF] 1, 6 + 743 743 ; line 171 : + 744 744 ; line 172 : case SLEEP_TRIG: //------------------------------- + 745 745 ; ------ + 746 746 000E9 ?L0008: + 747 747 ; line 173 : PM_VDD_ecoMode(); + 748 748 $DGL 0,139 + 749 749 000E9 302700 movw ax,#027H ; 39 ;[INF] 3, 1 + 750 750 000EC RFD0000 call !bs_F0057 ;[INF] 3, 3 + 751 751 ; line 174 : system_status.pwr_state = SLEEP; + 752 752 $DGL 0,140 + 753 753 000EF RCF000005 mov !_system_status,#05H ; 5 ;[INF] 4, 1 + 754 754 ; line 175 : break; + 755 755 $DGL 0,141 + 756 756 000F3 D7 ret ;[INF] 1, 6 + 757 757 ; line 176 : + 758 758 ; line 177 : case SLEEP: //------------------------------- + 759 759 ; ----------- + 760 760 000F4 ?L0009: + 761 761 ; line 178 : chk_emergencyExit(); + 762 762 $DGL 0,144 + 763 763 000F4 RFDBD01 call !_chk_emergencyExit ;[INF] 3, 3 + 764 764 ; line 179 : // スリープから復帰 + 765 765 ; line 180 : if( !SLP_REQ ){ + 766 766 $DGL 0,146 + 767 767 000F7 31020C1B bt P12.0,$?L0032 ;[INF] 4, 5 + 768 768 000FB ??bb0C_tsk_sys: + 769 769 ; line 181 : PM_VDD_normMode(); + 770 770 $DGL 0,147 + 771 771 000FB F6 clrw ax ;[INF] 1, 1 + 772 772 000FC RFD0000 call !bs_F0057 ;[INF] 3, 3 + 773 773 ; line 182 : wait_ms( 5 ); // tdly_sw + 774 774 $DGL 0,148 + 775 775 000FF 300500 movw ax,#05H ; 5 ;[INF] 3, 1 + 776 776 00102 RFD0000 call !_wait_ms ;[INF] 3, 3 + 777 777 ; line 183 : + 778 778 ; line 184 : #ifdef _MODEL_CTR_ + 779 779 ; line 185 : SLP_ACK = 1; + 780 780 $DGL 0,151 + 781 781 00105 717207 set1 P7.7 ;[INF] 3, 2 + 782 782 ; line 186 : NOP(); // 適当ウェイト + 783 783 $DGL 0,152 + 784 784 00108 00 nop ;[INF] 1, 1 + 785 785 ; line 187 : NOP(); + 786 786 $DGL 0,153 + 787 787 00109 00 nop ;[INF] 1, 1 + 788 788 ; line 188 : NOP(); + 789 789 $DGL 0,154 + 790 790 0010A 00 nop ;[INF] 1, 1 + 791 791 ; line 189 : NOP(); + 792 792 $DGL 0,155 + 793 793 0010B 00 nop ;[INF] 1, 1 + 794 794 ; line 190 : SLP_ACK = 0; + 795 795 $DGL 0,156 + 796 796 0010C 717307 clr1 P7.7 ;[INF] 3, 2 + 797 797 ; line 191 : #endif + 798 798 ; line 192 : + 799 799 ; line 193 : system_status.pwr_state = ON_TRIG; + 800 800 $DGL 0,159 + 801 801 0010F RCF000002 mov !_system_status,#02H ; 2 ;[INF] 4, 1 + 802 802 ; line 194 : renge_task_interval_run_force = 1; + 803 803 $DGL 0,160 + 804 804 00113 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 805 805 00116 ??eb0C_tsk_sys: + 806 806 ; line 195 : } + 807 807 00116 ?L0032: + 808 808 ; line 196 : + 809 809 ; line 197 : break; + 810 810 $DGL 0,163 + 811 811 00116 D7 ret ;[INF] 1, 6 + 812 812 ; line 198 : + 813 813 ; line 199 : case OFF_TRIG: //------------------------------- + 814 814 ; -------- + 815 815 00117 ?L0010: + 816 816 ; line 200 : // LED消灯を待つ + 817 817 ; line 201 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF; + 818 818 $DGL 0,167 + 819 819 00117 RCF290003 mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1 + 820 820 ; line 202 : if(( LED_duty_pow_H != 0 ) || ( LED_duty_pow_L != 0 )) + 821 821 $DGL 0,168 + 822 822 0011B F6 clrw ax ;[INF] 1, 1 + 823 823 0011C 426CFF cmpw ax,!TDR06 ;[INF] 3, 1 + 824 824 0011F DF05 bnz $?L0036 ;[INF] 2, 4 + 825 825 00121 426EFF cmpw ax,!TDR07 ;[INF] 3, 1 + 826 826 00124 61E8 skz ;[INF] 2, 1 + 827 827 00126 ?L0036: + 828 828 ; line 203 : { + 829 829 00126 ??bb0D_tsk_sys: + 830 830 ; line 204 : return; + 831 831 $DGL 0,170 + 832 832 00126 D7 ret ;[INF] 1, 6 + 833 833 00127 ??eb0D_tsk_sys: + 834 834 ; line 205 : } + 835 835 00127 ?L0034: + 836 836 ; line 206 : + 837 837 ; line 207 : PM_CHG_TIMEOUT_ENABLE(); + 838 838 ; line 208 : LED_stop( ); + 839 839 $DGL 0,174 + 840 840 00127 RFD0000 call !_LED_stop ;[INF] 3, 3 + 841 841 ; line 209 : IIC_ctr_Stop( ); + 842 842 $DGL 0,175 + 843 843 0012A RFD0000 call !_IIC_ctr_Stop ;[INF] 3, 3 + 844 844 ; line 210 : IIC_twl_Stop( ); + 845 845 $DGL 0,176 + 846 846 0012D RFD0000 call !_IIC_twl_Stop ;[INF] 3, 3 + 847 847 ; line 211 : RTC_32k_off(); + 848 848 $DGL 0,177 + 849 849 00130 ??bb0E_tsk_sys: + 850 850 00130 714B9D clr1 RTCC0.4 ;[INF] 3, 2 + 851 851 00133 ??eb0E_tsk_sys: + 852 852 ; line 212 : + 853 853 ; line 213 : vreg_ctr[VREG_C_IRQ0] = 0; + 854 854 $DGL 0,179 + 855 855 00133 RF51000 clrb !_vreg_ctr+16 ;[INF] 3, 1 + 856 856 ; line 214 : vreg_ctr[VREG_C_IRQ1] = 0; + 857 857 $DGL 0,180 + 858 858 00136 RF51100 clrb !_vreg_ctr+17 ;[INF] 3, 1 + 859 859 ; line 215 : vreg_ctr[VREG_C_IRQ2] = 0; + 860 860 $DGL 0,181 + 861 861 00139 RF51200 clrb !_vreg_ctr+18 ;[INF] 3, 1 + 862 862 ; line 216 : vreg_ctr[VREG_C_IRQ3] = 0; + 863 863 $DGL 0,182 + 864 864 0013C RF51300 clrb !_vreg_ctr+19 ;[INF] 3, 1 + 865 865 ; line 217 : + 866 866 ; line 218 : // 電源オン条件の割り込みセット + 867 867 ; line 219 : // PWSW KR3 押すとL + 868 868 ; line 220 : // BG24 KR4 + 869 869 ; line 221 : // ふた開け INTP5 閉じるとL + 870 870 ; line 222 : // ACアダプタ INTP4 アダプタありでL + 871 871 ; line 223 : // RTC + 872 872 ; line 224 : + 873 873 ; line 225 : #ifdef _PMIC_TWL_ + 874 874 ; line 226 : PM_TEG_LCD_dis( 1 ); + 875 875 ; line 227 : #endif + 876 876 ; line 228 : // IRQ0_deactive; + 877 877 ; line 229 : // pullup_off(); ↓ + 878 878 ; line 230 : { + 879 879 0013F ??bb0F_tsk_sys: + 880 880 ; line 231 : PU5 = 0b00000011; // PM_CHG,PM_CHGERR + 881 881 $DGL 0,197 + 882 882 0013F CF350003 mov !PU5,#03H ; 3 ;[INF] 4, 1 + 883 883 ; line 232 : PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC + 884 884 $DGL 0,198 + 885 885 00143 CF370019 mov !PU7,#019H ; 25 ;[INF] 4, 1 + 886 886 00147 ??eb0F_tsk_sys: + 887 887 ; line 233 : } + 888 888 ; line 234 : + 889 889 ; line 235 : PM_sys_pow_off( ); + 890 890 $DGL 0,201 + 891 891 00147 RFD0000 call !_PM_sys_pow_off ;[INF] 3, 3 + 892 892 ; line 236 : + 893 893 ; line 237 : KRM = ( KR_SW_POW ); // Mask ではなく、Modeなのだそう + 894 894 ; だ。紛らわしい + 895 895 $DGL 0,203 + 896 896 0014A CE3708 mov KRM,#08H ; 8 ;[INF] 3, 1 + 897 897 ; line 238 : // intp20系は後ほど + 898 898 ; line 239 : MK0 = ~( INT_MSK0_EXTDC ); + 899 899 $DGL 0,205 + 900 900 0014D CBE4BFFF movw MK0,#0FFBFH ; -65 ;[INF] 4, 1 + 901 901 ; line 240 : MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCALARM | INT_MSK1_RTCI + 902 902 ; NTVAL ); + 903 903 $DGL 0,206 + 904 904 00151 CBE6FFF1 movw MK1,#0F1FFH ; -3585 ;[INF] 4, 1 + 905 905 ; line 241 : MK2L = 0b11111111; + 906 906 $DGL 0,207 + 907 907 00155 CED4FF mov MK2L,#0FFH ; 255 ;[INF] 3, 1 + 908 908 ; line 242 : + 909 909 ; line 243 : IF0 = 0; + 910 910 $DGL 0,209 + 911 911 00158 F6 clrw ax ;[INF] 1, 1 + 912 912 00159 BEE0 movw IF0,ax ;[INF] 2, 1 + 913 913 ; line 244 : IF1 = 0; + 914 914 $DGL 0,210 + 915 915 0015B BEE2 movw IF1,ax ;[INF] 2, 1 + 916 916 ; line 245 : IF2 = 0; + 917 917 $DGL 0,211 + 918 918 0015D BED0 movw IF2,ax ;[INF] 2, 1 + 919 919 ; line 246 : + 920 920 ; line 247 : timeout = 0; + 921 921 $DGL 0,213 + 922 922 0015F RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1 + 923 923 ; line 248 : + 924 924 ; line 249 : system_status.pwr_state = BT_CHARGE; + 925 925 $DGL 0,215 + 926 926 00162 RCF000006 mov !_system_status,#06H ; 6 ;[INF] 4, 1 + 927 927 ; line 250 : SW_pow_count = 0; + 928 928 $DGL 0,216 + 929 929 00166 RF50000 clrb !_SW_pow_count ;[INF] 3, 1 + 930 930 ; line 251 : SW_wifi_count = 0; + 931 931 $DGL 0,217 + 932 932 00169 RF50000 clrb !_SW_wifi_count ;[INF] 3, 1 + 933 933 ; line 252 : // no break // + 934 934 ; line 253 : + 935 935 ; line 254 : case BT_CHARGE: + 936 936 0016C ?L0011: + 937 937 ; line 255 : if( !PM_EXTDC_n ) + 938 938 $DGL 0,221 + 939 939 0016C 3102071F bt P7.0,$?L0037 ;[INF] 4, 5 + 940 940 ; line 256 : { + 941 941 00170 ??bb10_tsk_sys: + 942 942 ; line 257 : // アダプタ有り：充電温度監視 + 943 943 ; line 258 : BT_TEMP_P = 1; + 944 944 $DGL 0,224 + 945 945 00170 717201 set1 P1.7 ;[INF] 3, 2 + 946 946 ; line 259 : + 947 947 ; line 260 : // 電源on？ + 948 948 ; line 261 : if( ( SW_pow_count > 3 ) || ( SW_wifi_count > 3 ) + 949 949 ; line 262 : || ( system_status.poweron_reason == RTC_ALARM ) + 950 950 ; ) + 951 951 $DGL 0,228 + 952 952 00173 R40000004 cmp !_SW_pow_count,#04H ; 4 ;[INF] 4, 1 + 953 953 00177 DE0C bnc $?L0041 ;[INF] 2, 4 + 954 954 00179 R40000004 cmp !_SW_wifi_count,#04H ; 4 ;[INF] 4, 1 + 955 955 0017D DE06 bnc $?L0041 ;[INF] 2, 4 + 956 956 0017F R40010002 cmp !_system_status+1,#02H ; 2 ;[INF] 4, 1 + 957 957 00183 DF37 bnz $?L0004 ;[INF] 2, 4 + 958 958 00185 ?L0041: + 959 959 ; line 263 : { + 960 960 00185 ??bb11_tsk_sys: + 961 961 ; line 264 : system_status.pwr_state = OFF; // 若干抵抗有るが + 962 962 ; ... + 963 963 $DGL 0,230 + 964 964 00185 RE50000 oneb !_system_status ;[INF] 3, 1 + 965 965 ; line 265 : renge_task_interval_run_force = 1; + 966 966 $DGL 0,231 + 967 967 00188 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 968 968 ; line 266 : KRMK = 1; + 969 969 $DGL 0,232 + 970 970 0018B 713AE7 set1 MK1H.3 ;[INF] 3, 2 + 971 971 ; line 267 : return; + 972 972 $DGL 0,233 + 973 973 0018E D7 ret ;[INF] 1, 6 + 974 974 0018F ??eb11_tsk_sys: + 975 975 ; line 268 : } + 976 976 ; line 269 : return; + 977 977 0018F ??eb10_tsk_sys: + 978 978 ; line 270 : } + 979 979 0018F ?L0037: + 980 980 ; line 271 : else + 981 981 ; line 272 : { + 982 982 0018F ??bb12_tsk_sys: + 983 983 ; line 273 : // 省電力へ移行 + 984 984 ; line 274 : BT_TEMP_P = 0; + 985 985 $DGL 0,240 + 986 986 0018F 717301 clr1 P1.7 ;[INF] 3, 2 + 987 987 ; line 275 : while( RWST ) + 988 988 $DGL 0,241 + 989 989 00192 ?L0042: + 990 990 00192 31949E02 bf RTCC1.1,$?L0043 ;[INF] 4, 5 + 991 991 ; line 276 : {;} + 992 992 $DGL 0,242 + 993 993 00196 ??bb13_tsk_sys: + 994 994 00196 ??eb13_tsk_sys: + 995 995 00196 EFFA br $?L0042 ;[INF] 2, 3 + 996 996 00198 ?L0043: + 997 997 ; line 277 : + 998 998 ; line 278 : iic_mcu_stop( ); + 999 999 $DGL 0,244 + 1000 1000 00198 RFD0000 call !_iic_mcu_stop ;[INF] 3, 3 + 1001 1001 ; line 279 : + 1002 1002 ; line 280 : // 割り込み待ちで寝る // + 1003 1003 ; line 281 : RTCIMK = 1; + 1004 1004 $DGL 0,247 + 1005 1005 0019B 712AE7 set1 MK1H.2 ;[INF] 3, 2 + 1006 1006 ; line 282 : #ifndef _PARRADIUM_ + 1007 1007 ; line 283 : + 1008 1008 ; line 284 : #ifdef _MCU_BSR_ + 1009 1009 ; line 285 : CKC = 0b00001001; + 1010 1010 $DGL 0,251 + 1011 1011 0019E CEA409 mov CKC,#09H ; 9 ;[INF] 3, 1 + 1012 1012 ; line 286 : OSMC = 0x00; + 1013 1013 $DGL 0,252 + 1014 1014 001A1 F5F300 clrb !OSMC ;[INF] 3, 1 + 1015 1015 ; line 287 : #endif + 1016 1016 ; line 288 : STOP( ); + 1017 1017 $DGL 0,254 + 1018 1018 001A4 61FD stop ;[INF] 2, 3 + 1019 1019 ; line 289 : #ifdef _MCU_BSR_ + 1020 1020 ; line 290 : OSMC = 0x01; + 1021 1021 $DGL 0,256 + 1022 1022 001A6 E5F300 oneb !OSMC ;[INF] 3, 1 + 1023 1023 ; line 291 : CKC = 0b00001000; + 1024 1024 $DGL 0,257 + 1025 1025 001A9 CEA408 mov CKC,#08H ; 8 ;[INF] 3, 1 + 1026 1026 ; line 292 : #endif + 1027 1027 ; line 293 : + 1028 1028 ; line 294 : #endif + 1029 1029 ; line 295 : RTCIMK = 0; + 1030 1030 $DGL 0,261 + 1031 1031 001AC 712BE7 clr1 MK1H.2 ;[INF] 3, 2 + 1032 1032 ; line 296 : // 起きる // + 1033 1033 ; line 297 : + 1034 1034 ; line 298 : // 起きる条件は + 1035 1035 ; line 299 : // ・KeyReturn割り込み（電源ボたん） + 1036 1036 ; line 300 : // ・RTCアラーム + 1037 1037 ; line 301 : // ・アダプタ挿抜 + 1038 1038 ; line 302 : system_status.pwr_state = OFF; // + 1039 1039 $DGL 0,268 + 1040 1040 001AF RE50000 oneb !_system_status ;[INF] 3, 1 + 1041 1041 ; line 303 : renge_task_interval_run_force = 1; + 1042 1042 $DGL 0,269 + 1043 1043 001B2 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 1044 1044 ; line 304 : KRMK = 1; + 1045 1045 $DGL 0,270 + 1046 1046 001B5 713AE7 set1 MK1H.3 ;[INF] 3, 2 + 1047 1047 ; line 305 : return; + 1048 1048 $DGL 0,271 + 1049 1049 001B8 D7 ret ;[INF] 1, 6 + 1050 1050 001B9 ??eb12_tsk_sys: + 1051 1051 ; line 306 : } + 1052 1052 001B9 ?L0038: + 1053 1053 ; line 307 : + 1054 1054 ; line 308 : default: + 1055 1055 ; line 309 : while( 1 ) + 1056 1056 ; line 310 : { + 1057 1057 001B9 ??bb14_tsk_sys: + 1058 1058 ; line 311 : NOP( ); + 1059 1059 $DGL 0,277 + 1060 1060 001B9 00 nop ;[INF] 1, 1 + 1061 1061 001BA ??eb14_tsk_sys: + 1062 1062 ; line 312 : // あり得ないステート + 1063 1063 ; line 313 : } + 1064 1064 $DGL 0,279 + 1065 1065 001BA EFFD br $?L0038 ;[INF] 2, 3 + 1066 1066 001BC ??eb00_tsk_sys: + 1067 1067 ; line 314 : + 1068 1068 ; line 315 : } + 1069 1069 001BC ?L0004: + 1070 1070 ; line 316 : } + 1071 1071 $DGL 0,282 + 1072 1072 001BC ??ef_tsk_sys: + 1073 1073 001BC D7 ret ;[INF] 1, 6 + 1074 1074 001BD ??ee_tsk_sys: + 1075 1075 ; line 317 : + 1076 1076 ; line 318 : + 1077 1077 ; line 319 : + 1078 1078 ; line 320 : /*******************************************************//** + 1079 1079 ; line 321 : PMICが電源異常で止めたか確認 + 1080 1080 ; line 322 : **********************************************************/ + 1081 1081 ; line 323 : static void chk_emergencyExit(){ + 1082 1082 001BD _chk_emergencyExit: + 1083 1083 $DGL 1,166 + 1084 1084 001BD ??bf_chk_emergencyExit: + 1085 1085 ; line 324 : #ifndef _PARRADIUM_ + 1086 1086 ; line 325 : static state; + 1087 1087 ; line 326 : + 1088 1088 ; line 327 : if( !RESET1_n ) + 1089 1089 $DGL 0,5 + 1090 1090 001BD 31020040 bt P0.0,$?L0049 ;[INF] 4, 5 + 1091 1091 ; line 328 : { + 1092 1092 001C1 ??bb00_chk_emergencyExit: + 1093 1093 ; line 329 : if( PM_chk_LDSW( ) == 0 ) + 1094 1094 $DGL 0,7 + 1095 1095 001C1 300300 movw ax,#03H ; 3 ;[INF] 3, 1 + 1096 1096 001C4 C1 push ax ;[INF] 1, 1 + 1097 1097 001C5 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1098 1098 001C7 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3 + 1099 1099 001CA C0 pop ax ;[INF] 1, 1 + 1100 1100 001CB 62 mov a,c ;[INF] 1, 1 + 1101 1101 001CC 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 1102 1102 001CE D1 cmp0 a ;[INF] 1, 1 + 1103 1103 001CF DF07 bnz $?L0051 ;[INF] 2, 4 + 1104 1104 ; line 330 : { + 1105 1105 001D1 ??bb01_chk_emergencyExit: + 1106 1106 ; line 331 : // PMICが異常終了判断をした + 1107 1107 ; line 332 : system_status.pwr_state = OFF_TRIG; + 1108 1108 $DGL 0,10 + 1109 1109 001D1 RF50000 clrb !_system_status ;[INF] 3, 1 + 1110 1110 ; line 333 : renge_task_interval_run_force = 1; + 1111 1111 $DGL 0,11 + 1112 1112 001D4 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2 + 1113 1113 001D7 ??eb01_chk_emergencyExit: + 1114 1114 ; line 334 : } + 1115 1115 $DGL 0,12 + 1116 1116 001D7 D7 ret ;[INF] 1, 6 + 1117 1117 001D8 ?L0051: + 1118 1118 ; line 335 : else + 1119 1119 ; line 336 : { + 1120 1120 001D8 ??bb02_chk_emergencyExit: + 1121 1121 ; line 337 : if( state == 0 ) + 1122 1122 $DGL 0,15 + 1123 1123 001D8 F6 clrw ax ;[INF] 1, 1 + 1124 1124 001D9 R420000 cmpw ax,!?L0048 ; state ;[INF] 3, 1 + 1125 1125 001DC DF27 bnz $?L0050 ;[INF] 2, 4 + 1126 1126 ; line 338 : { + 1127 1127 001DE ??bb03_chk_emergencyExit: + 1128 1128 ; line 339 : state = 1; + 1129 1129 $DGL 0,17 + 1130 1130 001DE E6 onew ax ;[INF] 1, 1 + 1131 1131 001DF RBF0000 movw !?L0048,ax ; state ;[INF] 3, 1 + 1132 1132 ; line 340 : // デバッガなりがリセットをかけた + 1133 1133 ; line 341 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, + 1134 1134 ; 0 ); + 1135 1135 $DGL 0,19 + 1136 1136 001E2 F6 clrw ax ;[INF] 1, 1 + 1137 1137 001E3 C1 push ax ;[INF] 1, 1 + 1138 1138 001E4 5004 mov x,#04H ; 4 ;[INF] 2, 1 + 1139 1139 001E6 C1 push ax ;[INF] 1, 1 + 1140 1140 001E7 5084 mov x,#084H ; 132 ;[INF] 2, 1 + 1141 1141 001E9 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3 + 1142 1142 001EC 1004 addw sp,#04H ; 4 ;[INF] 2, 1 + 1143 1143 ; line 342 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] + 1144 1144 ; & 0b10011111 ); + 1145 1145 $DGL 0,20 + 1146 1146 001EE R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1 + 1147 1147 001F1 5C9F and a,#09FH ; 159 ;[INF] 2, 1 + 1148 1148 001F3 R9F0F00 mov !_vreg_ctr+15,a ;[INF] 3, 1 + 1149 1149 ; line 343 : vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ; + 1150 1150 $DGL 0,21 + 1151 1151 001F6 R71102000 set1 !_vreg_ctr+32.1 ;[INF] 4, 2 + 1152 1152 ; line 344 : renge_task_immed_add( do_command0 ); + 1153 1153 $DGL 0,22 + 1154 1154 001FA R300000 movw ax,#loww (_do_command0) ;[INF] 3, 1 + 1155 1155 001FD RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1156 1156 00200 ??eb03_chk_emergencyExit: + 1157 1157 ; line 345 : } + 1158 1158 ; line 346 : } + 1159 1159 00200 ??eb02_chk_emergencyExit: + 1160 1160 ; line 347 : } + 1161 1161 $DGL 0,25 + 1162 1162 00200 ??eb00_chk_emergencyExit: + 1163 1163 00200 D7 ret ;[INF] 1, 6 + 1164 1164 00201 ?L0049: + 1165 1165 ; line 348 : else + 1166 1166 ; line 349 : { + 1167 1167 00201 ??bb04_chk_emergencyExit: + 1168 1168 ; line 350 : state = 0; + 1169 1169 $DGL 0,28 + 1170 1170 00201 F6 clrw ax ;[INF] 1, 1 + 1171 1171 00202 RBF0000 movw !?L0048,ax ; state ;[INF] 3, 1 + 1172 1172 00205 ??eb04_chk_emergencyExit: + 1173 1173 ; line 351 : } + 1174 1174 00205 ?L0050: + 1175 1175 ; line 352 : #endif + 1176 1176 ; line 353 : } + 1177 1177 $DGL 0,31 + 1178 1178 00205 ??ef_chk_emergencyExit: + 1179 1179 00205 D7 ret ;[INF] 1, 6 + 1180 1180 00206 ??ee_chk_emergencyExit: + 1181 1181 ; line 354 : + 1182 1182 ; line 355 : + 1183 1183 ; line 356 : + 1184 1184 ; line 357 : + 1185 1185 ; line 358 : + 1186 1186 ; line 359 : /* ======================================================== + 1187 1187 ; line 360 : CPUからのスリープ要求 + 1188 1188 ; line 361 : 　ポーリングにしました。 + 1189 1189 ; line 362 : ======================================================== */ + 1190 1190 ; line 363 : /* + 1191 1191 ; line 364 : __interrupt void intp0_slp( ) + 1192 1192 ; line 365 : { // SLP + 1193 1193 ; line 366 : if( SLP_REQ ){ + 1194 1194 ; line 367 : system_status.pwr_state = SLEEP_TRIG; + 1195 1195 ; line 368 : }else{ + 1196 1196 ; line 369 : system_status.pwr_state = ON_TRIG; + 1197 1197 ; line 370 : if( PM_BL_set() != ERR_SUCCESS ){ + 1198 1198 ; line 371 : renge_task_interval_run_force = 1; + 1199 1199 ; line 372 : iic_mcu_stop(); + 1200 1200 ; line 373 : system_status.pwr_state = OFF_TRIG; + 1201 1201 ; line 374 : } + 1202 1202 ; line 375 : } + 1203 1203 ; line 376 : renge_task_interval_run_force = 1; + 1204 1204 ; line 377 : } + 1205 1205 ; line 378 : */ + 1206 1206 ; line 379 : + 1207 1207 ; line 380 : + 1208 1208 ; line 381 : + 1209 1209 ; line 382 : /*******************************************************//** + 1210 1210 ; line 383 : 全く意味ないですが、気分的な物で... + 1211 1211 ; line 384 : **********************************************************/ + 1212 1212 ; line 385 : task_status_immed tski_firm_update(){ + 1213 1213 00206 _tski_firm_update: + 1214 1214 $DGL 1,193 + 1215 1215 00206 ??bf_tski_firm_update: + 1216 1216 ; line 386 : firm_update(); + 1217 1217 $DGL 0,2 + 1218 1218 00206 RFD0000 call !_firm_update ;[INF] 3, 3 + 1219 1219 ; line 387 : return( ERR_SUCCESS ); + 1220 1220 $DGL 0,3 + 1221 1221 00209 F7 clrw bc ;[INF] 1, 1 + 1222 1222 ; line 388 : } + 1223 1223 $DGL 0,4 + 1224 1224 0020A ??ef_tski_firm_update: + 1225 1225 0020A D7 ret ;[INF] 1, 6 + 1226 1226 0020B ??ee_tski_firm_update: + 1227 1227 + 1228 1228 ----- @@CODEL CSEG + 1229 1229 + 1230 1230 ----- @@BASE CSEG BASE + 1231 1231 END + 1232 1232 + 1233 1233 + 1234 1234 ; *** Code Information *** + 1235 1235 ; + 1236 1236 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c + 1237 1237 ; + 1238 1238 ; $FUNC tsk_sys(35) + 1239 1239 ; void=(void) + 1240 1240 ; CODE SIZE= 433 bytes, CLOCK_SIZE= 384 clocks, STACK_SIZE= 12 bytes + 1241 1241 ; + 1242 1242 ; $CALL iic_mcu_start(80) + 1243 1243 ; void=(void) + 1244 1244 ; + 1245 1245 ; $CALL PM_init(83) + 1246 1246 ; void=(void) + 1247 1247 ; + 1248 1248 ; $CALL PM_sys_pow_on(85) + 1249 1249 ; bc=(void) + 1250 1250 ; + 1251 1251 ; $CALL iic_mcu_stop(88) + 1252 1252 ; void=(void) + 1253 1253 ; + 1254 1254 ; $CALL PM_LCD_vcom_set(100) + 1255 1255 ; bc=(void) + 1256 1256 ; + 1257 1257 ; $CALL LED_init(122) + 1258 1258 ; void=(void) + 1259 1259 ; + 1260 1260 ; $CALL IIC_ctr_Init(126) + 1261 1261 ; void=(void) + 1262 1262 ; + 1263 1263 ; $CALL set_irq(136) + 1264 1264 ; void=(int:ax, int:[sp+4]) + 1265 1265 ; + 1266 1266 ; $CALL IIC_twl_Init(138) + 1267 1267 ; void=(void) + 1268 1268 ; + 1269 1269 ; $CALL chk_emergencyExit(163) + 1270 1270 ; void=(void) + 1271 1271 ; + 1272 1272 ; $CALL iic_mcu_write_a_byte(173) + 1273 1273 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1274 1274 ; + 1275 1275 ; $CALL chk_emergencyExit(178) + 1276 1276 ; void=(void) + 1277 1277 ; + 1278 1278 ; $CALL iic_mcu_write_a_byte(181) + 1279 1279 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1280 1280 ; + 1281 1281 ; $CALL wait_ms(182) + 1282 1282 ; void=(int:ax) + 1283 1283 ; + 1284 1284 ; $CALL LED_stop(208) + 1285 1285 ; void=(void) + 1286 1286 ; + 1287 1287 ; $CALL IIC_ctr_Stop(209) + 1288 1288 ; void=(void) + 1289 1289 ; + 1290 1290 ; $CALL IIC_twl_Stop(210) + 1291 1291 ; void=(void) + 1292 1292 ; + 1293 1293 ; $CALL PM_sys_pow_off(235) + 1294 1294 ; bc=(void) + 1295 1295 ; + 1296 1296 ; $CALL iic_mcu_stop(278) + 1297 1297 ; void=(void) + 1298 1298 ; + 1299 1299 ; $FUNC chk_emergencyExit(323) + 1300 1300 ; void=(void) + 1301 1301 ; CODE SIZE= 73 bytes, CLOCK_SIZE= 68 clocks, STACK_SIZE= 8 bytes + 1302 1302 ; + 1303 1303 ; $CALL iic_mcu_read_a_byte(329) + 1304 1304 ; bc=(int:ax, int:[sp+4]) + 1305 1305 ; + 1306 1306 ; $CALL iic_mcu_write_a_byte(341) + 1307 1307 ; bc=(int:ax, int:[sp+4], int:[sp+6]) + 1308 1308 ; + 1309 1309 ; $CALL renge_task_immed_add(344) + 1310 1310 ; bc=(pointer:ax) + 1311 1311 ; + 1312 1312 ; $FUNC tski_firm_update(385) + 1313 1313 ; bc=(void) + 1314 1314 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes + 1315 1315 ; + 1316 1316 ; $CALL firm_update(386) + 1317 1317 ; bc=(void) + 1318 1318 + 1319 1319 ; Target chip : uPD79F0104 + 1320 1320 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00002H @@R_INIT +00000 00002H @@INIT +00000 00002H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 0020BH ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/task_sys.rel b/branches/0.10(X3)/task_sys.rel new file mode 100644 index 0000000..41dd882 Binary files /dev/null and b/branches/0.10(X3)/task_sys.rel differ diff --git a/branches/0.10(X3)/user_define.h b/branches/0.10(X3)/user_define.h new file mode 100644 index 0000000..9699834 --- /dev/null +++ b/branches/0.10(X3)/user_define.h @@ -0,0 +1,279 @@ +#ifndef _USER_DEF_ +#define _USER_DEF_ + +#define IIC_SLV_ADDR_MONITOR 0x6E +#define IIC_T_SLAVEADDRESS 0x4A +#define IIC_C_SLAVEADDRESS 0x4A + +#define IIC_SLA_DCP 0x50 + +#ifdef _debug_ + +// 8ドットのLED +#define IIC_SLA_8LEDS 0x42 +#define IIC_8LEDS_REG_DO 1 +#define IIC_8LEDS_REG_DI 2 +#define IIC_8LEDS_REG_DIR 3 + +// 7セグ 4バイト版 +#define IIC_SLA_DBG_MONITOR 0x44 + + +#endif + +#ifdef _debug_led_ +#define DBG_LED_WIFI_2_on { PM2.4 = 0; P2.4 = 1; } +#define DBG_LED_WIFI_2_off { PM2.4 = 1; P2.4 = 0; } +#define DBG_LED_WIFI_2_toggle ( P2.4 ^= 1 ) + +#else +#define DBG_LED_WIFI_2_on ; +#define DBG_LED_WIFI_2_off ; +#define DBG_LED_WIFI_2_toggle ; +#endif + + +#ifdef _PMIC_TWL_ +#define PM_TEG_PWSW P7.5 // TEGのみ +#define PM_TEG_LCD_dis( val ) ( P7.6 = val ) // TEGのみ + +#else + +#define SLP_ACK P7.7 +#endif + + +#define IIC_SLA_CODEC 0xA4 +#define IIC_SLA_ACCEL 0x30 // ST LIS331DLH + + +// PMxは0で出力モード + +// SoC +#ifdef _MODEL_TEG2_ +#define IRQ0_ast { P3.0 = 0; PM3.0 = 0; } +#define IRQ0_neg { PM3.0 = 1; } +#define IRQ0 ( P3.0 ) +#endif +#ifdef _MODEL_WM0_ +#define IRQ0_ast { P3.0 = 0; PM3.0 = 0; } +#define IRQ0_neg { PM3.0 = 1; } +#define IRQ0 ( P3.0 ) +#endif + +#ifdef _MODEL_TS0_ +#define IRQ0_ast { P7.6 = 0; PM7.6 = 0; } +#define IRQ0_neg { PM7.6 = 1; } +#define IRQ0 ( P7.6 ) +#endif +#ifdef _MODEL_CTR_ +#define IRQ0_ast { P7.6 = 0; PM7.6 = 0; } +#define IRQ0_neg { PM7.6 = 1; } +#define IRQ0 ( P7.6 ) +#endif + + +// ↓誤代入防止 +#define RESET1_n ( P0.0 ) + +#if 0 // PM_RESET1〜を使う +#define RESET1_ast { P0.0 = 0; PM0.0 = 0; } +#define RESET1_neg { PM0.0 = 1; } +#endif + +#define RESET2_ast { P0.1 = 0; PM0.1 = 0; } +#define RESET2_neg { PM0.1 = 1; } + +#ifndef _PARRADIUM_ +#define SLP_REQ P12.0 +#else +#define SLP_REQ 0 +#endif + +// FCRAM +#ifdef _MODEL_TEG2_ +#define FCRAM_RST P14.0 +#define FCRAM_RST_ast { P14.0 = 0; } +#define FCRAM_RST_neg { P14.0 = 1; } +#endif +#ifdef _MODEL_WM0_ +#define FCRAM_RST P14.0 +#define FCRAM_RST_ast { P14.0 = 0; } +#define FCRAM_RST_neg { P14.0 = 1; } +#endif + +#ifdef _MODEL_TS0_ +#define FCRAM_RST P3.0 +#define FCRAM_RST_ast { P3.0 = 0; } +#define FCRAM_RST_neg { P3.0 = 1; } +#endif +#ifdef _MODEL_CTR_ +#define FCRAM_RST P3.0 +#define FCRAM_RST_ast { P3.0 = 0; } +#define FCRAM_RST_neg { P3.0 = 1; } +#endif + + +// CODEC +#define PM_IRQ_n P7.2 +// INTP6 + +#ifndef _MODEL_CTR_ +#define SND_DEPOP_ACT P7.6 = 1 +#define SND_DEPOP_DEACT P7.6 = 0 +#else +#define SND_DEPOP_ACT ; +#define SND_DEPOP_DEACT ; +#endif + +// PM +#define PM_EXTDC_n P7.0 +// INTP7 +//#define BT_TEMP P15.0 +// ANI8 +//#define BT_DET P15.1 +// ANI9 +#define BT_DET_P P1.6 +#define BT_TEMP_P P1.7 + + +// 充電せよ(out) +#ifdef _PMIC_CTR_ +#define BT_CHG_ENABLE() ( P4.3 = 0 ) +#define BT_CHG_DISABLE() ( P4.3 = 1 ) +#else +#define BT_CHG_ENABLE() ( P4.2 = 0 ) +#define BT_CHG_DISABLE() ( P4.2 = 1 ) +#endif + +#ifdef PM_CCIC_TIM +#define PM_CHG_TIMEOUT_ENABLE() ( P5.0 = 0 ) +#define PM_CHG_TIMEOUT_DISABLE() ( P5.0 = 1 ) +#else +#define PM_CHG_TIMEOUT_ENABLE() ; +#define PM_CHG_TIMEOUT_DISABLE() ; +#endif + +// 充電中(in) +#define BT_CHG_n P5.1 + +#define SW_WIFI_n P7.4 +// KR4 +#define SW_POW_n P7.3 +// KR3 +#define SW_SEL_n P2.3 +//#define VOL P2.7 +// ANI7 + +#define SW_HOME_n_JIKKI P20.4 +// INTP22 +#define SW_HOME_n_TSBOARD P2.0 + +// WiFi +#ifndef _TEG_ +#define WL_TX P20.3 // INTP21 +#define WL_RX P20.2 // INTP20 +#else +#define WL_TX P20.3 // INTP21 +#define WL_RX P20.2 // INTP20 +#endif + +//#define LED_CAM P1.0 // TO02 +//#define LED_WIFI P1.1 // TO03 +//#define LED_NOTIFY P1.3 // TO05 +//#define LED_TUNE P5.2 // SLTO ← TO01 +//#define LED_POW2 P1.4 // TO06 ( 青 ) +//#define LED_POW1 P1.5 // TO07 ( 赤 ) +#define LED_CHARGE P2.4 + + +#ifdef _MODEL_CTR_ +// P5.3 に加え、P5.5, P140 P141 +// P140が出力専用なので... +#define I2C_PU_on() { PM5.3 = 1; PM3.3 = 1; P14 |= 0x03; P5.3 = 1; PM5.3 = 0; P3.3 = 1; PM3.3 = 0; } +#define I2C_PU_off() { PM5.3 = 1; PM3.3 = 1; P14 &= ~0x03; P5.3 = 0; PM5.3 = 0; P3.3 = 0; PM3.3 = 0; } +#endif + +//#define I2C_M_SDA P3.1 // SDA10 +//#define I2C_M_SCL P3.2 // SCL10 + +//#define I2C_0_SCL P6.0 // IIC_TWL SCL0 +//#define I2C_0_SDA P6.1 // SDA0 + +//#define I2C_1_SCL P20.0 // IIC CTR SCL1 +//#define I2C_1_SDA P20.1 // SDA1 + +//#define 32kHz_O P1.2 // RTCCL +//#define 32k_I1 P12.3 // XT1 +//#define 32k_I2 P12.4 // XT2 + +#define DIPSW_0 P4.0 // mini cube ソフトウェアディップスイッチ +#define DIPSW_1 P4.1 // mini cube ソフトウェアディップスイッチ + +#ifndef _MODEL_WM0_ +#define SHELL_OPEN P7.1 // INTP5 ふた開閉 (閉じると?) +#else +#define SHELL_OPEN 1 +#endif + +//#define DBG_VR P2.6 +// ANI6 + +#define DBG P14.1 + +#ifdef _MODEL_TEG2_ +#define ACC_VALID P15.2 +#define ACCEL_INT1 P2.5 +#endif + +#ifdef _MODEL_TS0_ || _MODEL_CTR_ +#define ACC_VALID P20.5 +#define ACCEL_INT1 P2.5 +#endif + +#ifdef _MODEL_WM0_ +// テレコになっていたが、センサ側の設定を変えたため、TS0と同じでよい +#define ACC_VALID P20.5 +#define ACCEL_INT1 P2.5 +#endif + +#ifdef _MODEL_CTR_ +#define ACC_VALID P20.5 +#define ACCEL_INT1 P2.5 +#endif + + + +#define DBG_M_n P2.1 +#define DBG_P_n P2.2 + + + +#define KR_SW_POW ( 1 << 3 ) +#define KR_SW_WIFI ( 1 << 4 ) + + +#define INT_MSK0_IIC_M_DMA 0b0001000000000000 +#define INT_MSK0_SHELL 0b0000000010000000 +#define INT_MSK0_EXTDC 0b0000000001000000 +//#define INT_MSK0_SLP 0b0000000000000100 ) +//#define INT_MSK0_RSV 0b1110111100111011 ) +#define INT_MSK0_RSV 0b1110111100111111 + +#define INT_MSK1_KR 0b0000100000000000 +#define INT_MSK1_RTCINTVAL 0b0000010000000000 +#define INT_MSK1_RTCALARM 0b0000001000000000 +#define INT_MSK1_ADC 0b0000000100000000 +#define INT_MSK1_IIC_CTR 0b0000000000001000 +#define INT_MSK1_IIC_MCU 0b0000000000000001 +#define INT_MSK1_RSV 0b1111000011110110 + +#define INT_MSK2_WIFI_TX_KE3 0b00010000 +#define INT_MSK2L_RSV 0b11101111 + +#define INT_MSK2_IIC_TWL ( 0b0000000100000000 ) +#define INT_MSK2_WIFI_TX_BSR ( 0b0000010000000000 ) +#define INT_MSK2_CODEC_PMIRQ ( 0b0000000000001000 ) +#define INT_MSK2_RSV 0b1111101111110111 + +#endif diff --git a/branches/0.10(X3)/vreg_ctr.c b/branches/0.10(X3)/vreg_ctr.c new file mode 100644 index 0000000..b65f0e8 --- /dev/null +++ b/branches/0.10(X3)/vreg_ctr.c @@ -0,0 +1,407 @@ +/* ======================================================== + +CTR MCU I2Cレジスタ + + ====================================================== */ +#include "incs.h" +#include "vreg_ctr.h" +#include "rtc.h" +#include "led.h" +#include "accero.h" +#include "pm.h" + +#include +#include "fsl_user.h" + +extern u8 mcu_info_read(); // task_misc.c + + + +// ******************************************************** +u8 vreg_ctr[VREG_C_ENDMARK_]; + +bit irq_readed; // AAA型のため。 + +extern bit update; +extern u16 pool[]; + + +// ******************************************************** +extern task_status_immed tski_firm_update(); +extern task_status_immed tski_mcu_info_read(); + +// ******************************************************** +#ifdef _MCU_BSR_ +#define IICAMK IICAMK1 +#endif + + +// ******************************************************** +// 非ゼロの初期値の指定が必要なアドレス +void vreg_ctr_init( ) +{ + vreg_ctr[VREG_C_LED_BRIGHT] = 0xFF; + +#ifdef _PMIC_TWL_ + vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR; +#else + vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR | 0x10; +#endif + vreg_ctr[VREG_C_MCU_VER_MINOR] = MCU_VER_MINOR; + + vreg_ctr[VREG_C_VCOM_T] = VCOM_DEFAULT_T; + vreg_ctr[VREG_C_VCOM_B] = VCOM_DEFAULT_B; +} + + + + +// ******************************************************** +// I2C仮想レジスタに書きます。 +//　引数 adrs は内部アドレス +// 　書けないアドレスにアクセスした場合、何もしません。 +// ●書き込んだ結果、I2C_mcu通信が発生する場合、renge_task_immed_add() +// を使用しないと、I2C_mcu使用中でエラー終了した場合にリトライしません。 +void vreg_ctr_write( u8 adrs, u8 data ) +{ + if( adrs >= VREG_C_ENDMARK_ ) + return; + + switch ( adrs ) + { + + case ( VREG_C_MCU_STATUS ): + vreg_ctr[adrs] = data; + vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( ( data & 0xC0 ) >> 6 ); + break; + + case ( VREG_C_VCOM_T ): + case ( VREG_C_VCOM_B ): + renge_task_immed_add( tski_vcom_set ); + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_DBG1 ): + case ( VREG_C_DBG2 ): + vreg_ctr[adrs] = data; + break; + case ( VREG_C_DBG3 ): + vreg_ctr[adrs] = data; + if( ( vreg_ctr[VREG_C_DBG1] == 'j' ) + && ( vreg_ctr[VREG_C_DBG2] == 'h' ) + && ( data == 'l' ) ) + { + renge_task_immed_add( tski_firm_update ); + IICAMK = 1; + } + break; + + case ( VREG_C_IRQ_MASK0 ): + case ( VREG_C_IRQ_MASK1 ): + case ( VREG_C_IRQ_MASK2 ): + case ( VREG_C_IRQ_MASK3 ): + case ( VREG_C_IRQ_MASK4 ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_COMMAND0 ): + vreg_ctr[adrs] |= data; + if( data != 0 ) + { + renge_task_immed_add( do_command0 ); + } + break; + + case ( VREG_C_COMMAND2 ): + // こちらからの完了割り込みを待ってくれないそうです。 #-ω-) 何のための割り込みだ + // 液晶電源 + if(( data & REG_BIT_CMD_LCD_ON ) != 0 ) + { + renge_task_immed_add( tski_PM_LCD_on ); + } + else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 ) + { + renge_task_immed_add( tski_PM_LCD_off ); + } + + // バックライト設定 + /// 今のところさらに細かくは分けないけど… + if(( data & REG_BITS_CMD_BL ) != 0 ) + { + vreg_ctr[adrs] = ( data & REG_BITS_CMD_BL ); + renge_task_immed_add( tski_PM_BL_set ); + } + break; + + case ( VREG_C_COMMAND1 ): + if( data != 0 ) + { + // TWLに割り込みを入れる + /// 実際に割り込みを入れるのはSoC + vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT_SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; //pwsw_det + vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; //reset_req + + vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //off_req + + vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; //batt_low + vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; //batt_empty + + vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00; //vol_changed + } + break; + + case ( VREG_C_DBG20 ): + case ( VREG_C_DBG21 ): + case ( VREG_C_DBG22 ): + case ( VREG_C_DBG23 ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_FREE_0 ): + case ( VREG_C_FREE_1 ): + case ( VREG_C_FREE_2 ): + case ( VREG_C_FREE_3 ): + case ( VREG_C_FREE_4 ): + case ( VREG_C_FREE_5 ): + case ( VREG_C_FREE_6 ): + case ( VREG_C_FREE_7 ): + case ( VREG_C_FREE_8 ): + case ( VREG_C_FREE_9 ): + case ( VREG_C_FREE_A ): + case ( VREG_C_FREE_B ): + case ( VREG_C_FREE_C ): + case ( VREG_C_FREE_D ): + case ( VREG_C_FREE_E ): + case ( VREG_C_FREE_F ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_LED_BRIGHT ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_LED_POW ): + case ( VREG_C_LED_WIFI ): + case ( VREG_C_LED_CAM ): + case ( VREG_C_LED_TUNE ): + case ( VREG_C_LED_NOTIFY ): + vreg_ctr[adrs] = data & 0x0F; + break; + + /// 非同期で動いているためここでは書かない。 + // 予約するだけでstopで書く + case ( VREG_C_RTC_SEC ): + case ( VREG_C_RTC_MIN ): + set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F ); + break; + + case ( VREG_C_RTC_HOUR ): + set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); + break; + + case ( VREG_C_RTC_YOBI ): + set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 ); + break; + + case ( VREG_C_RTC_DAY ): + set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); + break; + + case ( VREG_C_RTC_MONTH ): + set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F ); + break; + + case ( VREG_C_RTC_YEAR ): + set_rtc( adrs - VREG_C_RTC_SEC, data ); + break; + + case ( VREG_C_RTC_COMP ): + vreg_ctr[adrs] = data; + SUBCUD = data; + break; + + case ( VREG_C_RTC_ALARM_MIN ): + vreg_ctr[adrs] = ( data & 0x7F ); + rtc_alarm_dirty = 1; + break; + + case ( VREG_C_RTC_ALARM_HOUR ): + vreg_ctr[adrs] = ( data & 0x3F ); + rtc_alarm_dirty = 1; + break; + + // 書くだけでよい + case ( VREG_C_RTC_ALARM_DAY ): + vreg_ctr[adrs] = ( data & 0x3F ); + break; + + case ( VREG_C_RTC_ALARM_MONTH ): + vreg_ctr[adrs] = ( data & 0x1F ); + break; + + case ( VREG_C_RTC_ALARM_YEAR ): + vreg_ctr[adrs] = data; + break; + + + case ( VREG_C_ACC_CONFIG ): + vreg_ctr[adrs] = data; + renge_task_immed_add( acc_hosu_set ); + break; + + case ( VREG_C_ACC_R_ADRS ): + vreg_ctr[adrs] = data; + renge_task_immed_add( acc_read ); + break; + + case ( VREG_C_ACC_W_ADRS ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_ACC_W_BUF ): + vreg_ctr[adrs] = data; + renge_task_immed_add( acc_write ); + break; + + case ( VREG_C_ACC_HOSU_L ): + case ( VREG_C_ACC_HOSU_M ): + case ( VREG_C_ACC_HOSU_H ): + vreg_ctr[adrs] = data; + break; + + case ( VREG_C_ACC_HOSU_SETTING ): + if( ( data & 0x01 ) != 0 ) + { + clear_hosu_hist(); // 履歴クリア + } + break; + + case ( VREG_C_COMMAND3 ): + vreg_ctr[adrs] = data; + switch ( data ) + { + case ( 'r' ): + // 割り込みルーチンからFSLライブラリを呼ぶのは禁止のため +// renge_task_immed_add( tski_mcu_reset ); +// break; + + case ( 'w' ): + // WDTで再起動（テスト向け） + WDTE = 0xAA; + break; + } + } + return; +} + + + +// ******************************************************** +// I2C仮想レジスタから読みます。 +// 戻り： xx データ +// 注意：次のアドレスの準備で呼ばれる ので、 +// リードされたらクリアなどは気をつける +u8 vreg_ctr_read( u8 adrs ) +{ + static u16 rsub_temp; + + // RTCは読み出し途中に繰り上がるのを避けるため + if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR ) ) + { + rtc_buf_reflesh( ); + } + else if( adrs == VREG_C_MCU_STATUS ) + { + return( vreg_ctr[ VREG_C_MCU_STATUS ] | ( ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) ); + } + else if( adrs == VREG_C_ACC_HOSU_HIST ) + { + return( hosu_read() ); + } + else if( adrs == VREG_C_RTC_SEC_FINE_L ) + { + rsub_temp = RSUBC; + return( (u8)( rsub_temp & 0xFF ) ); + } + else if( adrs == VREG_C_RTC_SEC_FINE_H ) + { + return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) ); + } + else if( adrs == VREG_C_INFO ) + { + renge_task_immed_add( tski_mcu_info_read ); + IICAMK = 1; + return( 0x4A ); + } + +#if 1 + if( adrs >= VREG_C_ENDMARK_ ) + { + // VREG_C_INFO > VREG_C_ENDMARK_ なので + // いじるときは注意 + return( 0xEE ); + } +#endif + return ( vreg_ctr[adrs] ); +} + + + +// ******************************************************** +// I2C仮想レジスタから読まれて何かするレジスタ +void vreg_ctr_after_read( u8 adrs ) +{ + + // 割り込みフラグはリードでクリア + switch( adrs ) + { + case VREG_C_IRQ0: + case VREG_C_IRQ1: + case VREG_C_IRQ2: + case VREG_C_IRQ3: + case VREG_C_IRQ4: + vreg_ctr[ adrs ] = 0; + irq_readed = 1; + break; + + default: + break; + } +} + + + + + + +/****************************************************************************** + 割り込みを入れる + 割り込みマスクが必要と言うことでこんな事をする羽目になりました + *****************************************************************************/ +#if 0 +// マスクされてたら、フラグは立てるが、割り込みは入れない。 +#define set_irq( irqreg, bitpos ) \ +{ \ + vreg_ctr[ irqreg ] |= bitpos; \ + if( ( vreg_ctr[ irqreg+8 ] & bitpos ) == 0 ){ \ + IRQ0_ast; \ + } \ +} +#endif + +// マスクされてたら、フラグも立てず、割り込みも入れない。 +void set_irq( u8 irqreg, u8 irq_flg ) +{ + u8 tot; + + DI(); + if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 ){ + vreg_ctr[ irqreg ] |= irq_flg; + IRQ0_neg; // 一瞬上げて落とし直す。 +// EI(); + tot = 0; + while( !IRQ0 && ( ++tot != 0 ) ){;} // O.D.なのでちゃんとあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) + IRQ0_ast; + } + EI(); +} diff --git a/branches/0.10(X3)/vreg_ctr.h b/branches/0.10(X3)/vreg_ctr.h new file mode 100644 index 0000000..19c1557 --- /dev/null +++ b/branches/0.10(X3)/vreg_ctr.h @@ -0,0 +1,272 @@ +#ifndef __vreg_ctr__ +#define __vreg_ctr__ + + +#include "config.h" + +#define REG_BIT__SYS_MODE0 0b01000000 +#define REG_BIT_MCU_FIRMBROKEN 0b10000000 + + +// VREG_C_MCU_STATUS +#define REG_BIT_STATUS_WDT_RESET ( 1 << 1 ) +#define REG_BIT_RTC_BLACKOUT ( 1 << 0 ) + + +// VREG_C_STATUS, +#define REG_BIT_LCD_POW ( 1 << 7 ) +#define REG_BIT_BL_U ( 1 << 6 ) +#define REG_BIT_BL_L ( 1 << 5 ) +#define REG_BIT_BATT_CHARGE ( 1 << 4 ) +#define REG_BIT_POW_SUPPLY ( 1 << 3 ) +// 未使用 ( 1 << 2 ) +#define REG_BIT_ST_SHELL_OPEN ( 1 << 1 ) +// 未使用 ( 1 << 0 ) + + +// VREG_C_STATUS_X +// 未使用 ( 1 << 6 ) +// 未使用 ( 1 << 5 ) +// 未使用 ( 1 << 4 ) +// 未使用 ( 1 << 3 ) +// 未使用 ( 1 << 2 ) +#define REG_BIT_ACCERO_ERR ( 1 << 1 ) +#define REG_BIT_GASGAUGE_ERR ( 1 << 0 ) + + + +// VREG_C_IRQ0 +#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 7 ) +#define REG_BIT_IRQ_WDT_RESET ( 1 << 7 ) +#define REG_BIT_SHELL_OPEN ( 1 << 6 ) +#define REG_BIT_SHELL_CLOSE ( 1 << 5 ) +#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 ) +#define REG_BIT_SW_HOME_HOLD ( 1 << 3 ) +#define REG_BIT_SW_HOME_CLICK ( 1 << 2 ) +#define REG_BIT_SW_POW_HOLD ( 1 << 1 ) +#define REG_BIT_SW_POW_CLICK ( 1 << 0 ) + +// VREG_C_IRQ1 +#define REG_BIT_BT_CHG_START ( 1 << 7 ) +#define REG_BIT_BT_CHG_STOP ( 1 << 6 ) +#define REG_BIT_BT_REMAIN ( 1 << 5 ) +#define REG_BIT_ACC_DAT_RDY ( 1 << 4 ) +#define REG_BIT_ACC_ACK ( 1 << 3 ) +#define REG_BIT_RTC_ALARM ( 1 << 2 ) +#define REG_BIT_BT_DC_CONNECT ( 1 << 1 ) +#define REG_BIT_BT_DC_DISC ( 1 << 0 ) + +// VREG_C_IRQ2 +#define REG_BIT_TWL_SNDVOL_CHANGE ( 1 << 6 ) +#define REG_BIT_TWL_BL_U_ON ( 1 << 5 ) +#define REG_BIT_TWL_BL_U_OFF ( 1 << 4 ) +#define REG_BIT_TWL_BL_L_ON ( 1 << 3 ) +#define REG_BIT_TWL_BL_L_OFF ( 1 << 2 ) +#define REG_BIT_TWL_OFF_REQ ( 1 << 1 ) +#define REG_BIT_TWL_RESET_REQ ( 1 << 0 ) + +// VREG_C_IRQ3 +#define REG_BIT_BL_U_ON ( 1 << 5 ) +#define REG_BIT_BL_U_OFF ( 1 << 4 ) +#define REG_BIT_BL_L_ON ( 1 << 3 ) +#define REG_BIT_BL_L_OFF ( 1 << 2 ) +#define REG_BIT_LCD_ON ( 1 << 1 ) +#define REG_BIT_LCD_OFF ( 1 << 0 ) + + +// そのうちどこかに... +//#define REG_BIT_VR_TUNE_CHANGE ( 1 << 7 ) + + + +// VREG_C_COMMAND0 +//#define REG_BIT_CMD_LCD_ON ( 1 << 7 ) +//#define REG_BIT_CMD_LCD_OFF ( 1 << 6 ) +//#define REG_BIT_CMD_BL_ON ( 1 << 5 ) +//#define REG_BIT_CMD_BL_OFF ( 1 << 4 ) +#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 ) +#define REG_BIT_RESET2_REQ ( 1 << 2 ) +#define REG_BIT_RESET1_REQ ( 1 << 1 ) +#define REG_BIT_OFF_REQ ( 1 << 0 ) + +// VREG_C_COMMAND1 (TWLに割り込みを入れる) +// 未使用 ( 1 << 7 ) +// 未使用 ( 1 << 6 ) +#define REG_BIT_SEND_TWL_VOL_CLICK ( 1 << 5 ) +#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 ) +#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 ) +#define REG_BIT_SEND_TWL_OFF_DET ( 1 << 2 ) +#define REG_BIT_SEND_TWL_RESET_DET ( 1 << 1 ) +#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 ) + +// VREG_C_COMMAND2 液晶関係 +#define REG_BIT_CMD_BL_U_ON ( 1 << 5 ) +#define REG_BIT_CMD_BL_U_OFF ( 1 << 4 ) +#define REG_BIT_CMD_BL_L_ON ( 1 << 3 ) +#define REG_BIT_CMD_BL_L_OFF ( 1 << 2 ) +#define REG_BIT_CMD_LCD_ON ( 1 << 1 ) +#define REG_BIT_CMD_LCD_OFF ( 1 << 0 ) +#define REG_BITS_CMD_BL ( REG_BIT_CMD_BL_U_ON | REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_ON | REG_BIT_CMD_BL_L_OFF ) + + +// ↑TWLに通知するIRQレジスタ +#define REG_BIT_TWL_IRQ_PWSW_DET 0x08 +#define REG_BIT_TWL_IRQ_RESET 0x01 +#define REG_BIT_TWL_IRQ_OFF 0x02 +#define REG_BIT_TWL_IRQ_BT_LOW 0x20 +#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10 +#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40 + + +// CODEC上のPMIC NTR の代理レジスタ +#define REG_BIT_TWL_REQ_OFF ( 1 << 6 ) +#define REG_BIT_TWL_REQ_BL_U ( 1 << 3 ) +#define REG_BIT_TWL_REQ_BL_L ( 1 << 2 ) +#define REG_BIT_TWL_REQ_RESET ( 1 << 0 ) + + +/* + テンプレ +#define REG_BIT_ ( 1 << 7 ) +#define REG_BIT_ ( 1 << 6 ) +#define REG_BIT_ ( 1 << 5 ) +#define REG_BIT_ ( 1 << 4 ) +#define REG_BIT_ ( 1 << 3 ) +#define REG_BIT_ ( 1 << 2 ) +#define REG_BIT_ ( 1 << 1 ) +#define REG_BIT_ ( 1 << 0 ) +*/ + + + +/*============================================================================*/ +extern u8 vreg_ctr[]; + +/*============================================================================*/ +enum VREG_C +{ // 未定義アドレスへ書き込んだ際の動作は不定 + VREG_C_MCU_VER_MAJOR = 0x00, + VREG_C_MCU_VER_MINOR, + VREG_C_MCU_STATUS, + + VREG_C_VCOM_T = 0x03, + VREG_C_VCOM_B, + + VREG_C_DBG1 = 0x05, + VREG_C_DBG2, + VREG_C_DBG3, + + VREG_C_TUNE = 0x08, + VREG_C_SND_VOL, + VREG_C_BT_TEMP, + VREG_C_BT_REMAIN, + VREG_C_BT_REMAIN_FINE, + VREG_C_BT_VOLTAGE, + + VREG_C_STATUS_1 = 0x0E, + VREG_C_STATUS = 0x0F, + + VREG_C_IRQ0 = 0x10, + VREG_C_IRQ1, + VREG_C_IRQ2, + VREG_C_IRQ3, + VREG_C_IRQ4, + + VREG_C_IRQ_MASK0 = 0x18, + VREG_C_IRQ_MASK1, + VREG_C_IRQ_MASK2, + VREG_C_IRQ_MASK3, + VREG_C_IRQ_MASK4, + + VREG_C_COMMAND0 = 0x20, + VREG_C_COMMAND1, + VREG_C_COMMAND2, + VREG_C_COMMAND3, // 'r' でマイコンリセット + + VREG_C_DBG20 = 0x24, + VREG_C_DBG21, + VREG_C_DBG22, + VREG_C_DBG23, + + VREG_C_LED_BRIGHT = 0x28, + VREG_C_LED_POW, + VREG_C_LED_WIFI, + VREG_C_LED_CAM, + VREG_C_LED_TUNE, + VREG_C_LED_NOTIFY, + + VREG_C_RTC_SEC = 0x30, + VREG_C_RTC_MIN, + VREG_C_RTC_HOUR, + VREG_C_RTC_YOBI, + VREG_C_RTC_DAY, + VREG_C_RTC_MONTH, + VREG_C_RTC_YEAR, + + VREG_C_RTC_COMP, + + VREG_C_RTC_ALARM_MIN = 0x38, + VREG_C_RTC_ALARM_HOUR, + VREG_C_RTC_ALARM_DAY, + VREG_C_RTC_ALARM_MONTH, + VREG_C_RTC_ALARM_YEAR, + + VREG_C_RTC_SEC_FINE_L, + VREG_C_RTC_SEC_FINE_H, + + VREG_C_ACC_CONFIG = 0x40, + VREG_C_ACC_R_ADRS, + VREG_C_ACC_RESERVE, + VREG_C_ACC_W_ADRS, + VREG_C_ACC_W_BUF, + + VREG_C_ACC_XL = 0x45, + VREG_C_ACC_XH, + VREG_C_ACC_YL, + VREG_C_ACC_YH, + VREG_C_ACC_ZL, + VREG_C_ACC_ZH, + + VREG_C_ACC_HOSU_L = 0x4B, + VREG_C_ACC_HOSU_M, + VREG_C_ACC_HOSU_H, + VREG_C_ACC_HOSU_SETTING, + VREG_C_ACC_HOSU_HIST = 0x4F, + +// VREG_C_AMBIENT_BRIGHTNESS = 0x60, + +// 歩数計の評価のため... + VREG_C_FREE_0 = 0x50, + VREG_C_FREE_1, + VREG_C_FREE_2, + VREG_C_FREE_3, + VREG_C_FREE_4, + VREG_C_FREE_5, + VREG_C_FREE_6, + VREG_C_FREE_7, + VREG_C_FREE_8, + VREG_C_FREE_9, + VREG_C_FREE_A, + VREG_C_FREE_B, + VREG_C_FREE_C, + VREG_C_FREE_D, + VREG_C_FREE_E, + VREG_C_FREE_F, + + VREG_C_ENDMARK_ +}; +#define VREG_C_INFO 0x7F + +/* + VREG_C_PM_INFO, // 未使用 + VREG_C_BT_INFO, // 未使用 +*/ + +/*============================================================================*/ +void vreg_ctr_init( ); +void vreg_ctr_write( u8 adrs, u8 data ); +u8 vreg_ctr_read( u8 phy_adrs ); +void vreg_ctr_after_read( u8 adrs ); +void set_irq( u8 irqreg, u8 irq_flg ); + +#endif diff --git a/branches/0.10(X3)/vreg_ctr.prn b/branches/0.10(X3)/vreg_ctr.prn new file mode 100644 index 0000000..c6e9fa6 --- /dev/null +++ b/branches/0.10(X3)/vreg_ctr.prn @@ -0,0 +1,1648 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\vreg_ctr.asm +Para-file: +In-file: inter_asm\vreg_ctr.asm +Obj-file: vreg_ctr.rel +Prn-file: vreg_ctr.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_ctr.c + 6 6 ; In-file : vreg_ctr.c + 7 7 ; Asm-file : inter_asm\vreg_ctr.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 0A1H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, vreg_ctr.c + 18 18 $DGS MOD_NAM, vreg_ctr, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H + 36 36 $DGS AUX_TAG, 01H, 019H + 37 37 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H + 38 38 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H + 39 39 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H + 40 40 $DGS AUX_EOS, 013H, 01H + 41 41 $DGS LAB_SYM, bs_S0105, U, U, 00H, 06H, 00H, 00H + 42 42 $DGS LAB_SYM, es_S0105, U, U, 00H, 06H, 00H, 00H + 43 43 $DGS LAB_SYM, bs_S0106, U, U, 00H, 06H, 00H, 00H + 44 44 $DGS LAB_SYM, es_S0106, U, U, 00H, 06H, 00H, 00H + 45 45 $DGS LAB_SYM, bs_S0104, U, U, 00H, 06H, 00H, 00H + 46 46 $DGS LAB_SYM, es_S0104, U, U, 00H, 06H, 00H, 00H + 47 47 $DGS LAB_SYM, bs_F0102, U, U, 00H, 06H, 00H, 00H + 48 48 $DGS LAB_SYM, es_F0102, U, U, 00H, 06H, 00H, 00H + 49 49 $DGS LAB_SYM, bs_S0103, U, U, 00H, 06H, 00H, 00H + 50 50 $DGS LAB_SYM, es_S0103, U, U, 00H, 06H, 00H, 00H + 51 51 $DGS LAB_SYM, bs_F0101, U, U, 00H, 06H, 00H, 00H + 52 52 $DGS LAB_SYM, es_F0101, U, U, 00H, 06H, 00H, 00H + 53 53 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 54 54 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 55 55 $DGS GLV_SYM, _vreg_ctr_init, U, U, 01H, 026H, 01H, 02H + 56 56 $DGS AUX_FUN, 00H, U, U, 02DH, 00H, 00H + 57 57 $DGS BEG_FUN, ??bf_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H + 58 58 $DGS AUX_BEG, 02AH, 00H, 02DH + 59 59 $DGS END_FUN, ??ef_vreg_ctr_init, U, U, 00H, 065H, 01H, 00H + 60 60 $DGS AUX_END, 0DH + 61 61 $DGS GLV_SYM, _vreg_ctr_write, U, U, 01H, 026H, 01H, 02H + 62 62 $DGS AUX_FUN, 00H, U, U, 059H, 00H, 00H + 63 63 $DGS BEG_FUN, ??bf_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H + 64 64 $DGS AUX_BEG, 042H, 02H, 033H + 65 65 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 66 66 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H + 67 67 $DGS BEG_BLK, ??bb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 68 68 $DGS AUX_BEG, 06H, 00H, 035H + 69 69 $DGS BEG_BLK, ??bb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 70 70 $DGS AUX_BEG, 01CH, 00H, 039H + 71 71 $DGS END_BLK, ??eb01_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 72 72 $DGS AUX_END, 01FH + 73 73 $DGS BEG_BLK, ??bb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 74 74 $DGS AUX_BEG, 02DH, 00H, 03DH + 75 75 $DGS END_BLK, ??eb02_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 76 76 $DGS AUX_END, 02FH + 77 77 $DGS BEG_BLK, ??bb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_BEG, 036H, 00H, 041H + 79 79 $DGS END_BLK, ??eb03_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 80 80 $DGS AUX_END, 038H + 81 81 $DGS BEG_BLK, ??bb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 82 82 $DGS AUX_BEG, 03AH, 00H, 045H + 83 83 $DGS END_BLK, ??eb04_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 84 84 $DGS AUX_END, 03CH + 85 85 $DGS BEG_BLK, ??bb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 86 86 $DGS AUX_BEG, 041H, 00H, 049H + 87 87 $DGS END_BLK, ??eb05_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_END, 044H + 89 89 $DGS BEG_BLK, ??bb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_BEG, 049H, 00H, 04DH + 91 91 $DGS END_BLK, ??eb06_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_END, 055H + 93 93 $DGS BEG_BLK, ??bb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_BEG, 0D1H, 00H, 051H + 95 95 $DGS END_BLK, ??eb07_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_END, 0D3H + 97 97 $DGS BEG_BLK, ??bb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_BEG, 0D9H, 00H, 00H + 99 99 $DGS END_BLK, ??eb08_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_END, 0E3H + 101 101 $DGS END_BLK, ??eb00_vreg_ctr_write, U, U, 00H, 064H, 01H, 00H + 102 102 $DGS AUX_END, 0E4H + 103 103 $DGS END_FUN, ??ef_vreg_ctr_write, U, U, 00H, 065H, 01H, 00H + 104 104 $DGS AUX_END, 0E6H + 105 105 $DGS GLV_SYM, _vreg_ctr_read, U, U, 0CH, 026H, 01H, 02H + 106 106 $DGS AUX_FUN, 00H, U, U, 07DH, 00H, 00H + 107 107 $DGS BEG_FUN, ??bf_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H + 108 108 $DGS AUX_BEG, 0131H, 02H, 05FH + 109 109 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 110 110 $DGS STA_SYM, _rsub_temp, ?L0073, U, 0DH, 03H, 00H, 00H + 111 111 $DGS BEG_BLK, ??bb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 112 112 $DGS AUX_BEG, 06H, 00H, 063H + 113 113 $DGS END_BLK, ??eb00_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 114 114 $DGS AUX_END, 08H + 115 115 $DGS BEG_BLK, ??bb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 116 116 $DGS AUX_BEG, 0AH, 00H, 067H + 117 117 $DGS END_BLK, ??eb01_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 118 118 $DGS AUX_END, 0CH + 119 119 $DGS BEG_BLK, ??bb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 120 120 $DGS AUX_BEG, 0EH, 00H, 06BH + 121 121 $DGS END_BLK, ??eb02_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 122 122 $DGS AUX_END, 010H + 123 123 $DGS BEG_BLK, ??bb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 124 124 $DGS AUX_BEG, 012H, 00H, 06FH + 125 125 $DGS END_BLK, ??eb03_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 126 126 $DGS AUX_END, 015H + 127 127 $DGS BEG_BLK, ??bb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 128 128 $DGS AUX_BEG, 017H, 00H, 073H + 129 129 $DGS END_BLK, ??eb04_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 130 130 $DGS AUX_END, 019H + 131 131 $DGS BEG_BLK, ??bb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 132 132 $DGS AUX_BEG, 01BH, 00H, 077H + 133 133 $DGS END_BLK, ??eb05_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 134 134 $DGS AUX_END, 01FH + 135 135 $DGS BEG_BLK, ??bb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 136 136 $DGS AUX_BEG, 023H, 00H, 00H + 137 137 $DGS END_BLK, ??eb06_vreg_ctr_read, U, U, 00H, 064H, 01H, 00H + 138 138 $DGS AUX_END, 027H + 139 139 $DGS END_FUN, ??ef_vreg_ctr_read, U, U, 00H, 065H, 01H, 00H + 140 140 $DGS AUX_END, 02AH + 141 141 $DGS GLV_SYM, _vreg_ctr_after_read, U, U, 01H, 026H, 01H, 02H + 142 142 $DGS AUX_FUN, 00H, U, U, 088H, 00H, 00H + 143 143 $DGS BEG_FUN, ??bf_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H + 144 144 $DGS AUX_BEG, 0161H, 02H, 082H + 145 145 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 146 146 $DGS BEG_BLK, ??bb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H + 147 147 $DGS AUX_BEG, 05H, 00H, 00H + 148 148 $DGS END_BLK, ??eb00_vreg_ctr_after_read, U, U, 00H, 064H, 01H, 00H + 149 149 $DGS AUX_END, 011H + 150 150 $DGS END_FUN, ??ef_vreg_ctr_after_read, U, U, 00H, 065H, 01H, 00H + 151 151 $DGS AUX_END, 012H + 152 152 $DGS GLV_SYM, _set_irq, U, U, 01H, 026H, 01H, 02H + 153 153 $DGS AUX_FUN, 00H, U, U, 0A1H, 00H, 00H + 154 154 $DGS BEG_FUN, ??bf_set_irq, U, U, 00H, 065H, 01H, 00H + 155 155 $DGS AUX_BEG, 018AH, 04H, 08FH + 156 156 $DGS FUN_ARG, _irqreg, 02H, 0FFFFH, 0CH, 09H, 00H, 00H + 157 157 $DGS FUN_ARG, _irq_flg, 0AH, 0FFFFH, 0CH, 09H, 00H, 00H + 158 158 $DGS AUT_VAR, _tot, 01H, 0FFFFH, 0CH, 01H, 00H, 00H + 159 159 $DGS BEG_BLK, ??bb00_set_irq, U, U, 00H, 064H, 01H, 00H + 160 160 $DGS AUX_BEG, 05H, 00H, 091H + 161 161 $DGS BEG_BLK, ??bb01_set_irq, U, U, 00H, 064H, 01H, 00H + 162 162 $DGS AUX_BEG, 07H, 00H, 095H + 163 163 $DGS END_BLK, ??eb01_set_irq, U, U, 00H, 064H, 01H, 00H + 164 164 $DGS AUX_END, 07H + 165 165 $DGS BEG_BLK, ??bb02_set_irq, U, U, 00H, 064H, 01H, 00H + 166 166 $DGS AUX_BEG, 0AH, 00H, 099H + 167 167 $DGS END_BLK, ??eb02_set_irq, U, U, 00H, 064H, 01H, 00H + 168 168 $DGS AUX_END, 0AH + 169 169 $DGS BEG_BLK, ??bb03_set_irq, U, U, 00H, 064H, 01H, 00H + 170 170 $DGS AUX_BEG, 0BH, 00H, 00H + 171 171 $DGS END_BLK, ??eb03_set_irq, U, U, 00H, 064H, 01H, 00H + 172 172 $DGS AUX_END, 0BH + 173 173 $DGS END_BLK, ??eb00_set_irq, U, U, 00H, 064H, 01H, 00H + 174 174 $DGS AUX_END, 0CH + 175 175 $DGS END_FUN, ??ef_set_irq, U, U, 00H, 065H, 01H, 00H + 176 176 $DGS AUX_END, 0EH + 177 177 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 026H, 01H, 03H + 178 178 $DGS AUX_STR, 00H, 00H, 060H, 060H, 00H, 00H, 00H, 00H + 179 179 $DGS GLV_SYM, _irq_readed, U, U, 034CH, 027H, 00H, 00H + 180 180 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 02H, 01H, 03H + 181 181 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 182 182 $DGS GLV_SYM, _set_rtc, U, U, 01H, 02H, 01H, 02H + 183 183 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 184 184 $DGS GLV_SYM, _tski_vcom_set, U, U, 0AH, 02H, 01H, 02H + 185 185 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 186 186 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H + 187 187 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 188 188 $DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 02H, 01H, 02H + 189 189 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 190 190 $DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H + 191 191 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 192 192 $DGS GLV_SYM, _tski_PM_LCD_on, U, U, 0AH, 02H, 01H, 02H + 193 193 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 194 194 $DGS GLV_SYM, _tski_PM_LCD_off, U, U, 0AH, 02H, 01H, 02H + 195 195 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 196 196 $DGS GLV_SYM, _tski_PM_BL_set, U, U, 0AH, 02H, 01H, 02H + 197 197 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 198 198 $DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 02H, 00H, 00H + 199 199 $DGS GLV_SYM, _acc_hosu_set, U, U, 0AH, 02H, 01H, 02H + 200 200 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 201 201 $DGS GLV_SYM, _acc_read, U, U, 0AH, 02H, 01H, 02H + 202 202 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 203 203 $DGS GLV_SYM, _acc_write, U, U, 0AH, 02H, 01H, 02H + 204 204 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 205 205 $DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 02H, 01H, 02H + 206 206 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 207 207 $DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 02H, 01H, 02H + 208 208 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 209 209 $DGS GLV_SYM, _hosu_read, U, U, 0CH, 02H, 01H, 02H + 210 210 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 211 211 $DGS GLV_SYM, _tski_mcu_info_read, U, U, 0AH, 02H, 01H, 02H + 212 212 $DGS AUX_FUN, 013H, U, U, 00H, 00H, 00H + 213 213 + 214 214 EXTRN _vreg_twl + 215 215 EXTRN _set_rtc + 216 216 EXTRN _tski_vcom_set + 217 217 EXTRN _renge_task_immed_add + 218 218 EXTRN _tski_firm_update + 219 219 EXTRN _do_command0 + 220 220 EXTRN _tski_PM_LCD_on + 221 221 EXTRN _tski_PM_LCD_off + 222 222 EXTRN _tski_PM_BL_set + 223 223 EXTRN _acc_hosu_set + 224 224 EXTRN _acc_read + 225 225 EXTRN _acc_write + 226 226 EXTRN _clear_hosu_hist + 227 227 EXTRN _rtc_buf_reflesh + 228 228 EXTRN _hosu_read + 229 229 EXTRN _tski_mcu_info_read + 230 230 EXTBIT _rtc_alarm_dirty + 231 231 PUBLIC _vreg_ctr + 232 232 PUBLIC _irq_readed + 233 233 PUBLIC _vreg_ctr_init + 234 234 PUBLIC _vreg_ctr_write + 235 235 PUBLIC _vreg_ctr_read + 236 236 PUBLIC _vreg_ctr_after_read + 237 237 PUBLIC _set_irq + 238 238 + 239 239 ----- @@BITS BSEG + 240 240 00000.0 _irq_readed DBIT + 241 241 + 242 242 ----- @@CNST CSEG MIRRORP + 243 243 00000 01 _lpf_coeff: DB 01H ; 1 + 244 244 00001 02 DB 02H ; 2 + 245 245 00002 02 DB 02H ; 2 + 246 246 00003 03 DB 03H ; 3 + 247 247 00004 03 DB 03H ; 3 + 248 248 00005 02 DB 02H ; 2 + 249 249 00006 00 DB 00H ; 0 + 250 250 00007 FE DB 0FEH ; 254 + 251 251 00008 FB DB 0FBH ; 251 + 252 252 00009 F7 DB 0F7H ; 247 + 253 253 0000A F3 DB 0F3H ; 243 + 254 254 0000B F0 DB 0F0H ; 240 + 255 255 0000C F0 DB 0F0H ; 240 + 256 256 0000D F3 DB 0F3H ; 243 + 257 257 0000E FA DB 0FAH ; 250 + 258 258 0000F 04 DB 04H ; 4 + 259 259 00010 12 DB 012H ; 18 + 260 260 00011 25 DB 025H ; 37 + 261 261 00012 38 DB 038H ; 56 + 262 262 00013 4D DB 04DH ; 77 + 263 263 00014 5F DB 05FH ; 95 + 264 264 00015 6E DB 06EH ; 110 + 265 265 00016 77 DB 077H ; 119 + 266 266 00017 7A DB 07AH ; 122 + 267 267 00018 77 DB 077H ; 119 + 268 268 00019 6E DB 06EH ; 110 + 269 269 0001A 5F DB 05FH ; 95 + 270 270 0001B 4D DB 04DH ; 77 + 271 271 0001C 38 DB 038H ; 56 + 272 272 0001D 25 DB 025H ; 37 + 273 273 0001E 12 DB 012H ; 18 + 274 274 0001F 04 DB 04H ; 4 + 275 275 00020 FA DB 0FAH ; 250 + 276 276 00021 F3 DB 0F3H ; 243 + 277 277 00022 F0 DB 0F0H ; 240 + 278 278 00023 F0 DB 0F0H ; 240 + 279 279 00024 F3 DB 0F3H ; 243 + 280 280 00025 F7 DB 0F7H ; 247 + 281 281 00026 FB DB 0FBH ; 251 + 282 282 00027 FE DB 0FEH ; 254 + 283 283 00028 00 DB 00H ; 0 + 284 284 00029 02 DB 02H ; 2 + 285 285 0002A 03 DB 03H ; 3 + 286 286 0002B 03 DB 03H ; 3 + 287 287 0002C 02 DB 02H ; 2 + 288 288 0002D 02 DB 02H ; 2 + 289 289 0002E 01 DB 01H ; 1 + 290 290 0002F 00 DB (1) + 291 291 + 292 292 ----- @@R_INIT CSEG UNIT64KP + 293 293 + 294 294 ----- @@INIT DSEG BASEP + 295 295 + 296 296 ----- @@DATA DSEG BASEP + 297 297 00000 _vreg_ctr: DS (96) + 298 298 00060 ?L0073: DS (2) + 299 299 + 300 300 ----- @@R_INIS CSEG UNIT64KP + 301 301 + 302 302 ----- @@INIS DSEG SADDRP + 303 303 + 304 304 ----- @@DATS DSEG SADDRP + 305 305 + 306 306 ----- @@CNSTL CSEG PAGE64KP + 307 307 + 308 308 ----- @@RLINIT CSEG UNIT64KP + 309 309 + 310 310 ----- @@INITL DSEG UNIT64KP + 311 311 + 312 312 ----- @@DATAL DSEG UNIT64KP + 313 313 + 314 314 ----- @@CALT CSEG CALLT0 + 315 315 + 316 316 ; Sub-Routines created by CC78K0R + 317 317 + 318 318 ----- ROM_CODE CSEG BASE + 319 319 00000 bs_S0105: + 320 320 00000 66 mov a,l ;[INF] 1, 1 + 321 321 00001 73 mov b,a ;[INF] 1, 1 + 322 322 00002 67 mov a,h ;[INF] 1, 1 + 323 323 00003 R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 + 324 324 00006 D7 ret ;[INF] 1, 6 + 325 325 00007 es_S0105: + 326 326 + 327 327 ----- ROM_CODE CSEG BASE + 328 328 00007 bs_S0106: + 329 329 00007 R340100 movw de,#loww (_vreg_twl+1) ;[INF] 3, 1 + 330 330 0000A 89 mov a,[de] ;[INF] 1, 1 + 331 331 0000B 6168 or a,x ;[INF] 2, 1 + 332 332 0000D 99 mov [de],a ;[INF] 1, 1 + 333 333 0000E D7 ret ;[INF] 1, 6 + 334 334 0000F es_S0106: + 335 335 + 336 336 ----- ROM_CODE CSEG BASE + 337 337 0000F bs_S0104: + 338 338 0000F 72 mov c,a ;[INF] 1, 1 + 339 339 00010 66 mov a,l ;[INF] 1, 1 + 340 340 00011 73 mov b,a ;[INF] 1, 1 + 341 341 00012 62 mov a,c ;[INF] 1, 1 + 342 342 00013 R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 + 343 343 00016 D7 ret ;[INF] 1, 6 + 344 344 00017 es_S0104: + 345 345 + 346 346 ----- ROM_CODE CSEG BASE + 347 347 00017 bs_F0102: + 348 348 00017 318E shrw ax,8 ;[INF] 2, 1 + 349 349 00019 C1 push ax ;[INF] 1, 1 + 350 350 0001A 17 movw ax,hl ;[INF] 1, 1 + 351 351 0001B F1 clrb a ;[INF] 1, 1 + 352 352 0001C 243000 subw ax,#030H ; 48 ;[INF] 3, 1 + 353 353 0001F RFD0000 call !_set_rtc ;[INF] 3, 3 + 354 354 00022 C0 pop ax ;[INF] 1, 1 + 355 355 00023 D7 ret ;[INF] 1, 6 + 356 356 00024 es_F0102: + 357 357 + 358 358 ----- ROM_CODE CSEG BASE + 359 359 00024 bs_S0103: + 360 360 00024 67 mov a,h ;[INF] 1, 1 + 361 361 00025 5C3F and a,#03FH ; 63 ;[INF] 2, 1 + 362 362 00027 72 mov c,a ;[INF] 1, 1 + 363 363 00028 66 mov a,l ;[INF] 1, 1 + 364 364 00029 73 mov b,a ;[INF] 1, 1 + 365 365 0002A 62 mov a,c ;[INF] 1, 1 + 366 366 0002B R180000 mov _vreg_ctr[b],a ;[INF] 3, 1 + 367 367 0002E D7 ret ;[INF] 1, 6 + 368 368 0002F es_S0103: + 369 369 + 370 370 ----- ROM_CODE CSEG BASE + 371 371 0002F bs_F0101: + 372 372 0002F 5C3F and a,#03FH ; 63 ;[INF] 2, 1 + 373 373 00031 318E shrw ax,8 ;[INF] 2, 1 + 374 374 00033 C1 push ax ;[INF] 1, 1 + 375 375 00034 17 movw ax,hl ;[INF] 1, 1 + 376 376 00035 F1 clrb a ;[INF] 1, 1 + 377 377 00036 243000 subw ax,#030H ; 48 ;[INF] 3, 1 + 378 378 00039 RFD0000 call !_set_rtc ;[INF] 3, 3 + 379 379 0003C C0 pop ax ;[INF] 1, 1 + 380 380 0003D D7 ret ;[INF] 1, 6 + 381 381 0003E es_F0101: + 382 382 + 383 383 ; *** Sub-Routine Information *** + 384 384 ; + 385 385 ; $SUB bs_F0101 + 386 386 ; CODE SIZE= 15 bytes + 387 387 ; + 388 388 ; $SUB bs_F0102 + 389 389 ; CODE SIZE= 13 bytes + 390 390 ; + 391 391 ; $SUB bs_S0103 + 392 392 ; CODE SIZE= 11 bytes + 393 393 ; + 394 394 ; $SUB bs_S0104 + 395 395 ; CODE SIZE= 8 bytes + 396 396 ; + 397 397 ; $SUB bs_S0105 + 398 398 ; CODE SIZE= 7 bytes + 399 399 ; + 400 400 ; $SUB bs_S0106 + 401 401 ; CODE SIZE= 8 bytes + 402 402 + 403 403 ; End of Sub-Routines + 404 404 + 405 405 ; line 1 : /* ======================================================== + 406 406 ; line 2 : + 407 407 ; line 3 : CTR MCU I2Cレジスタ + 408 408 ; line 4 : + 409 409 ; line 5 : ====================================================== */ + 410 410 ; line 6 : #include "incs.h" + 411 411 ; line 7 : #include "vreg_ctr.h" + 412 412 ; line 8 : #include "rtc.h" + 413 413 ; line 9 : #include "led.h" + 414 414 ; line 10 : #include "accero.h" + 415 415 ; line 11 : #include "pm.h" + 416 416 ; line 12 : + 417 417 ; line 13 : #include + 418 418 ; line 14 : #include "fsl_user.h" + 419 419 ; line 15 : + 420 420 ; line 16 : extern u8 mcu_info_read(); // task_misc.c + 421 421 ; line 17 : + 422 422 ; line 18 : + 423 423 ; line 19 : + 424 424 ; line 20 : // ******************************************************** + 425 425 ; line 21 : u8 vreg_ctr[VREG_C_ENDMARK_]; + 426 426 ; line 22 : + 427 427 ; line 23 : bit irq_readed; // AAA型のため。 + 428 428 ; line 24 : + 429 429 ; line 25 : extern bit update; + 430 430 ; line 26 : extern u16 pool[]; + 431 431 ; line 27 : + 432 432 ; line 28 : + 433 433 ; line 29 : // ******************************************************** + 434 434 ; line 30 : extern task_status_immed tski_firm_update(); + 435 435 ; line 31 : extern task_status_immed tski_mcu_info_read(); + 436 436 ; line 32 : + 437 437 ; line 33 : // ******************************************************** + 438 438 ; line 34 : #ifdef _MCU_BSR_ + 439 439 ; line 35 : #define IICAMK IICAMK1 + 440 440 ; line 36 : #endif + 441 441 ; line 37 : + 442 442 ; line 38 : + 443 443 ; line 39 : // ******************************************************** + 444 444 ; line 40 : // 非ゼロの初期値の指定が必要なアドレス + 445 445 ; line 41 : void vreg_ctr_init( ) + 446 446 ; line 42 : { + 447 447 + 448 448 ----- ROM_CODE CSEG BASE + 449 449 0003E _vreg_ctr_init: + 450 450 $DGL 1,39 + 451 451 0003E ??bf_vreg_ctr_init: + 452 452 ; line 43 : vreg_ctr[VREG_C_LED_BRIGHT] = 0xFF; + 453 453 $DGL 0,2 + 454 454 0003E RCF2800FF mov !_vreg_ctr+40,#0FFH ; 255 ;[INF] 4, 1 + 455 455 ; line 44 : + 456 456 ; line 45 : #ifdef _PMIC_TWL_ + 457 457 ; line 46 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR; + 458 458 ; line 47 : #else + 459 459 ; line 48 : vreg_ctr[VREG_C_MCU_VER_MAJOR] = MCU_VER_MAJOR | 0x10; + 460 460 $DGL 0,7 + 461 461 00042 RCF000010 mov !_vreg_ctr,#010H ; 16 ;[INF] 4, 1 + 462 462 ; line 49 : #endif + 463 463 ; line 50 : vreg_ctr[VREG_C_MCU_VER_MINOR] = MCU_VER_MINOR; + 464 464 $DGL 0,9 + 465 465 00046 RCF010010 mov !_vreg_ctr+1,#010H ; 16 ;[INF] 4, 1 + 466 466 ; line 51 : + 467 467 ; line 52 : vreg_ctr[VREG_C_VCOM_T] = VCOM_DEFAULT_T; + 468 468 $DGL 0,11 + 469 469 0004A RCF03005C mov !_vreg_ctr+3,#05CH ; 92 ;[INF] 4, 1 + 470 470 ; line 53 : vreg_ctr[VREG_C_VCOM_B] = VCOM_DEFAULT_B; + 471 471 $DGL 0,12 + 472 472 0004E RCF04005F mov !_vreg_ctr+4,#05FH ; 95 ;[INF] 4, 1 + 473 473 ; line 54 : } + 474 474 $DGL 0,13 + 475 475 00052 ??ef_vreg_ctr_init: + 476 476 00052 D7 ret ;[INF] 1, 6 + 477 477 00053 ??ee_vreg_ctr_init: + 478 478 ; line 55 : + 479 479 ; line 56 : + 480 480 ; line 57 : + 481 481 ; line 58 : + 482 482 ; line 59 : // ******************************************************** + 483 483 ; line 60 : // I2C仮想レジスタに書きます。 + 484 484 ; line 61 : //　引数 adrs は内部アドレス + 485 485 ; line 62 : // 　書けないアドレスにアクセスした場合、何もしません。 + 486 486 ; line 63 : // ●書き込んだ結果、I2C_mcu通信が発生する場合、renge_task_immed + 487 487 ; _add() + 488 488 ; line 64 : // を使用しないと、I2C_mcu使用中でエラー終了した場合にリトライし + 489 489 ; ません。 + 490 490 ; line 65 : void vreg_ctr_write( u8 adrs, u8 data ) + 491 491 ; line 66 : { + 492 492 00053 _vreg_ctr_write: + 493 493 $DGL 1,45 + 494 494 00053 C7 push hl ;[INF] 1, 1 + 495 495 00054 8806 mov a,[sp+6] ;[INF] 2, 1 + 496 496 00056 16 movw hl,ax ;[INF] 1, 1 + 497 497 00057 ??bf_vreg_ctr_write: + 498 498 ; line 67 : if( adrs >= VREG_C_ENDMARK_ ) + 499 499 $DGL 0,2 + 500 500 00057 66 mov a,l ;[INF] 1, 1 + 501 501 00058 4C60 cmp a,#060H ; 96 ;[INF] 2, 1 + 502 502 0005A 61C8 skc ;[INF] 2, 1 + 503 503 0005C REDE502 br !?L0067 ;[INF] 3, 3 + 504 504 ; line 68 : return; + 505 505 ; line 69 : + 506 506 ; line 70 : switch ( adrs ) + 507 507 $DGL 0,5 + 508 508 0005F 17 movw ax,hl ;[INF] 1, 1 + 509 509 00060 F1 clrb a ;[INF] 1, 1 + 510 510 00061 E7 onew bc ;[INF] 1, 1 + 511 511 00062 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 512 512 00065 25 subw ax,de ;[INF] 1, 1 + 513 513 00066 61F8 sknz ;[INF] 2, 1 + 514 514 00068 RED4001 br !?L0008 ;[INF] 3, 3 + 515 515 0006B B1 decw ax ;[INF] 1, 1 + 516 516 0006C 23 subw ax,bc ;[INF] 1, 1 + 517 517 0006D 61E3 skh ;[INF] 2, 1 + 518 518 0006F RED4D01 br !?L0009 ;[INF] 3, 3 + 519 519 00072 B1 decw ax ;[INF] 1, 1 + 520 520 00073 23 subw ax,bc ;[INF] 1, 1 + 521 521 00074 61E3 skh ;[INF] 2, 1 + 522 522 00076 RED5901 br !?L0010 ;[INF] 3, 3 + 523 523 00079 23 subw ax,bc ;[INF] 1, 1 + 524 524 0007A 61F8 sknz ;[INF] 2, 1 + 525 525 0007C RED5F01 br !?L0011 ;[INF] 3, 3 + 526 526 0007F 241100 subw ax,#011H ; 17 ;[INF] 3, 1 + 527 527 00082 240500 subw ax,#05H ; 5 ;[INF] 3, 1 + 528 528 00085 61D8 sknc ;[INF] 2, 1 + 529 529 00087 RED7E01 br !?L0012 ;[INF] 3, 3 + 530 530 0008A 240300 subw ax,#03H ; 3 ;[INF] 3, 1 + 531 531 0008D 61F8 sknz ;[INF] 2, 1 + 532 532 0008F RED8401 br !?L0013 ;[INF] 3, 3 + 533 533 00092 23 subw ax,bc ;[INF] 1, 1 + 534 534 00093 61F8 sknz ;[INF] 2, 1 + 535 535 00095 REDCA01 br !?L0015 ;[INF] 3, 3 + 536 536 00098 23 subw ax,bc ;[INF] 1, 1 + 537 537 00099 61F8 sknz ;[INF] 2, 1 + 538 538 0009B RED9B01 br !?L0014 ;[INF] 3, 3 + 539 539 0009E 23 subw ax,bc ;[INF] 1, 1 + 540 540 0009F 61F8 sknz ;[INF] 2, 1 + 541 541 000A1 REDD302 br !?L0038 ;[INF] 3, 3 + 542 542 000A4 B1 decw ax ;[INF] 1, 1 + 543 543 000A5 240400 subw ax,#04H ; 4 ;[INF] 3, 1 + 544 544 000A8 61D8 sknc ;[INF] 2, 1 + 545 545 000AA RED2802 br !?L0016 ;[INF] 3, 3 + 546 546 000AD 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 547 547 000B0 61F8 sknz ;[INF] 2, 1 + 548 548 000B2 RED3402 br !?L0018 ;[INF] 3, 3 + 549 549 000B5 B1 decw ax ;[INF] 1, 1 + 550 550 000B6 240500 subw ax,#05H ; 5 ;[INF] 3, 1 + 551 551 000B9 61D8 sknc ;[INF] 2, 1 + 552 552 000BB RED3A02 br !?L0019 ;[INF] 3, 3 + 553 553 000BE 25 subw ax,de ;[INF] 1, 1 + 554 554 000BF 23 subw ax,bc ;[INF] 1, 1 + 555 555 000C0 61E3 skh ;[INF] 2, 1 + 556 556 000C2 RED4302 br !?L0020 ;[INF] 3, 3 + 557 557 000C5 23 subw ax,bc ;[INF] 1, 1 + 558 558 000C6 61F8 sknz ;[INF] 2, 1 + 559 559 000C8 RED4C02 br !?L0021 ;[INF] 3, 3 + 560 560 000CB 23 subw ax,bc ;[INF] 1, 1 + 561 561 000CC 61F8 sknz ;[INF] 2, 1 + 562 562 000CE RED5302 br !?L0022 ;[INF] 3, 3 + 563 563 000D1 23 subw ax,bc ;[INF] 1, 1 + 564 564 000D2 61F8 sknz ;[INF] 2, 1 + 565 565 000D4 RED5C02 br !?L0023 ;[INF] 3, 3 + 566 566 000D7 23 subw ax,bc ;[INF] 1, 1 + 567 567 000D8 61F8 sknz ;[INF] 2, 1 + 568 568 000DA RED6302 br !?L0024 ;[INF] 3, 3 + 569 569 000DD 23 subw ax,bc ;[INF] 1, 1 + 570 570 000DE 61F8 sknz ;[INF] 2, 1 + 571 571 000E0 RED6B02 br !?L0025 ;[INF] 3, 3 + 572 572 000E3 23 subw ax,bc ;[INF] 1, 1 + 573 573 000E4 61F8 sknz ;[INF] 2, 1 + 574 574 000E6 RED7102 br !?L0026 ;[INF] 3, 3 + 575 575 000E9 23 subw ax,bc ;[INF] 1, 1 + 576 576 000EA 61F8 sknz ;[INF] 2, 1 + 577 577 000EC RED7802 br !?L0027 ;[INF] 3, 3 + 578 578 000EF 23 subw ax,bc ;[INF] 1, 1 + 579 579 000F0 61F8 sknz ;[INF] 2, 1 + 580 580 000F2 RED8302 br !?L0028 ;[INF] 3, 3 + 581 581 000F5 23 subw ax,bc ;[INF] 1, 1 + 582 582 000F6 61F8 sknz ;[INF] 2, 1 + 583 583 000F8 RED8B02 br !?L0029 ;[INF] 3, 3 + 584 584 000FB 23 subw ax,bc ;[INF] 1, 1 + 585 585 000FC 61F8 sknz ;[INF] 2, 1 + 586 586 000FE RED9002 br !?L0030 ;[INF] 3, 3 + 587 587 00101 23 subw ax,bc ;[INF] 1, 1 + 588 588 00102 61F8 sknz ;[INF] 2, 1 + 589 589 00104 RED9802 br !?L0031 ;[INF] 3, 3 + 590 590 00107 240400 subw ax,#04H ; 4 ;[INF] 3, 1 + 591 591 0010A 61F8 sknz ;[INF] 2, 1 + 592 592 0010C RED9D02 br !?L0032 ;[INF] 3, 3 + 593 593 0010F 23 subw ax,bc ;[INF] 1, 1 + 594 594 00110 61F8 sknz ;[INF] 2, 1 + 595 595 00112 REDA802 br !?L0033 ;[INF] 3, 3 + 596 596 00115 25 subw ax,de ;[INF] 1, 1 + 597 597 00116 61F8 sknz ;[INF] 2, 1 + 598 598 00118 REDB302 br !?L0034 ;[INF] 3, 3 + 599 599 0011B 23 subw ax,bc ;[INF] 1, 1 + 600 600 0011C 61F8 sknz ;[INF] 2, 1 + 601 601 0011E REDB802 br !?L0035 ;[INF] 3, 3 + 602 602 00121 240700 subw ax,#07H ; 7 ;[INF] 3, 1 + 603 603 00124 240300 subw ax,#03H ; 3 ;[INF] 3, 1 + 604 604 00127 61D8 sknc ;[INF] 2, 1 + 605 605 00129 REDC302 br !?L0036 ;[INF] 3, 3 + 606 606 0012C 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 607 607 0012F 61F8 sknz ;[INF] 2, 1 + 608 608 00131 REDC802 br !?L0037 ;[INF] 3, 3 + 609 609 00134 25 subw ax,de ;[INF] 1, 1 + 610 610 00135 241000 subw ax,#010H ; 16 ;[INF] 3, 1 + 611 611 00138 61D8 sknc ;[INF] 2, 1 + 612 612 0013A RED2E02 br !?L0017 ;[INF] 3, 3 + 613 613 0013D REDE502 br !?L0067 ;[INF] 3, 3 + 614 614 ; line 71 : { + 615 615 00140 ??bb00_vreg_ctr_write: + 616 616 ; line 72 : + 617 617 ; line 73 : case ( VREG_C_MCU_STATUS ): + 618 618 00140 ?L0008: + 619 619 ; line 74 : vreg_ctr[adrs] = data; + 620 620 $DGL 0,9 + 621 621 00140 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 622 622 ; line 75 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( ( data & 0xC0 ) >> + 623 623 ; 6 ); + 624 624 $DGL 0,10 + 625 625 00143 5CC0 and a,#0C0H ; 192 ;[INF] 2, 1 + 626 626 00145 316A shr a,6 ;[INF] 2, 1 + 627 627 00147 R9F0300 mov !_vreg_twl+3,a ;[INF] 3, 1 + 628 628 ; line 76 : break; + 629 629 $DGL 0,11 + 630 630 0014A REDE502 br !?L0067 ;[INF] 3, 3 + 631 631 ; line 77 : + 632 632 ; line 78 : case ( VREG_C_VCOM_T ): + 633 633 0014D ?L0009: + 634 634 ; line 79 : case ( VREG_C_VCOM_B ): + 635 635 ; line 80 : renge_task_immed_add( tski_vcom_set ); + 636 636 $DGL 0,15 + 637 637 0014D R300000 movw ax,#loww (_tski_vcom_set) ;[INF] 3, 1 + 638 638 00150 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 639 639 ; line 81 : vreg_ctr[adrs] = data; + 640 640 $DGL 0,16 + 641 641 00153 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 642 642 ; line 82 : break; + 643 643 $DGL 0,17 + 644 644 00156 REDE502 br !?L0067 ;[INF] 3, 3 + 645 645 ; line 83 : + 646 646 ; line 84 : case ( VREG_C_DBG1 ): + 647 647 00159 ?L0010: + 648 648 ; line 85 : case ( VREG_C_DBG2 ): + 649 649 ; line 86 : vreg_ctr[adrs] = data; + 650 650 $DGL 0,21 + 651 651 00159 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 652 652 ; line 87 : break; + 653 653 $DGL 0,22 + 654 654 0015C REDE502 br !?L0067 ;[INF] 3, 3 + 655 655 ; line 88 : case ( VREG_C_DBG3 ): + 656 656 0015F ?L0011: + 657 657 ; line 89 : vreg_ctr[adrs] = data; + 658 658 $DGL 0,24 + 659 659 0015F RFD0000 call !bs_S0105 ;[INF] 3, 3 + 660 660 ; line 90 : if( ( vreg_ctr[VREG_C_DBG1] == 'j' ) + 661 661 ; line 91 : && ( vreg_ctr[VREG_C_DBG2] == 'h' ) + 662 662 ; line 92 : && ( data == 'l' ) ) + 663 663 $DGL 0,27 + 664 664 00162 R4005006A cmp !_vreg_ctr+5,#06AH ; 106 ;[INF] 4, 1 + 665 665 00166 DF13 bnz $?L0041 ;[INF] 2, 4 + 666 666 00168 R40060068 cmp !_vreg_ctr+6,#068H ; 104 ;[INF] 4, 1 + 667 667 0016C DF0D bnz $?L0041 ;[INF] 2, 4 + 668 668 0016E 4C6C cmp a,#06CH ; 108 ;[INF] 2, 1 + 669 669 00170 DF09 bnz $?L0041 ;[INF] 2, 4 + 670 670 ; line 93 : { + 671 671 00172 ??bb01_vreg_ctr_write: + 672 672 ; line 94 : renge_task_immed_add( tski_firm_update ); + 673 673 $DGL 0,29 + 674 674 00172 R300000 movw ax,#loww (_tski_firm_update) ;[INF] 3, 1 + 675 675 00175 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 676 676 ; line 95 : IICAMK = 1; + 677 677 $DGL 0,30 + 678 678 00178 713AD5 set1 MK2H.3 ;[INF] 3, 2 + 679 679 0017B ??eb01_vreg_ctr_write: + 680 680 ; line 96 : } + 681 681 0017B ?L0041: + 682 682 ; line 97 : break; + 683 683 $DGL 0,32 + 684 684 0017B REDE502 br !?L0067 ;[INF] 3, 3 + 685 685 ; line 98 : + 686 686 ; line 99 : case ( VREG_C_IRQ_MASK0 ): + 687 687 0017E ?L0012: + 688 688 ; line 100 : case ( VREG_C_IRQ_MASK1 ): + 689 689 ; line 101 : case ( VREG_C_IRQ_MASK2 ): + 690 690 ; line 102 : case ( VREG_C_IRQ_MASK3 ): + 691 691 ; line 103 : case ( VREG_C_IRQ_MASK4 ): + 692 692 ; line 104 : vreg_ctr[adrs] = data; + 693 693 $DGL 0,39 + 694 694 0017E RFD0000 call !bs_S0105 ;[INF] 3, 3 + 695 695 ; line 105 : break; + 696 696 $DGL 0,40 + 697 697 00181 REDE502 br !?L0067 ;[INF] 3, 3 + 698 698 ; line 106 : + 699 699 ; line 107 : case ( VREG_C_COMMAND0 ): + 700 700 00184 ?L0013: + 701 701 ; line 108 : vreg_ctr[adrs] |= data; + 702 702 $DGL 0,43 + 703 703 00184 17 movw ax,hl ;[INF] 1, 1 + 704 704 00185 F1 clrb a ;[INF] 1, 1 + 705 705 00186 R040000 addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 + 706 706 00189 14 movw de,ax ;[INF] 1, 1 + 707 707 0018A 89 mov a,[de] ;[INF] 1, 1 + 708 708 0018B 616F or a,h ;[INF] 2, 1 + 709 709 0018D 99 mov [de],a ;[INF] 1, 1 + 710 710 ; line 109 : if( data != 0 ) + 711 711 $DGL 0,44 + 712 712 0018E 67 mov a,h ;[INF] 1, 1 + 713 713 0018F D1 cmp0 a ;[INF] 1, 1 + 714 714 00190 DD06 bz $?L0043 ;[INF] 2, 4 + 715 715 ; line 110 : { + 716 716 00192 ??bb02_vreg_ctr_write: + 717 717 ; line 111 : renge_task_immed_add( do_command0 ); + 718 718 $DGL 0,46 + 719 719 00192 R300000 movw ax,#loww (_do_command0) ;[INF] 3, 1 + 720 720 00195 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 721 721 00198 ??eb02_vreg_ctr_write: + 722 722 ; line 112 : } + 723 723 00198 ?L0043: + 724 724 ; line 113 : break; + 725 725 $DGL 0,48 + 726 726 00198 REDE502 br !?L0067 ;[INF] 3, 3 + 727 727 ; line 114 : + 728 728 ; line 115 : case ( VREG_C_COMMAND2 ): + 729 729 0019B ?L0014: + 730 730 ; line 116 : // こちらからの完了割り込みを待ってくれないそうです。 #- + 731 731 ; ω-) 何のための割り込みだ + 732 732 ; line 117 : // 液晶電源 + 733 733 ; line 118 : if(( data & REG_BIT_CMD_LCD_ON ) != 0 ) + 734 734 $DGL 0,53 + 735 735 0019B 67 mov a,h ;[INF] 1, 1 + 736 736 0019C 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 737 737 0019E D1 cmp0 a ;[INF] 1, 1 + 738 738 0019F DD08 bz $?L0045 ;[INF] 2, 4 + 739 739 ; line 119 : { + 740 740 001A1 ??bb03_vreg_ctr_write: + 741 741 ; line 120 : renge_task_immed_add( tski_PM_LCD_on ); + 742 742 $DGL 0,55 + 743 743 001A1 R300000 movw ax,#loww (_tski_PM_LCD_on) ;[INF] 3, 1 + 744 744 001A4 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 745 745 001A7 ??eb03_vreg_ctr_write: + 746 746 ; line 121 : } + 747 747 $DGL 0,56 + 748 748 001A7 EF0C br $?L0047 ;[INF] 2, 3 + 749 749 001A9 ?L0045: + 750 750 ; line 122 : else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 ) + 751 751 $DGL 0,57 + 752 752 001A9 67 mov a,h ;[INF] 1, 1 + 753 753 001AA 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 754 754 001AC D1 cmp0 a ;[INF] 1, 1 + 755 755 001AD DD06 bz $?L0047 ;[INF] 2, 4 + 756 756 ; line 123 : { + 757 757 001AF ??bb04_vreg_ctr_write: + 758 758 ; line 124 : renge_task_immed_add( tski_PM_LCD_off ); + 759 759 $DGL 0,59 + 760 760 001AF R300000 movw ax,#loww (_tski_PM_LCD_off) ;[INF] 3, 1 + 761 761 001B2 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 762 762 001B5 ??eb04_vreg_ctr_write: + 763 763 ; line 125 : } + 764 764 001B5 ?L0047: + 765 765 ; line 126 : + 766 766 ; line 127 : // バックライト設定 + 767 767 ; line 128 : /// 今のところさらに細かくは分けないけど… + 768 768 ; line 129 : if(( data & REG_BITS_CMD_BL ) != 0 ) + 769 769 $DGL 0,64 + 770 770 001B5 67 mov a,h ;[INF] 1, 1 + 771 771 001B6 5C3C and a,#03CH ; 60 ;[INF] 2, 1 + 772 772 001B8 D1 cmp0 a ;[INF] 1, 1 + 773 773 001B9 DD0C bz $?L0049 ;[INF] 2, 4 + 774 774 ; line 130 : { + 775 775 001BB ??bb05_vreg_ctr_write: + 776 776 ; line 131 : vreg_ctr[adrs] = ( data & REG_BITS_CMD_BL ); + 777 777 $DGL 0,66 + 778 778 001BB 67 mov a,h ;[INF] 1, 1 + 779 779 001BC 5C3C and a,#03CH ; 60 ;[INF] 2, 1 + 780 780 001BE RFD0F00 call !bs_S0104 ;[INF] 3, 3 + 781 781 ; line 132 : renge_task_immed_add( tski_PM_BL_set ); + 782 782 $DGL 0,67 + 783 783 001C1 R300000 movw ax,#loww (_tski_PM_BL_set) ;[INF] 3, 1 + 784 784 001C4 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 785 785 001C7 ??eb05_vreg_ctr_write: + 786 786 ; line 133 : } + 787 787 001C7 ?L0049: + 788 788 ; line 134 : break; + 789 789 $DGL 0,69 + 790 790 001C7 REDE502 br !?L0067 ;[INF] 3, 3 + 791 791 ; line 135 : + 792 792 ; line 136 : case ( VREG_C_COMMAND1 ): + 793 793 001CA ?L0015: + 794 794 ; line 137 : if( data != 0 ) + 795 795 $DGL 0,72 + 796 796 001CA 67 mov a,h ;[INF] 1, 1 + 797 797 001CB D1 cmp0 a ;[INF] 1, 1 + 798 798 001CC DD57 bz $?L0051 ;[INF] 2, 4 + 799 799 ; line 138 : { + 800 800 001CE ??bb06_vreg_ctr_write: + 801 801 ; line 139 : // TWLに割り込みを入れる + 802 802 ; line 140 : /// 実際に割り込みを入れるのはSoC + 803 803 ; line 141 : vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT + 804 804 ; _SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; + 805 805 ; //pwsw_det + 806 806 $DGL 0,76 + 807 807 001CE 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 808 808 001D0 D1 cmp0 a ;[INF] 1, 1 + 809 809 001D1 DD05 bz $?L0053 ;[INF] 2, 4 + 810 810 001D3 300800 movw ax,#08H ; 8 ;[INF] 3, 1 + 811 811 001D6 EF01 br $?L0054 ;[INF] 2, 3 + 812 812 001D8 ?L0053: + 813 813 001D8 F6 clrw ax ;[INF] 1, 1 + 814 814 001D9 ?L0054: + 815 815 001D9 60 mov a,x ;[INF] 1, 1 + 816 816 001DA R9F0100 mov !_vreg_twl+1,a ;[INF] 3, 1 + 817 817 ; line 142 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT + 818 818 ; _SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; + 819 819 ; //reset_req + 820 820 $DGL 0,77 + 821 821 001DD 67 mov a,h ;[INF] 1, 1 + 822 822 001DE 5C02 and a,#02H ; 2 ;[INF] 2, 1 + 823 823 001E0 D1 cmp0 a ;[INF] 1, 1 + 824 824 001E1 DD03 bz $?L0055 ;[INF] 2, 4 + 825 825 001E3 E6 onew ax ;[INF] 1, 1 + 826 826 001E4 EF01 br $?L0056 ;[INF] 2, 3 + 827 827 001E6 ?L0055: + 828 828 001E6 F6 clrw ax ;[INF] 1, 1 + 829 829 001E7 ?L0056: + 830 830 001E7 RFD0700 call !bs_S0106 ;[INF] 3, 3 + 831 831 ; line 143 : + 832 832 ; line 144 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT + 833 833 ; _SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //of + 834 834 ; f_req + 835 835 $DGL 0,79 + 836 836 001EA 67 mov a,h ;[INF] 1, 1 + 837 837 001EB 5C04 and a,#04H ; 4 ;[INF] 2, 1 + 838 838 001ED D1 cmp0 a ;[INF] 1, 1 + 839 839 001EE DD04 bz $?L0057 ;[INF] 2, 4 + 840 840 001F0 E6 onew ax ;[INF] 1, 1 + 841 841 001F1 A1 incw ax ;[INF] 1, 1 + 842 842 001F2 EF01 br $?L0058 ;[INF] 2, 3 + 843 843 001F4 ?L0057: + 844 844 001F4 F6 clrw ax ;[INF] 1, 1 + 845 845 001F5 ?L0058: + 846 846 001F5 RFD0700 call !bs_S0106 ;[INF] 3, 3 + 847 847 ; line 145 : + 848 848 ; line 146 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT + 849 849 ; _SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; + 850 850 ; //batt_low + 851 851 $DGL 0,81 + 852 852 001F8 67 mov a,h ;[INF] 1, 1 + 853 853 001F9 5C08 and a,#08H ; 8 ;[INF] 2, 1 + 854 854 001FB D1 cmp0 a ;[INF] 1, 1 + 855 855 001FC DD05 bz $?L0059 ;[INF] 2, 4 + 856 856 001FE 302000 movw ax,#020H ; 32 ;[INF] 3, 1 + 857 857 00201 EF01 br $?L0060 ;[INF] 2, 3 + 858 858 00203 ?L0059: + 859 859 00203 F6 clrw ax ;[INF] 1, 1 + 860 860 00204 ?L0060: + 861 861 00204 RFD0700 call !bs_S0106 ;[INF] 3, 3 + 862 862 ; line 147 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT + 863 863 ; _SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; + 864 864 ; //batt_empty + 865 865 $DGL 0,82 + 866 866 00207 67 mov a,h ;[INF] 1, 1 + 867 867 00208 5C10 and a,#010H ; 16 ;[INF] 2, 1 + 868 868 0020A D1 cmp0 a ;[INF] 1, 1 + 869 869 0020B DD05 bz $?L0061 ;[INF] 2, 4 + 870 870 0020D 301000 movw ax,#010H ; 16 ;[INF] 3, 1 + 871 871 00210 EF01 br $?L0062 ;[INF] 2, 3 + 872 872 00212 ?L0061: + 873 873 00212 F6 clrw ax ;[INF] 1, 1 + 874 874 00213 ?L0062: + 875 875 00213 RFD0700 call !bs_S0106 ;[INF] 3, 3 + 876 876 ; line 148 : + 877 877 ; line 149 : vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT + 878 878 ; _SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00 + 879 879 ; ; //vol_changed + 880 880 $DGL 0,84 + 881 881 00216 67 mov a,h ;[INF] 1, 1 + 882 882 00217 5C20 and a,#020H ; 32 ;[INF] 2, 1 + 883 883 00219 D1 cmp0 a ;[INF] 1, 1 + 884 884 0021A DD05 bz $?L0063 ;[INF] 2, 4 + 885 885 0021C 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 886 886 0021F EF01 br $?L0064 ;[INF] 2, 3 + 887 887 00221 ?L0063: + 888 888 00221 F6 clrw ax ;[INF] 1, 1 + 889 889 00222 ?L0064: + 890 890 00222 RFD0700 call !bs_S0106 ;[INF] 3, 3 + 891 891 00225 ??eb06_vreg_ctr_write: + 892 892 ; line 150 : } + 893 893 00225 ?L0051: + 894 894 ; line 151 : break; + 895 895 $DGL 0,86 + 896 896 00225 REDE502 br !?L0067 ;[INF] 3, 3 + 897 897 ; line 152 : + 898 898 ; line 153 : case ( VREG_C_DBG20 ): + 899 899 00228 ?L0016: + 900 900 ; line 154 : case ( VREG_C_DBG21 ): + 901 901 ; line 155 : case ( VREG_C_DBG22 ): + 902 902 ; line 156 : case ( VREG_C_DBG23 ): + 903 903 ; line 157 : vreg_ctr[adrs] = data; + 904 904 $DGL 0,92 + 905 905 00228 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 906 906 ; line 158 : break; + 907 907 $DGL 0,93 + 908 908 0022B REDE502 br !?L0067 ;[INF] 3, 3 + 909 909 ; line 159 : + 910 910 ; line 160 : case ( VREG_C_FREE_0 ): + 911 911 0022E ?L0017: + 912 912 ; line 161 : case ( VREG_C_FREE_1 ): + 913 913 ; line 162 : case ( VREG_C_FREE_2 ): + 914 914 ; line 163 : case ( VREG_C_FREE_3 ): + 915 915 ; line 164 : case ( VREG_C_FREE_4 ): + 916 916 ; line 165 : case ( VREG_C_FREE_5 ): + 917 917 ; line 166 : case ( VREG_C_FREE_6 ): + 918 918 ; line 167 : case ( VREG_C_FREE_7 ): + 919 919 ; line 168 : case ( VREG_C_FREE_8 ): + 920 920 ; line 169 : case ( VREG_C_FREE_9 ): + 921 921 ; line 170 : case ( VREG_C_FREE_A ): + 922 922 ; line 171 : case ( VREG_C_FREE_B ): + 923 923 ; line 172 : case ( VREG_C_FREE_C ): + 924 924 ; line 173 : case ( VREG_C_FREE_D ): + 925 925 ; line 174 : case ( VREG_C_FREE_E ): + 926 926 ; line 175 : case ( VREG_C_FREE_F ): + 927 927 ; line 176 : vreg_ctr[adrs] = data; + 928 928 $DGL 0,111 + 929 929 0022E RFD0000 call !bs_S0105 ;[INF] 3, 3 + 930 930 ; line 177 : break; + 931 931 $DGL 0,112 + 932 932 00231 REDE502 br !?L0067 ;[INF] 3, 3 + 933 933 ; line 178 : + 934 934 ; line 179 : case ( VREG_C_LED_BRIGHT ): + 935 935 00234 ?L0018: + 936 936 ; line 180 : vreg_ctr[adrs] = data; + 937 937 $DGL 0,115 + 938 938 00234 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 939 939 ; line 181 : break; + 940 940 $DGL 0,116 + 941 941 00237 REDE502 br !?L0067 ;[INF] 3, 3 + 942 942 ; line 182 : + 943 943 ; line 183 : case ( VREG_C_LED_POW ): + 944 944 0023A ?L0019: + 945 945 ; line 184 : case ( VREG_C_LED_WIFI ): + 946 946 ; line 185 : case ( VREG_C_LED_CAM ): + 947 947 ; line 186 : case ( VREG_C_LED_TUNE ): + 948 948 ; line 187 : case ( VREG_C_LED_NOTIFY ): + 949 949 ; line 188 : vreg_ctr[adrs] = data & 0x0F; + 950 950 $DGL 0,123 + 951 951 0023A 67 mov a,h ;[INF] 1, 1 + 952 952 0023B 5C0F and a,#0FH ; 15 ;[INF] 2, 1 + 953 953 0023D RFD0F00 call !bs_S0104 ;[INF] 3, 3 + 954 954 ; line 189 : break; + 955 955 $DGL 0,124 + 956 956 00240 REDE502 br !?L0067 ;[INF] 3, 3 + 957 957 ; line 190 : + 958 958 ; line 191 : /// 非同期で動いているためここでは書かない。 + 959 959 ; line 192 : // 予約するだけでstopで書く + 960 960 ; line 193 : case ( VREG_C_RTC_SEC ): + 961 961 00243 ?L0020: + 962 962 ; line 194 : case ( VREG_C_RTC_MIN ): + 963 963 ; line 195 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F ); + 964 964 $DGL 0,130 + 965 965 00243 67 mov a,h ;[INF] 1, 1 + 966 966 00244 5C7F and a,#07FH ; 127 ;[INF] 2, 1 + 967 967 00246 RFD1700 call !bs_F0102 ;[INF] 3, 3 + 968 968 ; line 196 : break; + 969 969 $DGL 0,131 + 970 970 00249 REDE502 br !?L0067 ;[INF] 3, 3 + 971 971 ; line 197 : + 972 972 ; line 198 : case ( VREG_C_RTC_HOUR ): + 973 973 0024C ?L0021: + 974 974 ; line 199 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); + 975 975 $DGL 0,134 + 976 976 0024C 67 mov a,h ;[INF] 1, 1 + 977 977 0024D RFD2F00 call !bs_F0101 ;[INF] 3, 3 + 978 978 ; line 200 : break; + 979 979 $DGL 0,135 + 980 980 00250 REDE502 br !?L0067 ;[INF] 3, 3 + 981 981 ; line 201 : + 982 982 ; line 202 : case ( VREG_C_RTC_YOBI ): + 983 983 00253 ?L0022: + 984 984 ; line 203 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 ); + 985 985 $DGL 0,138 + 986 986 00253 67 mov a,h ;[INF] 1, 1 + 987 987 00254 5C07 and a,#07H ; 7 ;[INF] 2, 1 + 988 988 00256 RFD1700 call !bs_F0102 ;[INF] 3, 3 + 989 989 ; line 204 : break; + 990 990 $DGL 0,139 + 991 991 00259 REDE502 br !?L0067 ;[INF] 3, 3 + 992 992 ; line 205 : + 993 993 ; line 206 : case ( VREG_C_RTC_DAY ): + 994 994 0025C ?L0023: + 995 995 ; line 207 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F ); + 996 996 $DGL 0,142 + 997 997 0025C 67 mov a,h ;[INF] 1, 1 + 998 998 0025D RFD2F00 call !bs_F0101 ;[INF] 3, 3 + 999 999 ; line 208 : break; + 1000 1000 $DGL 0,143 + 1001 1001 00260 REDE502 br !?L0067 ;[INF] 3, 3 + 1002 1002 ; line 209 : + 1003 1003 ; line 210 : case ( VREG_C_RTC_MONTH ): + 1004 1004 00263 ?L0024: + 1005 1005 ; line 211 : set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F ); + 1006 1006 $DGL 0,146 + 1007 1007 00263 67 mov a,h ;[INF] 1, 1 + 1008 1008 00264 5C1F and a,#01FH ; 31 ;[INF] 2, 1 + 1009 1009 00266 RFD1700 call !bs_F0102 ;[INF] 3, 3 + 1010 1010 ; line 212 : break; + 1011 1011 $DGL 0,147 + 1012 1012 00269 EF7A br $?L0067 ;[INF] 2, 3 + 1013 1013 ; line 213 : + 1014 1014 ; line 214 : case ( VREG_C_RTC_YEAR ): + 1015 1015 0026B ?L0025: + 1016 1016 ; line 215 : set_rtc( adrs - VREG_C_RTC_SEC, data ); + 1017 1017 $DGL 0,150 + 1018 1018 0026B 67 mov a,h ;[INF] 1, 1 + 1019 1019 0026C RFD1700 call !bs_F0102 ;[INF] 3, 3 + 1020 1020 ; line 216 : break; + 1021 1021 $DGL 0,151 + 1022 1022 0026F EF74 br $?L0067 ;[INF] 2, 3 + 1023 1023 ; line 217 : + 1024 1024 ; line 218 : case ( VREG_C_RTC_COMP ): + 1025 1025 00271 ?L0026: + 1026 1026 ; line 219 : vreg_ctr[adrs] = data; + 1027 1027 $DGL 0,154 + 1028 1028 00271 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1029 1029 ; line 220 : SUBCUD = data; + 1030 1030 $DGL 0,155 + 1031 1031 00274 9E99 mov SUBCUD,a ;[INF] 2, 1 + 1032 1032 ; line 221 : break; + 1033 1033 $DGL 0,156 + 1034 1034 00276 EF6D br $?L0067 ;[INF] 2, 3 + 1035 1035 ; line 222 : + 1036 1036 ; line 223 : case ( VREG_C_RTC_ALARM_MIN ): + 1037 1037 00278 ?L0027: + 1038 1038 ; line 224 : vreg_ctr[adrs] = ( data & 0x7F ); + 1039 1039 $DGL 0,159 + 1040 1040 00278 67 mov a,h ;[INF] 1, 1 + 1041 1041 00279 5C7F and a,#07FH ; 127 ;[INF] 2, 1 + 1042 1042 0027B RFD0F00 call !bs_S0104 ;[INF] 3, 3 + 1043 1043 ; line 225 : rtc_alarm_dirty = 1; + 1044 1044 $DGL 0,160 + 1045 1045 0027E R710200 set1 _rtc_alarm_dirty ;[INF] 3, 2 + 1046 1046 ; line 226 : break; + 1047 1047 $DGL 0,161 + 1048 1048 00281 EF62 br $?L0067 ;[INF] 2, 3 + 1049 1049 ; line 227 : + 1050 1050 ; line 228 : case ( VREG_C_RTC_ALARM_HOUR ): + 1051 1051 00283 ?L0028: + 1052 1052 ; line 229 : vreg_ctr[adrs] = ( data & 0x3F ); + 1053 1053 $DGL 0,164 + 1054 1054 00283 RFD2400 call !bs_S0103 ;[INF] 3, 3 + 1055 1055 ; line 230 : rtc_alarm_dirty = 1; + 1056 1056 $DGL 0,165 + 1057 1057 00286 R710200 set1 _rtc_alarm_dirty ;[INF] 3, 2 + 1058 1058 ; line 231 : break; + 1059 1059 $DGL 0,166 + 1060 1060 00289 EF5A br $?L0067 ;[INF] 2, 3 + 1061 1061 ; line 232 : + 1062 1062 ; line 233 : // 書くだけでよい + 1063 1063 ; line 234 : case ( VREG_C_RTC_ALARM_DAY ): + 1064 1064 0028B ?L0029: + 1065 1065 ; line 235 : vreg_ctr[adrs] = ( data & 0x3F ); + 1066 1066 $DGL 0,170 + 1067 1067 0028B RFD2400 call !bs_S0103 ;[INF] 3, 3 + 1068 1068 ; line 236 : break; + 1069 1069 $DGL 0,171 + 1070 1070 0028E EF55 br $?L0067 ;[INF] 2, 3 + 1071 1071 ; line 237 : + 1072 1072 ; line 238 : case ( VREG_C_RTC_ALARM_MONTH ): + 1073 1073 00290 ?L0030: + 1074 1074 ; line 239 : vreg_ctr[adrs] = ( data & 0x1F ); + 1075 1075 $DGL 0,174 + 1076 1076 00290 67 mov a,h ;[INF] 1, 1 + 1077 1077 00291 5C1F and a,#01FH ; 31 ;[INF] 2, 1 + 1078 1078 00293 RFD0F00 call !bs_S0104 ;[INF] 3, 3 + 1079 1079 ; line 240 : break; + 1080 1080 $DGL 0,175 + 1081 1081 00296 EF4D br $?L0067 ;[INF] 2, 3 + 1082 1082 ; line 241 : + 1083 1083 ; line 242 : case ( VREG_C_RTC_ALARM_YEAR ): + 1084 1084 00298 ?L0031: + 1085 1085 ; line 243 : vreg_ctr[adrs] = data; + 1086 1086 $DGL 0,178 + 1087 1087 00298 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1088 1088 ; line 244 : break; + 1089 1089 $DGL 0,179 + 1090 1090 0029B EF48 br $?L0067 ;[INF] 2, 3 + 1091 1091 ; line 245 : + 1092 1092 ; line 246 : + 1093 1093 ; line 247 : case ( VREG_C_ACC_CONFIG ): + 1094 1094 0029D ?L0032: + 1095 1095 ; line 248 : vreg_ctr[adrs] = data; + 1096 1096 $DGL 0,183 + 1097 1097 0029D RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1098 1098 ; line 249 : renge_task_immed_add( acc_hosu_set ); + 1099 1099 $DGL 0,184 + 1100 1100 002A0 R300000 movw ax,#loww (_acc_hosu_set) ;[INF] 3, 1 + 1101 1101 002A3 RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1102 1102 ; line 250 : break; + 1103 1103 $DGL 0,185 + 1104 1104 002A6 EF3D br $?L0067 ;[INF] 2, 3 + 1105 1105 ; line 251 : + 1106 1106 ; line 252 : case ( VREG_C_ACC_R_ADRS ): + 1107 1107 002A8 ?L0033: + 1108 1108 ; line 253 : vreg_ctr[adrs] = data; + 1109 1109 $DGL 0,188 + 1110 1110 002A8 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1111 1111 ; line 254 : renge_task_immed_add( acc_read ); + 1112 1112 $DGL 0,189 + 1113 1113 002AB R300000 movw ax,#loww (_acc_read) ;[INF] 3, 1 + 1114 1114 002AE RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1115 1115 ; line 255 : break; + 1116 1116 $DGL 0,190 + 1117 1117 002B1 EF32 br $?L0067 ;[INF] 2, 3 + 1118 1118 ; line 256 : + 1119 1119 ; line 257 : case ( VREG_C_ACC_W_ADRS ): + 1120 1120 002B3 ?L0034: + 1121 1121 ; line 258 : vreg_ctr[adrs] = data; + 1122 1122 $DGL 0,193 + 1123 1123 002B3 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1124 1124 ; line 259 : break; + 1125 1125 $DGL 0,194 + 1126 1126 002B6 EF2D br $?L0067 ;[INF] 2, 3 + 1127 1127 ; line 260 : + 1128 1128 ; line 261 : case ( VREG_C_ACC_W_BUF ): + 1129 1129 002B8 ?L0035: + 1130 1130 ; line 262 : vreg_ctr[adrs] = data; + 1131 1131 $DGL 0,197 + 1132 1132 002B8 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1133 1133 ; line 263 : renge_task_immed_add( acc_write ); + 1134 1134 $DGL 0,198 + 1135 1135 002BB R300000 movw ax,#loww (_acc_write) ;[INF] 3, 1 + 1136 1136 002BE RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1137 1137 ; line 264 : break; + 1138 1138 $DGL 0,199 + 1139 1139 002C1 EF22 br $?L0067 ;[INF] 2, 3 + 1140 1140 ; line 265 : + 1141 1141 ; line 266 : case ( VREG_C_ACC_HOSU_L ): + 1142 1142 002C3 ?L0036: + 1143 1143 ; line 267 : case ( VREG_C_ACC_HOSU_M ): + 1144 1144 ; line 268 : case ( VREG_C_ACC_HOSU_H ): + 1145 1145 ; line 269 : vreg_ctr[adrs] = data; + 1146 1146 $DGL 0,204 + 1147 1147 002C3 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1148 1148 ; line 270 : break; + 1149 1149 $DGL 0,205 + 1150 1150 002C6 EF1D br $?L0067 ;[INF] 2, 3 + 1151 1151 ; line 271 : + 1152 1152 ; line 272 : case ( VREG_C_ACC_HOSU_SETTING ): + 1153 1153 002C8 ?L0037: + 1154 1154 ; line 273 : if( ( data & 0x01 ) != 0 ) + 1155 1155 $DGL 0,208 + 1156 1156 002C8 67 mov a,h ;[INF] 1, 1 + 1157 1157 002C9 5C01 and a,#01H ; 1 ;[INF] 2, 1 + 1158 1158 002CB D1 cmp0 a ;[INF] 1, 1 + 1159 1159 002CC DD17 bz $?L0067 ;[INF] 2, 4 + 1160 1160 ; line 274 : { + 1161 1161 002CE ??bb07_vreg_ctr_write: + 1162 1162 ; line 275 : clear_hosu_hist(); // 履歴クリア + 1163 1163 $DGL 0,210 + 1164 1164 002CE RFD0000 call !_clear_hosu_hist ;[INF] 3, 3 + 1165 1165 002D1 ??eb07_vreg_ctr_write: + 1166 1166 ; line 276 : } + 1167 1167 ; line 277 : break; + 1168 1168 $DGL 0,212 + 1169 1169 002D1 EF12 br $?L0067 ;[INF] 2, 3 + 1170 1170 ; line 278 : + 1171 1171 ; line 279 : case ( VREG_C_COMMAND3 ): + 1172 1172 002D3 ?L0038: + 1173 1173 ; line 280 : vreg_ctr[adrs] = data; + 1174 1174 $DGL 0,215 + 1175 1175 002D3 RFD0000 call !bs_S0105 ;[INF] 3, 3 + 1176 1176 ; line 281 : switch ( data ) + 1177 1177 $DGL 0,216 + 1178 1178 002D6 318E shrw ax,8 ;[INF] 2, 1 + 1179 1179 002D8 247200 subw ax,#072H ; 114 ;[INF] 3, 1 + 1180 1180 002DB DD05 bz $?L0068 ;[INF] 2, 4 + 1181 1181 002DD 240500 subw ax,#05H ; 5 ;[INF] 3, 1 + 1182 1182 002E0 61F8 sknz ;[INF] 2, 1 + 1183 1183 ; line 282 : { + 1184 1184 002E2 ??bb08_vreg_ctr_write: + 1185 1185 ; line 283 : case ( 'r' ): + 1186 1186 002E2 ?L0068: + 1187 1187 ; line 284 : // 割り込みルーチンからFSLライブラリを呼ぶのは禁止の + 1188 1188 ; ため + 1189 1189 ; line 285 : // renge_task_immed_add( tski_mcu_reset ); + 1190 1190 ; line 286 : // break; + 1191 1191 ; line 287 : + 1192 1192 ; line 288 : case ( 'w' ): + 1193 1193 ; line 289 : // WDTで再起動（テスト向け） + 1194 1194 ; line 290 : WDTE = 0xAA; + 1195 1195 $DGL 0,225 + 1196 1196 002E2 CEABAA mov WDTE,#0AAH ; 170 ;[INF] 3, 1 + 1197 1197 ; line 291 : break; + 1198 1198 002E5 ??eb08_vreg_ctr_write: + 1199 1199 ; line 292 : } + 1200 1200 002E5 ?L0067: + 1201 1201 002E5 ??eb00_vreg_ctr_write: + 1202 1202 ; line 293 : } + 1203 1203 ; line 294 : return; + 1204 1204 ; line 295 : } + 1205 1205 $DGL 0,230 + 1206 1206 002E5 ??ef_vreg_ctr_write: + 1207 1207 002E5 C6 pop hl ;[INF] 1, 1 + 1208 1208 002E6 D7 ret ;[INF] 1, 6 + 1209 1209 002E7 ??ee_vreg_ctr_write: + 1210 1210 ; line 296 : + 1211 1211 ; line 297 : + 1212 1212 ; line 298 : + 1213 1213 ; line 299 : // ******************************************************** + 1214 1214 ; line 300 : // I2C仮想レジスタから読みます。 + 1215 1215 ; line 301 : // 戻り： xx データ + 1216 1216 ; line 302 : // 注意：次のアドレスの準備で呼ばれる ので、 + 1217 1217 ; line 303 : // リードされたらクリアなどは気をつける + 1218 1218 ; line 304 : u8 vreg_ctr_read( u8 adrs ) + 1219 1219 ; line 305 : { + 1220 1220 002E7 _vreg_ctr_read: + 1221 1221 $DGL 1,89 + 1222 1222 002E7 C7 push hl ;[INF] 1, 1 + 1223 1223 002E8 16 movw hl,ax ;[INF] 1, 1 + 1224 1224 002E9 ??bf_vreg_ctr_read: + 1225 1225 ; line 306 : static u16 rsub_temp; + 1226 1226 ; line 307 : + 1227 1227 ; line 308 : // RTCは読み出し途中に繰り上がるのを避けるため + 1228 1228 ; line 309 : if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR + 1229 1229 ; ) ) + 1230 1230 $DGL 0,5 + 1231 1231 002E9 66 mov a,l ;[INF] 1, 1 + 1232 1232 002EA 4C30 cmp a,#030H ; 48 ;[INF] 2, 1 + 1233 1233 002EC DC09 bc $?L0074 ;[INF] 2, 4 + 1234 1234 002EE 4C37 cmp a,#037H ; 55 ;[INF] 2, 1 + 1235 1235 002F0 DE05 bnc $?L0074 ;[INF] 2, 4 + 1236 1236 ; line 310 : { + 1237 1237 002F2 ??bb00_vreg_ctr_read: + 1238 1238 ; line 311 : rtc_buf_reflesh( ); + 1239 1239 $DGL 0,7 + 1240 1240 002F2 RFD0000 call !_rtc_buf_reflesh ;[INF] 3, 3 + 1241 1241 002F5 ??eb00_vreg_ctr_read: + 1242 1242 ; line 312 : } + 1243 1243 $DGL 0,8 + 1244 1244 002F5 EF51 br $?L0084 ;[INF] 2, 3 + 1245 1245 002F7 ?L0074: + 1246 1246 ; line 313 : else if( adrs == VREG_C_MCU_STATUS ) + 1247 1247 $DGL 0,9 + 1248 1248 002F7 66 mov a,l ;[INF] 1, 1 + 1249 1249 002F8 4C02 cmp a,#02H ; 2 ;[INF] 2, 1 + 1250 1250 002FA DF11 bnz $?L0076 ;[INF] 2, 4 + 1251 1251 ; line 314 : { + 1252 1252 002FC ??bb01_vreg_ctr_read: + 1253 1253 ; line 315 : return( vreg_ctr[ VREG_C_MCU_STATUS ] | ( ( vreg_twl[ RE + 1254 1254 ; G_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) ); + 1255 1255 $DGL 0,11 + 1256 1256 002FC R8F0300 mov a,!_vreg_twl+3 ;[INF] 3, 1 + 1257 1257 002FF 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 1258 1258 00301 318E shrw ax,8 ;[INF] 2, 1 + 1259 1259 00303 316D shlw ax,6 ;[INF] 2, 1 + 1260 1260 00305 08 xch a,x ;[INF] 1, 1 + 1261 1261 00306 R6F0200 or a,!_vreg_ctr+2 ;[INF] 3, 1 + 1262 1262 00309 08 xch a,x ;[INF] 1, 1 + 1263 1263 0030A 12 movw bc,ax ;[INF] 1, 1 + 1264 1264 0030B EF4D br $?L0072 ;[INF] 2, 3 + 1265 1265 0030D ??eb01_vreg_ctr_read: + 1266 1266 ; line 316 : } + 1267 1267 0030D ?L0076: + 1268 1268 ; line 317 : else if( adrs == VREG_C_ACC_HOSU_HIST ) + 1269 1269 $DGL 0,13 + 1270 1270 0030D 66 mov a,l ;[INF] 1, 1 + 1271 1271 0030E 4C4F cmp a,#04FH ; 79 ;[INF] 2, 1 + 1272 1272 00310 DF06 bnz $?L0078 ;[INF] 2, 4 + 1273 1273 ; line 318 : { + 1274 1274 00312 ??bb02_vreg_ctr_read: + 1275 1275 ; line 319 : return( hosu_read() ); + 1276 1276 $DGL 0,15 + 1277 1277 00312 RFD0000 call !_hosu_read ;[INF] 3, 3 + 1278 1278 00315 F3 clrb b ;[INF] 1, 1 + 1279 1279 00316 EF42 br $?L0072 ;[INF] 2, 3 + 1280 1280 00318 ??eb02_vreg_ctr_read: + 1281 1281 ; line 320 : } + 1282 1282 00318 ?L0078: + 1283 1283 ; line 321 : else if( adrs == VREG_C_RTC_SEC_FINE_L ) + 1284 1284 $DGL 0,17 + 1285 1285 00318 66 mov a,l ;[INF] 1, 1 + 1286 1286 00319 4C3D cmp a,#03DH ; 61 ;[INF] 2, 1 + 1287 1287 0031B DF0C bnz $?L0080 ;[INF] 2, 4 + 1288 1288 ; line 322 : { + 1289 1289 0031D ??bb03_vreg_ctr_read: + 1290 1290 ; line 323 : rsub_temp = RSUBC; + 1291 1291 $DGL 0,19 + 1292 1292 0031D AE90 movw ax,RSUBC ;[INF] 2, 1 + 1293 1293 0031F RBF6000 movw !?L0073,ax ; rsub_temp ;[INF] 3, 1 + 1294 1294 ; line 324 : return( (u8)( rsub_temp & 0xFF ) ); + 1295 1295 $DGL 0,20 + 1296 1296 00322 RD96000 mov x,!?L0073 ; rsub_temp ;[INF] 3, 1 + 1297 1297 00325 F1 clrb a ;[INF] 1, 1 + 1298 1298 00326 12 movw bc,ax ;[INF] 1, 1 + 1299 1299 00327 EF31 br $?L0072 ;[INF] 2, 3 + 1300 1300 00329 ??eb03_vreg_ctr_read: + 1301 1301 ; line 325 : } + 1302 1302 00329 ?L0080: + 1303 1303 ; line 326 : else if( adrs == VREG_C_RTC_SEC_FINE_H ) + 1304 1304 $DGL 0,22 + 1305 1305 00329 66 mov a,l ;[INF] 1, 1 + 1306 1306 0032A 4C3E cmp a,#03EH ; 62 ;[INF] 2, 1 + 1307 1307 0032C DF07 bnz $?L0082 ;[INF] 2, 4 + 1308 1308 ; line 327 : { + 1309 1309 0032E ??bb04_vreg_ctr_read: + 1310 1310 ; line 328 : return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) ); + 1311 1311 $DGL 0,24 + 1312 1312 0032E RD96100 mov x,!?L0073+1 ; rsub_temp ;[INF] 3, 1 + 1313 1313 00331 F1 clrb a ;[INF] 1, 1 + 1314 1314 00332 12 movw bc,ax ;[INF] 1, 1 + 1315 1315 00333 EF25 br $?L0072 ;[INF] 2, 3 + 1316 1316 00335 ??eb04_vreg_ctr_read: + 1317 1317 ; line 329 : } + 1318 1318 00335 ?L0082: + 1319 1319 ; line 330 : else if( adrs == VREG_C_INFO ) + 1320 1320 $DGL 0,26 + 1321 1321 00335 66 mov a,l ;[INF] 1, 1 + 1322 1322 00336 4C7F cmp a,#07FH ; 127 ;[INF] 2, 1 + 1323 1323 00338 DF0E bnz $?L0084 ;[INF] 2, 4 + 1324 1324 ; line 331 : { + 1325 1325 0033A ??bb05_vreg_ctr_read: + 1326 1326 ; line 332 : renge_task_immed_add( tski_mcu_info_read ); + 1327 1327 $DGL 0,28 + 1328 1328 0033A R300000 movw ax,#loww (_tski_mcu_info_read) ;[INF] 3, 1 + 1329 1329 0033D RFD0000 call !_renge_task_immed_add ;[INF] 3, 3 + 1330 1330 ; line 333 : IICAMK = 1; + 1331 1331 $DGL 0,29 + 1332 1332 00340 713AD5 set1 MK2H.3 ;[INF] 3, 2 + 1333 1333 ; line 334 : return( 0x4A ); + 1334 1334 $DGL 0,30 + 1335 1335 00343 324A00 movw bc,#04AH ; 74 ;[INF] 3, 1 + 1336 1336 00346 EF12 br $?L0072 ;[INF] 2, 3 + 1337 1337 00348 ??eb05_vreg_ctr_read: + 1338 1338 ; line 335 : } + 1339 1339 00348 ?L0084: + 1340 1340 ; line 336 : + 1341 1341 ; line 337 : #if 1 + 1342 1342 ; line 338 : if( adrs >= VREG_C_ENDMARK_ ) + 1343 1343 $DGL 0,34 + 1344 1344 00348 66 mov a,l ;[INF] 1, 1 + 1345 1345 00349 4C60 cmp a,#060H ; 96 ;[INF] 2, 1 + 1346 1346 0034B DC05 bc $?L0086 ;[INF] 2, 4 + 1347 1347 ; line 339 : { + 1348 1348 0034D ??bb06_vreg_ctr_read: + 1349 1349 ; line 340 : // VREG_C_INFO > VREG_C_ENDMARK_ なので + 1350 1350 ; line 341 : // いじるときは注意 + 1351 1351 ; line 342 : return( 0xEE ); + 1352 1352 $DGL 0,38 + 1353 1353 0034D 32EE00 movw bc,#0EEH ; 238 ;[INF] 3, 1 + 1354 1354 00350 EF08 br $?L0072 ;[INF] 2, 3 + 1355 1355 00352 ??eb06_vreg_ctr_read: + 1356 1356 ; line 343 : } + 1357 1357 00352 ?L0086: + 1358 1358 ; line 344 : #endif + 1359 1359 ; line 345 : return ( vreg_ctr[adrs] ); + 1360 1360 $DGL 0,41 + 1361 1361 00352 66 mov a,l ;[INF] 1, 1 + 1362 1362 00353 73 mov b,a ;[INF] 1, 1 + 1363 1363 00354 R090000 mov a,_vreg_ctr[b] ;[INF] 3, 1 + 1364 1364 00357 318E shrw ax,8 ;[INF] 2, 1 + 1365 1365 00359 12 movw bc,ax ;[INF] 1, 1 + 1366 1366 ; line 346 : } + 1367 1367 0035A ?L0072: + 1368 1368 $DGL 0,42 + 1369 1369 0035A ??ef_vreg_ctr_read: + 1370 1370 0035A C6 pop hl ;[INF] 1, 1 + 1371 1371 0035B D7 ret ;[INF] 1, 6 + 1372 1372 0035C ??ee_vreg_ctr_read: + 1373 1373 ; line 347 : + 1374 1374 ; line 348 : + 1375 1375 ; line 349 : + 1376 1376 ; line 350 : // ******************************************************** + 1377 1377 ; line 351 : // I2C仮想レジスタから読まれて何かするレジスタ + 1378 1378 ; line 352 : void vreg_ctr_after_read( u8 adrs ) + 1379 1379 ; line 353 : { + 1380 1380 0035C _vreg_ctr_after_read: + 1381 1381 $DGL 1,125 + 1382 1382 0035C C7 push hl ;[INF] 1, 1 + 1383 1383 0035D 16 movw hl,ax ;[INF] 1, 1 + 1384 1384 0035E ??bf_vreg_ctr_after_read: + 1385 1385 ; line 354 : + 1386 1386 ; line 355 : // 割り込みフラグはリードでクリア + 1387 1387 ; line 356 : switch( adrs ) + 1388 1388 $DGL 0,4 + 1389 1389 0035E 17 movw ax,hl ;[INF] 1, 1 + 1390 1390 0035F F1 clrb a ;[INF] 1, 1 + 1391 1391 00360 241000 subw ax,#010H ; 16 ;[INF] 3, 1 + 1392 1392 00363 240500 subw ax,#05H ; 5 ;[INF] 3, 1 + 1393 1393 00366 DE09 bnc $?L0092 ;[INF] 2, 4 + 1394 1394 ; line 357 : { + 1395 1395 00368 ??bb00_vreg_ctr_after_read: + 1396 1396 ; line 358 : case VREG_C_IRQ0: + 1397 1397 ; line 359 : case VREG_C_IRQ1: + 1398 1398 ; line 360 : case VREG_C_IRQ2: + 1399 1399 ; line 361 : case VREG_C_IRQ3: + 1400 1400 ; line 362 : case VREG_C_IRQ4: + 1401 1401 ; line 363 : vreg_ctr[ adrs ] = 0; + 1402 1402 $DGL 0,11 + 1403 1403 00368 66 mov a,l ;[INF] 1, 1 + 1404 1404 00369 72 mov c,a ;[INF] 1, 1 + 1405 1405 0036A R38000000 mov _vreg_ctr[c],#00H ; 0 ;[INF] 4, 1 + 1406 1406 ; line 364 : irq_readed = 1; + 1407 1407 $DGL 0,12 + 1408 1408 0036E R710200 set1 _irq_readed ;[INF] 3, 2 + 1409 1409 ; line 365 : break; + 1410 1410 ; line 366 : + 1411 1411 ; line 367 : default: + 1412 1412 00371 ?L0092: + 1413 1413 ; line 368 : break; + 1414 1414 00371 ??eb00_vreg_ctr_after_read: + 1415 1415 ; line 369 : } + 1416 1416 ; line 370 : } + 1417 1417 $DGL 0,18 + 1418 1418 00371 ??ef_vreg_ctr_after_read: + 1419 1419 00371 C6 pop hl ;[INF] 1, 1 + 1420 1420 00372 D7 ret ;[INF] 1, 6 + 1421 1421 00373 ??ee_vreg_ctr_after_read: + 1422 1422 ; line 371 : + 1423 1423 ; line 372 : + 1424 1424 ; line 373 : + 1425 1425 ; line 374 : + 1426 1426 ; line 375 : + 1427 1427 ; line 376 : + 1428 1428 ; line 377 : /*************************************************************** + 1429 1429 ; *************** + 1430 1430 ; line 378 : 割り込みを入れる + 1431 1431 ; line 379 : 割り込みマスクが必要と言うことでこんな事をする羽目になりました + 1432 1432 ; line 380 : *************************************************************** + 1433 1433 ; **************/ + 1434 1434 ; line 381 : #if 0 + 1435 1435 ; line 382 : // マスクされてたら、フラグは立てるが、割り込みは入れない。 + 1436 1436 ; line 383 : #define set_irq( irqreg, bitpos ) \ + 1437 1437 ; line 384 : { \ + 1438 1438 ; line 385 : vreg_ctr[ irqreg ] |= bitpos; \ + 1439 1439 ; line 386 : if( ( vreg_ctr[ irqreg+8 ] & bitpos ) == 0 ){ \ + 1440 1440 ; line 387 : IRQ0_ast; \ + 1441 1441 ; line 388 : } \ + 1442 1442 ; line 389 : } + 1443 1443 ; line 390 : #endif + 1444 1444 ; line 391 : + 1445 1445 ; line 392 : // マスクされてたら、フラグも立てず、割り込みも入れない。 + 1446 1446 ; line 393 : void set_irq( u8 irqreg, u8 irq_flg ) + 1447 1447 ; line 394 : { + 1448 1448 00373 _set_irq: + 1449 1449 $DGL 1,136 + 1450 1450 00373 717BFA di ;[INF] 3, 4 + 1451 1451 00376 C7 push hl ;[INF] 1, 1 + 1452 1452 00377 C1 push ax ;[INF] 1, 1 + 1453 1453 00378 C1 push ax ;[INF] 1, 1 + 1454 1454 00379 FBF8FF movw hl,sp ;[INF] 3, 1 + 1455 1455 0037C ??bf_set_irq: + 1456 1456 ; line 395 : u8 tot; + 1457 1457 ; line 396 : + 1458 1458 ; line 397 : DI(); + 1459 1459 ; line 398 : if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 ){ + 1460 1460 $DGL 0,5 + 1461 1461 0037C 8C02 mov a,[hl+2] ; irqreg ;[INF] 2, 1 + 1462 1462 0037E 73 mov b,a ;[INF] 1, 1 + 1463 1463 0037F R090800 mov a,_vreg_ctr+8[b] ;[INF] 3, 1 + 1464 1464 00382 5E0A and a,[hl+10] ; irq_flg ;[INF] 2, 1 + 1465 1465 00384 D1 cmp0 a ;[INF] 1, 1 + 1466 1466 00385 DF24 bnz $?L0097 ;[INF] 2, 4 + 1467 1467 00387 ??bb00_set_irq: + 1468 1468 ; line 399 : vreg_ctr[ irqreg ] |= irq_flg; + 1469 1469 $DGL 0,6 + 1470 1470 00387 8C02 mov a,[hl+2] ; irqreg ;[INF] 2, 1 + 1471 1471 00389 318E shrw ax,8 ;[INF] 2, 1 + 1472 1472 0038B R040000 addw ax,#loww (_vreg_ctr) ;[INF] 3, 1 + 1473 1473 0038E 14 movw de,ax ;[INF] 1, 1 + 1474 1474 0038F 89 mov a,[de] ;[INF] 1, 1 + 1475 1475 00390 6E0A or a,[hl+10] ; irq_flg ;[INF] 2, 1 + 1476 1476 00392 99 mov [de],a ;[INF] 1, 1 + 1477 1477 ; line 400 : IRQ0_neg; // 一瞬上げて落とし直す。 + 1478 1478 $DGL 0,7 + 1479 1479 00393 ??bb01_set_irq: + 1480 1480 00393 716A27 set1 PM7.6 ;[INF] 3, 2 + 1481 1481 00396 ??eb01_set_irq: + 1482 1482 ; line 401 : // EI(); + 1483 1483 ; line 402 : tot = 0; + 1484 1484 $DGL 0,9 + 1485 1485 00396 CC0100 mov [hl+1],#00H ; tot,0 ;[INF] 3, 1 + 1486 1486 ; line 403 : while( !IRQ0 && ( ++tot != 0 ) ){;} // O.D.なのでちゃん + 1487 1487 ; とあがるのを待つ ＆ IRQ_mcu がLに縛られてると困る(基板不良) + 1488 1488 $DGL 0,10 + 1489 1489 00399 ?L0099: + 1490 1490 00399 31620708 bt P7.6,$?L0100 ;[INF] 4, 5 + 1491 1491 0039D 615901 inc [hl+1] ; tot ;[INF] 3, 2 + 1492 1492 003A0 8C01 mov a,[hl+1] ; tot ;[INF] 2, 1 + 1493 1493 003A2 D1 cmp0 a ;[INF] 1, 1 + 1494 1494 003A3 DFF4 bnz $?L0099 ;[INF] 2, 4 + 1495 1495 003A5 ??bb02_set_irq: + 1496 1496 003A5 ??eb02_set_irq: + 1497 1497 003A5 ?L0100: + 1498 1498 ; line 404 : IRQ0_ast; + 1499 1499 $DGL 0,11 + 1500 1500 003A5 ??bb03_set_irq: + 1501 1501 003A5 716307 clr1 P7.6 ;[INF] 3, 2 + 1502 1502 003A8 716B27 clr1 PM7.6 ;[INF] 3, 2 + 1503 1503 003AB ??eb03_set_irq: + 1504 1504 003AB ??eb00_set_irq: + 1505 1505 ; line 405 : } + 1506 1506 003AB ?L0097: + 1507 1507 ; line 406 : EI(); + 1508 1508 ; line 407 : } + 1509 1509 $DGL 0,14 + 1510 1510 003AB ??ef_set_irq: + 1511 1511 003AB 1004 addw sp,#04H ;[INF] 2, 1 + 1512 1512 003AD C6 pop hl ;[INF] 1, 1 + 1513 1513 003AE 717AFA ei ;[INF] 3, 4 + 1514 1514 003B1 D7 ret ;[INF] 1, 6 + 1515 1515 003B2 ??ee_set_irq: + 1516 1516 + 1517 1517 ----- @@CODEL CSEG + 1518 1518 + 1519 1519 ----- @@BASE CSEG BASE + 1520 1520 END + 1521 1521 + 1522 1522 + 1523 1523 ; *** Code Information *** + 1524 1524 ; + 1525 1525 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c + 1526 1526 ; + 1527 1527 ; $FUNC vreg_ctr_init(42) + 1528 1528 ; void=(void) + 1529 1529 ; CODE SIZE= 21 bytes, CLOCK_SIZE= 11 clocks, STACK_SIZE= 0 bytes + 1530 1530 ; + 1531 1531 ; $FUNC vreg_ctr_write(66) + 1532 1532 ; void=(unsigned char adrs:x, unsigned char data:[sp+6]) + 1533 1533 ; CODE SIZE= 660 bytes, CLOCK_SIZE= 961 clocks, STACK_SIZE= 12 bytes + 1534 1534 ; + 1535 1535 ; $CALL renge_task_immed_add(80) + 1536 1536 ; bc=(pointer:ax) + 1537 1537 ; + 1538 1538 ; $CALL renge_task_immed_add(94) + 1539 1539 ; bc=(pointer:ax) + 1540 1540 ; + 1541 1541 ; $CALL renge_task_immed_add(111) + 1542 1542 ; bc=(pointer:ax) + 1543 1543 ; + 1544 1544 ; $CALL renge_task_immed_add(120) + 1545 1545 ; bc=(pointer:ax) + 1546 1546 ; + 1547 1547 ; $CALL renge_task_immed_add(124) + 1548 1548 ; bc=(pointer:ax) + 1549 1549 ; + 1550 1550 ; $CALL renge_task_immed_add(132) + 1551 1551 ; bc=(pointer:ax) + 1552 1552 ; + 1553 1553 ; $CALL set_rtc(195) + 1554 1554 ; void=(int:ax, int:[sp+4]) + 1555 1555 ; + 1556 1556 ; $CALL set_rtc(199) + 1557 1557 ; void=(int:ax, int:[sp+4]) + 1558 1558 ; + 1559 1559 ; $CALL set_rtc(203) + 1560 1560 ; void=(int:ax, int:[sp+4]) + 1561 1561 ; + 1562 1562 ; $CALL set_rtc(207) + 1563 1563 ; void=(int:ax, int:[sp+4]) + 1564 1564 ; + 1565 1565 ; $CALL set_rtc(211) + 1566 1566 ; void=(int:ax, int:[sp+4]) + 1567 1567 ; + 1568 1568 ; $CALL set_rtc(215) + 1569 1569 ; void=(int:ax, int:[sp+4]) + 1570 1570 ; + 1571 1571 ; $CALL renge_task_immed_add(249) + 1572 1572 ; bc=(pointer:ax) + 1573 1573 ; + 1574 1574 ; $CALL renge_task_immed_add(254) + 1575 1575 ; bc=(pointer:ax) + 1576 1576 ; + 1577 1577 ; $CALL renge_task_immed_add(263) + 1578 1578 ; bc=(pointer:ax) + 1579 1579 ; + 1580 1580 ; $CALL clear_hosu_hist(275) + 1581 1581 ; void=(void) + 1582 1582 ; + 1583 1583 ; $FUNC vreg_ctr_read(305) + 1584 1584 ; bc=(unsigned char adrs:x) + 1585 1585 ; CODE SIZE= 117 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 6 bytes + 1586 1586 ; + 1587 1587 ; $CALL rtc_buf_reflesh(311) + 1588 1588 ; void=(void) + 1589 1589 ; + 1590 1590 ; $CALL hosu_read(319) + 1591 1591 ; bc=(void) + 1592 1592 ; + 1593 1593 ; $CALL renge_task_immed_add(332) + 1594 1594 ; bc=(pointer:ax) + 1595 1595 ; + 1596 1596 ; $FUNC vreg_ctr_after_read(353) + 1597 1597 ; void=(unsigned char adrs:x) + 1598 1598 ; CODE SIZE= 23 bytes, CLOCK_SIZE= 22 clocks, STACK_SIZE= 2 bytes + 1599 1599 ; + 1600 1600 ; $FUNC set_irq(394) + 1601 1601 ; void=(unsigned char irqreg:x, unsigned char irq_flg:[sp+4]) + 1602 1602 ; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 6 bytes + 1603 1603 + 1604 1604 ; Target chip : uPD79F0104 + 1605 1605 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.1 @@BITS +00000 00030H @@CNST +00000 00000H @@R_INIT +00000 00000H @@INIT +00000 00062H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 003B2H ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/vreg_ctr.rel b/branches/0.10(X3)/vreg_ctr.rel new file mode 100644 index 0000000..24cf048 Binary files /dev/null and b/branches/0.10(X3)/vreg_ctr.rel differ diff --git a/branches/0.10(X3)/vreg_twl.c b/branches/0.10(X3)/vreg_twl.c new file mode 100644 index 0000000..2a162c5 --- /dev/null +++ b/branches/0.10(X3)/vreg_twl.c @@ -0,0 +1,146 @@ +/* ======================================================== + +TWL互換側のI2Cレジスタ + + ======================================================== */ +#include "incs.h" +#include "jhl_defs.h" +#include "vreg_twl.h" + +#include "vreg_ctr.h" +#include "renge\renge_task_intval.h" + +// ======================================================== +#define TWL_REG_VER_INFO 0x35 +#define NON_EXIST_REG 0xFF + +// ======================================================== +u8 vreg_twl[_REG_TWL_INT_ADRS_ENDMARK]; + + +/* ======================================================== + 仮想レジスタの初期化 + ======================================================== */ +void vreg_twl_init( ) +{ + vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03; +} + + +// ======================================================== +// I2C仮想レジスタに書く・何かアクションする +//　引数 adrs は内部アドレス +// 　存在しないアドレスにアクセスした場合、何もしません。 +void vreg_twl_write( u8 adrs, u8 data ) +{ + switch ( adrs ) + { + case ( REG_TWL_INT_ADRS_VOL ): + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE ); + break; + } + + case ( REG_TWL_INT_ADRS_MODE ): + vreg_twl[adrs] = ( data & 0x03 ); + break; + + case ( REG_TWL_INT_ADRS_CAM ): + vreg_twl[adrs] = ( data & 0x03 ); + tsk_led_cam(); // todo 大丈夫？ + break; + + case ( REG_TWL_INT_ADRS_TEMP0 ): + vreg_twl[adrs] = data; + break; + + case ( REG_TWL_INT_ADRS_COMMAND ): +/* + if( data <= 2 ){ + if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 ) + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); // OFFも実装していたらしい。 + break; + } + else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 ) + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); //リセットしかない。他のは、SPIから来ます。 + break; + } + } +*/ + if( data == REG_BIT_TWL_RESET_REQ ) + { + set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); //リセットしかない。他のは、SPIから来ます。 + break; + } + } + return; +} + + + +// ======================================================== +// I2C仮想レジスタから読みます。 +//　引数 adrs 外から見たときの、アドレス +//　戻り xx データ +// 　存在しないアドレスにアクセスした場合、戻り値は0x5A +u8 vreg_twl_read( u8 phy_adrs ) +{ + u8 temp; + + switch( phy_adrs ){ + case( REG_TWL_INT_ADRS_VER_INFO ): + return( TWL_REG_VER_INFO ); + + case( REG_TWL_INT_ADRS_POWER_INFO ): + if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F; + }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B; + }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07; + }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03; + }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 5 ){ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01; + }else{ + vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00; + } + + return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !BT_CHG_n ? 0x80: 0x00 ) ); // アダプタbit + + case( REG_TWL_INT_ADRS_IRQ ): + temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ]; + vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0; + return( temp ); + + default: + return( vreg_twl[ phy_adrs ] ); + + case( REG_TWL_ADRS_NON_EXIST ): + return( 0x00 ); + } +} + + + +// ======================================================== +// 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える +// 0xFFは存在しないアドレス。 +u8 adrs_table_twl_ext2int( u8 img ) +{ + switch( img ){ + case( REG_TWL_ADRS_IRQ ): return( REG_TWL_INT_ADRS_IRQ ); + case( REG_TWL_ADRS_COMMAND ): return( REG_TWL_INT_ADRS_COMMAND ); + case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_POWER_INFO ); + case( REG_TWL_ADRS_CAM ): return( REG_TWL_INT_ADRS_CAM ); + case( REG_TWL_ADRS_VOL ): return( REG_TWL_INT_ADRS_VOL ); + case( REG_TWL_ADRS_TEMP0 ): return( REG_TWL_INT_ADRS_TEMP0 ); + case( REG_TWL_ADRS_VER_INFO ): return( REG_TWL_INT_ADRS_VER_INFO ); + case( REG_TWL_ADRS_MODE ): return( REG_TWL_INT_ADRS_MODE ); + default: return( REG_TWL_ADRS_NON_EXIST ); +// 0が読めればよい、書けなくて良い +// case( REG_TWL_ADRS_WIFI ): return( REG_TWL_INT_ADRS_WIFI ); + } +} diff --git a/branches/0.10(X3)/vreg_twl.h b/branches/0.10(X3)/vreg_twl.h new file mode 100644 index 0000000..a1325d8 --- /dev/null +++ b/branches/0.10(X3)/vreg_twl.h @@ -0,0 +1,129 @@ +#ifndef __vreg_twl__ +#define __vreg_twl__ +/* ========================================================================= */ +extern u8 vreg_twl[]; + + + + +/* + * 外から見たときのマイコンレジスタアドレス。 + * 拡張性などを考えて飛び飛びにしてある。 + */ +/* + * 割り込み要因フラグは + * MSB:外部電源供給有り/なし変化 （未実装） + * 6:Volキー操作（変更に限らず。MAX時に＋でも。） + * 5:電池電圧 少 検出 + * 4: 僅 + * 3:電源スイッチ 押され検出 + * 2:（未設定） + * 1:電源スイッチ OFF 時間押され検出 + * LSB: リセット + */ +enum REG_TWL_ADRS +{ // 未定義アドレスへ書き込んだ際は無視 + REG_TWL_ADRS_VER_INFO = 0x00, + REG_TWL_ADRS_PMIC_INFO, + REG_TWL_ADRS_BATT_INFO, + REG_TWL_ADRS_IRQ = 0x10, + REG_TWL_ADRS_COMMAND, + REG_TWL_ADRS_MODE, + REG_TWL_ADRS_POWER_INFO = 0x20, + REG_TWL_ADRS_POWER_SAVE, + REG_TWL_ADRS_WIFI = 0x30, + REG_TWL_ADRS_CAM, + REG_TWL_ADRS_VOL = 0x40, + REG_TWL_ADRS_BL, + REG_TWL_ADRS_CODEC_MIC_GAIN = 0x50, + REG_TWL_ADRS_ADC_CALIB = 0x60, + REG_TWL_ADRS_ADC_CALIB_STATUS, + REG_TWL_ADRS_ADC_CALIB_VALUE, + REG_TWL_ADRS_POWER_LED, + REG_TWL_ADRS_TEMP0 = 0x70, + REG_TWL_ADRS_TEMP1, + REG_TWL_ADRS_TEMP2, + REG_TWL_ADRS_TEMP3, + REG_TWL_ADRS_TEMP4, + REG_TWL_ADRS_TEMP5, + REG_TWL_ADRS_TEMP6, + REG_TWL_ADRS_TEMP7, + REG_TWL_ADRS_TIME_PWSW_DELAY = 0x80, + REG_TWL_ADRS_TIME_PWSW_THRESHOLD +}; + +#define REG_TWL_ADRS_NON_EXIST 0xFF + +/* + * マイコン内部でのレジスタの実装 + * もちろんつめてある + */ +enum REG_TWL_ADRS_INT +{ + REG_TWL_INT_ADRS_VER_INFO = 0x00, +// REG_TWL_INT_ADRS_PMIC_INFO, +// REG_TWL_INT_ADRS_BATT_INFO, + REG_TWL_INT_ADRS_IRQ, // 0x10, + REG_TWL_INT_ADRS_COMMAND, + REG_TWL_INT_ADRS_MODE, + REG_TWL_INT_ADRS_POWER_INFO, // 0x20, +// REG_TWL_INT_ADRS_POWER_SAVE, +// REG_TWL_INT_ADRS_WIFI, // 0x30, + REG_TWL_INT_ADRS_CAM, + REG_TWL_INT_ADRS_VOL, // 0x40, +// REG_TWL_INT_ADRS_BL, +// REG_TWL_INT_ADRS_CODEC_MIC_GAIN, // 0x50, +// REG_TWL_INT_ADRS_CODEC_MIC_GAIN_RELOAD, +// REG_TWL_INT_ADRS_ADC_CALIB, // 0x60, +// REG_TWL_INT_ADRS_ADC_CALIB_STATUS, +// REG_TWL_INT_ADRS_ADC_CALIB_VALUE, +// REG_TWL_INT_ADRS_POWER_LED, + REG_TWL_INT_ADRS_TEMP0, // 0x70 - 0x77 + REG_TWL_INT_ADRS_TEMP1, + REG_TWL_INT_ADRS_TEMP2, + REG_TWL_INT_ADRS_TEMP3, + REG_TWL_INT_ADRS_TEMP4, + REG_TWL_INT_ADRS_TEMP5, + REG_TWL_INT_ADRS_TEMP6, + REG_TWL_INT_ADRS_TEMP7, +// REG_TWL_INT_ADRS_TIME_PWSW_DELAY, +// REG_TWL_INT_ADRS_TIME_PWSW_THRESHOLD + _REG_TWL_INT_ADRS_ENDMARK, +}; + + + +/* ========================================================================= */ +#define is_TWL ( vregs[ REG_TWL_INT_ADRS_MODE ] & 0x01 ) +#define with_NAND ( vregs[ REG_TWL_INT_ADRS_MODE ] & 0x02 ) +#define volSteps32 ( vregs[ REG_TWL_INT_ADRS_MODE ] & 0x80 ) + +#define reg_wifi_led ( vregs[ REG_TWL_INT_ADRS_WIFI ] & 0x01 ) +#define reg_wifi_led_blink ( vregs[ REG_TWL_INT_ADRS_WIFI ] & 0x02 ) + + +typedef enum twl_camLed_mode_{ + TWL_CAMLED_OFF, + TWL_CAMLED_ON, + TWL_CAMLED_BLINK, + TWL_CAMLED_DEF_ON +}camLed_mode; + + +/* ========================================================================= */ +void vreg_twl_init( ); +void vreg_twl_write( u8 adrs, u8 data ); +u8 adrs_table_twl_ext2int( u8 img ); +u8 vreg_twl_read( u8 phy_adrs ); + +task_status_immed command_from_twl( ); + + +// 読んだらクリアなどの処理 +#define vreg_twl_after_read( reg_adrs ); \ + if( reg_adrs == REG_TWL_INT_ADRS_IRQ ) \ + { \ + vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;\ + } + +#endif diff --git a/branches/0.10(X3)/vreg_twl.prn b/branches/0.10(X3)/vreg_twl.prn new file mode 100644 index 0000000..66c05b0 --- /dev/null +++ b/branches/0.10(X3)/vreg_twl.prn @@ -0,0 +1,781 @@ + + + +78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1 + + + +Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\vreg_twl.asm +Para-file: +In-file: inter_asm\vreg_twl.asm +Obj-file: vreg_twl.rel +Prn-file: vreg_twl.prn + + Assemble list + + ALNO STNO ADRS OBJECT M I SOURCE STATEMENT + + 1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24 + 2 2 + 3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i + 4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\ + 5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c + 6 6 ; In-file : vreg_twl.c + 7 7 ; Asm-file : inter_asm\vreg_twl.asm + 8 8 ; Para-file : + 9 9 + 10 10 $PROCESSOR(9F0104) + 11 11 $DEBUG + 12 12 $NODEBUGA + 13 13 $KANJICODE SJIS + 14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H + 15 15 + 16 16 $DGS FIL_NAM, .file, 062H, 0FFFEH, 03FH, 067H, 01H, 00H + 17 17 $DGS AUX_FIL, vreg_twl.c + 18 18 $DGS MOD_NAM, vreg_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H + 19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H + 20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H + 21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H + 22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H + 23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H + 24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H + 25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H + 26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H + 27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H + 28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H + 29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H + 30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H + 31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H + 32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H + 33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H + 34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H + 35 35 $DGS LAB_SYM, bs_S0051, U, U, 00H, 06H, 00H, 00H + 36 36 $DGS LAB_SYM, es_S0051, U, U, 00H, 06H, 00H, 00H + 37 37 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H + 38 38 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H + 39 39 $DGS STA_SYM, _tasks, U, U, 01H, 03H, 01H, 027H + 40 40 $DGS AUX_STR, 00H, 00H, 016H, 0BH, 00H, 00H, 00H, 04H + 41 41 $DGS GLV_SYM, _vreg_twl_init, U, U, 01H, 026H, 01H, 02H + 42 42 $DGS AUX_FUN, 00H, U, U, 01FH, 00H, 00H + 43 43 $DGS BEG_FUN, ??bf_vreg_twl_init, U, U, 00H, 065H, 01H, 00H + 44 44 $DGS AUX_BEG, 019H, 00H, 01FH + 45 45 $DGS END_FUN, ??ef_vreg_twl_init, U, U, 00H, 065H, 01H, 00H + 46 46 $DGS AUX_END, 03H + 47 47 $DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 026H, 01H, 02H + 48 48 $DGS AUX_FUN, 00H, U, U, 033H, 00H, 00H + 49 49 $DGS BEG_FUN, ??bf_vreg_twl_write, U, U, 00H, 065H, 01H, 00H + 50 50 $DGS AUX_BEG, 023H, 02H, 025H + 51 51 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 52 52 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H + 53 53 $DGS BEG_BLK, ??bb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 54 54 $DGS AUX_BEG, 03H, 00H, 027H + 55 55 $DGS BEG_BLK, ??bb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 56 56 $DGS AUX_BEG, 05H, 00H, 02BH + 57 57 $DGS END_BLK, ??eb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 58 58 $DGS AUX_END, 08H + 59 59 $DGS BEG_BLK, ??bb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 60 60 $DGS AUX_BEG, 027H, 00H, 00H + 61 61 $DGS END_BLK, ??eb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 62 62 $DGS AUX_END, 02AH + 63 63 $DGS END_BLK, ??eb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H + 64 64 $DGS AUX_END, 02BH + 65 65 $DGS END_FUN, ??ef_vreg_twl_write, U, U, 00H, 065H, 01H, 00H + 66 66 $DGS AUX_END, 02DH + 67 67 $DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 026H, 01H, 02H + 68 68 $DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H + 69 69 $DGS BEG_FUN, ??bf_vreg_twl_read, U, U, 00H, 065H, 01H, 00H + 70 70 $DGS AUX_BEG, 059H, 02H, 039H + 71 71 $DGS REG_PAR, _phy_adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 72 72 $DGS REG_VAR, _temp, 07H, 0FFFFH, 010CH, 04H, 00H, 00H + 73 73 $DGS BEG_BLK, ??bb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 74 74 $DGS AUX_BEG, 04H, 00H, 03BH + 75 75 $DGS BEG_BLK, ??bb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 76 76 $DGS AUX_BEG, 09H, 00H, 03FH + 77 77 $DGS END_BLK, ??eb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 78 78 $DGS AUX_END, 0BH + 79 79 $DGS BEG_BLK, ??bb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 80 80 $DGS AUX_BEG, 0BH, 00H, 043H + 81 81 $DGS END_BLK, ??eb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 82 82 $DGS AUX_END, 0DH + 83 83 $DGS BEG_BLK, ??bb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 84 84 $DGS AUX_BEG, 0DH, 00H, 047H + 85 85 $DGS END_BLK, ??eb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 86 86 $DGS AUX_END, 0FH + 87 87 $DGS BEG_BLK, ??bb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 88 88 $DGS AUX_BEG, 0FH, 00H, 04BH + 89 89 $DGS END_BLK, ??eb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 90 90 $DGS AUX_END, 011H + 91 91 $DGS BEG_BLK, ??bb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 92 92 $DGS AUX_BEG, 011H, 00H, 04FH + 93 93 $DGS END_BLK, ??eb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 94 94 $DGS AUX_END, 013H + 95 95 $DGS BEG_BLK, ??bb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 96 96 $DGS AUX_BEG, 013H, 00H, 00H + 97 97 $DGS END_BLK, ??eb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 98 98 $DGS AUX_END, 015H + 99 99 $DGS END_BLK, ??eb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H + 100 100 $DGS AUX_END, 023H + 101 101 $DGS END_FUN, ??ef_vreg_twl_read, U, U, 00H, 065H, 01H, 00H + 102 102 $DGS AUX_END, 024H + 103 103 $DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 026H, 01H, 02H + 104 104 $DGS AUX_FUN, 00H, U, U, 062H, 00H, 00H + 105 105 $DGS BEG_FUN, ??bf_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H + 106 106 $DGS AUX_BEG, 084H, 02H, 05CH + 107 107 $DGS REG_PAR, _img, 06H, 0FFFFH, 010CH, 011H, 00H, 00H + 108 108 $DGS BEG_BLK, ??bb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H + 109 109 $DGS AUX_BEG, 02H, 00H, 00H + 110 110 $DGS END_BLK, ??eb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H + 111 111 $DGS AUX_END, 0EH + 112 112 $DGS END_FUN, ??ef_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H + 113 113 $DGS AUX_END, 0FH + 114 114 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 026H, 01H, 03H + 115 115 $DGS AUX_STR, 00H, 00H, 0FH, 0FH, 00H, 00H, 00H, 00H + 116 116 $DGS GLV_SYM, _tsk_sw, U, U, 01H, 02H, 01H, 02H + 117 117 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 118 118 $DGS GLV_SYM, _tsk_adc, U, U, 01H, 02H, 01H, 02H + 119 119 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 120 120 $DGS GLV_SYM, _tsk_batt, U, U, 01H, 02H, 01H, 02H + 121 121 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 122 122 $DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 02H, 01H, 02H + 123 123 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 124 124 $DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 02H, 01H, 02H + 125 125 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 126 126 $DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 02H, 01H, 02H + 127 127 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 128 128 $DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 02H, 01H, 02H + 129 129 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 130 130 $DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 02H, 01H, 02H + 131 131 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 132 132 $DGS GLV_SYM, _tsk_debug, U, U, 01H, 02H, 01H, 02H + 133 133 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 134 134 $DGS GLV_SYM, _tsk_debug2, U, U, 01H, 02H, 01H, 02H + 135 135 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 136 136 $DGS GLV_SYM, _tsk_sys, U, U, 01H, 02H, 01H, 02H + 137 137 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 138 138 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H + 139 139 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H + 140 140 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H + 141 141 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H + 142 142 + 143 143 EXTRN _tsk_sw + 144 144 EXTRN _tsk_adc + 145 145 EXTRN _tsk_batt + 146 146 EXTRN _tsk_led_pow + 147 147 EXTRN _tsk_led_wifi + 148 148 EXTRN _tsk_led_notify + 149 149 EXTRN _tsk_led_cam + 150 150 EXTRN _tsk_misc_stat + 151 151 EXTRN _tsk_debug + 152 152 EXTRN _tsk_debug2 + 153 153 EXTRN _tsk_sys + 154 154 EXTRN _set_irq + 155 155 EXTRN _vreg_ctr + 156 156 PUBLIC _vreg_twl + 157 157 PUBLIC _vreg_twl_init + 158 158 PUBLIC _vreg_twl_write + 159 159 PUBLIC _vreg_twl_read + 160 160 PUBLIC _adrs_table_twl_ext2int + 161 161 + 162 162 ----- @@BITS BSEG + 163 163 + 164 164 ----- @@CNST CSEG MIRRORP + 165 165 00000 01 _lpf_coeff: DB 01H ; 1 + 166 166 00001 02 DB 02H ; 2 + 167 167 00002 02 DB 02H ; 2 + 168 168 00003 03 DB 03H ; 3 + 169 169 00004 03 DB 03H ; 3 + 170 170 00005 02 DB 02H ; 2 + 171 171 00006 00 DB 00H ; 0 + 172 172 00007 FE DB 0FEH ; 254 + 173 173 00008 FB DB 0FBH ; 251 + 174 174 00009 F7 DB 0F7H ; 247 + 175 175 0000A F3 DB 0F3H ; 243 + 176 176 0000B F0 DB 0F0H ; 240 + 177 177 0000C F0 DB 0F0H ; 240 + 178 178 0000D F3 DB 0F3H ; 243 + 179 179 0000E FA DB 0FAH ; 250 + 180 180 0000F 04 DB 04H ; 4 + 181 181 00010 12 DB 012H ; 18 + 182 182 00011 25 DB 025H ; 37 + 183 183 00012 38 DB 038H ; 56 + 184 184 00013 4D DB 04DH ; 77 + 185 185 00014 5F DB 05FH ; 95 + 186 186 00015 6E DB 06EH ; 110 + 187 187 00016 77 DB 077H ; 119 + 188 188 00017 7A DB 07AH ; 122 + 189 189 00018 77 DB 077H ; 119 + 190 190 00019 6E DB 06EH ; 110 + 191 191 0001A 5F DB 05FH ; 95 + 192 192 0001B 4D DB 04DH ; 77 + 193 193 0001C 38 DB 038H ; 56 + 194 194 0001D 25 DB 025H ; 37 + 195 195 0001E 12 DB 012H ; 18 + 196 196 0001F 04 DB 04H ; 4 + 197 197 00020 FA DB 0FAH ; 250 + 198 198 00021 F3 DB 0F3H ; 243 + 199 199 00022 F0 DB 0F0H ; 240 + 200 200 00023 F0 DB 0F0H ; 240 + 201 201 00024 F3 DB 0F3H ; 243 + 202 202 00025 F7 DB 0F7H ; 247 + 203 203 00026 FB DB 0FBH ; 251 + 204 204 00027 FE DB 0FEH ; 254 + 205 205 00028 00 DB 00H ; 0 + 206 206 00029 02 DB 02H ; 2 + 207 207 0002A 03 DB 03H ; 3 + 208 208 0002B 03 DB 03H ; 3 + 209 209 0002C 02 DB 02H ; 2 + 210 210 0002D 02 DB 02H ; 2 + 211 211 0002E 01 DB 01H ; 1 + 212 212 0002F 00 DB (1) + 213 213 + 214 214 ----- @@R_INIT CSEG UNIT64KP + 215 215 00000 R0000 DW loww (_tsk_sw) + 216 216 00002 R0000 DW loww (_tsk_adc) + 217 217 00004 R0000 DW loww (_tsk_batt) + 218 218 00006 R0000 DW loww (_tsk_led_pow) + 219 219 00008 R0000 DW loww (_tsk_led_wifi) + 220 220 0000A R0000 DW loww (_tsk_led_notify) + 221 221 0000C R0000 DW loww (_tsk_led_cam) + 222 222 0000E R0000 DW loww (_tsk_misc_stat) + 223 223 00010 R0000 DW loww (_tsk_debug) + 224 224 00012 R0000 DW loww (_tsk_debug2) + 225 225 00014 R0000 DW loww (_tsk_sys) + 226 226 + 227 227 ----- @@INIT DSEG BASEP + 228 228 00000 _tasks: DS (22) + 229 229 + 230 230 ----- @@DATA DSEG BASEP + 231 231 00000 _vreg_twl: DS (15) + 232 232 0000F DS (1) + 233 233 + 234 234 ----- @@R_INIS CSEG UNIT64KP + 235 235 + 236 236 ----- @@INIS DSEG SADDRP + 237 237 + 238 238 ----- @@DATS DSEG SADDRP + 239 239 + 240 240 ----- @@CNSTL CSEG PAGE64KP + 241 241 + 242 242 ----- @@RLINIT CSEG UNIT64KP + 243 243 + 244 244 ----- @@INITL DSEG UNIT64KP + 245 245 + 246 246 ----- @@DATAL DSEG UNIT64KP + 247 247 + 248 248 ----- @@CALT CSEG CALLT0 + 249 249 + 250 250 ; Sub-Routines created by CC78K0R + 251 251 + 252 252 ----- ROM_CODE CSEG BASE + 253 253 00000 bs_S0051: + 254 254 00000 67 mov a,h ;[INF] 1, 1 + 255 255 00001 5C03 and a,#03H ; 3 ;[INF] 2, 1 + 256 256 00003 72 mov c,a ;[INF] 1, 1 + 257 257 00004 66 mov a,l ;[INF] 1, 1 + 258 258 00005 73 mov b,a ;[INF] 1, 1 + 259 259 00006 62 mov a,c ;[INF] 1, 1 + 260 260 00007 R180000 mov _vreg_twl[b],a ;[INF] 3, 1 + 261 261 0000A D7 ret ;[INF] 1, 6 + 262 262 0000B es_S0051: + 263 263 + 264 264 ; *** Sub-Routine Information *** + 265 265 ; + 266 266 ; $SUB bs_S0051 + 267 267 ; CODE SIZE= 11 bytes + 268 268 + 269 269 ; End of Sub-Routines + 270 270 + 271 271 ; line 1 : /* ======================================================== + 272 272 ; line 2 : + 273 273 ; line 3 : TWL互換側のI2Cレジスタ + 274 274 ; line 4 : + 275 275 ; line 5 : ======================================================== */ + 276 276 ; line 6 : #include "incs.h" + 277 277 ; line 7 : #include "jhl_defs.h" + 278 278 ; line 8 : #include "vreg_twl.h" + 279 279 ; line 9 : + 280 280 ; line 10 : #include "vreg_ctr.h" + 281 281 ; line 11 : #include "renge\renge_task_intval.h" + 282 282 ; line 12 : + 283 283 ; line 13 : // ======================================================== + 284 284 ; line 14 : #define TWL_REG_VER_INFO 0x35 + 285 285 ; line 15 : #define NON_EXIST_REG 0xFF + 286 286 ; line 16 : + 287 287 ; line 17 : // ======================================================== + 288 288 ; line 18 : u8 vreg_twl[_REG_TWL_INT_ADRS_ENDMARK]; + 289 289 ; line 19 : + 290 290 ; line 20 : + 291 291 ; line 21 : /* ======================================================== + 292 292 ; line 22 : 仮想レジスタの初期化 + 293 293 ; line 23 : ======================================================== */ + 294 294 ; line 24 : void vreg_twl_init( ) + 295 295 ; line 25 : { + 296 296 + 297 297 ----- ROM_CODE CSEG BASE + 298 298 0000B _vreg_twl_init: + 299 299 $DGL 1,25 + 300 300 0000B ??bf_vreg_twl_init: + 301 301 ; line 26 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03; + 302 302 $DGL 0,2 + 303 303 0000B RCF030003 mov !_vreg_twl+3,#03H ; 3 ;[INF] 4, 1 + 304 304 ; line 27 : } + 305 305 $DGL 0,3 + 306 306 0000F ??ef_vreg_twl_init: + 307 307 0000F D7 ret ;[INF] 1, 6 + 308 308 00010 ??ee_vreg_twl_init: + 309 309 ; line 28 : + 310 310 ; line 29 : + 311 311 ; line 30 : // ======================================================== + 312 312 ; line 31 : // I2C仮想レジスタに書く・何かアクションする + 313 313 ; line 32 : //　引数 adrs は内部アドレス + 314 314 ; line 33 : // 　存在しないアドレスにアクセスした場合、何もしません。 + 315 315 ; line 34 : void vreg_twl_write( u8 adrs, u8 data ) + 316 316 ; line 35 : { + 317 317 00010 _vreg_twl_write: + 318 318 $DGL 1,31 + 319 319 00010 C7 push hl ;[INF] 1, 1 + 320 320 00011 8806 mov a,[sp+6] ;[INF] 2, 1 + 321 321 00013 16 movw hl,ax ;[INF] 1, 1 + 322 322 00014 ??bf_vreg_twl_write: + 323 323 ; line 36 : switch ( adrs ) + 324 324 $DGL 0,2 + 325 325 00014 17 movw ax,hl ;[INF] 1, 1 + 326 326 00015 F1 clrb a ;[INF] 1, 1 + 327 327 00016 E7 onew bc ;[INF] 1, 1 + 328 328 00017 340200 movw de,#02H ; 2 ;[INF] 3, 1 + 329 329 0001A 25 subw ax,de ;[INF] 1, 1 + 330 330 0001B DD2F bz $?L0010 ;[INF] 2, 4 + 331 331 0001D 23 subw ax,bc ;[INF] 1, 1 + 332 332 0001E DD17 bz $?L0007 ;[INF] 2, 4 + 333 333 00020 25 subw ax,de ;[INF] 1, 1 + 334 334 00021 DD19 bz $?L0008 ;[INF] 2, 4 + 335 335 00023 23 subw ax,bc ;[INF] 1, 1 + 336 336 00024 DD05 bz $?L0006 ;[INF] 2, 4 + 337 337 00026 23 subw ax,bc ;[INF] 1, 1 + 338 338 00027 DD1B bz $?L0009 ;[INF] 2, 4 + 339 339 00029 EF2D br $?L0013 ;[INF] 2, 3 + 340 340 ; line 37 : { + 341 341 0002B ??bb00_vreg_twl_write: + 342 342 ; line 38 : case ( REG_TWL_INT_ADRS_VOL ): + 343 343 0002B ?L0006: + 344 344 ; line 39 : { + 345 345 0002B ??bb01_vreg_twl_write: + 346 346 ; line 40 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE ); + 347 347 $DGL 0,6 + 348 348 0002B 304000 movw ax,#040H ; 64 ;[INF] 3, 1 + 349 349 0002E C1 push ax ;[INF] 1, 1 + 350 350 0002F 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 351 351 00031 RFD0000 call !_set_irq ;[INF] 3, 3 + 352 352 00034 C0 pop ax ;[INF] 1, 1 + 353 353 ; line 41 : break; + 354 354 $DGL 0,7 + 355 355 00035 EF21 br $?L0013 ;[INF] 2, 3 + 356 356 00037 ??eb01_vreg_twl_write: + 357 357 ; line 42 : } + 358 358 ; line 43 : + 359 359 ; line 44 : case ( REG_TWL_INT_ADRS_MODE ): + 360 360 00037 ?L0007: + 361 361 ; line 45 : vreg_twl[adrs] = ( data & 0x03 ); + 362 362 $DGL 0,11 + 363 363 00037 RFD0000 call !bs_S0051 ;[INF] 3, 3 + 364 364 ; line 46 : break; + 365 365 $DGL 0,12 + 366 366 0003A EF1C br $?L0013 ;[INF] 2, 3 + 367 367 ; line 47 : + 368 368 ; line 48 : case ( REG_TWL_INT_ADRS_CAM ): + 369 369 0003C ?L0008: + 370 370 ; line 49 : vreg_twl[adrs] = ( data & 0x03 ); + 371 371 $DGL 0,15 + 372 372 0003C RFD0000 call !bs_S0051 ;[INF] 3, 3 + 373 373 ; line 50 : tsk_led_cam(); // todo 大丈夫？ + 374 374 $DGL 0,16 + 375 375 0003F RFD0000 call !_tsk_led_cam ;[INF] 3, 3 + 376 376 ; line 51 : break; + 377 377 $DGL 0,17 + 378 378 00042 EF14 br $?L0013 ;[INF] 2, 3 + 379 379 ; line 52 : + 380 380 ; line 53 : case ( REG_TWL_INT_ADRS_TEMP0 ): + 381 381 00044 ?L0009: + 382 382 ; line 54 : vreg_twl[adrs] = data; + 383 383 $DGL 0,20 + 384 384 00044 66 mov a,l ;[INF] 1, 1 + 385 385 00045 73 mov b,a ;[INF] 1, 1 + 386 386 00046 67 mov a,h ;[INF] 1, 1 + 387 387 00047 R180000 mov _vreg_twl[b],a ;[INF] 3, 1 + 388 388 ; line 55 : break; + 389 389 $DGL 0,21 + 390 390 0004A EF0C br $?L0013 ;[INF] 2, 3 + 391 391 ; line 56 : + 392 392 ; line 57 : case ( REG_TWL_INT_ADRS_COMMAND ): + 393 393 0004C ?L0010: + 394 394 ; line 58 : /* + 395 395 ; line 59 : if( data <= 2 ){ + 396 396 ; line 60 : if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 ) + 397 397 ; line 61 : { + 398 398 ; line 62 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ ); + 399 399 ; // OFFも実装していたらしい。 + 400 400 ; line 63 : break; + 401 401 ; line 64 : } + 402 402 ; line 65 : else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 ) + 403 403 ; line 66 : { + 404 404 ; line 67 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); + 405 405 ; //リセットしかない。他のは、SPIから来ます。 + 406 406 ; line 68 : break; + 407 407 ; line 69 : } + 408 408 ; line 70 : } + 409 409 ; line 71 : */ + 410 410 ; line 72 : if( data == REG_BIT_TWL_RESET_REQ ) + 411 411 $DGL 0,38 + 412 412 0004C 67 mov a,h ;[INF] 1, 1 + 413 413 0004D 91 dec a ;[INF] 1, 1 + 414 414 0004E DF08 bnz $?L0013 ;[INF] 2, 4 + 415 415 ; line 73 : { + 416 416 00050 ??bb02_vreg_twl_write: + 417 417 ; line 74 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ ); + 418 418 ; //リセットしかない。他のは、SPIから来ます。 + 419 419 $DGL 0,40 + 420 420 00050 E6 onew ax ;[INF] 1, 1 + 421 421 00051 C1 push ax ;[INF] 1, 1 + 422 422 00052 5012 mov x,#012H ; 18 ;[INF] 2, 1 + 423 423 00054 RFD0000 call !_set_irq ;[INF] 3, 3 + 424 424 00057 C0 pop ax ;[INF] 1, 1 + 425 425 ; line 75 : break; + 426 426 00058 ??eb02_vreg_twl_write: + 427 427 ; line 76 : } + 428 428 00058 ?L0013: + 429 429 00058 ??eb00_vreg_twl_write: + 430 430 ; line 77 : } + 431 431 ; line 78 : return; + 432 432 ; line 79 : } + 433 433 $DGL 0,45 + 434 434 00058 ??ef_vreg_twl_write: + 435 435 00058 C6 pop hl ;[INF] 1, 1 + 436 436 00059 D7 ret ;[INF] 1, 6 + 437 437 0005A ??ee_vreg_twl_write: + 438 438 ; line 80 : + 439 439 ; line 81 : + 440 440 ; line 82 : + 441 441 ; line 83 : // ======================================================== + 442 442 ; line 84 : // I2C仮想レジスタから読みます。 + 443 443 ; line 85 : //　引数 adrs 外から見たときの、アドレス + 444 444 ; line 86 : //　戻り xx データ + 445 445 ; line 87 : // 　存在しないアドレスにアクセスした場合、戻り値は0x5A + 446 446 ; line 88 : u8 vreg_twl_read( u8 phy_adrs ) + 447 447 ; line 89 : { + 448 448 0005A _vreg_twl_read: + 449 449 $DGL 1,51 + 450 450 0005A C7 push hl ;[INF] 1, 1 + 451 451 0005B 16 movw hl,ax ;[INF] 1, 1 + 452 452 0005C ??bf_vreg_twl_read: + 453 453 ; line 90 : u8 temp; + 454 454 ; line 91 : + 455 455 ; line 92 : switch( phy_adrs ){ + 456 456 $DGL 0,4 + 457 457 0005C 17 movw ax,hl ;[INF] 1, 1 + 458 458 0005D F1 clrb a ;[INF] 1, 1 + 459 459 0005E E7 onew bc ;[INF] 1, 1 + 460 460 0005F 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 461 461 00062 DD0F bz $?L0018 ;[INF] 2, 4 + 462 462 00064 23 subw ax,bc ;[INF] 1, 1 + 463 463 00065 DD61 bz $?L0020 ;[INF] 2, 4 + 464 464 00067 240300 subw ax,#03H ; 3 ;[INF] 3, 1 + 465 465 0006A DD0C bz $?L0019 ;[INF] 2, 4 + 466 466 0006C 24FB00 subw ax,#0FBH ; 251 ;[INF] 3, 1 + 467 467 0006F DD6C bz $?L0022 ;[INF] 2, 4 + 468 468 00071 EF60 br $?L0021 ;[INF] 2, 3 + 469 469 00073 ??bb00_vreg_twl_read: + 470 470 ; line 93 : case( REG_TWL_INT_ADRS_VER_INFO ): + 471 471 00073 ?L0018: + 472 472 ; line 94 : return( TWL_REG_VER_INFO ); + 473 473 $DGL 0,6 + 474 474 00073 323500 movw bc,#035H ; 53 ;[INF] 3, 1 + 475 475 00076 EF66 br $?L0017 ;[INF] 2, 3 + 476 476 ; line 95 : + 477 477 ; line 96 : case( REG_TWL_INT_ADRS_POWER_INFO ): + 478 478 00078 ?L0019: + 479 479 ; line 97 : if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){ + 480 480 $DGL 0,9 + 481 481 00078 R400B005B cmp !_vreg_ctr+11,#05BH ; 91 ;[INF] 4, 1 + 482 482 0007C DC06 bc $?L0025 ;[INF] 2, 4 + 483 483 0007E ??bb01_vreg_twl_read: + 484 484 ; line 98 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F; + 485 485 $DGL 0,10 + 486 486 0007E RCF04000F mov !_vreg_twl+4,#0FH ; 15 ;[INF] 4, 1 + 487 487 00082 ??eb01_vreg_twl_read: + 488 488 ; line 99 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){ + 489 489 $DGL 0,11 + 490 490 00082 EF32 br $?L0034 ;[INF] 2, 3 + 491 491 00084 ?L0025: + 492 492 00084 R400B004C cmp !_vreg_ctr+11,#04CH ; 76 ;[INF] 4, 1 + 493 493 00088 DC06 bc $?L0027 ;[INF] 2, 4 + 494 494 0008A ??bb02_vreg_twl_read: + 495 495 ; line 100 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B; + 496 496 $DGL 0,12 + 497 497 0008A RCF04000B mov !_vreg_twl+4,#0BH ; 11 ;[INF] 4, 1 + 498 498 0008E ??eb02_vreg_twl_read: + 499 499 ; line 101 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){ + 500 500 $DGL 0,13 + 501 501 0008E EF26 br $?L0034 ;[INF] 2, 3 + 502 502 00090 ?L0027: + 503 503 00090 R400B0033 cmp !_vreg_ctr+11,#033H ; 51 ;[INF] 4, 1 + 504 504 00094 DC06 bc $?L0029 ;[INF] 2, 4 + 505 505 00096 ??bb03_vreg_twl_read: + 506 506 ; line 102 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07; + 507 507 $DGL 0,14 + 508 508 00096 RCF040007 mov !_vreg_twl+4,#07H ; 7 ;[INF] 4, 1 + 509 509 0009A ??eb03_vreg_twl_read: + 510 510 ; line 103 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){ + 511 511 $DGL 0,15 + 512 512 0009A EF1A br $?L0034 ;[INF] 2, 3 + 513 513 0009C ?L0029: + 514 514 0009C R400B001A cmp !_vreg_ctr+11,#01AH ; 26 ;[INF] 4, 1 + 515 515 000A0 DC06 bc $?L0031 ;[INF] 2, 4 + 516 516 000A2 ??bb04_vreg_twl_read: + 517 517 ; line 104 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03; + 518 518 $DGL 0,16 + 519 519 000A2 RCF040003 mov !_vreg_twl+4,#03H ; 3 ;[INF] 4, 1 + 520 520 000A6 ??eb04_vreg_twl_read: + 521 521 ; line 105 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 5 ){ + 522 522 $DGL 0,17 + 523 523 000A6 EF0E br $?L0034 ;[INF] 2, 3 + 524 524 000A8 ?L0031: + 525 525 000A8 R400B0006 cmp !_vreg_ctr+11,#06H ; 6 ;[INF] 4, 1 + 526 526 000AC DC05 bc $?L0033 ;[INF] 2, 4 + 527 527 000AE ??bb05_vreg_twl_read: + 528 528 ; line 106 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01; + 529 529 $DGL 0,18 + 530 530 000AE RE50400 oneb !_vreg_twl+4 ;[INF] 3, 1 + 531 531 000B1 ??eb05_vreg_twl_read: + 532 532 ; line 107 : }else{ + 533 533 $DGL 0,19 + 534 534 000B1 EF03 br $?L0034 ;[INF] 2, 3 + 535 535 000B3 ?L0033: + 536 536 000B3 ??bb06_vreg_twl_read: + 537 537 ; line 108 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00; + 538 538 $DGL 0,20 + 539 539 000B3 RF50400 clrb !_vreg_twl+4 ;[INF] 3, 1 + 540 540 000B6 ??eb06_vreg_twl_read: + 541 541 ; line 109 : } + 542 542 000B6 ?L0034: + 543 543 ; line 110 : + 544 544 ; line 111 : return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !B + 545 545 ; T_CHG_n ? 0x80: 0x00 ) ); // アダプタbit + 546 546 $DGL 0,23 + 547 547 000B6 31120505 bt P5.1,$?L0035 ;[INF] 4, 5 + 548 548 000BA 308000 movw ax,#080H ; 128 ;[INF] 3, 1 + 549 549 000BD EF01 br $?L0036 ;[INF] 2, 3 + 550 550 000BF ?L0035: + 551 551 000BF F6 clrw ax ;[INF] 1, 1 + 552 552 000C0 ?L0036: + 553 553 000C0 08 xch a,x ;[INF] 1, 1 + 554 554 000C1 R6F0400 or a,!_vreg_twl+4 ;[INF] 3, 1 + 555 555 000C4 08 xch a,x ;[INF] 1, 1 + 556 556 000C5 12 movw bc,ax ;[INF] 1, 1 + 557 557 000C6 EF16 br $?L0017 ;[INF] 2, 3 + 558 558 ; line 112 : + 559 559 ; line 113 : case( REG_TWL_INT_ADRS_IRQ ): + 560 560 000C8 ?L0020: + 561 561 ; line 114 : temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ]; + 562 562 $DGL 0,26 + 563 563 000C8 R8F0100 mov a,!_vreg_twl+1 ;[INF] 3, 1 + 564 564 ; line 115 : vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0; + 565 565 $DGL 0,27 + 566 566 000CB RF50100 clrb !_vreg_twl+1 ;[INF] 3, 1 + 567 567 ; line 116 : return( temp ); + 568 568 $DGL 0,28 + 569 569 000CE 318E shrw ax,8 ;[INF] 2, 1 + 570 570 000D0 12 movw bc,ax ;[INF] 1, 1 + 571 571 000D1 EF0B br $?L0017 ;[INF] 2, 3 + 572 572 ; line 117 : + 573 573 ; line 118 : default: + 574 574 000D3 ?L0021: + 575 575 ; line 119 : return( vreg_twl[ phy_adrs ] ); + 576 576 $DGL 0,31 + 577 577 000D3 66 mov a,l ;[INF] 1, 1 + 578 578 000D4 73 mov b,a ;[INF] 1, 1 + 579 579 000D5 R090000 mov a,_vreg_twl[b] ;[INF] 3, 1 + 580 580 000D8 318E shrw ax,8 ;[INF] 2, 1 + 581 581 000DA 12 movw bc,ax ;[INF] 1, 1 + 582 582 000DB EF01 br $?L0017 ;[INF] 2, 3 + 583 583 ; line 120 : + 584 584 ; line 121 : case( REG_TWL_ADRS_NON_EXIST ): + 585 585 000DD ?L0022: + 586 586 ; line 122 : return( 0x00 ); + 587 587 $DGL 0,34 + 588 588 000DD F7 clrw bc ;[INF] 1, 1 + 589 589 000DE ??eb00_vreg_twl_read: + 590 590 ; line 123 : } + 591 591 000DE ?L0017: + 592 592 ; line 124 : } + 593 593 $DGL 0,36 + 594 594 000DE ??ef_vreg_twl_read: + 595 595 000DE C6 pop hl ;[INF] 1, 1 + 596 596 000DF D7 ret ;[INF] 1, 6 + 597 597 000E0 ??ee_vreg_twl_read: + 598 598 ; line 125 : + 599 599 ; line 126 : + 600 600 ; line 127 : + 601 601 ; line 128 : // ======================================================== + 602 602 ; line 129 : // 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える + 603 603 ; line 130 : // 0xFFは存在しないアドレス。 + 604 604 ; line 131 : u8 adrs_table_twl_ext2int( u8 img ) + 605 605 ; line 132 : { + 606 606 000E0 _adrs_table_twl_ext2int: + 607 607 $DGL 1,87 + 608 608 000E0 C7 push hl ;[INF] 1, 1 + 609 609 000E1 16 movw hl,ax ;[INF] 1, 1 + 610 610 000E2 ??bf_adrs_table_twl_ext2int: + 611 611 ; line 133 : switch( img ){ + 612 612 $DGL 0,2 + 613 613 000E2 17 movw ax,hl ;[INF] 1, 1 + 614 614 000E3 F1 clrb a ;[INF] 1, 1 + 615 615 000E4 E7 onew bc ;[INF] 1, 1 + 616 616 000E5 240000 subw ax,#00H ; 0 ;[INF] 3, 1 + 617 617 000E8 DD3C bz $?L0046 ;[INF] 2, 4 + 618 618 000EA 241000 subw ax,#010H ; 16 ;[INF] 3, 1 + 619 619 000ED DD1C bz $?L0040 ;[INF] 2, 4 + 620 620 000EF 23 subw ax,bc ;[INF] 1, 1 + 621 621 000F0 DD1C bz $?L0041 ;[INF] 2, 4 + 622 622 000F2 23 subw ax,bc ;[INF] 1, 1 + 623 623 000F3 DD34 bz $?L0047 ;[INF] 2, 4 + 624 624 000F5 240E00 subw ax,#0EH ; 14 ;[INF] 3, 1 + 625 625 000F8 DD18 bz $?L0042 ;[INF] 2, 4 + 626 626 000FA 241100 subw ax,#011H ; 17 ;[INF] 3, 1 + 627 627 000FD DD18 bz $?L0043 ;[INF] 2, 4 + 628 628 000FF 240F00 subw ax,#0FH ; 15 ;[INF] 3, 1 + 629 629 00102 DD18 bz $?L0044 ;[INF] 2, 4 + 630 630 00104 243000 subw ax,#030H ; 48 ;[INF] 3, 1 + 631 631 00107 DD18 bz $?L0045 ;[INF] 2, 4 + 632 632 00109 EF23 br $?L0048 ;[INF] 2, 3 + 633 633 0010B ??bb00_adrs_table_twl_ext2int: + 634 634 ; line 134 : case( REG_TWL_ADRS_IRQ ): return( REG_TWL_INT_ADRS_ + 635 635 ; IRQ ); + 636 636 $DGL 0,3 + 637 637 0010B ?L0040: + 638 638 0010B E7 onew bc ;[INF] 1, 1 + 639 639 0010C EF22 br $?L0039 ;[INF] 2, 3 + 640 640 ; line 135 : case( REG_TWL_ADRS_COMMAND ): return( REG_TWL_INT_ADRS_ + 641 641 ; COMMAND ); + 642 642 $DGL 0,4 + 643 643 0010E ?L0041: + 644 644 0010E E7 onew bc ;[INF] 1, 1 + 645 645 0010F A3 incw bc ;[INF] 1, 1 + 646 646 00110 EF1E br $?L0039 ;[INF] 2, 3 + 647 647 ; line 136 : case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_ + 648 648 ; POWER_INFO ); + 649 649 $DGL 0,5 + 650 650 00112 ?L0042: + 651 651 00112 320400 movw bc,#04H ; 4 ;[INF] 3, 1 + 652 652 00115 EF19 br $?L0039 ;[INF] 2, 3 + 653 653 ; line 137 : case( REG_TWL_ADRS_CAM ): return( REG_TWL_INT_ADRS_ + 654 654 ; CAM ); + 655 655 $DGL 0,6 + 656 656 00117 ?L0043: + 657 657 00117 320500 movw bc,#05H ; 5 ;[INF] 3, 1 + 658 658 0011A EF14 br $?L0039 ;[INF] 2, 3 + 659 659 ; line 138 : case( REG_TWL_ADRS_VOL ): return( REG_TWL_INT_ADRS_ + 660 660 ; VOL ); + 661 661 $DGL 0,7 + 662 662 0011C ?L0044: + 663 663 0011C 320600 movw bc,#06H ; 6 ;[INF] 3, 1 + 664 664 0011F EF0F br $?L0039 ;[INF] 2, 3 + 665 665 ; line 139 : case( REG_TWL_ADRS_TEMP0 ): return( REG_TWL_INT_ADRS_ + 666 666 ; TEMP0 ); + 667 667 $DGL 0,8 + 668 668 00121 ?L0045: + 669 669 00121 320700 movw bc,#07H ; 7 ;[INF] 3, 1 + 670 670 00124 EF0A br $?L0039 ;[INF] 2, 3 + 671 671 ; line 140 : case( REG_TWL_ADRS_VER_INFO ): return( REG_TWL_INT_ADRS_ + 672 672 ; VER_INFO ); + 673 673 $DGL 0,9 + 674 674 00126 ?L0046: + 675 675 00126 F7 clrw bc ;[INF] 1, 1 + 676 676 00127 EF07 br $?L0039 ;[INF] 2, 3 + 677 677 ; line 141 : case( REG_TWL_ADRS_MODE ): return( REG_TWL_INT_ADRS_ + 678 678 ; MODE ); + 679 679 $DGL 0,10 + 680 680 00129 ?L0047: + 681 681 00129 320300 movw bc,#03H ; 3 ;[INF] 3, 1 + 682 682 0012C EF02 br $?L0039 ;[INF] 2, 3 + 683 683 ; line 142 : default: return( REG_TWL_ADRS_NON_ + 684 684 ; EXIST ); + 685 685 $DGL 0,11 + 686 686 0012E ?L0048: + 687 687 0012E F7 clrw bc ;[INF] 1, 1 + 688 688 0012F 92 dec c ;[INF] 1, 1 + 689 689 00130 ??eb00_adrs_table_twl_ext2int: + 690 690 ; line 143 : // 0が読めればよい、書けなくて良い + 691 691 ; line 144 : // case( REG_TWL_ADRS_WIFI ): return( REG_TWL_INT_ADR + 692 692 ; S_WIFI ); + 693 693 ; line 145 : } + 694 694 00130 ?L0039: + 695 695 ; line 146 : } + 696 696 $DGL 0,15 + 697 697 00130 ??ef_adrs_table_twl_ext2int: + 698 698 00130 C6 pop hl ;[INF] 1, 1 + 699 699 00131 D7 ret ;[INF] 1, 6 + 700 700 00132 ??ee_adrs_table_twl_ext2int: + 701 701 + 702 702 ----- @@CODEL CSEG + 703 703 + 704 704 ----- @@BASE CSEG BASE + 705 705 END + 706 706 + 707 707 + 708 708 ; *** Code Information *** + 709 709 ; + 710 710 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c + 711 711 ; + 712 712 ; $FUNC vreg_twl_init(25) + 713 713 ; void=(void) + 714 714 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes + 715 715 ; + 716 716 ; $FUNC vreg_twl_write(35) + 717 717 ; void=(unsigned char adrs:x, unsigned char data:[sp+6]) + 718 718 ; CODE SIZE= 74 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 8 bytes + 719 719 ; + 720 720 ; $CALL set_irq(40) + 721 721 ; void=(int:ax, int:[sp+4]) + 722 722 ; + 723 723 ; $CALL tsk_led_cam(50) + 724 724 ; void=(void) + 725 725 ; + 726 726 ; $CALL set_irq(74) + 727 727 ; void=(int:ax, int:[sp+4]) + 728 728 ; + 729 729 ; $FUNC vreg_twl_read(89) + 730 730 ; bc=(unsigned char phy_adrs:x) + 731 731 ; CODE SIZE= 134 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 2 bytes + 732 732 ; + 733 733 ; $FUNC adrs_table_twl_ext2int(132) + 734 734 ; bc=(unsigned char img:x) + 735 735 ; CODE SIZE= 82 bytes, CLOCK_SIZE= 90 clocks, STACK_SIZE= 2 bytes + 736 736 + 737 737 ; Target chip : uPD79F0104 + 738 738 ; Device file : E1.00b + +Segment informations: + +ADRS LEN NAME + +00000 00000H.0 @@BITS +00000 00030H @@CNST +00000 00016H @@R_INIT +00000 00016H @@INIT +00000 00010H @@DATA +00000 00000H @@R_INIS +00000 00000H @@INIS +00000 00000H @@DATS +00000 00000H @@CNSTL +00000 00000H @@RLINIT +00000 00000H @@INITL +00000 00000H @@DATAL +00000 00000H @@CALT +00000 00132H ROM_CODE +00000 00000H @@CODEL +00000 00000H @@BASE + + Target chip : uPD79F0104 + Device file : E1.00b +Assembly complete, 0 error(s) and 0 warning(s) found. ( 0) + \ No newline at end of file diff --git a/branches/0.10(X3)/vreg_twl.rel b/branches/0.10(X3)/vreg_twl.rel new file mode 100644 index 0000000..e90a1b4 Binary files /dev/null and b/branches/0.10(X3)/vreg_twl.rel differ diff --git a/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.ncb b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.ncb new file mode 100644 index 0000000..472fc0f Binary files /dev/null and b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.ncb differ diff --git a/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.sln b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.sln new file mode 100644 index 0000000..12875bf --- /dev/null +++ b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.sln @@ -0,0 +1,20 @@ +ｻｿ +Microsoft Visual Studio Solution File, Format Version 10.00 +# Visual C++ Express 2008 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "yav-mcu-basara_sdk0.9", "yav-mcu-basara_sdk0.9\yav-mcu-basara_sdk0.9.vcproj", "{266AA0C8-5E7F-431C-B1C8-C77746E8CE8A}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {266AA0C8-5E7F-431C-B1C8-C77746E8CE8A}.Debug|Win32.ActiveCfg = Debug|Win32 + {266AA0C8-5E7F-431C-B1C8-C77746E8CE8A}.Debug|Win32.Build.0 = Debug|Win32 + {266AA0C8-5E7F-431C-B1C8-C77746E8CE8A}.Release|Win32.ActiveCfg = Release|Win32 + {266AA0C8-5E7F-431C-B1C8-C77746E8CE8A}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.suo b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.suo new file mode 100644 index 0000000..2df9b06 Binary files /dev/null and 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b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/Debug/vc90.pdb differ diff --git a/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj new file mode 100644 index 0000000..8f6d1ab --- /dev/null +++ b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj @@ -0,0 +1,373 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj.NCL.N2232.user b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj.NCL.N2232.user new file mode 100644 index 0000000..c409164 --- /dev/null +++ b/branches/0.10(X3)/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9/yav-mcu-basara_sdk0.9.vcproj.NCL.N2232.user @@ -0,0 +1,65 @@ + + + + + + + + + + + diff --git a/branches/0.10(X3)/yav_mcu_bsr.fni b/branches/0.10(X3)/yav_mcu_bsr.fni new file mode 100644 index 0000000..869fed8 --- /dev/null +++ b/branches/0.10(X3)/yav_mcu_bsr.fni @@ -0,0 +1,169 @@ +[SrcFileName] +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,1273731530 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\magic.c,1276425107 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,1276424581 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c,1273731530 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\ini_VECT.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,1273731530 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,1273731530 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c,1273731531 +C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,1273731531 + +[Function] +main,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,68 +int_kr,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,139 +intp4,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,148 +intp5,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,156 +hdwinit,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,163 +hdwinit2,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c,187 +PM_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,45 +PM_bt_temp_update,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,162 +PM_LCD_on,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,226 +PM_LCD_off,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,264 +PM_BL_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,313 +PM_LCD_vcom_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,394 +PM_LCD_on,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,408 +PM_LCD_off,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,417 +PM_BL_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,425 +PM_LCD_vcom_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,436 +tski_vcom_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,449 +PM_sys_pow_on,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,465 +PM_sys_pow_off,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,582 +tsk_batt,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,636 +intp4_extdc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,723 +intp5_shell,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,734 +intp6_PM_irq,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,743 +ntr_pmic_comm,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,759 +PM_get_batt_left,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,868 +tski_PM_LCD_on,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,903 +tski_PM_LCD_off,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,909 +tski_PM_BL_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.c,915 +int_iic_ctr,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c,64 +IIC_ctr_Init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c,205 +IIC_ctr_Stop,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c,254 +main_loop,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c,32 +read_dipsw,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c,94 +WDT_Restart,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c,11 +nop8,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,75 +iic_mcu_read_a_byte,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,86 +iic_mcu_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,157 +iic_mcu_write_a_byte,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,241 +iic_mcu_write,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,296 +int_dma1,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.c,387 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+tsk_led_pow,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,119 +led_pow_normal,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,173 +led_pow_hotaru,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,228 +tsk_led_wifi,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,315 +tsk_led_notify,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,400 +tsk_led_cam,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.c,519 +RTC_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,22 +int_rtc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,71 +rtc_buf_reflesh,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,98 +set_rtc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,122 +rtc_unlock,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,139 +int_rtc_int,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c,177 +vreg_ctr_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,41 +vreg_ctr_write,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,65 +vreg_ctr_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,304 +vreg_ctr_after_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,352 +set_irq,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.c,393 +vreg_twl_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c,24 +vreg_twl_write,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c,34 +vreg_twl_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c,88 +adrs_table_twl_ext2int,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c,131 +tsk_adc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c,60 +getmean3,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c,227 +int_adc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c,257 +get_adc,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.c,327 +renge_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,53 +renge_task_interval_run,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,81 +renge_task_immed_init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,117 +renge_task_immed_add,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,131 +renge_task_immed_run,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,176 +wait_ms,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.c,343 +tsk_cbk_accero,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,65 +acc_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,122 +acc_write,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,139 +acc_hosu_set,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,157 +intp23_ACC_ready,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c,236 +firm_update,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,96 +firm_restore,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,226 +FSL_Open,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,251 +FSL_Close,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,286 +firm_duplicate,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,311 +my_FSL_Init,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,376 +tski_mcu_reset,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\self_flash.c,391 +my_reboot,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c,14 +tsk_sw,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c,55 +tsk_debug,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c,15 +tsk_debug2,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c,42 +tsk_hina,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c,80 +tsk_imm_hina,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c,101 +tsk_misc_stat,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c,54 +do_command0,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c,158 +tski_mcu_info_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_misc.c,216 +tsk_sys,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c,34 +chk_emergencyExit,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c,323 +tski_firm_update,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c,385 +pedometer,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,29 +hosu_increment,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,182 +fill_hosu_hist_hours,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,263 +clear_hosu_hist,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,286 +hosu_read_end,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,309 +hosu_read,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,319 +get_long_hour,C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedo_alg_thre_det2.c,380 + diff --git a/branches/0.10(X3)/yav_mcu_bsr.mak b/branches/0.10(X3)/yav_mcu_bsr.mak new file mode 100644 index 0000000..e8228fe --- /dev/null +++ b/branches/0.10(X3)/yav_mcu_bsr.mak @@ -0,0 +1,590 @@ +# +# Project manager generated MAKEFILE +# +TITLE = yav-mcu +DEVFILE = C:\Program Files\NEC Electronics Tools\DEV\D9F0104.78K +PROJDIR = C:\78k_data\yav-mcu-basara\branches\0.10(fix) +TOOLDIR = C:\Program Files\NEC Electronics Tools\PM+\V6.31\bin +WORKDIR = C:\78k_data\yav-mcu-basara\branches\0.10(fix) +DEBUG = + +CC = "C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\bin\cc78k0r.exe" +RA = "C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\ra78k0r.exe" +LK = "C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\lk78k0r.exe" +OC = "C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\oc78k0r.exe" +LCNV = "C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\lc78k0r.exe" + +OBJS = loader.rel \ + pm.rel \ + i2c_ctr.rel \ + main.rel \ + magic.rel \ + WDT.rel \ + i2c_mcu.rel \ + i2c_twl.rel \ + ini_VECT.rel \ + led.rel \ + rtc.rel \ + vreg_ctr.rel \ + vreg_twl.rel \ + adc.rel \ + renge.rel \ + accero.rel \ + self_flash.rel \ + reboot.rel \ + sw.rel \ + task_debug.rel \ + task_misc.rel \ + task_sys.rel \ + pedo_alg_thre_det2.rel + +DEP_loader_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs_loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\fsl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\fsl_user.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.h + +DEP_pm_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\batt_params.h \ + "C:\78k_data\yav-mcu-basara\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r\fsl.h" \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\fsl_user.h + +DEP_i2c_ctr_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h + +DEP_main_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs_loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.h + +DEP_magic_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h + +DEP_WDT_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs_loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h + +DEP_i2c_mcu_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h + +DEP_i2c_twl_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl_defs.h + +DEP_ini_VECT_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h + +DEP_led_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h + +DEP_rtc_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h + +DEP_vreg_ctr_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + "C:\78k_data\yav-mcu-basara\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r\fsl.h" \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\fsl_user.h + +DEP_vreg_twl_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_intval.h + +DEP_adc_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h + +DEP_renge_renge_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_intval.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h + +DEP_accero_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + "C:\78k_data\yav-mcu-basara\Program Files\NEC Electronics Tools\CC78K0R\W2.10\inc78k0r\math.h" + +DEP_self_flash_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs_loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h \ + "C:\78k_data\yav-mcu-basara\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r\fsl.h" \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\fsl_user.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.h + +DEP_reboot_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs_loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.h + +DEP_sw_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h + +DEP_task_debug_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h + +DEP_task_misc_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.h + +DEP_task_sys_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\led.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pm.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\adc.h + +DEP_pedo_alg_thre_det2_c = C:\78k_data\yav-mcu-basara\branches\0.10(fix)\incs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\jhl_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\config.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\user_define.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr_system.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_defs.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\renge\renge_task_immediate.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_ctr.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_mcu.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.h \ + C:\78k_data\yav-mcu-basara\branches\0.10(fix)\pedometer.h \ + "C:\78k_data\yav-mcu-basara\Program Files\NEC Electronics Tools\CC78K0R\W2.10\inc78k0r\math.h" + +GOAL : C:\78k_data\yav-mcu-basara\branches\0.10(fix)\bsr.hex + +BeforeBuild: #ビルド前の処理(疑似ターゲット) + C:\WINDOWS\system32\cmd.exe /c touch magic.c +inter_asm\loader.asm : loader.c $(DEP_loader_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no loader.c + +loader.rel : inter_asm\loader.asm $(DEP_loader_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\loader.asm + +inter_asm\pm.asm : pm.c $(DEP_pm_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no pm.c + +pm.rel : inter_asm\pm.asm $(DEP_pm_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\pm.asm + +inter_asm\i2c_ctr.asm : i2c_ctr.c $(DEP_i2c_ctr_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c + +i2c_ctr.rel : inter_asm\i2c_ctr.asm $(DEP_i2c_ctr_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\i2c_ctr.asm + +inter_asm\main.asm : main.c $(DEP_main_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no main.c + +main.rel : inter_asm\main.asm $(DEP_main_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\main.asm + +inter_asm\magic.asm : magic.c $(DEP_magic_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no magic.c + +magic.rel : inter_asm\magic.asm $(DEP_magic_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\magic.asm + +inter_asm\WDT.asm : WDT.c $(DEP_WDT_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no WDT.c + +WDT.rel : inter_asm\WDT.asm $(DEP_WDT_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\WDT.asm + +inter_asm\i2c_mcu.asm : i2c_mcu.c $(DEP_i2c_mcu_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no i2c_mcu.c + +i2c_mcu.rel : inter_asm\i2c_mcu.asm $(DEP_i2c_mcu_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\i2c_mcu.asm + +inter_asm\i2c_twl.asm : i2c_twl.c $(DEP_i2c_twl_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c + +i2c_twl.rel : inter_asm\i2c_twl.asm $(DEP_i2c_twl_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\i2c_twl.asm + +inter_asm\ini_VECT.asm : ini_VECT.c $(DEP_ini_VECT_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no ini_VECT.c + +ini_VECT.rel : inter_asm\ini_VECT.asm $(DEP_ini_VECT_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\ini_VECT.asm + +inter_asm\led.asm : led.c $(DEP_led_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no led.c + +led.rel : inter_asm\led.asm $(DEP_led_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\led.asm + +inter_asm\rtc.asm : rtc.c $(DEP_rtc_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no rtc.c + +rtc.rel : inter_asm\rtc.asm $(DEP_rtc_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\rtc.asm + +inter_asm\vreg_ctr.asm : vreg_ctr.c $(DEP_vreg_ctr_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no vreg_ctr.c + +vreg_ctr.rel : inter_asm\vreg_ctr.asm $(DEP_vreg_ctr_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\vreg_ctr.asm + +inter_asm\vreg_twl.asm : vreg_twl.c $(DEP_vreg_twl_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c + +vreg_twl.rel : inter_asm\vreg_twl.asm $(DEP_vreg_twl_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\vreg_twl.asm + +inter_asm\adc.asm : adc.c $(DEP_adc_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no adc.c + +adc.rel : inter_asm\adc.asm $(DEP_adc_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\adc.asm + +inter_asm\renge.asm : renge\renge.c $(DEP_renge_renge_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no renge\renge.c + +renge.rel : inter_asm\renge.asm $(DEP_renge_renge_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\renge.asm + +inter_asm\accero.asm : accero.c $(DEP_accero_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no accero.c + +accero.rel : inter_asm\accero.asm $(DEP_accero_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\accero.asm + +inter_asm\self_flash.asm : self_flash.c $(DEP_self_flash_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no self_flash.c + +self_flash.rel : inter_asm\self_flash.asm $(DEP_self_flash_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\self_flash.asm + +inter_asm\reboot.asm : reboot.c $(DEP_reboot_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no reboot.c + +reboot.rel : inter_asm\reboot.asm $(DEP_reboot_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\reboot.asm + +inter_asm\sw.asm : sw.c $(DEP_sw_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no sw.c + +sw.rel : inter_asm\sw.asm $(DEP_sw_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\sw.asm + +inter_asm\task_debug.asm : task_debug.c $(DEP_task_debug_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no task_debug.c + +task_debug.rel : inter_asm\task_debug.asm $(DEP_task_debug_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\task_debug.asm + +inter_asm\task_misc.asm : task_misc.c $(DEP_task_misc_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no task_misc.c + +task_misc.rel : inter_asm\task_misc.asm $(DEP_task_misc_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\task_misc.asm + +inter_asm\task_sys.asm : task_sys.c $(DEP_task_sys_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no task_sys.c + +task_sys.rel : inter_asm\task_sys.asm $(DEP_task_sys_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\task_sys.asm + +inter_asm\pedo_alg_thre_det2.asm : pedo_alg_thre_det2.c $(DEP_pedo_alg_thre_det2_c) + $(CC) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no pedo_alg_thre_det2.c + +pedo_alg_thre_det2.rel : inter_asm\pedo_alg_thre_det2.asm $(DEP_pedo_alg_thre_det2_c) + $(RA) -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\pedo_alg_thre_det2.asm + +bsr.lmf : $(OBJS) + $(LK) -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -obsr.lmf "..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r\s0rm.rel" -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFFFFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -b"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib" -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i"C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r" -dbsr_mcu.dr -s -w0 loader.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot.rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg_thre_det2.rel + +bsr.hex : bsr.lmf + $(OC) -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -o.\bsr.hex -nu -ki bsr.lmf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +AfterBuild: #ビルド後の処理(疑似ターゲット) + C:\WINDOWS\system32\cmd.exe /c ruby nec_s_2_bsrbin2.rb bsr.hex diff --git a/branches/0.10(X3)/yav_mcu_bsr.plg b/branches/0.10(X3)/yav_mcu_bsr.plg new file mode 100644 index 0000000..d261d28 --- /dev/null +++ b/branches/0.10(X3)/yav_mcu_bsr.plg @@ -0,0 +1,16 @@ +C:\WINDOWS\system32\cmd.exe /c touch magic.c +"C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\bin\cc78k0r.exe" -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -irenge -i"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r" -ms -qvjl3wt -sainter_asm -zp -no magic.c +Compilation complete, 0 error(s) and 0 warning(s) found. +"C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\ra78k0r.exe" -c9F0104 -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff inter_asm\magic.asm +Assembly complete, 0 error(s) and 0 warning(s) found. +"C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\lk78k0r.exe" -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -obsr.lmf "..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r\s0rm.rel" -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFFFFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -b"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib" -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i"C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r" -dbsr_mcu.dr -s -w0 loader.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot.rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg_thre_det2.rel +Link complete, 0 error(s) and 0 warning(s) found. +"C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\oc78k0r.exe" -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -o.\bsr.hex -nu -ki bsr.lmf +Object Conversion Complete, 0 error(s) and 0 warning(s) found. +C:\WINDOWS\system32\cmd.exe /c ruby nec_s_2_bsrbin2.rb bsr.hex +nec_s_2_bsrbin2.rb:2: warning: variable $KCODE is no longer effective; ignored +intel-HEX to bsr bin converter + file converted! + + +Build Total error(s) : 0 Total warning(s) : 0 diff --git a/branches/0.10(X3)/yav_mcu_bsr.pri b/branches/0.10(X3)/yav_mcu_bsr.pri new file mode 100644 index 0000000..f844e44 --- /dev/null +++ b/branches/0.10(X3)/yav_mcu_bsr.pri @@ -0,0 +1,1018 @@ +[Project.ID] +Ver=200 +Target=IDK0R32G +[Configuration] +Chip=uPD79F0104 +Internal Rom=32KB +Internal Ram=1536B +Clock=Target +Sub Clock=Target +Peripheral Break=0x3 +Firm Clock=System +Flash Programming=Permit +Low-voltage Flash Rewriting=On +Fail Safe Break=0x2000 +Port=1 +NMI=OFF +TRESET=ON +IRESET=OFF +WAIT=OFF +SysClock=None +SubClock=None +[Mapping] +Count=0 +[Main] +Geometry=-1174, 31, 1219, 1099 +Window=Normal +MDI_MAX=OFF +Button=ON +Mode=Auto +Trace=Uncond ON +Trace2=Non Stop +Coverage=OFF +Timer=OFF +Tracer=OFF +[Load File] +Dir=..\yav-mcu-basara\ +SaveFilter=0 +Start=0xffF00 +End=0xfffff +LoadFilter=5 +Offset=0 +Object=ON +Symbol=ON +Erase=OFF +HighSpeed=OFF +Symbol Reset=ON +CPU Reset=ON +File1=bsr.lmf +LoadFilter1=5 +Offset1=0 +Object1=ON +Symbol1=ON +Erase1=ON +HighSpeed1=OFF +CPU Reset1=ON +Symbol Reset1=ON +[View File] +Dir=..\yav-mcu-basara\ +Filter=Source +[Debugger Option] +Source Path=".;renge" +Symbol Size=Byte +Symbol Format=Hex +Register Name=Func +Offset Label=OFF +Offset Mnemonic=ON +Tab Count=4 +Tab Size1=*.*, 8 +Tab Size2=*.c, 8 +Tab Size3=*.s, 8 +Tab Size4=*.asm, 8 +Default Source=*.c;*.s;*.asm +Default Module=*.lnk;*.lmf +Startup Start=_@cstart +Startup End=_@cend +Main Symbol=_main +Symbol Type=OFF +Language=C +Kanji=SJIS +[Source] +Geometry=48, 22, 707, 899 +Window=Normal +DispStart=68 +CaretPos=69,0 +Mode=Normal +DispFile= +Address1= +Address2= +Address3= +Address4= +Address5= +Address6= +Address7= +Address8= +Address9= +Address10= +Address11= +Address12= +Address13= +Address14= +Address15= +Address16= +Data1=iic_mcu_initialized +Data2= +Data3= +Data4= +Data5= +Data6= +Data7= +Data8= +Data9= +Data10= +Data11= +Data12= +Data13= +Data14= +Data15= +Data16= +Option=0 +Case=ON +Direction=Down +File1= +File2= +File3= +File4= +File5= +File6= +File7= +File8= +File9= +File10= +File11= +File12= +File13= +File14= +File15= +File16= +SaveRange=Screen +SaveStart= +SaveEnd= +Accumulative=ON +[Assemble] +Geometry=674, 20, 600, 400 +Window=Hide +DispStart=864505856 +CaretPos=0,0 +Address1= +Address2= +Address3= +Address4= +Address5= +Address6= +Address7= +Address8= +Address9= +Address10= +Address11= +Address12= +Address13= +Address14= +Address15= +Address16= +Data1= +Data2= +Data3= +Data4= +Data5= +Data6= +Data7= +Data8= +Data9= +Data10= +Data11= +Data12= +Data13= +Data14= +Data15= +Data16= +Case=ON +Scan=OFF +Direction=Down +FindStart=0 +FindEnd=0 +SaveRange=Screen +SaveStart= +SaveEnd= +[Memory] +Geometry=632, 59, 578, 791 +Window=Hide +Boundary=0 +Format=Hex +Mode=Byte +Endian= +Ascii=OFF +Idtag=OFF +Address= +DispStart=FFFFFFFF +CaretPosData=0, 0 +CaretPosAscii=0, 0 +Address1= +Address2= +Address3= +Address4= +Address5= +Address6= +Address7= +Address8= +Address9= +Address10= +Address11= +Address12= +Address13= +Address14= +Address15= +Address16= +Data1= +Data2= +Data3= +Data4= +Data5= +Data6= +Data7= +Data8= +Data9= +Data10= +Data11= +Data12= +Data13= +Data14= +Data15= +Data16= +Binary=ON +Scan=OFF +Direction=DOWN +FindStart= +FindEnd= +Unit=Byte +SaveRange=Screen +SaveStart= +SaveEnd= +Accumulative=ON +[Memory fill] +Scope=0, 0 +Code=0 +[Memory copy] +Scope=0, 0 +To=0 +[Memory compare] +Source=0, 0 +Destination=0 +[I/O Port] +Line=0 +[Stack] +Geometry=525, 527, 400, 399 +Window=Hide +Boundary=13762687 +Mode=Proper +[Sfr] +Geometry=0, 0, 396, 1089 +Window=Hide +Address1= +Address2= +Address3= +Address4= +Address5= +Address6= +Address7= +Address8= +Address9= +Address10= +Address11= +Address12= +Address13= +Address14= +Address15= +Address16= +Boundary=0, 0 +Mode=Hex +Attribute=Show +Sort=Unsort +Pickup=OFF +SelectSort=Address +Last Name=P0 +Line=531 +L1=P0 +L2=P1 +L3=P2 +L4=P3 +L5=P4 +L6=P5 +L7=P6 +L8=P7 +L9=P12 +L10=P14 +L11=P15 +L12=SDR00 +L13=SIO00 +L14=TXD0 +L15=SDR01 +L16=RXD0 +L17=SIO01 +L18=TDR00 +L19=TDR01 +L20=ADCRH +L21=PM0 +L22=PM1 +L23=PM2 +L24=PM3 +L25=PM4 +L26=PM5 +L27=PM6 +L28=PM7 +L29=PM12 +L30=PM14 +L31=PM15 +L32=ADM +L33=ADCE +L34=ADCS +L35=ADS +L36=KRM +L37=EGP0 +L38=EGN0 +L39=ISC +L40=TIS0 +L41=SDR02 +L42=SIO10 +L43=TXD1 +L44=SDR03 +L45=RXD1 +L46=IICA0 +L47=IICS0 +L48=SPD0 +L49=STD0 +L50=ACKD0 +L51=TRC0 +L52=COI0 +L53=EXC0 +L54=ALD0 +L55=MSTS0 +L56=IICF0 +L57=IICRSV0 +L58=STCEN0 +L59=IICBSY0 +L60=STCF0 +L61=TDR02 +L62=TDR03 +L63=TDR04 +L64=TDR05 +L65=TDR06 +L66=TDR07 +L67=RSUBC +L68=SEC +L69=MIN +L70=HOUR +L71=WEEK +L72=DAY +L73=MONTH +L74=YEAR +L75=SUBCUD +L76=ALARMWM +L77=ALARMWH +L78=ALARMWW +L79=RTCC0 +L80=RCLOE0 +L81=RCLOE1 +L82=RTCE +L83=RTCC1 +L84=RWAIT +L85=RWST +L86=RIFG +L87=WAFG +L88=WALIE +L89=WALE +L90=RTCC2 +L91=RCKDIV +L92=RCLOE2 +L93=RINTE +L94=CMC +L95=CSC +L96=HIOSTOP +L97=XTSTOP +L98=MSTOP +L99=OSTC +L100=OSTS +L101=CKC +L102=MCM0 +L103=MCS +L104=CSS +L105=CLS +L106=CKS0 +L107=PCLOE0 +L108=CKS1 +L109=PCLOE1 +L110=RESF +L111=LVIM +L112=LVIF +L113=LVIMD +L114=LVISEL +L115=LVION +L116=LVIS +L117=WDTE +L118=DSA0 +L119=DSA1 +L120=DRA0 +L121=DRA0L +L122=DRA0H +L123=DRA1 +L124=DRA1L +L125=DRA1H +L126=DBC0 +L127=DBC0L +L128=DBC0H +L129=DBC1 +L130=DBC1L +L131=DBC1H +L132=DMC0 +L133=DWAIT0 +L134=DS0 +L135=DRS0 +L136=STG0 +L137=DMC1 +L138=DWAIT1 +L139=DS1 +L140=DRS1 +L141=STG1 +L142=DRC0 +L143=DST0 +L144=DEN0 +L145=DRC1 +L146=DST1 +L147=DEN1 +L148=BECTL +L149=FLMDPUP +L150=PFCMD +L151=PFS +L152=FPRERR +L153=FLPMC +L154=BFAEN +L155=FWEPR +L156=BRAMEN +L157=IF2 +L158=IF2L +L159=TMIF05 +L160=TMIF06 +L161=TMIF07 +L162=PIF6 +L163=IF2H +L164=IICAIF1 +L165=PIF20 +L166=PIF21 +L167=PIF22 +L168=PIF23 +L169=MK2 +L170=MK2L +L171=TMMK05 +L172=TMMK06 +L173=TMMK07 +L174=PMK6 +L175=MK2H +L176=IICAMK1 +L177=PMK20 +L178=PMK21 +L179=PMK22 +L180=PMK23 +L181=PR02 +L182=PR02L +L183=TMPR005 +L184=TMPR006 +L185=TMPR007 +L186=PPR06 +L187=PR02H +L188=IICAPR01 +L189=PPR020 +L190=PPR021 +L191=PPR022 +L192=PPR023 +L193=PR12 +L194=PR12L +L195=TMPR105 +L196=TMPR106 +L197=TMPR107 +L198=PPR16 +L199=PR12H +L200=IICAPR11 +L201=PPR120 +L202=PPR121 +L203=PPR122 +L204=PPR123 +L205=IF0 +L206=IF0L +L207=WDTIIF +L208=LVIIF +L209=PIF0 +L210=PIF1 +L211=PIF2 +L212=PIF4 +L213=PIF5 +L214=IF0H +L215=DMAIF0 +L216=DMAIF1 +L217=CSIIF00 +L218=STIF0 +L219=CSIIF01 +L220=SRIF0 +L221=SREIF0 +L222=IF1 +L223=IF1L +L224=CSIIF10 +L225=IICIF10 +L226=STIF1 +L227=SRIF1 +L228=SREIF1 +L229=IICAIF0 +L230=TMIF00 +L231=TMIF01 +L232=TMIF02 +L233=TMIF03 +L234=IF1H +L235=ADIF +L236=RTCIF +L237=RTCIIF +L238=KRIF +L239=MDIF +L240=TMIF04 +L241=MK0 +L242=MK0L +L243=WDTIMK +L244=LVIMK +L245=PMK0 +L246=PMK1 +L247=PMK2 +L248=PMK4 +L249=PMK5 +L250=MK0H +L251=DMAMK0 +L252=DMAMK1 +L253=CSIMK00 +L254=STMK0 +L255=CSIMK01 +L256=SRMK0 +L257=SREMK0 +L258=MK1 +L259=MK1L +L260=CSIMK10 +L261=IICMK10 +L262=STMK1 +L263=SRMK1 +L264=SREMK1 +L265=IICAMK0 +L266=TMMK00 +L267=TMMK01 +L268=TMMK02 +L269=TMMK03 +L270=MK1H +L271=ADMK +L272=RTCMK +L273=RTCIMK +L274=KRMK +L275=MDMK +L276=TMMK04 +L277=PR00 +L278=PR00L +L279=WDTIPR0 +L280=LVIPR0 +L281=PPR00 +L282=PPR01 +L283=PPR02 +L284=PPR04 +L285=PPR05 +L286=PR00H +L287=DMAPR00 +L288=DMAPR01 +L289=CSIPR000 +L290=STPR00 +L291=CSIPR001 +L292=SRPR00 +L293=SREPR00 +L294=PR01 +L295=PR01L +L296=CSIPR010 +L297=IICPR010 +L298=STPR01 +L299=SRPR01 +L300=SREPR01 +L301=IICAPR00 +L302=TMPR000 +L303=TMPR001 +L304=TMPR002 +L305=TMPR003 +L306=PR01H +L307=ADPR0 +L308=RTCPR0 +L309=RTCIPR0 +L310=KRPR0 +L311=MDPR0 +L312=TMPR004 +L313=PR10 +L314=PR10L +L315=WDTIPR1 +L316=LVIPR1 +L317=PPR10 +L318=PPR11 +L319=PPR12 +L320=PPR14 +L321=PPR15 +L322=PR10H +L323=DMAPR10 +L324=DMAPR11 +L325=CSIPR100 +L326=STPR10 +L327=CSIPR101 +L328=SRPR10 +L329=SREPR10 +L330=PR11 +L331=PR11L +L332=CSIPR110 +L333=IICPR110 +L334=STPR11 +L335=SRPR11 +L336=SREPR11 +L337=IICAPR10 +L338=TMPR100 +L339=TMPR101 +L340=TMPR102 +L341=TMPR103 +L342=PR11H +L343=ADPR1 +L344=RTCPR1 +L345=RTCIPR1 +L346=KRPR1 +L347=MDPR1 +L348=TMPR104 +L349=MDAL +L350=MULA +L351=MDAH +L352=MULB +L353=MDBH +L354=MULOH +L355=MDBL +L356=MULOL +L357=PMC +L358=MAA +L359=ADPC +L360=PU0 +L361=PU1 +L362=PU3 +L363=PU4 +L364=PU5 +L365=PU7 +L366=PU12 +L367=PU14 +L368=PIM3 +L369=PIM7 +L370=POM3 +L371=POM7 +L372=NFEN0 +L373=NFEN1 +L374=NFEN2 +L375=MDCL +L376=MDCH +L377=MDUC +L378=DIVST +L379=DIVMODE +L380=PER0 +L381=SAU0EN +L382=IICA0EN +L383=ADCEN +L384=RTCEN +L385=PER2 +L386=TAU0EN +L387=OSMC +L388=BCDADJ +L389=SSR00 +L390=SSR00L +L391=SSR01 +L392=SSR01L +L393=SSR02 +L394=SSR02L +L395=SSR03 +L396=SSR03L +L397=SIR00 +L398=SIR00L +L399=SIR01 +L400=SIR01L +L401=SIR02 +L402=SIR02L +L403=SIR03 +L404=SIR03L +L405=SMR00 +L406=SMR01 +L407=SMR02 +L408=SMR03 +L409=SCR00 +L410=SCR01 +L411=SCR02 +L412=SCR03 +L413=SE0 +L414=SE0L +L415=SS0 +L416=SS0L +L417=ST0 +L418=ST0L +L419=SPS0 +L420=SPS0L +L421=SO0 +L422=SOE0 +L423=SOE0L +L424=SOL0 +L425=SOL0L +L426=TCR00 +L427=TCR01 +L428=TCR02 +L429=TCR03 +L430=TCR04 +L431=TCR05 +L432=TCR06 +L433=TCR07 +L434=TMR00 +L435=TMR01 +L436=TMR02 +L437=TMR03 +L438=TMR04 +L439=TMR05 +L440=TMR06 +L441=TMR07 +L442=TSR00 +L443=TSR00L +L444=TSR01 +L445=TSR01L +L446=TSR02 +L447=TSR02L +L448=TSR03 +L449=TSR03L +L450=TSR04 +L451=TSR04L +L452=TSR05 +L453=TSR05L +L454=TSR06 +L455=TSR06L +L456=TSR07 +L457=TSR07L +L458=TE0 +L459=TE0L +L460=TS0 +L461=TS0L +L462=TT0 +L463=TT0L +L464=TPS0 +L465=TPS0L +L466=TO0 +L467=TO0L +L468=TOE0 +L469=TOE0L +L470=TOL0 +L471=TOL0L +L472=TOM0 +L473=TOM0L +L474=IICCTL00 +L475=SPT0 +L476=STT0 +L477=ACKE0 +L478=WTIM0 +L479=SPIE0 +L480=WREL0 +L481=LREL0 +L482=IICE0 +L483=IICCTL10 +L484=DFC0 +L485=SMC0 +L486=DAD0 +L487=CLD0 +L488=WUP0 +L489=IICWL0 +L490=IICWH0 +L491=SVA0 +L492=PER3 +L493=IICA1EN +L494=P20 +L495=PM20 +L496=PU20 +L497=EGP2 +L498=EGN2 +L499=IICA1 +L500=IICS1 +L501=SPD1 +L502=STD1 +L503=ACKD1 +L504=TRC1 +L505=COI1 +L506=EXC1 +L507=ALD1 +L508=MSTS1 +L509=IICF1 +L510=IICRSV1 +L511=STCEN1 +L512=IICBSY1 +L513=STCF1 +L514=IICCTL01 +L515=SPT1 +L516=STT1 +L517=ACKE1 +L518=WTIM1 +L519=SPIE1 +L520=WREL1 +L521=LREL1 +L522=IICE1 +L523=IICCTL11 +L524=DFC1 +L525=SMC1 +L526=DAD1 +L527=CLD1 +L528=WUP1 +L529=IICWL1 +L530=IICWH1 +L531=SVA1 +[Local Variable] +Geometry=864, 668, 400, 259 +Window=Hide +Boundary=13041851 +Mode=Proper +[Trace View] +Geometry=0, 0, 0, 0 +Window=Hide +Mode=Normal +Frame=Show +Timetag=Clock +Address=Show +Data=Hex +Status=Show +Address2=Show +Data2=Hex +Status2=Show +Disasm=Show +Pick Up=Off +Synchronize=0 0 0 0 +Frameno= +Frameno1= +Frameno2= +Frameno3= +Frameno4= +Frameno5= +Frameno6= +Frameno7= +Frameno8= +Frameno9= +Frameno10= +Frameno11= +Frameno12= +Frameno13= +Frameno14= +Frameno15= +Frameno16= +ScanStatus=ALL +Access Size=B +ScanAddress=<>-<> +Mask Address= +ScanData= +Mask Data= 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Emulation] +Geometry=0, 0, 0, 0 +Window=Hide +[Data Flash Option] +Data Flash Emulation=OFF +[List] +Geometry=0, 0, 0, 0 +Window=Hide +[Console] +Geometry=0, 0, 0, 0 +Window=Hide diff --git a/branches/0.10(X3)/yav_mcu_bsr.prj b/branches/0.10(X3)/yav_mcu_bsr.prj new file mode 100644 index 0000000..785fddc --- /dev/null +++ b/branches/0.10(X3)/yav_mcu_bsr.prj @@ -0,0 +1,1044 @@ +[ProjectManager] +Version=6.00 +Path=C:\78k_data\yav-mcu-basara\branches\0.10(fix)\ +Title=yav-mcu +Series=78K0R.PM +Device=uPD79F0104 +DeviceVer=E1.00b +DebugMode=1 +Target=bsr.lmf +[BuildMode0] +BuildModeName=Debug Build +TargetFile=0 +[BuildMode1] +BuildModeName=Release Build +TargetFile=0 +[Tools] +MakeFile=yav_mcu_bsr.mak +Debugger=C:\Program Files\NEC Electronics Tools\ID78K0R-QB\V3.60\BIN\IDK0R32G.EXE +DebOption= +DebCpuReset=1 +DebSymReset=1 +MuitiLoad=0 +LoadPrjNum=0 +CheckVersion=CC78K0R|W2.10;RA78K0R|W1.31 +[Option.IDK0R32G] +File=yav_mcu_bsr.pri +[BuildBefore-AfterCmd] +Before1=touch magic.c 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