From 7258d5bf5ae993b5e8f3bee861abcd2f431c5eb2 Mon Sep 17 00:00:00 2001
From: n2232 <n2232@013db118-44a6-b54f-8bf7-843cb86687b1>
Date: Fri, 2 Sep 2011 01:41:57 +0000
Subject: [PATCH] =?UTF-8?q?=E2=96=A02.0E=20=E3=82=BF=E3=82=B0=E3=81=86?=
 =?UTF-8?q?=E3=81=A1=E3=80=80SDK3.1=E3=81=AB=E5=8F=8E=E9=8C=B2?=
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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@404 013db118-44a6-b54f-8bf7-843cb86687b1
---
 tags/2.03_SDK-3.1/OMakefile                   |  159 ++
 tags/2.03_SDK-3.1/OMakeroot                   |    4 +
 tags/2.03_SDK-3.1/WDT.c                       |    2 +
 tags/2.03_SDK-3.1/WDT.h                       |   20 +
 tags/2.03_SDK-3.1/accero.c                    |  263 +++
 tags/2.03_SDK-3.1/accero.h                    |   14 +
 tags/2.03_SDK-3.1/adc.c                       |  450 ++++++
 tags/2.03_SDK-3.1/adc.h                       |   48 +
 tags/2.03_SDK-3.1/batt_params.c               |   84 +
 tags/2.03_SDK-3.1/batt_params.h               |   49 +
 tags/2.03_SDK-3.1/bsr.hex                     |  995 ++++++++++++
 tags/2.03_SDK-3.1/bsr.lmf                     |  Bin 0 -> 179864 bytes
 tags/2.03_SDK-3.1/bsr_k0r.map                 |  830 ++++++++++
 tags/2.03_SDK-3.1/bsr_mcu.dr                  |   46 +
 tags/2.03_SDK-3.1/bsr_system.h                |   67 +
 tags/2.03_SDK-3.1/config.h                    |   94 ++
 tags/2.03_SDK-3.1/fsl.h                       |  362 +++++
 tags/2.03_SDK-3.1/fsl_user.h                  |  113 ++
 tags/2.03_SDK-3.1/hal.c                       |  177 +++
 tags/2.03_SDK-3.1/hal.h                       |   16 +
 tags/2.03_SDK-3.1/hoge.bin                    |  Bin 0 -> 16387 bytes
 tags/2.03_SDK-3.1/i2c_ctr.c                   |  297 ++++
 tags/2.03_SDK-3.1/i2c_ctr.h                   |  210 +++
 tags/2.03_SDK-3.1/i2c_mcu.c                   |  657 ++++++++
 tags/2.03_SDK-3.1/i2c_mcu.h                   |   40 +
 tags/2.03_SDK-3.1/i2c_twl.c                   |  231 +++
 tags/2.03_SDK-3.1/i2c_twl.h                   |    7 +
 tags/2.03_SDK-3.1/i2c_twl_defs.h              |  196 +++
 tags/2.03_SDK-3.1/incs.h                      |   58 +
 tags/2.03_SDK-3.1/incs_loader.h               |   47 +
 tags/2.03_SDK-3.1/ini_VECT.c                  |  383 +++++
 tags/2.03_SDK-3.1/jhl_defs.h                  |   29 +
 tags/2.03_SDK-3.1/led.c                       |  354 +++++
 tags/2.03_SDK-3.1/led.h                       |  142 ++
 tags/2.03_SDK-3.1/led_cam.c                   |  151 ++
 tags/2.03_SDK-3.1/led_pow.c                   |  269 ++++
 tags/2.03_SDK-3.1/loader.c                    |  406 +++++
 tags/2.03_SDK-3.1/loader.h                    |    7 +
 tags/2.03_SDK-3.1/magic.c                     |   29 +
 tags/2.03_SDK-3.1/magic.h                     |   24 +
 tags/2.03_SDK-3.1/main.c                      |   91 ++
 tags/2.03_SDK-3.1/nec_s_2_bsrbin2.rb          |   82 +
 tags/2.03_SDK-3.1/pedo_alg_thre_det2.c        |  575 +++++++
 tags/2.03_SDK-3.1/pedo_lpf_coeff.c            |   83 +
 tags/2.03_SDK-3.1/pedo_lpf_coeff.h            |   84 +
 tags/2.03_SDK-3.1/pedometer.h                 |   36 +
 tags/2.03_SDK-3.1/pm.c                        | 1390 ++++++++++++++++
 tags/2.03_SDK-3.1/pm.h                        |  216 +++
 tags/2.03_SDK-3.1/pool.h                      |   24 +
 tags/2.03_SDK-3.1/reboot.c                    |   24 +
 tags/2.03_SDK-3.1/reboot.h                    |    6 +
 tags/2.03_SDK-3.1/renge/renge.c               |  312 ++++
 tags/2.03_SDK-3.1/renge/renge.h               |   26 +
 tags/2.03_SDK-3.1/renge/renge_defs.h          |   55 +
 tags/2.03_SDK-3.1/renge/renge_task_config.rb  |   59 +
 .../2.03_SDK-3.1/renge/renge_task_immediate.h |   25 +
 tags/2.03_SDK-3.1/renge/renge_task_intval.h   |   37 +
 tags/2.03_SDK-3.1/renge/renge_tasks.txt       |   11 +
 tags/2.03_SDK-3.1/rtc.c                       |  177 +++
 tags/2.03_SDK-3.1/rtc.h                       |   21 +
 tags/2.03_SDK-3.1/self_flash.c                |  608 +++++++
 tags/2.03_SDK-3.1/self_flash.h                |    9 +
 tags/2.03_SDK-3.1/sw.c                        |  188 +++
 tags/2.03_SDK-3.1/sw.h                        |   20 +
 tags/2.03_SDK-3.1/task_debug.c                |  112 ++
 tags/2.03_SDK-3.1/task_misc.c                 |  399 +++++
 tags/2.03_SDK-3.1/task_status.c               |   79 +
 tags/2.03_SDK-3.1/task_sys.c                  |  654 ++++++++
 tags/2.03_SDK-3.1/user_define.h               |  209 +++
 tags/2.03_SDK-3.1/voltable.c                  |   48 +
 tags/2.03_SDK-3.1/voltable.h                  |   57 +
 tags/2.03_SDK-3.1/vreg_ctr.c                  |  591 +++++++
 tags/2.03_SDK-3.1/vreg_ctr.h                  |  302 ++++
 tags/2.03_SDK-3.1/vreg_twl.c                  |  156 ++
 tags/2.03_SDK-3.1/vreg_twl.h                  |  127 ++
 tags/2.03_SDK-3.1/yav_mcu_bsr.plg             |   44 +
 tags/2.03_SDK-3.1/yav_mcu_bsr.pri             | 1028 ++++++++++++
 tags/2.03_SDK-3.1/yav_mcu_bsr.prj             | 1407 +++++++++++++++++
 tags/2.03_SDK-3.1/yav_mcu_bsr.prk             |   23 +
 tags/2.03_SDK-3.1/yav_mcu_bsr.prw             |    8 +
 tags/2.03_SDK-3.1/yav_mcu_bsr.sdb             |  312 ++++
 tags/2.03_SDK-3.1/ベースからの変更.xls        |  Bin 0 -> 26624 bytes
 82 files changed, 17045 insertions(+)
 create mode 100644 tags/2.03_SDK-3.1/OMakefile
 create mode 100644 tags/2.03_SDK-3.1/OMakeroot
 create mode 100644 tags/2.03_SDK-3.1/WDT.c
 create mode 100644 tags/2.03_SDK-3.1/WDT.h
 create mode 100644 tags/2.03_SDK-3.1/accero.c
 create mode 100644 tags/2.03_SDK-3.1/accero.h
 create mode 100644 tags/2.03_SDK-3.1/adc.c
 create mode 100644 tags/2.03_SDK-3.1/adc.h
 create mode 100644 tags/2.03_SDK-3.1/batt_params.c
 create mode 100644 tags/2.03_SDK-3.1/batt_params.h
 create mode 100644 tags/2.03_SDK-3.1/bsr.hex
 create mode 100644 tags/2.03_SDK-3.1/bsr.lmf
 create mode 100644 tags/2.03_SDK-3.1/bsr_k0r.map
 create mode 100644 tags/2.03_SDK-3.1/bsr_mcu.dr
 create mode 100644 tags/2.03_SDK-3.1/bsr_system.h
 create mode 100644 tags/2.03_SDK-3.1/config.h
 create mode 100644 tags/2.03_SDK-3.1/fsl.h
 create mode 100644 tags/2.03_SDK-3.1/fsl_user.h
 create mode 100644 tags/2.03_SDK-3.1/hal.c
 create mode 100644 tags/2.03_SDK-3.1/hal.h
 create mode 100644 tags/2.03_SDK-3.1/hoge.bin
 create mode 100644 tags/2.03_SDK-3.1/i2c_ctr.c
 create mode 100644 tags/2.03_SDK-3.1/i2c_ctr.h
 create mode 100644 tags/2.03_SDK-3.1/i2c_mcu.c
 create mode 100644 tags/2.03_SDK-3.1/i2c_mcu.h
 create mode 100644 tags/2.03_SDK-3.1/i2c_twl.c
 create mode 100644 tags/2.03_SDK-3.1/i2c_twl.h
 create mode 100644 tags/2.03_SDK-3.1/i2c_twl_defs.h
 create mode 100644 tags/2.03_SDK-3.1/incs.h
 create mode 100644 tags/2.03_SDK-3.1/incs_loader.h
 create mode 100644 tags/2.03_SDK-3.1/ini_VECT.c
 create mode 100644 tags/2.03_SDK-3.1/jhl_defs.h
 create mode 100644 tags/2.03_SDK-3.1/led.c
 create mode 100644 tags/2.03_SDK-3.1/led.h
 create mode 100644 tags/2.03_SDK-3.1/led_cam.c
 create mode 100644 tags/2.03_SDK-3.1/led_pow.c
 create mode 100644 tags/2.03_SDK-3.1/loader.c
 create mode 100644 tags/2.03_SDK-3.1/loader.h
 create mode 100644 tags/2.03_SDK-3.1/magic.c
 create mode 100644 tags/2.03_SDK-3.1/magic.h
 create mode 100644 tags/2.03_SDK-3.1/main.c
 create mode 100755 tags/2.03_SDK-3.1/nec_s_2_bsrbin2.rb
 create mode 100644 tags/2.03_SDK-3.1/pedo_alg_thre_det2.c
 create mode 100644 tags/2.03_SDK-3.1/pedo_lpf_coeff.c
 create mode 100644 tags/2.03_SDK-3.1/pedo_lpf_coeff.h
 create mode 100644 tags/2.03_SDK-3.1/pedometer.h
 create mode 100644 tags/2.03_SDK-3.1/pm.c
 create mode 100644 tags/2.03_SDK-3.1/pm.h
 create mode 100644 tags/2.03_SDK-3.1/pool.h
 create mode 100644 tags/2.03_SDK-3.1/reboot.c
 create mode 100644 tags/2.03_SDK-3.1/reboot.h
 create mode 100644 tags/2.03_SDK-3.1/renge/renge.c
 create mode 100644 tags/2.03_SDK-3.1/renge/renge.h
 create mode 100644 tags/2.03_SDK-3.1/renge/renge_defs.h
 create mode 100644 tags/2.03_SDK-3.1/renge/renge_task_config.rb
 create mode 100644 tags/2.03_SDK-3.1/renge/renge_task_immediate.h
 create mode 100644 tags/2.03_SDK-3.1/renge/renge_task_intval.h
 create mode 100644 tags/2.03_SDK-3.1/renge/renge_tasks.txt
 create mode 100644 tags/2.03_SDK-3.1/rtc.c
 create mode 100644 tags/2.03_SDK-3.1/rtc.h
 create mode 100644 tags/2.03_SDK-3.1/self_flash.c
 create mode 100644 tags/2.03_SDK-3.1/self_flash.h
 create mode 100644 tags/2.03_SDK-3.1/sw.c
 create mode 100644 tags/2.03_SDK-3.1/sw.h
 create mode 100644 tags/2.03_SDK-3.1/task_debug.c
 create mode 100644 tags/2.03_SDK-3.1/task_misc.c
 create mode 100644 tags/2.03_SDK-3.1/task_status.c
 create mode 100644 tags/2.03_SDK-3.1/task_sys.c
 create mode 100644 tags/2.03_SDK-3.1/user_define.h
 create mode 100644 tags/2.03_SDK-3.1/voltable.c
 create mode 100644 tags/2.03_SDK-3.1/voltable.h
 create mode 100644 tags/2.03_SDK-3.1/vreg_ctr.c
 create mode 100644 tags/2.03_SDK-3.1/vreg_ctr.h
 create mode 100644 tags/2.03_SDK-3.1/vreg_twl.c
 create mode 100644 tags/2.03_SDK-3.1/vreg_twl.h
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.plg
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.pri
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.prj
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.prk
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.prw
 create mode 100644 tags/2.03_SDK-3.1/yav_mcu_bsr.sdb
 create mode 100644 tags/2.03_SDK-3.1/ベースからの変更.xls

diff --git a/tags/2.03_SDK-3.1/OMakefile b/tags/2.03_SDK-3.1/OMakefile
new file mode 100644
index 0000000..42baad6
--- /dev/null
+++ b/tags/2.03_SDK-3.1/OMakefile
@@ -0,0 +1,159 @@
+############################################################
+# 環境設定
+############################################################
+
+# マイコン開発環境のインストール先を環境変数で指定する
+NECEL_ROOT =
+    if $(defined-env NECEL_ROOT)
+        value $(absname $"$(getenv NECEL_ROOT)")
+    else
+        value "C:\Program Files (x86)\NEC Electronics Tools"
+
+# cygwinのインストール先を環境変数で指定する
+CYGWIN_ROOT = 
+    if $(defined-env CYGWIN_ROOT)
+        value $(absname $"$(getenv CYGWIN_ROOT)")
+    else
+        value "C:\cygwin"
+
+# GCCバージョンを環境変数で指定する
+CYGWIN_GCC =
+    if $(defined-env CYGWIN_GCC)
+        value $(CYGWIN_ROOT)/bin/$"$(getenv CYGWIN_GCC)"
+    else
+        value $(CYGWIN_ROOT)/bin/gcc-4
+
+#デバイスファイルは NECEL_ROOT/dev に置くこと
+#自己アップデート用ライブラリは CC_LIBS_ROOT/以下に置くこと
+
+SUBDIR_INTER_ASM = $(dir inter_asm)
+
+CC_ROOT = $(NECEL_ROOT)/CC78K0R
+CC_VER = W2.13
+CC = $(CC_ROOT)/$(CC_VER)/bin/cc78k0r.exe
+RA = $(NECEL_ROOT)/RA78K0R/W1.33/bin/ra78k0r.exe
+LK = $(NECEL_ROOT)/RA78K0R/W1.33/bin/lk78k0r.exe
+OC = $(NECEL_ROOT)/RA78K0R/W1.33/bin/oc78k0r.exe
+LCNV = $(NECEL_ROOT)/RA78K0R/W1.33/bin/lc78k0r.exe
+DEVFILE_ROOT = $(NECEL_ROOT)/dev
+
+CC_LIBS_ROOT = $(CC_ROOT)/$(CC_VER)/lib78k0r
+CC_INCLUDES_ROOT = $(CC_ROOT)/$(CC_VER)/inc78k0r
+S0RM = s0rm.rel
+
+# セキュリティID
+GIVALUE = 1B339499E033F240BFAAh
+
+# ユーザオプションバイト
+GBValue = 7EFBFFh
+
+DEVICE_NAME = 9F0104
+
+FSL_LIB = fsl.lib
+
+TARGET_NAME = bsr
+TARGET_LMF = $(TARGET_NAME).lmf
+TARGET_HEX = $(TARGET_NAME).hex
+
+# ここまで
+############################################################
+
+############################################################
+# ソースを追加したら編集する箇所
+############################################################
+
+SRC_FILES[] = 
+    loader
+    pm
+    i2c_ctr
+    main
+    magic
+    WDT
+    i2c_mcu
+    i2c_twl
+    led
+    rtc
+    vreg_ctr
+    vreg_twl
+    adc
+    renge\renge
+    accero
+    self_flash
+    sw
+    task_debug
+    task_misc
+    task_sys
+    pedo_alg_thre_det2
+    ini_VECT
+    task_status
+    led_cam
+    led_pow
+    hal
+    batt_params
+    voltable
+    pedo_lpf_coeff
+
+INCLUDES[] =
+    ./
+    renge
+
+# ここまで
+############################################################
+
+.PHONY: clean BeforeBuild
+
+AddRel(files) =
+    file_names = $(addsuffix .rel, $(files))
+    return $(file_names)
+
+# *.cからinter_asm/*.asmを作るための関数
+AsmProgram(files) =
+    foreach(filename, $(files))
+        asm_name = $(addprefix $(SUBDIR_INTER_ASM)/, $(addsuffix .asm, $(basename $(filename))))
+        c_name = $(addsuffix .c, $(filename))
+
+        .SCANNER: $(asm_name): $(c_name)
+            $(CYGWIN_GCC) -MM -w -I$(CC_INCLUDES_ROOT) $(c_name) | sed 's/$(filename)\.o/$(SUBDIR_INTER_ASM)\/$(filename)\.asm/g'
+
+        $(asm_name): $(c_name)
+            $(CC) -c$(DEVICE_NAME) -y$(DEVFILE_ROOT) -_msgoff -irenge -i$(CC_INCLUDES_ROOT) -ms -qvjl2w -sa$(SUBDIR_INTER_ASM) -zpb -no $(c_name)
+
+    return $(addsuffix .c, $(files))
+
+# inter_asm/*.asm から *.relを作るための関数
+RelProgram(files) =
+    foreach(filename, $(files))
+        rel_name = $(addsuffix .rel, $(basename $(filename)))
+        asm_name = $(addprefix $(SUBDIR_INTER_ASM)/, $(addsuffix .asm, $(basename $(filename))))
+        asm_win_name = $(addprefix $(SUBDIR_INTER_ASM)\\, $(addsuffix .asm, $(basename $(filename))))
+        c_name = $(addsuffix .c, $(filename))
+
+        .SCANNER: $(rel_name): $(asm_win_name)
+            $(CYGWIN_GCC) -MM -w -I$(CC_INCLUDES_ROOT) $(c_name) | sed 's/\.o/\.rel/g'
+
+        $(rel_name): $(asm_name)
+            $(RA) -c$(DEVICE_NAME) -y$(DEVFILE_ROOT) -_msgoff $(asm_win_name)
+
+    return $(addsuffix .rel, $(basename $(files)))
+
+$(TARGET_LMF): $(RelProgram $(SRC_FILES)) $(AsmProgram $(SRC_FILES))
+    $(LK) -y$(DEVFILE_ROOT) -_msgoff -o$(TARGET_LMF) $(CC_LIBS_ROOT)/$(S0RM)  -gi$(GIVALUE) -pbsr_k0r.map -nkd -gb$(GBValue) -b$(CC_LIBS_ROOT)/$(FSL_LIB) -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i$(CC_LIBS_ROOT) -dbsr_mcu.dr -s -w0  $(AddRel $(basename $(SRC_FILES)))
+
+$(TARGET_HEX) : $(TARGET_LMF)
+    $(OC) -y$(DEVFILE_ROOT) -_msgoff -o.\\$(TARGET_HEX) -nu -ki  $(TARGET_LMF)
+
+BeforeBuild:
+# ビルド前に必ず実行したい処理
+# OMakeがタイムスタンプではなくMD5でファイルの状態を管理しているので
+# 残念ながら cleanしてからビルドしなおす必要がある
+    C:\Windows\system32\cmd.exe /c $(CYGWIN_ROOT)\bin\touch magic.c
+    if $(not $(file-exists $(SUBDIR_INTER_ASM)))
+        mkdir $(SUBDIR_INTER_ASM)
+
+hoge.bin: BeforeBuild $(TARGET_HEX)
+    C:\Windows\system32\cmd.exe /c ruby nec_s_2_bsrbin2.rb $(TARGET_HEX)
+
+clean:
+    rm -rf *.prn *.rel $(SUBDIR_INTER_ASM)/*.asm *.omc .omakedb .omakedb.lock
+
+.DEFAULT: hoge.bin
diff --git a/tags/2.03_SDK-3.1/OMakeroot b/tags/2.03_SDK-3.1/OMakeroot
new file mode 100644
index 0000000..16f4b11
--- /dev/null
+++ b/tags/2.03_SDK-3.1/OMakeroot
@@ -0,0 +1,4 @@
+#
+# Include the OMakefile in this directory.
+#
+.SUBDIRS: .
diff --git a/tags/2.03_SDK-3.1/WDT.c b/tags/2.03_SDK-3.1/WDT.c
new file mode 100644
index 0000000..436a51c
--- /dev/null
+++ b/tags/2.03_SDK-3.1/WDT.c
@@ -0,0 +1,2 @@
+#include "incs_loader.h"
+
diff --git a/tags/2.03_SDK-3.1/WDT.h b/tags/2.03_SDK-3.1/WDT.h
new file mode 100644
index 0000000..2e28e9d
--- /dev/null
+++ b/tags/2.03_SDK-3.1/WDT.h
@@ -0,0 +1,20 @@
+#ifndef _WDT_
+#define _WDT_
+
+
+
+//=========================================================
+#define WDT_RESTART_MAGIC    0xAC
+
+
+
+//=========================================================
+// �E�H�b�`�h�b�O�^�C�}�̃��X�^�[�g
+// void WDT_Restart( void );
+#define WDT_Restart()        WDTE = WDT_RESTART_MAGIC
+
+// �K��l�ȊO�������Ɨ�O�Ń��Z�b�g��������
+#define mcu_wdt_reset        WDTE = 0x0
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/accero.c b/tags/2.03_SDK-3.1/accero.c
new file mode 100644
index 0000000..fc1f98b
--- /dev/null
+++ b/tags/2.03_SDK-3.1/accero.c
@@ -0,0 +1,263 @@
+/* ========================================================
+�@�����x�Z���T�֌W
+�E�f�[�^�X�V�����Ńf�[�^���z���グ�背�W�X�^���X�V�ACPU�Ɋ��荞��
+�E�t���O�������Ă���Ε����J�E���g
+�E�����x�Z���T���荞�݂���^�X�N��o�^���ĉ������B�iI2C�̋�������Ȃǂ�����̂Łj
+
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+#pragma ROT
+// rorb, rolb, rorw, rolw
+#pragma MUL
+#pragma BCD
+
+#endif
+
+#include "config.h"
+#ifndef _WIN32
+
+#pragma interrupt INTP23	intp23_ACC_ready RB3       // �����x�Z���T�A�f�[�^��������
+
+#endif
+
+
+#include "incs.h"
+
+#ifndef _WIN32
+#include <math.h>
+#endif
+// ========================================================
+// ���W�X�^��
+#define ACC_REG_WHOAMI 0x0F
+#define ACC_REG_CTRL1  0x20
+#define ACC_REG_CTRL5  0x24
+#define ACC_REG_X      0x28
+
+#define ACC_REG_FLG_BURST_ACCESS	0x80
+
+// �r�b�g�ʒu
+#define ACC_bP_PM0    5
+#define ACC_bP_DR0    3
+
+// �r�b�g�ݒ�l
+#define ACC_BITS_PM_PDN   0
+#define ACC_BITS_PM_NORM  1
+#define ACC_BITS_PM_LP0R5 2
+#define ACC_BITS_PM_LP1   3
+#define ACC_BITS_PM_LP2   4
+#define ACC_BITS_PM_LP5   5
+#define ACC_BITS_PM_LP10  6
+
+#define ACC_BITS_DR_50Hz   0
+#define ACC_BITS_DR_100Hz  1
+#define ACC_BITS_DR_400Hz  2
+#define ACC_BITS_DR_1000Hz 3
+
+#define ACC_BITS_ALL_AXIS_ON 7
+
+
+#define VREG_BITMASK_ACC_CONF_ACQ  ( 1 << 0 )
+#define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 )
+
+
+
+// ========================================================
+#define ACC_RAW_DATA_SIZE	6
+
+
+
+// ========================================================
+task_status tsk_soft_int(  );
+
+extern void DI_wt_chk(); 
+
+
+
+/* ========================================================
+�@�E���荞�݂��m�F���ăf�[�^���z���グ�A���W�X�^�ɏ����o���܂�
+  �E�{���ł���΃R�[���o�b�N�֐���o�^���Ă����΂��������ƂȂ�̂ł����A
+  I2C���g�p����������H�Ƃ��l����Ǝ��ł͂����܂łł��Ȃ��̂ł��B
+  �E���������v�Ƃ��ł�����
+ ======================================================== */
+task_status_immed tski_cbk_accero(  )
+{                               // �i�^���jisr����o�^����܂�
+    static u8 err_count;
+	u8 acc_dat_buff[ ACC_RAW_DATA_SIZE ];
+
+    // �����x�Z���T�f�[�^���W�X�^�ւ̔��f
+    if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | ACC_REG_FLG_BURST_ACCESS ), ACC_RAW_DATA_SIZE, acc_dat_buff )
+        != ERR_SUCCESS )
+    {
+        err_count ++;
+        if( err_count < 8 )
+        {
+            // ���g���C
+            return( ERR_CONTINUE );
+        }
+        else
+        {
+            // �����x�Z���T���ُ�ɂȂ����̂Ŏ~�߂�
+            vreg_ctr[ VREG_C_ACC_CONFIG ] &= ~( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ );
+            tski_acc_setup();
+            vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
+            return ( ERR_FINISED ); // �^�X�N�̍폜�͕K�v
+        }
+    }
+    else
+    {
+		memcpy( &vreg_ctr[VREG_C_ACC_XL], acc_dat_buff, ACC_RAW_DATA_SIZE );
+
+        err_count = 0;
+        // ���펞�p�X //
+        // �����x�X�V�����荞��
+        if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_ACQ ) != 0 ) &&
+            ( system_status.pwr_state == ON )
+            )
+            {
+                set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY );
+            // �S�~�f�[�^�̃J���ǂ�
+            if( ACC_VALID )
+            {
+                u8 temp[ACC_RAW_DATA_SIZE];
+                iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | ACC_REG_FLG_BURST_ACCESS ), ACC_RAW_DATA_SIZE, temp );
+            }
+        }
+        if(( system_status.pwr_state == ON )
+			||( system_status.pwr_state == SLEEP )
+            )
+        {
+            pedometer();    // �����v
+        }
+    }
+    return ( ERR_FINISED );
+}
+
+
+
+
+
+/*=======================================================
+�@�����x�Z���T���߃A�N�Z�X�@���[�h
+ ========================================================*/
+task_status_immed tski_acc_read(  )
+{
+    vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
+	set_irq( VREG_C_IRQ1, REG_BIT_ACC_ACK );
+    return ( ERR_FINISED );
+}
+
+
+
+/*=========================================================
+�@�����x�Z���T���߃A�N�Z�X�@���C�g
+ ========================================================*/
+task_status_immed tski_acc_write(  )
+{
+    iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_ADRS], vreg_ctr[VREG_C_ACC_W_BUF] );
+	set_irq( VREG_C_IRQ1, REG_BIT_ACC_ACK );
+    return ( ERR_FINISED );
+}
+
+
+
+/*=========================================================
+�@�����x�Z���T�̐ݒ�
+ ========================================================*/
+task_status_immed tski_acc_setup(  )
+{
+
+	// �����x on/off�ݒ肷��
+	{
+		u8      str_send_buf[4];
+
+		str_send_buf[1] = 0x00;     // ctrl2  HPF:normal, filterd, HPF for IRQ : dis/dis, HPF coeff:norm
+
+		// �s���s���̂��߁ATS�Ƃ���ȊO�i��H�Ⴂ�j����ʂ��Đݒ�
+		if( system_status.model == MODEL_TS_BOARD )
+		{
+			str_send_buf[2] = bits8(0,0,0,0, 0,0,1,0);	
+		}
+		else
+		{
+			str_send_buf[2] = bits8(0,0,0,1, 0,0,0,0);
+		}
+		str_send_buf[3] = 0x80;         // ctrl3  block update:enable, MSB first, scale: +-2G(default), selftest: dis
+
+		{
+			u8 acc_setting_sent = ( vreg_ctr[VREG_C_ACC_CONFIG] &
+				( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ ));
+
+			do{ 
+				EI();
+				if( acc_setting_sent == 0 )
+				{
+					PMK23 = 1;
+					// ���S��~
+					str_send_buf[0] =
+						( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | ACC_BITS_ALL_AXIS_ON );
+				}
+				else
+				{
+					PMK23 = 0;
+					// 100Hz ������荞��
+					str_send_buf[0] =
+						( ACC_BITS_PM_NORM << ACC_bP_PM0
+						  | ACC_BITS_DR_100Hz << ACC_bP_DR0
+						  | ACC_BITS_ALL_AXIS_ON );
+				}
+		
+				// ���������݌��A�ʐM�ł������t���O�X�V
+				if( iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | ACC_REG_FLG_BURST_ACCESS ), 4, str_send_buf ) == I2C_ERR_NOSLAVE )
+				{
+					vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
+				}else{
+					vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR;
+				}
+
+				// �J���ǂ݁B�O��̃S�~��ǂݎ̂�
+				if( ACC_VALID )
+				{
+					if( system_status.pwr_state == ON )
+					{
+						u8 temp[ACC_RAW_DATA_SIZE];
+						iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | ACC_REG_FLG_BURST_ACCESS ), 6, temp );
+					}
+				}
+
+				// �Z���T�ɏ����ɂ����Ă���Œ���SoC���܂����������Ă��܂���������Ȃ�
+				DI_wt_chk(); 
+			}while( acc_setting_sent != ( vreg_ctr[VREG_C_ACC_CONFIG] &
+					( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ )) );
+					
+		}
+	}
+
+	// DI��Ԃ̂܂܋A��
+    return ( ERR_FINISED );
+}
+
+
+
+/* ========================================================
+ �����x�Z���T���荞��
+  I2C���g�p����������Ȃ��̂ŁA�ǂݏo���^�X�N�̓o�^���s���̂�
+ ======================================================== */
+__interrupt void intp23_ACC_ready(  )
+{
+    EI();
+    if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 )
+    {
+        if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) )
+        {
+            if( ACC_VALID )
+            {
+                renge_task_immed_add( tski_cbk_accero );
+            }
+        }
+    }
+}
diff --git a/tags/2.03_SDK-3.1/accero.h b/tags/2.03_SDK-3.1/accero.h
new file mode 100644
index 0000000..fbf80d6
--- /dev/null
+++ b/tags/2.03_SDK-3.1/accero.h
@@ -0,0 +1,14 @@
+#ifndef _accero_
+#define _accero_
+
+
+#include "jhl_defs.h"
+#include "pedometer.h"
+
+
+///////////////////////////////////////////////////////////
+task_status_immed tski_cbk_accero(  );
+task_status_immed tski_acc_setup(  );
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/adc.c b/tags/2.03_SDK-3.1/adc.c
new file mode 100644
index 0000000..73a1cb6
--- /dev/null
+++ b/tags/2.03_SDK-3.1/adc.c
@@ -0,0 +1,450 @@
+/* ========================================================
+    ���c���J�Z
+    nintendo
+    '09 Apr
+ ======================================================== */
+#include "incs.h"
+#include "adc.h"
+#include "pm.h"
+
+#include "led.h"
+
+#include "vreg_twl.h"
+
+
+// ===================================================== //
+static bit	adc_updated;
+static bit	vol_changed_by_ctr;
+bit     vol_changed_by_twl;
+static u8	vol_old;
+
+static u8	adc_raw_vol;
+static u8	adc_raw_dep;
+
+u8		vol_polling;
+u8		vol_level_twl;
+
+extern const u8	slider_to_codec[];
+
+
+
+// ===================================================== //
+typedef struct filter_work
+{
+    u8* value_used;
+    s8 diffs;                   // KIKAN���̕΂�
+    s8 kikan;
+    u8 large_diff_count;
+}filter_work;
+
+
+static filter_work work_vr_3d = {
+    &vreg_ctr[ VREG_C_3D ]
+	// �̂���͕s��l�ł悵�Bconst�ɂ�����_��
+    };
+
+
+static u8 vol_data_ctr;
+static u8 vol_data_ctr_tmp;
+static filter_work work_vr_vol = {
+    &vol_data_ctr_tmp
+	// �̂���͕s��l�ł悵�Bconst�ɂ�����_��
+    };
+
+
+// twl ��8�i�Kvol�̃��j�A�l����̋��E
+/*
+    twl����32 -> 8 �e�[�u��
+    0�`1,�`4,�`8,�`13,�`18,�`23,�`28,31
+ */
+static const u8 TWL_VOL_BOUNDARY[] = {
+    1, 4, 8, 13, 18, 23, 28, 31
+};
+
+// ===================================================== //
+extern void nop8();
+static void adc_filter( u8 new_val, filter_work* work );
+static u8 adc_scaling( u8 );
+static void update_twl_vol( u8 sent_index );
+
+
+
+// ===================================================== //
+#define INTERVAL_TSK_ADC  15
+
+
+
+/* ========================================================
+ ADC�ݒ�ƁA�J�n
+
+  �ȉ��̃s���͎�ɂ����ő���E�Ď�����܂��B
+ �EBT_TEMP,_P
+ �EADIN1
+ �EVOL
+
+  �֌W���肻���ł����ʂ̂Ƃ���ŊǗ����Ă��܂�
+ �EPM_BT_DET,_P		BT_chk
+ ======================================================== */
+void tsk_adc(  )
+{
+    if( adc_updated )
+    {
+        adc_updated = false;
+
+        // 3D /////////////////////////////////////////
+        vreg_ctr[ VREG_C_3D ] = adc_raw_dep;         // ���l
+
+        // Volume /////////////////////////////////////
+        {
+            vreg_ctr[ VREG_C_VOL_ADC_RAW ] = adc_raw_vol;
+
+            adc_filter( adc_scaling( adc_raw_vol ), &work_vr_vol );  // ���ʂ�*work_vr_vol����w�����vol_data_ctr �ǂ݂ɂ���...
+            vol_data_ctr = vol_data_ctr_tmp / 4;
+
+            if( vol_old != vol_data_ctr )
+            {
+                vol_changed_by_ctr = true;
+                vol_old = vol_data_ctr;
+                vol_polling = 3;
+//                renge_task_immed_add( tski_vol_update );             ���œo�^
+            }
+        }
+
+        // �o�b�e������ ///////////////////////////
+        /* �Ă΂�܂��� */
+    }
+
+    // �����Y�ꂪ����Ƃ���Ȃ̂Ń|�[�����O orz
+    if( vol_polling < 5 )
+    {
+        renge_task_immed_add( tski_vol_update );
+        vol_polling = (u8)(200 / SYS_INTERVAL_TICK) + 5;                      // 5��/sec
+    }
+    vol_polling --;
+
+
+    ADCEN = 1;
+    ADM =  bits8(0,0,0,0, 1,0,1,1);      // �Z���N�g���[�h�A�����AfCLK/6 // �������� ��
+
+    ADPC = 0x06;            // ADC�|�[�g�̃Z���N�g
+    ADS = ADC_SEL_3D;
+    nop8();
+    ADCS = 1;               // AD�J�n�B                     // �����܂Ł@���@�܂ł�1us=8clk�ȏ�J����
+
+    ADIF = 0;
+    ADMK = 0;
+}
+
+
+
+void vol_reset()
+{
+    vol_old = vol_data_ctr;
+    vreg_ctr[ VREG_C_SND_VOL ] = vol_data_ctr; // 64�i
+}
+
+
+/* ========================================================
+�@Vol���X�V���܂��B
+ �@����Ȏ��ɓo�^����܂��B
+�@�@�E���[�U�[��Vol�X���C�_�𓮂�����
+�@�@�EHorizon�ɋ����X�V���w�����ꂽ�@�icodec���Z�b�g���j
+�@�@�ETWL�A�v����Vol����������
+======================================================== */
+task_status_immed tski_vol_update()
+{
+    static u8 sent_index, sent_index_twl;
+    static bit last_modifyer_is_twl;  // false = ctr
+
+    if( !( system_status.pwr_state == ON ) || 
+        ( system_status.pwr_state == SLEEP )){
+        return( ERR_FINISED );
+    }
+
+    // �ǂ̉��ʂɂ���́H //
+	if( vol_changed_by_ctr )
+    {
+        // �X���C�_
+        vol_changed_by_ctr = false;
+        last_modifyer_is_twl = false;
+        sent_index = vol_data_ctr;
+    }
+    else if( vol_changed_by_twl )
+    {
+        // TWL�A�v��
+        vol_changed_by_twl = false;
+        last_modifyer_is_twl = true;
+        if( vreg_twl[ REG_TWL_INT_ADRS_VOL ] == 0 )
+        {
+            sent_index_twl = 0;
+        }
+        else
+        {
+            sent_index_twl = vreg_twl[ REG_TWL_INT_ADRS_VOL ] *2 +1;
+        }
+        sent_index = sent_index_twl;
+    }
+    else
+    {
+        // force_slider��0�ɂ����Ƃ� & �����܂���Ƃ�
+        //  �X���C�_��TWL�̍Ō�ɃZ�b�g���������Z�b�g
+        if( last_modifyer_is_twl )
+        {
+            sent_index = sent_index_twl;
+        }
+        else
+        {
+            sent_index = vol_data_ctr;
+        }
+    }
+
+    // ���W�X�^�̍X�V //
+    vreg_ctr[ VREG_C_SND_VOL ] = sent_index;
+
+	// twl���X�V
+	update_twl_vol( sent_index );
+
+    // codec�ɓ`����
+    /// ���l�ł�����
+    iic_mcu_write_a_byte_codec( CODEC_REG_VOL, slider_to_codec[ sent_index ] );
+
+    //    set_irq( VREG_C_IRQ0, REG_BIT_VR_SNDVOL_CHANGE );  // ���荞�ݔp�~
+    return( ERR_FINISED );
+}
+
+
+static void update_twl_vol( u8 sent_index )
+{
+	// �X�P�[�����O
+    if( sent_index == 0 )
+    {
+        vreg_twl[ REG_TWL_INT_ADRS_VOL ] = 0;
+    }
+    else if( sent_index <= 4 )
+    {
+        vreg_twl[ REG_TWL_INT_ADRS_VOL ] = 2;	// �P�̓~�b�V���O�Ő���
+    }
+    else
+    {
+        vreg_twl[ REG_TWL_INT_ADRS_VOL ] = sent_index/2 ;
+    }
+
+    // 8�i�K�̃��x�����B�@���荞�݂�����̂ɕK�v
+    {
+        static u8 vol_twl_old;
+        
+        if( vol_twl_old != vreg_twl[ REG_TWL_INT_ADRS_VOL ] )
+        {
+            // 8�i���x���ɕϊ�
+            u8 new_level = 31;
+            u8 i;
+            
+            vol_twl_old = vreg_twl[ REG_TWL_INT_ADRS_VOL ];
+
+            for( i=0; i<=7; i++ )
+            {
+                if( vreg_twl[ REG_TWL_INT_ADRS_VOL ] <= TWL_VOL_BOUNDARY[ i ] )
+                {
+                    new_level = i;
+                    break;
+                }
+            }
+            vol_level_twl = new_level;
+        }
+    }
+}
+
+
+
+/* ========================================================
+�@���O�Ŏ��̃`�����l��
+�@�@��ʂ�I�������~�߂�
+ ======================================================== */
+__interrupt void int_adc(  )
+{
+    volatile u8 adc_data = ADCRH;
+
+    switch ( ADS )
+    {
+/*
+case ( ADC_SEL_AMB_BRIT ): // �‹����邳
+        vreg_ctr[ VREG_C_AMBIENT_BRIGHTNESS ] = adc_data;
+        break;
+*/
+
+    case ( ADC_SEL_3D ):
+        EI();
+        adc_raw_dep = adc_data;
+        break;
+
+    case ( ADC_SEL_VOL ):
+        EI();
+        if( system_status.model == MODEL_TS_BOARD )
+        {
+            adc_raw_vol = adc_data;
+        }
+        else
+        {
+            adc_raw_vol = 255 - adc_data;
+        }
+
+        break;
+
+    case ( ADC_SEL_BATT_TEMP ):
+        EI();
+#ifdef _ENABLE_HAL_
+		if( vreg_ctr[ VREG_C_HAL_OVW_TEMPERATURE ] == 0xFF )	// HAL����
+#else
+		if( 1 )
+#endif
+		{
+	        raw_adc_temperature = adc_data;
+		}
+		else
+		{
+			raw_adc_temperature = vreg_ctr[ VREG_C_HAL_OVW_TEMPERATURE ];
+		}
+
+        if(// (( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_MGIC_ERR ) == 0 ) &&
+            (( system_status.pwr_state == ON ) ||
+             ( system_status.pwr_state == SLEEP )
+             )
+            )
+        {
+            renge_task_immed_add( tski_BT_temp_update );
+        }
+        break;
+
+/* �Ă΂�܂���
+    case ( ADC_SEL_BATT_DET ):
+        break;
+*/
+    }
+
+// �����Ƃ܂Ƃ��ȏ����������肻����
+    if( ADS < ADC_SEL_BATT_DET )
+    {
+        ADS += 1;               // ���̃`�����l��
+    }
+    else
+    {
+        ADCEN = 0;              // �~�߂Ă��܂�
+        adc_updated = true;
+    }
+    ADIF = 0;               // ����������Ȃ��ƁA�������O�̃`�����l���̃f�[�^�̊����Œ���Ɋ��荞�މ”\��������
+}
+
+
+
+/* ========================================================
+ tsk_adc�Ƌ������邱�Ƃ��l�����Ă��܂���B
+ ======================================================== */
+u8 get_adc( u8 ch )
+{
+    u8      temp;
+
+    ADMK = 1;
+    ADIF = 0;
+
+    ADCEN = 1;
+    ADM = bits8(0,0,0,0, 1,0,1,1);          // �Z���N�g���[�h�A�����AfCLK/6  ///�������火
+
+    ADPC = 0x06;                // ADC�|�[�g�̃Z���N�g
+    ADS = ch;
+
+    nop8();
+
+    ADCS = 1;                   // AD�J�n�B                     /// �����܂Ł��@�ɁA1us�ȏ�J����
+
+    ADIF = 0;
+    while( ADIF == 0 ){;}
+    temp = ADCRH;
+    ADCEN = 0;
+
+    ADMK = 0;
+    return ( temp );
+}
+
+
+
+
+
+/* ========================================================
+ VR�̉“��͈͂��l���ăX�P�[�����O
+
+ ����Vol��p�@�g���񂷂Ȃ炻�̂Ƃ��ǂ��ɂ�����
+======================================================== */
+static u8 adc_scaling( u8 orig_val )
+{
+    u16 temp;
+
+    if( orig_val <= vreg_ctr[ VREG_C_VOL_CAL_MIN ] )
+    {
+        return( 0 );
+    }
+    if( orig_val >= vreg_ctr[ VREG_C_VOL_CAL_MAX ] )
+    {
+        return( 255 );
+    }
+
+    temp = (u16)(( orig_val - vreg_ctr[ VREG_C_VOL_CAL_MIN ] ) * 256 ) / ( vreg_ctr[ VREG_C_VOL_CAL_MAX ] - vreg_ctr[ VREG_C_VOL_CAL_MIN ] );
+    if( temp > 255 )
+    {
+        temp = 255;
+    }
+
+    return( (u8)( temp & 0xFF ) );
+}
+
+
+
+
+/* ========================================================
+ ����q�X�e���V�X V2
+ �l�̌ܓ��I�ȓ������܂�
+======================================================== */
+#define KIKAN 16
+static void adc_filter( u8 new_val, filter_work *work )
+{
+    if( abs( new_val - *( work -> value_used )) > 2 )
+    {
+        // �傫�����ꂽ
+        work -> large_diff_count ++;
+        if( work -> large_diff_count > 16 )
+        {
+            *( work -> value_used ) = new_val;
+            work -> diffs = 0;
+            work -> kikan = KIKAN;
+        }
+    }
+    else
+    {
+        work -> large_diff_count = 0;
+        // �ߏ��̒l�ł��A������Ԃł����ς��΂��Ă����炻�����Ɋ񂹂�
+        if( *( work -> value_used ) < new_val )
+        {
+            work -> diffs ++;
+        }
+        else if( *( work -> value_used ) > new_val )
+        {
+            work -> diffs --;
+        }
+
+        if( --( work -> kikan ) == 0 )
+        {
+            if( ( work -> diffs ) == KIKAN )
+//                if( ( work -> diffs ) > (s8)( KIKAN * 0.8 ) )
+            {
+                *( work -> value_used ) = *( work -> value_used ) + 1;
+            }
+            else if( ( work -> diffs ) == ( -1 * KIKAN ) )
+//            else if( ( work -> diffs ) < (s8)( -1 * KIKAN * 0.8 ) )
+            {
+                *( work -> value_used ) = *( work -> value_used ) - 1;
+            }
+            work -> diffs = 0;
+            work -> kikan = KIKAN;
+        }
+    }
+}
+
diff --git a/tags/2.03_SDK-3.1/adc.h b/tags/2.03_SDK-3.1/adc.h
new file mode 100644
index 0000000..6f4ad04
--- /dev/null
+++ b/tags/2.03_SDK-3.1/adc.h
@@ -0,0 +1,48 @@
+#ifndef __adc__
+#define __adc__
+
+#include "jhl_defs.h"
+
+///////////////////////////////////////
+// ANI2 P22
+#define ADC_SEL_AMB_BRIT  0x02
+
+/*
+// ANI3 P23
+#define ADC_SEL_GYRO_YAW  0x03
+// ANI4 P24
+#define ADC_SEL_GYRO_PITCH 0x04
+// ANI5 P25
+#define ADC_SEL_GYRO_ROLL 0x05
+*/
+
+// ANI6 P26
+#define ADC_SEL_3D      0x06
+// ANI7 P27
+#define ADC_SEL_VOL       0x07
+
+// ANI8 P150
+#define ADC_SEL_BATT_TEMP 0x08
+// ANI9 P151
+#define ADC_SEL_BATT_DET  0x09
+
+
+
+///////////////////////////////////////
+#define CODEC_REG_VOL 0x13
+
+
+
+///////////////////////////////////////
+extern u8 vol_polling;
+extern u8 vol_level_twl;
+
+
+
+///////////////////////////////////////
+u8 get_adc( u8 ch );
+void vol_reset();
+
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/batt_params.c b/tags/2.03_SDK-3.1/batt_params.c
new file mode 100644
index 0000000..74d87df
--- /dev/null
+++ b/tags/2.03_SDK-3.1/batt_params.c
@@ -0,0 +1,84 @@
+#include "jhl_defs.h"
+
+#include "batt_params.h"
+
+/* ========================================================
+    �e�Ѓo�b�e���[�p�����[�^
+ ======================================================== */
+const bt_param_ bt_param[ _BT_PARAM_NUM_ ] =
+{
+    // ctr ////////////////////////////////////////////////
+    // BT_PARAM_CTR_MAXELL
+    {
+        {
+            0xAE, 0xF0, 0xB4, 0x30, 0xB7, 0x40, 0xBA, 0x30,
+            0xBB, 0x50, 0xBB, 0xB0, 0xBC, 0x50, 0xBD, 0x10,
+            0xBD, 0x60, 0xBD, 0xB0, 0xBF, 0xE0, 0xC2, 0xB0,
+            0xC4, 0x20, 0xC7, 0xB0, 0xCA, 0xE0, 0xCE, 0x10,
+            0x01, 0xF0, 0x14, 0x10, 0x14, 0x20, 0x06, 0x30,
+            0x63, 0x90, 0x49, 0x00, 0x6E, 0x00, 0x77, 0x70,
+            0x7B, 0x00, 0x19, 0x00, 0x19, 0x00, 0x17, 0xF0,
+            0x1C, 0x60, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00
+            },
+        2,
+        { 92, (u8)(-256* 0.79), (u8)(-256* 4.35) },
+        0xD800,
+        { 0xEA, 0xE8 }
+    },
+
+    // BT_PARAM_CTR_PANA
+    {
+        {
+            0x8C, 0x30, 0x9C, 0x10, 0xA5, 0xE0, 0xB0, 0x40,
+            0xB1, 0xC0, 0xB2, 0x00, 0xB2, 0x50, 0xB3, 0x10,
+            0xB4, 0x90, 0xB6, 0x20, 0xB8, 0x60, 0xBA, 0x50,
+            0xBF, 0xA0, 0xC6, 0xB0, 0xCE, 0x90, 0xD0, 0x20,
+            0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20,
+            0x7B, 0x30, 0x68, 0x60, 0x20, 0x00, 0x17, 0x00,
+            0x17, 0x30, 0x12, 0xF0, 0x0D, 0xE0, 0x07, 0xF0,
+            0x07, 0x00, 0x09, 0x30, 0x01, 0xC0, 0x01, 0xC0
+            },
+        1,
+        { 171, (u8)(-256* 1.00), (u8)(-256* 2.60) },
+        0xDA20,
+        { 0x69, 0x67 },
+    },
+
+    // spfl ///////////////////////////////////////////////
+    // BT_PARAM_SPFL_MAXELL
+    {
+        {
+            0xA1, 0x20, 0xB7, 0x50, 0xB9, 0xD0, 0xBB, 0x00, 
+            0xBC, 0x30, 0xBC, 0x60, 0xBC, 0xA0, 0xBD, 0x10,
+            0xBD, 0xC0, 0xBE, 0x70, 0xBF, 0xD0, 0xC2, 0xA0,
+            0xC4, 0x00, 0xC8, 0x50, 0xCC, 0x80, 0xD0, 0xB0, 
+            0x01, 0xA0, 0x25, 0x10, 0x18, 0xB0, 0x17, 0xC0,
+            0x95, 0x20, 0x6F, 0xE0, 0x7C, 0x60, 0x35, 0x10,
+            0x35, 0x00, 0x37, 0xF0, 0x16, 0xF0, 0x1C, 0xA0,
+            0x17, 0x30, 0x11, 0xD0, 0x11, 0xF0, 0x11, 0xF0
+            },
+        2,
+        { 94, (u8)(-256* 0.35), (u8)(-256* 3.85) },
+        0xDAB0,
+        { 0xF5, 0xF3 }
+    },
+
+    // BT_PARAM_SPFL_PANA  !!dummy!!
+    {
+        {
+            0x8C, 0x30, 0x9C, 0x10, 0xA5, 0xE0, 0xB0, 0x40,
+            0xB1, 0xC0, 0xB2, 0x00, 0xB2, 0x50, 0xB3, 0x10,
+            0xB4, 0x90, 0xB6, 0x20, 0xB8, 0x60, 0xBA, 0x50,
+            0xBF, 0xA0, 0xC6, 0xB0, 0xCE, 0x90, 0xD0, 0x20,
+            0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20,
+            0x7B, 0x30, 0x68, 0x60, 0x20, 0x00, 0x17, 0x00,
+            0x17, 0x30, 0x12, 0xF0, 0x0D, 0xE0, 0x07, 0xF0,
+            0x07, 0x00, 0x09, 0x30, 0x01, 0xC0, 0x01, 0xC0
+            },
+        1,
+        { 171, (u8)(-256* 1.00), (u8)(-256* 2.60) },
+        0xDA20,
+        { 0x69, 0x67 },
+    }
+};
+
diff --git a/tags/2.03_SDK-3.1/batt_params.h b/tags/2.03_SDK-3.1/batt_params.h
new file mode 100644
index 0000000..343b3f4
--- /dev/null
+++ b/tags/2.03_SDK-3.1/batt_params.h
@@ -0,0 +1,49 @@
+#ifndef _bt_params_h_
+#define _bt_params_h_
+
+#include "jhl_defs.h"
+/*
+   �d�r����        CTR   | SPFL | YBS
+      0   ID = 0  maxell    ��
+    120        1
+    360        2
+    750 �@     3
+    1.3k�@     4
+    2.7k       5   pana     ��
+    8.2k�@     6
+*/
+
+
+typedef enum
+{
+    BT_PARAM_CTR_MAXELL = 0,
+    BT_PARAM_CTR_PANA,
+    BT_PARAM_SPFL_MAXELL,
+    BT_PARAM_SPFL_PANA,
+    BT_PARAM_SHRIMP_MAXELL,
+    BT_PARAM_SHRIMP_PANA,
+    _BT_PARAM_NUM_
+} BT_TYPE;
+
+typedef struct
+{
+    u8 rcomp;
+    s16 up,down;
+} rcomp_;
+
+typedef struct
+{
+    u8 hi,low;
+} verify_;
+
+typedef struct
+{
+    u8 mg_param[64];
+    u8 v_scale;
+    rcomp_ rcomp;
+    u16 ocv;
+    verify_ verify;
+} bt_param_;
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/bsr.hex b/tags/2.03_SDK-3.1/bsr.hex
new file mode 100644
index 0000000..1afe94a
--- /dev/null
+++ b/tags/2.03_SDK-3.1/bsr.hex
@@ -0,0 +1,995 @@
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diff --git a/tags/2.03_SDK-3.1/bsr.lmf b/tags/2.03_SDK-3.1/bsr.lmf
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literal 0
HcmV?d00001

diff --git a/tags/2.03_SDK-3.1/bsr_k0r.map b/tags/2.03_SDK-3.1/bsr_k0r.map
new file mode 100644
index 0000000..9284d37
--- /dev/null
+++ b/tags/2.03_SDK-3.1/bsr_k0r.map
@@ -0,0 +1,830 @@
+
+
+
+78K0R Linker W1.33                            Date: 2 Sep 2011 Page:   1
+
+Command:   -yc:\program files (x86)\nec electronics tools\dev -_msgoff -
+           obsr.lmf ..\..\..\Program Files (x86)\NEC Electronics Tools\C
+           C78K0R\W2.13\lib78k0r\s0rm.rel -gi1B339499E033F240BFAAh -pbsr
+           _k0r.map -nkd -gb7EFBFFh -bC:\Program Files (x86)\NEC Electro
+           nics Tools\CC78K0R\W2.13\lib78k0r\fsl.lib -bcl0rdm.lib -bcl0r
+           m.lib -bcl0rmf.lib -iC:\Program Files (x86)\NEC Electronics T
+           ools\CC78K0R\W2.13\lib78k0r -dbsr_mcu.dr -s -w2 loader.rel pm
+           .rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_t
+           wl.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel reng
+           e.rel accero.rel self_flash.rel sw.rel task_debug.rel task_mi
+           sc.rel task_sys.rel pedo_alg_thre_det2.rel ini_VECT.rel task_
+           status.rel led_cam.rel led_pow.rel hal.rel batt_params.rel vo
+           ltable.rel pedo_lpf_coeff.rel kanaria.rel kanaria_c.rel get_e
+           i.rel
+Para-file:
+Out-file:  bsr.lmf
+Map-file:  bsr_k0r.map
+Direc-file:bsr_mcu.dr
+
+
+*** Link information ***
+
+    71 output segment(s)
+ 3D17H byte(s) real data
+  6305 symbol(s) defined
+
+
+*** Memory map ***
+
+
+  SPACE=REGULAR
+
+  MEMORY=BCL0
+  BASE ADDRESS=00000H   SIZE=01000H
+         OUTPUT   INPUT    INPUT      BASE      SIZE
+         SEGMENT  SEGMENT  MODULE     ADDRESS
+         @@VECT00                     00000H    00002H  CSEG AT
+                  @@VECT00 @cstart    00000H    00002H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL loader     00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL WDT        00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL i2c_mcu    00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL self_flash
+                                      00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL task_debug
+                                      00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL task_status
+                                      00002H    00000H
+         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
+                  LDR_CNSL hal        00002H    00000H
+* gap *                               00002H    0000EH
+         @@VECT10                     00010H    00004H  CSEG AT
+                  @@VECT10 ini_VECT   00010H    00004H
+* gap *                               00014H    00008H
+         @@VECT1C                     0001CH    00002H  CSEG AT
+                  @@VECT1C ini_VECT   0001CH    00002H
+* gap *                               0001EH    00006H
+         @@VECT24                     00024H    00002H  CSEG AT
+                  @@VECT24 ini_VECT   00024H    00002H
+* gap *                               00026H    00004H
+         @@VECT2A                     0002AH    00002H  CSEG AT
+                  @@VECT2A i2c_twl    0002AH    00002H
+* gap *                               0002CH    00008H
+         @@VECT34                     00034H    00008H  CSEG AT
+                  @@VECT34 ini_VECT   00034H    00008H
+* gap *                               0003CH    0000EH
+         @@VECT4A                     0004AH    00002H  CSEG AT
+                  @@VECT4A ini_VECT   0004AH    00002H
+* gap *                               0004CH    0000EH
+         @@VECT5A                     0005AH    00002H  CSEG AT
+                  @@VECT5A i2c_ctr    0005AH    00002H
+* gap *                               0005CH    00006H
+         @@VECT62                     00062H    00002H  CSEG AT
+                  @@VECT62 accero     00062H    00002H
+* gap *                               00064H    0001CH
+         @@CALT                       00080H    00006H  CSEG CALLT0
+                  @@CALT   @cstart    00080H    00000H
+                  @@CALT   loader     00080H    00000H
+                  @@CALT   pm         00080H    00000H
+                  @@CALT   i2c_ctr    00080H    00000H
+                  @@CALT   main       00080H    00000H
+                  @@CALT   magic      00080H    00000H
+                  @@CALT   WDT        00080H    00000H
+                  @@CALT   i2c_mcu    00080H    00000H
+                  @@CALT   i2c_twl    00080H    00000H
+                  @@CALT   led        00080H    00000H
+                  @@CALT   rtc        00080H    00000H
+                  @@CALT   vreg_ctr   00080H    00000H
+                  @@CALT   vreg_twl   00080H    00000H
+                  @@CALT   adc        00080H    00000H
+                  @@CALT   renge      00080H    00006H
+                  @@CALT   accero     00086H    00000H
+                  @@CALT   self_flash
+                                      00086H    00000H
+                  @@CALT   sw         00086H    00000H
+                  @@CALT   task_debug
+                                      00086H    00000H
+                  @@CALT   task_misc
+                                      00086H    00000H
+                  @@CALT   task_sys   00086H    00000H
+                  @@CALT   pedo_alg_thre_det2
+                                      00086H    00000H
+                  @@CALT   ini_VECT   00086H    00000H
+                  @@CALT   task_status
+                                      00086H    00000H
+                  @@CALT   led_cam    00086H    00000H
+                  @@CALT   led_pow    00086H    00000H
+                  @@CALT   hal        00086H    00000H
+                  @@CALT   batt_params
+                                      00086H    00000H
+                  @@CALT   voltable   00086H    00000H
+                  @@CALT   pedo_lpf_coeff
+                                      00086H    00000H
+                  @@CALT   kanaria_c
+                                      00086H    00000H
+* gap *                               00086H    0003AH
+         ?CSEGOB0                     000C0H    00004H  CSEG OPT_BYTE
+         @@CODE                       000C4H    00000H  CSEG BASE
+                  @@CODE   magic      000C4H    00000H
+                  @@CODE   ini_VECT   000C4H    00000H
+                  @@CODE   batt_params
+                                      000C4H    00000H
+         LDR_CODL                     000C4H    00000H  CSEG
+                  LDR_CODL loader     000C4H    00000H
+                  LDR_CODL WDT        000C4H    00000H
+                  LDR_CODL i2c_mcu    000C4H    00000H
+                  LDR_CODL self_flash
+                                      000C4H    00000H
+                  LDR_CODL task_debug
+                                      000C4H    00000H
+                  LDR_CODL task_status
+                                      000C4H    00000H
+                  LDR_CODL hal        000C4H    00000H
+         ?CSEGSI                      000C4H    0000AH  CSEG
+         LDR_CODE                     000CEH    0093CH  CSEG
+                  LDR_CODE loader     000CEH    0019FH
+                  LDR_CODE WDT        0026DH    00000H
+                  LDR_CODE i2c_mcu    0026DH    002D9H
+                  LDR_CODE self_flash
+                                      00546H    00373H
+                  LDR_CODE task_debug
+                                      008B9H    00000H
+                  LDR_CODE task_status
+                                      008B9H    00075H
+                  LDR_CODE hal        0092EH    000DCH
+         FSL_CODE                     00A0AH    00322H  CSEG
+                  FSL_CODE fsl_block_cmd
+                                      00A0AH    0002BH
+                  FSL_CODE fsl_block_check
+                                      00A35H    00013H
+                  FSL_CODE fsl_common
+                                      00A48H    0014FH
+                  FSL_CODE fsl_reset
+                                      00B97H    00001H
+                  FSL_CODE fsl_si_ibf
+                                      00B98H    00064H
+                  FSL_CODE fsl_phySwap
+                                      00BFCH    0004DH
+                  FSL_CODE fsl_si_common
+                                      00C49H    00061H
+                  FSL_CODE fsl_swap   00CAAH    00030H
+                  FSL_CODE fsl_write
+                                      00CDAH    00052H
+         @@LCODE                      00D2CH    00277H  CSEG
+                  @@LCODE  @cstart    00D2CH    0006DH
+                  @@LCODE  @imul      00D99H    00011H
+                  @@LCODE  @lumul     00DAAH    0002BH
+                  @@LCODE  @isdiv     00DD5H    00022H
+                  @@LCODE  @iudiv     00DF7H    0002DH
+                  @@LCODE  @isrem     00E24H    00021H
+                  @@LCODE  @iurem     00E45H    0002FH
+                  @@LCODE  @lsdiv     00E74H    00039H
+                  @@LCODE  @ludiv     00EADH    0003FH
+                  @@LCODE  @divuw     00EECH    00034H
+                  @@LCODE  @ladd      00F20H    0000FH
+                  @@LCODE  @llsh      00F2FH    0001BH
+                  @@LCODE  @lursh     00F4AH    0001FH
+                  @@LCODE  @iscmp     00F69H    0000CH
+                  @@LCODE  @lband     00F75H    00014H
+                  @@LCODE  @bcdtob    00F89H    0001AH
+* gap *                               00FA3H    00053H
+         MGC_LOAD                     00FF6H    0000AH  CSEG AT
+                  MGC_LOAD magic      00FF6H    0000AH
+
+  MEMORY=ROM
+  BASE ADDRESS=02000H   SIZE=03000H
+         OUTPUT   INPUT    INPUT      BASE      SIZE
+         SEGMENT  SEGMENT  MODULE     ADDRESS
+         MGC_MIMI                     02000H    0000AH  CSEG AT
+                  MGC_MIMI magic      02000H    0000AH
+         @@CNST                       0200AH    00282H  CSEG
+                  @@CNST   @cstart    0200AH    00000H
+                  @@CNST   loader     0200AH    00000H
+                  @@CNST   pm         0200AH    00008H
+                  @@CNST   i2c_ctr    02012H    00000H
+                  @@CNST   main       02012H    00000H
+                  @@CNST   magic      02012H    00000H
+                  @@CNST   WDT        02012H    00000H
+                  @@CNST   i2c_mcu    02012H    00000H
+                  @@CNST   i2c_twl    02012H    00000H
+                  @@CNST   led        02012H    00000H
+                  @@CNST   rtc        02012H    00000H
+                  @@CNST   vreg_ctr   02012H    00000H
+                  @@CNST   vreg_twl   02012H    00000H
+                  @@CNST   adc        02012H    00008H
+                  @@CNST   renge      0201AH    00000H
+                  @@CNST   accero     0201AH    00000H
+                  @@CNST   self_flash
+                                      0201AH    00002H
+                  @@CNST   sw         0201CH    00000H
+                  @@CNST   task_debug
+                                      0201CH    00000H
+                  @@CNST   task_misc
+                                      0201CH    00000H
+                  @@CNST   task_sys   0201CH    00000H
+                  @@CNST   pedo_alg_thre_det2
+                                      0201CH    00018H
+                  @@CNST   ini_VECT   02034H    00000H
+                  @@CNST   task_status
+                                      02034H    00000H
+                  @@CNST   led_cam    02034H    00000H
+                  @@CNST   led_pow    02034H    00020H
+                  @@CNST   hal        02054H    00000H
+                  @@CNST   batt_params
+                                      02054H    001C8H
+                  @@CNST   voltable   0221CH    00040H
+                  @@CNST   pedo_lpf_coeff
+                                      0225CH    00030H
+                  @@CNST   kanaria_c
+                                      0228CH    00000H
+         ROM_CODE                     0228CH    0249EH  CSEG
+                  ROM_CODE pm         0228CH    0098CH
+                  ROM_CODE i2c_ctr    02C18H    0005CH
+                  ROM_CODE main       02C74H    00055H
+                  ROM_CODE i2c_twl    02CC9H    0005EH
+                  ROM_CODE led        02D27H    0024FH
+                  ROM_CODE rtc        02F76H    000E0H
+                  ROM_CODE vreg_ctr   03056H    0047DH
+                  ROM_CODE vreg_twl   034D3H    000F9H
+                  ROM_CODE adc        035CCH    00261H
+                  ROM_CODE renge      0382DH    00018H
+                  ROM_CODE accero     03845H    00146H
+                  ROM_CODE sw         0398BH    00126H
+                  ROM_CODE task_misc
+                                      03AB1H    001E7H
+                  ROM_CODE task_sys   03C98H    00381H
+                  ROM_CODE pedo_alg_thre_det2
+                                      04019H    004D4H
+                  ROM_CODE led_cam    044EDH    000BBH
+                  ROM_CODE led_pow    045A8H    0016FH
+                  ROM_CODE voltable   04717H    00000H
+                  ROM_CODE pedo_lpf_coeff
+                                      04717H    00000H
+                  ROM_CODE kanaria_c
+                                      04717H    00006H
+                  ROM_CODE get_ei     0471DH    0000DH
+         @@BASE                       0472AH    0064EH  CSEG BASE
+                  @@BASE   loader     0472AH    00000H
+                  @@BASE   pm         0472AH    0003EH
+                  @@BASE   i2c_ctr    04768H    00170H
+                  @@BASE   main       048D8H    00000H
+                  @@BASE   magic      048D8H    00000H
+                  @@BASE   WDT        048D8H    00000H
+                  @@BASE   i2c_mcu    048D8H    000F2H
+                  @@BASE   i2c_twl    049CAH    000D0H
+                  @@BASE   led        04A9AH    00000H
+                  @@BASE   rtc        04A9AH    0005DH
+                  @@BASE   vreg_ctr   04AF7H    00000H
+                  @@BASE   vreg_twl   04AF7H    00000H
+                  @@BASE   adc        04AF7H    00094H
+                  @@BASE   renge      04B8BH    0016CH
+                  @@BASE   accero     04CF7H    00049H
+                  @@BASE   self_flash
+                                      04D40H    00000H
+                  @@BASE   sw         04D40H    00000H
+                  @@BASE   task_debug
+                                      04D40H    00000H
+                  @@BASE   task_misc
+                                      04D40H    00000H
+                  @@BASE   task_sys   04D40H    00000H
+                  @@BASE   pedo_alg_thre_det2
+                                      04D40H    00000H
+                  @@BASE   ini_VECT   04D40H    00038H
+                  @@BASE   task_status
+                                      04D78H    00000H
+                  @@BASE   led_cam    04D78H    00000H
+                  @@BASE   led_pow    04D78H    00000H
+                  @@BASE   hal        04D78H    00000H
+                  @@BASE   batt_params
+                                      04D78H    00000H
+                  @@BASE   voltable   04D78H    00000H
+                  @@BASE   pedo_lpf_coeff
+                                      04D78H    00000H
+                  @@BASE   kanaria_c
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  @cstart    04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  pm         04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  i2c_ctr    04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  main       04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  i2c_twl    04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  led        04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  rtc        04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  vreg_ctr   04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  vreg_twl   04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  adc        04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  renge      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  accero     04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  sw         04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  task_misc
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  task_sys   04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  pedo_alg_thre_det2
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  ini_VECT   04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  led_cam    04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  led_pow    04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  batt_params
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  voltable   04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  pedo_lpf_coeff
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    00000H  CSEG PAGE64KP
+                  @@CNSTL  kanaria_c
+                                      04D78H    00000H
+         @@CNSTL                      04D78H    0000AH  CSEG PAGE64KP
+                  @@CNSTL  @bcdtob    04D78H    0000AH
+         @@R_INIT                     04D82H    0004AH  CSEG UNIT64KP
+                  @@R_INIT @cstart    04D82H    00000H
+                  @@R_INIT loader     04D82H    00000H
+                  @@R_INIT pm         04D82H    00000H
+                  @@R_INIT i2c_ctr    04D82H    00000H
+                  @@R_INIT main       04D82H    00000H
+                  @@R_INIT magic      04D82H    00000H
+                  @@R_INIT WDT        04D82H    00000H
+                  @@R_INIT i2c_mcu    04D82H    00000H
+                  @@R_INIT i2c_twl    04D82H    00000H
+                  @@R_INIT led        04D82H    00000H
+                  @@R_INIT rtc        04D82H    00000H
+                  @@R_INIT vreg_ctr   04D82H    00000H
+                  @@R_INIT vreg_twl   04D82H    00000H
+                  @@R_INIT adc        04D82H    0000CH
+                  @@R_INIT renge      04D8EH    00014H
+                  @@R_INIT accero     04DA2H    00000H
+                  @@R_INIT self_flash
+                                      04DA2H    00000H
+                  @@R_INIT sw         04DA2H    00000H
+                  @@R_INIT task_debug
+                                      04DA2H    00000H
+                  @@R_INIT task_misc
+                                      04DA2H    00026H
+                  @@R_INIT task_sys   04DC8H    00000H
+                  @@R_INIT pedo_alg_thre_det2
+                                      04DC8H    00000H
+                  @@R_INIT ini_VECT   04DC8H    00000H
+                  @@R_INIT task_status
+                                      04DC8H    00000H
+                  @@R_INIT led_cam    04DC8H    00000H
+                  @@R_INIT led_pow    04DC8H    00004H
+                  @@R_INIT hal        04DCCH    00000H
+                  @@R_INIT batt_params
+                                      04DCCH    00000H
+                  @@R_INIT voltable   04DCCH    00000H
+                  @@R_INIT pedo_lpf_coeff
+                                      04DCCH    00000H
+                  @@R_INIT kanaria_c
+                                      04DCCH    00000H
+                  @@R_INIT @rom       04DCCH    00000H
+         @@R_INIS                     04DCCH    00010H  CSEG UNIT64KP
+                  @@R_INIS @cstart    04DCCH    00000H
+                  @@R_INIS loader     04DCCH    00000H
+                  @@R_INIS pm         04DCCH    00002H
+                  @@R_INIS i2c_ctr    04DCEH    00002H
+                  @@R_INIS main       04DD0H    00000H
+                  @@R_INIS magic      04DD0H    00000H
+                  @@R_INIS WDT        04DD0H    00000H
+                  @@R_INIS i2c_mcu    04DD0H    00000H
+                  @@R_INIS i2c_twl    04DD0H    00000H
+                  @@R_INIS led        04DD0H    00000H
+                  @@R_INIS rtc        04DD0H    00000H
+                  @@R_INIS vreg_ctr   04DD0H    00000H
+                  @@R_INIS vreg_twl   04DD0H    00000H
+                  @@R_INIS adc        04DD0H    00000H
+                  @@R_INIS renge      04DD0H    00000H
+                  @@R_INIS accero     04DD0H    00000H
+                  @@R_INIS self_flash
+                                      04DD0H    00000H
+                  @@R_INIS sw         04DD0H    00000H
+                  @@R_INIS task_debug
+                                      04DD0H    00000H
+                  @@R_INIS task_misc
+                                      04DD0H    00000H
+                  @@R_INIS task_sys   04DD0H    00002H
+                  @@R_INIS pedo_alg_thre_det2
+                                      04DD2H    00006H
+                  @@R_INIS ini_VECT   04DD8H    00000H
+                  @@R_INIS task_status
+                                      04DD8H    00000H
+                  @@R_INIS led_cam    04DD8H    00002H
+                  @@R_INIS led_pow    04DDAH    00002H
+                  @@R_INIS hal        04DDCH    00000H
+                  @@R_INIS batt_params
+                                      04DDCH    00000H
+                  @@R_INIS voltable   04DDCH    00000H
+                  @@R_INIS pedo_lpf_coeff
+                                      04DDCH    00000H
+                  @@R_INIS kanaria_c
+                                      04DDCH    00000H
+                  @@R_INIS @rom       04DDCH    00000H
+         @@RLINIT                     04DDCH    00000H  CSEG UNIT64KP
+                  @@RLINIT loader     04DDCH    00000H
+                  @@RLINIT pm         04DDCH    00000H
+                  @@RLINIT i2c_ctr    04DDCH    00000H
+                  @@RLINIT main       04DDCH    00000H
+                  @@RLINIT magic      04DDCH    00000H
+                  @@RLINIT WDT        04DDCH    00000H
+                  @@RLINIT i2c_mcu    04DDCH    00000H
+                  @@RLINIT i2c_twl    04DDCH    00000H
+                  @@RLINIT led        04DDCH    00000H
+                  @@RLINIT rtc        04DDCH    00000H
+                  @@RLINIT vreg_ctr   04DDCH    00000H
+                  @@RLINIT vreg_twl   04DDCH    00000H
+                  @@RLINIT adc        04DDCH    00000H
+                  @@RLINIT renge      04DDCH    00000H
+                  @@RLINIT accero     04DDCH    00000H
+                  @@RLINIT self_flash
+                                      04DDCH    00000H
+                  @@RLINIT sw         04DDCH    00000H
+                  @@RLINIT task_debug
+                                      04DDCH    00000H
+                  @@RLINIT task_misc
+                                      04DDCH    00000H
+                  @@RLINIT task_sys   04DDCH    00000H
+                  @@RLINIT pedo_alg_thre_det2
+                                      04DDCH    00000H
+                  @@RLINIT ini_VECT   04DDCH    00000H
+                  @@RLINIT task_status
+                                      04DDCH    00000H
+                  @@RLINIT led_cam    04DDCH    00000H
+                  @@RLINIT led_pow    04DDCH    00000H
+                  @@RLINIT hal        04DDCH    00000H
+                  @@RLINIT batt_params
+                                      04DDCH    00000H
+                  @@RLINIT voltable   04DDCH    00000H
+                  @@RLINIT pedo_lpf_coeff
+                                      04DDCH    00000H
+                  @@RLINIT kanaria_c
+                                      04DDCH    00000H
+                  @@RLINIT @rom       04DDCH    00000H
+         @@CODEL                      04DDCH    00000H  CSEG
+                  @@CODEL  pm         04DDCH    00000H
+                  @@CODEL  i2c_ctr    04DDCH    00000H
+                  @@CODEL  main       04DDCH    00000H
+                  @@CODEL  magic      04DDCH    00000H
+                  @@CODEL  i2c_twl    04DDCH    00000H
+                  @@CODEL  led        04DDCH    00000H
+                  @@CODEL  rtc        04DDCH    00000H
+                  @@CODEL  vreg_ctr   04DDCH    00000H
+                  @@CODEL  vreg_twl   04DDCH    00000H
+                  @@CODEL  adc        04DDCH    00000H
+                  @@CODEL  renge      04DDCH    00000H
+                  @@CODEL  accero     04DDCH    00000H
+                  @@CODEL  sw         04DDCH    00000H
+                  @@CODEL  task_misc
+                                      04DDCH    00000H
+                  @@CODEL  task_sys   04DDCH    00000H
+                  @@CODEL  pedo_alg_thre_det2
+                                      04DDCH    00000H
+                  @@CODEL  ini_VECT   04DDCH    00000H
+                  @@CODEL  led_cam    04DDCH    00000H
+                  @@CODEL  led_pow    04DDCH    00000H
+                  @@CODEL  batt_params
+                                      04DDCH    00000H
+                  @@CODEL  voltable   04DDCH    00000H
+                  @@CODEL  pedo_lpf_coeff
+                                      04DDCH    00000H
+                  @@CODEL  kanaria_c
+                                      04DDCH    00000H
+         @@LCODEL                     04DDCH    00022H  CSEG
+                  @@LCODEL abs        04DDCH    00008H
+                  @@LCODEL memcpy_n   04DE4H    0001AH
+* gap *                               04DFEH    001F6H
+         MGC_VER                      04FF4H    00002H  CSEG AT
+                  MGC_VER  magic      04FF4H    00002H
+         MGC_TAIL                     04FF6H    0000AH  CSEG AT
+                  MGC_TAIL magic      04FF6H    0000AH
+
+  MEMORY=RAM
+  BASE ADDRESS=FF900H   SIZE=00500H
+         OUTPUT   INPUT    INPUT      BASE      SIZE
+         SEGMENT  SEGMENT  MODULE     ADDRESS
+         @@DATA                       FF900H    003CCH  DSEG BASEP
+                  @@DATA   @cstart    FF900H    00002H
+                  @@DATA   loader     FF902H    00000H
+                  @@DATA   pm         FF902H    00002H
+                  @@DATA   i2c_ctr    FF904H    00000H
+                  @@DATA   main       FF904H    0021EH
+                  @@DATA   magic      FFB22H    00000H
+                  @@DATA   WDT        FFB22H    00000H
+                  @@DATA   i2c_mcu    FFB22H    00004H
+                  @@DATA   i2c_twl    FFB26H    00000H
+                  @@DATA   led        FFB26H    00076H
+                  @@DATA   rtc        FFB9CH    00008H
+                  @@DATA   vreg_ctr   FFBA4H    0005CH
+                  @@DATA   vreg_twl   FFC00H    00010H
+                  @@DATA   adc        FFC10H    00000H
+                  @@DATA   renge      FFC10H    00014H
+                  @@DATA   accero     FFC24H    00000H
+                  @@DATA   self_flash
+                                      FFC24H    00002H
+                  @@DATA   sw         FFC26H    00000H
+                  @@DATA   task_debug
+                                      FFC26H    00000H
+                  @@DATA   task_misc
+                                      FFC26H    00008H
+                  @@DATA   task_sys   FFC2EH    00000H
+                  @@DATA   pedo_alg_thre_det2
+                                      FFC2EH    00098H
+                  @@DATA   ini_VECT   FFCC6H    00000H
+                  @@DATA   task_status
+                                      FFCC6H    00000H
+                  @@DATA   led_cam    FFCC6H    00000H
+                  @@DATA   led_pow    FFCC6H    00006H
+                  @@DATA   hal        FFCCCH    00000H
+                  @@DATA   batt_params
+                                      FFCCCH    00000H
+                  @@DATA   voltable   FFCCCH    00000H
+                  @@DATA   pedo_lpf_coeff
+                                      FFCCCH    00000H
+                  @@DATA   kanaria    FFCCCH    00000H
+                  @@DATA   kanaria_c
+                                      FFCCCH    00000H
+                  @@DATA   @rom       FFCCCH    00000H
+         @@INIT                       FFCCCH    0004AH  DSEG BASEP
+                  @@INIT   @cstart    FFCCCH    00000H
+                  @@INIT   loader     FFCCCH    00000H
+                  @@INIT   pm         FFCCCH    00000H
+                  @@INIT   i2c_ctr    FFCCCH    00000H
+                  @@INIT   main       FFCCCH    00000H
+                  @@INIT   magic      FFCCCH    00000H
+                  @@INIT   WDT        FFCCCH    00000H
+                  @@INIT   i2c_mcu    FFCCCH    00000H
+                  @@INIT   i2c_twl    FFCCCH    00000H
+                  @@INIT   led        FFCCCH    00000H
+                  @@INIT   rtc        FFCCCH    00000H
+                  @@INIT   vreg_ctr   FFCCCH    00000H
+                  @@INIT   vreg_twl   FFCCCH    00000H
+                  @@INIT   adc        FFCCCH    0000CH
+                  @@INIT   renge      FFCD8H    00014H
+                  @@INIT   accero     FFCECH    00000H
+                  @@INIT   self_flash
+                                      FFCECH    00000H
+                  @@INIT   sw         FFCECH    00000H
+                  @@INIT   task_debug
+                                      FFCECH    00000H
+                  @@INIT   task_misc
+                                      FFCECH    00026H
+                  @@INIT   task_sys   FFD12H    00000H
+                  @@INIT   pedo_alg_thre_det2
+                                      FFD12H    00000H
+                  @@INIT   ini_VECT   FFD12H    00000H
+                  @@INIT   task_status
+                                      FFD12H    00000H
+                  @@INIT   led_cam    FFD12H    00000H
+                  @@INIT   led_pow    FFD12H    00004H
+                  @@INIT   hal        FFD16H    00000H
+                  @@INIT   batt_params
+                                      FFD16H    00000H
+                  @@INIT   voltable   FFD16H    00000H
+                  @@INIT   pedo_lpf_coeff
+                                      FFD16H    00000H
+                  @@INIT   kanaria    FFD16H    00000H
+                  @@INIT   kanaria_c
+                                      FFD16H    00000H
+                  @@INIT   @rom       FFD16H    00000H
+         FSL_DATA                     FFD16H    00010H  DSEG UNITP
+                  FSL_DATA fsl_common
+                                      FFD16H    00010H
+         @@INITL                      FFD26H    00000H  DSEG UNIT64KP
+                  @@INITL  loader     FFD26H    00000H
+                  @@INITL  pm         FFD26H    00000H
+                  @@INITL  i2c_ctr    FFD26H    00000H
+                  @@INITL  main       FFD26H    00000H
+                  @@INITL  magic      FFD26H    00000H
+                  @@INITL  WDT        FFD26H    00000H
+                  @@INITL  i2c_mcu    FFD26H    00000H
+                  @@INITL  i2c_twl    FFD26H    00000H
+                  @@INITL  led        FFD26H    00000H
+                  @@INITL  rtc        FFD26H    00000H
+                  @@INITL  vreg_ctr   FFD26H    00000H
+                  @@INITL  vreg_twl   FFD26H    00000H
+                  @@INITL  adc        FFD26H    00000H
+                  @@INITL  renge      FFD26H    00000H
+                  @@INITL  accero     FFD26H    00000H
+                  @@INITL  self_flash
+                                      FFD26H    00000H
+                  @@INITL  sw         FFD26H    00000H
+                  @@INITL  task_debug
+                                      FFD26H    00000H
+                  @@INITL  task_misc
+                                      FFD26H    00000H
+                  @@INITL  task_sys   FFD26H    00000H
+                  @@INITL  pedo_alg_thre_det2
+                                      FFD26H    00000H
+                  @@INITL  ini_VECT   FFD26H    00000H
+                  @@INITL  task_status
+                                      FFD26H    00000H
+                  @@INITL  led_cam    FFD26H    00000H
+                  @@INITL  led_pow    FFD26H    00000H
+                  @@INITL  hal        FFD26H    00000H
+                  @@INITL  batt_params
+                                      FFD26H    00000H
+                  @@INITL  voltable   FFD26H    00000H
+                  @@INITL  pedo_lpf_coeff
+                                      FFD26H    00000H
+                  @@INITL  kanaria    FFD26H    00000H
+                  @@INITL  kanaria_c
+                                      FFD26H    00000H
+                  @@INITL  @rom       FFD26H    00000H
+         @@DATAL                      FFD26H    00000H  DSEG UNIT64KP
+                  @@DATAL  loader     FFD26H    00000H
+                  @@DATAL  pm         FFD26H    00000H
+                  @@DATAL  i2c_ctr    FFD26H    00000H
+                  @@DATAL  main       FFD26H    00000H
+                  @@DATAL  magic      FFD26H    00000H
+                  @@DATAL  WDT        FFD26H    00000H
+                  @@DATAL  i2c_mcu    FFD26H    00000H
+                  @@DATAL  i2c_twl    FFD26H    00000H
+                  @@DATAL  led        FFD26H    00000H
+                  @@DATAL  rtc        FFD26H    00000H
+                  @@DATAL  vreg_ctr   FFD26H    00000H
+                  @@DATAL  vreg_twl   FFD26H    00000H
+                  @@DATAL  adc        FFD26H    00000H
+                  @@DATAL  renge      FFD26H    00000H
+                  @@DATAL  accero     FFD26H    00000H
+                  @@DATAL  self_flash
+                                      FFD26H    00000H
+                  @@DATAL  sw         FFD26H    00000H
+                  @@DATAL  task_debug
+                                      FFD26H    00000H
+                  @@DATAL  task_misc
+                                      FFD26H    00000H
+                  @@DATAL  task_sys   FFD26H    00000H
+                  @@DATAL  pedo_alg_thre_det2
+                                      FFD26H    00000H
+                  @@DATAL  ini_VECT   FFD26H    00000H
+                  @@DATAL  task_status
+                                      FFD26H    00000H
+                  @@DATAL  led_cam    FFD26H    00000H
+                  @@DATAL  led_pow    FFD26H    00000H
+                  @@DATAL  hal        FFD26H    00000H
+                  @@DATAL  batt_params
+                                      FFD26H    00000H
+                  @@DATAL  voltable   FFD26H    00000H
+                  @@DATAL  pedo_lpf_coeff
+                                      FFD26H    00000H
+                  @@DATAL  kanaria    FFD26H    00000H
+                  @@DATAL  kanaria_c
+                                      FFD26H    00000H
+                  @@DATAL  @rom       FFD26H    00000H
+* gap *                               FFD26H    000DAH
+
+  MEMORY=RAM2
+  BASE ADDRESS=FFE20H   SIZE=000C0H
+         OUTPUT   INPUT    INPUT      BASE      SIZE
+         SEGMENT  SEGMENT  MODULE     ADDRESS
+         @@INIS                       FFE20H    00010H  DSEG SADDRP
+                  @@INIS   @cstart    FFE20H    00000H
+                  @@INIS   loader     FFE20H    00000H
+                  @@INIS   pm         FFE20H    00002H
+                  @@INIS   i2c_ctr    FFE22H    00002H
+                  @@INIS   main       FFE24H    00000H
+                  @@INIS   magic      FFE24H    00000H
+                  @@INIS   WDT        FFE24H    00000H
+                  @@INIS   i2c_mcu    FFE24H    00000H
+                  @@INIS   i2c_twl    FFE24H    00000H
+                  @@INIS   led        FFE24H    00000H
+                  @@INIS   rtc        FFE24H    00000H
+                  @@INIS   vreg_ctr   FFE24H    00000H
+                  @@INIS   vreg_twl   FFE24H    00000H
+                  @@INIS   adc        FFE24H    00000H
+                  @@INIS   renge      FFE24H    00000H
+                  @@INIS   accero     FFE24H    00000H
+                  @@INIS   self_flash
+                                      FFE24H    00000H
+                  @@INIS   sw         FFE24H    00000H
+                  @@INIS   task_debug
+                                      FFE24H    00000H
+                  @@INIS   task_misc
+                                      FFE24H    00000H
+                  @@INIS   task_sys   FFE24H    00002H
+                  @@INIS   pedo_alg_thre_det2
+                                      FFE26H    00006H
+                  @@INIS   ini_VECT   FFE2CH    00000H
+                  @@INIS   task_status
+                                      FFE2CH    00000H
+                  @@INIS   led_cam    FFE2CH    00002H
+                  @@INIS   led_pow    FFE2EH    00002H
+                  @@INIS   hal        FFE30H    00000H
+                  @@INIS   batt_params
+                                      FFE30H    00000H
+                  @@INIS   voltable   FFE30H    00000H
+                  @@INIS   pedo_lpf_coeff
+                                      FFE30H    00000H
+                  @@INIS   kanaria_c
+                                      FFE30H    00000H
+                  @@INIS   @rom       FFE30H    00000H
+         @@DATS                       FFE30H    00062H  DSEG SADDRP
+                  @@DATS   @cstart    FFE30H    00000H
+                  @@DATS   loader     FFE30H    00000H
+                  @@DATS   pm         FFE30H    00016H
+                  @@DATS   i2c_ctr    FFE46H    00004H
+                  @@DATS   main       FFE4AH    00000H
+                  @@DATS   magic      FFE4AH    00000H
+                  @@DATS   WDT        FFE4AH    00000H
+                  @@DATS   i2c_mcu    FFE4AH    00008H
+                  @@DATS   i2c_twl    FFE52H    00000H
+                  @@DATS   led        FFE52H    00006H
+                  @@DATS   rtc        FFE58H    00000H
+                  @@DATS   vreg_ctr   FFE58H    00004H
+                  @@DATS   vreg_twl   FFE5CH    00000H
+                  @@DATS   adc        FFE5CH    0000AH
+                  @@DATS   renge      FFE66H    00002H
+                  @@DATS   accero     FFE68H    00002H
+                  @@DATS   self_flash
+                                      FFE6AH    00000H
+                  @@DATS   sw         FFE6AH    0000CH
+                  @@DATS   task_debug
+                                      FFE76H    00000H
+                  @@DATS   task_misc
+                                      FFE76H    00004H
+                  @@DATS   task_sys   FFE7AH    00002H
+                  @@DATS   pedo_alg_thre_det2
+                                      FFE7CH    0000EH
+                  @@DATS   ini_VECT   FFE8AH    00000H
+                  @@DATS   task_status
+                                      FFE8AH    00002H
+                  @@DATS   led_cam    FFE8CH    00002H
+                  @@DATS   led_pow    FFE8EH    00004H
+                  @@DATS   hal        FFE92H    00000H
+                  @@DATS   batt_params
+                                      FFE92H    00000H
+                  @@DATS   voltable   FFE92H    00000H
+                  @@DATS   pedo_lpf_coeff
+                                      FFE92H    00000H
+                  @@DATS   kanaria_c
+                                      FFE92H    00000H
+                  @@DATS   @rom       FFE92H    00000H
+         @@BITS                       FFE92H    00006H  BSEG
+                  @@BITS   @cstart    FFE92H.0  00000H.0
+                  @@BITS   loader     FFE92H.0  00000H.0
+                  @@BITS   pm         FFE92H.0  00001H.1
+                  @@BITS   i2c_ctr    FFE93H.1  00000H.0
+                  @@BITS   main       FFE93H.1  00000H.1
+                  @@BITS   magic      FFE93H.2  00000H.0
+                  @@BITS   WDT        FFE93H.2  00000H.0
+                  @@BITS   i2c_mcu    FFE93H.2  00000H.4
+                  @@BITS   i2c_twl    FFE93H.6  00000H.0
+                  @@BITS   led        FFE93H.6  00000H.4
+                  @@BITS   rtc        FFE94H.2  00000H.3
+                  @@BITS   vreg_ctr   FFE94H.5  00000H.1
+                  @@BITS   vreg_twl   FFE94H.6  00000H.0
+                  @@BITS   adc        FFE94H.6  00000H.4
+                  @@BITS   renge      FFE95H.2  00000H.2
+                  @@BITS   accero     FFE95H.4  00000H.0
+                  @@BITS   self_flash
+                                      FFE95H.4  00000H.0
+                  @@BITS   sw         FFE95H.4  00000H.1
+                  @@BITS   task_debug
+                                      FFE95H.5  00000H.0
+                  @@BITS   task_misc
+                                      FFE95H.5  00000H.3
+                  @@BITS   task_sys   FFE96H.0  00000H.0
+                  @@BITS   pedo_alg_thre_det2
+                                      FFE96H.0  00000H.2
+                  @@BITS   ini_VECT   FFE96H.2  00000H.0
+                  @@BITS   task_status
+                                      FFE96H.2  00000H.0
+                  @@BITS   led_cam    FFE96H.2  00000H.1
+                  @@BITS   led_pow    FFE96H.3  00000H.0
+                  @@BITS   hal        FFE96H.3  00000H.6
+                  @@BITS   batt_params
+                                      FFE97H.1  00000H.0
+                  @@BITS   voltable   FFE97H.1  00000H.0
+                  @@BITS   pedo_lpf_coeff
+                                      FFE97H.1  00000H.0
+                  @@BITS   kanaria_c
+                                      FFE97H.1  00000H.0
+* gap *                               FFE98H    0003CH
+         @@SEGREG                     FFED4H    00004H  DSEG AT
+                  @@SEGREG @SEGREG    FFED4H    00004H
+         @@RTARG0                     FFED8H    00008H  DSEG AT
+                  @@RTARG0 @RTARG0    FFED8H    00008H
+
+
+ Target chip : uPD79F0104
+ Device file : E1.00b
+
\ No newline at end of file
diff --git a/tags/2.03_SDK-3.1/bsr_mcu.dr b/tags/2.03_SDK-3.1/bsr_mcu.dr
new file mode 100644
index 0000000..81aeecc
--- /dev/null
+++ b/tags/2.03_SDK-3.1/bsr_mcu.dr
@@ -0,0 +1,46 @@
+;;; �̈�̒�`
+;32kB = 0x7FFF
+MEMORY BCL0:     (00000H, 01000H )
+;MEMORY BCL1:    (01000H, 01000H )          ; �o�b�N�A�b�v�̈�
+MEMORY ROM :     (02000H, 03000H )
+;MEMORY ROM_BKUP:(05000H, 03000H )          ; �o�b�N�A�b�v�̈�
+;MEMORY OCD :(0FC00H, 00400H )          ; OCD���g���Ă���炵��
+
+
+;;; �Z�O�����g�̊�����ݒ�
+; �u�[�g�u���b�N0�Ɋ��蓖�Ă�
+MERGE LDR_CODE : =BCL0
+MERGE LDR_CODL : =BCL0
+MERGE FSL_CODE : =BCL0         ; =FSL ; �ސ��t���b�V�����C�u����
+MERGE @@LCODE  : =BCL0         ; �X�^�[�g�A�b�v���[�`��
+;MERGE @@LCODEL : =BCL0
+
+;MERGE LDR_RINT:=BCL0
+;MERGE LDR_CNST:=BCL0
+MERGE LDR_CNSL:=BCL0
+
+
+
+; �ʏ�̈�ɒu��
+MERGE ROM_CODE:=ROM
+MERGE @@CNST:    =ROM
+MERGE @@R_INIT:  =ROM        ; ROM�ȊO�ɒu�������Ȃ�X�^�[�g�A�b�v���[�`����v�C��
+
+
+
+
+
+
+; �}�W�b�N�i���o�[
+;; magic.c�̒��Ŏw��
+
+
+;--- RAM�̈� -------------------------------------------------------
+;
+; RAM1,RAM2�̈�̓��[�U�[�v���O�����Ŏg�p���Ă��ǂ��ł����A�Z���t�v���O��������
+; �Z���t�v���O�����̃��C�u�������g�p���邽�߁A�l�͔j�󂳂�܂��B
+;
+memory RAM      : (0FF900H, 0500H)     ; ���[�U�[�q�`�l�̈�
+;memory SLF_RAM : (0FF900H, 0020H)     ; Slef Program�\��̈�[�g�p�֎~]
+memory RAM2     : (0FFE20H, 00C0H)     ; �Z���t�v���O�������A�g�p�֎~�̈�
+;memory SLF_RAM : (0FFE00H, 0020H)     ; Slef Program�\��̈�[�g�p�֎~]
diff --git a/tags/2.03_SDK-3.1/bsr_system.h b/tags/2.03_SDK-3.1/bsr_system.h
new file mode 100644
index 0000000..bb6105f
--- /dev/null
+++ b/tags/2.03_SDK-3.1/bsr_system.h
@@ -0,0 +1,67 @@
+#ifndef __bsr_system__
+#define __bsr_system__
+
+// �C�x���g���[�v�̃X�e�[�g
+enum pwr_state_
+{
+  OFF_TRIG = 0,
+  ON_CHECK,
+  ON_TRIG,
+  ON,
+//  SLEEP_TRIG,
+  SLEEP,
+//  WAKE,
+  OFF,
+};
+
+enum poweron_reason_
+{
+  NONE = 0,
+  RSN_PWSW,
+  RSN_RTC_ALARM,
+  RSN_TRIAL,		// �̌���
+  RSN_RSV4,
+  RSN_RSV5
+};
+
+
+enum model_
+{
+  MODEL_JIKKI,
+  MODEL_TS_BOARD,
+  MODEL_SHIROBAKO,
+  MODEL_JIKKI_NOBATT,
+  MODEL_CAPTURE_BOX,
+  MODEL_ISBAKO,         // �������Asystem_status.model�� MODEL_JIKKI �ɂ��Ă����̂Ŗ��g�p
+  MODEL_RESERVED3,
+};
+
+enum family_
+{
+  FAMILY_CTR,
+  FAMILY_SPFL,
+  FAMILY_SHRIMP
+};
+
+// �^�X�N�V�X�e���̏�ԏ��Ȃ�
+typedef struct _system_status_
+{
+  enum pwr_state_ pwr_state;
+  enum poweron_reason_ poweron_reason;
+  unsigned char reboot:1;
+//  unsigned char info_fullcolor:1;
+  unsigned char captureBox:1;         // �L���v�`���� SDK�ɂ͎��@�ƕԂ�
+  unsigned char taikendai:1;
+  unsigned char taikendai_nbd:1;
+  unsigned char is_dev:1;
+  enum model_   model;
+  enum family_  family;
+}system_status_;
+
+extern bit force_off;
+
+extern system_status_ system_status;
+
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/config.h b/tags/2.03_SDK-3.1/config.h
new file mode 100644
index 0000000..71320cf
--- /dev/null
+++ b/tags/2.03_SDK-3.1/config.h
@@ -0,0 +1,94 @@
+#ifndef __config__
+#define __config__
+
+
+#define MCU_VER_MAJOR    0x02
+#define MCU_VER_MINOR    0x0E
+
+
+// �f�o�b�O�����X�C�b�`
+
+//#define _debug_led_				// LED print �f�o�b�O���������Ƃ�
+//#define _ALLOW_NOBATT_			// ���@�d�r�Ȃ��i=�A�_�v�^�̂݁j�ł̋N��������
+//#define _DBG_LED_PRINT_			// LED print �f�o�b�O���������Ƃ�(���ȃA�b�v�f�[�g�p)
+//#define _ENABLE_COMMAND3_			// mcu���Z�b�g��wdt�R�}���h��L���ɂ���
+//#define _FORCE_TAIKENDAI_
+//#define _FORCE_TAIKENDAI_NBD_
+
+//#define _DBG_CHK_OFF_LEAK_		// OFF�����[�N�d���̃`�F�b�N(�f�o�b�K�Ŋm�F)
+//#define _DBG_NOP_					// �u���[�N��\�邽�߂�NOP()��L���ɂ������Ƃ�
+
+//#define _ENABLE_HAL_				// �f�o�b�O�p��HAL��L���ɂ���B�R�����g�A�E�g�ŃX���[�ɂȂ�B
+//#define _ENABLE_PRESS_SEL_TO_WDT_	// SEL ��������WDT����
+
+//#define _DI_WITH_CHECK_			// ���荞�݋֎~���d�Ɋ|���Ȃ����`�F�b�N
+
+#ifdef  _DBG_NOP_					// �R�[�h��K�v��NOP�Ƌ�ʂ��邽��
+# define dbg_nop()	NOP()
+#else
+# define dbg_nop()	;
+#endif
+
+
+#define _I2C_ERR_ABORT_				// *�W����on* I2C�Ō돑�����݂炵��������������ȍ~�����@
+									//. �u���[�N�����Ă��S�R����������Ȃ��Ȃ�܂�����...
+
+// ����d�l�t�@�[��
+//#define _TAIKENDAI_
+//					home���j���[�ɓ���Ă��܂��̂�����������t�@�[�����‚���BROM������Ȃ��̂œd�r�p�����[�^������p�X����
+//#define _TAIKENDAI_SEISAN_SPECIAL_
+//					���Y���ɑ̌�������g�p�����ǂ���ƁA�A�_�v�^���Ȃ��Ɠd�������炸�Ɍ����Ɏx�Ⴊ����̂ňꎞ�t�@�[��
+//#define _RVD_
+//					�f�o�b�K�A�^�b�`���Ƀ^�[�Q�b�g���Z�b�g�œd�����؂�Ă��܂��̂����
+
+
+// �������̎��́��C���‚��Ȃ��Ƒ̌���̐��Y�ł��Ȃ�����ˁI
+#ifdef _TAIKENDAI_SEISAN_SPECIAL_
+#define MCU_VER_MINOR    0x80
+#endif
+
+
+#ifdef _TAIKENDAI_
+#define MCU_VER_MINOR    0x92
+// 0x90 1.31 �����@HOME�ɓ���Ă��܂��̂��X�C�b�`�̃}�X�N�ő΍�
+//                 ROM�s���̂��߁A�d�r�p�����[�^�폜
+
+#endif
+
+
+#define _firm_format_v3_
+
+//#define _MODEL_TEG2_
+      // ��TEG2 CPU �{ Type-T
+
+//#define _MODEL_WM0_
+//#define _MODEL_WM0_TEG2_CTRC_
+
+//#define _MODEL_TS0_
+      // ��TEG2 CPU �{ Type-C
+
+#define _MODEL_CTR_
+      // ��TS board, WM1,1 TS-CTRC, ���@
+
+
+// ---------------------------------- //
+#ifdef _MODEL_TEG2_
+unsupported!
+#endif
+
+
+#ifdef _MODEL_WM0_
+unsupported!
+#endif
+
+
+#ifdef _MODEL_TS0_
+unsupported!
+#endif
+
+#ifdef _MODEL_CTR_
+#define _PMIC_CTR_
+#define _MCU_BSR_
+#endif
+
+#endif
diff --git a/tags/2.03_SDK-3.1/fsl.h b/tags/2.03_SDK-3.1/fsl.h
new file mode 100644
index 0000000..0e806b5
--- /dev/null
+++ b/tags/2.03_SDK-3.1/fsl.h
@@ -0,0 +1,362 @@
+/*==============================================================================================*/
+/* Project      = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash    */
+/* Module       = fsl.h                                                                         */
+/* Version      = V1.01                                                                         */
+/* Date         = 28.03.2008 11:45:42                                                           */
+/*==============================================================================================*/
+/*                                  COPYRIGHT                                                   */
+/*==============================================================================================*/
+/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH,                                         */
+/*               a company of the NEC Electronics Corporation                                   */
+/*==============================================================================================*/
+/* Purpose:                                                                                     */
+/*              constant, type and function prototype definitions used by the FSL               */
+/*                                                                                              */
+/*==============================================================================================*/
+/*                                                                                              */
+/* Warranty Disclaimer                                                                          */
+/*                                                                                              */
+/* Because the Product(s) is licensed free of charge, there is no warranty of any kind          */
+/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied,        */
+/* including but not limited to those for non-infringement of intellectual property,            */
+/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */
+/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/
+/*                                                                                              */
+/* Each User is solely responsible for determining the appropriateness of using the Product(s)  */
+/* and assumes all risks associated with its exercise of rights under this Agreement,           */
+/* including, but not limited to the risks and costs of program errors, compliance with         */
+/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or     */
+/* interruption of operations.                                                                  */
+/*                                                                                              */
+/* Limitation of Liability                                                                      */
+/*                                                                                              */
+/* In no event shall NEC be liable to the User for any incidental, consequential, indirect,     */
+/* or punitive damage (including but not limited to lost profits) regardless of whether         */
+/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */
+/* failure of essential purpose or otherwise and even if advised of the possibility of          */
+/* such damages. NEC shall not be liable for any services or products provided by third party   */
+/* vendors, developers or consultants identified or referred to the User by NEC in connection   */
+/* with the Product(s) and/or the Application.                                                  */
+/*                                                                                              */
+/*==============================================================================================*/
+/* Environment: PM plus (V6.30)                                                                 */
+/*              RA78K0(V1.20)                                                                   */
+/*              CC78K0(V2.00)                                                                   */
+/*==============================================================================================*/
+
+#ifndef __FSL_H_INCLUDED
+#define __FSL_H_INCLUDED
+
+
+/*==============================================================================================*/
+/* FSL type definitions                                                                         */
+/*==============================================================================================*/
+typedef unsigned char fsl_u08;
+typedef unsigned int fsl_u16;
+typedef unsigned long int fsl_u32;
+
+
+/*==============================================================================================*/
+/* constant definitions                                                                         */
+/*==============================================================================================*/
+
+/*status code definitions returned by the FSL functions                                         */
+#define   FSL_OK                    0x00
+#define   FSL_ERR_FLMD0             0x01
+#define   FSL_ERR_PARAMETER         0x05
+#define   FSL_ERR_PROTECTION        0x10
+#define   FSL_ERR_ERASE             0x1A
+#define   FSL_ERR_BLANKCHECK        0x1B
+#define   FSL_ERR_IVERIFY           0x1B
+#define   FSL_ERR_WRITE             0x1C
+#define   FSL_ERR_EEP_IVERIFY       0x1D
+#define   FSL_ERR_EEP_BLANKCHECK    0x1E
+#define   FSL_ERR_INTERRUPTION      0x1F
+
+
+/*==============================================================================================*/
+/* global function prototypes                                                                   */
+/*==============================================================================================*/
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      initialization of selfprogramming environment                                  */
+/*               After initialization:                                                          */
+/*               - the pointer to the data-buffer is stored                                     */
+/*               - all timing data are re-calculated according to the used system clock         */
+/*                                                                                              */
+/*               CAUTION:                                                                       */
+/*               The FSL_Init(&data_buffer) function is interruptible. Please use the           */
+/*               FSL_Init_cont(&data_buffer) to recall it as long return status is 0x1F.        */
+/*                                                                                              */
+/* Input:        data_buffer_pu08 - pointer to a data buffer of N...256 bytes                   */
+/*                                 (used for data exchange between firmware and application)    */
+/* Output:       -                                                                              */
+/* Returned:     u08, status_code                                                               */
+/*                    = 0x00(FSL_OK), normal and means initialization OK                        */
+/*                    = 0x1F(FSL_ERR_INTERRUPTION), initialization interrupted by user interrupt*/
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_Init( fsl_u08 * data_buffer_pu08 );
+extern fsl_u08 FSL_Init_cont( fsl_u08 * data_buffer_pu08 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      checks the voltage level (high or low) at FLMD0 pin                            */
+/* Input:        -                                                                              */
+/* Output:       -                                                                              */
+/* Returned:     fsl_u08, status_code                                                           */
+/*                    = 0x00(FSL_OK), normal and means FLMD0=HIGH                               */
+/*                    = 0x01(FSL_ERR_FLMD0), error, FLMD0=LOW                                   */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_ModeCheck( void );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      checks if specified block is blank                                             */
+/* Input:        block_u16 - block number has to be checked                                     */
+/* Output:       -                                                                              */
+/* Returned:     fsl_u08, status_code                                                           */
+/*                    = 0x00(FSL_OK), normal and means "block is blank"                         */
+/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
+/*                    = 0x1B(FSL_ERR_BLANKCHECK), blank-check error, means "block not blank"    */
+/*                    = 0x1F(FSL_ERR_INTERRUPTION), blank-check interrupted by user interrupt   */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_BlankCheck( fsl_u16 block_u16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/*  Block type:   FSL command function                                                          */
+/*----------------------------------------------------------------------------------------------*/
+/*  Purpose:      erase specified block                                                         */
+/*  Input:        block_u16 - block number has to be erase                                      */
+/*  Output:       -                                                                             */
+/*  Returned:     fsl_u08, status_code                                                          */
+/*                     = 0x00(FSL_OK), normal and means "block erased successfully"             */
+/*                     = 0x05(FSL_ERR_PARAMETER), parameter error                               */
+/*                     = 0x10(FSL_ERR_PROTECTION), tried to erase protected area                */
+/*                     = 0x1A(FSL_ERR_ERASE), erase error, retry up to max. 255 times           */
+/*                     = 0x1F(FSL_ERR_INTERRUPTION), erasing interrupted by user interrupt      */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_Erase( fsl_u16 block_u16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      performs internal verify on specified block                                    */
+/* Input:        block_u16 - block number has to be verified                                    */
+/* Output:       -                                                                              */
+/* Returned:     fsl_u08, status_code                                                           */
+/*                    = 0x00(FSL_OK), normal and means "block is verified"                      */
+/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
+/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
+/*                    = 0x1F(FSL_ERR_INTERRUPTION), verify interrupted by user interrupt        */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_IVerify( fsl_u16 block_u16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      writes N words from the data buffer into flash                                 */
+/* Input:        s_address_u32 - starting flash address the data has to be written              */
+/*                               See Condition  2) please.                                      */
+/*               my_wordcount_u08  - number of words (4 bytes) has to be written                */
+/* Output:       -                                                                              */
+/* Condition:   1) (s_address_u32 MOD 4 == 0)                                                   */
+/*              2) most significant byte (MSB) of  s_address_u32 has to be 0x00.                */
+/*                 Means: 0x00abcdef 24 bit flash address allowed                               */
+/*              3) (word_count_u08 <= sizeof(data buffer))  NOT CHECKED BY LIBRARY  !!!!!       */
+/* Changed:     -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                   = 0x00(FSL_OK), normal                                                     */
+/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
+/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
+/*                   = 0x1C(FSL_ERR_WRITE), write error                                         */
+/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_Write( fsl_u32 s_address_u32, fsl_u08 word_count_u08 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      writes N words from the data buffer into flash                                 */
+/*               Before "writing" a N-word blankcheck is performed.                             */
+/*               After "writing" a N-Word internal verify is performed.                         */
+/* Input:        s_address_u32 - starting destination address has to be written                 */
+/*               my_wordcount_u08  - number of words (4 bytes) has to be written                */
+/* Output:       -                                                                              */
+/* Condition:   1) (s_address_u32 MOD 4 == 0)                                                   */
+/*              2) (word_count_u08 <= sizeof(data buffer))  NOT CHECKED BY FIRMWARE !!!!!       */
+/* Changed:     -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                   = 0x00(FSL_OK), normal                                                     */
+/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
+/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
+/*                   = 0x1C(FSL_ERR_WRITE), write error                                         */
+/*                   = 0x1D(FSL_ERR_EEP_IVERIFY), verify error                                  */
+/*                   = 0x1E(FSL_ERR_EEP_BLANKCHECK), blankcheck error                           */
+/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_EEPROMWrite( fsl_u32 s_address_u32,
+                                fsl_u08 word_count_u08 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      reads the security information                                                 */
+/* Input:        destination_pu16 - destination address of the security info                    */
+/*               The format of the security info is: "unsigned short int"                       */
+/*                                                                                              */
+/*               Format of the security info:                                                   */
+/*               bit_0 = 0 -> chip erase command disabled, otherwise enabled                    */
+/*               bit_1 = 0 -> block erase command disabled, otherwise enabled                   */
+/*               bit_2 = 0 -> write command disabled, otherwise enabled                         */
+/*               bit_4 = 0 -> boot-area re-programming disabled, otherwise enabled              */
+/*               bit_8...bit_15 = 03H -> last block of the boot-area                            */
+/*               other bits = 1                                                                 */
+/* Output:       -                                                                              */
+/* Changed:      content of the data_buffer                                                     */
+/* Returned:     fsl_u08, status code                                                           */
+/*                  = 0x00(FSL_OK), normal                                                      */
+/*                  = 0x05(FSL_ERR_PARAMETER), parameter error                                  */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_GetSecurityFlags( fsl_u16 * destination_pu16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      read the boot flag i                                                           */
+/* Input:        destination_pu08 - destination address of the bootflag info                    */
+/*               The format of the boot-flag info is: "unsigned char"                           */
+/*               The value of the boot info is 0x00 for cluster 0 and 0x01 for cluster 1.       */
+/* Output:       -                                                                              */
+/* Changed:      content of the data_buffer                                                     */
+/* Returned:     fsl_u08, status code                                                           */
+/*                  = 0x00(FSL_OK), normal                                                      */
+/*                  = 0x05(FSL_ERR_PARAMETER), parameter error                                  */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_GetActiveBootCluster( fsl_u08 * destination_pu08 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:     puts the last address of the specified block into *destination_pu32             */
+/* Input:       *destination_pu32 - destination where the last-block-address                    */
+/*                                  should be stored                                            */
+/*              block_u16         - block number of the last address is needed                  */
+/* Changed:     -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                   = 0x00(FSL_OK), normal                                                     */
+/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_GetBlockEndAddr( fsl_u32 * destination_pu32,
+                                    fsl_u16 block_u16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:     puts the information about the protected flash area into the function parameter */
+/* Input:       *start_block_pu16 - destination where the FSW start block should be stored      */
+/*              *end_block_pu16   - destination where the FSW end block should be stored        */
+/* Changed:     -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                   = 0x00(FSL_OK), normal                                                     */
+/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_GetFlashShieldWindow( fsl_u16 * start_block_pu16,
+                                         fsl_u16 * end_block_pu16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:     defines a new Flash-Shield-Window area inside the flash memory                  */
+/* Input:       start_block_u16 - starting block of the Flash-Shield-Window (FSW)               */
+/*              end_block_u16   - ending block of the flash-Shield-Window (FSW)                 */
+/* Changed:     -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                    = 0x00(FSL_OK), normal                                                    */
+/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
+/*                    = 0x10(FSL_ERR_PROTECTION), protection error                              */
+/*                    = 0x1A(FSL_ERR_ERASE), erase error                                        */
+/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
+/*                    = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt         */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_SetFlashShieldWindow( fsl_u16 start_block_u16,
+                                         fsl_u16 end_block_u16 );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:     Swapping of bootcluster 0 and 1                                                 */
+/*                                                                                              */
+/*              CAUTION !!!!                                                                    */
+/*              After this function the boot cluster are immediately swapped                    */
+/* Input:       -                                                                               */
+/* Output:      -                                                                               */
+/* Returned:    fsl_u08, status code                                                            */
+/*                   = 0x00(FSL_OK), normal                                                     */
+/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
+/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
+/*                   = 0x1A(FSL_ERR_ERASE), erase error                                         */
+/*                   = 0x1B(FSL_ERR_IVERIFY), internal verify error                             */
+/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_SwapBootCluster( void );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL command function                                                           */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:      sets specified security flag by dedicated command-function.                    */
+/*                                                                                              */
+/*               There are following security levels:                                           */
+/*               a) chip-erase protection   (cannot be reset by programmer !!!)                 */
+/*               b) block-erase protection  (can be reset by chip-erase on programmer)          */
+/*               c) write protection        (can be reset by chip-erase on programmer)          */
+/*               d) boot-cluster protection (cannot be reset by programmer !!!)                 */
+/*                                                                                              */
+/*               CAUTION !!!!                                                                   */
+/*               Each security flag can be written by the application only once                 */
+/*                                                                                              */
+/* Input:        -                                                                              */
+/* Output:       -                                                                              */
+/* Returned:     fsl_u08, status code                                                           */
+/*                    = 0x00(FSL_OK), normal                                                    */
+/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
+/*                    = 0x10(FSL_ERR_PROTECTION), protection error                              */
+/*                    = 0x1A(FSL_ERR_ERASE), erase error                                        */
+/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
+/*                    = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt         */
+/*----------------------------------------------------------------------------------------------*/
+extern fsl_u08 FSL_SetChipEraseProtectFlag( void );
+extern fsl_u08 FSL_SetBlockEraseProtectFlag( void );
+extern fsl_u08 FSL_SetWriteProtectFlag( void );
+extern fsl_u08 FSL_SetBootClusterProtectFlag( void );
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* Block type:   FSL function                                                                   */
+/*----------------------------------------------------------------------------------------------*/
+/* Purpose:     defines the firmware operation method after interrupt service (ISR) execution.  */
+/* Input:       mode_u08 = 0x00,  after RETI the firmware is continuing the interrupted command.*/
+/*                       = other, after RETI the firmware is interrupted with status 0x1F.      */
+/* Changed:     -                                                                               */
+/* Returned:    -                                                                               */
+/*----------------------------------------------------------------------------------------------*/
+extern void FSL_SetInterruptMode( fsl_u08 mode_u08 );
+
+#endif
diff --git a/tags/2.03_SDK-3.1/fsl_user.h b/tags/2.03_SDK-3.1/fsl_user.h
new file mode 100644
index 0000000..1018689
--- /dev/null
+++ b/tags/2.03_SDK-3.1/fsl_user.h
@@ -0,0 +1,113 @@
+/*==============================================================================================*/
+/* Project      = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash    */
+/* Module       = fsl_user.h                                                                    */
+/* Version      = V1.01                                                                         */
+/* Date         = 28.03.2008 11:45:55                                                           */
+/*==============================================================================================*/
+/*                                  COPYRIGHT                                                   */
+/*==============================================================================================*/
+/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH,                                         */
+/*               a company of the NEC Electronics Corporation                                   */
+/*==============================================================================================*/
+/* Purpose:                                                                                     */
+/*              user configurable constant/macros of the selfprogramming library                */
+/*                                                                                              */
+/*==============================================================================================*/
+/*                                                                                              */
+/* Warranty Disclaimer                                                                          */
+/*                                                                                              */
+/* Because the Product(s) is licensed free of charge, there is no warranty of any kind          */
+/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied,        */
+/* including but not limited to those for non-infringement of intellectual property,            */
+/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */
+/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/
+/*                                                                                              */
+/* Each User is solely responsible for determining the appropriateness of using the Product(s)  */
+/* and assumes all risks associated with its exercise of rights under this Agreement,           */
+/* including, but not limited to the risks and costs of program errors, compliance with         */
+/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or     */
+/* interruption of operations.                                                                  */
+/*                                                                                              */
+/* Limitation of Liability                                                                      */
+/*                                                                                              */
+/* In no event shall NEC be liable to the User for any incidental, consequential, indirect,     */
+/* or punitive damage (including but not limited to lost profits) regardless of whether         */
+/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */
+/* failure of essential purpose or otherwise and even if advised of the possibility of          */
+/* such damages. NEC shall not be liable for any services or products provided by third party   */
+/* vendors, developers or consultants identified or referred to the User by NEC in connection   */
+/* with the Product(s) and/or the Application.                                                  */
+/*                                                                                              */
+/*==============================================================================================*/
+/* Environment: PM plus (V6.30)                                                                 */
+/*              RA78K0(V1.20)                                                                   */
+/*              CC78K0(V2.00)                                                                   */
+/*==============================================================================================*/
+
+
+#ifndef __FSL_USER_H_INCLUDED
+#define __FSL_USER_H_INCLUDED
+
+
+/*==============================================================================================*/
+/* constant definitions                                                                         */
+/*==============================================================================================*/
+
+
+/* specify the CPU frequency in [Hz], only 2MHz....20MHz allowed  */
+#define   FSL_SYSTEM_FREQUENCY      8000000
+
+/* define whether low-voltage mode is used or not                 */
+/* #define   FSL_LOW_VOLTAGE_MODE                                 */
+
+/* size of the common data buffer expressed in [bytes]                                          */
+/* the data buffer is used for data-exchange between the firmware and the selflib.              */
+//#define   FSL_DATA_BUFFER_SIZE    256
+#define   FSL_DATA_BUFFER_SIZE    0
+
+
+/* customizable interrupt controller configuration during selfprogramming period                */
+/* Bit     --7-------6-------5-------4-------3-------2-------1-------0----------------------    */
+/* MK0L:     PMK5    PMK4    PMK3    PMK2    PMK1    PMK0    LVIMK   WDTIMK                     */
+/* MK0H:     SREMK0  SRMK0*  STMK0*  DMAMK1  DMAMK0  SREMK3  SRMK3   STMK3                      */
+/* MK1L:     TMMK03  TMMK02  TMMK01  TMMK00  IICMK0  SREMK1  SRMK1   STMK1*                     */
+/* MK1H:     TMMK04  SREMK2  SRMK2   STMK2*  KRMK    RTCIMK  RTCMK   ADMK                       */
+/* MK2L:     PMK10   PMK9    PMK8    PMK7    PMK6    TMMK07  TMMK06  TMMK05                     */
+/* MK2H:     1       1       1       1       1       1       1       PMK11                      */
+/*------------------------------------------------------------------------------------------    */
+/*                                                                                              */
+/* Examples:                                                                                    */
+/* =========                                                                                    */
+/*#define   FSL_MK0L_MASK   0xF7   -> allow INTP1 interrupt during selfprogramming              */
+/*#define   FSL_MK0H_MASK   0xEF   -> allow DMA1 interrupt during selfprogramming               */
+/*#define   FSL_MK1L_MASK   0xBF   -> allow TM02 interrupt during selfprogramming               */
+/*#define   FSL_MK1H_MASK   0xFF   -> all interrupts disabled during selfprogramming            */
+/*#define   FSL_MK2L_MASK   0xF7   -> allow INTP6 interrupt during selfprogramming              */
+/*#define   FSL_MK2H_MASK   0xFF   -> all interrupts disabled during selfprogramming            */
+/*------------------------------------------------------------------------------------------    */
+#define   FSL_MK0L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+#define   FSL_MK0H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+#define   FSL_MK1L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+#define   FSL_MK1H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+#define   FSL_MK2L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+#define   FSL_MK2H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
+
+
+/* FLMD0 control bit                        */
+#ifndef _WIN32
+#define  FSL_FLMD0_HIGH   {BECTL.7 = 1;}
+#define  FSL_FLMD0_LOW    {BECTL.7 = 0;}
+#else
+#define  FSL_FLMD0_HIGH   {BECTL_7 = 1;}
+#define  FSL_FLMD0_LOW    {BECTL_7 = 0;}
+#endif
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* switch interrupt backu functionality ON/OFF using #define/#undef                             */
+/*----------------------------------------------------------------------------------------------*/
+/* #define  FSL_INT_BACKUP */
+#undef  FSL_INT_BACKUP
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/hal.c b/tags/2.03_SDK-3.1/hal.c
new file mode 100644
index 0000000..e321719
--- /dev/null
+++ b/tags/2.03_SDK-3.1/hal.c
@@ -0,0 +1,177 @@
+#ifndef _WIN32
+#pragma SFR
+#endif
+
+#include "incs_loader.h"
+
+
+#define WIFI_txLatch PIF21					// �d�g���M�p���X �{�� led.h �Œ�`
+
+
+// HAL�ł��Ԃ���� ////////////////////////////////////////
+// ����Ȏ�����Ȃ琳�_���ɂ�r...���≽�ł��Ȃ�
+bit PM_EXTDC_n;
+bit BT_IN_CHG_n;
+bit SW_POW_n;
+bit SW_HOME_n;
+bit SW_WIFI_n;
+bit SHELL_OPEN;
+
+/*
+#define REG_BIT_HAL0_PM_EXTDC_n     ( 1 << 7 )
+#define REG_BIT_HAL0_BT_IN_CHG_n    ( 1 << 6 )
+//#define REG_BIT_HAL0_PM_IRQ_n     ( 1 << 5 )  // �g��Ȃ�
+#define REG_BIT_HAL0_WL_TX          ( 1 << 4 )
+#define REG_BIT_HAL0_SHELL_OPEN     ( 1 << 3 )
+#define REG_BIT_HAL0_SW_WIFI_n      ( 1 << 2 )
+#define REG_BIT_HAL0_SW_HOME_n      ( 1 << 1 )
+#define REG_BIT_HAL0_SW_POW_n       ( 1 << 0 )
+
+#define REG_BIT_HAL1_DIPSW_1        ( 1 << 3 )
+#define REG_BIT_HAL1_DIPSW_0        ( 1 << 2 )
+#define REG_BIT_HAL1_HW_DET_1       ( 1 << 1 )
+#define REG_BIT_HAL1_HW_DET_0       ( 1 << 0 )
+*/
+
+
+// �ڂ��ւ�
+// �`���^�����O�����Ȃ炱���ł������(�������ԃJ�E���g�͕�)
+void hal_update()
+{
+#ifdef _ENABLE_HAL_
+    u8 temp_conf = vreg_ctr[ VREG_C_HAL_OVW_CONT0 ];
+    u8 temp_dat  = vreg_ctr[ VREG_C_HAL_OVW_DAT0 ];
+#else
+    u8 temp_conf = 0x00;
+    u8 temp_dat  = 0;	// ���ł��ǂ�
+#endif
+
+    // �A�_�v�^�L��
+    if( temp_conf & REG_BIT_HAL0_PM_EXTDC_n )
+    {
+        // �O�����͂Ȃ񂾂��傫���Ȃ肪��
+        if(( temp_dat & REG_BIT_HAL0_PM_EXTDC_n ) == 0 )
+        {
+            PM_EXTDC_n = 0;
+        }
+        else
+        {
+            PM_EXTDC_n = 1;
+        }
+    }
+    else
+    {
+        PM_EXTDC_n = PM_EXTDC_n_RAW;
+    }
+
+    // �[�d���H
+    if( temp_conf & REG_BIT_HAL0_BT_IN_CHG_n )
+    {
+        if(( temp_dat & REG_BIT_HAL0_BT_IN_CHG_n ) == 0 )
+        {
+            BT_IN_CHG_n = 0;
+        }
+        else
+        {
+            BT_IN_CHG_n = 1;
+        }
+    }
+    else
+    {
+        BT_IN_CHG_n = BT_IN_CHG_n_RAW;
+    }
+
+    // �d���t
+    if( temp_conf & REG_BIT_HAL0_SW_POW_n )
+    {
+        if(( temp_dat & REG_BIT_HAL0_SW_POW_n ) == 0 )
+        {
+            SW_POW_n = 0 ;
+        }
+        else
+        {
+            SW_POW_n = 1;
+        }
+    }
+    else
+    {
+        SW_POW_n = SW_POW_n_RAW;
+    }
+
+    // ���Ɩt
+    if( temp_conf & REG_BIT_HAL0_SW_HOME_n )
+    {
+        if(( temp_dat & REG_BIT_HAL0_SW_HOME_n ) == 0 )
+        {
+            SW_HOME_n = 0;
+        }
+        else
+        {
+            SW_HOME_n = 1;
+        }
+    }
+    else
+    {
+        if( system_status.model == MODEL_TS_BOARD )// �ڑ���̃|�[�g���Ⴄ����
+        {
+            SW_HOME_n = SW_HOME_n_TSBOARD_RAW;
+        }
+        else
+        {
+            SW_HOME_n = SW_HOME_n_JIKKI_RAW;  
+        }
+    }
+
+    // �����J��
+    if( temp_conf & REG_BIT_HAL0_SW_WIFI_n )
+    {
+        if(( temp_dat & REG_BIT_HAL0_SW_WIFI_n ) == 0 )
+        {
+            SW_WIFI_n = 0;
+        }
+        else
+        {
+            SW_WIFI_n = 1;
+        }
+    }
+    else
+    {
+        SW_WIFI_n = SW_WIFI_n_RAW;
+    }
+
+    // ����
+    if( temp_conf & REG_BIT_HAL0_SHELL_OPEN )
+    {
+        if(( temp_dat & REG_BIT_HAL0_SHELL_OPEN ) == 0 )
+        {
+            SHELL_OPEN = 0;
+        }
+        else
+        {
+            SHELL_OPEN = 1;
+        }
+    }
+    else
+    {
+        SHELL_OPEN = SHELL_OPEN_RAW;
+    }
+
+    // �����d�g����
+    if( temp_conf & REG_BIT_HAL0_WL_TX )
+    {
+        WIFI_txLatch = 1;
+    }
+
+}
+
+
+
+void hal_reset()
+{
+    vreg_ctr[ VREG_C_HAL_OVW_CONT0 ] = 0;
+    vreg_ctr[ VREG_C_HAL_OVW_CONT1 ] = 0;
+    vreg_ctr[ VREG_C_HAL_OVW_TEMPERATURE ] = 0xFF;
+    vreg_ctr[ VREG_C_HAL_OVW_BT_FUEL ] = 0xFF;
+    vreg_ctr[ VREG_C_HAL_OVW_BT_VOLTAGE ] = 0xFF;
+}
+
diff --git a/tags/2.03_SDK-3.1/hal.h b/tags/2.03_SDK-3.1/hal.h
new file mode 100644
index 0000000..245be75
--- /dev/null
+++ b/tags/2.03_SDK-3.1/hal.h
@@ -0,0 +1,16 @@
+#ifndef _hal_h_
+#define _hal_h_
+
+
+extern bit PM_EXTDC_n;
+extern bit BT_IN_CHG_n;
+extern bit SW_POW_n;
+extern bit SW_HOME_n;
+extern bit SW_WIFI_n;
+extern bit SHELL_OPEN;
+
+// ========================================================
+void hal_update();
+void hal_reset();
+
+#endif
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diff --git a/tags/2.03_SDK-3.1/i2c_ctr.c b/tags/2.03_SDK-3.1/i2c_ctr.c
new file mode 100644
index 0000000..f37a4f9
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_ctr.c
@@ -0,0 +1,297 @@
+/* ========================================================
+  ��SoC �V�K�`�����l�� I2C�ʐM
+    ���c���J�Z.nintendo
+	'09 Apr
+ ======================================================== */
+
+#include "config.h"
+
+// TS�̓}�U�{�Ńe���R�AWM�͉�H�}���e���R�Ō��Lj�v�c
+
+#ifndef _WIN32
+#pragma interrupt INTIICA1	int_iic_ctr RB1
+#endif
+
+
+#include "incs.h"
+
+#ifdef _MCU_BSR_
+// #ifdef _MODEL_TS0_ || _MODEL_WM0_
+
+// ���[�L���O���f����I2C���t
+// TEG�͉�H�}�Ńe���R
+#define ACKD       ACKD1
+#define ACKE       ACKE1
+#define COI        COI1
+#define IICAEN     IICA1EN
+#define IICRSV     IICRSV1
+#define IICA       IICA1
+#define IICAIF     IICAIF1
+#define IICAMK     IICAMK1
+#define IICAPR0    IICAPR11
+#define IICAPR1    IICAPR01
+#define IICCTL0    IICCTL10
+#define IICE       IICE1
+#define IICF       IICF1
+#define IICS       IICS1
+#define IICWH      IICWH1
+#define IICWL      IICWL1
+#define LREL       LREL1
+#define SPD        SPD1
+#define SPIE       SPIE1
+#define STCEN      STCEN1
+#define STD        STD1
+#define SVA        SVA1
+#define WREL       WREL1
+#define WTIM       WTIM1
+#define TRC        TRC1
+#define SMC        SMC1
+#define DFC        DFC1
+
+#endif
+
+
+
+// ==============================================
+enum en_IIC_STATE
+{
+    IIC_IDLE = 0,
+    IIC_RCV_REG_ADRS,
+    IIC_TX_OR_RX,
+    IIC_TX,
+    IIC_RX
+};
+
+
+
+// ==============================================
+extern bit irq_readed;                 // �����ꂩ��IRQ���W�X�^���ǂ܂ꂽ
+
+u8 iic_burst_state;
+static enum en_IIC_STATE state = IIC_IDLE;
+
+#define bit_iics_spd	(i2c_stat & (1<<0))
+#define bit_iics_std	(i2c_stat & (1<<1))
+#define bit_iics_ackd	(i2c_stat & (1<<2))
+#define bit_iics_trc	(i2c_stat & (1<<3))
+#define bit_iics_coi	(i2c_stat & (1<<4))
+
+// ==============================================
+__interrupt void int_iic_ctr(  )
+{
+    static u8 reg_adrs;
+    static u8 tx_buf;
+    u8 rx_buf;
+    static u8 adrs_access_from;			// �o�[�X�g�A�N�Z�X�̎��Ɏg��
+
+	u8 i2c_stat = IICS1;				// volatile�̂���
+
+    // �ǂݏo���I��
+    if( !bit_iics_ackd                 // ���荞�ݗv����NAK�i�f�[�^���M�̍Ō�j
+		|| bit_iics_spd )              // �X�g�b�v�R���f�B�V����(!ACKD �ɗ����Ƃ��͊��荞�ݗ��Ȃ� (SPIE = 0))
+    {
+		/* 
+			I2C�̔������x���Ă��̃t���O����������O��STD�����Ă��܂����Ƃ�����
+			���ǁA���Ȃ����삷��‚���
+		*/
+
+        // ���W�X�^���[�h�ŁA���荞�݃s�����l�Q�[�g
+        // �܂��ǂ܂�ĂȂ����荞�݂�����΁A�ēx�A�T�[�g
+        if( irq_readed )
+        {
+            IRQ0_neg;
+            irq_readed = false;
+            if( !(  (( vreg_ctr[VREG_C_IRQ0] & vreg_ctr[VREG_C_IRQ_MASK0 ] ) == 0 )
+                    && (( vreg_ctr[VREG_C_IRQ1] & vreg_ctr[VREG_C_IRQ_MASK1 ] ) == 0 )
+                    && (( vreg_ctr[VREG_C_IRQ2] & vreg_ctr[VREG_C_IRQ_MASK2 ] ) == 0 )
+                    && (( vreg_ctr[VREG_C_IRQ3] & vreg_ctr[VREG_C_IRQ_MASK3 ] ) == 0 ) ))
+            {
+                while( !IRQ0 ){;}  // ���ԉ҂��s�v����
+                IRQ0_ast;
+            }
+        }
+
+        // I2C�I�����ɉ������镨 //
+        hosu_read_end(  );		// �����v�ǂݏo���I��
+        rtc_unlock(  );
+
+        state = IIC_IDLE;
+        SPIE = 0;
+        LREL = 1;
+        EI();
+        return;
+    }
+
+    if( bit_iics_std )                   // ���荞�ݗv���F�X�^�[�g�R���f�B�V����
+    {
+        if( !( state == IIC_IDLE || state == IIC_TX_OR_RX ))
+        {
+            // sp/nack ��葹�˂�
+//            dbg_nop();          // ���Ȃ��͂�...
+/*
+            // �p�P�b�g�̐擪��st�ƌ��Ȃ��B
+            // ���ʂɑ��s
+            state = IIC_IDLE;
+/*/
+			// ���g���C���Ă��炤
+			state = IIC_IDLE;
+			SPIE = 0;
+			LREL = 1;
+			EI();
+//*/
+		}
+		// �ʏ�
+	}
+
+	EI();
+
+    switch ( state )
+    {
+    case ( IIC_IDLE ):
+        // ���njĂяo���ɉ����B
+        // �������Ȃ�
+        iic_burst_state = 0;
+        SPIE = 1;
+        WREL = 1;               // �E�F�C�g����
+        state = IIC_RCV_REG_ADRS;
+		return;
+
+    case ( IIC_RCV_REG_ADRS ):  // �Q�o�C�g�ځi���W�X�^�A�h���X�j��M��ɗ���
+        // ���W�X�^�A�h���X��M
+        reg_adrs = IICA;
+
+        WREL = 1;
+        adrs_access_from = reg_adrs;
+        tx_buf = vreg_ctr_read( reg_adrs );    // �f�[�^�̏��������Ă���
+        state = IIC_TX_OR_RX;
+		return;
+
+    case ( IIC_TX_OR_RX ):      // ���̎��ɗ��銄�荞�݁BST�Ȃ瑗�M�����A�f�[�^�������珑�����܂�
+  //    if( TRC )               // ���M�����t���O �ŋ�ʂ���̂́A���荞�ݒx�����ɕs����N���肦��
+        if( bit_iics_std )
+        {                       // �X�^�[�g�R���f�B�V�������o�t���O
+            // ���[�h�����
+            if( bit_iics_coi )
+            {                   // �A�h���X��v�t���O
+                state = IIC_TX;
+                // no break, no return //
+            }
+            else
+            {
+                // ���X�^�[�g�ňႤ�f�o�C�X���Ă΂ꂽ�I
+                SPIE = 0;
+                LREL = 1;       // �E�F�C�g����?
+                state = IIC_IDLE;       // �I������
+                return;
+            }
+        }
+        else
+        {
+            state = IIC_RX;     // �f�[�^1�o�C�g��M�̊��荞�݂�����
+            // no break, no return //
+        }
+        /* FALLTHROUGH */
+
+    default:                    // �o�[�X�g R/W �ł�����������Ă΂�邱�ƂɂȂ�
+        if( state == IIC_TX )
+        {                       // ���M
+            IICA = tx_buf;
+            vreg_ctr_after_read( reg_adrs, tx_buf );    // �ǂ񂾂�N���A�Ȃǂ̏���
+        }
+        else
+        {                       // ��M
+            rx_buf = IICA;
+
+#ifdef _I2C_ERR_ABORT_
+			if( reg_adrs >= 0x80 || reg_adrs <= 1 )
+            {
+                LREL = 1; // �Ȃ񂩃f�[�^�������̂ŒʐM�I�� nak���Ԃ�̂��Ȃ��c
+                return;
+            }
+#endif
+			vreg_ctr_write( reg_adrs, rx_buf );
+            WREL = 1;
+		}
+
+		// ���W�X�^�A�h���X�̃C���N�������g
+        /// �A�N�Z�X�|�C���^��i�߂Ȃ�����ȃ��W�X�^
+        switch( adrs_access_from )
+        {
+        case( VREG_C_ACC_HOSU_HIST ):
+        case( VREG_C_LED_NOTIFY_DATA ):
+        case( VREG_C_LED_POW ):
+        case( VREG_CX_INFO ):
+        case( VREG_CX_FREE_DATA ):
+            break;
+        case( VREG_CX_FREE_ADRS ):
+            if( reg_adrs == VREG_CX_FREE_ADRS )
+            {
+                reg_adrs = VREG_CX_FREE_DATA;
+            }
+            break;
+        default:
+	        reg_adrs ++;
+        }
+
+        if( state == IIC_TX )
+        {                       // ����ɂ‚��ɑ���f�[�^�̏��������V�e�I�N�BSP�����Ďg���Ȃ���������Ȃ�
+            tx_buf = vreg_ctr_read( reg_adrs );
+        }
+        break;
+    }
+}
+
+
+
+// ========================================================
+void IIC_ctr_Init( void )
+{
+
+    IICAEN = 1;
+
+    IICE = 0;                   /* IICA disable */
+
+    IICAMK = 1;                 /* INTIICA disable */
+    IICAIF = 0;                 /* clear INTIICA interrupt flag */
+
+//    IICAPR0 = 1;                /* set INTIICA high priority */
+//    IICAPR1 = 0;                /* set INTIICA high priority */  �X�^�b�N�s��
+
+    P20 &= ~0x3;
+
+    SVA = IIC_C_SLAVEADDRESS;
+    IICF = 0x01;
+
+    STCEN = 1;                  // ���X�^�[�g�̋���
+    IICRSV = 1;                 // �ʐM�\��������Ȃ�:�X���[�u�ɓO����
+
+    SPIE = 0;                   // �X�g�b�v�R���f�B�V�����ł̊��荞�݂��֎~
+    WTIM = 1;                   // ������ACK��Ԃ�����clk��L�ɌŒ肷��
+    ACKE = 1;
+
+    IICWH = 5;
+    IICWL = 10;                 // L���Ԃ̒���
+
+    SMC = 1;                    // �������[�h
+    DFC = 1;                    // �f�W�^���t�B���^on (@fast mode)
+
+    IICAMK = 0;                 // ���荞�݂�����
+
+    IICE = 1;
+
+    PM20 &= ~0x3;                /* set clock pin for IICA */
+
+	state = IIC_IDLE;
+}
+
+
+
+// ========================================================
+void IIC_ctr_Stop( void )
+{
+    IICE = 0;                   /* IICA disable */
+    IICAEN = 0;
+}
+
+
+
diff --git a/tags/2.03_SDK-3.1/i2c_ctr.h b/tags/2.03_SDK-3.1/i2c_ctr.h
new file mode 100644
index 0000000..16234ff
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_ctr.h
@@ -0,0 +1,210 @@
+#ifndef _MDSERIAL_A_
+#define _MDSERIAL_A_
+
+
+/* IIC operation enable	(IICE0)	*/
+#define	IIC0_OPERATION				0x80
+#define	IIC0_OPERATION_DISABLE		0x00    /* stop operation */
+#define	IIC0_OPERATION_ENABLE		0x80    /* enable operation     */
+
+/* Exit	from communications	(LREL0)	*/
+#define	IIC0_COMMUNICATION			0x40
+#define	IIC0_COMMUNICATION_NORMAL	0x00    /* normal operation     */
+#define	IIC0_COMMUNICATION_EXIT		0x40    /* exit from current communication */
+
+/* Wait	cancellation (WREL0) */
+#define	IIC0_WAITCANCEL				0x20
+#define	IIC0_WAIT_NOTCANCEL			0x00    /* do not cancel wait */
+#define	IIC0_WAIT_CANCEL			0x20    /* cancel wait */
+
+/* Generation of interrupt when	stop condition (SPIE0) */
+#define	IIC0_STOPINT				0x10
+#define	IIC0_STOPINT_DISABLE		0x00    /* disable */
+#define	IIC0_STOPINT_ENABLE			0x10    /* enable */
+
+/* Wait	and	interrupt generation (WTIM0) */
+#define	IIC0_WAITINT				0x08
+#define	IIC0_WAITINT_CLK8FALLING	0x00    /* generate     at the eighth clocks falling edge       */
+#define	IIC0_WAITINT_CLK9FALLING	0x08    /* generated at the     ninth clocks falling edge       */
+
+/* Acknowledgement control (ACKE0) */
+#define	IIC0_ACK					0x04
+#define	IIC0_ACK_DISABLE			0x00    /* enable acknowledgement */
+#define	IIC0_ACK_ENABLE				0x04    /* disable acknowledgement */
+
+/* Start condition trigger (STT0) */
+#define	IIC0_STARTCONDITION			0x02
+#define	IIC0_START_NOTGENERATE		0x00    /* do not generate start condition */
+#define	IIC0_START_GENERATE			0x02    /* generate     start condition */
+
+/* Stop	condition trigger (SPT0) */
+#define	IIC0_STOPCONDITION			0x01
+#define	IIC0_STOP_NOTGENERATE		0x00    /* do not generate stop condition */
+#define	IIC0_STOP_GENERATE			0x01    /* generate     stop condition */
+
+/*
+	IIC	Status Register	0 (IICS0)
+*/
+/* Master device status	(MSTS0)	*/
+#define	IIC0_MASTERSTATUS			0x80
+#define	IIC0_STATUS_NOTMASTER		0x00    /* slave device status or communication standby status */
+#define	IIC0_STATUS_MASTER			0x80    /* master device communication status */
+
+/* Detection of	arbitration	loss (ALD0)	*/
+#define	IIC0_ARBITRATION			0x40
+#define	IIC0_ARBITRATION_NO			0x00    /* arbitration win or no arbitration */
+#define	IIC0_ARBITRATION_LOSS		0x40    /* arbitration loss     */
+
+/* Detection of	extension code reception (EXC0)	*/
+#define	IIC0_EXTENSIONCODE			0x20
+#define	IIC0_EXTCODE_NOT			0x00    /* extension code not received */
+#define	IIC0_EXTCODE_RECEIVED		0x20    /* extension code received */
+
+/* Detection of	matching addresses (COI0) */
+#define	IIC0_ADDRESSMATCH			0x10
+#define	IIC0_ADDRESS_NOTMATCH		0x00    /* addresses do not     match */
+#define	IIC0_ADDRESS_MATCH			0x10    /* addresses match */
+
+/* Detection of	transmit/receive status	(TRC0) */
+#define	IIC0_STATUS					0x08
+#define	IIC0_STATUS_RECEIVE			0x00    /* receive status */
+#define	IIC0_STATUS_TRANSMIT		0x08    /* transmit     status */
+
+/* Detection of	acknowledge	signal (ACKD0) */
+#define	IIC0_ACKDETECTION			0x04
+#define	IIC0_ACK_NOTDETECTED		0x00    /* ACK signal was not detected */
+#define	IIC0_ACK_DETECTED			0x04    /* ACK signal was detected */
+
+/* Detection of	start condition	(STD0) */
+#define	IIC0_STARTDETECTION			0x02
+#define	IIC0_START_NOTDETECTED		0x00    /* start condition not detected */
+#define	IIC0_START_DETECTED			0x02    /* start condition detected     */
+
+/* Detection of	stop condition (SPD0) */
+#define	IIC0_STOPDETECTION			0x01
+#define	IIC0_STOP_NOTDETECTED		0x00    /* stop condition not detected */
+#define	IIC0_STOP_DETECTED			0x01    /* stop condition detected */
+
+/*
+	IIC	Flag Register 0	(IICF0)
+*/
+/* STT0	clear flag (STCF) */
+#define	IIC0_STARTFLAG				0x80
+#define	IIC0_STARTFLAG_GENERATE		0x00    /* generate     start condition */
+#define	IIC0_STARTFLAG_UNSUCCESSFUL	0x80    /* start condition generation unsuccessful */
+
+/* IIC bus status flag (IICBSY)	*/
+#define	IIC0_BUSSTATUS				0x40
+#define	IIC0_BUS_RELEASE			0x00    /* bus release status */
+#define	IIC0_BUS_COMMUNICATION		0x40    /* bus communication status     */
+
+/* Initial start enable	trigger	(STCEN)	*/
+#define	IIC0_STARTWITHSTOP			0x02
+#define	IIC0_START_WITHSTOP			0x00    /* generation of a start condition without detecting a stop     condition */
+#define	IIC0_START_WITHOUTSTOP		0x02    /* generation of a start condition upon detection of a stop     condition */
+
+/* Communication reservation function disable bit (IICRSV) */
+#define	IIC0_RESERVATION			0x01
+#define	IIC0_RESERVATION_ENABLE		0x00    /* enable communication reservation     */
+#define	IIC0_RESERVATION_DISABLE	0x01    /* disable communication reservation */
+
+/*
+	IIC	clock selection	register 0 (IICCL0)
+*/
+#define IICCL0_INITIALVALUE   		0x00
+/* Detection of	SCL0 pin level (CLD0) */
+#define	IIC0_SCLLEVEL				0x20
+#define	IIC0_SCL_LOW				0x00    /* clock line at low level */
+#define	IIC0_SCL_HIGH				0x20    /* clock line at high level     */
+
+/* Detection of	SDA0 pin level (DAD0) */
+#define	IIC0_SDALEVEL				0x10
+#define	IIC0_SDA_LOW				0x00    /* data line at low     level */
+#define	IIC0_SDA_HIGH				0x10    /* data line at high level */
+
+/* Operation mode switching	(SMC0) */
+#define	IIC0_OPERATIONMODE			0x08
+#define	IIC0_MODE_STANDARD			0x00    /* operates     in standard     mode */
+#define	IIC0_MODE_HIGHSPEED			0x08    /* operates     in high-speed mode */
+
+/* Digital filter operation	control	(DFC0) */
+#define	IIC0_DIGITALFILTER			0x04
+#define	IIC0_FILTER_OFF				0x00    /* digital filter off */
+#define	IIC0_FILTER_ON				0x04    /* digital filter on */
+
+/* Operation mode switching	(CL01, CL00) */
+#define	IIC0_CLOCKSELECTION			0x03
+
+/*	Combine	of (SMC0, CL01,	CL00)*/
+#define	IIC0_CLOCK0					0x00
+#define	IIC0_CLOCK1					0x01
+#define	IIC0_CLOCK2					0x02
+#define	IIC0_CLOCK3					0x03
+#define	IIC0_CLOCK4					0x08
+#define	IIC0_CLOCK5					0x09
+#define	IIC0_CLOCK6					0x0a
+#define	IIC0_CLOCK7					0x0b
+
+/*
+	IIC	function expansion register	0 (IICX0)
+*/
+/* IIC clock expension (CLX0) */
+#define	IIC0_CLOCKEXPENSION			0x01
+#define	IIC0_EXPENSION0				0x00
+#define	IIC0_EXPENSION1				0x01
+
+/*  Operation clock (CLX0, SMC0, CL01, CL00)
+            |   IIC0_EXPENSION0 |   IIC0_EXPENSION1 |                                
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK0 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/88     |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK1 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/172    |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK2 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/344    |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK3 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
+            |       fw/66       |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK4 |       fprs/2      |       fprs/2      |   selection clock(fw)
+            |       fprs/48     |       fprs/24     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------            
+IIC0_CLOCK5 |       fprs/2      |       fprs/2      |   selection clock(fw)
+            |       fprs/48     |       fprs/24     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK6 |       fprs/4      |       fprs/4      |   selection clock(fw)
+            |       fprs/96     |       fprs/48     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK7 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
+            |       fw/18       |                   |   transfer clock
+            |     high speed    |                   |   mode
+------------|-------------------|-------------------|----------------------
+*/
+
+#define ADDRESS_COMPLETE   			0x80
+#define IIC_MASTER_FLAG_CLEAR 		0x00
+
+/******************************************************************************
+ *  Macro define
+ ******************************************************************************/
+
+
+
+/******************************************************************************
+ *  Function define
+ ******************************************************************************/
+
+void IIC_ctr_Init( void );
+void IIC_ctr_Stop( void );
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/i2c_mcu.c b/tags/2.03_SDK-3.1/i2c_mcu.c
new file mode 100644
index 0000000..cae7314
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_mcu.c
@@ -0,0 +1,657 @@
+/* ========================================================
+  �Ȉ�I2C�i�����y���t�F�����g�p�j�ʐM
+    de JHL ���c���J�Z
+    '09 Feb -
+ ======================================================== */
+#ifndef _WIN32
+#pragma sfr
+#pragma di
+#pragma ei
+#pragma nop
+#pragma inline                  // memcpy()���C�����C���W�J����(�̕����������I)
+#endif
+
+#include "incs_loader.h"
+#include "i2c_mcu.h"
+
+
+// ========================================================
+// ���W�X�^�̃r�b�g��
+// �v���t�B�b�N�Xb�����A�ꕔ�̃r�b�g�������W�X�^���ɂ��Ԃ邽��...
+// SMR0n
+#define bCKS0    ( 1 << 15 )
+#define bCCS0    ( 1 << 14 )
+#define bSTS0    ( 1 << 8 )
+#define bSIS0    ( 1 << 6 )
+#define bMD0n2   ( 1 << 2 )
+#define bMD0n1   ( 1 << 1 )
+#define bMD0n0   ( 1 << 0 )
+#define bSMR0n_FIXEDBIT  ( 1 << 5 )
+
+// SSR0n
+#define bit_TSF0   6
+#define PEF0       ( 1 << 1 )
+
+// SIR0n
+#define PECT0      ( 1 << 1 )
+
+// SCR0n
+#define TXE0       ( 1 << 15 )
+#define RXE0       ( 1 << 14 )
+#define SLC02      4
+#define DLS02      0
+#define TSF0       ( 1 << 6 )
+
+// SOn
+#define TAUS_MASK  0x0B0B;
+
+// DMCn
+#define DRS        ( 1 << 6 )
+
+
+
+// ========================================================
+static void iic_mcu_send_st(  );
+static void iic_mcu_send_re_st(  );
+static void iic_mcu_send_sp(  );
+static i2c_err iic_mcu_send_a_byte( u8 );
+static i2c_err iic_mcu_call_slave( u8 slave );
+extern void DI_wt_chk();
+
+
+
+
+// ========================================================
+bit     iic_mcu_wo_dma;
+volatile bit iic_mcu_busy;
+static volatile bit iic_mcu_initialized;
+
+
+static u8	iic_send_work[4];
+static u8	*p_iic_send_wo_dma_dat;
+static u8	iic_send_wo_dma_len;
+
+// �f�[�^�G���[�iROHM�������x�Z���T�j�����g���C�̂���
+/// �Ƃ肠�����ADMA�g�p�}���`�o�C�g���C�g �̎��ɂ����@�\���Ȃ�
+static u8 last_slave, last_reg_adrs, last_size;
+
+i2c_err		iic_mcu_result;     // �ꕶ�����[�h�̎��̓f�[�^��Ԃ��B
+
+#ifdef i2c_timeout_test
+extern bit i2c_mcu_time_out_error;
+#endif
+
+// ========================================================
+void nop8()
+{
+	// �����ɗ��� call ��3clk, return �� 6clk
+}
+
+
+static i2c_err iic_mcu_wait_free()
+{
+    u16 tot = 0;
+
+    iic_mcu_start(  );
+    while( 1 )
+    {
+        DI_wt_chk();
+        if( !iic_mcu_busy )
+        {
+            iic_mcu_busy = true;
+		    EI();
+            break;
+        }
+        EI();
+        if( ++tot == 0 )
+        {
+#ifdef i2c_timeout_test
+            i2c_mcu_time_out_error = true;
+#endif
+			return( I2C_ERR_TIMEOUT );
+        }
+    }
+    return( I2C_ERR_OK );
+}
+
+
+/* ========================================================
+  �X���[�u����� �w1�����x ���[�h
+  �Ԓl���f�[�^���̂��̂ł��B
+ ======================================================== */
+u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs )
+{
+    u8      dat;
+
+	iic_mcu_result = iic_mcu_read( SLA, adrs, 1, &dat );
+
+	return ( dat );
+}
+
+
+
+/* ========================================================
+  �X���[�u����̃��[�h
+  0 ����I��
+  1 �X���[�u���������Ȃ�
+  2 �o�X���N���ɐ�L����Ă��ă^�C���A�E�g
+  3 �Ӗ��s���G���[
+  �y���z
+  �X���[�u���E�F�C�g�R���f�B�V�������o�����Ƃ͋֎~�ł��B
+  ���̏ꍇ�ł��G���[���o�Ȃǂł��܂���
+ ======================================================== */
+i2c_err iic_mcu_read( u8 slave, u8 adrs, u8 len, u8 * dest )
+{
+
+#if 1
+    if( iic_mcu_wait_free() != I2C_ERR_OK )
+    {
+		// (�^�C���A�E�g)
+        return( I2C_ERR_TIMEOUT );
+    }
+#else
+      // �g�p���Ȃ�A��
+#endif
+
+    // �X�^�[�g�R���f�B�V�����ƃX���[�u�̌Ăяo���A���W�X�^�A�h���X�̑��M
+    if( iic_mcu_call_slave( slave ) != 0 )
+    {
+        iic_mcu_busy = false;
+        return ( I2C_ERR_NOSLAVE );
+    }
+
+    // ���W�X�^�A�h���X�̑��M
+    iic_mcu_send_a_byte( adrs );        // �I���܂ŋA���Ă��Ȃ�
+
+	// ��΂�NAK���A���Ă��Ȃ��O��
+
+    // �f�[�^��M //
+    iic_mcu_send_re_st(  );     // ���X�^�[�g�R���f�B�V����
+    iic_mcu_send_a_byte( slave | 0x01 );        // ���M�����܂Ŗ߂��Ă��܂���B
+
+    // �f�[�^��M
+    ST0 = 0x0004;               // ��M���[�h�ɐݒ��ς���̂Ń��W�b�N��~
+    SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02;     // ��M�ݒ�
+    SS0 = 0x0004;               // �ʐM�ҋ@
+
+    do
+    {
+        if( len == 1 )
+        {
+            SOE0 = 0x0000;      // �Ō��NAK
+        }
+        IICIF10 = 0;
+        SIO10 = 0xFF;           // �_�~�[�f�[�^�������Ǝ�M�J�n
+        while( IICIF10 == 0 )
+        {;}                       // ��M�����҂�
+
+        *dest = SIO10;
+        dest++;
+        len--;
+    }
+    while( len != 0 );
+
+    iic_mcu_send_sp(  );
+
+    IICIF10 = 0;
+    iic_mcu_busy = false;
+    return ( I2C_ERR_OK );
+}
+
+
+
+
+/* ========================================================
+  �X���[�u�� �w�P�o�C�g�x ���C�g
+  �O�̓]�����I���̂�҂��āA���C�g���܂��B
+  �Ԓl�@iic_mcu_write�@�ɓ���
+ ======================================================== */
+i2c_err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat )
+{
+    // �P�����̎���DMA�Ƃ��N�����Ȃ��ł������ƏI��点��
+    if( iic_mcu_wait_free() != I2C_ERR_OK )
+    {
+        return( I2C_ERR_TIMEOUT );
+    }
+
+    // �X�^�[�g�R���f�B�V�����ƃX���[�u�̌Ăяo��...
+    IICMK10 = 1;
+    if( iic_mcu_call_slave( SLA ) != I2C_ERR_OK )
+    {
+        iic_mcu_busy = false;
+        return( I2C_ERR_NOSLAVE );
+    }
+    iic_mcu_send_a_byte( adrs );
+    iic_mcu_send_a_byte( dat );
+    iic_mcu_send_sp(  );
+    iic_mcu_busy = false;
+    return ( I2C_ERR_OK );
+}
+
+
+
+/* ========================================================
+  �X���[�u�փ��C�g
+ ���W�X�^ adrs ��擪�ɁA
+ *str����
+ len���������܂��B
+
+   I2C_ERR_OK		����I��
+   I2C_ERR_NAK		�X���[�u���������Ȃ�
+   I2C_ERR_TIMEOUT	�d�C�I�̏�ŁH�^�C���A�E�g
+   // I2C_ERR_		�O�Ɏw�����ꂽ�ʐM���܂��I����ĂȂ�
+  �y���z
+  �X���[�u���E�F�C�g�R���f�B�V�������o�����Ƃ͋֎~�ł��B
+  ���̏ꍇ�ł��G���[���o�Ȃǂł��܂���
+  DMA1���g�p���܂��B
+ ******************************************************************************/
+i2c_err iic_mcu_write( u8 slave, u8 adrs, u8 len, void * src )
+{
+    if( iic_mcu_wait_free() != I2C_ERR_OK )
+    {
+        return( I2C_ERR_TIMEOUT );
+    }
+#if 0 // renge���^�̃}���`�^�X�N�ɂȂ����łɂ�
+  // �g�p���Ȃ�A��
+#endif
+
+  // �X�^�[�g�R���f�B�V�����ƃX���[�u�̌Ăяo��...
+    IICMK10 = 1;
+    IICIF10 = 0;
+    if( iic_mcu_call_slave( slave ) != I2C_ERR_OK )
+    {
+        iic_mcu_busy = false;
+        return ( I2C_ERR_NOSLAVE );
+    }
+
+    IICIF10 = 0;
+    if( !iic_mcu_wo_dma )
+    {
+        // DMA���g�p����i�ʏ�j//
+
+        // ���W�X�^�A�h���X�𑗂�A�f�[�^�̏���
+        memcpy( iic_send_work, src, 4 );        //�o�b�t�@�Ƃ���4�o�C�g�����p�ӂ��Ė������߁B
+
+        // ���g���C���̂���
+        last_slave = slave;
+        last_reg_adrs = adrs;
+        last_size = len;
+
+        // DMA�Z�b�g
+        while( DST1 )
+        {;}
+
+        DEN1 = 1;
+        DSA1 = (u8)( &SIO10 );
+        DRA1 = (u16)( &iic_send_work[0] );
+        DBC1 = len;
+        DMC1 = DRS | 8;         // RAM -> SFR, 8bit, IRQ, IIC10
+
+        DMAIF1 = 0;
+        DMAMK1 = 0;
+        DST1 = 1;               // DEN1 = 1����2clk�ȏ�J��
+
+        SIO10 = adrs;           // �������ςȂ��I ���荞�݂���������DMA�X�^�[�g
+        // �c��͊��荞�݃��[�`������
+    }
+    else
+    {
+        // DMA���g�p���Ȃ� //
+
+        // ���W�X�^�A�h���X�̑��M
+        IICMK10 = 0;
+        SIO10 = adrs;
+
+        iic_send_wo_dma_len = len;
+        p_iic_send_wo_dma_dat = (u8*)src;
+        // �c��͊��荞�݃��[�`������
+    }
+
+    return ( I2C_ERR_OK );
+}
+
+
+
+
+/* ========================================================
+  DMA�P�]���I�����荞��
+  IIC_mcu �̑��M�����R�[���o�b�N�֐��̂悤�Ȃ���
+  ���FDMA�]�����I����������ŁAI2C�̓]���͏I����Ă܂���
+�@  ���荞�ݒ��ȂǂŁADMA1�̏������x�������ꍇ�A
+  IIC10�̊��荞�݂̏������ł����ɁA���荞�݂𔭐��������Ȃ��Ȃ�
+  ���ꂪ����܂��B�܂��A�����@�����ɂ���܂���B
+  �@���̂��߁ADMA�d�l�̍��ق́A�Ō�̃o�C�g�͑��M������
+  �t���O�̃|�[�����O�Ŋm�F���܂��B
+ ======================================================== */
+__interrupt void int_dma1(  )
+{
+    static bit in_retry;
+
+    EI();
+
+    // �Ō�̃o�C�g�̑��M�����҂�
+    while( ( SSR02L & TSF0 ) != 0 )	
+    {
+        u16 i = 0;
+        if( ++i == 0 )  // �^�C���A�E�g�H
+        {
+            break;
+        }
+    }
+
+	// �X�g�b�v�R���f�B�V�������s
+//    iic_mcu_send_sp();    // ISR���ŊO�̊֐����ĂԂ͓̂s���������i�ėp���W�X�^�Ҕ�����������j�̂œW�J
+	{
+		ST0 = 0x0004;
+		SOE0 = 0;                   // ��M�̎��͂����ƑO�Ɂu���v�ݒ肵�Ă�B(NACK�o��)
+		SO0 = 0x0000 | TAUS_MASK;   // SCL
+        nop8();                 //. ���������|���Ȃ��B�O�̊֐��Ă�
+/*
+ 		 NOP(); NOP(); NOP(); NOP();
+		 NOP(); NOP(); NOP(); NOP();
+*/
+        SO0 = 0x0400 | TAUS_MASK;   // SCL
+        nop8();
+/*
+		 NOP(); NOP(); NOP(); NOP();
+		 NOP(); NOP(); NOP(); NOP();
+*/
+        SO0 = 0x0404 | TAUS_MASK;
+	}
+
+	IICMK10 = 1;
+
+    // �f�[�^�̓r���� NAK ��������A��x�������g���C����B
+    /// �蔲������
+    if( SIR02 != 0 )
+    {
+        SIR02 = SSR02;
+
+        if( !in_retry )
+        {
+			in_retry = true;
+
+            IICIF10 = 0;
+            iic_mcu_call_slave( last_slave ); // ������NAK�͍��m���P�A
+
+            while( DST1 ){;}
+            DRA1 = (u16)( &iic_send_work[0] );  // �����C���N�������g����Ă��܂��Ă���̂ōăZ�b�g
+	        DBC1 = last_size;					// �����f�N�������g����Ă��܂��Ă���̂ōăZ�b�g
+            // �ق��̐ݒ�͑O��̂܂�
+
+            DMAIF1 = 0;
+            DMAMK1 = 0;
+            DST1 = 1;
+            
+            SIO10 = last_reg_adrs;           // �������ςȂ��I ���荞�݂���������DMA�X�^�[�g
+            return;
+            // �����܂��@�܂��ˁI //
+        }
+        else
+        {
+            // �G���[��x�ځB�����m��Ȃ�
+            dbg_nop();
+            // ���̂܂܏I��������
+        }
+    }
+
+    // ����I��
+	in_retry = false;
+    DMAMK1 = 1;
+    DEN1 = 0;
+    iic_mcu_busy = false;
+}
+
+
+
+/* ========================================================
+  IIC MCU�̃o�C�g���o�������荞��
+  ��DMA�g�p���͎g�p����܂���B
+  �@���̊��荞�ݏ�������DMA�̊��荞�݂ɂ�����΂Ȃ��ꍇ�A
+  �@IIC���荞�݂̃Z�b�g���Ԃɍ��킸���邱�Ƃ�����܂��B
+ ======================================================== */
+__interrupt void int_iic10(  )
+{
+    EI();
+    if( iic_send_wo_dma_len != 0 )	// �܂����M�������Ă��Ȃ��H
+    {
+        SIO10 = *p_iic_send_wo_dma_dat;
+        p_iic_send_wo_dma_dat ++;
+        iic_send_wo_dma_len --;
+        return;
+		// �����܂� //
+    }
+
+    // �Ō�̃o�C�g���M�����A�X�g�b�v�R���f�B�V�������s
+    IICMK10 = 1;
+//    iic_mcu_send_sp();    // ISR���ŊO�̊֐����ĂԂ͓̂s���������i�ėp���W�X�^�Ҕ�����������j�̂œW�J
+	{
+		ST0 = 0x0004;
+		SOE0 = 0;                   // ��M�̎��͂����ƑO�Ɂu���v�ݒ肵�Ă�B(NACK�o��)
+		SO0 = 0x0000 | TAUS_MASK;   // clear SCL
+ 		 NOP(); NOP(); NOP(); NOP();	// NOP8�����Ă�ł͂���
+		 NOP(); NOP(); NOP(); NOP();
+        SO0 = 0x0400 | TAUS_MASK;   // set SCL
+		 NOP(); NOP(); NOP(); NOP();
+		 NOP(); NOP(); NOP(); NOP();
+        SO0 = 0x0404 | TAUS_MASK;	// set CSL adn SDA
+	}
+
+    iic_mcu_wo_dma = false;
+    iic_mcu_busy = false;
+}
+
+
+
+/* ========================================================
+  �X���[�u�̌Ăяo��
+�@�X���[�u�A�h���X���Ă�ŁAACK�̊m�F�B
+  ACK�@���@�@�@�@�@�@�@�@�@�@�@�@�@�@�@�@�@�ԁF0
+�@NACK ���@�X�g�b�v�R���f�B�V�������o���B�@�ԁF1
+ ======================================================== */
+static i2c_err iic_mcu_call_slave( u8 slave )
+{
+    iic_mcu_send_st(  );
+
+/*
+// dbg
+	if( SSR02 != 0 )
+	{
+		P1.5 = P1.0 = P1.3 = 1;
+	}
+*/
+
+    SIR02 = SSR02;              // NAK�G���[�̃t���O�N���A
+    if( iic_mcu_send_a_byte( slave ) != I2C_ERR_OK )
+    {
+        iic_mcu_send_sp(  );
+        return ( I2C_ERR_NOSLAVE );     // �w��̃X���[�u�����Ȃ�
+    }
+
+    return ( I2C_ERR_OK );
+}
+
+
+
+/* ========================================================
+  �ق�ƂɂP�o�C�g�����̂�
+  �����I���܂ŋA��܂���
+ ======================================================== */
+static i2c_err iic_mcu_send_a_byte( u8 dat )
+{
+    IICMK10 = 1;
+    IICIF10 = 0;
+    SIO10 = dat;
+    while( IICIF10 == 0 )
+    {
+//        NOP(  );
+    }                           // �ʐM��
+
+    if( SSR02 != 0 )            // ���炩�G���[����?
+    {
+        SIR02 = SSR02;          // �G���[�N���A
+        return( I2C_ERR_NAK );
+    }
+    return( I2C_ERR_OK );
+}
+
+
+
+/* ========================================================
+  �X�^�[�g�R���f�B�V�����𔭍s
+  �\�t�g�E�F�A����
+ ======================================================== */
+static void iic_mcu_send_st(  )
+{
+    SO0 &= ~0x0004;             // SDA
+    nop8();
+
+    SO0 &= ~0x0400;             // SCL
+    SOE0 = 0x0004;              // �n�[�h�����
+
+    SCR02 = TXE0 | 1 << SLC02 | 7 << DLS02;     // ���M���A�f�[�^�͂W�r�b�g�P��
+    SS0 = 0x0004;               // �ʐM�ҋ@
+}
+
+
+
+/* ========================================================
+  ���X�^�[�g���s
+ ======================================================== */
+static void iic_mcu_send_re_st(  )
+{
+    ST0 |= 0x0004;
+    SO0 |= 0x0400 | TAUS_MASK;  // ( SDA = H ), SCL -> H
+    nop8();
+
+    SOE0 &= ~0x0004;            // ( SCL = H ), SDA -> L
+    nop8();
+
+    iic_mcu_send_st(  );
+}
+
+
+
+/* ========================================================
+  �X�g�b�v�R���f�B�V�������s
+  ���̑O�ɁA�u�Ō�̃o�C�g�̑���M�v�̎��ɑO�������K�v�ł��B
+ ======================================================== */
+static void iic_mcu_send_sp(  )
+{
+    ST0 = 0x0004;
+    SOE0 = 0;                   // ��M�̎��͂����ƑO�Ɂu���v�ݒ肵�Ă�B(NACK�o��)
+    SO0 = 0x0000 | TAUS_MASK;   // SCL
+    nop8();
+
+    SO0 = 0x0400 | TAUS_MASK;   // SCL
+    nop8();
+
+    SO0 = 0x0404 | TAUS_MASK;
+}
+
+
+
+
+/* ========================================================
+  �y���t�F�������W���[���̏�����
+ ======================================================== */
+void iic_mcu_start(  )
+{
+    if( iic_mcu_initialized )
+    {
+        return;
+    }
+
+    iic_mcu_busy = true;
+//    DST1 = 0;
+
+    I2C_PU_on();
+//    DEN1 = 0;                   // DST1 = 0 ���� 2clk�������́ADSTn==0���|�[�����O���Ă���
+
+    wait_ms( 1 );               // �����オ��̂�50us�ʂ�����
+
+    SAU0EN = 1;
+    nop8();
+
+    SPS0 = 0x0000;              // �V���A�����j�b�g�̃N���b�N�O�B(8M/2)/1
+    SMR02 = bSMR0n_FIXEDBIT | bMD0n2;	// �Ȉ�I2C�ɐݒ�
+    SDR02 = 10 << 9;             // �{�[���[�g�ݒ� 8M/1/(x+1)/2
+
+    SO0 = 0x0404 | TAUS_MASK;   // �ŏ���HH
+    iic_mcu_wo_dma = false;
+
+
+    // �o�X�̃��Z�b�g
+    {
+        IICIF10 = 0;
+        IICMK10 = 1;
+
+        iic_mcu_send_st();
+
+        SIO10 = 0xFF;
+        while( IICIF10 == 0 ){;}                           // �ʐM��
+        iic_mcu_send_sp();
+
+        SIR02 = SSR02;
+    }
+
+    iic_mcu_busy = false;
+    iic_mcu_initialized = true;
+}
+
+
+
+/* ========================================================
+  ���W���[���̒�~
+  �ēx�g���Ƃ��͏��������K�v
+ ======================================================== */
+void iic_mcu_stop(  )
+{
+    while( iic_mcu_busy )
+    {;}                         // DMA���쒆�͂��������҂�
+    iic_mcu_send_re_st(  );     // SCL,SDA��LL�ɂ���
+    I2C_PU_off();
+    SAU0EN = 0;
+    iic_mcu_initialized = false;
+}
+
+
+
+
+/* ========================================================
+  �R�[�f�b�N�� �w�P�o�C�g�x ���C�g
+  iic_mcu_write_a_byte CODEC�s����[�N�A���E���h
+ ======================================================== */
+i2c_err iic_mcu_write_a_byte_codec( u8 adrs, u8 dat )
+{
+    static u8 count;
+
+    // �P�����̎���DMA�Ƃ��N�����Ȃ��ł������ƏI��点��
+    if( iic_mcu_wait_free() !=I2C_ERR_OK )
+    {
+        return( I2C_ERR_TIMEOUT );
+    }
+
+    // �X�^�[�g�R���f�B�V�����ƃX���[�u�̌Ăяo��...
+    IICMK10 = 1;
+    if( iic_mcu_call_slave( IIC_SLA_CODEC ) != I2C_ERR_OK )
+    {
+        iic_mcu_busy = false;
+        return ( I2C_ERR_NOSLAVE );
+    }
+    iic_mcu_send_a_byte( adrs );
+    iic_mcu_send_a_byte( dat );
+
+    // ���[�N�A���E���h��������
+    /// ���X�^�[�g�ɂ��ă_�~�[���C�g
+    iic_mcu_send_re_st(  );
+    iic_mcu_send_a_byte( IIC_SLA_CODEC );	// �_�~�[���C�g
+    iic_mcu_send_a_byte( 0x20 );			// �S�~�������Ă����Ȃ��A�h���X
+    iic_mcu_send_a_byte( count );			// ���ł��悢�̂����B����������Ȃ��Ȃ�����Œ�l��
+
+    count ++;
+
+    iic_mcu_send_sp(  );
+    iic_mcu_busy = false;
+    return ( I2C_ERR_OK );
+}
diff --git a/tags/2.03_SDK-3.1/i2c_mcu.h b/tags/2.03_SDK-3.1/i2c_mcu.h
new file mode 100644
index 0000000..16eeba8
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_mcu.h
@@ -0,0 +1,40 @@
+#ifndef __ic2_mcu__
+#define __ic2_mcu__
+
+
+// ========================================================
+typedef enum{
+	I2C_ERR_OK = 0,
+	I2C_ERR_NAK,
+	I2C_ERR_NOSLAVE,
+	I2C_ERR_TIMEOUT,
+	I2C_ERR_UNDEF = 0xFF
+}i2c_err;
+
+
+
+// ========================================================
+extern volatile bit iic_mcu_busy;
+extern bit iic_mcu_wo_dma;
+
+extern i2c_err iic_mcu_result;
+
+
+// ========================================================
+i2c_err iic_mcu_read( u8 SLA, u8 adrs, u8 len, u8 * dest );
+u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs );
+
+i2c_err iic_mcu_write( u8 SLA, u8 adrs, u8 len, void * src );
+i2c_err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat );
+
+i2c_err iic_mcu_write_a_byte_codec( u8 adrs, u8 dat );	// codec�o�O����@�\�t��
+
+
+// �����̒ʐM�������������������܂��B
+#define iic_mcu_set_wo_dma()           { while( iic_mcu_busy ){;} iic_mcu_wo_dma = true; }
+
+void iic_mcu_start(  );
+void iic_mcu_stop(  );
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/i2c_twl.c b/tags/2.03_SDK-3.1/i2c_twl.c
new file mode 100644
index 0000000..48c1447
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_twl.c
@@ -0,0 +1,231 @@
+#ifndef _WIN32
+
+#pragma sfr                     /* ����@�\���W�X�^�g�p */
+
+#endif
+
+
+/*============================================================================*/
+
+#include "config.h"
+
+#ifndef _WIN32
+
+#pragma interrupt INTIICA0	int_iic_twl RB2
+
+#endif
+
+#include "incs.h"
+#include "i2c_twl_defs.h"
+#include "i2c_twl.h"
+
+extern u8 vreg_twl[];
+
+#ifdef _MCU_BSR_
+//#ifdef _MODEL_TS0_ || _MODEL_WM0_
+
+// ���[�L���O���f����I2C���t
+#define ACKD       ACKD0
+#define ACKE       ACKE0
+#define COI        COI0
+#define IICAEN     IICA0EN
+#define IICRSV     IICRSV0
+#define IICA       IICA0
+#define IICAIF     IICAIF0
+#define IICAMK     IICAMK0
+#define IICAPR0    IICAPR00
+#define IICAPR1    IICAPR10
+#define IICCTL0    IICCTL00
+#define IICE       IICE0
+#define IICF       IICF0
+#define IICS       IICS0
+#define IICWH      IICWH0
+#define IICWL      IICWL0
+#define LREL       LREL0
+#define SPD        SPD0
+#define SPIE       SPIE0
+#define STCEN      STCEN0
+#define STD        STD0
+#define SVA        SVA0
+#define WREL       WREL0
+#define WTIM       WTIM0
+#define SMC        SMC0
+#define TRC        TRC0
+
+#endif // _MCU_BSR_
+
+#ifndef _MCU_BSR_
+
+// ke3�̎��̓_�~�[�֐�
+void IIC_twl_Stop( void )
+{
+}
+void IIC_twl_Init( void )
+{
+}
+#else // _MCU_BSR_
+
+
+
+enum IIC_TWL_STATE{
+    WAIT_ADRS = 0,
+    WAIT_DATA,
+    DATA_READED
+};
+
+
+
+
+/*============================================================================*/
+
+// ���I�@���̓}�N���Ȃ̂ŁAreturn�̓��C�����[�v�ɖ߂�܂��B
+#define wait_next {                                    \
+    tot = 0;                                           \
+  while( IICAIF != 1 ){                                \
+    tot ++;                                             \
+    if( tot == 0 ){                                    \
+      LREL = 1;                                        \
+      return;                                          \
+    }                                                  \
+  }                                                    \
+}
+
+
+__interrupt void int_iic_twl(  )
+{
+    u8      vreg_adrs;
+    u8      state;
+
+    // �@
+    WREL = 1;                   // �E�F�C�g�������Ď��̃o�C�g��҂�
+    WDT_Restart();
+    state = WAIT_ADRS;
+
+    while( 1 )
+    {
+        u8 my_iics;
+
+		{
+			u16 tot;
+	        wait_next;              // �P�o�C�g��M������҂�
+		}
+
+		my_iics = IICS;
+        IICAIF = 0;
+
+        if( my_iics & 0x02 )    // ( STD && !SPD )
+        {
+            // �X�^�[�g�R���f�B�V����������
+            if( ( my_iics & 0x08 ) == 0 ) // ( TRC ) ���M�����t���O 0:�}�C�R������M
+            {
+                // �@�f�}�C�R���������ł����ATWL�����g���C�����Ƃ��Ƃ�
+                // �����ɗ���̂̓X���[�u�Ăяo���̎� //
+                WREL = 1;
+                state = WAIT_ADRS;
+                /// ���W�X�^�A�h���X���������̂�҂�
+            }
+            else
+            {
+                // �BR R�ł̃X���[�u�Ăяo��(���X�^�[�g�R���f�B�V����) //
+                IICA = vreg_twl_read( vreg_adrs ); // �f�[�^���M
+                // �X�g�b�v�҂���ALREL = 1 �ɂ��Ȃ��ƁA���M�o�b�t�@���j�󂳂�邱�Ƃ�����
+                state = DATA_READED;
+            }
+        }
+        else if( ( my_iics & 0x03 ) == 0 ) // ( !STD && !SPD )
+        {
+			u8 rcvd;
+
+            // ���炩��M
+            rcvd = IICA;
+            WREL = 1;
+
+            if( state == WAIT_ADRS )
+            {
+                // �A
+                vreg_adrs = adrs_table_twl_ext2int( rcvd );
+                /// �f�[�^��������邩�A���X�^�[�g�œǂݏo�����̂�҂�
+                state = WAIT_DATA;
+            }
+            else if( state == DATA_READED )
+            {
+                // �f�[�^1�o�C�g���M�㔭������
+                LREL = 1;
+                return;
+            }
+            else
+            {
+                // �BW
+                // �f�[�^�������܂�
+                SVA = 0x5A;     // �_�~�[
+                LREL = 1;       // �X�^�[�g�R���f�B�V�����҂���(�A���������ݖ��Ή��̂���)
+                vreg_twl_write( vreg_adrs, rcvd );
+                SVA = IIC_T_SLAVEADDRESS;
+                return;         // ��M�����܂� //
+            }
+        }
+        else if( my_iics & 0x01 ) // SPD
+        {
+            // �I��
+            LREL = 1;
+            return;
+        }
+        else
+        {
+            // NOP();
+        }
+    }
+}
+
+
+
+/*****************************************************/
+void IIC_twl_Init( void )
+{
+
+    IICAEN = 1;
+
+    IICE = 0;                   /* IICA disable */
+
+    IICAMK = 1;                 /* INTIICA disable */
+    IICAIF = 0;                 /* clear INTIICA interrupt flag */
+
+    IICAPR0 = 0;                /* set INTIICA high priority */
+    IICAPR1 = 0;                /* set INTIICA high priority */
+    P20 &= ~0x3;
+
+    SVA = IIC_T_SLAVEADDRESS;
+    IICF = 0x01;
+
+    STCEN = 1;                  // ���X�^�[�g�̋���
+    IICRSV = 1;                 // �ʐM�\��������Ȃ�:�X���[�u�ɓO����
+
+    SPIE = 0;                   // �X�g�b�v�R���f�B�V�����ł̊��荞�݂��֎~
+    WTIM = 1;                   // ������ACK��Ԃ�����clk��L�ɌŒ肷��
+    ACKE = 1;                   //  �_��CPU�͖������Ď��̒ʐM���͂��߂邩������Ȃ���ő���clk���J�����Ȃ��Ƃ����Ȃ�
+
+    IICWH = 5;
+    IICWL = 10;                 // L���Ԃ̒����i�H�j
+
+    SMC = 1;
+
+    IICAMK = 0;                 // ���荞�݂�����
+
+    IICE = 1;
+
+    PM20 &= ~0x3;               /* set clock pin for IICA */
+
+    LREL = 1;
+}
+
+
+
+//****************************************************************************
+void IIC_twl_Stop( void )
+{
+    IICE = 0;                   /* IICA disable */
+    IICAEN = 0;
+}
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/i2c_twl.h b/tags/2.03_SDK-3.1/i2c_twl.h
new file mode 100644
index 0000000..0f608b0
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_twl.h
@@ -0,0 +1,7 @@
+#ifndef _iic_twl_
+#define _iic_twl_
+
+void IIC_twl_Init( void );
+void IIC_twl_Stop( void );
+
+#endif
diff --git a/tags/2.03_SDK-3.1/i2c_twl_defs.h b/tags/2.03_SDK-3.1/i2c_twl_defs.h
new file mode 100644
index 0000000..be5d566
--- /dev/null
+++ b/tags/2.03_SDK-3.1/i2c_twl_defs.h
@@ -0,0 +1,196 @@
+#ifndef _MDSERIAL_
+#define _MDSERIAL_
+
+
+/* IIC operation enable	(IICE0)	*/
+#define	IIC0_OPERATION				0x80
+#define	IIC0_OPERATION_DISABLE		0x00    /* stop operation */
+#define	IIC0_OPERATION_ENABLE		0x80    /* enable operation     */
+
+/* Exit	from communications	(LREL0)	*/
+#define	IIC0_COMMUNICATION			0x40
+#define	IIC0_COMMUNICATION_NORMAL	0x00    /* normal operation     */
+#define	IIC0_COMMUNICATION_EXIT		0x40    /* exit from current communication */
+
+/* Wait	cancellation (WREL0) */
+#define	IIC0_WAITCANCEL				0x20
+#define	IIC0_WAIT_NOTCANCEL			0x00    /* do not cancel wait */
+#define	IIC0_WAIT_CANCEL			0x20    /* cancel wait */
+
+/* Generation of interrupt when	stop condition (SPIE0) */
+#define	IIC0_STOPINT				0x10
+#define	IIC0_STOPINT_DISABLE		0x00    /* disable */
+#define	IIC0_STOPINT_ENABLE			0x10    /* enable */
+
+/* Wait	and	interrupt generation (WTIM0) */
+#define	IIC0_WAITINT				0x08
+#define	IIC0_WAITINT_CLK8FALLING	0x00    /* generate     at the eighth clocks falling edge       */
+#define	IIC0_WAITINT_CLK9FALLING	0x08    /* generated at the     ninth clocks falling edge       */
+
+/* Acknowledgement control (ACKE0) */
+#define	IIC0_ACK					0x04
+#define	IIC0_ACK_DISABLE			0x00    /* enable acknowledgement */
+#define	IIC0_ACK_ENABLE				0x04    /* disable acknowledgement */
+
+/* Start condition trigger (STT0) */
+#define	IIC0_STARTCONDITION			0x02
+#define	IIC0_START_NOTGENERATE		0x00    /* do not generate start condition */
+#define	IIC0_START_GENERATE			0x02    /* generate     start condition */
+
+/* Stop	condition trigger (SPT0) */
+#define	IIC0_STOPCONDITION			0x01
+#define	IIC0_STOP_NOTGENERATE		0x00    /* do not generate stop condition */
+#define	IIC0_STOP_GENERATE			0x01    /* generate     stop condition */
+
+/*
+	IIC	Status Register	0 (IICS0)
+*/
+/* Master device status	(MSTS0)	*/
+#define	IIC0_MASTERSTATUS			0x80
+#define	IIC0_STATUS_NOTMASTER		0x00    /* slave device status or communication standby status */
+#define	IIC0_STATUS_MASTER			0x80    /* master device communication status */
+
+/* Detection of	arbitration	loss (ALD0)	*/
+#define	IIC0_ARBITRATION			0x40
+#define	IIC0_ARBITRATION_NO			0x00    /* arbitration win or no arbitration */
+#define	IIC0_ARBITRATION_LOSS		0x40    /* arbitration loss     */
+
+/* Detection of	extension code reception (EXC0)	*/
+#define	IIC0_EXTENSIONCODE			0x20
+#define	IIC0_EXTCODE_NOT			0x00    /* extension code not received */
+#define	IIC0_EXTCODE_RECEIVED		0x20    /* extension code received */
+
+/* Detection of	matching addresses (COI0) */
+#define	IIC0_ADDRESSMATCH			0x10
+#define	IIC0_ADDRESS_NOTMATCH		0x00    /* addresses do not     match */
+#define	IIC0_ADDRESS_MATCH			0x10    /* addresses match */
+
+/* Detection of	transmit/receive status	(TRC0) */
+#define	IIC0_STATUS					0x08
+#define	IIC0_STATUS_RECEIVE			0x00    /* receive status */
+#define	IIC0_STATUS_TRANSMIT		0x08    /* transmit     status */
+
+/* Detection of	acknowledge	signal (ACKD0) */
+#define	IIC0_ACKDETECTION			0x04
+#define	IIC0_ACK_NOTDETECTED		0x00    /* ACK signal was not detected */
+#define	IIC0_ACK_DETECTED			0x04    /* ACK signal was detected */
+
+/* Detection of	start condition	(STD0) */
+#define	IIC0_STARTDETECTION			0x02
+#define	IIC0_START_NOTDETECTED		0x00    /* start condition not detected */
+#define	IIC0_START_DETECTED			0x02    /* start condition detected     */
+
+/* Detection of	stop condition (SPD0) */
+#define	IIC0_STOPDETECTION			0x01
+#define	IIC0_STOP_NOTDETECTED		0x00    /* stop condition not detected */
+#define	IIC0_STOP_DETECTED			0x01    /* stop condition detected */
+
+/*
+	IIC	Flag Register 0	(IICF0)
+*/
+/* STT0	clear flag (STCF) */
+#define	IIC0_STARTFLAG				0x80
+#define	IIC0_STARTFLAG_GENERATE		0x00    /* generate     start condition */
+#define	IIC0_STARTFLAG_UNSUCCESSFUL	0x80    /* start condition generation unsuccessful */
+
+/* IIC bus status flag (IICBSY)	*/
+#define	IIC0_BUSSTATUS				0x40
+#define	IIC0_BUS_RELEASE			0x00    /* bus release status */
+#define	IIC0_BUS_COMMUNICATION		0x40    /* bus communication status     */
+
+/* Initial start enable	trigger	(STCEN)	*/
+#define	IIC0_STARTWITHSTOP			0x02
+#define	IIC0_START_WITHSTOP			0x00    /* generation of a start condition without detecting a stop     condition */
+#define	IIC0_START_WITHOUTSTOP		0x02    /* generation of a start condition upon detection of a stop     condition */
+
+/* Communication reservation function disable bit (IICRSV) */
+#define	IIC0_RESERVATION			0x01
+#define	IIC0_RESERVATION_ENABLE		0x00    /* enable communication reservation     */
+#define	IIC0_RESERVATION_DISABLE	0x01    /* disable communication reservation */
+
+/*
+	IIC	clock selection	register 0 (IICCL0)
+*/
+#define IICCL0_INITIALVALUE   		0x00
+/* Detection of	SCL0 pin level (CLD0) */
+#define	IIC0_SCLLEVEL				0x20
+#define	IIC0_SCL_LOW				0x00    /* clock line at low level */
+#define	IIC0_SCL_HIGH				0x20    /* clock line at high level     */
+
+/* Detection of	SDA0 pin level (DAD0) */
+#define	IIC0_SDALEVEL				0x10
+#define	IIC0_SDA_LOW				0x00    /* data line at low     level */
+#define	IIC0_SDA_HIGH				0x10    /* data line at high level */
+
+/* Operation mode switching	(SMC0) */
+#define	IIC0_OPERATIONMODE			0x08
+#define	IIC0_MODE_STANDARD			0x00    /* operates     in standard     mode */
+#define	IIC0_MODE_HIGHSPEED			0x08    /* operates     in high-speed mode */
+
+/* Digital filter operation	control	(DFC0) */
+#define	IIC0_DIGITALFILTER			0x04
+#define	IIC0_FILTER_OFF				0x00    /* digital filter off */
+#define	IIC0_FILTER_ON				0x04    /* digital filter on */
+
+/* Operation mode switching	(CL01, CL00) */
+#define	IIC0_CLOCKSELECTION			0x03
+
+/*	Combine	of (SMC0, CL01,	CL00)*/
+#define	IIC0_CLOCK0					0x00
+#define	IIC0_CLOCK1					0x01
+#define	IIC0_CLOCK2					0x02
+#define	IIC0_CLOCK3					0x03
+#define	IIC0_CLOCK4					0x08
+#define	IIC0_CLOCK5					0x09
+#define	IIC0_CLOCK6					0x0a
+#define	IIC0_CLOCK7					0x0b
+
+/*
+	IIC	function expansion register	0 (IICX0)
+*/
+/* IIC clock expension (CLX0) */
+#define	IIC0_CLOCKEXPENSION			0x01
+#define	IIC0_EXPENSION0				0x00
+#define	IIC0_EXPENSION1				0x01
+
+/*  Operation clock (CLX0, SMC0, CL01, CL00)
+            |   IIC0_EXPENSION0 |   IIC0_EXPENSION1 |                                
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK0 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/88     |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK1 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/172    |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK2 |       fprs/2      |       prohibited  |   selection clock(fw)
+            |       fprs/344    |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK3 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
+            |       fw/66       |                   |   transfer clock
+            |       normal      |                   |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK4 |       fprs/2      |       fprs/2      |   selection clock(fw)
+            |       fprs/48     |       fprs/24     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------            
+IIC0_CLOCK5 |       fprs/2      |       fprs/2      |   selection clock(fw)
+            |       fprs/48     |       fprs/24     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK6 |       fprs/4      |       fprs/4      |   selection clock(fw)
+            |       fprs/96     |       fprs/48     |   transfer clock
+            |     high speed    |       high speed  |   mode
+------------|-------------------|-------------------|----------------------
+IIC0_CLOCK7 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
+            |       fw/18       |                   |   transfer clock
+            |     high speed    |                   |   mode
+------------|-------------------|-------------------|----------------------
+*/
+
+#define ADDRESS_COMPLETE   			0x80
+#define IIC_MASTER_FLAG_CLEAR 		0x00
+
+#endif
diff --git a/tags/2.03_SDK-3.1/incs.h b/tags/2.03_SDK-3.1/incs.h
new file mode 100644
index 0000000..cd33a79
--- /dev/null
+++ b/tags/2.03_SDK-3.1/incs.h
@@ -0,0 +1,58 @@
+#ifndef _WIN32
+#pragma SFR
+#pragma di
+#pragma ei
+#pragma nop
+#pragma stop
+#pragma halt
+#endif
+
+#ifndef _WIN32
+#pragma section @@CODE ROM_CODE
+//#pragma section @@CNST ROM_CNST
+#endif
+
+#ifdef _WIN32
+// VC�̐Ԑ����ǂ��ɂ�����
+#include "sim/simOnWin.h"
+# endif
+
+
+
+//=========================================================
+#ifndef _incs_h_
+#define _incs_h_
+
+// �� �����v��_pc_�ƂŐ؂�ւ��Ă܂�
+#define _mcu_
+
+#include "jhl_defs.h"
+#include "user_define.h"
+
+#include "hal.h"
+
+#include "bsr_system.h"
+#include "renge\renge.h"
+#include "loader.h"
+
+#include "vreg_ctr.h"
+#include "vreg_twl.h"
+
+#include "i2c_mcu.h"
+#include "i2c_twl.h"
+
+#include "rtc.h"
+
+#include "accero.h"
+
+#include "pm.h"
+
+#include "sw.h"
+
+#include "adc.h"
+
+#include "wdt.h"
+
+//=========================================================
+
+#endif
diff --git a/tags/2.03_SDK-3.1/incs_loader.h b/tags/2.03_SDK-3.1/incs_loader.h
new file mode 100644
index 0000000..4bb13b5
--- /dev/null
+++ b/tags/2.03_SDK-3.1/incs_loader.h
@@ -0,0 +1,47 @@
+#ifndef _WIN32
+#pragma SFR
+#pragma di
+#pragma ei
+#pragma nop
+#pragma stop
+#pragma halt
+
+
+#pragma section @@CODE       LDR_CODE
+#pragma section @@CODEL      LDR_CODL
+
+//#pragma section @@R_INIT     FSL_RINT  // ������ƃX�^�[�g�A�b�v���[�`���������l��
+//#pragma section @@CNST       FSL_CNST  // �Z�b�g���Ă���Ȃ�
+#pragma section @@CNSTL      LDR_CNSL
+
+#endif
+
+# ifdef _WIN32
+// VC�̐Ԑ����ǂ��ɂ�����
+#include "sim/simOnWin.h"
+# endif
+
+
+//=========================================================
+#include "jhl_defs.h"
+#include "user_define.h"
+
+#include "hal.h"
+
+#include "bsr_system.h"
+#include "renge\renge.h"
+
+#include "vreg_ctr.h"
+#include "vreg_twl.h"
+
+#include "loader.h"
+
+#include "i2c_mcu.h"
+
+#include "WDT.h"
+
+
+
+//=========================================================
+void firm_update(  );
+void firm_restore(  );
diff --git a/tags/2.03_SDK-3.1/ini_VECT.c b/tags/2.03_SDK-3.1/ini_VECT.c
new file mode 100644
index 0000000..10ea9ea
--- /dev/null
+++ b/tags/2.03_SDK-3.1/ini_VECT.c
@@ -0,0 +1,383 @@
+#ifndef _WIN32
+
+#pragma nop
+
+#endif
+
+#include "config.h"
+
+#ifndef _WIN32
+//#pragma interrupt INTWDTI     fn_intwdti  // ���g�p
+//#pragma interrupt INTLVI      fn_intlvi   // ���g�p
+
+//#pragma interrupt INTP0		intp0_slp       // SLP (CPU���A�v��) �|�[�����O
+//#pragma interrupt INTP1               fn_intp1 // (I2C)
+//#pragma interrupt INTP2               fn_intp2 // (I2C)
+//#pragma interrupt INTP3               fn_intp3 // ������
+#pragma interrupt INTP4		intp4_extdc     // EXTDC, �������d��off����N�����̂݁B�ʏ�̓|�[�����O
+#pragma interrupt INTP5		intp5_shell     // SHELL_CLOSE, �������d��off����N�����̂݁B�ʏ�̓|�[�����O
+#pragma interrupt INTP6		intp6_PM_irq    // CODEC�o�R�ŋ�PMIC�ւ̃R�}���h��������
+
+//#ifdef _MCU_BSR_                          // ���荞�݂��̂��͎̂g���܂���
+//#pragma interrupt INTP21	intp21_RFTx     // �d�g���M�p���X
+//#else
+//#pragma interrupt INTP7		intp21_RFTx
+//#endif
+
+
+/*
+
+ accero��
+#ifdef _MCU_BSR_
+#pragma interrupt INTP23	intp23_ACC_ready RB3       // �����x�Z���T�A�f�[�^��������
+#endif
+*/
+
+//#pragma interrupt INTCMP0     fn_intcmp0
+//#pragma interrupt INTCMP1     fn_intcmp1
+//#pragma interrupt INTDMA0     fn_intdma0
+#pragma interrupt INTDMA1	int_dma1
+
+//#pragma interrupt INTST0      fn_intst0
+/* #pragma interrupt INTCSI00	fn_intcsi00 */
+//#pragma interrupt INTSR0      fn_intsr0
+/* #pragma interrupt INTCSI01	fn_intcsi01 */
+//#pragma interrupt INTSRE0     fn_intsre0
+
+//#pragma interrupt INTST1      fn_intst1
+/* #pragma interrupt INTCSI10	fn_intcsi10 */
+#pragma interrupt INTIIC10	int_iic10
+//#pragma interrupt INTSR1      fn_intsr1
+//#pragma interrupt INTSRE1     fn_intsre1
+
+
+/*
+// TS�̓}�U�{�Ńe���R�AWM�͉�H�}���e���R�Ō��Lj�v�c
+#pragma interrupt INTIICA1	int_iic_ctr RB1
+
+#pragma interrupt INTIICA0	int_iic_twl RB2
+*/
+
+//#pragma interrupt INTTM00     fn_inttm00
+//#pragma interrupt INTTM01     fn_inttm01
+//#pragma interrupt INTTM02     fn_inttm02
+//#pragma interrupt INTTM03     fn_inttm03
+
+#pragma interrupt INTAD		int_adc
+#pragma interrupt INTRTC	int_rtc
+#pragma interrupt INTRTCI	int_rtc_int
+#pragma interrupt INTKR		int_kr
+//#pragma interrupt INTMD               fn_intmd
+
+//#pragma interrupt INTTM04     fn_inttm04
+//#pragma interrupt INTTM05     fn_inttm05
+//#pragma interrupt INTTM06     fn_inttm06
+//#pragma interrupt INTTM07     fn_inttm07
+
+
+//#define _irq_debug_
+/****************************************************/
+/*  ���g�p���̃_�~�[�֐���`                        */
+/****************************************************/
+__interrupt void fn_intwdti(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intlvi(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intp0(){
+#ifdef _irq_debug_
+while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intp1(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}                               //
+__interrupt void fn_intp2(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+__interrupt void fn_intp3(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+
+__interrupt void intp21_RFTx(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+
+//__interrupt   void    fn_intp4(){ while(1){} } // pm.c
+//__interrupt   void    fn_intp5(){ while(1){} } // pm.c
+//__interrupt   void    fn_intp6(){ while(1){} } // pm.c
+//__interrupt   void    fn_intp7(){ while(1){} } // led.c
+//__interrupt   void    fn_intp21(){ while(1){} } // led.c
+
+__interrupt void fn_intcmp0(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intcmp1(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intdma0(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+//__interrupt   void    fn_intdma1(){}  // i2c_mcu.c�ɂ���
+
+__interrupt void fn_intst0(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+/* __interrupt	void	fn_intcsi00(){} */
+__interrupt void fn_intsr0(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+/* __interrupt	void	fn_intcsi01(){} */
+__interrupt void fn_intsre0(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intst1(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+/* __interrupt	void	fn_intcsi10(){} */
+//__interrupt   void    fn_intiic10(){ while(1){} }
+__interrupt void fn_intsr1(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_intsre1(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+//__interrupt   void    fn_intiica(){} // i2c.c�ɂ���
+/* __interrupt	void	fn_inttm00(){} *//* sub.c�ɂĒ�` */
+__interrupt void fn_inttm01(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_inttm02(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+__interrupt void fn_inttm03(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+//__interrupt   void    fn_intad(){ while(1){} }  // adc.c
+__interrupt void fn_intrtc(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+//__interrupt   void    int_rtcint(){} // rtc.c�ɂ���
+//__interrupt   void    fn_intkr(){}  // main.c
+__interrupt void fn_intmd(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_inttm04(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_inttm05(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_inttm06(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+__interrupt void fn_inttm07(  )
+{
+#ifdef _irq_debug_
+    while( 1 )
+    {
+        NOP();
+    }
+#endif
+}
+
+
+
+/* ========================================================
+  �L�[���^�[�����荞��
+ ======================================================== */
+__interrupt void int_kr(  )
+{
+    // �N���邾��
+}
+
+
+
+/* ========================================================
+  ext dc
+ ======================================================== */
+__interrupt void intp4(  )
+{
+    // �N���邾��
+}
+
+
+
+/* ========================================================
+ shell close
+ ======================================================== */
+__interrupt void intp5(  )
+{
+    // �N���邾��
+}
+
+
+#else
+
+#include "sim/sim_interrupt_decrare.c"
+
+#endif
+
diff --git a/tags/2.03_SDK-3.1/jhl_defs.h b/tags/2.03_SDK-3.1/jhl_defs.h
new file mode 100644
index 0000000..b0b36c6
--- /dev/null
+++ b/tags/2.03_SDK-3.1/jhl_defs.h
@@ -0,0 +1,29 @@
+#ifndef __jhl_defs_h__
+#define __jhl_defs_h__
+
+typedef unsigned char u8;
+typedef   signed char s8;
+typedef unsigned short u16;
+typedef   signed short s16;
+
+typedef unsigned short ux16;
+typedef   signed short sx16;
+
+#define true 1
+#define false 0
+
+
+// typedef unsigned char err;
+
+#include "config.h"
+
+#define set_bit( cond, reg, pos ) \
+{                                 \
+  if( cond ){                     \
+    reg |= pos;                   \
+  }else{                          \
+    reg &= ~pos;                  \
+  }                               \
+}
+
+#endif
diff --git a/tags/2.03_SDK-3.1/led.c b/tags/2.03_SDK-3.1/led.c
new file mode 100644
index 0000000..c21af05
--- /dev/null
+++ b/tags/2.03_SDK-3.1/led.c
@@ -0,0 +1,354 @@
+/* ========================================================
+  LED.c
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma sfr
+
+#endif
+
+#include "incs.h"
+#include "led.h"
+
+
+
+// ========================================================
+// TPS0
+#define BIT_PRS012             ( 1 << 2 )
+#define BIT_PRS002             ( 1 << 6 )
+
+// TMR0
+#define BIT_CKS0             15
+#define BIT_CCS0             12
+#define BIT_MASTER0          11
+#define BIT_STS0              8
+#define BIT_CIS0              6
+#define BIT_MD123             1
+#define BIT_MD0               0
+
+
+
+// ========================================================
+bit ledInitialized;
+
+
+// ���m�点LED
+uni_info_LED info_LED;		// �p�^�[���f�[�^
+bit info_led_off;			// �d��off���ȂǁA���������t���O
+bit info_led_override;		// �d�r�c�ʋ͏������_�ŏ㏑���r�b�g
+
+// wifi led �X�e�[�g
+static u8 state_wifi_tx;
+static u8 flag_wifi_TX;
+
+
+// �[�d�����ۂ�
+extern bit BT_IN_CHG_delayed_n;
+
+
+// ========================================================
+#define led_fade_to( now, goal )       now = fade_to( now, goal )
+
+/* ========================================================
+   reg_led��goal�ɂȂ�܂ŃO���f�[�V��������
+   �Ƃ肠�����A�X�e�b�v�Œ�
+   ====================================================== */
+u8 fade_to( u8 now, u8 goal )
+{
+    if( now != goal )
+    {
+        if( now > goal )
+        {
+            now --;
+        }
+        else
+        {
+            now ++;
+        }
+    }
+    return( now );
+}
+
+
+
+
+// ========================================================
+#define led_fade_to2( led, status )                      \
+    led = fade_to2( status )
+
+
+u8 fade_to2( st_LED_dim_status* status )
+{
+    if( status->now != status->to )
+    {
+        if( abs(( status->to - status->now )) > abs(status->delta) )
+        {
+            status->now += status->delta;
+        }
+        else
+        {
+            status->now = status->to;
+        }
+    }
+    return( status->now / 128 );
+}
+
+
+
+
+// ========================================================
+
+
+// ========================================================
+void LED_init(  )
+{
+/**
+  PWM�̃Z�b�g�A�Ƃ肠�����S������
+
+  �}�X�^�`���l���F�O�@(P01:/reset2)�@�}�X�^�[�͋����`���l�������ł��Ȃ�
+  �X���[�u�@�@�@�@�P�@�r�k�s�n�B(�R�c �k�d�c�H)
+  �@�@�@�@�@�@�@�@�Q�@�J����
+  �@�@�@�@�@�@�@�@�R�@WiFi
+  �@�@�@�@�@�@�@�@�S�@(�s���͂q�s�b32kHz out �Ɏg�p)
+  �@�@�@�@�@�@�@�@�T�@�[�d
+  �@�@�@�@�@�@�@�@�U�@�d�� �k
+  �@�@�@�@�@�@�@�@�V�@�d�� �g
+ */
+    TAU0EN = 1;
+    TPS0 = BIT_PRS012 | BIT_PRS002;     // �}�X�^�[�N���b�N��CK01,8M/2 /2^4 = 250kHz
+
+    TMR00 =
+        1 << BIT_CKS0 | 0 << BIT_CCS0 | 1 << BIT_MASTER0 | 0 << BIT_STS0 | 0
+        << BIT_CIS0 | 0 << BIT_MD123 | 1 << BIT_MD0;
+    TMR01 = TMR02 = TMR03 = TMR04 = TMR05 = TMR06 = TMR07 =
+        1 << BIT_CKS0 | 0 << BIT_CCS0 | 0 << BIT_MASTER0 | 4 << BIT_STS0 | 0
+        << BIT_CIS0 | 4 << BIT_MD123 | 1 << BIT_MD0;
+    ISC = 0;
+    TOM0 = 0x00FE; // �o�̓��[�h�B4��PWM�o�͂��Ȃ���1�ɂ��Ȃ���TO5�ȍ~�ɃN���b�N���͂��Ȃ�
+
+    TOL0 = 0x0000; // �o�͂𔽓]�����邩�t���O
+
+    TO0 = 0x0000;                    // �^�C�}�[���쒆�ŁA�^�C�}�[�o�͂ɂ��ĂȂ��Ƃ��̃s���̃��b�`�B�^�C�}�[�o�͂��g��Ȃ��Ȃ�O
+    TOE0 = 0x00EE; // TOx���^�C�}�[���W���[��������H
+
+    TS0 = 0x00EF;  // ����J�n
+
+    TDR00 = LED_BRIGHT_MAX - 1; // ���� 10bit
+
+//    system_status.info_fullcolor = 1;		// ���m�点1���d�l�p�~
+
+	if( system_status.reboot )
+    {
+        vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO;
+        LED_duty_pow_blu = LED_BRIGHT_MAX;
+    }
+    info_led_off = false;
+	ledInitialized = true;
+}
+
+
+
+void LED_stop(  )
+{
+    TT0 = 0x00EF;  // ��Ē�~�i���Ȃ��Ƃ��߁j
+    TOE0 = 0x0000; // TOx���^�C�}�[���W���[��������H(GPIO�ɂȂ�)
+    TAU0EN = 0;
+    LED_pow_red = 0;
+    LED_CAM     = 0;
+
+	LED_duty_notify_red = 0;
+    LED_duty_notify_blu = 0;
+    LED_duty_notify_grn = 0;
+    LED_pow_red = 0;
+    LED_CAM     = 0;
+
+    WIFI_txLatch = 0;
+    flag_wifi_TX = 0;
+    state_wifi_tx = 0;
+
+	ledInitialized = false;
+}
+
+
+
+
+
+
+
+/* ========================================================
+  * ���荞�݂��̂��͎̂g���܂��� *
+  LED_Wifi           3
+ ======================================================== */
+void tsk_led_wifi(  )
+{
+    static u8 task_interval;
+
+    if( task_interval-- != 0 )
+    {
+        return;
+    }
+
+    // ���M�p���X�̃��b�`
+    if( WIFI_txLatch )         // ���荞�݃t���O���̂��̂��g���Ă��܂�
+    {
+        WIFI_txLatch = 0;
+        flag_wifi_TX = 1;
+    }
+
+    if( flag_wifi_TX != 0 )
+    {
+        vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_WIFI_TX;
+        // ���M�p�^�[��
+        switch ( state_wifi_tx )
+        {
+          case ( 1 ):
+          case ( 3 ):
+          case ( 5 ):
+            LED_duty_WiFi = 0;
+            break;
+          default:
+            LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT];
+        }
+        state_wifi_tx ++;
+        if( state_wifi_tx == 32 )  // ���_�Ō�A�_�����Ă�����Ԃ̒���
+        {
+            state_wifi_tx = 0;
+            flag_wifi_TX --;
+        }
+        task_interval = 25;
+        return;
+    }
+    else
+    {
+        task_interval = 30;
+        // ���M�t���O�҂�
+        vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_WIFI_TX;
+        if( vreg_ctr[VREG_C_LED_WIFI] == WIFI_LED_OFF )
+        {
+            LED_duty_WiFi = 0;
+            return;
+        }
+        else
+        {
+            if( LED_duty_WiFi == vreg_ctr[VREG_C_LED_BRIGHT] )
+            {
+                return;
+            }
+            else if( LED_duty_WiFi < vreg_ctr[VREG_C_LED_BRIGHT] )
+            {
+                LED_duty_WiFi ++;
+            }
+            else
+            {
+                LED_duty_WiFi --;
+            }
+        }
+        task_interval = 3;
+        return;
+    }
+}
+
+
+
+
+bit info_led_pattern_updated;
+/* ========================================================
+ ���m�点LED
+ ======================================================== */
+// �O���f�[�V�����v�Z�Ȃ�
+static void calc_info_led_fade_out( st_LED_dim_status* tgt_led )
+{
+    tgt_led -> to = 0;
+    tgt_led -> delta = ( 0 - tgt_led -> now ) / 64;
+}
+
+
+static void calc_info_led_next_frame( st_LED_dim_status* tgt_led, u8 color )
+{
+    tgt_led -> to = color * 128;
+    // �O���f�[�V�����̃f���^���v�Z
+    tgt_led -> delta = (( tgt_led -> to - tgt_led -> now ) ) / info_LED.info_LED.fade_time;
+}
+
+
+// �{��
+void tsk_led_notify(  )
+{
+    static u8 time_to_next_frame;
+    static u8 frame;
+    static u8 loops;
+    static st_LED_dim_status LED_dim_status_info_R, LED_dim_status_info_G, LED_dim_status_info_B;
+
+    if( info_led_override )
+    {
+        // �d�r�؂ꂪ�D�悷��
+        return;
+    }
+
+    if( system_status.pwr_state == ON_TRIG )
+    {
+        LED_duty_notify_blu = 0;
+        LED_duty_notify_red = 0;
+        LED_duty_notify_grn = 0;
+        LED_dim_status_info_R.now = 0;
+        LED_dim_status_info_G.now = 0;
+        LED_dim_status_info_B.now = 0;
+    }
+
+    if( info_led_off )  // ���d��off���ȂNj���off
+    {
+        // �t�F�[�h�A�E�g������
+        calc_info_led_fade_out( &LED_dim_status_info_R );
+        calc_info_led_fade_out( &LED_dim_status_info_G );
+        calc_info_led_fade_out( &LED_dim_status_info_B );
+    }
+    else
+    {
+        // �ʏ�^�]
+        if( info_led_pattern_updated )
+        {
+            info_led_pattern_updated = false;
+            vreg_ctr[ VREG_C_LED_NOTIFY_FLAG ] &= ~REG_BIT_IN_LOOP;
+            frame = 0;                      // �����Ə�����
+            time_to_next_frame = 0;
+        }
+        else
+        {
+            // ���̃t���[���ɐi�߂�H
+            if( time_to_next_frame == 0 )
+            {
+                time_to_next_frame = info_LED.info_LED.term;
+
+                if( frame >= NOTIFY_LED_TERM -1 )
+                {
+                    vreg_ctr[ VREG_C_LED_NOTIFY_FLAG ] |= REG_BIT_IN_LOOP;
+                    if( info_LED.info_LED.last_loop != 255 )  // 255:�������[�v
+                    {
+                        loops ++;
+                        if( loops > info_LED.info_LED.last_loop )
+                        {
+                            frame = 0;
+                        }
+                    }
+                }
+                else
+                {
+                    frame = (( frame + 1 ) & 0x1F ); // �������Ń}�X�N�������Ă����Ȃ��ƍŏI�t���[���`�擪�Ԃ̃O���f�������Ȃ�
+                    vreg_ctr[ VREG_C_LED_NOTIFY_FLAG ] &= ~REG_BIT_IN_LOOP;
+                    loops = 0;
+                }
+
+                // �O���f�[�V�����v�Z
+                calc_info_led_next_frame( &LED_dim_status_info_R, info_LED.info_LED.red[frame] );
+                calc_info_led_next_frame( &LED_dim_status_info_G, info_LED.info_LED.grn[frame] );
+                calc_info_led_next_frame( &LED_dim_status_info_B, info_LED.info_LED.blu[frame] );
+                
+            }
+            time_to_next_frame --;
+        }
+    }
+
+    led_fade_to2( LED_duty_notify_red, &LED_dim_status_info_R );
+    led_fade_to2( LED_duty_notify_grn, &LED_dim_status_info_G );
+    led_fade_to2( LED_duty_notify_blu, &LED_dim_status_info_B );
+}
diff --git a/tags/2.03_SDK-3.1/led.h b/tags/2.03_SDK-3.1/led.h
new file mode 100644
index 0000000..ce8541f
--- /dev/null
+++ b/tags/2.03_SDK-3.1/led.h
@@ -0,0 +1,142 @@
+#ifndef __led__
+#define __led__
+
+
+
+// ====================================
+
+//#define LED_CHARGE           P2.4  // PM�Œ�`
+
+// LED_DUTY
+#define LED_duty_pow_blu     TDR06
+#define LED_duty_WiFi        TDR03
+
+#define LED_duty_3d          TDR01
+#define LED_duty_notify_red  TDR07
+#define LED_duty_notify_grn  TDR05
+#define LED_duty_notify_blu  TDR02
+
+// ������duty�ς����܂���
+#ifndef _WIN32
+#define LED_pow_red          P4.2
+#define LED_CAM              P7.5
+#else
+#define LED_pow_red          mcuRegP[ _P4_2 ]
+#define LED_CAM              mcuRegP[ _P7_5 ]
+#endif
+
+#define NOTIFY_LED_TERM     32
+
+
+#define LED_BRIGHT_MAX      0x00FF
+
+// ====================================
+#define WIFI_txLatch PIF21					// �d�g���M�p���X
+
+
+
+// ====================================
+enum LED_ILUM_MODE
+{
+  LED_POW_ILM_AUTO = 0,
+  LED_POW_ILM_ON,
+  LED_POW_ILM_SLEEP,
+  LED_POW_ILM_OFF,
+  LED_POW_ILM_ONLY_RED,
+  LED_POW_ILM_ONLY_BLUE,
+  LED_POW_ILM_FORCE_BT_EMPTY
+};
+
+
+enum LED_MODE_3D
+{
+  LED_3D_ILM_OFF = 0,
+  LED_3D_ILM_ON
+};
+
+
+// VREG_C_WIFI_LED
+enum WIFI_LED_MODE
+{
+  WIFI_LED_OFF = 0,
+  WIFI_LED_ON
+};
+
+
+// VREG_C_WIFI_NOTIFY
+enum NOTIFY_LED_MODE
+{
+  NOTIFY_LED_OFF = 0,
+  NOTIFY_LED_ON,
+  NOTIFY_LED_PTN0,
+  NOTIFY_LED_PTN1,
+  NOTIFY_LED_PTN2
+};
+
+
+// VREG_C_CAM_LED
+enum CAM_LED_MODE
+{
+  CAM_LED_OFF = 0,
+  CAM_LED_BLINK,
+  CAM_LED_ON,
+  CAM_LED_BY_TWL,
+  CAM_LED_ON_PLUSE,
+  CAM_LED_OFF_PLUSE
+};
+
+
+
+// ���m�点LED�����֌W //
+typedef struct _st_info_LED
+{
+    u8 term;                    // 1�t���[�����`�b�N�H
+    u8 fade_time;               // ���`�b�N�Ŏ��̃t���[���̐F�ɒB���邩
+    u8 last_loop;               // �ŏI�t���[�����J��Ԃ��H
+    u8 resv1;
+    u8 red[32];
+    u8 grn[32];
+    u8 blu[32];
+}st_info_LED;
+
+typedef union _uni_info_LED
+{
+    st_info_LED info_LED;
+    u8 bindata[ sizeof( st_info_LED ) ];
+}uni_info_LED;
+
+extern uni_info_LED info_LED;
+
+
+// ��LED �_�Ō��� //
+typedef struct _st_led_red_batt_empty
+{
+    u8 dats[4];
+}st_led_red_batt_empty;
+
+extern st_led_red_batt_empty led_red_batt_empty;
+
+
+/*
+   ���m�点LED
+*/
+typedef struct _st_LED_dim_status
+{
+    sx16 to;
+    sx16 delta;
+    sx16 now;                   // �����_�ȉ����o���Ă����Ȃ��Ă͂Ȃ�Ȃ�����
+}st_LED_dim_status;
+
+
+
+// ====================================
+void LED_init(  );
+void LED_stop(  );
+
+
+// ====================================
+extern bit ledInitialized;
+extern bit info_led_override;
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/led_cam.c b/tags/2.03_SDK-3.1/led_cam.c
new file mode 100644
index 0000000..80224a7
--- /dev/null
+++ b/tags/2.03_SDK-3.1/led_cam.c
@@ -0,0 +1,151 @@
+/******************************************************//**
+  LED_Cam          TO02
+\n  BLINK,*_PLUSE �̎��́A1�������͕K�����̏�ԂɂȂ�܂��B
+\n  ���̊Ԃ� OFF��BLINK �Ȃǂ����ƁAOFF����������܂��B
+ *********************************************************/
+#ifndef _WIN32
+
+#pragma sfr
+
+#endif
+
+#include "incs.h"
+#include "led.h"
+
+
+
+// ========================================================
+static u8 state_led_cam = 0;
+static u16 task_interval;
+
+bit cam_led_update;
+
+
+
+// ========================================================
+static void cam_led_twl();
+extern void DI_wt_chk();
+
+
+
+
+// ========================================================
+// �C���^�[�o�����s�^�X�N�ƁAtwl���W�X�^�ւ̏������݂̂Q�J������
+// �Ă΂�܂��B
+void tsk_led_cam(  )
+{
+	DI_wt_chk();                    // ���W�X�^�ւ̏������݂ŋ����N���������邱�Ƃ����邽��
+    if( !cam_led_update )
+    {
+        if( task_interval != 0 )
+        {
+            task_interval --;
+			EI();
+            return;
+        }
+    }
+
+	cam_led_update = false;  // TWL �̃u�����N�ݒ�i�ꔭ�����_���j�̂���
+	EI();
+
+	if( system_status.pwr_state == SLEEP )  // sleep���A��������
+	{
+        LED_CAM = 0;
+        state_led_cam = 0;
+	}
+	else
+	{
+		// �u�����N�̂悤�ɑ҂��������Ƃ��ȊO�͖��T�N������
+		//  (���W�X�^�̕ύX�ɂ����ɔ�������)
+		switch ( vreg_ctr[VREG_C_LED_CAM] )
+		{
+		case ( CAM_LED_OFF ):
+		default:
+			LED_CAM = 0;
+			state_led_cam = 0;
+			break;
+
+		case ( CAM_LED_ON ):
+			LED_CAM = 1;
+			state_led_cam = 0;
+			break;
+
+		case ( CAM_LED_BLINK ):
+			if( state_led_cam == 0 )
+			{
+				LED_CAM = 1;
+				state_led_cam = 1;
+			}
+			else
+			{
+				LED_CAM = 0;
+				state_led_cam = 0;
+			}
+			task_interval = 250;
+			break;
+
+		case ( CAM_LED_ON_PLUSE ):
+			if( state_led_cam == 0 )
+			{
+				LED_CAM = 1;
+				state_led_cam = 1;
+				task_interval = 250;
+			}
+			else
+			{
+				vreg_ctr[VREG_C_LED_CAM] = CAM_LED_OFF;
+			}
+			break;
+
+		case ( CAM_LED_OFF_PLUSE ):
+			if( state_led_cam == 0 )
+			{
+				LED_CAM = 0;
+				state_led_cam = 1;
+				task_interval = 250;
+			}
+			else
+			{
+				vreg_ctr[VREG_C_LED_CAM] = CAM_LED_ON;
+			}
+			break;
+
+		case( CAM_LED_BY_TWL ):
+			cam_led_twl();
+		}
+	} // if( system_status.pwr_state == sleep ) ... else ...
+}
+
+
+
+static void cam_led_twl()
+{
+	// TWL�݊� //
+	switch ( vreg_twl[ REG_TWL_INT_ADRS_CAM ] ){
+	case( TWL_CAMLED_OFF ):
+		LED_CAM = 0;
+		state_led_cam = 0;
+		break;
+
+	case( TWL_CAMLED_BLINK ):
+		if( state_led_cam == 0 )
+		{
+			LED_CAM = 1;
+			state_led_cam = 1;
+		}
+		else
+		{
+			LED_CAM = 0;
+			state_led_cam = 0;
+		}
+		task_interval = (u8)( 600 / SYS_INTERVAL_TICK ) + 250;
+		break;
+
+	case( TWL_CAMLED_ON ):
+	case( TWL_CAMLED_DEF_ON ):
+	default:
+		LED_CAM = 1;
+		state_led_cam = 1;
+		break;
+	}
+}
diff --git a/tags/2.03_SDK-3.1/led_pow.c b/tags/2.03_SDK-3.1/led_pow.c
new file mode 100644
index 0000000..5906ee8
--- /dev/null
+++ b/tags/2.03_SDK-3.1/led_pow.c
@@ -0,0 +1,269 @@
+/* ========================================================
+  // �d��LED
+  LED_POW_B,R         6,7
+
+  TDR00�@����(0x03FF�BTPS0��250kHz�ŃJ�E���g�A�b�v�B10bit�Ȃ�250Hz�ʂɂȂ�)
+  TDR0x�@Duty 0�ŏ����ATDR00(���� =0x03FF�ȏ�)�œ_���ł��B
+
+  enum pwr_state_{
+  OFF_TRIG = 0,
+  ON_CHECK,
+  ON_TRIG,
+  ON,
+  SLEEP
+};
+
+enum LED_ILUM_MODE{
+  LED_POW_ILM_AUTO,
+  LED_POW_ILM_ON,
+  LED_POW_ILM_SLEEP,
+  LED_POW_ILM_CEOFF
+};
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma sfr
+
+#endif
+
+#include "incs.h"
+#include "led.h"
+
+
+// ========================================================
+// �X���[�v�����ł̃e�[�u���B�}�W���B
+const u8 LED_PTN_SLEEP[] = {
+     25,  38,  52,  68,  83,  98, 110, 119,
+    125, 128, 128, 125, 119, 110,  98,  83,
+     68,  52,  38,  25,  16,  10,   8,   8,
+      8,   8,   8,   8,   8,   8,  10,  16
+      };
+
+
+// ��LED�̓d�r�c��LED�̓_�Ńp�^�[��
+st_led_red_batt_empty led_red_batt_empty = { 0x55, 0x55, 0x55, 0x55 };
+#define LED_SLEEP_FRAME_LEN 71
+#define LED_SLEEP_DIM_LEN   71
+#define LED_SLEEP_FRAME_NUM 32
+
+
+
+// ========================================================
+static void led_pow_normal(  );
+static void led_pow_sleep(  );
+static void led_pow_bt_empty();
+static u8 led_pow_batt_low();
+
+#define led_fade_to( now, goal )       now = fade_to( now, goal )
+extern u8 fade_to( u8 now, u8 goal );
+
+#define led_fade_to2( led, status )    led = fade_to2( status )
+extern u8 fade_to2( st_LED_dim_status* status );
+
+
+
+// ========================================================
+// �d��LED�̃X���[�v�p�^�[���̃X�e�[�^�X��
+static u8 time_to_next_frame_sleep = LED_SLEEP_FRAME_LEN;
+static u8 frame_sleep;
+static st_LED_dim_status LED_dim_status_sleep;
+
+extern bit ledInitialized;
+extern bit BT_IN_CHG_delayed_n; 
+
+
+
+// ========================================================
+void tsk_led_pow(  )
+{
+	if( ! ledInitialized )
+	{
+		return;
+		// �����܂�
+	}
+
+    info_led_override = false;
+
+    switch ( vreg_ctr[VREG_C_LED_POW] )
+    {
+    case ( LED_POW_ILM_AUTO ):
+    default:
+        led_pow_normal(  );
+        break;
+
+    case ( LED_POW_ILM_SLEEP ):
+        led_pow_sleep(  );
+        break;
+
+    case ( LED_POW_ILM_ON ):
+        led_fade_to( LED_duty_pow_blu, vreg_ctr[VREG_C_LED_BRIGHT] );
+        LED_pow_red = 0;
+        break;
+
+    case ( LED_POW_ILM_OFF ):
+        led_fade_to( LED_duty_pow_blu, 0 );
+        LED_pow_red = 0;
+        break;
+
+    case ( LED_POW_ILM_ONLY_RED ):
+        LED_duty_pow_blu = 0;
+        LED_pow_red = 1;
+        break;
+
+    case ( LED_POW_ILM_ONLY_BLUE ):
+        LED_duty_pow_blu = LED_BRIGHT_MAX;
+        LED_pow_red = 0;
+        break;
+
+    case ( LED_POW_ILM_FORCE_BT_EMPTY ):
+        led_pow_bt_empty();
+        break;
+    }
+
+	if( system_status.pwr_state == OFF || system_status.pwr_state == ON_CHECK )
+	{
+        LED_pow_red = 0;
+	    info_led_override = false;
+    }
+
+    if( info_led_override )
+    {
+        LED_duty_notify_blu = 0;
+        LED_duty_notify_grn = 0;
+		LED_duty_notify_red = ( LED_pow_red == 0 )? 0 : 255;
+    }
+}
+
+
+
+/* ========================================================
+  �d�r�c�ʂŁA�@���ԁ��ԓ_��
+ ======================================================== */
+static void led_pow_normal(  )
+{
+    time_to_next_frame_sleep = LED_SLEEP_FRAME_LEN;
+    frame_sleep = 0;
+    LED_dim_status_sleep.now = (sx16)LED_duty_pow_blu * 128;
+
+    if( led_pow_batt_low() != 0 )  // �Ԃ̓_�������ł���Ă��܂�
+    {
+        return;
+        // �����܂�
+    }
+
+    // �“_��
+    led_fade_to( LED_duty_pow_blu, vreg_ctr[VREG_C_LED_BRIGHT] );
+}
+
+
+
+/* ========================================================
+  �z�^���p�^�[��
+   �d�r�c�ʂŐԁ��ԓ_�łɂ���
+ ======================================================== */
+static void led_pow_sleep(  )
+{
+    if( led_pow_batt_low() != 0 )		// �Ԃ̓_�������ł���Ă��܂�
+    {
+        time_to_next_frame_sleep = LED_SLEEP_FRAME_LEN;
+        frame_sleep = 0;
+        LED_dim_status_sleep.now = (sx16)LED_duty_pow_blu * 128;
+        return;
+        // �����܂�
+    }
+
+    LED_dim_status_sleep.to = LED_PTN_SLEEP[frame_sleep] * 128;
+
+    // �O���f�[�V�����̃f���^���v�Z
+    LED_dim_status_sleep.delta = (( LED_dim_status_sleep.to - LED_dim_status_sleep.now ) ) / LED_SLEEP_DIM_LEN;
+    led_fade_to2( LED_duty_pow_blu, &LED_dim_status_sleep );
+
+    // ���̃t���[���ɐi�߂�H
+    time_to_next_frame_sleep --;
+    if( time_to_next_frame_sleep == 0 )
+    {
+        time_to_next_frame_sleep = LED_SLEEP_FRAME_LEN;
+
+        frame_sleep ++;
+        if( frame_sleep >= LED_SLEEP_FRAME_NUM -1 )
+        {
+            frame_sleep = 0;
+        }
+    }
+}
+
+
+
+/* ========================================================
+  �d�r�����Ȃ��Ƃ��̋���
+�@�Ԓl�F�@0�@�d�r�����Ȃ��Ȃ�����
+�@�@�@�@�@1�@�@�@�@���Ȃ������̂ŋ��ʃp�^�[���ɂ���
+ ======================================================== */
+static u8 led_pow_batt_low()
+{
+    if( vreg_ctr[VREG_C_BT_REMAIN] > BATT_TH_LO )
+    {
+        LED_pow_red = 0;
+        return 0;
+        // �����܂�
+    }
+
+    if(( vreg_ctr[VREG_C_BT_REMAIN] > BATT_TH_EMPTY ) || !BT_IN_CHG_delayed_n )
+		// �d�r�c�ʂ�5%�i�`10%�j�@�܂��́A���ꖢ���ł��[�d��
+    {
+        // �ԓ_��
+        led_fade_to( LED_duty_pow_blu, 0 );
+		{
+	        LED_pow_red = 1;
+		}
+
+    }
+    else // �d�r��5%�����@���@�A�_�v�^�Ȃ�
+    {
+        led_pow_bt_empty();
+    }
+    return 1;
+}
+
+
+
+
+/* ========================================================
+�@�d�r���Ȃ��p�^�[��
+�@�@�w��p�^�[���𗬂�
+�@�@���m�点���㏑�������肷��
+ ======================================================== */
+static void led_pow_bt_empty()
+{
+    static u8 delay;
+    static u8 red_blink_poi;
+
+    info_led_override = true;
+
+    // �ԓ_��
+    led_fade_to( LED_duty_pow_blu, 0 );
+
+    // �Ԃ̓_�Ńp�^�[�����w��ł���
+    delay ++;
+    if( delay < 64 ) // �t���[���̕ێ����ԉ҂�
+    {
+        return;
+    }
+    delay = 0;
+
+    if( led_red_batt_empty.dats[ red_blink_poi / 8 ] & ( 1 << ( red_blink_poi % 8 )) )
+    {
+        LED_pow_red = 1;
+    }
+    else
+    {
+        LED_pow_red = 0;
+    }
+    red_blink_poi ++;
+    if( red_blink_poi >= 32 )
+    {
+        red_blink_poi = 0;
+    }
+}
+
+
diff --git a/tags/2.03_SDK-3.1/loader.c b/tags/2.03_SDK-3.1/loader.c
new file mode 100644
index 0000000..e820819
--- /dev/null
+++ b/tags/2.03_SDK-3.1/loader.c
@@ -0,0 +1,406 @@
+/* ========================================================
+  MCU CTR BSR
+  2009/03/30
+  �J���Z�p�� ���c
+
+  �u�[�g���[�_�[��
+  �z�X�g�̒ʐM�ƁA���ȏ��������A�t�@�[���̃`�F�b�N���s���B
+
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma SFR
+#pragma di
+#pragma ei
+#pragma nop
+#pragma stop
+#pragma halt
+#pragma opc
+
+#endif
+#include "incs_loader.h"
+
+#include <fsl.h>
+#include "fsl_user.h"
+
+#include "i2c_ctr.h"
+#include "i2c_mcu.h"
+#include "pm.h"
+#include "rtc.h"
+
+#include "reboot.h"
+
+#include "magic.h"
+
+
+
+#define REG_BIT_RESF_WDT     0x10
+#define REG_BIT_RESF_TRAP    0x80
+#define REG_BIT_RESF_LVI     0x01
+
+
+
+// ========================================================
+#if (FSL_DATA_BUFFER_SIZE>0)
+fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE];
+#endif
+
+
+
+#ifdef   FSL_INT_BACKUP
+static fsl_u08 fsl_MK0L_bak_u08;        /*    if (interrupt backup required)            */
+static fsl_u08 fsl_MK0H_bak_u08;        /*    {                                         */
+static fsl_u08 fsl_MK1L_bak_u08;        /*      reserve space for backup information    */
+static fsl_u08 fsl_MK1H_bak_u08;        /*      of interrupt mask flags                 */
+static fsl_u08 fsl_MK2L_bak_u08;        /*                                              */
+static fsl_u08 fsl_MK2H_bak_u08;        /*    }                                         */
+#endif
+
+
+
+// ========================================================
+void	hdwinit();
+static void	hdwinit2();
+static void	chk_platform_type();
+static void	chk_firm_broke();
+
+
+extern void main_loop();
+
+
+
+// ========================================================
+void main(  )
+{
+    while( 1 )
+    {
+        WDT_Restart(  );
+
+        if( RTCEN )  // �����TRAP(����update)�ɂ����g���Ȃ��BWDT���ł͗����Ȃ�
+        {
+            system_status.reboot = true;
+        }
+
+        {
+            volatile u8 my_resf = RESF;         // ���ǂނƏ�����
+            if( ( my_resf & REG_BIT_RESF_WDT ) != 0 )
+            {
+                vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_RESET;
+                // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
+                // ��I2C�̏�������ɍs��
+                system_status.reboot = true;
+            }
+            else if( ( my_resf & REG_BIT_RESF_TRAP ) != 0 ) // ( FSL_ForceReset, 'r' )
+            {
+                system_status.reboot = true;
+            }
+/* LVI�g�p����
+            else if(( my_resf & REG_BIT_RESF_LVI ) != 0 )
+            {
+                    vreg_ctr[ VREG_C_MCU_STATUS ] |= ( 1 << 2 );
+            }
+*/
+        }
+//* ROM���ǂ��ɂ�����Ȃ��Ȃ�����A�]���̏�R�����g�A�E�g
+        if( !system_status.reboot )
+        {
+            // �ʏ�̓d������
+            // �d�r�ڑ����A������Ƒ҂��Ă݂�(�`���^�����O�΍�)
+            u16      pwup_delay0;
+            for( pwup_delay0 = 0xFFFF; pwup_delay0 != 0; pwup_delay0 -- ){;};
+        }
+//*/
+        hdwinit2(  );
+
+#ifndef _WIN32
+        // �t�@�[���̐������`�F�b�N //
+        chk_firm_broke();	// ���Ă�����A���Ă��Ȃ�
+#endif
+
+        // ���V�䔻�� 
+        chk_platform_type();
+
+        // HAL�f�o�b�O���Z�b�g
+        hal_reset();
+        hal_update();
+
+        // RTC ������
+        RTC_init(  );               // �����Ń��u�[�g�����肵�ď��������邩���f���܂�
+
+        // �ʏ�^�]
+        main_loop(  );
+    }
+}
+
+
+
+void chk_firm_broke()
+{
+#ifndef _ENABLE_HAL_	// ROM�s���ׁ̈A�f�o�b�O���̂�
+    u8      i;
+    u8      comp = 0;
+
+    // ���[�_�[�Ɩ{�͓̂����o�[�W�������H
+    /// ���ւ̃A�b�v�f�[�g�̓r���ŏI����ĂȂ����H
+    for( i = 0; i < sizeof( __TIME__ ); i++ )      // sizeof( __TIME__ ) = 8 �炵
+    {
+        comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( u8 * )( MGC_FOOT + i ) ) ? 0 : 1;
+        comp += ( *( u8 * )( MGC_HEAD + i ) == *( u8 * )( MGC_FOOT + i ) ) ? 0 : 1;
+    }
+
+    if( *( u8 * )( MGC_FOOT +2 ) != ':' )  // �����ς̂܂�
+    {
+        comp ++;
+    }
+
+    if( comp != 0 )
+    {
+        // �t�@�[�����X�g�A�����݂�
+        firm_restore(  );
+        // �A���Ă��Ȃ��B���Z�b�g��������B
+    }
+#endif
+}
+
+
+/* ========================================================
+  �f�o�b�K�‚Ȃ��ł�Ə��ɔ���ł��Ȃ����Ƃ�����܂��B
+��CTR�t�@�~��
+ DEV_DET(P12.[2:1])
+  
+��CTR�����̊J���@��
+ P40,41                   !����! �f�o�b�O�L����P40��L����MCU���N�����܂���I
+ HH ���@
+ HL NBD���V��
+ LH �X�^���h�A�������V��
+ LL IS�f�o�b�K
+======================================================== */
+void chk_platform_type()
+{
+    // ��CTR�t�@�~�� //
+	system_status.family = (enum family_)( DEV_DET >> 1 );  /// ����...
+	if( system_status.family == FAMILY_SPFL )
+	{
+		pm_reg_bit_vddlcd = PM_REG_BIT_VDDLCD_AMO;
+	}
+	else
+	{
+		pm_reg_bit_vddlcd = PM_REG_BIT_VDDLCD_CGS;
+	}
+
+	// ��CTR�����̊J���@�� //
+	// �ꉞ������
+	system_status.is_dev = false;
+	system_status.taikendai = false;
+	system_status.taikendai_nbd = false;
+
+	switch( DIPSW )
+	{
+		case DIPSW_TAIKENDAI:
+			system_status.taikendai = true;
+			break;
+
+		case DIPSW_TAIKENDAI_NBD:
+			system_status.taikendai_nbd = true;
+			break;
+
+		case DIPSW_ISDEV:
+	        system_status.is_dev = true;
+			break;
+	}
+#ifdef _FORCE_TAIKENDAI_
+	system_status.taikendai = true;
+#endif
+
+#ifdef _FORCE_TAIKENDAI_NBD_
+	system_status.taikendai_nbd = true;
+#endif
+}
+
+
+
+
+// ========================================================
+void hdwinit( void )
+{                               // �X�^�[�g�A�b�v���[�`��������ɌĂт܂�
+    DI(  );                     /* �}�X�^���荞�݋֎~ */
+
+    CMC = bits8(0,0,0,1, 0,0,0,0);          /* X1���U����(���̓|�[�g)�AXT1�g�p�A����d�͔��U�͕s����ɕt���ʏ�� */
+    CSC = bits8(1,0,0,0, 0,0,0,0);          /* X1���U�Ȃ��AXT1���U����A�����������U���� */
+    OSMC = 0x01;				              /* �B�����W�X�^ */
+	NOP();NOP();NOP();  // 3clk�J����
+    CKC = bits8(0,0,0,0, 1,0,0,0);          /* CPU/���ӃN���b�N=fMAIN�AfMAIN=fMX�AfCLK=fMX */
+
+    /*--- ��d�����o��H�̐ݒ� ---*/
+    /* ���Z�b�g�������̃f�t�H���g�́A�I�v�V�����E�o�C�g�ɂĎw�肳��� */
+    LVIS = 0x00;         /* VLVI = 4.22�}0.1V */
+//  LVIM = 0x00;         /* LVI����֎~ */
+    /* �d���d��(VDD)�����o�d��(VLVI)���Ɋ������� */
+    /* �d���d��(VDD)�����o�d��<VLVI)�A�܂��͓���֎~���ɒ�d�����o */
+}
+
+
+
+/* ********************************************************
+ ���u�[�g���Ƃœ������Ⴄ����
+********************************************************** */
+static void hdwinit2(  )
+{
+	// �|�[�g�ݒ� //
+
+	// ���Z�b�g��̏����l���ۏ؂���Ă���̂͏ȗ�
+    if( system_status.reboot )  // ���Z�b�g�s�������͂����ɃZ�b�g����
+    {
+        P0  = bits8(0,0,0,0, 0,0,1,1);  // -,-,-,-, -,-,/reset2,/reset1
+        P3  = bits8(0,0,0,0, 1,1,1,1);  // -,-,-,-, i2c_pu,scl_m,sda_m,/fcr_rst		// �Ȉ�I2C�͏o�̓��b�`��1�ɂ���
+    }
+    else
+    {
+		// ���Z�b�g��̏����l0���ۏ؂���Ă���̂͏ȗ�
+//      P0  = bits8(0,0,0,0, 0,0,0,0);  // -,-,-,-, -,-,/reset2,/reset1
+//      P1  = bits8(0,0,0,0, 0,0,0,0);  // bt_temp_p,bt_det_p,led_info_r,led_pow_b led_info_g,32khz_o,led_wifi,led_info_b
+//      P2  = bits8(0,0,0,0, 0,0,0,0);  // ad_vol,ad_3d,acc_int1,led_chg, (sw_sel),(rbr_flight),(/rbr_rst),(ext_vdd33)
+        P3  = bits8(0,0,0,0, 1,1,1,0);  // -,-,-,-, i2c_pu,scl_m,sda_m,/fcr_rst		// �Ȉ�I2C�͏o�̓��b�`��1�ɂ���
+//      P6  = bits8(0,0,0,0, 0,0,0,0);  // -,-,-,-, -,-,sda2,scl2
+//      P7  = bits8(0,0,0,0, 0,0,0,0);  // slp_o,/irq,led_cam,sw_wifi, sw_pow,pm_irw,shell_close,/extdc
+//      P12 = bits8(0,0,0,0, 0,0,0,0);  // -,-,-,xtal, xtal,dip(�@�픻��)[1,0],slp_i
+//      P14 = bits8(0,0,0,0, 0,0,0,0);  // -,-,-,-, -,-,i2c_pu,i2c_pu				// i2c_pu�̃|�[�g�ݒ�͂����Ɛ�p�֐����g���ď��ԂɁB
+//      P15 = bits8(0,0,0,0, 0,0,0,0);  // -,-,-,-, -,-,ad_bt_det,ad_bt_temp		// AD�͂ǂ����ł�
+//      P20 = bits8(0,0,0,0, 0,0,0,0);  // -,-,accel2,sw_home, wl_tx,amoled_hv,sda1,sda2�B	// spfl reboot���̉t���d���̃P�A�͌�ق�
+
+        /*--- �^�C�}�E�A���C�E���j�b�g�̓����~ ---*/
+//      TAU0EN = 0;                 /* �^�C�}�E�A���C�E���j�b�g�ւ̃N���b�N������~ */
+        TT0 = 0x00ff;               /* �S�^�C�}�E�`���l���̓����~ */
+
+        /*--- RTC�̓����~ ---*/
+        // �ʓr�������֐�
+    }
+
+    P4  = bits8(0,0,0,0, 1,0,0,0);  // -,-,-,-, /chg_en, led_pow_r, dipsw[1,0]
+    P5  = bits8(0,0,0,0, 1,0,0,0);  // -,-,-,-, i2c_pu,led_3d,/chg,/gyro_cs
+
+    /*--- ���荞�ݐݒ� ---------*/
+//    IF0 = 0x0000;               /* ���荞�ݗv���t���O�N���A */
+//    IF1 = 0x0000;
+//    IF2 = 0x0000;
+//    MK0 = 0xFFFF;               /* ���荞�݋֎~ */
+//    MK1 = 0xFFFF;
+//    MK2 = 0xFFFF;
+
+
+//  PM0  = bits8(1,1,1,1, 1,1,1,1);     // BSR�}�C�R���ł́Areset1�͊Ď��݂̂ɂȂ�B
+    PM1  = bits8(0,0,0,0, 0,0,0,0);
+    PM2  = bits8(1,1,1,0, 1,0,0,1);
+    PM3  = bits8(1,1,1,1, 1,0,0,0);     // P31,32�͊Ȉ�I2C
+    PM4  = bits8(1,1,1,1, 0,0,1,1);
+    PM5  = bits8(1,1,1,1, 1,0,1,0);
+    PM6  = bits8(1,1,1,1, 1,1,0,0);		// I2C�̃��C����L�o�͂ɂȂ��Ă��܂����A�V�X�e����OFF�Ȃ̂ł��܂�Ȃ�
+    PM7  = bits8(0,1,0,1, 1,1,1,1);
+//    PM12 = bits8(1,1,1,1, 1,1,1,1);	// 32kHz�N���b�N�̃s���ݒ�͂ǂ����ł��悢
+    PM14 = bits8(1,1,1,1, 1,1,0,0);
+//    PM15 = bits8(1,1,1,1, 1,1,1,1);
+    PM20 = bits8(1,1,1,1, 1,0,0,0);		// p20.2�͂�������O��L�ɂ��Ă�������
+
+    PU20 = bits8(0,0,0,1, 0,0,0,1);
+//  PU0  = bits8(0,0,0,0, 0,0,0,0);		// �o�b�e���F�،�ɂ��ꂼ��Z�b�g
+//  PU1  = bits8(0,0,0,0, 0,0,0,0);
+//  PU3  = bits8(0,0,0,0, 0,0,0,0);		// �O���Ńv���A�b�v���Ȃ��Ƌ�������BCPU���v���A�b�v����
+//  PU4  = bits8(0,0,0,0, 0,0,0,0);		// �O���Ńv���A�b�v���Ăق���tool0,1)
+    PU5  = bits8(0,0,0,0, 0,0,1,0);
+    PU7  = bits8(0,0,0,1, 1,0,0,1);		 // irq(7.6)cpu��pu
+//  PU12 = bits8(0,0,0,0, 0,0,0,0);
+//  PU14 = bits8(0,0,0,0, 0,0,0,0);
+
+    // �|�[�g���̓��[�h�E���W�X�^�ݒ� /////////////////////
+    // [0:�ʏ���̓o�b�t�@ 1:TTL���̓o�b�t�@]
+//  PIM3 = bits8(0,0,0,0, 0,0,0,0);
+//  PIM7 = bits8(0,0,0,0, 0,0,0,0);
+
+    // �|�[�g�o�̓��[�h�E���W�X�^�ݒ�
+    // [0:�ʏ�o�̓��[�h 1:N-ch�I�[�v���E�h���[���o��]
+    POM3 = bits8(0,0,0,0, 0,1,1,0);
+//  POM7 = bits8(0,0,0,0, 0,0,0,0);
+
+    /* ���荞�ݗD�揇�ʁA�S�Ē��(LV3) */
+//  PR00 = 0xFFFF;
+//  PR01 = 0xFFFF;
+//  PR10 = 0xFFFF;
+    PR11 = 0xFFFE;
+//  PR02 = 0xFFFF;
+//  PR12 = 0xFFFF;
+
+    /*--- �O�������̗L���G�b�W�ݒ� ---*/
+    EGP0 = bits8(0,0,1,1, 0,0,0,1);
+    EGN0 = bits8(0,1,1,1, 0,0,0,0);
+    EGP2 = bits8(0,0,0,0, 1,0,1,0);
+//    EGN2 = bits8(0,0,0,0, 0,0,0,0);
+
+    /*--- �L�[���荞�ݐݒ� ---*/
+//  KRM = bits8(0,0,0,0, 0,0,0,0);          /* �S�L�[���荞�ݐM�������o���Ȃ� */
+
+    /*--- ADC�̓����~ ---*/
+//  ADCEN = 0;                  /* ADC�ւ̃N���b�N������~ */
+//  ADM  = bits8(0,0,0,0, 0,0,0,0);          /* �ϊ������~ */
+
+    /*--- �V���A���E�A���C�E���j�b�g�̓����~ ---*/
+//  SAU0EN = 0;                 /* �V���A���E�A���C�E���j�b�g0�ւ̃N���b�N������~ */
+    SCR00 = 0x0087;             /* �e�`�����l���̒ʐM�֎~ */
+    SCR01 = 0x0087;
+    SCR02 = 0x0087;
+    SCR03 = 0x0087;
+
+    // IIC�̓����~
+//  IICA0EN = 0;                /* IICA0(CTR)�ւ̃N���b�N������~ */
+//  IICCTL00 = 0x00;            /* IICA1�����~ */
+//  IICA1EN = 0;                // IICA1(TWL)�ւ̃N���b�N������~
+//  IICCTL01 = 0x00;            // IICA1�����~
+
+    /*--- DMA�̓����~ ---*/
+//  DRC0 = bits8(0,0,0,0, 0,0,0,0);         /* DMA�`���l��0�̓���֎~ */
+//  DRC1 = bits8(0,0,0,0, 0,0,0,0);         /* DMA�`���l��1�̓���֎~ */
+
+    /*--- �N���b�N�o��/�u�U�[�o�͒�~ ---*/
+//  CKS0 = bits8(0,0,0,0, 0,0,0,0);
+//  CKS1 = bits8(0,0,0,0, 0,0,0,0);
+}
+
+
+
+/******************************************************************************
+  �P�ʂ� ms
+  NOP���񂷂����A�w�莞��CPU�� *��L���܂�* �B
+  ���荞�݂Ƃ�����Ƃ��̕��x��܂��B
+  �����덷����܂��B
+ *****************************************************************************/
+void wait_ms( u8 ms ){
+  u16 fine;
+
+  WDT_Restart();
+  while( ms != 0 ){
+    ms--;
+    fine = 860;
+    while( fine != 0 ){
+      fine --;
+    }
+  }
+}
+
+
+
+
+extern unsigned char get_ei();
+
+void DI_wt_chk()
+#ifdef _DI_WITH_CHECK_
+{
+	if( !get_ei() )
+	{
+		dbg_nop();
+	}
+	DI();
+}
+#else
+{
+	DI();
+}
+#endif // _DI_WITH_CHECK_
diff --git a/tags/2.03_SDK-3.1/loader.h b/tags/2.03_SDK-3.1/loader.h
new file mode 100644
index 0000000..3b9faa6
--- /dev/null
+++ b/tags/2.03_SDK-3.1/loader.h
@@ -0,0 +1,7 @@
+#ifndef _loader_h_
+#define _loader_h_
+
+void wait_ms( u8 );
+
+#endif
+
diff --git a/tags/2.03_SDK-3.1/magic.c b/tags/2.03_SDK-3.1/magic.c
new file mode 100644
index 0000000..75aa461
--- /dev/null
+++ b/tags/2.03_SDK-3.1/magic.c
@@ -0,0 +1,29 @@
+/*****************************************************************************
+�r���h�����𖄂ߍ��݂܂��B
+�r���h�̓x�ɍX�V�����悤�ɂ���K�v������܂��B
+(touch����)
+ ****************************************************************************/
+#include "config.h"
+#include "magic.h"
+
+#ifndef _WIN32
+
+#pragma section @@CNSTL MGC_LOAD AT 0x0FF6
+__far const unsigned char MGC_LOADd[] = __TIME__;
+
+#ifdef _firm_format_v3_
+#pragma section @@CNST MGC_MIMI AT 0x2000
+const unsigned char MGC_HEADdN[] = __TIME__;
+
+#else
+#pragma section @@CNST MGC_MIM2 AT 0x2100
+const unsigned char MGC_HEADd[] = __TIME__;
+#endif
+
+#pragma section @@CNST MGC_TAIL AT 0x4FF6
+const unsigned char MGC_TAILd[] = __TIME__;
+
+#pragma section @@CNST MGC_VER AT 0x4FF4
+const unsigned char MCU_VER[2] = { MCU_VER_MAJOR +'0', MCU_VER_MINOR +'0' };
+
+#endif
diff --git a/tags/2.03_SDK-3.1/magic.h b/tags/2.03_SDK-3.1/magic.h
new file mode 100644
index 0000000..b80bfb2
--- /dev/null
+++ b/tags/2.03_SDK-3.1/magic.h
@@ -0,0 +1,24 @@
+#ifndef _magic_h_
+
+#define _magic_h_
+
+// magic.c �̋L�q�ƈ��Ȃ��悤�ɒ��ӁI
+#define MGC_LOAD   0x0FF6
+#define MGC_FOOT   0x4FF6
+
+#ifdef _firm_format_v3_
+#define MGC_HEAD   0x2000
+#else
+#define MGC_HEAD   0x2100
+#endif
+
+#define MGC_LOAD_BKUP   0x1FF6
+#define MGC_FOOT_BKUP   0x7FF6
+
+#ifdef _firm_format_v3_
+#define MGC_HEAD_BKUP  0x5000
+#else
+#define MGC_HEAD_BKUP   0x5100
+#endif
+
+#endif
diff --git a/tags/2.03_SDK-3.1/main.c b/tags/2.03_SDK-3.1/main.c
new file mode 100644
index 0000000..5cfb7da
--- /dev/null
+++ b/tags/2.03_SDK-3.1/main.c
@@ -0,0 +1,91 @@
+/* ========================================================
+  MCU CTR BSR
+                                       2008,2009 nintendo
+                                       �J���Z�p���@���c
+ ======================================================== */
+
+
+// ========================================================
+//#include "incs_loader.h"
+#include "incs.h"
+
+#include "WDT.h"
+#include "rtc.h"
+#include "pm.h"
+#include "accero.h"
+#include "led.h"
+#include "adc.h"
+
+#include "pool.h"
+
+
+// ========================================================
+system_status_ system_status;
+uni_pool pool;
+bit force_off;
+
+#ifdef i2c_timeout_test
+bit i2c_mcu_time_out_error;      // I2C�����炩�ŋl�܂����B���I�ȂNJ܂ށB
+extern void i2c_mcu_error_monitor();
+#endif
+
+extern bit pm_extdc_old;
+
+/* ========================================================
+ �{���̃G���g���֐��� loader.c �ɂ���܂�
+ ======================================================== */
+void main_loop( void )
+{
+    renge_init(  );
+
+#ifdef i2c_timeout_test
+    i2c_mcu_time_out_error = false;
+#endif
+    iic_mcu_start(  );
+
+    EI(  );
+
+    BT_chk();
+
+    system_status.pwr_state = OFF_TRIG;
+    // ���u�[�g����
+    if( system_status.reboot )
+    {
+        // �{�̓d��on�Ȃ�Aon���p��������
+        if( PM_chk_LDSW() )
+        {
+            system_status.pwr_state = ON_TRIG;
+        }
+        vreg_ctr[VREG_C_BT_REMAIN] = 100;
+        pm_extdc_old = PM_EXTDC_n_RAW;			// ���u�[�g���A�[�dLED���O��̏�Ԃ𑱂���悤��
+    }
+    else
+    {
+        pm_extdc_old = ~PM_EXTDC_n_RAW;			// �A�_�v�^��POR���ɓ_���邽�߁B
+    }
+
+    vreg_ctr_init(  );
+
+    clear_hosu_hist(); // �����N���A
+
+    renge_task_interval_run_force = true;
+
+    RTCIMK = 0;                 /* ���荞��(�A���[��&�C���^�[�o��)���� */
+
+    // ���C�����[�v //
+    while( 1 )
+    {                           // �V�X�e��tick�A�܂��͊��荞�݂ʼn��܂��B
+        renge_task_interval_run(  );    // �����ŁA�V�X�e��tick�܂��͋����N�����܂�
+        renge_task_immed_run();
+#ifdef i2c_timeout_test
+        if( i2c_mcu_time_out_error )
+        {
+            i2c_mcu_error_monitor();
+        }
+#endif
+        HALT(  );
+    }
+}
+
+
+
diff --git a/tags/2.03_SDK-3.1/nec_s_2_bsrbin2.rb b/tags/2.03_SDK-3.1/nec_s_2_bsrbin2.rb
new file mode 100755
index 0000000..c4c33fa
--- /dev/null
+++ b/tags/2.03_SDK-3.1/nec_s_2_bsrbin2.rb
@@ -0,0 +1,82 @@
+#!/usr/bin/ruby
+$KCODE = "S"
+=begin
+
+�@NEC�̊‹����f��������SREC���A
+�@�@�����w�蕔���ɂ�0xFF�p�f�B���O���A
+�@�@��BSR�̃A�b�v�f�[�g�p�ɕK�v�ȕ��������؂�o���܂��B
+�@�@�@�@�@�@�@�@�@�@�@�@�i0x0000 - 0x0FFF, 0x2000-0x47FF�j
+
+=end
+
+
+=begin
+if( ARGV[0] == nil )
+  print( "input file name is nessesary!\nabort.\n" )
+  exit(1)
+end
+
+
+unless(File.exist?( ARGV[0] ))
+  print( "file" << ARGV[0] << " not found.\nabort.\n" )
+  exit(1)
+end
+=end
+
+src = File.open( 'bsr.hex' )
+
+dest = File.new( "hoge.bin","wb" )
+
+
+dest.write( 'jhl' )
+
+### get data ##########################
+src_in = Hash.new 
+tempA = Array.new
+dataTemp = Array.new
+
+offset = Numeric.new
+bindata = Array.new( 32*1024, 0xFF )
+
+while(src.readline)
+  tempA = $_.scan(/(\:)(\w\w)(\w\w\w\w)(\w\w)(\w+)(\w\w)/)
+
+  break if( tempA.size == 0 )
+  
+  src_in = { "len" => tempA[0][1], "offset" => tempA[0][2], "type" => tempA[0][3], "data" => tempA[0][4], "CRC" => tempA[0][5] }
+
+  break if src_in["type"].hex == 01
+  break if src_in["len"].hex == 00
+  #  next if  src_in["type"].hex != 00
+  if( src_in["type"].hex != 00 )
+#    p dat
+    next
+  end
+
+  offset = src_in["offset"].hex
+  next if(( 0x1000 <= offset ) && ( offset < 0x2000 ))
+
+  dataTemp = src_in["data"].scan(/\w\w/)
+
+  ( 0...(src_in["len"].to_s.hex) ).each{|i|
+    bindata[ offset + i ] = ( dataTemp[ i ] ).to_s.hex
+  }
+end
+
+### debug enable bit check #############
+# �f�o�b�O���‚ɂȂ��Ă����IS�f�o�b�K�ŋN�����Ȃ��iMCU�����삵�Ȃ��j
+p bindata[0xC3]
+if( bindata[0xC3] != 0x04 )
+  print( "!E debug enable!!" )
+  exit( 1 )
+end
+
+
+### format data and output #############
+4096.times{
+  bindata.delete_at(4096)
+}
+dest.write( bindata[0..(0x4FFF - 0x1000)].pack("c*") )
+dest.close
+
+printf( "intel-HEX to bsr bin converter\n file converted!\n\n" )
diff --git a/tags/2.03_SDK-3.1/pedo_alg_thre_det2.c b/tags/2.03_SDK-3.1/pedo_alg_thre_det2.c
new file mode 100644
index 0000000..a7a13e2
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pedo_alg_thre_det2.c
@@ -0,0 +1,575 @@
+/* ********************************************************
+ �����v
+ 3�������x�̃��A���^�C���f�[�^����A�x�N�g���̃m�������o���A
+ 臒l�𒴂��鎞�ԁA�Ԋu�A�m�����̑傫����臒l��؂�ւ���Ȃ�
+********************************************************* */
+#ifndef _WIN32
+
+#pragma mul
+#pragma div
+#pragma bcd
+
+#endif
+
+#include "incs.h"
+
+#ifndef _WIN32
+#include <math.h>
+#endif
+
+#include "accero.h"
+#include "pedometer.h"
+
+#include "pool.h"
+
+// ========================================================
+// �����̍ŏI�L�^����
+//  ���̏��Ԃ̓��O�ǂݏo���̏��Ԃł�����̂ł�����Ȃ��ł�
+//  ���ԂɃA�h���X�̎Ⴂ�̂���m�ۂ����̂����҂��Ă܂�...
+typedef struct{
+    u8 hour_bcd;
+    u8 day_bcd;
+	u8 month_bcd;
+	u8 year_bcd;
+	u8 min_bcd;
+	u8 sec_bcd;
+}st_calender;
+
+
+
+// ========================================================
+static u16 get_long_hour();
+static u16 calc_hours_spend( u8 );
+extern void DI_wt_chk();
+
+
+
+// ========================================================
+bit pedolog_overflow;           // 192���ԋL�^�ς݃t���O(i2c�œǂ߂�)
+extern uni_pool pool;           // �������O�͂��̍\���̂̒�
+static u8 p_record;             // ���O�̏������݈ʒu
+static st_calender cal_log_latest; // �Ō�ɕ������X�V��������
+static u16 last_hour_fny;       // fny:from new year
+static st_calender cal_temp;
+static u16 now_longhour;
+
+
+
+
+
+
+// ========================================================
+#define _use_my_sqrt_
+#ifdef _use_my_sqrt_
+static unsigned long my_sqrt( unsigned long );
+#endif
+
+// ���N�͉[�N�H
+#define is_leapyear( y )  (( y & 0x03 ) == 0 )
+// �u���N�v�͉[�N�H
+#define is_firstyear( y ) (( y & 0x03 ) == 1 )
+
+
+// �����x�Z���T�l��FIR-LPF�ɒʂ��B����̌W��
+extern const s8 lpf_coeff[];
+#define TAP 64
+#define FIL_COEFF_QUANT 10
+
+
+
+/*=========================================================
+�@�����v
+ ========================================================*/
+void pedometer()
+{
+    static s16 th_H = 15000; // 臒l�B���I�ύX���܂�
+    static s16 th_L = 11000;
+    static u16 acc_norm[3]; // �����x�̑傫���̃q�X�g���B�������傫�������Â�
+    static u16 acc_norm_temp;
+    static u8 interval_hh = 0xFF;  // �R-�R�Ԃ̎��ԁB�Z�߂�����͂����B
+    static u8 time_l;       // �O��̋ɏ�����̌o�ߎ���
+    static u16 peak_l;      // �J�̐[��
+    static u16 norm_hist[TAP];
+
+    static u8 hist_indx;
+
+    signed long filterd;
+
+    u8 i;
+
+    u16 sx16,sy16,sz16;
+
+	DI_wt_chk();
+	sx16 = abs( (u16)vreg_ctr[VREG_C_ACC_XH] * 256 + vreg_ctr[VREG_C_ACC_XL] );
+    sy16 = abs( (u16)vreg_ctr[VREG_C_ACC_YH] * 256 + vreg_ctr[VREG_C_ACC_YL] );
+    sz16 = abs( (u16)vreg_ctr[VREG_C_ACC_ZH] * 256 + vreg_ctr[VREG_C_ACC_ZL] );
+	EI();
+
+    // �x�N�g���̃m����
+#ifdef _mcu_
+# ifndef _use_my_sqrt_
+    norm_hist[ hist_indx & TAP-1 ] = sqrt( (long)sx16 * ( sx16 / 2 ) +
+                                           (long)sy16 * ( sy16 / 2 ) +
+                                           (long)sz16 * ( sz16 / 2 )
+                                           );
+# else
+    norm_hist[ hist_indx & TAP-1 ] = my_sqrt( (long)sx16 * ( sx16 / 2 ) +
+                                              (long)sy16 * ( sy16 / 2 ) +
+                                              (long)sz16 * ( sz16 / 2 )
+                                              );
+# endif
+#endif
+
+#ifdef _pc_
+    norm_hist[ hist_indx & TAP-1 ] = normh * 256 + norml;
+#endif
+
+    hist_indx ++;
+
+    // �q�X�g���Ƀt�B���^(fir)���|���āA����̒l�����߂� //
+    filterd = 0;
+//    for( i = 8; i != 55; i++ )  // �W�����O�΂���̂���
+    for( i = 0; i != 46; i++ )  // �W���e�[�u����������܂����B�p�����[�^����������
+    {
+        filterd += (signed long)norm_hist[ ( hist_indx + i ) & TAP-1 ] * lpf_coeff[ i ];
+    }
+
+    filterd += (4096)*512;      // DC�����Z...�������Ǝv��
+    acc_norm_temp = (s16)( filterd /1024 & 0xFFFF ); // ��FIL_COEFF_QUANT���琳�K��
+/*
+    if( acc_norm[0] < acc_norm_temp )
+    {
+        t_rise ++;
+        if( t_rise == 0 )
+            t_rise == 254;
+    }
+    else
+    {
+        t_rise = 0;
+    }
+*/
+    if( acc_norm[0] != acc_norm_temp )
+    {
+        acc_norm[2] = acc_norm[1];  // �q�X�g��
+        acc_norm[1] = acc_norm[0];
+        acc_norm[0] = acc_norm_temp;
+    }
+
+    if( acc_norm[2] <= acc_norm[1] && acc_norm[1] > acc_norm[0]
+        && acc_norm[0] > th_H )
+        // �ɑ�ŁA臒l�𒴂��Ă���
+    {
+        if( 21 < interval_hh )
+            // �O��̋ɑ傩��̊Ԋu���قǂ悢
+        {
+            if(( interval_hh < 160 ) && ( time_l < interval_hh ))
+                // �J������ł���
+            {
+                if( acc_norm[0] - peak_l > 4200 ){
+                    // ����������܂���
+                    hosu_increment_if_necessary();
+                }
+            }
+            interval_hh = 0;
+        }
+        // �Ȃ񂿂����臒l�̓��I�ύX
+        if( acc_norm[0] > 18000 )
+        {
+            th_L = acc_norm[0] - 10000;
+        }
+        else
+        {
+            th_L = 11000;
+        }
+    }
+    else
+    {
+		if( interval_hh != 255 )	 // �O�a���Z���Ċy�ɏ������炢���̂�
+		{
+			interval_hh ++;
+		}
+    }
+
+    // (2) ���߂̋ɏ�����̎���
+    if( acc_norm[2] >= acc_norm[1] && acc_norm[1] < acc_norm[0]
+        && acc_norm[0] < th_L )
+    {
+        // �ɏ������o
+        time_l = 0;
+        peak_l = acc_norm[0];
+    }
+    else
+    {
+		if( time_l != 255 )
+		{
+			time_l ++;
+		}
+    }
+}
+
+
+/*=========================================================
+�@�����{�P
+�@�@�ݐς��C���N�������g
+  �@�������X�V
+   *2011/01/20
+	�d�l�ύX�@���O�������ς��ɂȂ����炻���Ŏ~�߂�
+ ========================================================*/
+
+
+#define HOSU_NODATA 0xFFFF
+#define HOSU_MAX    0xFFFE
+
+void hosu_increment_if_necessary()
+{
+    u8 year_compd;               // hour���E�␳�ς݌��ݔN�Bcomp(ensation -ed)
+
+	// ���ݎ����擾
+    DI_wt_chk();
+    RWAIT = 1;
+    while( !RWST ){;}
+
+    cal_temp.hour_bcd  = HOUR;
+    cal_temp.day_bcd   = DAY;
+    cal_temp.month_bcd = MONTH;
+    cal_temp.year_bcd  = YEAR;
+    cal_temp.min_bcd   = MIN;
+    cal_temp.sec_bcd   = SEC;
+    
+    RWAIT = 0;
+    EI();
+    
+    year_compd = bcdtob( cal_temp.year_bcd );
+
+    now_longhour = get_long_hour();
+
+	// �������݃|�C���^�̍X�V
+    if( ! ( vreg_ctr[ VREG_C_ACC_HOSU_L ] == 0 &&  // �����von��A�ŏ��̈���܂ł͑O�񂩂�̌o�ߎ��Ԃ��v�Z���Ȃ�
+            vreg_ctr[ VREG_C_ACC_HOSU_M ] == 0 &&
+            vreg_ctr[ VREG_C_ACC_HOSU_H ] == 0 ))  //. �S�r�b�gOR�Ń[�����肷��̂̓f�W�^����H���̕����݂���
+	{
+		// �����v���~�܂��Ă������Ԃ��l�����ĕK�v�Ȃ�i�߂�
+        // �␳�v�Z�@���U�뎞��ō�������ɂȂ����ꍇ�A��A����23����ɏ㏑��
+        if( now_longhour == (u16)-1 ) // ��N��A����23���䈵���̂Ƃ��A�v�Z���ʂ� -1 �ɂȂ��Ă�
+        {
+            now_longhour = 365 * 24 -1;
+			if( is_firstyear(year_compd) )
+			{
+				now_longhour += 24;
+			}
+            year_compd --;
+        }
+        fill_hosu_hist_hours( calc_hours_spend( year_compd ) );  // ���������݃|�C���^�̍X�V���s��
+
+		// ���O���ӂ�ŋL�^��~�H
+		if( pedolog_overflow )
+		{
+			return;
+            // �����܂��B���O�̍X�V���Ȃ��B
+		}
+	}
+
+	// �C���N�������g���ėǂ�
+    cal_log_latest = cal_temp;  // �����O�����X�V
+    last_hour_fny  = now_longhour;
+
+	// �������O�@�C���N�������g
+	if( pool.vreg_c_ext.pedo_log[ p_record ] == HOSU_MAX )
+	{
+		// �������Ȃ��ł����܂�
+		//. ���v�̍��v�Ɨ݌v������Ȃ��Ȃ�̂�����邽�߂��낤���ǁA�ǂ��Ȃ́H
+		return;
+	}
+	else if( pool.vreg_c_ext.pedo_log[ p_record ] == HOSU_NODATA )   // ���̎��ԑэŏ��̃J�E���g�̎�
+    {															//  ���ꂵ�Ȃ���1������Ȃ�
+        pool.vreg_c_ext.pedo_log[ p_record ] = 1;
+    }
+    else 
+	{
+		// �ʏ�p�X
+        pool.vreg_c_ext.pedo_log[ p_record ] ++;
+	}
+
+	// �ݐς̍X�V //
+	DI_wt_chk();
+	if( ++vreg_ctr[ VREG_C_ACC_HOSU_L ] == 0 )		// �J���X�g�`�F�b�N
+	{
+		if( ++vreg_ctr[ VREG_C_ACC_HOSU_M ] == 0 )
+		{
+			if( ++vreg_ctr[ VREG_C_ACC_HOSU_H ] == 0 ){
+				vreg_ctr[ VREG_C_ACC_HOSU_L ] = 255; //. ���낢�뎸�s��������...
+				vreg_ctr[ VREG_C_ACC_HOSU_M ] = 255;
+				vreg_ctr[ VREG_C_ACC_HOSU_H ] = 255;
+			}
+		}
+    }
+	EI();
+}
+
+
+
+/* ========================================================
+�󔒂̎��Ԃ�K�؂�0�ɂ��āA
+�����܂ނP���Ԃ̃f�[�^�������ʒu�Ƀ|�C���^�H��i�߂�
+======================================================== */
+static void fill_hosu_hist_hours( u16 hours )
+{
+	// ���O���ӂ�H
+	if( (u16)p_record + hours >= PEDOMETER_LOG_SIZE ) 
+	{
+		pedolog_overflow = true;
+		return;
+	}
+
+	// �󔒂̐����Ԃ̐ݒ�
+    while( hours != 0 )
+    {
+		// �V�d�l�@�����ς��Œ�~
+	    p_record ++;
+#if 1	// debug
+		if( p_record >= PEDOMETER_LOG_SIZE )
+        {
+			pedolog_overflow = true;
+//			dbg_nop();  // �����ɗ���悤���ƃo�O
+			break;
+        }
+		else
+#endif
+		{
+	        pool.vreg_c_ext.pedo_log[ p_record ] = 0;
+		}
+        hours --;
+    }
+
+	return;
+}
+
+
+
+/* ========================================================
+�󔒂̎��Ԃ�K�؂�0�ɂ��āA
+�����܂ނP���Ԃ̃f�[�^�������ʒu�Ƀ|�C���^�H��i�߂�
+======================================================== */
+void clear_hosu_hist()
+{
+    u8 hours = PEDOMETER_LOG_SIZE;
+    do
+    {
+        hours --;
+        pool.vreg_c_ext.pedo_log[ hours ] = 0xFFFF;
+    }
+    while( hours != 0 );
+
+	DI_wt_chk();
+	vreg_ctr[ VREG_C_ACC_HOSU_L ] = 0;
+    vreg_ctr[ VREG_C_ACC_HOSU_M ] = 0;
+    vreg_ctr[ VREG_C_ACC_HOSU_H ] = 0;
+    p_record = 0;
+	pedolog_overflow = false;
+	EI();
+}
+
+
+extern u8 iic_burst_state;
+bit pedolog_read_msb;
+/* ========================================================
+  �����v�q�X�g���ǂݏo���̌㏈��(������)
+  �ǂݏo���|�C���^�̃N���A
+======================================================== */
+/*	�}�N���ɂ��܂���
+void hosu_read_end(  )
+{
+    pedolog_read_msb = 0;
+}
+*/
+
+
+
+/* ========================================================
+  �����v�̃q�X�g����Ԃ��B
+  �P��Ăԓx�ɁA�q�X�g���̉��ʁA��ʁA�ꎞ�ԑk���ĉ��ʏ��...
+======================================================== */
+u8 hosu_read(  )
+{
+    u8 rv;
+    static u8 p_record_buffer;
+    static st_calender cal_buff;	// �ꉞ�A�A�g�~�b�N������
+
+    if( iic_burst_state == 0 )
+    {
+		p_record_buffer = p_record;
+		DI_wt_chk();
+		cal_buff = cal_log_latest;
+		EI();
+    }
+
+    if( iic_burst_state <= 5 )
+    {
+        rv = *( (u8*)&cal_buff + iic_burst_state );  // ��������
+        iic_burst_state ++;
+        return( rv );
+    }
+    else
+    {
+        u16 temp;
+        // 16�r�b�g�ŋL�^���Ă���̂ł΂炵�đ��� /// �����Ɗy������@������񂶂�
+        temp = pool.vreg_c_ext.pedo_log[ p_record_buffer ];
+        if( !pedolog_read_msb  )
+        {
+            rv = (u8)( temp & 0x00FF );
+        }
+        else
+        {
+            rv = (u8)(( temp >> 8 ) & 0x00FF );
+            if( p_record_buffer == 0 )
+            {
+                p_record_buffer = PEDOMETER_LOG_SIZE-1;
+            }
+            else
+            {
+                p_record_buffer --;
+            }
+        }
+        pedolog_read_msb ^= 1;
+        return( rv );
+    }
+
+}
+
+
+
+/* ========================================================
+  ���N�̌��U����̌o�ߎ���(hour)��Ԃ��B
+  ����  ����
+  �Ԓl  u16 long_hour
+======================================================== */
+const u16 DAYS_FROM_HNY[] = {
+    0,
+    31,
+    31+28,  // =59�B�@�c�R���O���͂P���T�X��
+    31+28+31,
+    31+28+31+30,
+    31+28+31+30+31,
+    31+28+31+30+31+30,
+    31+28+31+30+31+30+31,
+    31+28+31+30+31+30+31+31,
+    31+28+31+30+31+30+31+31+30,
+    31+28+31+30+31+30+31+31+30+31,
+    31+28+31+30+31+30+31+31+30+31+30
+    };
+
+static u16 get_long_hour()
+{
+    u8 year    = bcdtob( cal_temp.year_bcd );
+    u8 month   = bcdtob( cal_temp.month_bcd );
+    u8 day     = bcdtob( cal_temp.day_bcd );
+    u8 hour    = bcdtob( cal_temp.hour_bcd );
+    u8 min_bcd = cal_temp.min_bcd; // �召��r�������Ȃ��̂�bcd�̂܂܂ł悢
+    u8 sec_bcd = cal_temp.sec_bcd;
+    u16 long_hour;
+
+    // �܂������̕���
+    long_hour = DAYS_FROM_HNY[ month -1 ]; // -1�̓C���f�b�N�X���킹
+    if( is_leapyear(year) && ( 3 <= month ))
+    {
+        // �[�N�ŁA�[������
+        long_hour ++;
+    }
+    long_hour += day - 1;
+    long_hour *= 24; // ����������
+
+    long_hour += hour;
+
+    // ���E�����E�̑O�H��H
+    if( ( min_bcd > vreg_ctr[ VREG_C_ACC_HOSU_HOUR_BOUNDARY ] )
+        || ( ( min_bcd >= vreg_ctr[ VREG_C_ACC_HOSU_HOUR_BOUNDARY ] )
+                && ( sec_bcd >= vreg_ctr[ VREG_C_ACC_HOSU_HOUR_BOUNDARY_SEC ] ))
+        )
+    {
+        return( long_hour );
+    }
+    else
+    {
+        return( long_hour -1 );  // 1���ԑO�Ɋ܂߂� ���ӁF���U�ō�N�����ɂ���Ƃ��B-1 �ɂȂ�
+    }
+}
+
+
+
+/* ========================================================
+�@�y�ʕ������B
+�@�K�v�\���Ȑ��x�őł��؂�
+   pc��ŃV�~�����[�V�������đ��v����
+======================================================== */
+static unsigned long my_sqrt(unsigned long x)
+{
+    unsigned long s, t;
+
+    if (x <= 0) return 0;
+
+    s = 1;
+    t = x;
+    while (s < t)
+    {
+        s <<= 1;
+        t >>= 1;
+    }
+    do
+    {
+        t = s;
+        s = (x / s + s) >> 1;
+    } while (s < t);
+
+  return t;
+}
+
+
+
+
+/* ========================================================
+�@��‚� �O��Ă΂ꂽ�����ƁA���ݎ����̍��������߂�B�Ԃ�̂�fill_hosu_hist_hours �ɂ��̂܂ܓn����
+ //. ������year_bcd �Ȃ̂�������Ƃ��₾����...
+======================================================== */
+static u16 calc_hours_spend( u8 year )
+{
+	u8 cal_log_latest_year = bcdtob( cal_log_latest.year_bcd );
+
+	// �����N�̓�
+    if( cal_log_latest_year == year )
+    {
+        if( now_longhour > last_hour_fny )
+        {
+            return( now_longhour - last_hour_fny );
+        }
+		else if( now_longhour == 0 && last_hour_fny != 0 )
+		{
+			// �N�������΂���ŁA���E���z�������ځB������Ȃ��ƍ�N�Ō�ɉ��Z���Ă��܂��B
+			return( 1 );
+		}
+		else
+		{
+			return( 0 );  // �������ԑ�(�ƁA�����߂�B�@�ǂ��Ȃ��Ă��m��Ȃ�)
+		}
+    }
+    else if( cal_log_latest_year == ( year -1 ) )
+    {
+        // �N���܂����ł���Ƃ�
+		u16 temp = 365 * 24 - last_hour_fny + now_longhour;
+		if( is_firstyear(year) )
+		{
+			temp += 24;
+		}
+		return( temp );
+    }
+    else if( cal_log_latest_year < year )
+    {
+        // ���N���u
+        return( PEDOMETER_LOG_SIZE +1 );
+    }
+    else
+    {
+        // �J�����_�[�������߂�Ȃ�
+        // �m�[�P�A�ł悢�c���A�s��l�Ƃ����킯�ɂ������Ȃ�
+        return( 0 );
+    }
+}
diff --git a/tags/2.03_SDK-3.1/pedo_lpf_coeff.c b/tags/2.03_SDK-3.1/pedo_lpf_coeff.c
new file mode 100644
index 0000000..2e16755
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pedo_lpf_coeff.c
@@ -0,0 +1,83 @@
+
+#include "incs.h"
+
+// =========================================================
+#define TAP 64
+#define FIL_COEFF_QUANT 10
+const s8 lpf_coeff[]={
+/*
+Window Function Algorithm LPF
+Sampling Frequency =     100.0
+cutoff1 =   6.0000000
+Tap Count =64
+Kaiser Constant =  7.000000
+Quantized by 11 [bits]
+ */
+/*         0,// [0]
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+*/
+         1,// 8
+         2,
+         2,
+         3,
+         3,
+         2,
+         0,
+        -2,
+        -5,// 16
+        -9,
+       -13,
+       -16,
+       -16,
+       -13,
+        -6,
+         4,
+        18,// 24
+        37,
+        56,
+        77,
+        95,
+       110,
+       119,
+       122,
+       119,// 32
+       110,
+        95,
+        77,
+        56,
+        37,
+        18,
+         4,
+        -6,// 40
+       -13,
+       -16,
+       -16,
+       -13,
+        -9,
+        -5,
+        -2,
+         0,// 48
+         2,
+         3,
+         3,
+         2,
+         2,
+         1,
+/*
+         0,
+         0,// 56
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+         0
+*/
+};
diff --git a/tags/2.03_SDK-3.1/pedo_lpf_coeff.h b/tags/2.03_SDK-3.1/pedo_lpf_coeff.h
new file mode 100644
index 0000000..f81d6c2
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pedo_lpf_coeff.h
@@ -0,0 +1,84 @@
+#ifndef _pedo_coeff_h_
+#define _pedo_coeff_h_
+
+// =========================================================
+#define TAP 64
+#define FIL_COEFF_QUANT 10
+const s8 lpf_coeff[]={
+/*
+Window Function Algorithm LPF
+Sampling Frequency =     100.0
+cutoff1 =   6.0000000
+Tap Count =64
+Kaiser Constant =  7.000000
+Quantized by 11 [bits]
+ */
+/*         0,// [0]
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+*/
+         1,// 8
+         2,
+         2,
+         3,
+         3,
+         2,
+         0,
+        -2,
+        -5,// 16
+        -9,
+       -13,
+       -16,
+       -16,
+       -13,
+        -6,
+         4,
+        18,// 24
+        37,
+        56,
+        77,
+        95,
+       110,
+       119,
+       122,
+       119,// 32
+       110,
+        95,
+        77,
+        56,
+        37,
+        18,
+         4,
+        -6,// 40
+       -13,
+       -16,
+       -16,
+       -13,
+        -9,
+        -5,
+        -2,
+         0,// 48
+         2,
+         3,
+         3,
+         2,
+         2,
+         1,
+/*
+         0,
+         0,// 56
+         0,
+         0,
+         0,
+         0,
+         0,
+         0,
+         0
+*/
+};
+#endif
diff --git a/tags/2.03_SDK-3.1/pedometer.h b/tags/2.03_SDK-3.1/pedometer.h
new file mode 100644
index 0000000..8760308
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pedometer.h
@@ -0,0 +1,36 @@
+#ifndef _pedo_
+#define _pedo_
+
+#ifdef WIN32
+typedef unsigned char bit;
+typedef unsigned char u8;
+typedef unsigned short u16;
+
+
+#endif
+
+
+// =========================================================
+extern bit pedolog_read_msb;
+
+
+
+// =========================================================
+//void hosu_read_end(  );	�}�N����
+#define hosu_read_end()		pedolog_read_msb = 0
+
+u8   hosu_read(  );
+void hosu_increment_if_necessary();
+void fill_hosu_hist_hours( u16 );
+void clear_hosu_hist();
+void pedometer();
+
+
+
+// =========================================================
+#define PEDOMETER_LOG_SIZE ( 24 * 7 )
+
+
+
+// =========================================================
+#endif
diff --git a/tags/2.03_SDK-3.1/pm.c b/tags/2.03_SDK-3.1/pm.c
new file mode 100644
index 0000000..4acc09a
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pm.c
@@ -0,0 +1,1390 @@
+/* ========================================================
+  ��PMIC
+    ���c���J�Z
+    nintendo
+    '08 Dec
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma nop
+
+#endif
+
+#include "incs.h"
+#include "adc.h"
+#include "led.h"
+#include "pm.h"
+#include "renge\renge.h"
+
+#include "batt_params.h"
+
+#include <fsl.h>
+#include "fsl_user.h"
+
+
+
+// ========================================================
+u8			raw_adc_temperature;
+BT_VENDER	battery_manufacturer = BT_VENDER_NOT_CHECKED;
+static u8	ntr_pm_reg_shadow;                 // NTR PMIC ���W�X�^�~���[
+bit			bt_authorized;               // �o�b�e���p�����[�^���M�ρB�[�d�J�n����
+u8			chg_led_override;           // �A�_�v�^�������Ƃ��A�[�d���邵�Ȃ��Ɋւ�炸���΂炭�_��������
+
+static u16	bt_volt16;
+
+static bit	ntr_pm_bt_low_old;
+
+bit			BT_IN_CHG_delayed_n; 
+bit			temp_zone_charge_disable;    // ���x�ŏ[�d��~���鎞�Ƀq�X�e���V�X��t���邽��
+
+u8			pmic_version;
+u8			mgic_version[2];
+
+u8			pm_reg_bit_vddlcd;
+
+static bt_param_*	p_bt_param;
+extern const	bt_param_ bt_param[];
+
+bit			pm_extdc_old;				// �O��A�_�v�^�`�F�b�N�����Ƃ��h�����Ă������H
+
+
+
+// ========================================================
+static void BT_model_detect();
+static void BT_mgic_quick_start();
+static void BT_mgic_init();
+static void bt_chk_temparature();
+static void bt_get_charge_status();
+static void bt_param_select();
+static void bt_batt_update_twl();
+static void bt_batt_update_ntr();
+static void update_chg_led();
+
+
+// ���b�p�[
+static err send_cmd_mgic_2B( u8 reg, u16 dat );
+static err read_mgic_2B( u8 reg, u8* dat );
+static err read_BT_SOC( u8* dest );
+static err read_BT_voltage( u8* dest );
+static u8 conv_ctr_bt_to_twl_bt();
+
+
+
+// ========================================================
+#define swap_endian_16( x ) (unsigned int)(( x << 8 ) | ( x >> 8 ))
+
+
+
+// ========================================================
+const u8 BT_MANUF_BORDER[] = {
+    5, 33, 79, 123, 158, 197, 233
+    };
+
+
+
+/* ========================================================
+  �d�r�̊Ǘ�
+
+  �ȉ��̃s���͎�ɂ����ő���E�Ď�����܂��B
+  �EPM_BT_AUTH		����AGPI                  in
+  �EPM_CHARGE_n		CCIC /CHG                  in
+  �EPM_CHARGE_ERR_n      /FLT                  in
+  �EPM_EXTDC_n           /DOK          INTP4   in
+  �EPM_CHARGE_EN_n	     /CEN                  out
+
+  �ȉ��̕��͊֌W���肻���ł����ʂ̂Ƃ���Ŏ�ɊĎ�����Ă��܂��B
+  �ELED_Pow R, B, Charge	tsk_LED
+  �EBT_TEMP,_P				tsk_ADC
+
+  PM_EXTDC�͊��荞�݃��C���ɂ��邩��
+ ======================================================== */
+#define INTERVAL_TSK_BATT  60
+// ��100���Ə[�d�G���[���ɂ��܂��_�ł��Ȃ��̂�
+
+void tsk_batt(  )
+{
+    static u8 task_interval;
+
+    if( task_interval -- != 0 )
+    {
+        return;
+    }
+    else
+    {
+        task_interval = (u8)( INTERVAL_TSK_BATT / SYS_INTERVAL_TICK );
+    }
+
+    // �A�_�v�^�X�e�[�^�X�X�V //
+    pm_chk_adapter();
+
+    // �[�d //
+    bt_chk_temparature();       // ���x�`�F�b�N
+    if( !temp_zone_charge_disable && bt_authorized && !PM_EXTDC_n )
+    {
+        BT_CHG_ENABLE(); // ���x�͈�OK�ŏ[�d�ĊJ
+    }
+    else
+    {
+        BT_CHG_DISABLE(); // ���x�댯�I�@�[�d��~
+    }
+
+    bt_get_charge_status();		// �[�d�󋵃`�F�b�N
+	update_chg_led();			// chg led�X�V
+
+    // �d�r�c�� //
+    BT_get_left();
+}
+
+
+/* *******************************************************
+	�[�dLED�X�V
+	CCIC���[�d���Ƃ����Γ_������B
+	�łȂ��Ă��A�A�_�v�^�h�����΂���Ȃ�5�b�_������
+	�w�^���d�r�Ή��ʼnR�[�d���̎��A�q���[�Y�؂�iMGIC��NAK�j�Ȃ����
+ ******************************************************* */
+static void update_chg_led()
+{
+	static bit temp_led_chg;
+	
+	temp_led_chg = false;
+
+	// �A�_�v�^�‚Ȃ����u�ԁA���[�d�ł����b�킴�Ɠ_��������B���d���Ă邱�Ƃ��킩�点�邽�߁B
+	if( chg_led_override != 0 )
+	{
+		chg_led_override --;
+		temp_led_chg = true;
+	}
+
+	// CCIC ���[�d���Ƃ����̂ł���΁A���ꂪ��ԋ���		
+	if( ! BT_IN_CHG_delayed_n )         // bt_get_charge_status()�ōX�V����܂��B
+	{
+		temp_led_chg = true;
+	}
+
+	LED_CHARGE = temp_led_chg;
+
+	// ���W�X�^�̏[�d���r�b�g��LED�ɓ�������
+	set_bit( LED_CHARGE, vreg_ctr[VREG_C_STATUS], REG_BIT_BATT_CHARGE );  // set_bit�̂݁B
+}
+
+
+
+#define RAW_TEMP_LH    75	// 50 [degC]
+#define RAW_TEMP_LL    61	// 55
+#define RAW_TEMP_HL    184  //  1
+#define RAW_TEMP_HH    189  // -1
+#define AVG_COUNT      40
+
+/* *******************************************************
+ ���x�`�F�b�N
+  ���x�t���q�X�e���V�X
+ ******************************************************* */
+void bt_chk_temparature()
+{
+    static u8 heikinka_h,heikinka_l;
+
+    if(( RAW_TEMP_LH <= raw_adc_temperature )
+       && ( raw_adc_temperature <= RAW_TEMP_HL ))
+    {
+        if( heikinka_h < AVG_COUNT )
+        {
+            heikinka_h++;
+        }
+        else
+        {
+            temp_zone_charge_disable = false;         // �[�d����
+        }
+    }
+    else if(( raw_adc_temperature <= RAW_TEMP_LL )
+       || ( RAW_TEMP_HH <= raw_adc_temperature ))
+    {
+        if( heikinka_l < AVG_COUNT )
+        {
+            heikinka_l++;
+        }
+        else
+        {
+            temp_zone_charge_disable = true;         // �[�d�֎~
+        }
+    }
+    else
+    {
+        // temp_zone_charge_disable ���̂܂�
+        heikinka_h = 0;
+        heikinka_l = 0;
+    }
+}
+
+
+
+void bt_get_charge_status()
+{
+    // CCIC�̕s�����̂��߁A/CHG�̃l�Q�[�g��������ƒ��J�ɒx��������
+    static u8 anti_chatter;
+
+    if( !BT_IN_CHG_n )
+    {
+        // ����Ƀ`���^�����O����
+        if( anti_chatter < 2 )  // �d�r�����ŃA�_�v�^�����āA�d�ɂ����킳��
+        {                       //  ����Ə[�dLED��������������̂�
+            anti_chatter++;
+        }
+        else
+        {
+            BT_IN_CHG_delayed_n = 0;  // �[�d��
+        }
+    }
+    else
+    {
+        if( !BT_CHG_Ena_n 
+			&& ( vreg_ctr[ VREG_C_BT_REMAIN ] < 60 )
+			&& !( vreg_ctr[ VREG_C_STATUS_1 ] & REG_BIT_MGIC_ERR )
+			)
+        {
+            BT_IN_CHG_delayed_n = 0;  // �[�d���ƈ����B�[�d���I����Ă���͂����Ȃ�
+        }
+        else
+        {
+            BT_IN_CHG_delayed_n = 1;
+            anti_chatter = 0;
+        }
+    }
+}
+
+
+
+/********************************************************
+�A�_�v�^�̗L���`�F�b�N
+ �d��off���̃A�_�v�^���������ŊO����Ă΂�邽�ߕ���
+ ***********************************************************/
+void pm_chk_adapter()
+{
+    set_bit( !PM_EXTDC_n, vreg_ctr[VREG_C_STATUS], REG_BIT_POW_SUPPLY );
+
+    if( pm_extdc_old != PM_EXTDC_n )								// HAL ��ʂ����߁A PM_EXTDC_n �� volatile �ɂ���S�z�Ȃ�
+    {
+        pm_extdc_old = PM_EXTDC_n;
+        if( !PM_EXTDC_n )
+        {
+            // �h������
+            set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_CONNECT );
+            chg_led_override = (u8)( 2500 / INTERVAL_TSK_BATT );	// bt_chck��wait_ms(5)�̐��ŐL�΂����Btoriaezu�蓮������ 4.5 sec
+        }
+        else
+        {
+            u8 temp_v[2];
+
+            // ������
+            set_irq( VREG_C_IRQ1, REG_BIT_BT_DC_DISC );
+            chg_led_override = 0;
+
+            // �d�r�c�ʂ�1%��ŁA�A�_�v�^�L��̎��ɂ͖{�̂��N�����A�Q�[����������
+            //  1%��ɉ񕜂���O�ɃA�_�v�^���������Ƃ��A���荞�݂����Ȃ��Ɗ��Ғʂ��
+            //  ����łȂ��B���ʑΉ��̂��߂�����
+            if( read_mgic_2B( BT_GAUGE_REG_VCELL, temp_v ) == ERR_SUCCESS )
+            {
+                bt_volt16 = ( temp_v[0] * 256 + temp_v[1] );
+            }
+
+            if(( bt_volt16 < V_TH_ZERO ) || ( vreg_ctr[ VREG_C_BT_REMAIN ] == 0 ))
+            {
+                set_irq( VREG_C_IRQ1, REG_BIT_BT_REMAIN );
+            }
+        }
+    }
+}
+
+
+
+/********************************************************
+�d�r�֌W�̏�����
+
+�@�@�@�Q�[�W�@�@�b�@�L��@�@�@�@�@�b�@����
+�@�@�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[
+�@�@�@�d�r�@�L��b�@���@�@�@�@�@�@�b�@�H
+�@�@�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[
+�@�@�@�@�@�@�����b�@�����@�@�@�@�@�b�@�s�r
+�@�@�@�@�@�@�@�@�b�@���@�d�r�����@�b
+�@�@�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[�[
+
+�@�@�Q�[�W�L��A�d�r�����@�̔����^���@���ʂ́A
+�@�d�r���x�Ŕ��肷��
+
+ �Ԓl�F�@�d�r����               0xFF
+         �d�r�ς���ĂȂ�       0
+         �d�r���           1
+
+***********************************************************/
+bit bt_force_update;
+
+void BT_chk()
+{
+    BT_VENDER battery_manufacturer_old;
+
+    battery_manufacturer_old = battery_manufacturer;
+
+    BT_model_detect();
+	bt_param_select();  // �o�b�e���c�ʕ␳�p�����[�^�ȂǃZ�b�g ����@�ł��A�Ƃ肠�����̒l(�p�i)�w��ɂ��Ă����B
+						//  ���ʂ�rcomp�v�Z�����邪�A���������|�C���^���Q�Ƃ���̂��₾���A����@�Ȃ�v�Z���Ȃ��Ƃ��ʓ|
+
+    if( system_status.model != MODEL_JIKKI )
+    {
+        bt_authorized = false;
+        return;
+        // �����܂�
+    }
+
+    if(( battery_manufacturer_old != battery_manufacturer ) ||
+           bt_force_update )
+    {
+        bt_force_update = false;
+        iic_mcu_start(  ); // ���ŏ������t���O�������Ă�̂ŌĂт܂����ėǂ��@����ȂƂ���Ɂcorz
+        if( (( battery_manufacturer_old == BT_VENDER_OPEN ) ||
+             ( battery_manufacturer_old == BT_VENDER_NOT_CHECKED )) &&
+              !system_status.reboot )
+        {
+            BT_mgic_quick_start();
+        }
+        BT_mgic_init();          // �@�픻����s���܂�
+    }
+    bt_authorized = true;
+    renge_task_immed_add( tski_BT_temp_update ); // �d�r���x��
+}
+
+
+
+
+void BT_model_detect()
+{
+    u8 temp;
+
+    BT_DET_P = 1;
+    BT_TEMP_P = 1;
+    wait_ms( 3 );                 // �d�����オ��̂Ɏ��Ԃ��|����
+
+    raw_adc_temperature = get_adc( ADC_SEL_BATT_TEMP );
+    temp = get_adc( ADC_SEL_BATT_DET );
+    BT_DET_P = 0;
+
+    system_status.captureBox = 0;
+    // �v���b�g�t�H�[������ //
+    if( raw_adc_temperature > 0xF0 )
+    {
+        // TS //
+        system_status.model = MODEL_TS_BOARD;
+    }
+    else if( raw_adc_temperature < 4 )
+    {
+        // ���� //
+        system_status.model = MODEL_SHIROBAKO;
+
+        // ���������āF�L���v�`���{�[�h //
+        if(( iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_VERSION ) == 0x01 ) &&
+            ( iic_mcu_result == I2C_ERR_OK ))
+        {
+            system_status.captureBox = 1;
+        }
+    }
+    else
+    {
+        // ���@�A�c��IC NACK( �o�b�e�������܂��͎c��IC�̏� )
+        system_status.model = MODEL_JIKKI;  // �o�b�e�������̎��́��ŏ㏑������
+    }
+
+	// TS��home�{�^���A���@�͖��ڑ��Ȃ̂ŗv�[�q���� /// gnd�ɂ��Ƃ��΂悩�����c
+	if( system_status.model == MODEL_TS_BOARD )
+	{
+		PM_SW_HOME_n_TSBOARD = 1;
+	}
+	else
+	{
+		PM_SW_HOME_n_TSBOARD = 0;
+		SW_HOME_n_TSBOARD_RAW = 0;				/// ���@open �ǂ����ł������񂾂���
+	}
+
+    // �d�r���[�J�[�̎��� //
+    {
+        u8 i;
+
+        battery_manufacturer = BT_VENDER_OPEN;  // �f�t�H���g�l
+        for(i=0; i<=7; i++)
+        {
+            if( temp <= BT_MANUF_BORDER[ i ] )
+            {
+                battery_manufacturer = (BT_VENDER)i;
+                break;
+                /*
+                   BT_VENDER_MAXELL;  // = 0
+                   BT_VENDER_1;
+                   BT_VENDER_2;
+                   BT_VENDER_3;
+                   BT_VENDER_4;
+                   BT_VENDER_PANA;
+                   BT_VENDER_6;
+
+                   BT_VENDER_OPEN;
+                 */
+            }
+        }
+    }
+
+
+    if( ( battery_manufacturer == BT_VENDER_OPEN ) &&
+        ( system_status.model == MODEL_JIKKI ) )
+    {
+        system_status.model = MODEL_JIKKI_NOBATT;
+    }
+}
+
+
+
+static void BT_mgic_quick_start()
+{
+    wait_ms( 10 );  // MGIC�̋N���Ɋ|����
+
+    // 0. �o�b�e���c��IC �N�C�b�N�X�^�[�g
+    send_cmd_mgic_2B( BT_GAUGE_REG_MODE, swap_endian_16( 0x4000 ) );
+
+    wait_ms( 150 );
+}
+
+
+#define MGIC_CMD_UNLOCK_KEY      0x4A57
+#define MGIC_CMD_RESET           0x5400
+static void BT_mgic_init()
+{
+    u8      origParam[4];
+
+    /*
+    // -1. ���Z�b�g�������Ă݂�
+    �������Ⴞ��!
+    i2c_send_buff_2B._u16 = swap_endian_16( MGIC_CMD_RESET );
+    send_cmd_mgic_2B( BT_GAUGE_REG_COMMAND );  // �����‚�NACK��Ԃ�
+    */
+
+    if( system_status.model != MODEL_JIKKI )
+    {
+        return;
+        // �����܂�
+    }
+
+    // 1. ���b�N����
+    if( send_cmd_mgic_2B( BT_GAUGE_REG_LOCK, swap_endian_16( MGIC_CMD_UNLOCK_KEY ) ) != ERR_SUCCESS )
+    {
+        // �c��IC NACK
+        vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_MGIC_ERR;
+        return;
+        // �����܂�
+    }
+
+    vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_MGIC_ERR;
+
+    //        wait_ms( 5 + 1 ); �O�ɃE�F�C�g����Ă�̂ŕs�v
+
+    // 2. �����p�����[�^���ꎞ�ۑ�
+    iic_mcu_read( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, origParam );
+
+    // 3. �ꎞ�I��OCV��ύX
+    send_cmd_mgic_2B( BT_GAUGE_REG_OCV, swap_endian_16( p_bt_param->ocv )); // �}�W�b�N�i���o�[�I�Ȃ��́B���[�J�[�w��
+
+    // 4. �ꎞ�I��RCOMP��ύX
+    send_cmd_mgic_2B( BT_GAUGE_REG_RCOMP, swap_endian_16( 0xFF00 ) );
+
+    // 5.���[�J�[�ʃp�����[�^�̃��[�h
+    {
+        u8 loop;
+
+        // 16�o�C�g���Ƃɋ�؂�Ƃ̂��Ɓ@�i�m�C�Y�΍�Ƃ������񂾂��ǁA�Ӗ�����񂩁H�j
+        for( loop = 0; loop < 4; loop ++ )
+        {
+            iic_mcu_set_wo_dma(  );
+            iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_BT_PARAM + loop*16, 16, p_bt_param->mg_param + loop*16 );
+        }
+    }
+
+    // 6. 150ms�ȏ�҂�
+    wait_ms( 150 + 15 );
+
+    // 7. OCV�Ɂu�Ƃ���l�v������
+    send_cmd_mgic_2B( BT_GAUGE_REG_OCV, swap_endian_16( p_bt_param->ocv ) ); // �}�W�b�N�i���o�[�I�Ȃ��́B���[�J�[�w��
+
+    // 8. 150�`600ms�҂B600ms�͌���
+    wait_ms( 150 + 15 );
+
+    // 9. SOC��ǂށB�x���t�@�C�̂��߁B
+    { u8 temp;
+	    temp = iic_mcu_read_a_byte( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_SOC );
+
+    	if(( p_bt_param->verify.low <= temp ) && ( temp <= p_bt_param->verify.hi ))
+	    {
+    	    // �J�X�^�����f����������OK�I
+	    }else{
+    	    // ���s�������烊�g���C����̂��H
+	//        dbg_nop();
+    	}
+    }
+
+    // 10.����RCOMP��OCV�������߂�
+    iic_mcu_write( IIC_SLA_BT_GAUGE, BT_GAUGE_REG_RCOMP, 4, origParam );
+
+    // 11. ���b�N
+    send_cmd_mgic_2B( BT_GAUGE_REG_LOCK, swap_endian_16( 0x0000 ) ); // lock key
+}
+
+
+
+extern u16 _dbg_rcomp;
+/* ========================================================
+  raw_adc_temperature�ɓ����Ă���l�����ɕϊ�����ƂƂ��ɁA
+  �E���W�X�^�ɃZ�b�g
+  �E�c��IC�ɃZ�b�g
+ ======================================================== */
+task_status_immed tski_BT_temp_update(  )
+{
+    static u8 rawdat_old;
+    static s8 temperature;
+    s16       newrcomp;
+    static u8 heikinka;
+
+/*
+	�T�[�~�X�^ - 10k�������_�̎��A
+	��p���x�ł͕�����̃J�[�u���قڃ��j�A�ŁA
+	���c T[��] = 81.48  - 111.97 x ratio
+	TDK  T     = 81.406 - 111.81 x ratio
+*/
+
+    if( rawdat_old != raw_adc_temperature )
+    {
+        if( heikinka < 40 )
+        {
+            heikinka ++;
+        }
+        else
+        {
+            heikinka = 0;
+            rawdat_old = raw_adc_temperature;
+            //        temperature = 81.45 - 111.9 * raw_adc_temperature/256.0;
+            // ���ꂼ��256�{���Ă���
+            temperature = (u8)(( 20851 - 112 * raw_adc_temperature + (256/2) ) /256);
+            vreg_ctr[VREG_C_BT_TEMP] = temperature;
+
+            newrcomp = 0;
+            if( temperature > 20 )
+            {
+                newrcomp = ( ( temperature - 20 ) * p_bt_param->rcomp.up )/256;
+            }
+            else
+            {
+                newrcomp = ( ( temperature - 20 ) * p_bt_param->rcomp.down )/256;
+            }
+            newrcomp = p_bt_param->rcomp.rcomp + newrcomp;
+
+            if( newrcomp > 255 )
+            {
+                newrcomp = 255;
+            }
+            if( newrcomp < 0 )
+            {
+                newrcomp = 0;
+            }
+            _dbg_rcomp = newrcomp;
+
+            if( send_cmd_mgic_2B( BT_GAUGE_REG_RCOMP, newrcomp ) == ERR_SUCCESS )  // swap�s�v
+            {
+                rawdat_old = raw_adc_temperature;
+            }
+            else
+            {
+                vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_MGIC_ERR;
+            }
+        }
+    }
+    return ( ERR_FINISED );
+}
+
+
+
+/**********************************************************
+ �d�r�c��IC����c�ʂ��擾���A���W�X�^�ɏ������ށB
+ �@�d�r�c��IC�������E�̏�Ȃǂ̎��͂Ƃ肠�����c��99%�Ƃ���B
+ �@�@�@�@�@�@�@�@���� status_1�Ŋm�F�”\�B�d���������Ƀ`�F�b�N���Ă��܂��B
+ �@BT_chk()�����s����Ă���K�v������܂��B
+**********************************************************/
+void BT_get_left(){
+    u8 temp[2];
+    u8 reg_volatile_temp_bt_remain,reg_volatile_temp_bt_remain_fine;  // I2C�̔񓯊��ǂݍ��݂ł̂���‚��h�~ �L���b�v�����̏���
+    u8 fuel_cap_by_voltage;	// �d���ŃL���b�v�Ɏg��
+
+    // �d�r�c��
+    if( system_status.model == MODEL_TS_BOARD
+        || system_status.model == MODEL_SHIROBAKO )
+    {
+        // TS & ���� //
+        if( read_BT_SOC( temp ) == ERR_SUCCESS )
+        {
+            reg_volatile_temp_bt_remain = temp[0];
+            reg_volatile_temp_bt_remain_fine = temp[1];
+        }
+        else
+        {
+            // �G�~�����[�V�����@�\����������
+            // �@����œd���f�͕s�ւ����邾�낤
+            reg_volatile_temp_bt_remain = 99; 
+            reg_volatile_temp_bt_remain_fine = 0;
+        }
+    }
+    else
+    {
+        // ���@ //
+        // �c�ʃ��[�h
+        if( read_BT_SOC( temp ) != ERR_SUCCESS )
+        {
+            // �c��IC��NACK �c�o�b�e���͂��ꂽ
+            vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_MGIC_ERR;
+            bt_authorized = false;
+            reg_volatile_temp_bt_remain = 0;
+            force_off = true;
+        }
+        else
+        {
+            u16 temp_u16;
+
+		    vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_MGIC_ERR;
+            // �o�b�e���p�����[�^�̊֌W�Ńr�b�g�V�t�g���K�v
+            temp_u16 = temp[0] * 256 + temp[1];
+            temp_u16 /= p_bt_param->v_scale;
+            reg_volatile_temp_bt_remain = (u8)(( temp_u16 >> 8 ) & 0xFF );
+            if( reg_volatile_temp_bt_remain == 0 )
+            {
+                // 0%��̎���1.00%�ɏグ��
+                //  �[�d�J�n������΂炭�͓d�r�c�ʂ�����̂�
+                //  0%�ɓ��B���Ă��܂����Ƃ�����̂�
+                reg_volatile_temp_bt_remain = 1;
+				reg_volatile_temp_bt_remain_fine = 0;
+            }
+            else
+            {
+                reg_volatile_temp_bt_remain_fine = (u8)(temp_u16 & 0xFF);
+            }
+        }
+    }
+
+    // �d�r�d��
+    {
+        if( read_BT_voltage( temp ) != ERR_SUCCESS )  // 2byte read
+        {
+			temp[0] = (u8)( V_BT_4000MV / 256 );	// �d�r�d���ǂ߂Ȃ�������4000mV���������Ƃɂ��Ă����B
+            temp[1] = 0;
+        }
+        vreg_ctr[ VREG_C_BT_VOLTAGE ] = temp[0];
+        bt_volt16 = ( temp[0] * 256 + temp[1] );
+    }
+
+
+    // �d���ŃL���b�v...�̏���
+    {
+        static u16 hysteresis;
+
+        if( bt_volt16 > V_TH_30 )
+        {
+            fuel_cap_by_voltage = 100;
+            hysteresis = 0;
+        }
+        else if( bt_volt16 - hysteresis > V_TH_LO )
+        {
+            fuel_cap_by_voltage = 30;
+            hysteresis = 0;
+        }
+        else if( bt_volt16 > V_TH_EMPTY )
+        {
+            fuel_cap_by_voltage = BATT_TH_LO;  // ���������
+            hysteresis = 500;
+        }
+        else if( bt_volt16 > V_TH_ZERO )
+        {
+            fuel_cap_by_voltage = BATT_TH_EMPTY;
+            hysteresis = 500;
+        }
+        else if( bt_volt16 > V_TH_FORCE_OFF )
+        {
+            fuel_cap_by_voltage = 0;
+            hysteresis = 500;
+        }
+        else
+        {
+            force_off = true;
+            hysteresis = 500;
+        }
+    }
+    
+
+    // �[�d���i���A�_�v�^���h�����Ă�j�̂ɏ[�d���ĂȂ�
+    //     ���A�i���Ȃ��Ƃ��j�f�̓d�r�c�ʂ�60%�ȏ�iCCIC�o�O����ABT_IN_CHG_delayed_n�ɐD�荞�ݍς݁j
+    // = �[�d�����B�d�r���ւ����Ă����MGIC��100%��Ԃ��Ȃ�
+    if( !BT_CHG_Ena_n && BT_IN_CHG_delayed_n ){
+        reg_volatile_temp_bt_remain = 100;
+        reg_volatile_temp_bt_remain_fine = 0;
+    }
+    else
+    {   // �d���ł̃L���b�v���|���邩�H
+        if( fuel_cap_by_voltage < reg_volatile_temp_bt_remain )
+        {
+            reg_volatile_temp_bt_remain = fuel_cap_by_voltage;
+            reg_volatile_temp_bt_remain_fine = 0;
+        }
+    }
+
+	/*
+	�\���ɖ��Ȃ��d������������Ă�炵���̂ŃP�A�����ł悵
+	if( system_status.taikendai_nbd && system_status.model != MODEL_TS_BOARD )	// �d�r�[�q�ɓd�����‚Ȃ����ĂĒl���s���Ȃ��ߏ㏑���B
+    {
+        reg_volatile_temp_bt_remain = 100;
+    }
+	*/
+
+	vreg_ctr[ VREG_C_BT_REMAIN ]      = reg_volatile_temp_bt_remain;
+	vreg_ctr[ VREG_C_BT_REMAIN_FINE ] = reg_volatile_temp_bt_remain_fine;
+
+    // twl�̃��W�X�^�X�V�@(CTR�Ɋ��荞�ݓ����O�ɍX�V���Ȃ��Ɗ��荞�݂̃^�C�~���O���܂�����������Ȃ�)
+    bt_batt_update_twl();
+
+    // �c�ʂŊ��荞�݁B�}���Ɍ���Ɣ�Ԃ��Ƃ����� //
+    {
+        static u8 bt_remain_old_ctr;
+
+        if( bt_remain_old_ctr != reg_volatile_temp_bt_remain )
+        // CTR�ɒʒm
+        {
+            if( (( vreg_ctr[ VREG_C_BT_REMAIN ] <= BATT_TH_LO )    && ( BATT_TH_LO    < bt_remain_old_ctr ))||
+                (( vreg_ctr[ VREG_C_BT_REMAIN ] <= BATT_TH_EMPTY ) && ( BATT_TH_EMPTY < bt_remain_old_ctr ))||
+                (( vreg_ctr[ VREG_C_BT_REMAIN ] == 0 )             && ( bt_remain_old_ctr != 0 )) )
+            {
+                set_irq( VREG_C_IRQ1, REG_BIT_BT_REMAIN );
+            }
+        }
+        bt_remain_old_ctr = vreg_ctr[ VREG_C_BT_REMAIN ];
+    }
+
+    // PMIC-NTR�ɓd�r�c�ʂ������Ă�����
+    bt_batt_update_ntr();
+}
+
+
+
+/* ========================================================
+  �t���n�̓d������
+  �@�X�e�[�^�X�t���O�͂����ɗ��ĂĂ��܂��B
+   �@�s�������Ԃ����邵�A
+     �N�����s�ł���Γd����������
+     �ʂ̃^�X�N�œd�������͊Ď����Ă��āA�X�e�[�^�X���N���A����
+ ======================================================== */
+// BSR //
+err PM_LCD_on(  )
+{
+    err rv = ERR_ERR;
+
+    PM_VDDLCD_on(  );
+
+    if( system_status.family == FAMILY_SPFL )
+    {
+        SPFL_LCD_AMOL_HV_CONT = 1;
+    }
+
+    wait_ms( DELAY_PM_TSS_50B_AND_TCOM );
+
+    PM_TCOM_on(  );
+
+    wait_ms( DELAY_PM_TCOM_TO_VCS );
+
+    PM_VCS_on(  );
+
+    wait_ms( DELAY_PM_VCS_TO_BL );
+
+    if( PM_chk_LDSW() != 0 ) // ����p�X
+    {
+        // �d���N���G���[�Ȃ�d�����؂�Ă��܂��B�����ł̓P�A���Ȃ�
+        vreg_ctr[VREG_C_STATUS] |= REG_BIT_LCD_POW;
+        set_irq( VREG_C_IRQ3, REG_BIT_LCD_ON );
+		rv = ERR_SUCCESS;
+    }
+
+    return rv;
+}
+
+// BSR //
+void PM_LCD_off()
+{
+    // BL�‚��Ă�������B// �`�F�b�N����̂͊��荞�݂̊֌W
+    if( ( read_pmic( PM_REG_ADRS_BL ) & 0x03 ) != 0 )
+    {
+        u8 tot;
+
+        PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF );
+        vreg_ctr[VREG_C_STATUS] &= bits8(1,0,0,1, 1,1,1,1);
+
+        if( (( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 )
+        {
+            vreg_ctr[ VREG_C_IRQ3 ] |= ( ( REG_BIT_BL_U_OFF | REG_BIT_BL_L_OFF ) & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] );
+            IRQ0_neg;
+            tot = 0;
+            while( !IRQ0 && ( ++tot != 0 ) ){;}
+            IRQ0_ast;
+        }
+        vreg_ctr[VREG_C_COMMAND2] &= ~( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF );
+    }
+
+
+    // �t���d���؂� //
+    SPFL_LCD_AMOL_HV_CONT = 0;	// ���̃t�@�~���ł�L����Ȃ̂ŕ��Q�Ȃ�
+
+    // 50ms�Ƃ��҂‚��A�m�F���܂��傤���ˁc
+    if( read_pmic( PM_REG_ADRS_VDD_LCD ) != 0 )
+    {
+        if( system_status.family == FAMILY_SPFL )
+        {
+            wait_ms( 10 );  // �A�����t�@�X15V��؂����Ƃ��̃E�F�C�g�B
+        }
+
+        PM_TCOM_off();
+        wait_ms( 1 );
+        PM_TCOM_VCS_off(  );
+        wait_ms( DELAY_PM_LCD_OFF );
+
+        PM_VDDLCD_off(  ); // �c���Ă��̑S���~�߂܂��B
+        vreg_ctr[VREG_C_STATUS] &= ~REG_BIT_LCD_POW;
+    }
+
+	set_irq( VREG_C_IRQ3, REG_BIT_LCD_OFF );  // �������ɔ����B�}�X�N������΁B
+}
+
+
+
+/* ========================================================
+�@�o�b�N���C�g�̌•�on/off
+�@���󂩂�@on/off/�ێ��@�̃t���O�Ȃ̂Ŗʓ|
+�@�@�Ⴆ�΁ABL on/on �̏�ԂŁAon/on�ɂ���ƌ����Ă��Aon/on���荞�݂����܂��B
+======================================================== */
+err PM_BL_set( u8 dat )
+{
+    u8 blset;
+    u8 intset = 0;
+    // RMW���s��
+
+    // Read
+    blset = read_pmic( PM_REG_ADRS_BL );
+
+    // Modify
+    // ue
+    if(( dat & REG_BIT_CMD_BL_U_ON ) != 0 )
+    {
+        blset |= PM_REG_BIT_BL_U;
+        intset |= REG_BIT_BL_U_ON;
+    }
+    else if(( dat & REG_BIT_CMD_BL_U_OFF ) != 0 )
+    {
+        blset &= ~PM_REG_BIT_BL_U;
+        intset |= REG_BIT_BL_U_OFF;
+    }
+
+    // shita
+    if(( dat & REG_BIT_CMD_BL_L_ON ) != 0 )
+    {
+        blset |= PM_REG_BIT_BL_L;
+        intset |= REG_BIT_BL_L_ON;
+    }
+    else if(( dat & REG_BIT_CMD_BL_L_OFF ) != 0 )
+    {
+        blset &= ~PM_REG_BIT_BL_L;
+        intset |= REG_BIT_BL_L_OFF;
+    }
+
+    if( blset != 0 )  // BL��t����ꍇ�̓E�F�C�g�����܂Ȃ���PWM�����Ă��炸
+                      //  �V���b�g�_�E�����邱�Ƃ�����
+    {
+        wait_ms( 16 + 10 );
+    }
+    send_cmd_pmic(  PM_REG_ADRS_BL, blset );
+
+	//    SoC��PWM���o���悤���W�X�^���Z�b�g���Ă���x�����L�邽�߁A�X�e�[�^�X����
+	//    �X�V���Ă��܂��B���Ăق����Ƃ̗v���B
+
+	// PMIC��BL�̃r�b�g�ƁAMCU��STATUS���W�X�^�̃r�b�g�ʒu���t�Ȃ��ߓ���ւ�
+    vreg_ctr[VREG_C_STATUS] = (( vreg_ctr[VREG_C_STATUS] & bits8(1,0,0,1, 1,1,1,1) )
+                              | ( (( blset << 6 ) | ( blset << 4 )) & bits8(0,1,1,0, 0,0,0,0) ));
+
+    // ���荞��
+    /// �����r�b�g�܂Ƃ߂čs���̂ŁAset_irq()�g��Ȃ���������
+    {
+        u8 tot;
+
+        if( ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] ) != 0 )
+        {
+            vreg_ctr[ VREG_C_IRQ3 ] |= ( intset & ~vreg_ctr[ VREG_C_IRQ_MASK3 ] );
+            IRQ0_neg;
+            tot = 0;
+            while( !IRQ0 && ( ++tot != 0 ) ){;}
+            IRQ0_ast;
+        }
+    }
+
+    return( ERR_SUCCESS );         // �����łُ͈�`�F�b�N�s�v
+}
+
+
+
+/* ========================================================
+  �t���̑Ό��d���̐ݒ���s���܂��B
+  ���z���W�X�^�̓��e�𑗂邾��
+ ======================================================== */
+void PM_LCD_vcom_set(  )
+{
+    send_cmd_pmic(  PM_REG_ADRS_POW_DAC1, vreg_ctr[VREG_C_VCOM_T] );   // ��������Ȃ��ƂɁAPMIC�̓o�[�X�g�������ݕs��
+    send_cmd_pmic(  PM_REG_ADRS_POW_DAC2, vreg_ctr[VREG_C_VCOM_B] );
+    return;
+}
+
+
+
+/* ========================================================
+  ���ŁA���W�X�^�������݂���Ăяo����鎞�̂���
+  �@I2C�̎�荇���̊֌W�ł�������Ă�
+ ======================================================== */
+task_status_immed tski_vcom_set(  )
+{
+    PM_LCD_vcom_set(  );
+    return ( ERR_FINISED );
+}
+
+
+
+/* ========================================================
+  �V�[�P���X�̒ʂ�d���𗧂��グ�Ă䂫�܂��B
+  �Ԓl 0 �Ō�܂Ő���Ɋ��������B
+       1 �V���[�g�Ȃǂœd���������肫��Ȃ�����
+
+  �ȉ��̃s���͎�ɂ����ő���E�Ď�����܂��B
+  �EPOW_CONT1,2    TEG�d���̂�
+ ======================================================== */
+err PM_sys_pow_on(  )
+{
+    // �d�����������グ
+//    PM_reset_ast(  );       �s�v PM_LDSW_on�܂���
+    RESET2_ast;
+    FCRAM_RST_ast;
+    GYRO_DISABLE();
+
+    PM_LDSW_on(  );
+
+    wait_ms( 1 + DELAY_PM_TW_PWUP );
+
+    PM_VDD_normMode();
+    PM_VDD_on(  );
+//    wait_ms( DELAY_PM_TW_PWUP );   // GYRO�����ނ���
+    wait_ms( 10 );
+    GYRO_ENABLE();
+    wait_ms( DELAY_PM_TW_PWUP - 10 );
+
+    PM_VDD50A_on(  );  // �t���d���ł͂Ȃ��Aled�Ƃ��Ɏg�����̂ł�
+
+    wait_ms( DELAY_PM_TW_PWUP );
+
+    // �����d�����N���������`�F�b�N�B
+    if( !PM_chk_LDSW() )
+    {
+        return ( ERR_ERR );  // reset1�͂ق��Ƃ��ėǂ�
+    }
+
+    // �d������IC���
+    pmic_version = read_pmic( PM_REG_ADRS_VER );
+    read_mgic_2B( BT_GAUGE_REG_VERSION, mgic_version );
+
+    // ���Z�b�g�����ȂǁB�V�X�e���N���I
+    PM_reset_neg();
+    FCRAM_RST_neg;
+    RESET2_neg;
+
+    codec_reg_init();        // CODEC �s�背�W�X�^������(reset2�̌�łȂ��Ƃ����Ȃ��̂�)
+    ntr_pm_reg_shadow = 0;          // �@�V�@����ȂƂ����...
+
+    return ( ERR_SUCCESS );
+}
+
+
+
+
+/* ========================================================
+  �d��OFF�V�[�P���X
+ ======================================================== */
+void PM_sys_pow_off(  )
+{
+//    if( RESET1_n )
+    if( PM_chk_LDSW() )
+    {
+        // �ُ�I���łȂ��Ƃ�
+        PM_BL_set( REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_OFF );
+        PM_LCD_off();             //     TCOM,VCS OFF �������Ă��܂��B
+        wait_ms( 20 );
+
+        PM_reset_ast();
+    }
+
+    RESET2_ast;
+    FCRAM_RST_ast;
+
+    wait_ms( 20 );
+
+    PM_off(  );
+    PM_LDSW_off(  );
+
+}
+
+
+
+/*=========================================================
+  extDC���荞��
+  �d��OFF����N�����i�[�d�̉��x�Ď��̂��߁j�̂�
+  ���i�̓|�[�����O(pm)
+ =========================================================*/
+__interrupt void intp4_extdc(  )
+{
+}
+
+
+
+/*=========================================================
+  �t�^�J���‚ߊ��荞��
+  ���i�̓|�[���O(misc)
+ =========================================================*/
+__interrupt void intp5_shell(  )
+{
+    ;
+}
+
+
+/*=========================================================
+  ��PMIC�ւ̃R�}���h��������
+ =========================================================*/
+__interrupt void intp6_PM_irq(  )
+{
+    EI();
+    if( system_status.pwr_state == ON )
+    {
+        renge_task_immed_add( tski_ntr_pmic_comm );
+    }
+}
+
+
+/* ========================================================
+ PMIC����̊��荞�݂��󂯂āANTR PMIC�݊����W�X�^���烊�[�h
+ ======================================================== */
+task_status_immed tski_ntr_pmic_comm(  )
+{
+    u8        reg1_old;
+    u8        irq_work = 0;
+
+    reg1_old = ntr_pm_reg_shadow;
+    ntr_pm_reg_shadow = iic_mcu_read_a_byte( IIC_SLA_CODEC, CODEC_REG_PM );
+    if( iic_mcu_result != ERR_SUCCESS )
+    {
+        return ( ERR_FINISED );
+    }
+
+//    DI(  );
+
+    // �o�b�N���C�g �� ////////////////////////////////////
+    if( ( ( reg1_old ^ ntr_pm_reg_shadow ) & REG_BIT_TWL_REQ_BL_U ) != 0 )
+    {
+        if( ( ntr_pm_reg_shadow & REG_BIT_TWL_REQ_BL_U ) == 0 )             // ������
+        {
+            irq_work = REG_BIT_TWL_BL_U_OFF;
+        }
+        else
+        {
+            irq_work = REG_BIT_TWL_BL_U_ON;
+        }
+    }
+
+    // �o�b�N���C�g ��
+    if( ( ( reg1_old ^ ntr_pm_reg_shadow ) & REG_BIT_TWL_REQ_BL_L ) != 0 )
+    {
+        if( ( ntr_pm_reg_shadow & REG_BIT_TWL_REQ_BL_L ) == 0 )             // ������
+        {
+            irq_work |= REG_BIT_TWL_BL_L_OFF;
+        }
+        else
+        {
+            irq_work |= REG_BIT_TWL_BL_L_ON;
+        }
+    }
+
+//    EI();
+
+    vreg_ctr[ VREG_C_STATUS_1 ] = ( vreg_ctr[ VREG_C_STATUS_1 ] & ~REG_BIT_MASK_STATUS1_NTR_PM_REG ) 
+									| ( ntr_pm_reg_shadow & REG_BIT_MASK_STATUS1_NTR_PM_REG );  // TWL�o�b�N���C�g���̃~���[
+
+    irq_work &= ~vreg_ctr[ VREG_C_IRQ_MASK2 ];
+    // set_irq �����i
+    if( irq_work != 0 )
+    {
+        u8 tot;
+
+        vreg_ctr[ VREG_C_IRQ2 ] |= irq_work;
+        IRQ0_neg;  // ��u�グ�ăp���X�𑗂蒼��
+        tot = 0;
+        while( !IRQ0 && ( ++tot != 0 ) ){;}  // O.D�Ȃ̂ł����Ƃ�����̂�҂� �� IRQ_mcu ��L�ɔ����Ă�ƍ���(��•s��)
+        IRQ0_ast;
+    }
+
+    /// �o�b�N���C�g�A�C�𗘂����ď������肵�܂���B
+
+    // off���N�G�X�g //////////////////////////////////////
+    if( ( ntr_pm_reg_shadow & REG_BIT_TWL_REQ_OFF_REQ ) != 0 )
+    {
+        set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );
+    }
+
+    // ���Z�b�g���N�G�X�g /////////////////////////////////
+    if( ( ntr_pm_reg_shadow & REG_BIT_TWL_REQ_RST_REQ ) != 0 )
+    {
+        set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );
+    }
+
+    // �o�b�N���C�g���}�X�N���ď����߂�
+    EI(  );
+    if( ( ntr_pm_reg_shadow & ( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_REQ_RST_REQ )) != 0 )
+    {
+        ntr_pm_reg_shadow &= ~( REG_BIT_TWL_REQ_OFF_REQ | REG_BIT_TWL_REQ_RST_REQ );
+        iic_mcu_write_a_byte_codec( CODEC_REG_PM, ntr_pm_reg_shadow );
+    }
+    return ( ERR_FINISED );
+}
+
+
+
+/**********************************************************
+    command2 �t���n
+�@  ���b�p�[�I�ȕ��BERR_SUCCESS�����Ԃ��Ȃ����c
+**********************************************************/
+task_status_immed tski_PM_LCD_on()
+{
+    PM_LCD_on();
+    return( ERR_FINISED );
+}
+
+task_status_immed tski_PM_LCD_off()
+{
+    PM_LCD_off();
+    return( ERR_FINISED );
+}
+
+task_status_immed tski_PM_BL_set()
+{
+    u8 cmd_BL;                  // ��volatile�Ƃ��t���Ȃ��Ă����v�݂���
+
+    do
+    {
+        cmd_BL = vreg_ctr[VREG_C_COMMAND2];
+        PM_BL_set( cmd_BL ); // �}�X�N�ς�
+    }
+    while( cmd_BL != vreg_ctr[VREG_C_COMMAND2] );  // <- PM_BL_set���X�V����
+    vreg_ctr[VREG_C_COMMAND2] = 0;
+
+    return( ERR_FINISED );
+}
+
+
+
+/**********************************************************
+�@reset2 �� CODEC �Ƀ��Z�b�g��������A���W�X�^���s��ɂȂ邽��
+**********************************************************/
+void codec_reg_init()
+{
+    wait_ms( 100 );
+
+    ntr_pm_bt_low_old = conv_ctr_bt_to_twl_bt();
+
+    iic_mcu_write_a_byte_codec( CODEC_REG_BT, (u8)ntr_pm_bt_low_old ); // SoC ���珑����
+
+    vol_reset();
+//    renge_task_immed_add( tski_vol_update ); �|�[�����O����̂ŁB
+    vol_polling = 3;
+}
+
+
+/* ============================================================
+  �w���p�[�Ƃ��������b�p�[�Ƃ������H
+  ROM�ߖ�̂���
+ ============================================================ */
+err send_cmd_mgic_2B( u8 reg, u16 dat )  // ���M�o�b�t�@
+{
+    u16 temp = dat;
+    return iic_mcu_write( IIC_SLA_BT_GAUGE, reg, 2, &temp ); // DMA�]������̂ő��M�f�[�^�o�b�t�@�̃|�C���^���ǂ����K�v
+}
+
+err read_mgic_2B( u8 reg, u8* dat )  // ���M�o�b�t�@�͌Œ�
+{
+    return iic_mcu_read( IIC_SLA_BT_GAUGE, reg, 2, dat );
+}
+
+err send_cmd_pmic( u8 reg, u8 dat )
+{
+	return iic_mcu_write_a_byte( IIC_SLA_PMIC, reg, dat );
+}
+
+u8 read_pmic( u8 reg )
+{
+	return iic_mcu_read_a_byte( IIC_SLA_PMIC, reg );
+}
+
+
+/* ============================================================
+  �d�r���[�J�[�ƃ��f������A�g���d�r�p�����[�^�̌���
+ ============================================================ */
+void bt_param_select()
+{
+    BT_TYPE bt_type_temp;
+    // �Ή��������Ă����番��R�[�h���������‚����
+    if( battery_manufacturer <= BT_VENDER_3 )
+    {
+        bt_type_temp = BT_PARAM_CTR_MAXELL;
+    }
+    else
+    {
+        bt_type_temp = BT_PARAM_CTR_PANA;
+    }
+
+    if( system_status.family == FAMILY_SPFL )
+    {
+        bt_type_temp += BT_PARAM_SPFL_MAXELL;  // �I�t�Z�b�g �c�O�Ȏ����Łc�B
+    }
+    else if( system_status.family == FAMILY_SHRIMP )
+    {
+        bt_type_temp += BT_PARAM_SHRIMP_MAXELL;
+    }
+    p_bt_param = &bt_param[ bt_type_temp ];
+}
+
+
+
+
+#define TWL_BT_LEVEL_THREASH_F	60
+#define TWL_BT_LEVEL_THREASH_B	30
+#define TWL_BT_LEVEL_THREASH_1	0
+
+/* ============================================================
+  TWL�ɓd�r�c�ʂ������Ă�����
+ ============================================================ */
+static void bt_batt_update_twl()
+{
+    if (vreg_ctr[VREG_C_BT_REMAIN]		> TWL_BT_LEVEL_THREASH_F )
+    {
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x0F;
+    }
+    else if (vreg_ctr[VREG_C_BT_REMAIN] > TWL_BT_LEVEL_THREASH_B )
+    {
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x0B;
+    }
+    else if (vreg_ctr[VREG_C_BT_REMAIN] > BATT_TH_LO)
+    {
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x07;
+    }
+    else if (( vreg_ctr[ VREG_C_BT_REMAIN ] > BATT_TH_EMPTY )||
+             !BT_CHG_Ena_n )
+    { // �A�_�v�^�̗L���Œ�グ
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x03;
+    }
+    else if (vreg_ctr[VREG_C_BT_REMAIN] > TWL_BT_LEVEL_THREASH_1 )
+    {
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x01;
+    }
+    else
+    {
+        vreg_twl[REG_TWL_INT_ADRS_POWER_INFO] = 0x00;
+    }
+}
+
+
+/* ============================================================
+  NTR�ɓd�r�c�ʂ������Ă�����
+ ============================================================ */
+static void bt_batt_update_ntr()
+{
+    static bit initialized;
+    static bit flag;  // ����Hstatic�łȂ��ƃR���p�C���ɓ{����
+
+    if( system_status.pwr_state == OFF_TRIG )
+    {
+        initialized = false;
+    }
+    else
+    {
+
+        flag = conv_ctr_bt_to_twl_bt();
+
+        if(( ntr_pm_bt_low_old != flag ) || !initialized )
+        {
+            initialized = true;
+            ntr_pm_bt_low_old = flag;
+            iic_mcu_write_a_byte_codec( CODEC_REG_BT, (u8)flag );
+        }
+    }
+}
+
+
+/* ========================================================
+========================================================= */
+static err read_BT_SOC( u8* dest )
+{
+#ifdef _ENABLE_HAL_
+    if( vreg_ctr[ VREG_C_HAL_OVW_BT_FUEL ] != 0xFF )	// true�Ȃ�HAL�L��
+#else
+	if( 0 )
+#endif
+    {
+        *dest = vreg_ctr[ VREG_C_HAL_OVW_BT_FUEL ];
+        *(dest+1) = 0x00;
+        return ERR_SUCCESS;
+    }
+    else
+    {
+        return( read_mgic_2B( BT_GAUGE_REG_SOC, dest ) );
+    }
+}
+
+
+/* ========================================================
+========================================================= */
+static err read_BT_voltage( u8* dest )
+{
+#ifdef _ENABLE_HAL_
+	if( vreg_ctr[ VREG_C_HAL_OVW_BT_VOLTAGE ] != 0xFF )	// true�Ȃ�HAL�L��
+#else
+	if( 0 )
+#endif
+    {
+        *dest = vreg_ctr[ VREG_C_HAL_OVW_BT_VOLTAGE ];
+//        *(dest+1) = 0x00;            // �g��Ȃ���@���ǂQ�o�C�g���[�h�֐������p�ӂ��ĂȂ��̂ł�
+        return ERR_SUCCESS;
+    }
+    else
+    {
+        return( read_mgic_2B( BT_GAUGE_REG_VCELL, dest ) );
+    }
+}
+
+
+/* ========================================================
+ �d�r�c�ʂ�twl�Ƀt���O�ɂ��ĕԂ�
+========================================================= */
+static u8 conv_ctr_bt_to_twl_bt()
+{
+//    ntr_pm_bt_low_old = ( vreg_ctr[ VREG_C_BT_REMAIN ] <= BATT_TH_LO )? NTR_PM_BT_EMPTY: NTR_PM_BT_ENOUGH;  // 1�œd�r�؂�
+    if( vreg_ctr[ VREG_C_BT_REMAIN ] <= BATT_TH_LO )
+    {
+        return NTR_PM_BT_EMPTY;
+    }
+    else
+    {
+        return NTR_PM_BT_ENOUGH;
+    }
+}
diff --git a/tags/2.03_SDK-3.1/pm.h b/tags/2.03_SDK-3.1/pm.h
new file mode 100644
index 0000000..942da87
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pm.h
@@ -0,0 +1,216 @@
+#ifndef __PM__
+#define __PM__
+
+
+
+#define IIC_SLA_PMIC              0x84
+#define IIC_SLA_BT_GAUGE          0x6C
+
+#define VCOM_DEFAULT_T  92
+#define VCOM_DEFAULT_B  95
+
+
+
+#define BATT_TH_LO           10
+#define BATT_TH_EMPTY        5
+
+// �d�����W�X�^�ƒ��ڔ�r�ł���p�ɃI�t�Z�b�g
+#define V_BT_4000MV          (u16)( 4000 * 12.8 )		// �d���ǂݏo�����s�p 4000mV�ݒ�
+#define V_TH_30              (u16)( 3300 * 12.8 )		// 30%
+#define V_TH_LO              (u16)( 3200 * 12.8 )		// 10%
+#define V_TH_EMPTY           (u16)( 3150 * 12.8 )		//  5%
+#define V_TH_ZERO            (u16)( 3100 * 12.8 )		//  0%
+#define V_TH_FORCE_OFF       (u16)( 2900 * 12.8 )		// 2.9V �ŏI�����f
+
+
+//=========================================================
+#ifdef _WIN32
+#define LED_CHARGE           mcuRegP[ _P2_4 ]
+#else
+#define LED_CHARGE           P2.4
+#endif
+
+
+//=========================================================
+enum PMIC_REG_ADRS
+{
+  PM_REG_ADRS_VER = 0x00,       // verinfo �Ȃ�
+  PM_REG_ADRS_VDD_SYS,          // �V�X�e�����g�p����d��
+  PM_REG_ADRS_VDD_LCD,          // �t���d��
+  PM_REG_ADRS_CONT,             // /RESET1, LoadSwitch
+  PM_REG_ADRS_BL,               // �o�b�N���C�g on/off
+  PM_REG_ADRS_POW_SAVE,         // �ȓd�͐ݒ�
+  PM_REG_ADRS_POW_DAC1,
+  PM_REG_ADRS_POW_DAC2
+};
+
+enum BT_GAUGE_REG_ADRS
+{
+  BT_GAUGE_REG_VCELL    = 0x02,    // ���ꂼ��16�r�b�g�̂���
+  BT_GAUGE_REG_SOC      = 0x04,
+  BT_GAUGE_REG_MODE     = 0x06,
+  BT_GAUGE_REG_VERSION  = 0x08,
+  BT_GAUGE_REG_OCV      = 0x0E,
+  BT_GAUGE_REG_RCOMP    = 0x0C,
+  BT_GAUGE_REG_LOCK     = 0x3E,
+  BT_GAUGE_REG_BT_PARAM = 0x40,
+  BT_GAUGE_REG_COMMAND  = 0xFE
+};
+
+
+typedef enum BT_VENDER
+{
+    BT_VENDER_MAXELL = 0,               // �V���[�g
+    BT_VENDER_1,                       // 120
+    BT_VENDER_2,                       // 360
+    BT_VENDER_3,                       // 750
+    BT_VENDER_4,                       // 1.3k
+    BT_VENDER_PANA   = 5,              // 2.7k
+    BT_VENDER_6,                       // 8.2k
+    BT_VENDER_OPEN = 7,                // open
+    BT_VENDER_NOT_CHECKED = 0xFF,
+}BT_VENDER;
+
+
+
+enum NTR_PM_BT_STATUS{
+    NTR_PM_BT_ENOUGH,
+    NTR_PM_BT_EMPTY,
+    NTR_PM_BT_NOT_INITIALIZED = 0xFF
+};
+
+
+
+//=========================================================
+// CODEC���PMIC�݊����W�X�^
+#define CODEC_REG_PM 0x10
+#define CODEC_REG_BL 0x11
+#define CODEC_REG_BT 0x12
+//#define CODEC_REG_VOL 0x13   // ...�s���ɂ��Aadc.h�Œ�`
+
+// TWL��SPI��PMIC�ɓ������R�}���h
+#define REG_BIT_TWL_REQ_OFF_REQ  ( 1 << 6 )
+#define REG_BIT_TWL_REQ_RST_REQ  ( 1 << 0 )
+#define REG_BIT_TWL_REQ_BL       ( 3 << 2 )
+
+
+
+
+// 0x03 pw cnt3
+#define PM_REG_BIT_LDSW      ( 1 << 0 )
+#define PM_REG_BIT_nRST1     ( 1 << 1 )
+
+// 0x01 pw cnt1
+#define PM_REG_BIT_VDD        0x0F
+#define PM_REG_BIT_VDD50A    ( 1 << 4 )
+
+// 0x02 pw cnt2
+#define PM_REG_BIT_VDDLCD_CGS    0x07
+#define PM_REG_BIT_VDDLCD_AMO    0x05
+#define PM_REG_BIT_LCD_VCS   ( 0x01 << 4 )
+#define PM_REG_BIT_LCD_TCOM  ( 0x01 << 3 )
+
+// 0x04 bl cnt
+#define PM_REG_BIT_BL_U         0x01
+#define PM_REG_BIT_BL_L         0x02
+
+
+// 0x05 pow save
+#define PM_REG_BIT_VDD1P_1R15   bits8(0,0,0,0, 0,0,0,0)
+#define PM_REG_BIT_VDD1P_1R05   bits8(0,0,0,0, 1,0,0,0)
+#define PM_REG_BIT_VDD1P_0R90   bits8(0,0,1,0, 0,0,0,0)
+#define PM_REG_BIT_VDD_AUTO     bits8(0,0,0,0, 0,1,1,1)
+#define PM_REG_BIT_VDD_PWM      bits8(0,0,0,0, 0,0,0,0)
+
+
+#define DELAY_PM_TW_PWUP               16 + 2
+#define DELAY_PM_TSS_50B_AND_TCOM      17 + 1
+#define DELAY_PM_5V_TO_TCOM            17 + 1
+#define DELAY_PM_TCOM_TO_VCS           3
+#define DELAY_PM_VCS_TO_BL             ( 17 + 5 )
+#define DELAY_PM_LCD_OFF               ( 50 + 1 )
+
+
+//=========================================================
+extern u8 raw_adc_temperature;
+extern BT_VENDER battery_manufacturer;
+extern bit bt_force_update;
+
+extern u8 pmic_version;
+extern u8 mgic_version[];
+
+extern u8 pm_reg_bit_vddlcd;  // �A�����t�@�X�Ή�(�d���V�[�P���X���Ⴄ)
+
+
+//=========================================================
+err PM_sys_pow_on(  );
+void PM_sys_pow_off(  );
+//err PM_bt_auth(  );
+void PM_LCD_vcom_set(  );
+
+err PM_LCD_on(  );
+void PM_LCD_off(  );
+err PM_BL_set( u8 );
+
+
+void BT_chk();
+void BT_get_left();
+void pm_chk_adapter();
+
+void codec_reg_init();
+
+
+task_status_immed tski_BT_temp_update(  );
+task_status_immed tski_vcom_set(  );
+task_status_immed tski_PM_LCD_on();
+task_status_immed tski_PM_LCD_off();
+task_status_immed tski_PM_BL_set();
+
+
+err send_cmd_pmic( u8 reg, u8 dat );
+u8 read_pmic( u8 reg );
+
+
+#define PM_Chg_Stop()  { BT_TEMP_P = 0; BT_CHG_DISABLE(); LED_CHARGE = 0; bt_authorized = false; }
+//  �@������ĂԑO�ɁA���݉��x�������Ă����K�v������܂��B
+#define PM_reset()     ( send_cmd_pmic(  PM_REG_ADRS_CONT, 0x00 ) )
+
+
+//=========================================================
+
+
+// ���� //
+#define PM_LDSW_on()	( send_cmd_pmic(  PM_REG_ADRS_CONT, PM_REG_BIT_LDSW ))
+#define PM_LDSW_off()	( send_cmd_pmic(  PM_REG_ADRS_CONT, 0 ))
+
+
+// �V�X�e���d�� //
+#define PM_VDD_on()		( send_cmd_pmic(  PM_REG_ADRS_VDD_SYS, PM_REG_BIT_VDD ))
+#define PM_VDD50A_on()	( send_cmd_pmic(  PM_REG_ADRS_VDD_SYS, ( PM_REG_BIT_VDD | PM_REG_BIT_VDD50A )))
+#define PM_VDD_off()	( send_cmd_pmic(  PM_REG_ADRS_VDD_SYS, 0 ))
+#define PM_off()		PM_VDD_off()
+
+#define PM_VDD_normMode()   ( send_cmd_pmic(  PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_1R15 | PM_REG_BIT_VDD_PWM ))
+#define PM_VDD_ecoMode()    ( send_cmd_pmic(  PM_REG_ADRS_POW_SAVE, PM_REG_BIT_VDD1P_0R90 | PM_REG_BIT_VDD_AUTO ))
+// todo Y�ŃR�A�d�����ς�邩������Ȃ�
+
+// �ق� //
+#define PM_reset_neg()	( send_cmd_pmic(  PM_REG_ADRS_CONT, ( PM_REG_BIT_LDSW | PM_REG_BIT_nRST1 )))
+#define PM_reset_ast()	( send_cmd_pmic(  PM_REG_ADRS_CONT, ( PM_REG_BIT_LDSW )))
+#define PM_chk_LDSW()	( read_pmic( PM_REG_ADRS_CONT ) & PM_REG_BIT_LDSW )
+// �� 1�̂Ƃ��A���d��on
+
+// �t���n�d�� //
+#define PM_VDDLCD_on()	( send_cmd_pmic(  PM_REG_ADRS_VDD_LCD, pm_reg_bit_vddlcd ))
+#define PM_TCOM_on()	( send_cmd_pmic(  PM_REG_ADRS_VDD_LCD, ( pm_reg_bit_vddlcd | PM_REG_BIT_LCD_TCOM )))
+#define PM_VCS_on()		( send_cmd_pmic(  PM_REG_ADRS_VDD_LCD, ( pm_reg_bit_vddlcd | PM_REG_BIT_LCD_VCS | PM_REG_BIT_LCD_TCOM )))
+#define PM_TCOM_off()   ( send_cmd_pmic(  PM_REG_ADRS_VDD_LCD, ( pm_reg_bit_vddlcd | PM_REG_BIT_LCD_VCS )))
+#define PM_TCOM_VCS_off() PM_VDDLCD_on()
+#define PM_VDDLCD_off() ( send_cmd_pmic(  PM_REG_ADRS_VDD_LCD, 0 ) )
+
+#define PM_set_BL( dat )	( send_cmd_pmic(  PM_REG_ADRS_BL, dat ) )
+#define PM_set_adc1( dat )	( send_cmd_pmic(  PM_REG_ADRS_POW_DAC1, dat ) )
+#define PM_set_adc2( dat )	( send_cmd_pmic(  PM_REG_ADRS_POW_DAC2, dat ) )
+
+
+#endif // __PM__
diff --git a/tags/2.03_SDK-3.1/pool.h b/tags/2.03_SDK-3.1/pool.h
new file mode 100644
index 0000000..81c8091
--- /dev/null
+++ b/tags/2.03_SDK-3.1/pool.h
@@ -0,0 +1,24 @@
+#ifndef _pool_h_
+#define _pool_h_
+
+
+#include "pedometer.h"
+
+#define VREG_C_FREE_SIZE     200
+
+// �󂢂Ă郁����
+typedef struct _st_vreg_c_ext{
+    unsigned short pedo_log[ PEDOMETER_LOG_SIZE ];
+    unsigned char vreg_c_free[ VREG_C_FREE_SIZE ];
+}st_vreg_c_ext;
+
+typedef union _uni_pool
+{
+    st_vreg_c_ext vreg_c_ext;
+    u8 self_update_work[ 256 ]; // 256�ȏ�͂܂Ƃߏ����ł��Ȃ�
+}uni_pool;
+
+extern uni_pool pool;
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/reboot.c b/tags/2.03_SDK-3.1/reboot.c
new file mode 100644
index 0000000..b784f15
--- /dev/null
+++ b/tags/2.03_SDK-3.1/reboot.c
@@ -0,0 +1,24 @@
+/********************************************************//*
+
+  �ނ��胊�u�[�g
+
+  �t�@�C�����ɃC�����C���A�Z���u��������ƁA
+  ���̃��W���[���S���œK���������Ȃ��Ȃ邽�ߒǂ��o����
+
+ **********************************************************/
+#pragma SFR
+
+#include "incs_loader.h"
+
+
+void my_reboot(){
+#asm
+
+    MOV     PSW,#06H                ; �_�~�[��PSW���Z�b�g
+    MOVW    AX,#000d0h              ; ���Z�b�g�̃x�N�^�l����荞��ł��܂��B
+    PUSH    PSW
+    PUSH    AX                      ; �����RETI�̂��߂̃X�^�b�N������
+    RETI                            ; ����Ń��Z�b�g�E�x�N�^�ɕ���
+
+#endasm
+}
diff --git a/tags/2.03_SDK-3.1/reboot.h b/tags/2.03_SDK-3.1/reboot.h
new file mode 100644
index 0000000..c20e11e
--- /dev/null
+++ b/tags/2.03_SDK-3.1/reboot.h
@@ -0,0 +1,6 @@
+#ifndef __MYREBOOT__
+#define __MYREBOOT__
+
+void my_reboot();
+
+#endif
diff --git a/tags/2.03_SDK-3.1/renge/renge.c b/tags/2.03_SDK-3.1/renge/renge.c
new file mode 100644
index 0000000..c7ad624
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge.c
@@ -0,0 +1,312 @@
+#ifndef _WIN32
+
+#pragma section @@CODE ROM_CODE
+#pragma nop
+#pragma ei
+#pragma di
+#pragma sfr
+
+#endif
+
+
+#ifdef _WIN32
+typedef unsigned char bit;
+typedef unsigned char u8;
+#endif
+
+/******************************************************************************
+ �^�X�N�V�X�e���H
+  �Ȃ�قǁAiTRON�ɂ̓R���t�B�M�����[�^������͂����B
+  �����܂���
+  ctr_mcu_config.rb �Q�ƁB task_config.h���쐬����܂��B
+ *****************************************************************************/
+#include "renge.h"
+#include "renge_task_intval.h"
+#include "renge_task_immediate.h"
+#include "..\WDT.h"
+#include "..\config.h"
+#include "..\user_define.h"
+
+#ifdef _WIN32
+#include "../sim/simOnWin.h"
+#endif
+//#define _renge_test_
+
+#define true 1
+#define false 0
+
+//******************************************************************************
+u8 renge_flg_interval;
+bit renge_task_interval_run_force;
+bit renge_task_immediate_not_empty;
+
+
+#include "..\bsr_system.h"
+extern system_status_ system_status;
+
+
+//******************************************************************************
+static void renge_task_immed_init();
+static void renge_task_immed_del();
+
+
+
+//******************************************************************************
+task_status_immed ( *tasks_immed[ TASK_IMMED_RUN_LIST_MAX ] )();
+extern void DI_wt_chk();
+
+
+
+/******************************************************************************
+  ������
+�E�^�X�N�V�X�e���̓��I�����̏�����
+�E�C���^�[�o���^�C�}
+ *****************************************************************************/
+void renge_init(){
+  renge_task_immed_init();
+  /*
+    �C�x���g�^�C�}�̃Z�b�g�Ȃ�
+    �����RTC�𗬗p���Ă���̂ŃR�����g�A�E�g
+    #define renge_tick 19xxxxxxx [ms]
+    renge_interval_init(); �� RTC_init();
+   */
+}
+
+
+
+/******************************************************************************
+ �V�X�e���`�b�N��i�߂�
+ *****************************************************************************/
+/*
+void renge_interval(){
+// RTC����������
+��__interrupt void int_rtc_int();
+}
+*/
+
+
+
+/******************************************************************************
+ �R���p�C�����Ɍ��܂��Ă���A�C���^�[�o���N���̃^�X�N
+  ���̂����A�����N���ƍ����邩������Ȃ��B
+ *****************************************************************************/
+__callt err renge_task_interval_run(){
+  u8 i;
+
+  // �C���^�[�o���N��
+    DI_wt_chk();
+  if(( renge_flg_interval != 0 ) ||
+     ( renge_task_interval_run_force )) /// ���������������ȁc
+  {
+      renge_task_interval_run_force = false;  // ������N������^�X�N�A���荞�ރ^�X�N�Ńt���O�����‚����Ȃ̂�
+      if( renge_flg_interval != 0 )
+      {
+          renge_flg_interval --;
+          WDT_Restart(  );
+      }
+      EI();
+      for( i = 0; i != TSK_LAST; i ++ )
+      {
+          tasks[ i ]();
+          // �����N���^�X�N����������Ԃɋ���
+          renge_task_immed_run();
+      }
+  }
+  EI();
+  return( ERR_SUCCESS );
+}
+
+
+
+/*****************************************************************************
+ ������N���^�X�N��
+
+ ��task_immed ��Ԃ��֐��B
+ ���V�X�e��tick�A���炩�̊��荞�݁iI2C�ʐM�����Ȃǁj��
+ �X���[�v���畜�A�����^�C�~���O�Ŏ��s����܂��B
+
+���Ԓl�@ERR_FINISED�@�^�X�N���폜
+�@�@�@�@����ȊO     ���̃^�C�~���O�ł܂����s
+
+ *****************************************************************************/
+
+
+/**************************************
+ **************************************/
+void renge_task_immed_init(){
+    u8 i;
+
+    for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i++ ){
+        tasks_immed[ i ] = TSK_IMM_EMPTY_;
+    }
+}
+
+
+
+/**************************************
+  �������s�^�X�N�̓o�^
+  ���荞�݋֎~ 36us ��
+ **************************************/
+__callt err renge_task_immed_add( task_status_immed (*new_task)() ){
+    u8 i;
+
+    // ���X�g�̋󂫂̐擪�ɓo�^
+    // �폜�����΂���̃^�X�N�́A�폜�}�[�N(TSK_IMM_DELETED_)�ƂȂ�A�󂫂Ƃ͖����I�ɋ�ʂ����
+    // �d���o�^�������
+    for( i = 0; i < TASK_IMMED_RUN_LIST_MAX; i ++ )
+    {
+        DI_wt_chk();
+        if( tasks_immed[ i ] == TSK_IMM_EMPTY_ )
+        {
+            // �󂫂����‚���
+            tasks_immed[ i ] = new_task;
+            EI();
+            return( ERR_SUCCESS );
+        }
+        else
+        {
+            // �d���o�^�`�F�b�N
+            /// �������ɂȂ��ĂȂ��A�O�l�߂���Ă�O��
+            if( tasks_immed[ i ] == new_task )
+            {
+                // �d���o�^�͂��Ȃ�
+                EI();
+                return( ERR_ERR );
+            }
+        }
+        EI();
+    }
+    // �^�X�N�o�^������(�����͂�
+    return( ERR_ERR );
+}
+
+
+
+/**************************************
+  �������s�^�X�N�̎��s
+ **************************************/
+__callt err renge_task_immed_run(){
+    u8 list_id;
+
+//    while( tasks_immed[ 0 ] != TSK_IMM_EMPTY_ )
+    if( tasks_immed[ 0 ] != TSK_IMM_EMPTY_ )
+    {
+        DI_wt_chk();
+        for( list_id = 0; list_id < TASK_IMMED_RUN_LIST_MAX; list_id ++ ){
+            if( tasks_immed[ list_id ] == TSK_IMM_EMPTY_ ){
+                // ���X�g����
+                EI();
+                break;
+            }
+#ifdef _renge_test_
+            else if( tasks_immed[ list_id ] == TSK_IMM_DELETED_ )
+            {
+                EI();
+                NOP();
+                // �^�X�N�Ǘ��̕s��
+                // ���݂��Ȃ��^�X�N�����s���悤�Ƃ���
+                // �^�X�N�̍폜��̏������܂���
+                // �\�����Ȃ��^�C�~���O�� immed_run ���Ă΂ꂽ
+            }
+#endif
+            else
+            {
+                u8 rv;
+
+                EI();
+                rv = tasks_immed[ list_id ]();	// �^�X�N���s
+                if( rv == ERR_SUCCESS )
+                {
+                    tasks_immed[ list_id ] = TSK_IMM_DELETED_;
+                }
+				// ����ǂ��^�C�~���O�œ����^�X�N�̓o�^������ƍ���̂�DI��Ԃł������ė��鎖������
+            }
+            DI_wt_chk();
+        }
+        // ���X�g��̃^�X�N����ʂ���s����
+
+        // �^�X�N�폜 //
+        {
+            u8 i = 0; // ���X�g�̕��בւ���
+            u8 j = 1;
+
+            // �K�� i < j�Aj < TASK_IMMED_RUN_LIST_MAX (�łȂ��ƃ^�X�N���ӂ�)
+            while( 1 )
+            {
+                if( tasks_immed[ i ] == TSK_IMM_EMPTY_ )
+                {
+                    // �O�l�ߊ��� && ���X�g�����
+                    // break;
+                    goto imm_list_sort_fin;
+                }
+                else if( tasks_immed[ i ] == TSK_IMM_DELETED_ )
+                {
+                    for( ; j < TASK_IMMED_RUN_LIST_MAX; j++ )
+                    {
+                        if( tasks_immed[ j ] == TSK_IMM_DELETED_ )
+                        {
+                            // �ׁi�H�j���폜�Ώۂ�����
+                            // next j
+                        }
+                        else
+                        {
+                            DI_wt_chk();
+                            if( tasks_immed[ j ] == TSK_IMM_EMPTY_ )
+                            {
+                                do{
+                                    j --;
+                                    tasks_immed[ j ] = TSK_IMM_EMPTY_;
+                                    // ���X�g�O�l�ߊ���
+                                }while( i < j );
+                                EI();
+                                goto imm_list_sort_fin;
+                            }
+                            else
+                            {
+                                // �O�l�߂��ׂ��^�X�N�����‚���
+                                tasks_immed[ i ] = tasks_immed[ j ];
+                                tasks_immed[ j ] = TSK_IMM_DELETED_;
+                                i ++;
+                                EI();
+                            }
+                        }
+                    }
+                }
+                else
+                {
+                    // ���̃^�X�N�A�ؗ�
+                }
+                i ++;
+            }
+        }
+    }
+
+imm_list_sort_fin:
+        // �����܂łŊ��S�ɑO�l�߂���Ă���
+#ifdef _renge_test_
+        /// �ق��?
+        {
+            u8 a,b;
+
+            a = 0;
+            for( b = 0 ; b < TASK_IMMED_RUN_LIST_MAX; b++ )
+            {
+                if( tasks_immed[ b ] == TSK_IMM_EMPTY_ )
+                {
+                    a = 1;
+                }
+                else
+                {
+                    if( a != 0 )
+                    {
+                        NOP();    // EMPTY�����Ƀ^�X�N��deleted���L��
+                    }
+                }
+            }
+        }
+#else
+        NOP();  // �Ȃ񂩖����ƃ����J���{��
+#endif
+//  }
+    return( ERR_SUCCESS );
+}
diff --git a/tags/2.03_SDK-3.1/renge/renge.h b/tags/2.03_SDK-3.1/renge/renge.h
new file mode 100644
index 0000000..9c7b2e4
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge.h
@@ -0,0 +1,26 @@
+#ifndef __renge__
+#define __renge__
+
+//******************************************************************************
+
+
+
+//******************************************************************************
+#include "renge_defs.h"
+#include "renge_task_immediate.h"
+// #include "renge_task_interval_run.h" // �O���狭���N���֎~�I
+
+//******************************************************************************
+void renge_init();
+void renge_task_immed_init();
+__callt err renge_task_immed_run();
+__callt err renge_task_immed_add( task_status_immed (*p_task_func)() );
+// static err renge_task_immed_del( u8 );
+
+
+//******************************************************************************
+__callt err renge_task_interval_run();
+extern u8 renge_flg_interval;
+extern bit renge_task_interval_run_force;  // �^�X�N�������s�t���O
+
+#endif
diff --git a/tags/2.03_SDK-3.1/renge/renge_defs.h b/tags/2.03_SDK-3.1/renge/renge_defs.h
new file mode 100644
index 0000000..0199d76
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge_defs.h
@@ -0,0 +1,55 @@
+#ifndef __renge_defs__
+#define __renge_defs__
+/******************************************************************************
+  Renge Ver.0      (2009/04/09)
+  2009- 7k4jhl R.Fujita @ RED.nintendo
+
+  OS�ɂ͂قlj����A�ȈՓI�ȃ^�X�N�V�X�e���B
+  Range �� Typo �ł͂Ȃ��ł��B�����Q�ł��B
+
+  �Ȃ�� �����Q �͑��̂œ��{���� �Q���Q
+  ���������ǖ��ɗ��–𑐂ł��B
+  �傫������ĂˁI
+ ******************************************************************************/
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+
+
+// ************************************
+#define SYS_INTERVAL_TICK 1.953
+
+
+
+// ************************************
+typedef enum _ERR
+{
+  ERR_SUCCESS = 0,
+  ERR_ERR
+}err;
+
+
+typedef enum _IMMED_TASK_ERR
+{
+  ERR_FINISED = 0,
+  ERR_CONTINUE
+}IMMED_TASK_ERR;
+
+
+
+/**************************************
+ �C���^�[�o���N��
+ *************************************/
+typedef void task_status;
+
+
+/**************************************
+ ����N���̃^�X�N���X�g
+ �p�~�ɂȂ邩������Ȃ���
+ *************************************/
+typedef IMMED_TASK_ERR task_status_immed;
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/renge/renge_task_config.rb b/tags/2.03_SDK-3.1/renge/renge_task_config.rb
new file mode 100644
index 0000000..c2de509
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge_task_config.rb
@@ -0,0 +1,59 @@
+#!/usr/bin/ruby -Ks
+
+tasklist = Array.new
+
+
+if( ARGV[0] == nil )
+  printf( "����t�@�C�� renge_tasks.txt ���g�p���܂�" )
+  datfile = "renge_tasks.txt"
+else
+  datfile = ARGV[0]
+end
+
+if( !File.exist?( datfile ) )
+  printf("�ݒ�t�@�C�������‚���܂���B")
+  exit( 1 )
+end
+  
+
+setting = File.open( datfile )
+
+setting.each{|dat|
+  dat.chomp!
+  if( dat != nil )
+    tasklist << dat
+  end
+}
+
+tasklist.each{|dat|
+  printf( "\n%s" , dat )
+}
+printf( "\n----------\n�^�X�N�� %d \n", tasklist.size )
+
+
+#----- �ÓI�^�X�N�̗� -------------------------------------------------------
+conf = File.new( "renge_task_intval.h", "w+" )
+
+conf << "/*�X�N���v�g�ɂ�鎩�������ł��B�蓮�ŏ��������Ȃ������悢�ł�*/\n\n"
+conf << "#ifndef __renge_task__\n#define __renge_task__\n\n"
+conf << "#include \"renge_defs.h\"\n\n"
+
+conf << "enum {\n  "
+tasklist.each{|dat|
+  conf << "TSK_" << dat.upcase << ", "
+}
+conf << "TSK_LAST \n  };\n\n"
+
+
+tasklist.each{|dat|
+  conf << "extern void tsk_" << dat << "();\n"
+}
+conf << "\n"
+
+conf << "const void ( *tasks[ TSK_LAST ] )() = {\n"
+tasklist.each{|dat|
+  conf << "  tsk_" << dat << ",\n"
+}
+conf << "  };\n"
+
+conf << "\n#endif\n"
diff --git a/tags/2.03_SDK-3.1/renge/renge_task_immediate.h b/tags/2.03_SDK-3.1/renge/renge_task_immediate.h
new file mode 100644
index 0000000..9ac3bd2
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge_task_immediate.h
@@ -0,0 +1,25 @@
+#ifndef __tasks__
+#define __tasks__
+
+#include "renge_defs.h"
+
+// *************************************
+#define TASK_IMMED_RUN_LIST_MAX 10
+
+
+extern task_status_immed tski_do_command0(  );
+extern task_status_immed tski_ntr_pmic_comm();
+extern task_status_immed tski_acc_read();
+extern task_status_immed tski_acc_write();
+//extern task_status_immed tski_acc_setup();  // accero.h
+extern task_status_immed tski_mcu_reset();
+extern task_status_immed tski_vol_update();
+
+
+// *************************************
+#define TSK_IMM_EMPTY_ ( void * )( 0x0000 )
+#define TSK_IMM_DELETED_ ( void * )( 0x0001 )
+
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/renge/renge_task_intval.h b/tags/2.03_SDK-3.1/renge/renge_task_intval.h
new file mode 100644
index 0000000..9b0d9ea
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge_task_intval.h
@@ -0,0 +1,37 @@
+/*�X�N���v�g�ɂ�鎩�������ł��B�蓮�ŏ��������Ȃ������悢�ł�*/
+
+#ifndef __renge_task__
+#define __renge_task__
+
+#include "renge_defs.h"
+
+enum TSK
+{
+  TSK_SW, TSK_ADC, TSK_BATT, TSK_LED_POW, TSK_LED_WIFI, TSK_LED_NOTIFY, TSK_LED_CAM, TSK_MISC, TSK_STATUS, TSK_SYS, TSK_LAST 
+  };
+
+extern void tsk_sw();
+extern void tsk_adc();
+extern void tsk_batt();
+extern void tsk_led_pow();
+extern void tsk_led_wifi();
+extern void tsk_led_notify();
+extern void tsk_led_cam();
+extern void tsk_misc();
+extern void tsk_status();
+extern void tsk_sys();
+
+const void ( *tasks[ TSK_LAST ] )() = {
+  tsk_sw,
+  tsk_adc,
+  tsk_batt,
+  tsk_led_pow,
+  tsk_led_wifi,
+  tsk_led_notify,
+  tsk_led_cam,
+  tsk_misc,
+  tsk_status,
+  tsk_sys,
+  };
+
+#endif
diff --git a/tags/2.03_SDK-3.1/renge/renge_tasks.txt b/tags/2.03_SDK-3.1/renge/renge_tasks.txt
new file mode 100644
index 0000000..73af545
--- /dev/null
+++ b/tags/2.03_SDK-3.1/renge/renge_tasks.txt
@@ -0,0 +1,11 @@
+sw
+adc
+batt
+led_pow
+led_wifi
+led_notify
+led_cam
+misc
+status
+debug
+sys
diff --git a/tags/2.03_SDK-3.1/rtc.c b/tags/2.03_SDK-3.1/rtc.c
new file mode 100644
index 0000000..e3bdcfa
--- /dev/null
+++ b/tags/2.03_SDK-3.1/rtc.c
@@ -0,0 +1,177 @@
+/* ========================================================
+  RTC
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma sfr
+#pragma inline
+
+#endif
+
+#include "incs.h"
+
+
+#define RTC_DATA_SIZE 7
+// ========================================================
+static u8      rtc_work[RTC_DATA_SIZE];
+static bit     rtc_lock;
+static bit     rtc_dirty;
+bit     rtc_alarm_dirty;
+
+
+/* ========================================================
+ �y���t�F�����̏�����
+ ���W�X�^�̓d�r�����r�b�g�̃Z�b�g
+ ======================================================== */
+void RTC_init( void )
+{
+
+    if( !RTCEN )            // �r�b�g�������Ă����烊�u�[�g
+    {
+        RTCEN = 1;              // ���W���[��ON
+
+        // RTC�ݒ�
+        RTCC0 = bits8(0,0,0,0, 1,0,0,0);    /* �����~�A24���Ԑ��A32k�o�́u�܂��Ȃ��v�A��������荞�݂Ȃ� */
+											// (RTCE 0 RCLOE1 RCLOE0 AMPM CT2 CT1 CT0)
+        RTCC1 = bits8(1,1,0,0, 0,0,0,0);    /* �A���[�����荞�ݗL��������J�n */
+											// (WALE WALIE 0 WAFG RIFG 0 RWST RWAIT)
+        RTCC2 = bits8(1,0,0,0, 0,0,0,0);    /* �C���^�[�o��:32k/2^6=2ms�ARTCDIV�o�͂Ȃ� */
+											// (RINTE RCLOE2 RCKDIV 0 0 ICT2 ICT1 ICT0)
+
+        HOUR  = 0x00;
+        MIN   = 0x00;
+        SEC   = 0x00;
+        MONTH = 0x01;
+        DAY   = 0x01;
+        WEEK  = 0x01;           // Mon
+        YEAR  = 0x01;
+
+        ALARMWW = 0x7F;
+
+        vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT;
+    }
+    // ���荞�ݐݒ�
+    RTCIF = 0;
+    RTCIIF = 0;
+    RTCMK = 1;                  /* ���荞��(�����)�֎~ */
+    RTCIMK = 0;                 /* ���荞��(�A���[��&�C���^�[�o��)���� */
+
+    RTCE = 1;                   /* ����J�n */
+
+    RWAIT = 1;
+    while( !RWST )
+    {;}
+    RWAIT = 0;
+
+    rtc_lock = false;
+    rtc_dirty = false;
+    rtc_alarm_dirty = false;
+}
+
+
+
+/* ========================================================
+ RTC �A���[�����荞��
+ ======================================================== */
+__interrupt void int_rtc(  )
+{
+    RWAIT = 1;
+    while( !RWST )
+    {;}
+    // ���t���w�����
+    if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY )
+        && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH )
+        && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) )
+    {
+        set_irq( VREG_C_IRQ1, REG_BIT_RTC_ALARM );
+    }
+    RWAIT = 0;
+}
+
+
+
+/* ========================================================
+ RTC �̃��[�h
+  ���W�X�^�́Asec,min,hour,week,day,month,year �̏�
+ ======================================================== */
+void rtc_buf_refresh(  )
+{
+    if( !rtc_lock )
+    {
+        rtc_lock = true;
+        RWAIT = 1;
+        while( !RWST )
+        {;}
+
+        memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, RTC_DATA_SIZE );
+        RWAIT = 0;
+//    renge_task_immed_add( tski_rtc_close );
+    }
+}
+
+
+
+/* ========================================================
+ RTC �̃��C�g
+  set_rtc_close �Ƒ΂Ŏg���ĉ������B
+  �����‚̓o�b�t�@�ɃR�s�[���邾���ŁA
+  ���ۂ�RTC�ɃZ�b�g����̂�set_rtc_close()�ł��B
+ ======================================================== */
+void set_rtc( u8 adrs, u8 data )
+{
+    if( !rtc_dirty )
+    {
+        rtc_dirty = true;
+        memcpy( rtc_work, &SEC, RTC_DATA_SIZE );
+//    renge_task_immed_add( tski_rtc_close );  // I2C�I�����ɍs��
+    }
+    rtc_work[adrs] = data;
+}
+
+
+
+/* ========================================================
+ �K�v�Ȃ�΁ARTC���W�X�^�̍X�V
+ ======================================================== */
+// task_status_immed tski_rtc_close(){
+void rtc_unlock(  )
+{
+    // ���[�h���b�N
+    rtc_lock = false;
+
+    // ���C�g���b�N
+    if( rtc_dirty )
+    {
+        rtc_dirty = false;
+        RWAIT = 1;
+        while( !RWST )
+        {;}
+        memcpy( &SEC, rtc_work, RTC_DATA_SIZE );
+        RWAIT = 0;
+    }
+
+    // �A���[���Z�b�g
+    if( rtc_alarm_dirty )
+    {
+        rtc_alarm_dirty = false;
+        WALE = 0;
+        ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN];
+        ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR];
+        WALE = 1;
+    }
+}
+
+
+
+
+
+/* ========================================================
+ RTC �V�X�e���`�b�N�^�C�}���荞�݃x�N�^
+  2^6/fXT�i1.953125 ms�j
+ ======================================================== */
+__interrupt void int_rtc_int(  )
+{
+//    renge_flg_interval ++;  // �C���N�������g/�f�N�������g���߂��g���̂� DI()�s�v
+    renge_flg_interval = 1;  // �C���N�������g/�f�N�������g���߂��g���̂� DI()�s�v
+}
+
diff --git a/tags/2.03_SDK-3.1/rtc.h b/tags/2.03_SDK-3.1/rtc.h
new file mode 100644
index 0000000..6b2d9f8
--- /dev/null
+++ b/tags/2.03_SDK-3.1/rtc.h
@@ -0,0 +1,21 @@
+#ifndef __rtc_h__
+#define __rtc_h__
+
+
+void RTC_init( void );
+void rtc_buf_refresh(  );
+void set_rtc( u8 adrs, u8 data );
+
+//task_status_immed tski_rtc_close();
+void rtc_unlock(  );
+
+// ------------------------------------
+#define RTC_32k_on()         { RCLOE0 = 1; }
+#define RTC_32k_off()        { RCLOE0 = 0; }
+
+
+// ------------------------------------
+extern bit rtc_alarm_dirty;
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/self_flash.c b/tags/2.03_SDK-3.1/self_flash.c
new file mode 100644
index 0000000..d1ff4dd
--- /dev/null
+++ b/tags/2.03_SDK-3.1/self_flash.c
@@ -0,0 +1,608 @@
+/* ========================================================
+  ���ȃA�b�v�f�[�^
+ ======================================================== */
+#ifndef _WIN32
+
+#pragma SFR
+#pragma di
+#pragma ei
+#pragma nop
+#pragma stop
+#pragma halt
+
+#endif
+
+#include "incs_loader.h"
+
+#include <fsl.h>
+#include "fsl_user.h"
+#include "i2c_ctr.h"
+
+#include "pool.h"
+#include "magic.h"
+
+#include "pm.h"
+
+// ========================================================
+const u8 fsl_fx_MHz_u08 = 8;
+const u8 fsl_low_voltage_u08 = 1;
+
+
+// ���ȃt���b�V���p�����[�^
+#define SAM_BLOCK_SIZE                 1024
+ // ��256�o�C�g�ȏ�͂܂Ƃ߂Ă����܂���B
+#define SELF_UPDATE_BUFF_SIZE          256
+#define SELF_UPDATE_SPLIT_WRITE_NUM    ( SAM_BLOCK_SIZE / SELF_UPDATE_BUFF_SIZE )
+#define SAM_WORD_SIZE                  4
+
+//                                    ���u���b�N�ԍ��i1�u���b�N��1kB�j
+#define INACTIVE_BOOTSECT_TOP          4
+#define FIRM_TOP                       8
+#define FIRM_SIZE                     12
+#define ALTERNATE_FIRMTOP             20
+
+
+#ifdef _MCU_BSR_
+#define ACKD       ACKD1
+#define ACKE       ACKE1
+#define COI        COI1
+#define IICAEN     IICA1EN
+#define IICAPR0    IICAPR10
+#define IICRSV     IICRSV1
+#define IICA       IICA1
+#define IICAIF     IICAIF1
+#define IICAMK     IICAMK1
+#define IICAPR1    IICAPR11
+#define IICCTL0    IICCTL01
+#define IICE       IICE1
+#define IICF       IICF1
+#define IICS       IICS1
+#define IICWH      IICWH1
+#define IICWL      IICWL1
+#define LREL       LREL1
+#define SPD        SPD1
+#define SPIE       SPIE1
+#define STCEN      STCEN1
+#define STD        STD1
+#define SVA        SVA1
+#define WREL       WREL1
+#define WTIM       WTIM1
+#endif
+
+#ifndef _WIN32
+#define LED_POW1 P1.5
+#define LED_PM_POW1 PM1.5
+#else
+#define LED_POW1	mcuRegP[ _P1_5 ]
+#define LED_PM_POW1 mcuRegPM[ _P1_5 ]
+#endif
+
+// ========================================================
+static void FSL_Open( void );
+static void FSL_Close( void );
+void     firm_restore(  );
+
+static err my_FSL_Init();
+static err firm_duplicate( u8 block_src, u8 block_dest );
+
+#ifdef _DBG_LED_PRINT_
+void alert( u8 );
+void led_print( u8 );
+#else
+# define alert( x )         ;
+# define led_print( x )     ;
+#endif
+
+
+// ========================================================
+extern uni_pool pool;
+
+
+// 0.D�ȍ~ �V�A�b�v�f�[�^����
+// �V�t�@�[���͑��v�H
+#define N_MGC_L   0x1FF6
+#define N_MGC_T   0x4FF6
+
+
+
+/* ========================================================
+  I2C�Ŏ�M���āA
+  �������݁A
+  �`�F�b�NOK�@���@�V�t�@�[���ɐ؂�ւ��čċN��
+  �@�@�@�@NG�@���@���i���j�t�@�[���ɖ߂��čċN��
+  �i���̊֐�����͖߂�܂���j
+ ======================================================== */
+void firm_update(  )
+{
+    u8      target_block;
+    u8      split_write_count;  // �u���b�N�ւ��܂��܏������ރJ�E���^
+
+    // �����ւ��O���� /////////////////////////////////////
+    my_FSL_Init();
+
+    /* �t�@�[���̃o�b�N�A�b�v
+    �J�n�A�h���X�A�������ݐ�̐擪�h�u���b�N�ԍ��h (�T�C�Y�� FIRM_SIZE)
+       0x2000 - 0x4FFF ��
+       0x5000 - 0x7FFF (�u���b�N 20 - 31) �ɃR�s�[
+     */
+    firm_duplicate( FIRM_TOP,
+                    ALTERNATE_FIRMTOP );
+
+    // �S�u���b�N�폜 /////////////////////////////////////
+    // �d���f�𔻒肷�邽�߁A�ŏ��ɑS�N���X�^��������
+    //�i�V�t�@�[�����������Ƃ���Ɏc���Ă�A�ȑO�̃t�@�[���̃t�b�^�����������j
+    for( target_block = INACTIVE_BOOTSECT_TOP;
+         target_block < ALTERNATE_FIRMTOP;
+         target_block ++ )
+    {
+        FSL_Erase( target_block );
+    }
+
+
+    // �����ւ� ///////////////////////////////////////////
+    // ���X�g�b�v�R���f�B�V����������܂ő�����
+    // ���I�������A�X�^�[�g�A�b�v���[�`���ɔ��
+    for( target_block = INACTIVE_BOOTSECT_TOP;
+         target_block < ALTERNATE_FIRMTOP;
+         target_block ++ )
+    {
+            u8      my_spd;
+
+/* ���łɏ����Ă���B�łȂ��ƒ��f���ꂽ�Ƃ��I�����Ă邩���ʏo���Ȃ�
+//          // �V�t�@�[���̈�폜
+//        FSL_Erase( target_block );
+*/
+        // ������������
+        for( split_write_count = 0;
+             split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM;
+             split_write_count ++ )
+        {
+            u8*     p_buffer = &pool.self_update_work[0];
+            u16     buff_written_size = 0;
+
+            WDT_Restart(  );
+
+            // I2C���珑�����݃f�[�^���o�b�t�@�ɂ��߂�
+            do
+            {
+                while( !IICAIF && !SPD )
+                {;}
+                my_spd = SPD;
+                IICAIF = 0;
+                *p_buffer = IICA;
+                WREL = 1;
+                p_buffer ++;
+                buff_written_size ++;
+            }
+            while( ( buff_written_size != SELF_UPDATE_BUFF_SIZE )
+                   && !SPD );
+
+            my_spd += SPD;
+
+            // ��������
+            // �Ōゾ�ƁA�S�~���p�f�B���O���邪�ʂɂ��܂�Ȃ�
+            if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOCK_SIZE
+                                         + split_write_count * SELF_UPDATE_BUFF_SIZE ),
+                           ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE / SAM_WORD_SIZE ) )
+
+                != FSL_OK )
+            {
+                alert(1);
+                // �������݌�̃`�F�b�N�G���[
+                // ���X�g�A
+                firm_duplicate( ALTERNATE_FIRMTOP, FIRM_TOP );
+                FSL_ForceReset(); // ���Z�b�g
+                // FSL_SwapBootCluster(  );  // �u�[�g�X���b�v�u�����Ɂv�ċN�����ďo���Ȃ��炵��
+                // �߂��Ă��Ȃ� //
+            }
+
+            if( my_spd != 0 )
+            {
+                break;
+            }
+        }
+
+        // 1�u���b�N�������݊����B�����x���t�@�C���s��
+        if( FSL_IVerify( target_block ) != FSL_OK ){
+            alert(2);
+            // �ēx�������������� �x���t�@�C���J��Ԃ���������_���ł���... /// �ď������݂��ׂ��H
+            // ���X�g�A
+            firm_duplicate( ALTERNATE_FIRMTOP, FIRM_TOP );
+            FSL_ForceReset(); // ���Z�b�g
+            // FSL_SwapBootCluster(  );  // �u�[�g�X���b�v�u�����Ɂv�ċN�����ďo���Ȃ��炵��
+            // �߂��Ă��Ȃ� //
+        }
+
+        if( my_spd != 0 )
+        {
+            break;
+        }
+    }
+
+    LREL = 1;
+
+    // �������񂾃t�@�[���̃`�F�b�N //
+    {
+        u8      i;
+        u8      comp = 0;
+
+        // ���[�_�[�̃}�W�b�N�ƁA�{���̖����̃}�W�b�N�͓������m�F
+        for( i = 0; i < sizeof( __TIME__ ); i++ )
+        {
+            comp += (u8)(( (*( __far u8 * ) ( N_MGC_L + i )) == (*( u8 * ) ( N_MGC_T + i ) )) ? 0 : 1);
+        }
+        if( *( __far u8 * )( N_MGC_L +2 ) != ':' )  // �����ς̂܂�
+        {
+            comp ++;
+        }
+
+        if( comp == 0 )
+        {
+            // OK!
+            FSL_InvertBootFlag(  );
+            FSL_SwapBootCluster(  );  // ���Z�b�g�����ɓ�����BFSL_Close�͕s�v
+        }
+        else
+        {
+            // �f�[�^(�}�W�b�N�i���o�[�������ĂȂ�)�G���[
+            // ���X�g�A
+            alert(3);
+
+            firm_duplicate( ALTERNATE_FIRMTOP, FIRM_TOP );
+            FSL_ForceReset(); // ���Z�b�g
+            // FSL_SwapBootCluster(  );  // �u�[�g�X���b�v�u�����Ɂv�ċN�����ďo���Ȃ��炵��
+        }
+        // �߂��Ă��Ȃ� //
+    }
+}
+
+
+
+
+/* ========================================================
+  �@���t�@�[�����o�b�N�A�b�v�̈悩�烊�X�g�A���܂��B
+  �@�`�F�b�N��A�Ō�̍Ō�Ńu�[�g�X���b�v����̂ŁA
+�@�����ł̓u�[�g�X���b�v�͕s�v�ł��B
+
+ ======================================================== */
+void firm_restore(  )
+{
+    DBG_LED_on;
+    LED_PM_POW1 = 0;
+
+    // �o�b�N�A�b�v�͐���H //
+    {
+        u16      i;
+        u8      comp = 0;
+
+        for( i = 0; i < sizeof( __TIME__ ); i++ )      // sizeof( __TIME__ ) = 8 �炵
+        {
+            comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( u8 * )( MGC_HEAD_BKUP + i ) ) ? 0 : 1;
+            comp += ( *( u8 * )( MGC_HEAD_BKUP + i ) == *( u8 * )( MGC_FOOT_BKUP + i ) ) ? 0 : 1;
+        }
+        if( *( u8 * )( MGC_FOOT_BKUP ) == 0xFF )
+        {
+            comp ++;
+        }
+
+        if( comp != 0 )
+        {
+            // �o�b�N�A�b�v�̈����ꂽ...
+            comp = 0;
+
+            // 3.3V���オ��Ȃ��ƍ���
+            EI(  );
+            iic_mcu_start(  );
+            RESET2_ast;
+            FCRAM_RST_ast;
+            GYRO_DISABLE();
+            PM_LDSW_on();
+            wait_ms( 1 + DELAY_PM_TW_PWUP );
+            PM_VDD_on(  );
+
+            while(1)
+            {
+                WDT_Restart();
+
+                {
+                    // ��LED �s�R�s�R
+                    comp++;
+                    LED_POW1 = ( comp == 1 || comp == 3 )? 1: 0;
+                    if( comp == 8 )
+                    {
+                        comp = 0;
+                    }
+                }
+
+                {
+                    // �d���{�^���œd��off
+                    static u8 sw_hold_count;
+
+                    if( !SW_POW_n_RAW )
+                    {
+                        sw_hold_count++;
+                    }
+                    else
+                    {
+                        sw_hold_count = 0;
+                    }
+
+                    if( sw_hold_count > 16 )
+                    {
+                        sw_hold_count = 0;
+                        // �d��off
+                        PM_LDSW_off(  );
+                        break;
+                    }
+                }
+
+                // �E�F�C�g
+                for( i = 1; i != 0; i++ )
+                {
+                    NOP();
+                    NOP();
+                    NOP();
+                    NOP();
+                }
+            }
+            {
+                // �ǁA�ǂ����悤�c�B
+
+                KRM = ( KR_SW_POW );    // Mask �ł͂Ȃ��AMode�Ȃ̂��������B����킵��
+                MK0 = 0xFFFF;
+                MK1 = ~( INT_MSK1_KR );
+                MK2L = 0xFF;
+
+                // PU5 ���̂܂�
+                PU7  = bits8(0,0,0,0, 1,0,0,0);   // PWSWI
+                PU20 = bits8(0,0,0,0, 0,0,0,0);;        // SW_HOME ��~
+
+                STOP(  );
+
+                mcu_wdt_reset;
+            }
+        }
+    }
+
+
+    if( my_FSL_Init() != ERR_SUCCESS ){
+        alert(1);
+    }
+
+    /* �t�@�[���̃��X�g�A
+       0x4800 - 0x7FFF (�u���b�N 18 - 27) ����
+       0x2000 - 0x47FF (�u���b�N  8 - 17) �փR�s�[
+     */
+    if( firm_duplicate( ALTERNATE_FIRMTOP, FIRM_TOP ) != ERR_SUCCESS )
+    {
+        alert(2);
+    }
+    DBG_LED_off;
+
+    // todo ���X�g�A���s������ALED���������Ƃ������āA�T�[�r�X����ɂ��Ă��炤�H
+
+/*
+// ���u�[�g
+    if( FSL_InvertBootFlag() != ERR_SUCCESS )
+    {
+        alert(3);
+    }
+*/
+    FSL_ForceReset(); // ���Z�b�g
+    // FSL_SwapBootCluster(  );  // �u�[�g�X���b�v�u�����Ɂv�ċN�����ďo���Ȃ��炵��
+}
+
+
+
+// ========================================================
+static void FSL_Open( void )
+{
+    /* save the configuration of the interrupt controller and set */
+#ifdef   FSL_INT_BACKUP
+    fsl_MK0L_bak_u08 = MK0L;    /* if (interrupt backup required)                 */
+    fsl_MK0H_bak_u08 = MK0H;    /* {                                              */
+    fsl_MK1L_bak_u08 = MK1L;    /*                                                */
+    fsl_MK1H_bak_u08 = MK1H;    /*        save interrupt controller               */
+    fsl_MK2L_bak_u08 = MK2L;    /*        configuration                           */
+    fsl_MK2H_bak_u08 = MK2H;    /*                                                */
+    MK0L = FSL_MK0L_MASK;       /*                                                */
+    MK0H = FSL_MK0H_MASK;       /*                                                */
+    MK1L = FSL_MK1L_MASK;       /*        prepare interrupt controller            */
+    MK1H = FSL_MK1H_MASK;       /*        for selfprogramming                     */
+    MK2L = FSL_MK2L_MASK;       /*                                                */
+    MK2H = FSL_MK2H_MASK;       /* }                                              */
+#endif
+
+    while( DST1 ){;}            // DMA��~
+    DEN1 = 0;
+
+    MK0 = 0xFFFF;
+    MK1 = 0xFFFF;
+    MK2 = 0xFFFF;
+/*
+    LVIM = bits8(0,0,0,0, 0,0,1,0);
+    LVIS = bits8(0,0,0,0, 1,0,0,0);
+    LVIM = bits8(1,0,0,0, 0,0,1,0);
+*/
+    FSL_FLMD0_HIGH;             // �t���b�V�������ւ�����
+}
+
+
+
+/*----------------------------------------------------------------------------------------------*/
+/* leave the "user room" and restore previous conditions                                        */
+/*----------------------------------------------------------------------------------------------*/
+static void FSL_Close( void )
+{
+    // ������n���H
+
+    FSL_FLMD0_LOW;              // �t���b�V�����C�g�v���e�N�g
+
+#ifdef   FSL_INT_BACKUP
+    MK0L = fsl_MK0L_bak_u08;    /*   do{                                          */
+    MK0H = fsl_MK0H_bak_u08;    /*        restore interrupt controller            */
+    MK1L = fsl_MK1L_bak_u08;    /*        configuration                           */
+    MK1H = fsl_MK1H_bak_u08;    /*                                                */
+    MK2L = fsl_MK2L_bak_u08;    /*                                                */
+    MK2H = fsl_MK2H_bak_u08;    /*   }                                            */
+#endif
+}
+
+
+
+/* ========================================================
+�@�}�C�R�����Ńt�@�[�����R�s�[���܂��B
+  __far u8 * p_rom  �R�s�[���̐擪�A�h���X
+  block_dest        �R�s�[��̐擪�u���b�N
+
+  �R�s�[��ɏ�����悤��my_FSL_Init�����炩���ߎ��s����K�v������܂��B
+ ======================================================== */
+//static err firm_duplicate( __far u8 * p_rom,
+//                           u8 block_dest )
+static err firm_duplicate( u8 block_src,
+                           u8 block_dest )
+{
+    u8      target_block;
+    u8      split_write_count;  // �u���b�N�ւ��܂��܏������ރJ�E���^
+    __far u8* p_src = ( __far u8* )( block_src * 0x400 );
+    u8      retry_error;
+
+    led_print(1);
+
+    // �������ݐ�u���b�N�̐������J��Ԃ�
+    for( target_block = block_dest;
+         target_block < ( block_dest + FIRM_SIZE );
+         target_block ++ )
+    {
+        led_print(2);
+        WDT_Restart(  );
+        // �u���b�N����
+        retry_error = 5 + 1;
+        while( FSL_BlankCheck( target_block ) != FSL_OK )
+        {
+            led_print(3);
+            FSL_Erase( target_block );
+            if( -- retry_error == 0 )
+            {
+                // �t���b�V�������H
+                FSL_Close(  );
+                return ( ERR_ERR );  // ���Z�b�g�����A�����݂�@�ǂ��Ȃ邩�m���
+            }
+        }
+
+        led_print(4);
+        // �����������ݕ��J��Ԃ�
+        for( split_write_count = 0;
+             split_write_count < SELF_UPDATE_SPLIT_WRITE_NUM;
+             split_write_count ++ )
+        {
+            u16     buff_written_size;
+            u8*     p_buff;
+
+            // �������݃f�[�^���o�b�t�@�ɂ��߂�
+            buff_written_size = 0;
+            p_buff = &pool.self_update_work[0];
+            do
+            {
+                *p_buff = *p_src;
+                p_src ++;
+                p_buff ++;
+                buff_written_size ++;
+            }
+            while( buff_written_size != SELF_UPDATE_BUFF_SIZE );
+
+            // ��������
+            if( FSL_Write( ( fsl_u32 ) ( target_block * SAM_BLOCK_SIZE
+                                         + split_write_count * SELF_UPDATE_BUFF_SIZE ),
+                           ( fsl_u08 ) ( SELF_UPDATE_BUFF_SIZE / SAM_WORD_SIZE ) )
+                != FSL_OK )
+            {
+                // ���J�o���̓��u�[�g�� //
+                FSL_Close(  );
+                led_print(5);
+//                while(1){}
+                return ( ERR_ERR );
+            }
+        }
+        led_print(6);
+
+        // 1�u���b�N�������݊����B�����d���`�F�b�N���s��
+        while( FSL_IVerify( target_block ) != FSL_OK )
+        {
+            // ���J�o���̓��u�[�g�� //
+            led_print(7);
+            return ( ERR_ERR );
+        }
+    }
+    return( ERR_SUCCESS );
+
+}
+
+
+
+/* ========================================================
+ ======================================================== */
+static err my_FSL_Init()
+{
+    u8 rv;
+
+    RTCE = 0;
+
+    // �����ւ��O���� //
+    DI(  );
+    FSL_Open(  );               // ���荞�݋֎~�Ȃ�
+
+    FSL_Init( &pool.self_update_work[0] );      // ���C�u�����������B���荞�ݒ��f�l������
+    rv = FSL_ModeCheck(  );   // ���C�g�v���e�N�g�`�F�b�N�B���s���邱�Ƃ��l������
+
+    return( (err)rv );
+}
+
+
+task_status_immed tski_mcu_reset()
+{
+    // ���ʂɍċN��
+    my_FSL_Init();
+
+    FSL_ForceReset();           // ���Z�b�g
+    FSL_Close(  );
+
+    // �ی��H //
+    mcu_wdt_reset;
+    return( ERR_SUCCESS );      // no reach
+}
+
+
+#ifdef _DBG_LED_PRINT_
+// P1.5 = led_pow_red_old
+void alert( u8 num )
+{
+    u8 i;
+
+    while(1)
+    {
+        WDT_Restart();
+        LED_POW1 = 1;
+        for( i = 0; i < num; i++ )
+        {
+            DBG_LED_on;
+            DBG_LED_off;
+        }
+        LED_POW1 = 0;
+    }
+}
+
+
+void led_print( u8 num )
+{
+    u8 i;
+
+    DBG_LED_on;
+    for( i = 0; i < num; i++ )
+    {
+        LED_POW1 = 1;
+        LED_POW1 = 0;
+    }
+    DBG_LED_off;
+}
+#endif
diff --git a/tags/2.03_SDK-3.1/self_flash.h b/tags/2.03_SDK-3.1/self_flash.h
new file mode 100644
index 0000000..768565e
--- /dev/null
+++ b/tags/2.03_SDK-3.1/self_flash.h
@@ -0,0 +1,9 @@
+#ifndef _self_flash_h_
+#define _self_flash_h_
+
+
+void firm_update();
+
+
+#endif
+
diff --git a/tags/2.03_SDK-3.1/sw.c b/tags/2.03_SDK-3.1/sw.c
new file mode 100644
index 0000000..5fd74ed
--- /dev/null
+++ b/tags/2.03_SDK-3.1/sw.c
@@ -0,0 +1,188 @@
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+
+#endif
+
+#include "incs.h"
+
+#include "i2c_twl.h"
+#include "i2c_ctr.h"
+#include "led.h"
+#include "pm.h"
+#include "rtc.h"
+#include "sw.h"
+
+
+//=========================================================
+/*
+ vreg_ctr����ǂ݂����̂Ńw�b�_��
+#define INTERVAL_TSK_SW
+#define CLICK_THRESHOLD
+
+#define HOLD_THREASHOLD
+#define FORCEOFF_THREASHOLD
+*/
+#define TIME_MUKAN					( u8)(   300 / INTERVAL_TSK_SW )
+#define TIME_MUKAN_PWSW_RED_TRIAL	(u16)( 15000 / INTERVAL_TSK_SW )	// ���V��Ahome�}�X�N����
+
+//=========================================================
+u16     SW_pow_count;
+bit     SW_pow_mask;
+
+static u8	SW_home_count, SW_wifi_count, SW_home_count_rel;
+static u8	sw_wifi_mukan_time;
+
+u16		off_timeout_timer;
+
+static u16	sw_pwsw_mukan_time;
+
+//=========================================================
+// ���������Ԃ𐔂���B�������ςȂ��ł�0�ɖ߂�Ȃ�
+// mask����0�̎��́A��x�����܂Ŗ�������
+#define count_sw_n( sw, counter, mask )   \
+  {                                       \
+    if( sw ){                             \
+      mask = 0;                           \
+      counter = 0;                        \
+    }else{                                \
+      if( mask != 0 ){                    \
+        counter = 0;                      \
+      }else{                              \
+        counter ++;                       \
+        if( counter == 0 ) counter = -1;  \
+      }                                   \
+    }                                     \
+  }
+
+
+#define chk_clicked( button, count, irq_bit_name )    \
+    if( !button )                                     \
+    {                                                 \
+        if( count < CLICK_THRESHOLD )                 \
+        {                                             \
+            count ++;                                 \
+			if( count == CLICK_THRESHOLD )            \
+			{                                         \
+	            count ++;                             \
+				set_irq( VREG_C_IRQ0, irq_bit_name ); \
+			}                                         \
+        }                                             \
+    }                                                 \
+    else                                              \
+    {                                                 \
+        count = 0;                                    \
+    }                                             
+
+
+
+/* ========================================================
+ �X�C�b�`�̊Ď�
+  �@�`���^�����O���͂˂���A��������A�������g���K�Ȃǂ̌��o�Ȃ�
+ ======================================================== */
+void tsk_sw(  )
+{
+    static u8 task_interval;
+
+	if( system_status.pwr_state == OFF_TRIG )
+    {
+        SW_pow_count = 0;  // �d�������ɔ����ăN���A
+//		task_interval = 0;
+    }
+
+	if( system_status.pwr_state != ON_CHECK )  // ���莞��(PWSW_POWON_TIME)���Z���̂Ńv���X�P�[�������@�łȂ��ƃ`���^���������܂肫���Ȃ�
+	{
+		if( task_interval != 0 )
+		{
+			task_interval--;
+			return;
+			// �����܂�
+		}
+
+		task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TICK ) -1;	// �v���X�P�[������Ɏg���Ă܂��ˁc
+																	// -1�̓|�X�g�f�N�������g�̂��߂̒���
+	}
+
+    // 8ms ���ɂ��܂�
+    switch ( system_status.pwr_state )
+    {
+    case ( ON ):
+    case ( SLEEP ):
+    case ( OFF ):
+    case ( ON_CHECK ):
+		// ���@�̏ꍇ
+        if( ! system_status.taikendai )
+        {
+            
+            // �d���X�C�b�`�̊Ď� //
+            if( SW_pow_count == ( TIME_PWSW_CLICK ) )  // �N���b�N���Ԃɓ��B
+            {
+                set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK );
+            }
+            else if( SW_pow_count == ( HOLD_THREASHOLD ) )  // �������ɓ��B
+            {
+                set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD );
+                if( off_timeout_timer == 0 ) // �����d���f�J�E���g�_�E���J�n�A���x���������Ȃ��悤�ɁB
+                {
+                    off_timeout_timer = vreg_ctr[ VREG_C_OFF_DELAY ] * 16;
+                }
+            }
+
+            if( off_timeout_timer != 0 )   // ���������荞�݌�A�^�C���A�E�g�ŋ����I�t�B
+            {
+                off_timeout_timer --;
+                if( off_timeout_timer == 0 )
+                {
+                    force_off = true;
+                }
+            }
+        
+        }else{
+			// �X�^���h�A�������V��
+            // �d���X�C�b�`�̊Ď� //
+            if( SW_pow_count == ( TIME_PWSW_CLICK ) )
+            {
+                if( sw_pwsw_mukan_time == 0 )
+                {
+                    set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK );
+                    // ����ȃ^�C�~���O��PWSW��������HOME���j���[�ɓ���Ă��܂��̂�������邽�߂̃}�X�N�^�C�}�[
+                    sw_pwsw_mukan_time = TIME_MUKAN_PWSW_RED_TRIAL;
+                }
+            }
+            else if( SW_pow_count == ( HOLD_THREASHOLD ) )
+            {
+                force_off = true;
+            }
+            
+            if( sw_pwsw_mukan_time != 0 )
+            {
+                sw_pwsw_mukan_time--;
+            }
+        }
+
+        count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask );        // �{�^���������Ԃ̃J�E���g
+
+        // HOME sw //
+        chk_clicked(  SW_HOME_n, SW_home_count,     REG_BIT_SW_HOME_CLICK );
+        chk_clicked( !SW_HOME_n, SW_home_count_rel, REG_BIT_SW_HOME_RELEASE );
+                
+        // wifi sw //
+        /// �ň��Ȏ����Ȃ̂͂킩���Ă��邪�A�s��ɏo�Ă��܂����s�ǃX�C�b�`���~������
+        if( sw_wifi_mukan_time != 0 )
+        {
+            sw_wifi_mukan_time--;
+        }
+        else
+        {
+            chk_clicked( SW_WIFI_n, SW_wifi_count, REG_BIT_SW_WIFI_CLICK );
+            if( SW_wifi_count == CLICK_THRESHOLD +1 ) // ���������蔭���I
+            {
+                sw_wifi_mukan_time = TIME_MUKAN;
+            }
+        }
+    }
+}
+
diff --git a/tags/2.03_SDK-3.1/sw.h b/tags/2.03_SDK-3.1/sw.h
new file mode 100644
index 0000000..abe9715
--- /dev/null
+++ b/tags/2.03_SDK-3.1/sw.h
@@ -0,0 +1,20 @@
+#ifndef _sw_
+#define _sw_
+
+#include "config.h"
+
+extern u16     SW_pow_count;
+extern bit     SW_pow_mask;
+
+#define INTERVAL_TSK_SW  8
+#define CLICK_THRESHOLD  5
+
+#define HOLD_THREASHOLD     (u16)( 3000 /INTERVAL_TSK_SW )
+#define TIME_PWSW_CLICK     (u8)(   220 /INTERVAL_TSK_SW )
+#define FORCEOFF_THREASHOLD (u8)( 12000 /INTERVAL_TSK_SW /16 )
+
+
+extern u16 off_timeout_timer;
+#define clear_pow_off_countdown(){ off_timeout_timer = 0; force_off = false; }
+
+#endif
diff --git a/tags/2.03_SDK-3.1/task_debug.c b/tags/2.03_SDK-3.1/task_debug.c
new file mode 100644
index 0000000..fc3ab4f
--- /dev/null
+++ b/tags/2.03_SDK-3.1/task_debug.c
@@ -0,0 +1,112 @@
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+
+#endif
+
+#include "incs_loader.h"
+//#include "incs.h"
+#include "renge\renge.h"
+#include "pm.h"
+#include "accero.h"
+
+
+/* ========================================================
+ ======================================================== */
+
+// 7�Z�O 4�o�C�g��
+# define IIC_SLA_DBG_MONITOR   0x44
+
+
+#if 0 // �f�o�b�O���j�^�p�^�X�N
+
+���ӁI�@�^�X�N���X�g������O���Ă܂��̂ŁA�g���Ȃ畜�������ĉ������I
+
+void tsk_debug(  )
+{
+//    u8      temp;
+
+    /*
+    if( system_status.pwr_state == ON_TRIG ){
+    {
+    static u8 count = 0;
+    // �f�o�b�OLED�i8bit�j�̏�����
+       temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO );
+       count ++;
+       iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, count );
+       iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count );
+    }
+    }
+     */
+
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VREG_C_IRQ1 ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_C_SND_VOL ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_3D ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VREG_C_ACC_ZH ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VREG_C_3D ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VREG_C_SND_VOL ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VREG_C_STATUS ] );
+//    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VREG_C_ACC_ZH ] );
+
+    /*
+    {
+        u8      str[4];
+        
+        if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) )
+        {
+            str[3] = vreg_ctr[ VREG_C_FREE0 ];
+            str[2] = vreg_ctr[ VREG_C_FREE1 ];
+            str[1] = vreg_ctr[ VREG_C_STATUS ];
+            str[0] = vreg_ctr[ VREG_C_RTC_SEC ];
+
+            str[3] = vreg_ctr[ VREG_C_SND_VOL ];
+            str[2] = vreg_ctr[ VREG_C_3D ];
+            str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ];
+            str[0] = SEC;
+            iic_mcu_write( IIC_SLA_DBG_MONITOR, 0x03, 4, &str );
+        }
+    }
+     */
+}
+
+#endif
+
+
+#if 0 // �^�X�N�ЂȌ`
+/* ========================================================
+ �^�X�N�ЂȌ`
+ ======================================================== */
+task_interval tsk_hina(  )
+{
+    switch ( system_status.pwr_state )
+    {
+    case ON_CHECK:
+    case ON_TRIG:
+    case ON:
+    case SLEEP:
+    case OFF_TRIG:
+    default:
+    }
+
+    return;  // �� tic �Ă΂�邱�ƂɂȂ�܂�
+}
+
+
+// �|�C���^�ʼn������炤�̂͊댯�ȋC�����Ă���
+/* ���̂悤�Ɏg��
+      renge_task_immed_add( �^�X�N�֐��ւ̃|�C���^ );
+*/
+task_status_immed tski_hina( u8 * arg )
+{
+    return ( ERR_FINISED );
+    // ERR_FINISED �^�X�N���폜
+    // ERR_CONTINUE ���ɂȂ񂩊��荞�݂Ȃ�A���[�U�[����Ȃ�A�V�X�e���`�b�N��
+    //             �����Ƃ��ɍēx���s
+}
+
+
+#endif
diff --git a/tags/2.03_SDK-3.1/task_misc.c b/tags/2.03_SDK-3.1/task_misc.c
new file mode 100644
index 0000000..d50d289
--- /dev/null
+++ b/tags/2.03_SDK-3.1/task_misc.c
@@ -0,0 +1,399 @@
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+
+#endif
+
+#include "incs.h"
+#include "renge\renge.h"
+#include "pm.h"
+
+#include "accero.h"
+#include "adc.h"
+#include "i2c_mcu.h"
+#include "led.h"
+#include "vreg_twl.h"
+
+
+
+#ifdef _MCU_BSR_
+#define ACKD       ACKD1
+#define ACKE       ACKE1
+#define COI        COI1
+#define IICAEN     IICA1EN
+#define IICRSV     IICRSV1
+#define IICA       IICA1
+#define IICAIF     IICAIF1
+#define IICAMK     IICAMK1
+#define IICAPR0    IICAPR11
+#define IICAPR1    IICAPR01
+#define IICCTL0    IICCTL10
+#define IICE       IICE1
+#define IICF       IICF1
+#define IICS       IICS1
+#define IICWH      IICWH1
+#define IICWL      IICWL1
+#define LREL       LREL1
+#define SPD        SPD1
+#define SPIE       SPIE1
+#define STCEN      STCEN1
+#define STD        STD1
+#define SVA        SVA1
+#define WREL       WREL1
+#define WTIM       WTIM1
+#define TRC        TRC1
+#define SMC        SMC1
+#define DFC        DFC1
+#endif
+
+// ========================================================
+extern void f();
+
+
+// ========================================================
+bit twl_ver_read;	// twl home menu��ver��ǂ񂾂�݊��J�[�l���Ɋ��荞�݂����邽��
+bit going_to_sleep; // SoC����Asleep�ɓ���ʒm�����炤�Bslp_i ��H���Ԃ�0�ɂȂ��
+					//  �X���[�v���畜�A�ł��Ȃ��Ȃ�̂�h������
+
+
+// �����e�X�g�p
+bit reserve_pedo_increnent;  
+
+
+// ========================================================
+static void update_LED_3D();
+static void check_twl_vol_irq();
+extern void DI_wt_chk();
+
+
+
+/* ========================================================
+ �X�e�[�^�X���W�X�^�Ȃ�
+ ======================================================== */
+void tsk_misc(  )
+{
+    /* ========================================================
+       �����x�Z���T���荞�݃s�����I���W�i���}�C�R���ɂ͖����̂�
+       �|�[�����O����B
+       �����v�p
+       BSR�}�C�R����accero.c�Ŋ��荞�݃��[�`������^�X�N�o�^���܂��B
+       ======================================================== */
+    // ���荞�݂̎�肱�ڂ��H
+    if( ACC_VALID )
+    {
+        if( renge_task_immed_add( tski_cbk_accero ) == ERR_SUCCESS ){
+            // dbg_nop();
+        }
+    }
+
+    if( system_status.pwr_state == ON )
+    {
+        /* ========================================================
+            PM�݊����W�X�^�ւ̏�������
+            �|�[�����O�������ĂȂ��B���荞�݁H
+            ======================================================== */
+        if( !PM_IRQ_n )
+		{
+            renge_task_immed_add( tski_ntr_pmic_comm );
+            // dbg_nop();
+        }
+
+        /* ========================================================
+            TWL�����`���[���N���������Ƃ�CTR���m�肽���炵��
+            ======================================================== */
+        if( twl_ver_read )
+        {
+            twl_ver_read = false;
+            set_irq( VREG_C_IRQ2, REG_BIT_TWL_VER_READ );
+        }
+
+		// TWL �̉��ʕω����荞�݃`�F�b�N //
+		check_twl_vol_irq();
+	}
+
+	// 3D �����v�X�V //
+	update_LED_3D();
+
+	if( reserve_pedo_increnent )
+	{
+		reserve_pedo_increnent = 0;
+		hosu_increment_if_necessary();
+	}
+
+#ifdef _ENABLE_PRESS_SEL_TO_WDT_
+	if( system_status.pwr_state == ON )
+	{
+		static u16 timer;
+		if( !SW_SEL_n )
+		{
+			timer += 1;
+			if( timer == 2000 )
+			{
+				DI();
+				timer = 0;
+				while(1)
+				{
+					NOP();	// ���̂���WDT����������
+				}
+			}
+		}
+	}
+#endif
+
+    //. �X�^�b�N�e�X�g
+//    f();
+}
+
+
+
+/* ========================================================
+    TWL��Vol�������̂ƁA�X���C�_�̑��삪�o�b�e�B���O�����
+    �s�������N���鎖������A�����h��
+        TWL�ł�8�ʏ펞�A�����{�^����8�i�K�������B����ɍ��킹�Ċ��荞�݂���ꂽ��
+    ======================================================== */
+void check_twl_vol_irq()
+{
+	static u8 vol_level_twl_sent;
+    static u8 mabiki;
+
+    if( !is_TWL )
+	{
+		return;
+		// �����܂�
+	}
+
+    if( mabiki != 0 )
+    {
+        mabiki--;
+		return;
+		// �����܂�
+	}
+
+	mabiki = 9;  // 1�t���[���͊J����
+    if( vol_level_twl != vol_level_twl_sent )
+    {
+		vol_level_twl_sent = vol_level_twl;
+        set_irq( VREG_C_IRQ2, REG_BIT_SLIDE_VOL_ACROSS_TWL_BOUNDARY );
+    }
+}
+
+
+
+// 3D_LED /////////////////////////////////////
+void update_LED_3D()
+{
+    if( system_status.pwr_state != ON )
+    {
+        LED_duty_3d = 0;
+		return;
+		// �����܂� //
+    }
+
+    if( vreg_ctr[VREG_C_LED_3D] == LED_3D_ILM_OFF )
+    {
+        if( LED_duty_3d != 0 )
+        {
+            LED_duty_3d --;
+        }
+    }
+    else
+    {
+        if( LED_duty_3d != vreg_ctr[VREG_C_LED_BRIGHT] )
+        {
+            if( LED_duty_3d < vreg_ctr[VREG_C_LED_BRIGHT] )
+            {
+            	LED_duty_3d ++;
+        	}
+        	else
+        	{
+        		LED_duty_3d --;
+        	}
+        }
+    }
+}
+
+
+
+/* ========================================================
+ ����N���^�X�N
+ ======================================================== */
+
+/* ========================================================
+  COMMAND���W�X�^�ւ̏�������
+�@  0�Ȃ�Ă΂�܂���B�P�A�s�v
+ ======================================================== */
+task_status_immed tski_do_command0(  )
+{
+    u8 temp_command;
+
+	// command0 �{�̓d���Ȃ�
+	DI_wt_chk();
+    temp_command = vreg_ctr[VREG_C_COMMAND0];
+    vreg_ctr[VREG_C_COMMAND0] = 0;
+	EI();
+
+    if( temp_command & REG_BIT_GOING_TO_SLEEP )
+    {
+        going_to_sleep = true;
+    }
+
+    if( ( temp_command & ( REG_BIT_OFF_REQ | REG_BIT_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) != 0x00 )
+    {
+        if( temp_command & REG_BIT_OFF_REQ )
+        {
+            system_status.pwr_state = OFF_TRIG;
+        }
+        else
+        {
+            if( temp_command & REG_BIT_RESET1_REQ )
+            {
+                PM_reset_ast(  );
+                RESET2_ast;
+                FCRAM_RST_ast;
+            }
+            if( temp_command & REG_BIT_RESET2_REQ )
+            {
+                RESET2_ast;
+                if( vreg_twl[ REG_TWL_INT_ADRS_MODE ] == 0 )
+                {
+                    FCRAM_RST_ast;         // twl��ntr���[�h�œ��삵�Ă�
+                }
+                // TWL���[�h����DS���[�h�ւ̐؂�ւ����Ƀ��Z�b�g�����
+                // IRQ���ǂ܂�Ȃ��ꍇ������̂�TWL���W�X�^������������
+                vreg_twl_init();
+            }
+            if( temp_command & REG_BIT_FCRAM_RESET_REQ )
+            {
+                FCRAM_RST_ast;
+            }
+            wait_ms( 5 );	// ���ԉ҂�
+            FCRAM_RST_neg;
+            PM_reset_neg();
+            RESET2_neg;
+
+            // CODEC �s�背�W�X�^������ //
+            codec_reg_init();
+        }
+    }
+/*
+    �X���[�v�v������ɓd��OFF�E���Z�b�g�R�}���h�͗��܂�
+    if( vreg_ctr[VREG_C_COMMAND0] != 0 )
+    {
+        return ( ERR_CONTINUE );
+    }
+*/
+    return ( ERR_FINISED );
+}
+
+
+
+/* �f�o�b�O�E�����e�X�g�p ============================== */
+u16 _dbg_rcomp;
+extern u8 raw_adc_temperature;
+
+extern u8 iic_burst_state;
+extern bit temp_zone_charge_disable;
+extern bit bt_authorized;
+
+
+/* ========================================================
+�@�f�o�b�O�p�ɂ��낢��ǂ�ł��܂��B
+�@�Ԓl�̓f�[�^���̂���
+ �o�Ă��鏇��́A
+ 1) �v���b�g�t�H�[��
+ 2) PMIC �o�[�W����
+ 3) �d�r���[�J�[
+ 4) �K�X�Q�[�W�o�[�W����
+ 5)        �V
+ 6) ( rcomp & 0xFF )
+ 7) raw_adc_temperature
+ 8) ( !temp_zone_charge_disable | ( bt_authorized << 1 ) )
+ 9) ���m�点LED�̓t���J���[�H
+ 10) system_status.family
+  ======================================================== */
+
+#define KOUMOKU 19
+
+static u8 infos_bits[2];
+static u8 infos_temp[5];
+
+static const u8 *infos_table[] = {
+    &infos_temp[0],               /* 0 */
+    &pmic_version,
+    (u8*)&battery_manufacturer,
+    &mgic_version[0],
+    &mgic_version[1],
+    &infos_temp[1],               /* 5 */
+    &raw_adc_temperature,
+    &infos_temp[2],
+    &infos_temp[3],
+    (u8*)&system_status.family,
+//        LED_pow_red,           /* 10 */
+    &infos_bits[0],
+    (u8*)&LED_duty_pow_blu,
+    (u8*)&LED_duty_3d,
+    (u8*)&LED_duty_notify_red,
+    (u8*)&LED_duty_notify_grn,
+    (u8*)&LED_duty_notify_blu,   /* 15 */
+    &infos_bits[1],
+//        &LED_CAM,
+    (u8*)&LED_duty_WiFi,
+    &infos_temp[4]                /* 18 */
+    /* ���ڑ����Ƃ��� KOUMOKU �ɒ��� */
+};
+
+	u8 extinfo_read(void)
+{
+	u8 ret = 0xFF;
+    
+    /*
+     * temp�͌v�Z�������K�v�ȃf�[�^�B�������ɗ]�T���Ȃ��̂Ōv�Z���K�v��
+     * �ϐ��́A�v/�s�v�Ɋւ�炸�v�Z����|���V�[
+     */
+
+    if( iic_burst_state < KOUMOKU )
+    {
+        infos_temp[0] = system_status.captureBox? MODEL_CAPTURE_BOX
+            : ( system_status.is_dev? MODEL_ISBAKO: (u8)system_status.model );
+        infos_temp[1] = (u8)( _dbg_rcomp & 0xFF ); 
+        infos_temp[2] = ( !temp_zone_charge_disable | ( bt_authorized << 1 ) ); 
+        infos_temp[3] = 1;            /* �d�l�ύX�ɂ��1�Œ�ɂȂ��� */
+        infos_temp[4] = 0
+//            | ( PM_EXTDC_n  ? REG_BIT_HAL0_PM_EXTDC_n  : 0 )  // status0�ɂ���
+              | ( RBR_RESET_n ? REG_BIT_HAL0_PM_EXTDC_n  : 0 )  // ���󂫂��g�킹�Ă��炤
+              | ( BT_IN_CHG_n ? REG_BIT_HAL0_BT_IN_CHG_n : 0 )   
+              | ( BT_CHG_Ena_n ? REG_BIT_HAL0_RSV_5      : 0 )  // �󂫃r�b�g�g�p,out pin
+              | 0                                               // WL_TX �g���Ȃ�
+//            | ( SHELL_OPEN  ? REG_BIT_HAL0_SHELL_OPEN  : 0 )  // status0�ɂ���
+              | ( RBR_FLIGHT  ? REG_BIT_HAL0_SHELL_OPEN  : 0 )  // ���󂫂��g�킹�Ă��炤
+              | ( SW_WIFI_n   ? REG_BIT_HAL0_SW_WIFI_n   : 0 )
+              | ( SW_HOME_n   ? REG_BIT_HAL0_SW_HOME_n   : 0 )
+              | ( SW_POW_n    ? REG_BIT_HAL0_SW_POW_n    : 0 );
+
+		infos_bits[0] = (u8)LED_pow_red;
+		infos_bits[1] = (u8)LED_CAM;
+
+		ret = *infos_table[iic_burst_state];
+        iic_burst_state ++;
+    }
+
+    return ret;
+}
+
+
+#ifdef i2c_timeout_test
+void i2c_mcu_error_monitor()
+{
+    LED_duty_pow_blu = 0xff;
+    LED_duty_3d         = 0xff;
+    LED_duty_notify_red = 0xff;
+    LED_duty_notify_grn = 0xff;
+    LED_duty_notify_blu = 0xff;
+    LED_pow_red         = 1;
+    LED_CAM             = 1;
+}
+#endif
+
diff --git a/tags/2.03_SDK-3.1/task_status.c b/tags/2.03_SDK-3.1/task_status.c
new file mode 100644
index 0000000..521b880
--- /dev/null
+++ b/tags/2.03_SDK-3.1/task_status.c
@@ -0,0 +1,79 @@
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+
+#endif
+
+#include "incs_loader.h"
+#include "renge\renge.h"
+#include "hal.h"
+
+#include "pm.h"
+
+#include "accero.h"
+#include "adc.h"
+#include "i2c_mcu.h"
+#include "led.h"
+
+
+/* ========================================================
+ �X�e�[�^�X���W�X�^���f�E���荞��
+ ======================================================== */
+void tsk_status(  )
+{
+    static u8 state_old;        // �X�e�[�^�X�ω����o�����荞�� �̈�
+    u8      diff;
+
+    // �W�J���`�F�b�N
+    set_bit( SHELL_OPEN, vreg_ctr[VREG_C_STATUS], REG_BIT_ST_SHELL_OPEN );
+
+    // �X�e�[�^�X���W�X�^�֌W �� ���荞�� //
+    // pm.c �ŁA���̏�ōs���܂��B
+    // REG_BIT_LCD_ON/OFF
+    // REG_BIT_BL_ON/OFF
+    // REG_BIT_BT_DC_CONNECT/DISC
+
+    diff = (u8)( vreg_ctr[VREG_C_STATUS] ^ state_old );
+    if( diff != 0 )
+    {
+        state_old = vreg_ctr[VREG_C_STATUS];
+
+        if( system_status.pwr_state == ON )
+        {
+            if( diff & REG_BIT_BATT_CHARGE )
+            {
+                // �[�d��Ԕ��f
+                if( vreg_ctr[VREG_C_STATUS] & REG_BIT_BATT_CHARGE ) // set_irq��ʁX�ɌĂԕ����R���p�N�g
+                {
+                    set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_START );
+                }
+                else
+                {
+                    set_irq( VREG_C_IRQ1, REG_BIT_BT_CHG_STOP );
+                }
+			}
+        }
+
+        if(( system_status.pwr_state == ON ) ||
+           ( system_status.pwr_state == SLEEP )
+           )
+        {
+            if( diff & REG_BIT_ST_SHELL_OPEN )
+            {
+                // �W�̊J���‚�
+                if( vreg_ctr[VREG_C_STATUS] & REG_BIT_ST_SHELL_OPEN )
+                {
+                    set_irq( VREG_C_IRQ0, REG_BIT_SHELL_OPEN );
+                }
+                else
+                {
+                    set_irq( VREG_C_IRQ0, REG_BIT_SHELL_CLOSE );
+                }
+            }
+        }
+    }
+}
+
diff --git a/tags/2.03_SDK-3.1/task_sys.c b/tags/2.03_SDK-3.1/task_sys.c
new file mode 100644
index 0000000..2931f7e
--- /dev/null
+++ b/tags/2.03_SDK-3.1/task_sys.c
@@ -0,0 +1,654 @@
+#ifndef _WIN32
+
+#pragma SFR
+#pragma NOP
+#pragma HALT
+#pragma STOP
+
+#endif
+
+#include "incs.h"
+
+#include "i2c_twl.h"
+#include "i2c_ctr.h"
+#include "led.h"
+#include "accero.h"
+#include "pm.h"
+#include "rtc.h"
+#include "sw.h"
+#include "adc.h"
+#include "self_flash.h"
+
+
+//=========================================================
+#define WAIT_SHIROBAKO_POW_CONTROL 240
+
+
+//=========================================================
+extern void nop8();
+
+
+static void chk_emergencyExit();
+static void force_off_check();
+static void send_getup_to_soc();
+#ifdef _DBG_CHK_OFF_LEAK_
+static void leak_check();
+#endif
+
+
+
+//=========================================================
+extern bit info_led_off;
+extern bit going_to_sleep;
+extern bit bt_authorized;
+
+static u8 timeout_sleep;
+extern u8 chg_led_override;
+
+#ifdef i2c_timeout_test
+extern bit i2c_mcu_time_out_error;
+#endif
+
+
+//=========================================================
+#define PWSW_POWON_TIME		(u8)( 20 / SYS_INTERVAL_TICK )	// [ms]  // INTERVAL_TSK_SW �Ŋ���Ȃ��B�l�������珬�����̂�
+#define PWSW_ON_CHECK_TIMEOUT		100	// �K�� �d��on�ׂ̈ɓd���X�C�b�`�����삳�ꂽ�Ƃ��A���̎��Ԍo�߂�����mcu���ȓd�͂ɖ߂�
+
+/* ========================================================
+ �}�C�R�������ŕK�v�Ȃ���
+�E�ȓd�͂ɓ����
+  �@system_status.pwr_state == OFF_TRIG �ŁA���̃^�X�N���Ă΂��ƁA
+  �ȓd�̓��[�h�ɓ���܂�
+ ======================================================== */
+void tsk_sys(  )
+{
+    static u8 pwsw_timeout = 0;	// �d���{�^���`���^�����O����B�@�^�C���A�E�g����܂łɓd�������m�肵�Ȃ���off�ɖ߂�
+
+	hal_update();
+
+	switch ( system_status.pwr_state )
+    {
+    case ON_CHECK:                  //-------------------------------------------------------
+		// �����d���f�J�E���g�_�E���^�C�}�N���A
+		clear_pow_off_countdown();
+
+		// ���̊��荞�݂�HALT(�X���[�v)������ �^�@�A�_�v�^�L��
+
+        // �d���X�C�b�`��HALT���� //
+        if( system_status.poweron_reason == RSN_PWSW )
+        {
+			if( PM_EXTDC_n )
+			{
+				// �A�_�v�^�Ȃ�
+				if( SW_pow_count != 0 )
+				{
+					pwsw_timeout = 0;
+				}
+				else
+				{
+					pwsw_timeout ++;
+				}
+
+				if( pwsw_timeout > PWSW_ON_CHECK_TIMEOUT )
+				{
+					SW_pow_count = 0;
+					system_status.pwr_state = OFF_TRIG;     // �X�C�b�`�̓m�C�Y�������B�Q��B
+					renge_task_interval_run_force = true;
+					return;
+				}
+			}
+			else
+			{
+				BT_chk();
+			}
+
+
+			if( SW_pow_count < PWSW_POWON_TIME )
+			{
+				// �������Ԃ��Z���ēd��on�ɓ��B���Ă��Ȃ�
+				return;
+			}
+        }
+		// else { if( system_status.poweron_reason == RSN_TRIAL�A�c ) �d������ }
+
+        SW_pow_mask = true;		// pwsw�������ςȂ��œd����/�� ���J��Ԃ��Ȃ��悤��
+
+        // �d������ //
+        iic_mcu_start(  );
+
+        bt_force_update = false;
+        BT_chk();				// ���@��o�b�e���̔���A�d�r�c��IC�̐ݒ�
+
+#ifndef _ALLOW_NOBATT_
+        if( system_status.model == MODEL_JIKKI_NOBATT )
+        {
+            renge_task_interval_run_force = true;
+            system_status.pwr_state = OFF_TRIG;
+            return;
+        }
+#endif
+
+        // �c�ʃ`�F�b�N
+        BT_get_left();         // ��ɁABT_chk()�����s����Ă���K�v������܂��B
+        if(
+//            ( vreg_ctr[VREG_C_BT_REMAIN] < 1 )  // �������Ŕ��肷��Ɠd�r���قƂ�ǖ����Ƃ���
+//                                                //  �A�_�v�^�����Ă������N���ł��Ȃ��Ȃ����Ⴄ
+            ( vreg_ctr[VREG_C_BT_VOLTAGE] < ( V_TH_ZERO / 256 ) ) // �d�r�����
+            )
+        {
+            // �d�r�����Ȃ��̂ŋN�������Ȃ�(�d���`�F�b�N������Ă�)
+            renge_task_interval_run_force = true;
+            system_status.pwr_state = OFF_TRIG;
+            return;
+        }
+
+        // �|�[�g�̕����ݒ�@�d�������O�ɁB
+        PM_SW_WIFI_n  = 1;
+        PM_SW_HOME_n_JIKKI = 1;
+        PM_WL_TX      = 1;
+        PM_SW_SEL_n   = 1;
+        PM_ACCEL_INT1 = 1;
+		PM_ACC_VALID  = 1;
+
+        if( PM_sys_pow_on(  ) != ERR_SUCCESS )  // ���Z�b�g���������Ă��܂�
+        {                       // �d���N���s�ƒG���[
+            renge_task_interval_run_force = true;
+            system_status.pwr_state = OFF_TRIG;
+            return;
+        }
+
+        // �����܂ŗ���ƁA�d�������m�� //
+		// �v���A�b�von
+        PU_BT_IN_CHG_n = 1;
+        PU7 = bits8(0,0,0,1, 1,1,0,1);       // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_EXTDC_n
+        PU_SW_HOME_n_JIKKI = 1;            // SW_HOME
+
+        if( system_status.poweron_reason == RSN_PWSW ||
+			system_status.poweron_reason == RSN_TRIAL )
+        {
+            // �d���{�^���ł�on�̎��́ALED��_��������
+            vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO;
+        }
+        else
+        {
+            // �Ƃ肠�����ALED������ԂŋN��������
+            vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF;
+        }
+
+        system_status.pwr_state = ON_TRIG;
+
+        PM_LCD_vcom_set(  );    // LCD�̑Ό��d���l�ȂǏ�������
+
+        break;
+
+    case ON_TRIG:              //-------------------------------------------------------
+#ifdef i2c_timeout_test
+        LED_duty_pow_blu = 0;     // debug
+        LED_duty_3d         = 0;
+        LED_duty_notify_red = 0;
+        LED_duty_notify_grn = 0;
+        LED_duty_notify_blu = 0;
+        LED_pow_red         = 0;
+        LED_CAM             = 0;
+        i2c_mcu_time_out_error = false;
+#endif
+        IIC_ctr_Init(  );
+        IIC_twl_Init(  );
+        RTC_32k_on(  );
+
+        vreg_twl_init(  );
+        vreg_ctr_reset(  );
+
+        KRM  = bits8(0,0,0,0, 0,0,0,0);
+        PIF0 = 0;
+
+        system_status.poweron_reason = NONE;
+        renge_task_interval_run_force = true;
+
+        MK0 = INT_MSK0_RSV;
+        MK1 = INT_MSK1_RSV;
+
+        iic_mcu_start();
+
+//        MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT_MSK2_CODEC_PMIRQ );
+//        PMK21 = 0;  // wifi  �g��Ȃ�
+        PMK6 = 0;   // pm_irq
+
+		// todo �����I�ɂ͊��S�Ƀ��W�X�^�����
+		RBR_RESET_n = 1;
+		RBR_FLIGHT  = 0;
+
+        // ���u�[�g���A�X�e�[�^�X�����ƂȂ��X�V
+        if( system_status.reboot )
+        {
+            u8 bl_status_temp;
+
+            bl_status_temp = read_pmic( PM_REG_ADRS_BL );
+            vreg_ctr[ VREG_C_STATUS ] |= (( bl_status_temp & 0x03 ) << 5 );
+            set_bit( ( read_pmic( PM_REG_ADRS_VDD_LCD ) != 0 ),
+                    vreg_ctr[ VREG_C_STATUS ], REG_BIT_LCD_POW );
+            BT_chk();
+        }
+
+        LED_init(  );  // reboot���́�BT_Chk,BT_chk��ɍs������
+
+        system_status.reboot = 0;
+        system_status.pwr_state = ON;
+
+        // WDT���Z�b�g���AI2C�̏������܂Ŋ��荞�ݕۗ�
+        //  �ق�Ƃ͂����ɂׂ������������Ȃ���...
+        if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT_RESET ) != 0 )
+        {
+            set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
+        }
+
+        break;
+
+    case ON:                   //---------------------------------------------
+        // PMIC�ɂ�鋭���d���f�`�F�b�N
+        // �f�o�b�K��reset1���A�T�[�g���邱�Ƃ�����B���̂Ƃ��͑S�����Z�b�g
+        chk_emergencyExit();
+
+        // SLP��
+        if( going_to_sleep )          // ��΂� SLP_REQ �̑O�ɗ\��������
+        {
+            timeout_sleep ++;
+            if( timeout_sleep == 0 ||  // �I�[�o�[�t���[�����ҁBsleep������Č��������Lj�u�ŋN���ċC���‚��Ȃ�����
+                ( PIF0 && !SLP_REQ ))  // slp���荞�݂��������C���������A�����N���Ă��܂���
+            {
+                PIF0 = 0;
+                send_getup_to_soc();
+            }
+            if( PIF0 && SLP_REQ ){
+                PIF0 = 0;
+                PM_VDD_ecoMode();
+                system_status.pwr_state = SLEEP;
+                renge_task_interval_run_force = true;
+            }
+        }
+
+        // ����off�J�E���g
+        force_off_check();
+
+#ifndef _TAIKENDAI_SEISAN_SPECIAL_
+        if( system_status.taikendai )		// �A�_�v�^���������玩���œd��off
+        {
+            if( PM_EXTDC_n )
+            {
+                system_status.pwr_state = OFF_TRIG;
+            }
+        }
+#endif
+
+        break;
+
+    case SLEEP:                //------------------------------------------
+        chk_emergencyExit();
+        // �X���[�v���畜�A
+        if( !SLP_REQ ){
+            PM_VDD_normMode();
+            wait_ms( 5 );  // tdly_sw
+            send_getup_to_soc();
+            system_status.pwr_state = ON;
+        }
+		
+        force_off_check();
+//		leak_check();
+
+#ifndef _TAIKENDAI_SEISAN_SPECIAL_
+        if( system_status.taikendai )		// �A�_�v�^���������玩���œd��off
+        {
+            if( PM_EXTDC_n )
+            {
+                system_status.pwr_state = OFF_TRIG;
+            }
+        }
+        break;	// �������ł悢�B
+#else
+		/* FALLTHROUGH */
+#endif
+
+    default:                   //---------------------------------------
+        system_status.pwr_state = OFF_TRIG;  // ���蓾�Ȃ��X�e�[�g�B�f�o�b�O�p
+//		dbg_nop();
+		/* FALLTHROUGH */
+
+	case OFF_TRIG:             //---------------------------------------
+        // LED������҂�
+        vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_OFF;
+        vreg_ctr[ VREG_C_LED_WIFI ] = WIFI_LED_OFF;
+        vreg_ctr[ VREG_C_LED_3D ] = LED_3D_ILM_OFF;
+        info_led_off = true;
+        if( LED_duty_pow_blu != 0 )
+        {
+            return;
+        }
+
+		// �����d���f�J�E���g�_�E���^�C�}�N���A
+		clear_pow_off_countdown();
+
+		// �����x�Z���T��~
+        vreg_ctr[ VREG_C_ACC_CONFIG ] = 0x00;
+        tski_acc_setup();
+		EI();	// DI��Ԃł������ė���̂ŁAI2C_mcu ����������̂ɕK�v��
+
+		// ���̑��y���t�F������~
+        LED_stop(  );
+        IIC_ctr_Stop(  );
+        IIC_twl_Stop(  );
+        RTC_32k_off();
+
+		// todo �}�N���ɂł�����
+		RBR_RESET_n = 0;
+		RBR_FLIGHT  = 0;
+
+//  �d���I�������̊��荞�݃Z�b�g
+// PWSW        KR3   ������L
+// BG24        KR4
+// �ӂ��J��    INTP5 �‚����L
+// AC�A�_�v�^  INTP4 �A�_�v�^�����L
+// RTC
+        while( iic_mcu_busy )
+        {;}
+
+		// irq�}�X�N�ݒ�
+        KRM = ( KR_SW_POW );    // Mask �ł͂Ȃ��AMode�Ȃ̂��������B����킵��
+        MK0 = ~( INT_MSK0_EXTDC );
+        MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCINTVAL );  // INT_MSK1_RTCALARM | RTC�A���[������
+        MK2L = 0xFF;
+
+		// irq�t���O�N���A
+		vreg_ctr[VREG_C_IRQ0] = 0;
+        vreg_ctr[VREG_C_IRQ1] = 0;
+        vreg_ctr[VREG_C_IRQ2] = 0;
+        vreg_ctr[VREG_C_IRQ3] = 0;
+
+        // PU5 ���̂܂�
+        PU7 = bits8(0,0,0,0, 1,0,0,1);   // PWSWI,PM_EXTTDC,( IRQ0_deactive(), PM_IRQ_deactive )
+        PU_SW_HOME_n_JIKKI = 0;          // SW_HOME ��~
+
+        IF0 = 0;
+        IF1 = 0;
+        IF2 = 0;
+
+        IRQ0_disable;
+
+        PM_sys_pow_off(  );				 // �d���J�b�g�I�t
+
+		// �|�[�g�ނ��~���[�h�ɁB����������H�ł��AL�o�͂ɂ��Ȃ��Ⴞ�߂������ȁB
+        SW_WIFI_n_RAW = 0;
+        PM_SW_WIFI_n = 0;
+
+        SW_HOME_n_JIKKI_RAW = 0;
+        PM_SW_HOME_n_JIKKI = 0;
+
+        WL_TX = 0;
+        PM_WL_TX = 0;
+
+        SW_SEL_n = 0;
+        PM_SW_SEL_n = 0;
+
+		ACCEL_INT1 = 0;
+        PM_ACCEL_INT1 = 0;
+        ACC_VALID = 0;
+        PM_ACC_VALID = 0;
+
+        system_status.pwr_state = OFF;
+        SW_pow_mask = true;
+        SW_pow_count = 0;
+
+		// HAL�f�o�b�O���Z�b�g�@�Y���Ɠd��on�o���Ȃ��Ȃ邱�Ƃ��c
+		hal_reset();
+		/* FALLTHROUGH */
+
+    case OFF:
+		//  ���F����ł͓d���{�^�������d�������͂���܂���B
+
+		system_status.poweron_reason = NONE;
+		pwsw_timeout = 0;
+
+		if( !PM_EXTDC_n 
+			|| chg_led_override != 0 )	// ���ꂪ�[���ɂȂ�܂ő҂�
+        {
+            // �A�_�v�^�L�� /////////////////////////////// �܂��́A�A�_�v�^�����ĂR�b�͏[�dLED��_���Ă������
+
+			// �d���{�^�������`�F�b�N��
+		    system_status.poweron_reason = RSN_PWSW;
+			system_status.pwr_state = ON_CHECK;		
+
+			// ���V��Ȃ玩���œd���ē���
+            if( system_status.taikendai )
+            {
+                vreg_ctr[ VREG_C_HAL_OVW_CONT0 ] = vreg_ctr[ VREG_C_HAL_OVW_CONT1 ] = 0;
+                wait_ms(46);    // pmic�̓d���ē����d�l�̂���
+				system_status.poweron_reason = RSN_TRIAL;
+                system_status.pwr_state = ON_CHECK;
+            }
+        }
+        else
+        {
+            // �A�_�v�^�Ȃ� ///////////////////////////////
+
+            // �ȓd�͂ֈڍs
+            iic_mcu_stop(  );
+            pm_chk_adapter();
+            PM_Chg_Stop();
+
+            bt_force_update = true;
+
+            while( RWST )
+            {;}
+
+            // ���荞�ݑ҂��ŐQ�� //
+            RTCIMK = 1;		// systick�p�C���^�[�o���^�C�}�[���荞�݃}�X�N
+
+#ifdef _DBG_CHK_OFF_LEAK_
+			leak_check();
+#endif
+            CKC  = bits8(0,0,0,0, 1,0,0,1);		// 4MHz�ɗ��Ƃ��Ă���STOP���Ȃ��Ă͂Ȃ�Ȃ�
+			OSMC = bits8(0,0,0,0, 0,0,0,0);		// 5MHz�ȉ����[�h�ցB
+
+			if( PM_EXTDC_n_RAW )  // ����ǂ��^�C�~���O�ő}�����N���邱�Ƃ�����BHAL�ʂ��Ȃ��ׂ��ioff���ł����j
+			{
+				STOP();
+			}
+
+			// �N���� //
+            // �N���������
+            // �EKeyReturn���荞�݁i�d���{�^���j
+            // �ERTC�A���[���i���ݕ���j
+
+			// �N���b�N���A
+			OSMC = bits8(1,0,0,0, 0,0,0,0);		// 8MHz���쏀��
+
+			renge_flg_interval = 0;
+			hal_update();
+
+			CKC  = bits8(0,0,0,0, 1,0,0,0);	// FSEL = 1 ��3clk�ȏ�J����
+
+			// �N�������R�́H
+			if( !PM_EXTDC_n ){
+	            system_status.pwr_state = OFF;	// ������Ă��āAON_CHECK�ɍs��
+			}
+/*			// RTC�A���[���B����
+			else if( vreg_ctr[ VREG_C_IRQ1 ] & REG_BIT_RTC_ALARM )
+			{
+		        system_status.poweron_reason = RSN_RTC_ALARM;
+	            system_status.pwr_state = ON_CHECK;
+			}
+			// else if( ���̊��荞�݂œd��on ){
+			//		���󑼂̗v���ł͋N���Ȃ�
+			// }
+*/
+			else // if( !SW_POW_n )	// �i����ȊO�Ȃ�j�d���{�^���ŋN����
+            {
+                SW_pow_mask = false;
+		        system_status.poweron_reason = RSN_PWSW;
+	            system_status.pwr_state = ON_CHECK;
+            }
+
+            RTCIMK = 0;         // sys tick �^�C�}�[�L��
+            
+            if( system_status.taikendai )
+            {
+                system_status.pwr_state = OFF_TRIG;
+            }
+
+        }
+    }
+}
+
+
+
+/*******************************************************//**
+    PMIC���d���ُ�Ŏ~�߂����m�F
+ **********************************************************/
+static void chk_emergencyExit(){
+    static u8 shirobako_power_control_count;
+
+    if( shirobako_power_control_count == 0 )
+    {
+        if( !RESET1_n )         // PM_chk_LDSW() ��I2C_m���g�p���A���R�X�g
+        {
+            if( !PM_chk_LDSW() )
+            {
+                // ���Z�b�g����������
+                /// PMIC���ُ�I�����f������
+                system_status.pwr_state = OFF_TRIG;
+                renge_task_interval_run_force = true;
+            }
+            else
+            {
+                // �����̎d��
+                shirobako_power_control_count = 1;
+            }
+        }
+    }
+    else
+    {
+        if( shirobako_power_control_count == WAIT_SHIROBAKO_POW_CONTROL ) // �}�W�b�N�i���o�[
+        // �f�o�b�K�����������Breset1����������܂ł͖���
+        {
+            if( RESET1_n )      // ���Z�b�g�l�Q�[�g�҂�
+            {
+                shirobako_power_control_count = 0;
+            }
+            else
+            {
+                // nothing to do
+            }
+        }
+        else if( shirobako_power_control_count == 200 ) // * (sys_tick)[ms]
+        // �f�o�b�K�������������炵��
+        {
+#ifndef _RVD_
+            // �����͓d����؂肽���炵��
+            system_status.pwr_state = OFF_TRIG;
+            renge_task_interval_run_force = true;
+            shirobako_power_control_count = WAIT_SHIROBAKO_POW_CONTROL;
+#endif
+        }
+        else
+        {
+            if( !RESET1_n )
+            {
+                if( shirobako_power_control_count != 255 )
+                    shirobako_power_control_count ++;
+            }
+            else
+            {
+                // (TS�{�[�h�Ŏ蓮��/�f�o�b�K��)���Z�b�g���������炵��
+                send_cmd_pmic(  PM_REG_ADRS_BL, 0 );
+                vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & bits8(1,0,0,1, 1,1,1,1) );
+                vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ;
+                renge_task_immed_add( tski_do_command0 );
+                shirobako_power_control_count = WAIT_SHIROBAKO_POW_CONTROL;
+            }
+        }
+    }
+}
+
+
+
+/* ========================================================
+  �E�d���{�^��������
+  �E�d�r�؂�
+  �E�d�r����
+  �ł̋���OFF�B��������Ɖ����s�\
+ ======================================================== */
+static void force_off_check()
+{
+    if( force_off )
+    {
+        system_status.pwr_state = OFF_TRIG;
+        renge_task_interval_run_force = true;
+    }
+}
+
+
+
+/* ========================================================
+  SoC���N����
+�@�@�d�����ʏ�ɖ߂��Ă���Ă�ʼn������B
+ ======================================================== */
+void send_getup_to_soc()
+{
+    going_to_sleep = false;
+    timeout_sleep  = 0;
+#ifdef _MODEL_CTR_
+    SLP_ACK = 1;
+    nop8();
+    SLP_ACK = 0;
+#endif
+}
+
+
+
+
+/* ========================================================
+  firm_update()�� task_status_immed�^ ��Ԃ��悤�ɂ���΂����̂ł���...
+ ======================================================== */
+task_status_immed tski_firm_update(){
+    firm_update();
+    return( ERR_SUCCESS );
+}
+
+
+
+#ifdef _DBG_CHK_OFF_LEAK_
+/* ========================================================
+    pin�ݒ�~�X�`�F�b�N
+ ======================================================== */
+static void leak_check()
+{
+	volatile u8 ports_i[12];
+	volatile u8 ports_o[12];
+
+	ports_i[0]  = ( PM0  & PU0  & ~P0  );	// �v���A�b�v�؂�Y��H
+	ports_i[1]  = ( PM1  & PU1  & ~P1  );
+	ports_i[2]  = 0;
+	ports_i[3]  = ( PM3  & PU3  & ~P3  );
+	ports_i[4]  = ( PM4  & PU4  & ~P4  );
+	ports_i[5]  = ( PM5  & PU5  & ~P5  );
+	ports_i[6]  = 0;
+	ports_i[7]  = ( PM7  & PU7  & ~P7  );
+	ports_i[8]  = ( PM12 & PU12 & ~P12 );
+	ports_i[9]  = ( PM14 & PU14 & ~P14 );
+	ports_i[10] = 0;
+	ports_i[11] = ( PM20 & PU20 & ~P20 );
+
+	ports_o[0]  = ( ~PM0  & P0  );			// H �o�͂�������Ă邩��
+	ports_o[1]  = ( ~PM1  & P1  );
+	ports_o[2]  = ( ~PM2  & P2  );
+	ports_o[3]  = ( ~PM3  & P3  & ~POM3 );
+	ports_o[4]  = ( ~PM4  & P4  ); // bit3��chg_en�Ȃ̂�1�ł��悢
+	ports_o[5]  = ( ~PM5  & P5  );
+	ports_o[6]  = ( ~PM6  & P6  );
+	ports_o[7]  = ( ~PM7  & P7  );
+	ports_o[8]  = ( ~PM12 & P12 );
+	ports_o[9]  = ( ~PM14 & P14 );
+	ports_o[10] = ( ~PM15 & P15 );
+	ports_o[11] = ( ~PM20 & P20 );
+	NOP();          // ���u���[�N�u������
+}
+#endif _DBG_CHK_OFF_LEAK_
diff --git a/tags/2.03_SDK-3.1/user_define.h b/tags/2.03_SDK-3.1/user_define.h
new file mode 100644
index 0000000..1d0773a
--- /dev/null
+++ b/tags/2.03_SDK-3.1/user_define.h
@@ -0,0 +1,209 @@
+#ifndef _USER_DEF_
+#define _USER_DEF_
+
+
+#define IIC_T_SLAVEADDRESS	0x4A
+#define IIC_C_SLAVEADDRESS	0x4A
+#define IIC_C_SLAVEADDRESS_DMY	0x4C
+
+//#define IIC_SLA_DCP     0x50
+
+#define bits8(a,b,c,d,e,f,g,h) ( a<<7 | b<<6 | c<<5 | d<<4 | e<<3 | f<<2 | g<<1 | h )
+
+#ifndef _WIN32
+// ���@�‹�
+
+#ifdef _debug_led_
+/*spfl�Ή��ȍ~�Anc�łȂ��Ȃ�̂Ŏg���܂���
+# define DBG_LED_on      { PM2.1 = 0; P2.1 = 1; }
+# define DBG_LED_off     { P2.1 = 0; }
+# define DBG_LED_toggle  ( P2.1 ^= 1 )
+# define DBG_LED2_on      { PM2.2 = 0; P2.2 = 1; }
+# define DBG_LED2_off     { P2.2 = 0; }
+# define DBG_LED2_toggle  ( P2.2 ^= 1 )
+*/
+#else
+# define DBG_LED_on      ;
+# define DBG_LED_off     ;
+# define DBG_LED_toggle  ;
+# define DBG_LED2_on      ;
+# define DBG_LED2_off     ;
+# define DBG_LED2_toggle  ;
+#endif // _debug_led_
+
+#define IIC_SLA_CODEC   0xA4
+#define IIC_SLA_ACCEL   0x30           // ST LIS331DLH
+
+
+#define SLP_ACK         P7.7
+
+
+// PMx��0�ŏo�̓��[�h
+
+// SoC
+#define IRQ0_ast            { P7.6 = 0; PM7.6 = 0; }
+#define IRQ0_neg            { P7.6 = 1; }
+#define IRQ0_enable         { PM7.6 = 0; }
+#define IRQ0_disable        { PM7.6 = 1; }
+#define IRQ0              ( P7.6 )
+
+
+// �������h�~
+#define RESET1_n             ( P0.0 )
+
+#if 0 // PM_RESET1�`���g��
+# define RESET1_ast           { P0.0 = 0; PM0.0 = 0; }
+# define RESET1_neg           { PM0.0 = 1; }
+#endif
+
+#define RESET2_ast           { P0.1 = 0; PM0.1 = 0; }
+#define RESET2_neg           { PM0.1 = 1; }
+
+#define SLP_REQ              P12.0
+
+// CTR,SPFL,�܂����ʔh���@����
+#define DEV_DET              ( P12 & 0b00000110 )
+#define DEV_CTR              ( 0b00 << 1 )
+#define DEV_SPFL             ( 0b01 << 1 )
+#define DEV_SHRIMP           ( 0b10 << 1 )
+#define DEV_RSV2             ( 0b11 << 1 )
+
+// FCRAM
+#define FCRAM_RST            P3.0
+#define FCRAM_RST_ast        { P3.0 = 0; }
+#define FCRAM_RST_neg        { P3.0 = 1; }
+
+// CODEC
+#define PM_IRQ_n             P7.2
+// INTP6
+
+// PM
+#define PM_EXTDC_n_RAW       P7.0
+// INTP7
+//#define BT_TEMP              P15.0
+// ANI8
+//#define BT_DET               P15.1
+// ANI9
+#define BT_DET_P             P1.6
+#define BT_TEMP_P            P1.7
+
+
+// SPFL�̃A�����t�@�XLCD�ŕK�v�ȁ}15V�̓d���B
+#define SPFL_LCD_AMOL_HV_CONT P20.2
+
+
+// �[�d����(out)
+// ���_���ł��B���ӁB
+#define BT_CHG_ENABLE()      ( P4.3 = 0 )
+#define BT_CHG_DISABLE()     ( P4.3 = 1 )
+#define BT_CHG_Ena_n         ( P4.3 )
+
+// �[�d��(in)
+#define BT_IN_CHG_n_RAW       P5.1
+#define PM_BT_IN_CHG_n       PM5.1
+#define PU_BT_IN_CHG_n       PU5.1
+
+#define SW_WIFI_n_RAW         P7.4
+#define PM_SW_WIFI_n         PM7.4
+// KR4
+#define SW_POW_n_RAW          P7.3
+// KR3
+#define SW_SEL_n              P2.3
+#define PM_SW_SEL_n          PM2.3
+//#define VOL                  P2.7
+// ANI7
+
+#define SW_HOME_n_JIKKI_RAW   P20.4
+#define PM_SW_HOME_n_JIKKI   PM20.4
+#define PU_SW_HOME_n_JIKKI   PU20.4
+
+// INTP22
+#define SW_HOME_n_TSBOARD_RAW P2.0	// TS�}�U�[���pull up(P2�͓���p.u.����)
+#define PM_SW_HOME_n_TSBOARD PM2.0
+
+// WiFi
+#define WL_TX                P20.3      // INTP21
+#define PM_WL_TX             PM20.3      // INTP21
+
+// RBR����
+#define RBR_RESET_n          P2.1
+#define RBR_FLIGHT           P2.2
+
+//#define LED_CAM            P1.0      // TO02
+//#define LED_WIFI           P1.1      // TO03
+//#define LED_NOTIFY         P1.3      // TO05
+//#define LED_3D           P5.2      // SLTO �� TO01
+//#define LED_POW2           P1.4      // TO06 ( �� )
+//#define LED_POW1           P1.5      // TO07 ( �� )
+//#define LED_CHARGE         P2.4
+
+// P5.3 �ɉ����AP5.5, P140 P141
+// P140���o�͐�p�Ȃ̂�...
+#define I2C_PU_on()          { P14 |= 0x03; PM5.3 = 0; PM3.3 = 0; }
+#define I2C_PU_off()         { PM5.3 = 1; PM3.3 = 1; P14 &= ~0x03; }
+
+#define GYRO_ENABLE()     P5.0 = 0
+#define GYRO_DISABLE()    P5.0 = 1
+
+//#define I2C_M_SDA            P3.1      // SDA10
+//#define I2C_M_SCL            P3.2      // SCL10
+
+//#define I2C_0_SCL            P6.0        // IIC_TWL SCL0
+//#define I2C_0_SDA            P6.1        //         SDA0
+
+//#define I2C_1_SCL            P20.0       // IIC CTR SCL1
+//#define I2C_1_SDA            P20.1       //         SDA1
+
+//#define 32kHz_O              P1.2        // RTCCL
+//#define 32k_I1               P12.3       // XT1
+//#define 32k_I2               P12.4       // XT2
+
+// ���@�A�J���@�A���V�䔻�ʁB
+#define DIPSW                ( P4 & 0b00000011 )  // mini cube & �\�t�g�E�F�A�f�B�b�v�X�C�b�` TOOL0,1�B P4.0�� L ���ӁI
+#define DIPSW_CTR            0b11  // ���g�p
+#define DIPSW_ISDEV          0b00  // KuC��BattGauge�Ŕ���
+#define DIPSW_TAIKENDAI      0b10
+#define DIPSW_TAIKENDAI_NBD  0b01
+
+
+#define SHELL_OPEN_RAW        P7.1       // INTP5 �ӂ��J�� (�‚����L)
+
+#define ACC_VALID             P20.5
+#define PM_ACC_VALID         PM20.5
+#define ACCEL_INT1            P2.5
+#define PM_ACCEL_INT1        PM2.5
+
+
+#endif // _WIN32 
+
+// win32 sim�‹��Ƌ���
+
+#define KR_SW_POW            ( 1 << 3 )
+#define KR_SW_WIFI           ( 1 << 4 )
+
+///////////////////////////////////////////////////////////
+
+#define INT_MSK0_IIC_M_DMA    1<<12
+#define INT_MSK0_SHELL        1<<7
+#define INT_MSK0_EXTDC        1<<6
+//#define INT_MSK0_SLP        1<<2
+#define INT_MSK0_RSV          ~( INT_MSK0_IIC_M_DMA | INT_MSK0_SHELL | INT_MSK0_EXTDC )
+
+#define INT_MSK1_KR           1<<11
+#define INT_MSK1_RTCINTVAL    1<<10
+#define INT_MSK1_RTCALARM     1<<9
+#define INT_MSK1_ADC          1<<8
+#define INT_MSK1_IIC_CTR      1<<3
+#define INT_MSK1_IIC_MCU      1<<0
+#define INT_MSK1_RSV          ~( INT_MSK1_KR | INT_MSK1_RTCINTVAL | INT_MSK1_RTCALARM | INT_MSK1_ADC \
+                                 | INT_MSK1_IIC_CTR | INT_MSK1_IIC_MCU )
+
+#define INT_MSK2_WIFI_TX_KE3  1<<4
+#define INT_MSK2L_RSV         ~( INT_MSK2_WIFI_TX_KE3 )
+
+#define INT_MSK2_IIC_TWL      1<<8
+#define INT_MSK2_WIFI_TX_BSR  1<<10
+#define INT_MSK2_CODEC_PMIRQ  1<<3
+#define INT_MSK2_RSV          ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT_MSK2_CODEC_PMIRQ )
+
+#endif // dupe include guard
diff --git a/tags/2.03_SDK-3.1/voltable.c b/tags/2.03_SDK-3.1/voltable.c
new file mode 100644
index 0000000..2aedcf0
--- /dev/null
+++ b/tags/2.03_SDK-3.1/voltable.c
@@ -0,0 +1,48 @@
+#include "incs.h"
+
+#define _10db_
+
+#ifdef _10db_
+// max -10db
+const u8 slider_to_codec[64] =
+{
+    127, 126, 125, 124, 122, 121, 120, 119,
+    118, 117, 116, 114, 113, 112, 111, 110,
+    109, 108, 106, 105, 104, 103, 102, 101,
+    100, 98, 97, 96, 95, 94, 93, 92,
+    90, 89, 88, 87, 86, 85, 83, 82,
+    81, 80, 79, 78, 77, 75, 74, 73,
+    73, 72, 71, 70, 69, 67, 66, 65,
+    64, 63, 62, 61, 59, 58, 57, 56
+    };
+#endif
+
+#ifdef _15db_
+// max -15db
+const u8 slider_to_codec[64] =
+{
+    127,	127,	127,	127,	127,	126,	125,	123,
+    122,	121,	120,	119,	118,	117,	116,	115,
+    114,	113,	112,	110,	109,	108,	107,	106,
+    105,	104,	103,	102,	101,	100,	99,	97,
+     96,	95,	94,	93,	92,	91,	90,	89,
+     88,	87,	86,	85,	84,	83,	82,	81,
+     80,	79,	78,	77,	76,	75,	74,	73,
+     71,	70,	69,	68,	67,	66,	66,	66
+};
+#endif
+
+#ifdef _4db_
+// max -4db
+const u8 slider_to_codec[64] =
+{
+    127,	127,	126,	125,	123,	122,	121,	119,
+    118,	117,	115,	114,	112,	111,	110,	108,
+    107,	106,	104,	103,	101,	100,	99,	97,
+     96,	94,	93,	92,	90,	89,	88,	86,
+     85,	83,	82,	81,	79,	78,	77,	75,
+     74,	72,	71,	70,	68,	67,	66,	64,
+     64,	63,	61,	60,	59,	57,	56,	54,
+     53,	52,	50,	49,	48,	46,	44,	44
+};
+#endif
diff --git a/tags/2.03_SDK-3.1/voltable.h b/tags/2.03_SDK-3.1/voltable.h
new file mode 100644
index 0000000..6ff34ab
--- /dev/null
+++ b/tags/2.03_SDK-3.1/voltable.h
@@ -0,0 +1,57 @@
+#ifdef _10db_
+// max -10db
+/*
+const u8 slider_to_codec[64] =
+{
+    127, 127, 127, 127, 126, 125, 123, 122,
+    121, 120, 118, 117, 116, 115, 113, 112,
+    111, 110, 108, 107, 106, 105, 103, 102,
+    101, 100,  98,  97,  96,  95,  93,  92,
+     91,  90,  88,  87,  86,  85,  83,  82,
+     81,  80,  78,  77,  76,  75,  73,  72,
+     72,  71,  70,  68,  67,  66,  64,  63,
+     62,  61,  59,  58,  57,  56,  55,  55
+     };
+*/
+const u8 slider_to_codec[64] =
+{
+    127, 126, 125, 124, 122, 121, 120, 119,
+    118, 117, 116, 114, 113, 112, 111, 110,
+    109, 108, 106, 105, 104, 103, 102, 101,
+    100, 98, 97, 96, 95, 94, 93, 92,
+    90, 89, 88, 87, 86, 85, 83, 82,
+    81, 80, 79, 78, 77, 75, 74, 73,
+    73, 72, 71, 70, 69, 67, 66, 65,
+    64, 63, 62, 61, 59, 58, 57, 56
+    };
+#endif
+
+#ifdef _15db_
+// max -15db
+const u8 slider_to_codec[64] =
+{
+    127,	127,	127,	127,	127,	126,	125,	123,
+    122,	121,	120,	119,	118,	117,	116,	115,
+    114,	113,	112,	110,	109,	108,	107,	106,
+    105,	104,	103,	102,	101,	100,	99,	97,
+     96,	95,	94,	93,	92,	91,	90,	89,
+     88,	87,	86,	85,	84,	83,	82,	81,
+     80,	79,	78,	77,	76,	75,	74,	73,
+     71,	70,	69,	68,	67,	66,	66,	66
+};
+#endif
+
+#ifdef _4db_
+// max -4db
+const u8 slider_to_codec[64] =
+{
+    127,	127,	126,	125,	123,	122,	121,	119,
+    118,	117,	115,	114,	112,	111,	110,	108,
+    107,	106,	104,	103,	101,	100,	99,	97,
+     96,	94,	93,	92,	90,	89,	88,	86,
+     85,	83,	82,	81,	79,	78,	77,	75,
+     74,	72,	71,	70,	68,	67,	66,	64,
+     64,	63,	61,	60,	59,	57,	56,	54,
+     53,	52,	50,	49,	48,	46,	44,	44
+};
+#endif
diff --git a/tags/2.03_SDK-3.1/vreg_ctr.c b/tags/2.03_SDK-3.1/vreg_ctr.c
new file mode 100644
index 0000000..11d7713
--- /dev/null
+++ b/tags/2.03_SDK-3.1/vreg_ctr.c
@@ -0,0 +1,591 @@
+/* ========================================================
+
+CTR MCU I2C���W�X�^
+
+  ====================================================== */
+#include "incs.h"
+#include "vreg_ctr.h"
+#include "rtc.h"
+#include "led.h"
+#include "accero.h"
+#include "pm.h"
+#include "pool.h"
+
+#include <fsl.h>
+
+#include "fsl_user.h"
+
+
+extern u8 extinfo_read();   // task_misc.c
+
+extern u8 iic_burst_state;  // ����o�[�X�g�A�N�Z�X���鎞�̃J�E���^
+extern bit info_led_pattern_updated;  // ���m�点LED�̃p�^�[����擪�ɖ߂�
+
+extern bit pedolog_overflow;
+extern bit reserve_pedo_increnent;
+
+
+
+// ********************************************************
+u8      vreg_ctr[VREG_C_ENDMARK_];
+
+static u8      vreg_free_adrs;      // �A�h���X���ł�̂ł��΂炭�͂����
+bit     irq_readed;					// AAA�^�̂��߁B
+
+
+
+// ********************************************************
+extern task_status_immed tski_firm_update();
+extern task_status_immed tski_mcu_reset();
+extern unsigned char get_ei();
+extern void DI_wt_chk();
+
+
+
+// ********************************************************
+#ifdef _MCU_BSR_
+#define IICAMK     IICAMK1
+#endif
+
+
+// ********************************************************
+// ��[���̏����l�̎w�肪�K�v�ȃA�h���X
+// �}�C�R�����Z�b�g���ɌĂ΂�܂�
+void vreg_ctr_init(  )
+{
+    vreg_ctr[ VREG_C_VCOM_T ] = VCOM_DEFAULT_T;
+    vreg_ctr[ VREG_C_VCOM_B ] = VCOM_DEFAULT_B;
+
+    vreg_ctr[ VREG_C_OFF_DELAY ] = FORCEOFF_THREASHOLD;
+
+    vreg_ctr[ VREG_C_VOL_CAL_MIN ] = 0x36;
+    vreg_ctr[ VREG_C_VOL_CAL_MAX ] = 0xFF - 0x36;
+
+	vreg_ctr[ VREG_C_RBR_CONTROL ] = REG_BIT_RESET_n; // todo | REG_BIT_FLIGHT;
+}
+
+
+// ********************************************************
+// �{�̂̓d���������ɃZ�b�g����܂�
+void vreg_ctr_reset(  )
+{
+    vreg_ctr[ VREG_C_MCU_VER_MAJOR ] = MCU_VER_MAJOR | 0x10;
+    vreg_ctr[ VREG_C_MCU_VER_MINOR ] = MCU_VER_MINOR;
+
+    vreg_ctr[ VREG_C_LED_BRIGHT ] = 0xFF;
+    vreg_ctr[ VREG_C_LED_POW ] = 0;
+    vreg_ctr[ VREG_C_LED_WIFI ] = 0;
+    vreg_ctr[ VREG_C_LED_CAM ] = 0;
+    vreg_ctr[ VREG_C_LED_3D ] = 0;
+//    vreg_ctr[ VREG_C_VOL_CAL_MIN ] = 0x36;            �����ŏ�������_���I
+//    vreg_ctr[ VREG_C_VOL_CAL_MAX ] = 0xFF - 0x36;     �d������邽�тɃf�t�H���g�l�ɂȂ��Ă��܂�
+    {
+        u8 i;
+        for( i = 0; i < sizeof( uni_info_LED ); i++ )
+        {
+            info_LED.bindata[ i ] = 0;
+        }
+    }
+}
+
+
+
+// ********************************************************
+// I2C���z���W�X�^�ɏ����܂��B
+//�@���� adrs �͓����A�h���X
+//  �@�����Ȃ��A�h���X�ɃA�N�Z�X�����ꍇ�A�������܂���B
+// ���������񂾌��ʁAI2C_mcu�ʐM����������ꍇ�Arenge_task_immed_add()
+//  ���g�p���Ȃ��ƁAI2C_mcu�g�p���ŃG���[�I�������ꍇ�Ƀ��g���C���܂���B
+void vreg_ctr_write( u8 adrs, u8 data )
+{
+    switch ( adrs )
+    {
+
+    case ( VREG_C_MCU_STATUS ):
+//        vreg_twl[ REG_TWL_INT_ADRS_MODE ] = (u8)( ( data >> 6 ) & 0x03 ); R�ł悢�B���̑��胊�Z�b�g�ŃN���A
+        vreg_ctr[ VREG_C_MCU_STATUS ] &= data;  // bit�N���A�͂��邪�Z�b�g�͂��Ȃ��B
+												// ��̕���twl���W�X�^�~���[�͓ǂݏo���ꎞ�ɍ���
+        break;
+
+    case ( VREG_C_VCOM_T ):
+    case ( VREG_C_VCOM_B ):
+        renge_task_immed_add( tski_vcom_set );
+        vreg_ctr[adrs] = data;
+        break;
+
+    case ( VREG_C_DBG03 ):
+        if( ( vreg_ctr[VREG_C_DBG01] == 'j' )
+            && ( vreg_ctr[VREG_C_DBG02] == 'h' )
+            && ( data == 'l' ) )
+        {
+            renge_task_immed_add( tski_firm_update );
+            IICAMK = 1;
+        }
+        vreg_ctr[ VREG_C_DBG03 ] = data;
+        break;
+
+    case ( VREG_C_COMMAND0 ):
+        if( data != 0 )
+        {
+            renge_task_immed_add( tski_do_command0 );
+	        vreg_ctr[ VREG_C_COMMAND0 ] |= data;
+        }
+        break;
+
+    case ( VREG_C_COMMAND2 ):
+        // �����炩��̊������荞�݂�҂��Ă���Ȃ������ł��B #-��-) ���̂��߂̊��荞�݂�
+        // �t���d��
+        if(( data & REG_BIT_CMD_LCD_ON ) != 0 )
+        {
+            renge_task_immed_add( tski_PM_LCD_on );
+        }
+        else if(( data & REG_BIT_CMD_LCD_OFF ) != 0 )
+        {
+            renge_task_immed_add( tski_PM_LCD_off );
+        }
+
+        // �o�b�N���C�g�ݒ�
+        /// ���̂Ƃ��낳��ɍׂ����͕����Ȃ����ǁc
+        if(( data & REG_BITS_CMD_BL ) != 0 )
+        {
+            renge_task_immed_add( tski_PM_BL_set );
+            vreg_ctr[adrs] = (u8)( data & REG_BITS_CMD_BL );
+        }
+        break;
+
+    case ( VREG_C_COMMAND1 ):
+        if( data != 0 )
+        {
+            // u8 temp; ���ԕϐ��g������΂��ł����Ȃ���...
+            // TWL�Ɋ��荞�݂�����
+            /// ���ۂɊ��荞�݂�����̂�SoC
+            /// �r�b�g�̕��т��Ⴄ����ʓ|
+            vreg_twl[ REG_TWL_INT_ADRS_IRQ ]  = ( ( data & REG_BIT_SEND_TWL_PWSW_DET )   != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00;  //pwsw_det
+            vreg_twl[ REG_TWL_INT_ADRS_IRQ ] |= ( ( data & REG_BIT_SEND_TWL_RESET_DET )  != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00;     //reset_req
+
+            vreg_twl[ REG_TWL_INT_ADRS_IRQ ] |= ( ( data & REG_BIT_SEND_TWL_OFF_DET )    != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00;       //off_req
+
+            vreg_twl[ REG_TWL_INT_ADRS_IRQ ] |= ( ( data & REG_BIT_SEND_TWL_BATT_LOW )   != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00;    //batt_low
+            vreg_twl[ REG_TWL_INT_ADRS_IRQ ] |= ( ( data & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00;  //batt_empty
+
+            if(( data & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 )
+            {
+                vreg_twl[ REG_TWL_INT_ADRS_IRQ ] |= REG_BIT_TWL_IRQ_VOL_CHANGE; //vol_changed
+            }
+        }
+        break;
+
+    case ( VREG_C_LED_POW ):
+        if( iic_burst_state == 0 )
+        {
+            vreg_ctr[ VREG_C_LED_POW ] = data;
+            iic_burst_state ++;
+        }
+        else if( iic_burst_state < 5 )
+        {
+            led_red_batt_empty.dats[ iic_burst_state -1 ] = data;
+            iic_burst_state ++;
+        }
+        break;
+
+    case ( VREG_C_LED_WIFI ):
+    case ( VREG_C_LED_CAM ):
+    case ( VREG_C_LED_3D ):
+        vreg_ctr[adrs] = (u8)( data & 0x0F );
+        break;
+
+    case ( VREG_C_LED_NOTIFY_DATA ):
+        if( iic_burst_state < sizeof( uni_info_LED ) )
+        {
+            if(( iic_burst_state == 1 ) && ( data == 0 ))  // fade_time == 0 �֎~
+            {
+                data = 1;
+            }
+            info_LED.bindata[ iic_burst_state ] = data;
+            iic_burst_state ++;
+            if( iic_burst_state > 4 )             // �p�^�[����1�����ł�������
+            {
+                info_led_pattern_updated = true;
+            }
+        }
+        break;
+
+    /// �񓯊��œ����Ă��邽�߂����ł͏����Ȃ��B
+    // �\�񂷂邾����stop�ŏ���
+    case ( VREG_C_RTC_SEC ):
+    case ( VREG_C_RTC_MIN ):
+        set_rtc( adrs - VREG_C_RTC_SEC, data & 0x7F );
+        break;
+
+    case ( VREG_C_RTC_DAY ):
+    case ( VREG_C_RTC_HOUR ):
+        set_rtc( adrs - VREG_C_RTC_SEC, data & 0x3F );
+        break;
+
+    case ( VREG_C_RTC_YOBI ):
+        set_rtc( adrs - VREG_C_RTC_SEC, data & 0x07 );
+        break;
+
+    case ( VREG_C_RTC_MONTH ):
+        set_rtc( adrs - VREG_C_RTC_SEC, data & 0x1F );
+        break;
+
+    case ( VREG_C_RTC_YEAR ):
+        set_rtc( adrs - VREG_C_RTC_SEC, data );
+        break;
+
+    case ( VREG_C_RTC_COMP ):
+        WDT_Restart();
+        while(1)
+        {
+            RWAIT = 1;
+            while( !RWST ){}
+            if( SEC != 0 )
+            {
+                break;
+            }
+            RWAIT = 0;
+        }
+        SUBCUD = data;
+        RWAIT = 0;
+        vreg_ctr[ VREG_C_RTC_COMP ] = data;
+        break;
+
+    case ( VREG_C_RTC_ALARM_MIN ):
+        rtc_alarm_dirty = true;
+        vreg_ctr[ VREG_C_RTC_ALARM_MIN ] = (u8)( data & 0x7F );
+        break;
+
+    case ( VREG_C_RTC_ALARM_HOUR ):
+        rtc_alarm_dirty = true;
+        vreg_ctr[ VREG_C_RTC_ALARM_HOUR ] = (u8)( data & 0x3F );
+        break;
+
+        // ���������ł悢
+    case ( VREG_C_RTC_ALARM_DAY ):
+        vreg_ctr[ VREG_C_RTC_ALARM_DAY ] = (u8)( data & 0x3F );
+        break;
+
+    case ( VREG_C_RTC_ALARM_MONTH ):
+        vreg_ctr[ VREG_C_RTC_ALARM_MONTH ] = (u8)( data & 0x1F );
+        break;
+
+    case ( VREG_C_ACC_CONFIG ):
+        renge_task_immed_add( tski_acc_setup );
+        vreg_ctr[ VREG_C_ACC_CONFIG ] = data;
+        break;
+
+    case ( VREG_C_ACC_R_ADRS ):
+        renge_task_immed_add( tski_acc_read );
+        vreg_ctr[ VREG_C_ACC_R_ADRS ] = data;
+        break;
+
+    case ( VREG_C_ACC_W_BUF ):
+        renge_task_immed_add( tski_acc_write );
+        vreg_ctr[ VREG_C_ACC_W_BUF ] = data;
+        break;
+
+    case ( VREG_C_ACC_HOSU_SETTING ):
+        if( ( data & 0x01 ) != 0 )
+        {
+            clear_hosu_hist(); // �����N���A
+        }
+        break;
+
+    case ( VREG_CX_FREE_DATA ):
+        if( vreg_free_adrs < VREG_C_FREE_SIZE )
+        {
+            pool.vreg_c_ext.vreg_c_free[ vreg_free_adrs ] = data;
+            vreg_free_adrs ++;
+        }
+        break;
+
+    case ( VREG_CX_FREE_ADRS ):
+        vreg_free_adrs = data;
+        break;
+
+    case ( VREG_C_RBR_CONTROL ):
+        if(( data & REG_BIT_RESET_n ) != 0 )
+        {
+            RBR_RESET_n = 1;
+        }
+        else
+        {
+            RBR_RESET_n = 0;
+        }
+        if(( data & REG_BIT_FLIGHT ) != 0 )
+        {
+            RBR_FLIGHT  = 1;
+        }
+        else
+        {
+            RBR_FLIGHT  = 0;
+        }
+        vreg_ctr[ VREG_C_RBR_CONTROL ] = data;
+        break;
+
+	case ( VREG_C_COMMAND3 ):
+        switch ( data )
+        {
+#ifdef _ENABLE_COMMAND3_
+        case ( 'r' ):
+            // ���荞�݃��[�`������FSL���C�u�������ĂԂ̂͋֎~
+            // �}�C�R�����ċN���B�@���W�X�^�ނ������������B
+            renge_task_immed_add( tski_mcu_reset );
+            break;
+
+        case ( 'w' ):
+            // WDT�ōċN���i�e�X�g�����j
+//            mcu_wdt_reset;  // ���̃R�}���h�g������Ӗ��Ȃ��ł���I
+            while(1)
+            {
+                dbg_NOP();
+            }
+            break;
+#endif //_ENABLE_COMMAND3_
+
+#ifdef _ENABLE_HAL_
+		case( 'p' ):
+			reserve_pedo_increnent = 1;
+			// �����ő��₷�ɂ̓X�^�b�N������Ȃ��B���ŗ\��̂݁Atask_misc���ŏ���
+//			hosu_increment_if_necessary();		// ���A���������
+			break;
+#endif //_ENABLE_HAL_
+
+        }
+//        vreg_ctr[ VREG_C_COMMAND3 ] = data;	// �����K�v�Ȃ�
+        break;
+
+	// read only //////////////////////////////////////////
+    case VREG_C_MCU_VER_MAJOR:
+    case VREG_C_MCU_VER_MINOR:
+	case VREG_C_3D:             // �����Ƀ��t���b�V�������
+    case VREG_C_SND_VOL:		// �����Ƀ��t���b�V�������
+    case VREG_C_BT_TEMP:		// �����Ƀ��t���b�V�������
+    case VREG_C_BT_REMAIN:      // �����Ƀ��t���b�V�������
+    case VREG_C_BT_REMAIN_FINE:	// �����Ƀ��t���b�V�������
+    case VREG_C_BT_VOLTAGE:     // �����Ƀ��t���b�V�������
+	case VREG_C_STATUS_1:		// �K���Ƀ��t���b�V�������
+    case VREG_C_STATUS:			// �K���Ƀ��t���b�V�������
+    case VREG_C_IRQ0:			// ���̂‚��łɊ��荞�݋N�����Ăق����Ȃ�...
+    case VREG_C_IRQ1:
+    case VREG_C_IRQ2:
+    case VREG_C_IRQ3:
+    case VREG_C_IRQ4:
+    case VREG_C_LED_NOTIFY_FLAG: // �������t���b�V�������
+    case VREG_C_RTC_SEC_FINE_L:	// �������t���b�V�������
+    case VREG_C_RTC_SEC_FINE_H:	// �������t���b�V�������
+        //  VREG_C_ACC_RESERVE,	// �����N���Ȃ�
+        //  VREG_C_ACC_HOSU_HIST = 0x4F,
+	case VREG_C_ACC_XH:				// �������t���b�V�������
+	case VREG_C_ACC_XL:
+	case VREG_C_ACC_YH:
+	case VREG_C_ACC_YL:
+	case VREG_C_ACC_ZH:
+	case VREG_C_ACC_ZL:
+//        dbg_nop();
+		// return( ERROR )
+        break;
+
+	case VREG_C_ACC_HOSU_L:	// �����Ă��������ǁA�f�o�b�O�p�B(�A�h���X0x4B == mcu sla(r))
+//        dbg_nop();
+        /* FALLTHROUGH */
+
+    // ���ʂɏ�����邾�� /////////////////////////////////
+	default:
+        /*
+    case VREG_C_IRQ_MASK0:
+    case VREG_C_IRQ_MASK1:
+    case VREG_C_IRQ_MASK2:
+    case VREG_C_IRQ_MASK3:
+    case VREG_C_IRQ_MASK4:
+    case VREG_C_DBG01:
+    case VREG_C_DBG02:
+    case VREG_C_LED_BRIGHT:
+    case VREG_C_ACC_HOSU_L:
+    case VREG_C_ACC_HOSU_M:
+    case VREG_C_ACC_HOSU_H:
+    case VREG_C_ACC_HOSU_HOUR_BOUNDARY:
+    case VREG_C_FREE_ADRS:
+    case VREG_C_RTC_ALARM_YEAR:
+    case VREG_C_ACC_W_ADRS:
+    case VREG_C_OFF_DELAY:
+    case VREG_C_HAL_OVW_CONT0:
+    case VREG_C_HAL_OVW_DAT0:
+    case VREG_C_HAL_OVW_CONT1:
+    case VREG_C_HAL_OVW_DAT1:
+        */
+        if( adrs < VREG_C_ENDMARK_ )
+        {
+            vreg_ctr[adrs] = data;
+            break;
+        }
+        else
+        {
+//            dbg_nop();		// ����`�A�h���X�ɏ������@�Ȃ񂩃o�O���ĂȂ��H
+			// return( ERROR )
+            break;
+        }
+    }
+//	return( SUCCESS )
+	return;
+}
+
+
+
+
+// ********************************************************
+// I2C���z���W�X�^����ǂ݂܂��B
+// �߂�F xx �f�[�^
+// ���ӁF���̃A�h���X�̏����ŌĂ΂�� �̂ŁA
+//       ���[�h���ꂽ��N���A�Ȃǂ͋C���‚���
+//       ( ��vreg_ctr_after_read( u8 adrs ) )
+u8 vreg_ctr_read( u8 adrs )
+{
+    static u16 rsub_temp;
+    u8 temp;
+
+    // RTC�͓ǂݏo���r���ɌJ��オ��̂�����邽��
+    if( ( VREG_C_RTC_SEC <= adrs ) && ( adrs <= VREG_C_RTC_YEAR ) )
+    {
+        rtc_buf_refresh(  );
+    }
+    else if( adrs == VREG_C_MCU_STATUS )
+    {
+        return( ( vreg_ctr[ VREG_C_MCU_STATUS ] & 0x03 ) |
+            ( ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x03 ) << 6 ) |  // sys_mode
+            ( ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x80 ) >> 2 ));   // vol32
+    }
+    else if( adrs == VREG_C_RTC_SEC_FINE_L )
+    {
+        rsub_temp = RSUBC;
+        return( (u8)( rsub_temp & 0xFF ) );
+    }
+    else if( adrs == VREG_C_RTC_SEC_FINE_H )
+    {
+        return( (u8)( ( rsub_temp >> 8 ) & 0xFF ) );
+    }
+/*
+	// debug �I��
+	else if( adrs == VREG_C_IRQ_MASK0 )
+    {
+        return( vreg_ctr[ VREG_C_IRQ_MASK0 ] & 0x7F );  // ���`��������MSB��0�B1�Ȃ�ʐM�G���[
+    }
+*/
+	else if( adrs == VREG_C_ACC_HOSU_HIST )
+    {
+        return( hosu_read() );
+    }
+    else if( adrs == VREG_CX_FREE_DATA )
+    {
+        temp = pool.vreg_c_ext.vreg_c_free[ vreg_free_adrs ];
+        // vreg_free_adrs ++;  // �����ʼn��Z���Ă��܂��ƃC���f�b�N�X�������
+        return( temp );
+    }
+    else if( adrs == VREG_CX_INFO )
+    {
+        return( extinfo_read() );
+    }
+    else if( adrs == VREG_C_ACC_HOSU_SETTING )
+    {
+        if( pedolog_overflow )
+        {
+            return( 0x10 );
+        }
+        else
+        {
+            return( 0 );
+        }
+    }
+
+    if( adrs >= VREG_C_ENDMARK_ )
+    {
+        // VREG_C_INFO > VREG_C_ENDMARK_ �Ȃ̂ł�����Ƃ�����
+        return( 0xFF );
+    }
+    return ( vreg_ctr[adrs] );
+}
+
+
+
+// ********************************************************
+// I2C���z���W�X�^����ǂ܂�ĉ������郌�W�X�^
+void vreg_ctr_after_read( u8 adrs, u8 data )
+{
+    // ���荞�݃t���O�̓��[�h�ŃN���A
+    switch( adrs )
+    {
+    case VREG_C_IRQ0:
+    case VREG_C_IRQ1:
+    case VREG_C_IRQ2:
+    case VREG_C_IRQ3:
+    case VREG_C_IRQ4:
+        DI_wt_chk();
+        vreg_ctr[ adrs ] ^= data;
+        EI();
+        irq_readed = true;
+        break;
+
+    case VREG_CX_FREE_DATA:
+        vreg_free_adrs ++;
+        break;
+
+    default:
+        break;
+    }
+}
+
+
+
+
+
+
+/******************************************************************************
+  ���荞�݂�����
+
+  �@�}�X�N����Ă���A�t���O�u���ĂȂ��v�A���荞�ݓ���Ȃ��B
+  �@���荞�݂����A�ǂݏo�����O�Ƀ}�X�N�����������Ƃ��́ASoC��̏����L���[��ɂ�
+  IRQ��ǂރ^�X�N���ς�ł���̂ŁA�ǂ݂ɂ͗���B
+  �@����ƁA�O�̂��߁A�}�X�N��������Ƃ��͋�ǂ݂��Ă��炤�B
+   �����ł�DI���̃`�F�b�N�s�v�B
+   �@DI���ɗ���̂�I2C_twl���ARTC_�A���[���B���̒��Ŗ��ڒ���EI���Ď��g�p����Ȃ�
+  *****************************************************************************/
+void set_irq( u8 irqreg, u8 irq_flg )
+{
+    u8 tot;
+//0	u8 ei_orig;		// EI�t���O�ۑ�
+
+    if(( system_status.pwr_state == ON ) ||
+       ( system_status.pwr_state == SLEEP ))
+    {
+/*0	���ł�DI��ԂȂ�P�A���K�v��������Ȃ�
+		ei_orig = get_ei();
+		
+		//. debug
+		if( !ei_orig )
+		{
+			dbg_nop();
+		}
+
+		DI_wt_chk();
+*/
+		DI();
+        if( ( vreg_ctr[ irqreg + 8 ] & irq_flg ) == 0 )
+		{
+            vreg_ctr[ irqreg ] |= irq_flg;
+            IRQ0_neg;   // ��u�グ��...
+//0			if( ei_orig )
+			{
+				EI();
+			}
+            tot = 0;
+            while( !IRQ0 && ( ++tot != 0 ) ){;}   // O.D.�Ȃ̂ł����Ƃ�����̂�҂� �� IRQ_mcu ��L�ɔ����Ă�ƍ���(��•s��)
+            IRQ0_ast;   // ���Ƃ������B�i�G�b�W���荞�ׁ݂̈j
+        }
+//0		if( ei_orig )
+		{
+			EI();
+		}
+    }
+}
+
diff --git a/tags/2.03_SDK-3.1/vreg_ctr.h b/tags/2.03_SDK-3.1/vreg_ctr.h
new file mode 100644
index 0000000..9e0b11e
--- /dev/null
+++ b/tags/2.03_SDK-3.1/vreg_ctr.h
@@ -0,0 +1,302 @@
+#ifndef __vreg_ctr__
+#define __vreg_ctr__
+
+
+#include "config.h"
+
+// VREG_C_MCU_STATUS
+// bit[7.6] twl.sys_mode��[1.0]     ctr���珑���Ȃ����Afcr_reset���ɓK���Ƀ��Z�b�g
+// bit[5]         �V      [7]       ctr���珑���Ȃ����Afcr_reset���ɓK���Ƀ��Z�b�g
+#define REG_BIT_STATUS_WDT_RESET    ( 1 << 1 )
+#define REG_BIT_RTC_BLACKOUT        ( 1 << 0 )
+
+
+//  VREG_C_STATUS,
+#define REG_BIT_LCD_POW             ( 1 << 7 )
+#define REG_BIT_BL_U                ( 1 << 6 )
+#define REG_BIT_BL_L                ( 1 << 5 )
+#define REG_BIT_BATT_CHARGE         ( 1 << 4 )
+#define REG_BIT_POW_SUPPLY          ( 1 << 3 )
+//                           ���g�p ( 1 << 2 )
+#define REG_BIT_ST_SHELL_OPEN       ( 1 << 1 )
+//                           ���g�p ( 1 << 0 )
+
+
+//  VREG_C_STATUS_X
+//                           ���g�p ( 1 << 6 )
+//                           ���g�p ( 1 << 5 )
+#define REG_BIT_WIFI_TX             ( 1 << 4 )
+//               twl bl �̃~���[[1: ( 1 << 3 )
+//                                0]( 1 << 2 )
+#define REG_BIT_ACCERO_ERR          ( 1 << 1 )
+#define REG_BIT_MGIC_ERR            ( 1 << 0 )
+
+#define REG_BIT_MASK_STATUS1_NTR_PM_REG	0x0C
+
+
+//  VREG_C_IRQ0
+#define REG_BIT_IRQ_WDT_RESET       ( 1 << 7 )
+#define REG_BIT_SHELL_OPEN          ( 1 << 6 )
+#define REG_BIT_SHELL_CLOSE         ( 1 << 5 )
+#define REG_BIT_SW_WIFI_CLICK       ( 1 << 4 )
+#define REG_BIT_SW_HOME_RELEASE     ( 1 << 3 )
+#define REG_BIT_SW_HOME_CLICK       ( 1 << 2 )
+#define REG_BIT_SW_POW_HOLD         ( 1 << 1 )
+#define REG_BIT_SW_POW_CLICK        ( 1 << 0 )
+
+//  VREG_C_IRQ1
+#define REG_BIT_BT_CHG_START        ( 1 << 7 )
+#define REG_BIT_BT_CHG_STOP         ( 1 << 6 )
+#define REG_BIT_BT_REMAIN           ( 1 << 5 )
+#define REG_BIT_ACC_DAT_RDY         ( 1 << 4 )
+#define REG_BIT_ACC_ACK             ( 1 << 3 )
+#define REG_BIT_RTC_ALARM           ( 1 << 2 )
+#define REG_BIT_BT_DC_CONNECT       ( 1 << 1 )
+#define REG_BIT_BT_DC_DISC          ( 1 << 0 )
+
+//  VREG_C_IRQ2
+#define REG_BIT_TWL_VER_READ        ( 1 << 7 )
+//#define REG_BIT_TWL_SNDVOL_CHANGE   ( 1 << 6 ) �p�~
+#define REG_BIT_SLIDE_VOL_ACROSS_TWL_BOUNDARY   ( 1 << 6 )
+#define REG_BIT_TWL_BL_U_ON         ( 1 << 5 )
+#define REG_BIT_TWL_BL_U_OFF        ( 1 << 4 )
+#define REG_BIT_TWL_BL_L_ON         ( 1 << 3 )
+#define REG_BIT_TWL_BL_L_OFF        ( 1 << 2 )
+#define REG_BIT_TWL_OFF_REQ         ( 1 << 1 )
+#define REG_BIT_TWL_RESET_REQ       ( 1 << 0 )
+
+//  VREG_C_IRQ3
+#define REG_BIT_BL_U_ON             ( 1 << 5 )
+#define REG_BIT_BL_U_OFF            ( 1 << 4 )
+#define REG_BIT_BL_L_ON             ( 1 << 3 )
+#define REG_BIT_BL_L_OFF            ( 1 << 2 )
+#define REG_BIT_LCD_ON              ( 1 << 1 )
+#define REG_BIT_LCD_OFF             ( 1 << 0 )
+
+
+// ���̂����ǂ�����...
+//#define REG_BIT_VR_3D_CHANGE      ( 1 << 7 )
+
+
+
+// VREG_C_COMMAND0
+//#define REG_BIT_CMD_LCD_ON              ( 1 << 7 )
+//#define REG_BIT_CMD_LCD_OFF             ( 1 << 6 )
+//#define REG_BIT_CMD_BL_ON               ( 1 << 5 )
+//#define REG_BIT_CMD_BL_OFF              ( 1 << 4 )
+#define REG_BIT_GOING_TO_SLEEP      ( 1 << 4 )
+#define REG_BIT_FCRAM_RESET_REQ     ( 1 << 3 )
+#define REG_BIT_RESET2_REQ          ( 1 << 2 )
+#define REG_BIT_RESET1_REQ          ( 1 << 1 )
+#define REG_BIT_OFF_REQ             ( 1 << 0 )
+
+// VREG_C_COMMAND1 (TWL�Ɋ��荞�݂�����)
+//                           ���g�p ( 1 << 7 )
+//                           ���g�p ( 1 << 6 )
+#define REG_BIT_SEND_TWL_VOL_CLICK  ( 1 << 5 )
+#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
+#define REG_BIT_SEND_TWL_BATT_LOW   ( 1 << 3 )
+#define REG_BIT_SEND_TWL_OFF_DET    ( 1 << 2 )
+#define REG_BIT_SEND_TWL_RESET_DET  ( 1 << 1 )
+#define REG_BIT_SEND_TWL_PWSW_DET   ( 1 << 0 )
+
+// VREG_C_COMMAND2 �t���֌W
+#define REG_BIT_CMD_BL_U_ON         ( 1 << 5 )
+#define REG_BIT_CMD_BL_U_OFF        ( 1 << 4 )
+#define REG_BIT_CMD_BL_L_ON         ( 1 << 3 )
+#define REG_BIT_CMD_BL_L_OFF        ( 1 << 2 )
+#define REG_BIT_CMD_LCD_ON          ( 1 << 1 )
+#define REG_BIT_CMD_LCD_OFF         ( 1 << 0 )
+#define REG_BITS_CMD_BL             ( REG_BIT_CMD_BL_U_ON | REG_BIT_CMD_BL_U_OFF | REG_BIT_CMD_BL_L_ON | REG_BIT_CMD_BL_L_OFF )
+
+
+// ��TWL�ɒʒm����IRQ���W�X�^
+#define REG_BIT_TWL_IRQ_PWSW_DET 0x08
+#define REG_BIT_TWL_IRQ_RESET    0x01
+#define REG_BIT_TWL_IRQ_OFF      0x02
+#define REG_BIT_TWL_IRQ_BT_LOW   0x20
+#define REG_BIT_TWL_IRQ_BT_EMPTY 0x10
+#define REG_BIT_TWL_IRQ_VOL_CHANGE 0x40
+
+
+// CODEC���PMIC NTR �̑㗝���W�X�^
+#define REG_BIT_TWL_REQ_OFF            ( 1 << 6 )
+#define REG_BIT_TWL_REQ_BL_U           ( 1 << 3 )
+#define REG_BIT_TWL_REQ_BL_L           ( 1 << 2 )
+#define REG_BIT_TWL_REQ_RESET          ( 1 << 0 )
+
+
+// VREG_C_LED_NOTIFY_FLAG
+#define REG_BIT_IN_LOOP                ( 1 << 0 )
+
+// RBR control (0x57)
+#define REG_BIT_FLIGHT              ( 1 << 1 )
+#define REG_BIT_RESET_n             ( 1 << 0 )
+
+
+// HAL bitfields 0
+#define REG_BIT_HAL0_PM_EXTDC_n     ( 1 << 7 )
+#define REG_BIT_HAL0_BT_IN_CHG_n    ( 1 << 6 )
+//#define REG_BIT_HAL0_PM_IRQ_n                 // �g��Ȃ�
+#define REG_BIT_HAL0_RSV_5          ( 1 << 5 ) 
+#define REG_BIT_HAL0_WL_TX          ( 1 << 4 )
+#define REG_BIT_HAL0_SHELL_OPEN     ( 1 << 3 )            // status�ɂ���܂�
+#define REG_BIT_HAL0_SW_WIFI_n      ( 1 << 2 )
+#define REG_BIT_HAL0_SW_HOME_n      ( 1 << 1 )
+#define REG_BIT_HAL0_SW_POW_n       ( 1 << 0 )
+
+
+// HAL bitfields 1
+#define REG_BIT_HAL1_DIPSW_1        ( 1 << 3 )
+#define REG_BIT_HAL1_DIPSW_0        ( 1 << 2 )
+#define REG_BIT_HAL1_HW_DET_1       ( 1 << 1 )
+#define REG_BIT_HAL1_HW_DET_0       ( 1 << 0 )
+
+/*
+  �e���v��
+#define REG_BIT_                    ( 1 << 7 )
+#define REG_BIT_                    ( 1 << 6 )
+#define REG_BIT_                    ( 1 << 5 )
+#define REG_BIT_                    ( 1 << 4 )
+#define REG_BIT_                    ( 1 << 3 )
+#define REG_BIT_                    ( 1 << 2 )
+#define REG_BIT_                    ( 1 << 1 )
+#define REG_BIT_                    ( 1 << 0 )
+*/
+
+
+
+/*============================================================================*/
+extern u8 vreg_ctr[];
+
+/*============================================================================*/
+enum VREG_C_ADRS
+{                               // ����`�A�h���X�֏������񂾍ۂ̓���͕s��
+  VREG_C_MCU_VER_MAJOR = 0x00,
+  VREG_C_MCU_VER_MINOR,
+  VREG_C_MCU_STATUS,
+
+  VREG_C_VCOM_T = 0x03,
+  VREG_C_VCOM_B,
+
+  VREG_C_DBG01 = 0x05,
+  VREG_C_DBG02,
+  VREG_C_DBG03,
+
+  VREG_C_3D = 0x08,
+  VREG_C_SND_VOL,
+  VREG_C_BT_TEMP,
+  VREG_C_BT_REMAIN,
+  VREG_C_BT_REMAIN_FINE,
+  VREG_C_BT_VOLTAGE,
+
+  VREG_C_STATUS_1 = 0x0E,
+  VREG_C_STATUS = 0x0F,
+
+  VREG_C_IRQ0 = 0x10,
+  VREG_C_IRQ1,
+  VREG_C_IRQ2,
+  VREG_C_IRQ3,
+  VREG_C_IRQ4,
+
+  VREG_C_IRQ_MASK0 = 0x18,
+  VREG_C_IRQ_MASK1,
+  VREG_C_IRQ_MASK2,
+  VREG_C_IRQ_MASK3,
+  VREG_C_IRQ_MASK4,
+
+  VREG_C_COMMAND0 = 0x20,
+  VREG_C_COMMAND1,
+  VREG_C_COMMAND2,
+  VREG_C_COMMAND3,  // 'r' �Ń}�C�R�����Z�b�g�A 'w' ��WDT���Z�b�g
+
+  VREG_C_OFF_DELAY = 0x24,
+//  VREG_C_VOL_DIGITAL = 0x25,  // todo ������
+//  VREG_C_VOL_OPTION,
+  VREG_C_VOL_ADC_RAW = 0x27,
+
+  VREG_C_LED_BRIGHT = 0x28,
+  VREG_C_LED_POW,
+  VREG_C_LED_WIFI,
+  VREG_C_LED_CAM,
+  VREG_C_LED_3D,
+  VREG_C_LED_NOTIFY_DATA,
+  VREG_C_LED_NOTIFY_FLAG,
+
+  VREG_C_RBR_CONTROL = 0x2F,
+
+  VREG_C_RTC_SEC = 0x30,
+  VREG_C_RTC_MIN,
+  VREG_C_RTC_HOUR,
+  VREG_C_RTC_YOBI,
+  VREG_C_RTC_DAY,
+  VREG_C_RTC_MONTH,
+  VREG_C_RTC_YEAR,
+
+  VREG_C_RTC_COMP,
+
+  VREG_C_RTC_ALARM_MIN = 0x38,
+  VREG_C_RTC_ALARM_HOUR,
+  VREG_C_RTC_ALARM_DAY,
+  VREG_C_RTC_ALARM_MONTH,
+  VREG_C_RTC_ALARM_YEAR,
+
+  VREG_C_RTC_SEC_FINE_L,
+  VREG_C_RTC_SEC_FINE_H,
+
+  VREG_C_ACC_CONFIG = 0x40,
+  VREG_C_ACC_R_ADRS,
+  VREG_C_ACC_RESERVE,
+  VREG_C_ACC_W_ADRS,
+  VREG_C_ACC_W_BUF,
+
+  VREG_C_ACC_XL = 0x45,
+  VREG_C_ACC_XH,
+  VREG_C_ACC_YL,
+  VREG_C_ACC_YH,
+  VREG_C_ACC_ZL,
+  VREG_C_ACC_ZH,
+
+  VREG_C_ACC_HOSU_L = 0x4B,
+  VREG_C_ACC_HOSU_M,
+  VREG_C_ACC_HOSU_H,
+  VREG_C_ACC_HOSU_SETTING,
+  VREG_C_ACC_HOSU_HIST = 0x4F,
+  
+  VREG_C_ACC_HOSU_HOUR_BOUNDARY = 0x50,
+  VREG_C_ACC_HOSU_HOUR_BOUNDARY_SEC,
+
+  VREG_C_HAL_OVW_CONT0 = 0x52,
+  VREG_C_HAL_OVW_DAT0,
+  VREG_C_HAL_OVW_CONT1,				// reserved
+  VREG_C_HAL_OVW_DAT1,				// reserved
+
+  VREG_C_HAL_OVW_BT_FUEL = 0x56,
+  VREG_C_HAL_OVW_BT_VOLTAGE,
+
+  VREG_C_VOL_CAL_MIN = 0x58,
+  VREG_C_VOL_CAL_MAX,
+
+  VREG_C_HAL_OVW_TEMPERATURE = 0x5A,
+
+  VREG_C_ENDMARK_
+};
+
+// ���Ԃ͔����ɂ��āA���������m�ۂ��Ȃ����߂� �ʂ� define ���Ă�
+#define VREG_CX_INFO 0x7F
+#define VREG_CX_FREE_ADRS 0x60
+#define VREG_CX_FREE_DATA 0x61
+//  VREG_C_AMBIENT_BRIGHTNESS = 0xXX,
+
+
+
+
+/*============================================================================*/
+void vreg_ctr_init(  );
+void vreg_ctr_reset(  );
+void vreg_ctr_write( u8 adrs, u8 data );
+u8 vreg_ctr_read( u8 phy_adrs );
+void vreg_ctr_after_read( u8 adrs, u8 data );
+void set_irq( u8 irqreg, u8 irq_flg );
+
+#endif
diff --git a/tags/2.03_SDK-3.1/vreg_twl.c b/tags/2.03_SDK-3.1/vreg_twl.c
new file mode 100644
index 0000000..15e971a
--- /dev/null
+++ b/tags/2.03_SDK-3.1/vreg_twl.c
@@ -0,0 +1,156 @@
+/* ========================================================
+
+TWL�݊�����I2C���W�X�^
+
+ ======================================================== */
+#include "incs.h"
+#include "jhl_defs.h"
+#include "led.h"
+
+#include "vreg_twl.h"
+#include "vreg_ctr.h"
+
+// ========================================================
+#define TWL_REG_VER_INFO               0x35
+#define NON_EXIST_REG                  0xFF
+
+// ========================================================
+u8      vreg_twl[_REG_TWL_INT_ADRS_ENDMARK];
+
+
+extern bit twl_ver_read;
+extern bit cam_led_update;
+extern bit vol_changed_by_twl;
+
+
+// ========================================================
+extern void tsk_led_cam();
+
+
+
+
+/* ========================================================
+  ���z���W�X�^�̏�����
+ ======================================================== */
+void vreg_twl_init(  )
+{
+    vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03;
+    vreg_twl[ REG_TWL_INT_ADRS_IRQ ] = 0;
+    vreg_twl[ REG_TWL_INT_ADRS_CAM ] = 0;
+    vreg_twl[ REG_TWL_INT_ADRS_TEMP0 ] = 0;
+}
+
+// ========================================================
+// I2C���z���W�X�^�ɏ����E�����A�N�V��������
+//�@���� adrs �͓����A�h���X
+//  �@���݂��Ȃ��A�h���X�ɃA�N�Z�X�����ꍇ�A�������܂���B
+void vreg_twl_write( u8 adrs, u8 data )
+{
+    switch ( adrs )
+    {
+      case ( REG_TWL_INT_ADRS_VOL ):
+        {
+            vol_changed_by_twl = true;
+            vreg_twl[ REG_TWL_INT_ADRS_VOL ] = data;
+            //renge_task_immed_add( tski_vol_update );
+            vol_polling = 3;
+            break;
+        }
+
+      case ( REG_TWL_INT_ADRS_MODE ):
+        vreg_twl[ REG_TWL_INT_ADRS_MODE ] = ( data & 0x83 );  // [8]vol32 [1:0]nand
+        break;
+
+      case ( REG_TWL_INT_ADRS_CAM ):
+        vreg_twl[ REG_TWL_INT_ADRS_CAM ] = ( data & 0x03 );
+        if( ( data & 0x03 ) == TWL_CAMLED_BLINK )
+        {
+        	cam_led_update = true;        	// �����łȂ��ƈꔭ�������ɕs������邽��
+        }
+	    tsk_led_cam();	// �u�����N�̓s���ŋ����N��
+        break;
+
+      case ( REG_TWL_INT_ADRS_TEMP0 ):
+        vreg_twl[ REG_TWL_INT_ADRS_TEMP0 ] = data;
+        break;
+
+      case ( REG_TWL_INT_ADRS_COMMAND ):
+/*
+        if( data <= 2 ){
+            if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 )
+            {
+                set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );      // OFF���������Ă����炵���B
+                break;
+            }
+            else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 )
+            {
+                set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );      //���Z�b�g�����Ȃ��B���̂́ASPI���痈�܂��B
+                break;
+            }
+          }
+*/
+        if( data == REG_BIT_TWL_RESET_REQ )
+        {
+            set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );      //���Z�b�g�����Ȃ��B���̂́ASPI���痈�܂��B
+            break;
+        }
+    }
+    return;
+}
+
+
+
+// ========================================================
+// I2C���z���W�X�^����ǂ݂܂��B
+//�@���� adrs �O���猩���Ƃ��́A�A�h���X
+//�@�߂�   xx �f�[�^
+//  �@���݂��Ȃ��A�h���X�ɃA�N�Z�X�����ꍇ�A�߂�l��0x5A
+u8 vreg_twl_read( u8 phy_adrs )
+{
+    u8 temp;
+
+    switch( phy_adrs ){
+        // 10%�ȉ��ŐԂɂȂ�
+      case( REG_TWL_INT_ADRS_POWER_INFO ):
+          // ���x���̃Z�b�g�� get_batt_left()���i�������x���Ė����ł����j
+          return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !PM_EXTDC_n ? 0x80: 0x00 ) );  // �A�_�v�^bit(�A�_�v�^�L��)
+
+      case( REG_TWL_INT_ADRS_IRQ ):
+          temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ];
+          vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;
+          return( temp );
+
+      case( REG_TWL_INT_ADRS_VER_INFO ):
+//          set_irq( VREG_C_IRQ2, REG_BIT_TWL_VER_READ );  // ���x�I�ɖ����Ȃ̂�
+          twl_ver_read = true;
+          return( TWL_REG_VER_INFO );
+
+      case( REG_TWL_ADRS_NON_EXIST ):
+          return( 0x00 );
+
+      default:
+          return( vreg_twl[ phy_adrs ] );
+    }
+}
+
+
+
+// ========================================================
+// �O�����猩���钎�H���A�h���X���A�����̘A���A�h���X�ɓǂݑւ���
+// 0xFF�͑��݂��Ȃ��A�h���X�B
+u8 adrs_table_twl_ext2int( u8 img )
+{
+    switch( img ){
+      case( REG_TWL_ADRS_IRQ ):        return( REG_TWL_INT_ADRS_IRQ );
+      case( REG_TWL_ADRS_COMMAND ):    return( REG_TWL_INT_ADRS_COMMAND );
+      case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_POWER_INFO );
+      case( REG_TWL_ADRS_VOL ):        return( REG_TWL_INT_ADRS_VOL );
+      case( REG_TWL_ADRS_CAM ):        return( REG_TWL_INT_ADRS_CAM );
+      case( REG_TWL_ADRS_TEMP0 ):      return( REG_TWL_INT_ADRS_TEMP0 );
+      case( REG_TWL_ADRS_VER_INFO ):   return( REG_TWL_INT_ADRS_VER_INFO );
+      case( REG_TWL_ADRS_MODE ):       return( REG_TWL_INT_ADRS_MODE );
+      default:                         return( REG_TWL_ADRS_NON_EXIST );
+//      0���ǂ߂�΂悢�A�����Ȃ��ėǂ�
+//      case( REG_TWL_ADRS_WIFI ):       return( REG_TWL_INT_ADRS_WIFI );
+    }
+}
diff --git a/tags/2.03_SDK-3.1/vreg_twl.h b/tags/2.03_SDK-3.1/vreg_twl.h
new file mode 100644
index 0000000..63cdd94
--- /dev/null
+++ b/tags/2.03_SDK-3.1/vreg_twl.h
@@ -0,0 +1,127 @@
+#ifndef __vreg_twl__
+#define __vreg_twl__
+/* ========================================================================= */
+extern u8 vreg_twl[];
+
+
+/*
+ * �O���猩���Ƃ��̃}�C�R�����W�X�^�A�h���X�B
+ * �g�����Ȃǂ��l���Ĕ�є�тɂ��Ă���B
+ */
+/*
+ * ���荞�ݗv���t���O��
+ * MSB:�O���d�������L��/�Ȃ��ω� �i�������j
+ *   6:Vol�L�[����i�ύX�Ɍ��炸�BMAX���Ɂ{�ł��B�j
+ *   5:�d�r�d�� �� ���o
+ *   4:         ��
+ *   3:�d���X�C�b�` �����ꌟ�o
+ *   2:�i���ݒ�j
+ *   1:�d���X�C�b�` OFF      ���ԉ����ꌟ�o
+ * LSB:             ���Z�b�g
+ */
+enum REG_TWL_ADRS
+{                               // ����`�A�h���X�֏������񂾍ۂ͖���
+  REG_TWL_ADRS_VER_INFO = 0x00,
+  REG_TWL_ADRS_PMIC_INFO,
+  REG_TWL_ADRS_BATT_INFO,
+  REG_TWL_ADRS_IRQ = 0x10,
+  REG_TWL_ADRS_COMMAND,
+  REG_TWL_ADRS_MODE,
+  REG_TWL_ADRS_POWER_INFO = 0x20,
+  REG_TWL_ADRS_POWER_SAVE,
+  REG_TWL_ADRS_WIFI = 0x30,
+  REG_TWL_ADRS_CAM,
+  REG_TWL_ADRS_VOL = 0x40,
+  REG_TWL_ADRS_BL,
+  REG_TWL_ADRS_CODEC_MIC_GAIN = 0x50,
+  REG_TWL_ADRS_ADC_CALIB = 0x60,
+  REG_TWL_ADRS_ADC_CALIB_STATUS,
+  REG_TWL_ADRS_ADC_CALIB_VALUE,
+  REG_TWL_ADRS_POWER_LED,
+  REG_TWL_ADRS_TEMP0 = 0x70,
+  REG_TWL_ADRS_TEMP1,
+  REG_TWL_ADRS_TEMP2,
+  REG_TWL_ADRS_TEMP3,
+  REG_TWL_ADRS_TEMP4,
+  REG_TWL_ADRS_TEMP5,
+  REG_TWL_ADRS_TEMP6,
+  REG_TWL_ADRS_TEMP7,
+  REG_TWL_ADRS_TIME_PWSW_DELAY = 0x80,
+  REG_TWL_ADRS_TIME_PWSW_THRESHOLD
+};
+
+#define REG_TWL_ADRS_NON_EXIST 0xFF
+
+/*
+ * �}�C�R�������ł̃��W�X�^�̎���
+ * �������‚߂Ă���
+ */
+enum REG_TWL_ADRS_INT
+{
+  REG_TWL_INT_ADRS_VER_INFO = 0x00,
+//  REG_TWL_INT_ADRS_PMIC_INFO,
+//  REG_TWL_INT_ADRS_BATT_INFO,
+  REG_TWL_INT_ADRS_IRQ,         // 0x10,
+  REG_TWL_INT_ADRS_COMMAND,
+  REG_TWL_INT_ADRS_MODE,
+  REG_TWL_INT_ADRS_POWER_INFO,  // 0x20,
+//  REG_TWL_INT_ADRS_POWER_SAVE,
+//  REG_TWL_INT_ADRS_WIFI,        // 0x30,
+  REG_TWL_INT_ADRS_CAM,
+  REG_TWL_INT_ADRS_VOL,         // 0x40,
+//  REG_TWL_INT_ADRS_BL,
+//  REG_TWL_INT_ADRS_CODEC_MIC_GAIN,      // 0x50,
+//  REG_TWL_INT_ADRS_CODEC_MIC_GAIN_RELOAD,
+//  REG_TWL_INT_ADRS_ADC_CALIB,   // 0x60,
+//  REG_TWL_INT_ADRS_ADC_CALIB_STATUS,
+//  REG_TWL_INT_ADRS_ADC_CALIB_VALUE,
+//  REG_TWL_INT_ADRS_POWER_LED,
+    REG_TWL_INT_ADRS_TEMP0,       // 0x70 - 0x77
+  REG_TWL_INT_ADRS_TEMP1,
+  REG_TWL_INT_ADRS_TEMP2,
+  REG_TWL_INT_ADRS_TEMP3,
+  REG_TWL_INT_ADRS_TEMP4,
+  REG_TWL_INT_ADRS_TEMP5,
+  REG_TWL_INT_ADRS_TEMP6,
+  REG_TWL_INT_ADRS_TEMP7,
+//  REG_TWL_INT_ADRS_TIME_PWSW_DELAY,
+//  REG_TWL_INT_ADRS_TIME_PWSW_THRESHOLD
+  _REG_TWL_INT_ADRS_ENDMARK,
+};
+
+
+
+/* ========================================================================= */
+#define is_TWL               ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x01 )
+#define with_NAND            ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x02 )
+#define volSteps32           ( vreg_twl[ REG_TWL_INT_ADRS_MODE ] & 0x80 )
+
+#define reg_wifi_led         ( vreg_twl[ REG_TWL_INT_ADRS_WIFI ] & 0x01 )
+#define reg_wifi_led_blink   ( vreg_twl[ REG_TWL_INT_ADRS_WIFI ] & 0x02 )
+
+#define REG_TWL_ADRS_MODE__VOL32 ( 1 << 7 )
+
+typedef enum CAM_LED_TWL_MODE
+{
+  TWL_CAMLED_OFF,
+  TWL_CAMLED_ON,
+  TWL_CAMLED_BLINK,
+  TWL_CAMLED_DEF_ON
+}twl_camLed_mode;
+
+
+/* ========================================================================= */
+void vreg_twl_init(  );
+void vreg_twl_write( u8 adrs, u8 data );
+u8 adrs_table_twl_ext2int( u8 img );
+u8 vreg_twl_read( u8 phy_adrs );
+
+
+// �ǂ񂾂�N���A�Ȃǂ̏���
+#define vreg_twl_after_read( reg_adrs );    \
+    if( reg_adrs == REG_TWL_INT_ADRS_IRQ )  \
+    {                                       \
+        vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;\
+    }
+
+#endif
diff --git a/tags/2.03_SDK-3.1/yav_mcu_bsr.plg b/tags/2.03_SDK-3.1/yav_mcu_bsr.plg
new file mode 100644
index 0000000..51ab1ff
--- /dev/null
+++ b/tags/2.03_SDK-3.1/yav_mcu_bsr.plg
@@ -0,0 +1,44 @@
+C:\Windows\system32\cmd.exe /c c:\cygwin\bin\touch magic.c
+"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\bin\cc78k0r.exe" -c9F0104 -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -irenge -i"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\inc78k0r" -ms -rd2s2 -qvjl2w -sainter_asm -zpb -no pm.c
+pm.c(501) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(795) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(799) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(827) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(848) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(913) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(922) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(1123) : CC78K0R warning W0401: Conversion may lose significant digits
+pm.c(1125) : CC78K0R warning W0401: Conversion may lose significant digits
+Compilation complete,    0 error(s) and    9 warning(s) found.
+"C:\Program Files (x86)\NEC Electronics Tools\RA78K0R\W1.33\bin\ra78k0r.exe" -c9F0104 -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -pinter_asm -ks -kx inter_asm\pm.asm
+Assembly complete,     0 error(s) and     0 warning(s) found.
+"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\bin\cc78k0r.exe" -c9F0104 -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -irenge -i"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\inc78k0r" -ms -rd2s2 -qvjl2w -sainter_asm -zpb -no magic.c
+Compilation complete,    0 error(s) and    0 warning(s) found.
+"C:\Program Files (x86)\NEC Electronics Tools\RA78K0R\W1.33\bin\ra78k0r.exe" -c9F0104 -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -pinter_asm -ks -kx inter_asm\magic.asm
+Assembly complete,     0 error(s) and     0 warning(s) found.
+"C:\Program Files (x86)\NEC Electronics Tools\RA78K0R\W1.33\bin\lk78k0r.exe" -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -obsr.lmf "..\..\..\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\lib78k0r\s0rm.rel"  -gi1B339499E033F240BFAAh -pbsr_k0r.map -nkd -gb7EFBFFh -b"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\lib78k0r\fsl.lib" -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i"C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\lib78k0r" -dbsr_mcu.dr -s -w2  loader.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_twl.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel renge.rel accero.rel self_flash.rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg_thre_det2.rel ini_VECT.rel task_status.rel led_cam.rel led_pow.rel hal.rel batt_params.rel voltable.rel pedo_lpf_coeff.rel kanaria.rel kanaria_c.rel get_ei.rel 
+RA78K0R warning W3420: File 'loader.rel' already has had error(s)/warning(s) by 'CC78K'
+ Read Device File Directory : C:\PROGRAM FILES (X86)\NEC ELECTRONICS TOOLS\DEV\
+RA78K0R warning W3420: File 'pm.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'i2c_mcu.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'led.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'vreg_ctr.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'vreg_twl.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'adc.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'accero.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'self_flash.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'task_misc.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'task_sys.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'pedo_alg_thre_det2.rel' already has had error(s)/warning(s) by 'CC78K'
+RA78K0R warning W3420: File 'led_pow.rel' already has had error(s)/warning(s) by 'CC78K'
+
+Link complete,     0 error(s) and    13 warning(s) found.
+"C:\Program Files (x86)\NEC Electronics Tools\RA78K0R\W1.33\bin\oc78k0r.exe" -y"c:\program files (x86)\nec electronics tools\dev" -_msgoff -o.\bsr.hex -nu -ki  bsr.lmf
+Object Conversion Complete,      0 error(s) and     0 warning(s) found.
+C:\Windows\system32\cmd.exe /c ruby nec_s_2_bsrbin2.rb bsr.hex
+4
+intel-HEX to bsr bin converter
+ file converted!
+
+
+Build Total error(s) : 0  Total warning(s) : 22 
diff --git a/tags/2.03_SDK-3.1/yav_mcu_bsr.pri b/tags/2.03_SDK-3.1/yav_mcu_bsr.pri
new file mode 100644
index 0000000..023f915
--- /dev/null
+++ b/tags/2.03_SDK-3.1/yav_mcu_bsr.pri
@@ -0,0 +1,1028 @@
+[Project.ID]
+Ver=200
+Target=IDK0R32G
+[Configuration]
+Chip=uPD79F0104
+Internal Rom=32KB
+Internal Ram=1536B
+Clock=Target
+Sub Clock=Target
+Peripheral Break=0x3
+Firm Clock=System
+Flash Programming=Permit
+Low-voltage Flash Rewriting=On
+Fail Safe Break=0x2000
+Port=1
+NMI=OFF
+TRESET=OFF
+IRESET=OFF
+WAIT=OFF
+SysClock=None
+SubClock=None
+[Mapping]
+Count=0
+[Main]
+Geometry=242, 242, 1200, 858
+Window=Max
+MDI_MAX=OFF
+Button=ON
+Mode=Auto
+Trace=Uncond ON
+Trace2=Non Stop
+Coverage=OFF
+Timer=OFF
+Tracer=OFF
+[Load File]
+Dir=\\Tsclient\c\78k_data\yav-mcu-basara\trunk\
+SaveFilter=0
+Start=0
+End=0
+LoadFilter=5
+Offset=0
+Object=ON
+Symbol=ON
+Erase=OFF
+HighSpeed=OFF
+Symbol Reset=ON
+CPU Reset=ON
+File1=\\Tsclient\c\78k_data\yav-mcu-basara\trunk\bsr.lmf
+LoadFilter1=5
+Offset1=0
+Object1=ON
+Symbol1=ON
+Erase1=OFF
+HighSpeed1=OFF
+CPU Reset1=ON
+Symbol Reset1=ON
+[View File]
+Dir=\\Tsclient\c\78k_data\yav-mcu-basara\trunk\
+Filter=Source
+[Debugger Option]
+Source Path=""
+Symbol Size=Byte
+Symbol Format=Hex
+Register Name=Func
+Offset Label=OFF
+Offset Mnemonic=ON
+Tab Count=4
+Tab Size1=*.*, 8
+Tab Size2=*.c, 8
+Tab Size3=*.s, 8
+Tab Size4=*.asm, 8
+Default Source=*.c;*.s;*.asm
+Default Module=*.lnk;*.lmf
+Startup Start=_@cstart
+Startup End=_@cend
+Main Symbol=_main
+Symbol Type=OFF
+Language=C
+Kanji=SJIS
+[Source]
+Geometry=0, 0, 600, 400
+Window=Normal
+DispStart=457
+CaretPos=458,0
+Mode=Normal
+DispFile=
+Address1=
+Address2=
+Address3=
+Address4=
+Address5=
+Address6=
+Address7=
+Address8=
+Address9=
+Address10=
+Address11=
+Address12=
+Address13=
+Address14=
+Address15=
+Address16=
+Data1=
+Data2=
+Data3=
+Data4=
+Data5=
+Data6=
+Data7=
+Data8=
+Data9=
+Data10=
+Data11=
+Data12=
+Data13=
+Data14=
+Data15=
+Data16=
+Option=0
+Case=ON
+Direction=Down
+File1=
+File2=
+File3=
+File4=
+File5=
+File6=
+File7=
+File8=
+File9=
+File10=
+File11=
+File12=
+File13=
+File14=
+File15=
+File16=
+SaveRange=Screen
+SaveStart=
+SaveEnd=
+Accumulative=ON
+[Assemble]
+Geometry=75, 75, 600, 400
+Window=Normal
+DispStart=16170
+CaretPos=16170,27
+Address1=
+Address2=
+Address3=
+Address4=
+Address5=
+Address6=
+Address7=
+Address8=
+Address9=
+Address10=
+Address11=
+Address12=
+Address13=
+Address14=
+Address15=
+Address16=
+Data1=
+Data2=
+Data3=
+Data4=
+Data5=
+Data6=
+Data7=
+Data8=
+Data9=
+Data10=
+Data11=
+Data12=
+Data13=
+Data14=
+Data15=
+Data16=
+Case=ON
+Scan=OFF
+Direction=Down
+FindStart=
+FindEnd=
+SaveRange=Screen
+SaveStart=
+SaveEnd=
+[Memory]
+Geometry=0, 0, 0, 0
+Window=Hide
+Boundary=0
+Format=Hex
+Mode=Byte
+Endian=
+Ascii=OFF
+Idtag=OFF
+Address=
+DispStart=FFFFFFFF
+CaretPosData=0, 0
+CaretPosAscii=0, 0
+Address1=
+Address2=
+Address3=
+Address4=
+Address5=
+Address6=
+Address7=
+Address8=
+Address9=
+Address10=
+Address11=
+Address12=
+Address13=
+Address14=
+Address15=
+Address16=
+Data1=
+Data2=
+Data3=
+Data4=
+Data5=
+Data6=
+Data7=
+Data8=
+Data9=
+Data10=
+Data11=
+Data12=
+Data13=
+Data14=
+Data15=
+Data16=
+Binary=ON
+Scan=OFF
+Direction=DOWN
+FindStart=
+FindEnd=
+Unit=Byte
+SaveRange=Screen
+SaveStart=
+SaveEnd=
+Accumulative=ON
+[Memory fill]
+Scope=0, 0
+Code=0
+[Memory copy]
+Scope=0, 0
+To=0
+[Memory compare]
+Source=0, 0
+Destination=0
+[I/O Port]
+Line=0
+[Stack]
+Geometry=0, 0, 0, 0
+Window=Hide
+Boundary=0
+Mode=Proper
+[Sfr]
+Geometry=0, 0, 0, 0
+Window=Hide
+Address1=
+Address2=
+Address3=
+Address4=
+Address5=
+Address6=
+Address7=
+Address8=
+Address9=
+Address10=
+Address11=
+Address12=
+Address13=
+Address14=
+Address15=
+Address16=
+Boundary=0, 0
+Mode=Hex
+Attribute=Show
+Sort=Address
+Pickup=OFF
+SelectSort=Address
+Last Name=
+Line=531
+L1=P0
+L2=P1
+L3=P2
+L4=P3
+L5=P4
+L6=P5
+L7=P6
+L8=P7
+L9=P12
+L10=P14
+L11=P15
+L12=SDR00
+L13=SIO00
+L14=TXD0
+L15=SDR01
+L16=RXD0
+L17=SIO01
+L18=TDR00
+L19=TDR01
+L20=ADCRH
+L21=PM0
+L22=PM1
+L23=PM2
+L24=PM3
+L25=PM4
+L26=PM5
+L27=PM6
+L28=PM7
+L29=PM12
+L30=PM14
+L31=PM15
+L32=ADM
+L33=ADCE
+L34=ADCS
+L35=ADS
+L36=KRM
+L37=EGP0
+L38=EGN0
+L39=ISC
+L40=TIS0
+L41=SDR02
+L42=SIO10
+L43=TXD1
+L44=SDR03
+L45=RXD1
+L46=IICA0
+L47=IICS0
+L48=SPD0
+L49=STD0
+L50=ACKD0
+L51=TRC0
+L52=COI0
+L53=EXC0
+L54=ALD0
+L55=MSTS0
+L56=IICF0
+L57=IICRSV0
+L58=STCEN0
+L59=IICBSY0
+L60=STCF0
+L61=TDR02
+L62=TDR03
+L63=TDR04
+L64=TDR05
+L65=TDR06
+L66=TDR07
+L67=RSUBC
+L68=SEC
+L69=MIN
+L70=HOUR
+L71=WEEK
+L72=DAY
+L73=MONTH
+L74=YEAR
+L75=SUBCUD
+L76=ALARMWM
+L77=ALARMWH
+L78=ALARMWW
+L79=RTCC0
+L80=RCLOE0
+L81=RCLOE1
+L82=RTCE
+L83=RTCC1
+L84=RWAIT
+L85=RWST
+L86=RIFG
+L87=WAFG
+L88=WALIE
+L89=WALE
+L90=RTCC2
+L91=RCKDIV
+L92=RCLOE2
+L93=RINTE
+L94=CMC
+L95=CSC
+L96=HIOSTOP
+L97=XTSTOP
+L98=MSTOP
+L99=OSTC
+L100=OSTS
+L101=CKC
+L102=MCM0
+L103=MCS
+L104=CSS
+L105=CLS
+L106=CKS0
+L107=PCLOE0
+L108=CKS1
+L109=PCLOE1
+L110=RESF
+L111=LVIM
+L112=LVIF
+L113=LVIMD
+L114=LVISEL
+L115=LVION
+L116=LVIS
+L117=WDTE
+L118=DSA0
+L119=DSA1
+L120=DRA0
+L121=DRA0L
+L122=DRA0H
+L123=DRA1
+L124=DRA1L
+L125=DRA1H
+L126=DBC0
+L127=DBC0L
+L128=DBC0H
+L129=DBC1
+L130=DBC1L
+L131=DBC1H
+L132=DMC0
+L133=DWAIT0
+L134=DS0
+L135=DRS0
+L136=STG0
+L137=DMC1
+L138=DWAIT1
+L139=DS1
+L140=DRS1
+L141=STG1
+L142=DRC0
+L143=DST0
+L144=DEN0
+L145=DRC1
+L146=DST1
+L147=DEN1
+L148=BECTL
+L149=FLMDPUP
+L150=PFCMD
+L151=PFS
+L152=FPRERR
+L153=FLPMC
+L154=BFAEN
+L155=FWEPR
+L156=BRAMEN
+L157=IF2
+L158=IF2L
+L159=TMIF05
+L160=TMIF06
+L161=TMIF07
+L162=PIF6
+L163=IF2H
+L164=IICAIF1
+L165=PIF20
+L166=PIF21
+L167=PIF22
+L168=PIF23
+L169=MK2
+L170=MK2L
+L171=TMMK05
+L172=TMMK06
+L173=TMMK07
+L174=PMK6
+L175=MK2H
+L176=IICAMK1
+L177=PMK20
+L178=PMK21
+L179=PMK22
+L180=PMK23
+L181=PR02
+L182=PR02L
+L183=TMPR005
+L184=TMPR006
+L185=TMPR007
+L186=PPR06
+L187=PR02H
+L188=IICAPR01
+L189=PPR020
+L190=PPR021
+L191=PPR022
+L192=PPR023
+L193=PR12
+L194=PR12L
+L195=TMPR105
+L196=TMPR106
+L197=TMPR107
+L198=PPR16
+L199=PR12H
+L200=IICAPR11
+L201=PPR120
+L202=PPR121
+L203=PPR122
+L204=PPR123
+L205=IF0
+L206=IF0L
+L207=WDTIIF
+L208=LVIIF
+L209=PIF0
+L210=PIF1
+L211=PIF2
+L212=PIF4
+L213=PIF5
+L214=IF0H
+L215=DMAIF0
+L216=DMAIF1
+L217=CSIIF00
+L218=STIF0
+L219=CSIIF01
+L220=SRIF0
+L221=SREIF0
+L222=IF1
+L223=IF1L
+L224=CSIIF10
+L225=IICIF10
+L226=STIF1
+L227=SRIF1
+L228=SREIF1
+L229=IICAIF0
+L230=TMIF00
+L231=TMIF01
+L232=TMIF02
+L233=TMIF03
+L234=IF1H
+L235=ADIF
+L236=RTCIF
+L237=RTCIIF
+L238=KRIF
+L239=MDIF
+L240=TMIF04
+L241=MK0
+L242=MK0L
+L243=WDTIMK
+L244=LVIMK
+L245=PMK0
+L246=PMK1
+L247=PMK2
+L248=PMK4
+L249=PMK5
+L250=MK0H
+L251=DMAMK0
+L252=DMAMK1
+L253=CSIMK00
+L254=STMK0
+L255=CSIMK01
+L256=SRMK0
+L257=SREMK0
+L258=MK1
+L259=MK1L
+L260=CSIMK10
+L261=IICMK10
+L262=STMK1
+L263=SRMK1
+L264=SREMK1
+L265=IICAMK0
+L266=TMMK00
+L267=TMMK01
+L268=TMMK02
+L269=TMMK03
+L270=MK1H
+L271=ADMK
+L272=RTCMK
+L273=RTCIMK
+L274=KRMK
+L275=MDMK
+L276=TMMK04
+L277=PR00
+L278=PR00L
+L279=WDTIPR0
+L280=LVIPR0
+L281=PPR00
+L282=PPR01
+L283=PPR02
+L284=PPR04
+L285=PPR05
+L286=PR00H
+L287=DMAPR00
+L288=DMAPR01
+L289=CSIPR000
+L290=STPR00
+L291=CSIPR001
+L292=SRPR00
+L293=SREPR00
+L294=PR01
+L295=PR01L
+L296=CSIPR010
+L297=IICPR010
+L298=STPR01
+L299=SRPR01
+L300=SREPR01
+L301=IICAPR00
+L302=TMPR000
+L303=TMPR001
+L304=TMPR002
+L305=TMPR003
+L306=PR01H
+L307=ADPR0
+L308=RTCPR0
+L309=RTCIPR0
+L310=KRPR0
+L311=MDPR0
+L312=TMPR004
+L313=PR10
+L314=PR10L
+L315=WDTIPR1
+L316=LVIPR1
+L317=PPR10
+L318=PPR11
+L319=PPR12
+L320=PPR14
+L321=PPR15
+L322=PR10H
+L323=DMAPR10
+L324=DMAPR11
+L325=CSIPR100
+L326=STPR10
+L327=CSIPR101
+L328=SRPR10
+L329=SREPR10
+L330=PR11
+L331=PR11L
+L332=CSIPR110
+L333=IICPR110
+L334=STPR11
+L335=SRPR11
+L336=SREPR11
+L337=IICAPR10
+L338=TMPR100
+L339=TMPR101
+L340=TMPR102
+L341=TMPR103
+L342=PR11H
+L343=ADPR1
+L344=RTCPR1
+L345=RTCIPR1
+L346=KRPR1
+L347=MDPR1
+L348=TMPR104
+L349=MDAL
+L350=MULA
+L351=MDAH
+L352=MULB
+L353=MDBH
+L354=MULOH
+L355=MDBL
+L356=MULOL
+L357=PMC
+L358=MAA
+L359=ADPC
+L360=PU0
+L361=PU1
+L362=PU3
+L363=PU4
+L364=PU5
+L365=PU7
+L366=PU12
+L367=PU14
+L368=PIM3
+L369=PIM7
+L370=POM3
+L371=POM7
+L372=NFEN0
+L373=NFEN1
+L374=NFEN2
+L375=MDCL
+L376=MDCH
+L377=MDUC
+L378=DIVST
+L379=DIVMODE
+L380=PER0
+L381=SAU0EN
+L382=IICA0EN
+L383=ADCEN
+L384=RTCEN
+L385=PER2
+L386=TAU0EN
+L387=OSMC
+L388=BCDADJ
+L389=SSR00
+L390=SSR00L
+L391=SSR01
+L392=SSR01L
+L393=SSR02
+L394=SSR02L
+L395=SSR03
+L396=SSR03L
+L397=SIR00
+L398=SIR00L
+L399=SIR01
+L400=SIR01L
+L401=SIR02
+L402=SIR02L
+L403=SIR03
+L404=SIR03L
+L405=SMR00
+L406=SMR01
+L407=SMR02
+L408=SMR03
+L409=SCR00
+L410=SCR01
+L411=SCR02
+L412=SCR03
+L413=SE0
+L414=SE0L
+L415=SS0
+L416=SS0L
+L417=ST0
+L418=ST0L
+L419=SPS0
+L420=SPS0L
+L421=SO0
+L422=SOE0
+L423=SOE0L
+L424=SOL0
+L425=SOL0L
+L426=TCR00
+L427=TCR01
+L428=TCR02
+L429=TCR03
+L430=TCR04
+L431=TCR05
+L432=TCR06
+L433=TCR07
+L434=TMR00
+L435=TMR01
+L436=TMR02
+L437=TMR03
+L438=TMR04
+L439=TMR05
+L440=TMR06
+L441=TMR07
+L442=TSR00
+L443=TSR00L
+L444=TSR01
+L445=TSR01L
+L446=TSR02
+L447=TSR02L
+L448=TSR03
+L449=TSR03L
+L450=TSR04
+L451=TSR04L
+L452=TSR05
+L453=TSR05L
+L454=TSR06
+L455=TSR06L
+L456=TSR07
+L457=TSR07L
+L458=TE0
+L459=TE0L
+L460=TS0
+L461=TS0L
+L462=TT0
+L463=TT0L
+L464=TPS0
+L465=TPS0L
+L466=TO0
+L467=TO0L
+L468=TOE0
+L469=TOE0L
+L470=TOL0
+L471=TOL0L
+L472=TOM0
+L473=TOM0L
+L474=IICCTL00
+L475=SPT0
+L476=STT0
+L477=ACKE0
+L478=WTIM0
+L479=SPIE0
+L480=WREL0
+L481=LREL0
+L482=IICE0
+L483=IICCTL10
+L484=DFC0
+L485=SMC0
+L486=DAD0
+L487=CLD0
+L488=WUP0
+L489=IICWL0
+L490=IICWH0
+L491=SVA0
+L492=PER3
+L493=IICA1EN
+L494=P20
+L495=PM20
+L496=PU20
+L497=EGP2
+L498=EGN2
+L499=IICA1
+L500=IICS1
+L501=SPD1
+L502=STD1
+L503=ACKD1
+L504=TRC1
+L505=COI1
+L506=EXC1
+L507=ALD1
+L508=MSTS1
+L509=IICF1
+L510=IICRSV1
+L511=STCEN1
+L512=IICBSY1
+L513=STCF1
+L514=IICCTL01
+L515=SPT1
+L516=STT1
+L517=ACKE1
+L518=WTIM1
+L519=SPIE1
+L520=WREL1
+L521=LREL1
+L522=IICE1
+L523=IICCTL11
+L524=DFC1
+L525=SMC1
+L526=DAD1
+L527=CLD1
+L528=WUP1
+L529=IICWL1
+L530=IICWH1
+L531=SVA1
+[Local Variable]
+Geometry=0, 0, 0, 0
+Window=Hide
+Boundary=0
+Mode=Proper
+[Trace View]
+Geometry=0, 0, 0, 0
+Window=Hide
+Mode=Normal
+Frame=Show
+Timetag=Clock
+Address=Show
+Data=Hex
+Status=Show
+Address2=Show
+Data2=Hex
+Status2=Show
+Disasm=Show
+Pick Up=Off
+Synchronize=0 0 0 0
+Frameno=
+Frameno1=
+Frameno2=
+Frameno3=
+Frameno4=
+Frameno5=
+Frameno6=
+Frameno7=
+Frameno8=
+Frameno9=
+Frameno10=
+Frameno11=
+Frameno12=
+Frameno13=
+Frameno14=
+Frameno15=
+Frameno16=
+ScanStatus=ALL
+Access Size=B
+ScanAddress=<>-<>
+Mask Address=
+ScanData=
+Mask Data=
+ScanExternal=
+Mask External=
+Scan=OFF
+Direction=Down
+FindStart=
+FindEnd=
+SaveRange=Screen
+SaveStart=
+SaveEnd=
+[Register]
+Geometry=0, 0, 0, 0
+Window=Hide
+Mode=Hex
+Boundary=0
+Pickup=OFF
+Name=Functional
+Register Bank=0
+RP0=3
+RP1=3
+RP2=3
+RP3=3
+PC=3
+SP=3
+PSW=3
+ES=3
+CS=3
+[Event Manager]
+Geometry=0, 0, 0, 0
+Window=Hide
+Sort by=Unsort
+Detail=OFF
+[Event Set]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Event Link]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Break]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Trace]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Delay Count0=2
+Count=0
+[Snap]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Stub]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Timer]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+TimerRateRunBreak=0011
+TimerBreakOutRunBreak=OFF
+Count=0
+[Timer Monitor]
+Count=0
+[Dmm]
+Geometry=0, 0, 0, 0
+Window=Hide
+Manager=ON
+Sort by=Unsort
+Detail=OFF
+Last Name=
+Count=0
+[Variable]
+Geometry=1145, 5, 440, 719
+Window=Normal
+Boundary=13762700
+0=.flag_wifi_TX,P,N,A,+,1
+1=.PIF21,B,S,A,+,1
+Line=2
+[Quick Watch]
+0=PIF21,B,A,1
+1=flag_wifi_TX,P,A,1
+2=
+3=
+4=
+5=
+6=
+7=
+8=
+9=
+10=
+11=
+12=
+13=
+14=
+15=
+[Software Break]
+Geometry=0, 0, 0, 0
+Window=Hide
+Width=150 30 200 100
+Name0=Swb00001
+Address0=led.c#_LED_init+0x62
+Window0=ASM
+Status0=ON
+Name1=Swb00002
+Address1=led.c#_tsk_led_wifi+0xb
+Window1=ASM
+Status1=ON
+Name2=Swb00003
+Address2=led.c#_tsk_led_wifi+0x10
+Window2=ASM
+Status2=ON
+Count=3
+[Reset]
+Debugger=ON
+Symbol=OFF
+Target CPU=OFF
+[Extended Option]
+OnClick Software Break=ON
+TraceTimetag=x1
+Redraw=500
+Break When Access Function=OFF
+Break When Access Whole=Select
+Verify=ON
+Break Sound=ON
+TraceAutoClear=OFF
+RRM Clock=Internal
+CKC Register Value=0x09
+RRM Internal Clock Frequency=8.000
+[About]
+Version=Program
+[Pseudo Emulation]
+Geometry=0, 0, 0, 0
+Window=Hide
+[Data Flash Option]
+Data Flash Emulation=OFF
+[List]
+Geometry=0, 0, 0, 0
+Window=Hide
+[Console]
+Geometry=0, 0, 0, 0
+Window=Hide
diff --git a/tags/2.03_SDK-3.1/yav_mcu_bsr.prj b/tags/2.03_SDK-3.1/yav_mcu_bsr.prj
new file mode 100644
index 0000000..8d026dc
--- /dev/null
+++ b/tags/2.03_SDK-3.1/yav_mcu_bsr.prj
@@ -0,0 +1,1407 @@
+[ProjectManager]
+Version=6.00
+Path=C:\78k_data\yav-mcu-basara\trunk\
+Title=yav-mcu
+Series=78K0R.PM
+Device=uPD79F0104
+DeviceVer=E1.00b
+DebugMode=1
+Target=bsr.lmf
+[BuildMode0]
+BuildModeName=Debug Build
+TargetFile=0
+[BuildMode1]
+BuildModeName=Release Build
+TargetFile=0
+[Tools]
+MakeFile=yav_mcu_bsr.mak
+Debugger=C:\Program Files (x86)\NEC Electronics Tools\ID78K0R-QB\V3.61\BIN\IDK0R32G.EXE
+DebOption=
+DebCpuReset=1
+DebSymReset=1
+MuitiLoad=0
+LoadPrjNum=0
+CheckVersion=CC78K0R|W2.13;RA78K0R|W1.33
+[Option.IDK0R32G]
+File=\\Tsclient\c\78k_data\yav-mcu-basara\trunk\yav_mcu_bsr.pri
+[BuildMode2]
+BuildModeName=K0R_dbg
+TargetFile=0
+[BuildMode3]
+BuildModeName=BSR_dbg
+TargetFile=0
+[BuildMode4]
+BuildModeName=BSR_rel
+TargetFile=0
+[BuildMode5]
+BuildModeName=BSR_WM0
+TargetFile=0
+[Options.OC78K0R 0]
+Version=100
+O0=.\bsr.hex
+O1=bsr.hex
+UC=1
+UN=FF
+UST=
+USZ=
+K=1
+ZF=0
+S=1
+E=0
+CommandFile=0
+[Options.OC78K0R 1]
+Version=100
+UC=1
+UN=FF
+UST=
+USZ=
+K=1
+ZF=0
+S=1
+E=0
+CommandFile=0
+[Options.OC78K0R 2]
+Version=100
+O0=.\bsr.hex
+O1=bsr.hex
+UC=0
+UN=FF
+UST=
+USZ=
+K=0
+ZF=0
+S=1
+E=0
+CommandFile=0
+[Options.OC78K0R 3]
+Version=100
+O0=.\bsr.hex
+O1=bsr.hex
+UC=1
+UN=FF
+UST=
+USZ=
+K=1
+ZF=0
+S=1
+E=0
+CommandFile=0
+[Options.OC78K0R 4]
+Version=100
+O0=.\bsr.hex
+O1=bsr.hex
+UC=1
+UN=FF
+UST=
+USZ=
+K=1
+ZF=0
+S=1
+E=0
+CommandFile=0
+[Options.OC78K0R 5]
+Version=100
+O0=.\bsr.hex
+O1=bsr.hex
+UC=1
+UN=FF
+UST=
+USZ=
+K=1
+ZF=0
+S=1
+E=0
+CommandFile=0
+[BuildBefore-AfterCmd]
+Before1=c:\cygwin\bin\touch magic.c
+After1=ruby nec_s_2_bsrbin2.rb bsr.hex
+[ToolSet]
+ToolSetName=(�ύX)78K0R Software Package V1.10
+Tool1=CC78K0R|W2.13
+Tool2=RA78K0R|W1.33
+Tool3=SK78K0R|V3.10
+Tool4=ID78K0R-QB|V3.61
+[SrcFile]
+Source1=loader.c
+Source2=pm.c
+Source3=i2c_ctr.c
+Source4=main.c
+Source5=magic.c
+Source6=WDT.c
+Source7=i2c_mcu.c
+Source8=i2c_twl.c
+Source9=led.c
+Source10=rtc.c
+Source11=vreg_ctr.c
+Source12=vreg_twl.c
+Source13=adc.c
+Source14=renge\renge.c
+Source15=accero.c
+Source16=self_flash.c
+Source17=sw.c
+Source18=task_debug.c
+Source19=task_misc.c
+Source20=task_sys.c
+Source21=pedo_alg_thre_det2.c
+Source22=ini_VECT.c
+Source23=task_status.c
+Source24=led_cam.c
+Source25=led_pow.c
+Source26=hal.c
+Source27=batt_params.c
+Source28=voltable.c
+Source29=pedo_lpf_coeff.c
+Source30=kanaria.asm
+Source31=kanaria_c.c
+Source32=get_ei.asm
+[IncFile]
+Include1=incs_loader.h
+Include2=sim\simOnWin.h
+Include3=sim\sfrAlias.h
+Include4=config.h
+Include5=jhl_defs.h
+Include6=user_define.h
+Include7=hal.h
+Include8=bsr_system.h
+Include9=renge\renge.h
+Include10=renge\renge_defs.h
+Include11=renge\renge_task_immediate.h
+Include12=vreg_ctr.h
+Include13=vreg_twl.h
+Include14=loader.h
+Include15=i2c_mcu.h
+Include16=WDT.h
+Include17=..\..\..\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\inc78k0r\fsl.h
+Include18=fsl_user.h
+Include19=i2c_ctr.h
+Include20=pm.h
+Include21=rtc.h
+Include22=reboot.h
+Include23=magic.h
+Include24=incs.h
+Include25=i2c_twl.h
+Include26=accero.h
+Include27=pedometer.h
+Include28=sw.h
+Include29=adc.h
+Include30=led.h
+Include31=batt_params.h
+Include32=pool.h
+Include33=i2c_twl_defs.h
+Include34=renge\renge_task_intval.h
+Include35=..\..\..\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\inc78k0r\math.h
+Include36=self_flash.h
+Include37=sim\sim_interrupt_decrare.c
+[Options.RA78K0R 0]
+Version=100
+G=1
+GA=1
+E=0
+COMMON=0
+COMPATI=0
+P=1
+KA=1
+KS=0
+KX=0
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=
+[Options.RA78K0R 1]
+Version=100
+G=0
+GA=0
+E=0
+COMMON=0
+COMPATI=0
+P=1
+KA=1
+KS=0
+KX=0
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=
+[Options.RA78K0R 2]
+Version=100
+O0=
+O1=obj
+G=1
+GA=1
+E=0
+COMMON=0
+COMPATI=0
+P=1
+P0=inter_asm
+KA=1
+KS=1
+KX=1
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=-pinter_asm -ks -kx 
+[Options.RA78K0R 3]
+Version=100
+G=1
+GA=1
+E=0
+COMMON=0
+COMPATI=0
+P=1
+KA=1
+KS=0
+KX=0
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=
+[Options.RA78K0R 4]
+Version=100
+G=1
+GA=1
+E=0
+COMMON=0
+COMPATI=0
+P=1
+KA=1
+KS=0
+KX=0
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=
+[Options.RA78K0R 5]
+Version=100
+G=1
+GA=1
+E=0
+COMMON=0
+COMPATI=0
+P=1
+KA=1
+KS=0
+KX=0
+LF=0
+LW=132
+LL=0
+LT=8
+Z=0
+CommandFile=0
+RA_OPT=
+[Options.CC78K0R 0]
+Version=210
+Include0=renge,C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r
+Include1=C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r
+Memorymodel=1
+Flashobj=0
+FlashStartadr=
+FlashBranchStartadr=
+Mirror=0
+Saddrglobalchk=0
+Saddrglobal=1066
+Saddrstaticchk=0
+Saddrstatic=1072
+Bitfieldmsb=0
+Onebytechk=0
+Pacstructchk=0
+AssignROMchk=0
+AssignROM=0
+Maxoptimizechk=0
+Maxoptimize=1104
+Charunexpandchk=1
+Unsignedchar=0
+Usesaddrchk=0
+Autoallocationchk=1
+Jumpoptimize=1
+Librarycallchk=0
+Librarycall=1129
+Aggressivechk=1
+Relativebranchchk=1
+Debugoptchk=0
+Outdebugchk=1
+Outdebug=1153
+Outasmsrccmb0=inter_asm
+Outasmsrccmb1=bsr.asm
+Outasmsrcchk=1
+Outasmsrc=1158
+Outasmoptall=1
+Common=0
+Outerrlistchk=0
+Outerrlist=1174
+Xreference=0
+Preprocess=0
+Prenocomment=0
+Predefine=0
+Preifdef=1
+Preinclude=0
+Preline=1
+Prenumber=1
+Formfeed=0
+Columns=132
+Lines=0
+Tablength=8
+Ansi=0
+Cpraspras=1
+Commentnest=0
+Intunexpand=0
+Kanjicode=1210
+Verbose=0
+CommandFile=0
+Warninglevel=0
+Startupchk=1
+Fixation=1
+FarROMization=0
+Objectsel=1305
+Librarychk=1
+Floatingpoint=0
+Muldivunit=1
+Mulunit=1
+Startup=s0rml.rel
+Library1=cl0rdm.lib
+Library2=cl0rm.lib
+Library3=cl0rmf.lib
+VfiFileBoot0=
+VfiFileBoot1=boot.vfi
+VF78K0Rchk=0
+VF78K0Rvs=
+[Options.CC78K0R 1]
+Version=210
+Memorymodel=2
+Flashobj=0
+FlashStartadr=
+FlashBranchStartadr=
+Mirror=0
+Saddrglobalchk=0
+Saddrglobal=1066
+Saddrstaticchk=0
+Saddrstatic=1072
+Bitfieldmsb=0
+Onebytechk=0
+Pacstructchk=0
+AssignROMchk=0
+AssignROM=0
+Maxoptimizechk=0
+Maxoptimize=1104
+Charunexpandchk=1
+Unsignedchar=0
+Usesaddrchk=0
+Autoallocationchk=1
+Jumpoptimize=1
+Librarycallchk=1
+Librarycall=1128
+Aggressivechk=1
+Relativebranchchk=0
+Debugoptchk=0
+Outdebugchk=0
+Outdebug=1153
+Outasmsrcchk=0
+Outasmsrc=1157
+Outasmoptall=1
+Common=0
+Outerrlistchk=0
+Outerrlist=1173
+Xreference=0
+Preprocess=0
+Prenocomment=0
+Predefine=0
+Preifdef=1
+Preinclude=0
+Preline=1
+Prenumber=1
+Formfeed=0
+Columns=132
+Lines=0
+Tablength=8
+Ansi=0
+Cpraspras=0
+Commentnest=0
+Intunexpand=0
+Kanjicode=1210
+Verbose=0
+CommandFile=0
+Warninglevel=1
+Startupchk=1
+Fixation=1
+FarROMization=1
+Objectsel=1305
+Librarychk=1
+Floatingpoint=0
+Muldivunit=1
+Mulunit=1
+Startup=s0rll.rel
+Library1=cl0rdm.lib
+Library2=cl0rm.lib
+Library3=cl0rmf.lib
+VF78K0Rchk=0
+VF78K0Rvs=
+[Options.CC78K0R 2]
+Version=210
+Define0=
+Define1=_debug_,_TEG_,proc_is_ke3
+Define2=_debug_,_TEG_,proc_is_ke3,%time%
+Define3=_TEG_,proc_is_ke3
+Define4=proc_is_ke3
+Include0=renge,C:\Program Files (x86)\NEC Electronics Tools\CC78K0R\W2.13\inc78k0r
+Include1=renge,C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r
+Include2=C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\inc78k0r
+Memorymodel=1
+Flashobj=0
+FlashStartadr=
+FlashBranchStartadr=
+Mirror=0
+Saddrglobalchk=1
+Saddrglobal=1063
+Saddrstaticchk=1
+Saddrstatic=1069
+Bitfieldmsb=0
+Onebytechk=0
+Pacstructchk=0
+AssignROMchk=0
+AssignROM=0
+Maxoptimizechk=0
+Maxoptimize=1104
+Charunexpandchk=0
+Unsignedchar=0
+Usesaddrchk=0
+Autoallocationchk=1
+Jumpoptimize=1
+Librarycallchk=1
+Librarycall=1129
+Aggressivechk=1
+Relativebranchchk=0
+Debugoptchk=0
+Outdebugchk=1
+Outdebug=1153
+Outobjectcmb0=
+Outobjectcmb1=obj
+Outasmsrccmb0=inter_asm
+Outasmsrccmb1=bsr.asm
+Outasmsrcchk=1
+Outasmsrc=1158
+Outasmoptall=1
+Common=0
+Outerrlistchk=0
+Outerrlist=1174
+Xreference=0
+Preprocess=0
+Prenocomment=0
+Predefine=0
+Preifdef=1
+Preinclude=1
+Preline=1
+Prenumber=1
+Formfeed=0
+Columns=132
+Lines=0
+Tablength=8
+Ansi=0
+Cpraspras=1
+Commentnest=0
+Intunexpand=1
+Kanjicode=1210
+Verbose=0
+CommandFile=0
+Warninglevel=1
+Startupchk=1
+Fixation=0
+FarROMization=0
+Objectsel=1305
+Librarychk=1
+Floatingpoint=0
+Muldivunit=1
+Mulunit=1
+Startup=s0rm.rel
+Library1=cl0rdm.lib
+Library2=cl0rm.lib
+Library3=cl0rmf.lib
+VfiFileBoot0=
+VfiFileBoot1=boot.vfi
+VF78K0Rchk=0
+VF78K0Rvs=
+[Options.CC78K0R 3]
+Version=210
+Define0=_debug_,proc_is_bsr,_TEG_
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