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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@487 013db118-44a6-b54f-8bf7-843cb86687b1
2025-10-31 13:51:10 -04:00 · 2012-11-28 08:02:38 +00:00 · 2012-11-28 08:02:38 +00:00 · 18ce0d711d
commit 18ce0d711d
parent e3b194fb5e
2305 changed files with 0 additions and 847786 deletions
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.c
@ -1,14 +0,0 @@
-#pragma sfr
-
-
-#include "incs_loader.h"
-
-
-
-//=========================================================
-// ウォッチドッグタイマのリスタート
-//   0xACはマジック
-void WDT_Restart( void )
-{
-    WDTE = WDT_RESTART_MAGIC;
-}
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.h
@ -1,18 +0,0 @@
-#ifndef _WDT_
-#define _WDT_
-
-
-
-//=========================================================
-#define WDT_RESTART_MAGIC    0xAC
-
-
-
-//=========================================================
-void WDT_Restart( void );
-
-// 規定値以外を書くと例外でリセットがかかる
-#define mcu_reset            WDTE = 0x5A
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.prn
@ -1,154 +0,0 @@
-
-
-
-78K0R Assembler W1.31                                                                                    Date:13 Jun 2010 Page:   1
-
-
-
-Command:  -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\WDT.asm
-Para-file:
-In-file:  inter_asm\WDT.asm
-Obj-file: WDT.rel
-Prn-file: WDT.prn
-
-      Assemble list
-
- ALNO  STNO ADRS   OBJECT   M I  SOURCE STATEMENT
-
-    1     1                      ; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-    2     2                      
-    3     3                      ; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-    4     4                      ;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-    5     5                      ;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no WDT.c
-    6     6                      ; In-file   : WDT.c
-    7     7                      ; Asm-file  : inter_asm\WDT.asm
-    8     8                      ; Para-file : 
-    9     9                      
-   10    10                      $PROCESSOR(9F0104)
-   11    11                      $DEBUG
-   12    12                      $NODEBUGA
-   13    13                      $KANJICODE SJIS
-   14    14                      $TOL_INF        03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-   15    15                      
-   16    16                      $DGS    FIL_NAM, .file,         019H,   0FFFEH, 03FH,   067H,   01H,    00H
-   17    17                      $DGS    AUX_FIL, WDT.c
-   18    18                      $DGS    MOD_NAM, WDT,           00H,    0FFFEH, 00H,    077H,   00H,    00H
-   19    19                      $DGS    SEC_NAM, @@BITS,        U,      U,      00H,    078H,   00H,    00H
-   20    20                      $DGS    SEC_NAM, @@CNST,        U,      U,      00H,    078H,   00H,    00H
-   21    21                      $DGS    SEC_NAM, @@R_INIT,      U,      U,      00H,    078H,   00H,    00H
-   22    22                      $DGS    SEC_NAM, @@INIT,        U,      U,      00H,    078H,   00H,    00H
-   23    23                      $DGS    SEC_NAM, @@DATA,        U,      U,      00H,    078H,   00H,    00H
-   24    24                      $DGS    SEC_NAM, @@R_INIS,      U,      U,      00H,    078H,   00H,    00H
-   25    25                      $DGS    SEC_NAM, @@INIS,        U,      U,      00H,    078H,   00H,    00H
-   26    26                      $DGS    SEC_NAM, @@DATS,        U,      U,      00H,    078H,   00H,    00H
-   27    27                      $DGS    SEC_NAM, LDR_CNSL,      U,      U,      00H,    078H,   00H,    00H
-   28    28                      $DGS    SEC_NAM, @@RLINIT,      U,      U,      00H,    078H,   00H,    00H
-   29    29                      $DGS    SEC_NAM, @@INITL,       U,      U,      00H,    078H,   00H,    00H
-   30    30                      $DGS    SEC_NAM, @@DATAL,       U,      U,      00H,    078H,   00H,    00H
-   31    31                      $DGS    SEC_NAM, @@CALT,        U,      U,      00H,    078H,   00H,    00H
-   32    32                      $DGS    SEC_NAM, LDR_CODE,      U,      U,      00H,    078H,   00H,    00H
-   33    33                      $DGS    SEC_NAM, LDR_CODL,      U,      U,      00H,    078H,   00H,    00H
-   34    34                      $DGS    SEC_NAM, @@BASE,        U,      U,      00H,    078H,   00H,    00H
-   35    35                      $DGS    GLV_SYM, _WDT_Restart,  U,      U,      01H,    026H,   01H,    02H
-   36    36                      $DGS    AUX_FUN, 00H,           U,      U,      019H,   00H,    00H
-   37    37                      $DGS    BEG_FUN, ??bf_WDT_Restart,      U,      U,      00H,    065H,   01H,    00H
-   38    38                      $DGS    AUX_BEG, 0CH,           00H,    019H
-   39    39                      $DGS    END_FUN, ??ef_WDT_Restart,      U,      U,      00H,    065H,   01H,    00H
-   40    40                      $DGS    AUX_END, 03H
-   41    41                      
-   42    42                              PUBLIC  _WDT_Restart
-   43    43                      
-   44    44 -----                @@BITS  BSEG
-   45    45                      
-   46    46 -----                @@CNST  CSEG    MIRRORP
-   47    47                      
-   48    48 -----                @@R_INIT        CSEG    UNIT64KP
-   49    49                      
-   50    50 -----                @@INIT  DSEG    BASEP
-   51    51                      
-   52    52 -----                @@DATA  DSEG    BASEP
-   53    53                      
-   54    54 -----                @@R_INIS        CSEG    UNIT64KP
-   55    55                      
-   56    56 -----                @@INIS  DSEG    SADDRP
-   57    57                      
-   58    58 -----                @@DATS  DSEG    SADDRP
-   59    59                      
-   60    60 -----                LDR_CNSL        CSEG    PAGE64KP
-   61    61                      
-   62    62 -----                @@RLINIT        CSEG    UNIT64KP
-   63    63                      
-   64    64 -----                @@INITL DSEG    UNIT64KP
-   65    65                      
-   66    66 -----                @@DATAL DSEG    UNIT64KP
-   67    67                      
-   68    68 -----                @@CALT  CSEG    CALLT0
-   69    69                      
-   70    70                      ; line     1 : #pragma sfr
-   71    71                      ; line     2 : 
-   72    72                      ; line     3 : 
-   73    73                      ; line     4 : #include "incs_loader.h"
-   74    74                      ; line     5 : 
-   75    75                      ; line     6 : 
-   76    76                      ; line     7 : 
-   77    77                      ; line     8 : //=========================================================
-   78    78                      ; line     9 : // ウォッチドッグタイマのリスタート
-   79    79                      ; line    10 : //   0xACはマジック
-   80    80                      ; line    11 : void WDT_Restart( void )
-   81    81                      ; line    12 : {
-   82    82                      
-   83    83 -----                LDR_CODE        CSEG    BASE
-   84    84 00000                _WDT_Restart:
-   85    85                      $DGL    1,19
-   86    86 00000                ??bf_WDT_Restart:
-   87    87                      ; line    13 :     WDTE = WDT_RESTART_MAGIC;
-   88    88                      $DGL    0,2
-   89    89 00000  CEABAC                mov     WDTE,#0ACH      ; 172                           ;[INF] 3, 1
-   90    90                      ; line    14 : }
-   91    91                      $DGL    0,3
-   92    92 00003                ??ef_WDT_Restart:
-   93    93 00003  D7                    ret                                                     ;[INF] 1, 6
-   94    94 00004                ??ee_WDT_Restart:
-   95    95                      
-   96    96 -----                LDR_CODL        CSEG
-   97    97                      
-   98    98 -----                @@BASE  CSEG    BASE
-   99    99                              END
-  100   100                      
-  101   101                      
-  102   102                      ; *** Code Information ***
-  103   103                      ;
-  104   104                      ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c
-  105   105                      ;
-  106   106                      ; $FUNC WDT_Restart(12)
-  107   107                      ;       void=(void)
-  108   108                      ;       CODE SIZE= 4 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
-  109   109                      
-  110   110                      ; Target chip : uPD79F0104
-  111   111                      ; Device file : E1.00b
-
-Segment informations:
-
-ADRS  LEN      NAME
-
-00000 00000H.0 @@BITS
-00000 00000H   @@CNST
-00000 00000H   @@R_INIT
-00000 00000H   @@INIT
-00000 00000H   @@DATA
-00000 00000H   @@R_INIS
-00000 00000H   @@INIS
-00000 00000H   @@DATS
-00000 00000H   LDR_CNSL
-00000 00000H   @@RLINIT
-00000 00000H   @@INITL
-00000 00000H   @@DATAL
-00000 00000H   @@CALT
-00000 00004H   LDR_CODE
-00000 00000H   LDR_CODL
-00000 00000H   @@BASE
-
- Target chip : uPD79F0104
- Device file : E1.00b
-Assembly complete,     0 error(s) and     0 warning(s) found. (    0)
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/WDT.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/__info.bat
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/__info.bat
@ -1,3 +0,0 @@
-@echo off
-set VF="C:\Program Files\NEC Electronics Tools\RA78K0R\W1.31\bin\vf78k0r.exe"
-%VF% -y"C:\Program Files\NEC Electronics Tools\DEV" -_msgoff -obsr.lmf "..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r\s0rm.rel"  -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFFFFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -b"C:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib" -bcl0rdm.lib -bcl0rm.lib -bcl0rmf.lib -i"C:\Program Files\NEC Electronics Tools\CC78K0R\W2.10\lib78k0r" -dbsr_mcu.dr -s -w0  loader.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vreg_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot.rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg_thre_det2.rel  -vx
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.c
@ -1,250 +0,0 @@
-/* ========================================================
-　加速度センサ関係
-・データ更新完了でデータを吸い上げ手レジスタを更新、CPUに割り込み
-・フラグが立っていれば歩数カウント
-・加速度センサ割り込みからタスクを登録して下さい。（I2Cの競合回避などがあるので）
-
- ======================================================== */
-#pragma SFR
-#pragma NOP
-#pragma HALT
-#pragma STOP
-#pragma ROT
-// rorb, rolb, rorw, rolw
-#pragma MUL
-#pragma BCD
-
-#include "incs.h"
-#include <math.h>
-
-// ========================================================
-// レジスタ名
-#define ACC_REG_WHOAMI 0x0F
-#define ACC_REG_CTRL1  0x20
-#define ACC_REG_CTRL5  0x24
-#define ACC_REG_X      0x28
-
-// ビット位置
-#define ACC_bP_PM0    5
-#define ACC_bP_DR0    3
-
-// ビット設定値
-#define ACC_BITS_PM_PDN   0
-#define ACC_BITS_PM_NORM  1
-#define ACC_BITS_PM_LP0R5 2
-#define ACC_BITS_PM_LP1   3
-#define ACC_BITS_PM_LP2   4
-#define ACC_BITS_PM_LP5   5
-#define ACC_BITS_PM_LP10  6
-
-#define ACC_BITS_DR_50Hz   0
-#define ACC_BITS_DR_100Hz  1
-#define ACC_BITS_DR_400Hz  2
-#define ACC_BITS_DR_1000Hz 3
-
-#define ACC_BITS_ALL_AXIS_ON 7
-
-
-#define VREG_BITMASK_ACC_CONF_ACQ  ( 1 << 0 )
-#define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 )
-
-
-
-
-// ========================================================
-task_status tsk_soft_int(  );
-
-
-
-/* ========================================================
-　・割り込みを確認してデータを吸い上げ、レジスタに書き出します
-  ・本当であればコールバック関数を登録しておけばいいじゃんとなるのですが、
-  I2Cが使用中だったら？とか考えると私ではそこまでできないのです。
-  ・自動歩数計とかでも結局
- ======================================================== */
-task_status_immed tsk_cbk_accero(  )
-{                               // （疑似）isrから登録されます
-
-/*
-    if(( system_status.pwr_state == OFF ) || ( system_status.pwr_state == BT_CHARGE ) )
-    {
-        return ( ERR_SUCCESS );
-    }
-    else
-    {
-*/
-        // 加速度センサデータレジスタへの反映
-        if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, &vreg_ctr[VREG_C_ACC_XL] )
-        != ERR_SUCCESS )
-    {
-        // 加速度センサが異常になったので止める
-        vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ );
-//        vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
-        acc_hosu_set();
-        return ( ERR_SUCCESS ); // タスクの削除は必要
-    }
-    else
-        {
-        // 正常時パス //
-        // 加速度更新＆割り込み
-        if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_ACQ ) != 0 ) &&
-            ( system_status.pwr_state == ON )
-            )
-            {
-                set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY );
-            // ゴミデータのカラ読み
-            if( ACC_VALID == 1 )
-            {
-                u8 temp[6];
-                iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, temp );
-            }
-        }
-        if(( system_status.pwr_state != OFF ) &&
-           ( system_status.pwr_state != BT_CHARGE ) &&
-           ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CONF_HOSU ) != 0 )
-           )
-        {
-    DBG_LED_WIFI_2_on;
-    pedometer();    // 歩数計
-    DBG_LED_WIFI_2_off;
-        }
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-
-
-/*=======================================================
-　加速度センサ透過アクセス　リード
- ========================================================*/
-task_status_immed acc_read(  )
-{
-    vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
-//  vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
-    vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
-    if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
-    {
-        IRQ0_ast;
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-/*=========================================================
-　加速度センサ透過アクセス　ライト
- ========================================================*/
-task_status_immed acc_write(  )
-{
-    iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_ADRS], vreg_ctr[VREG_C_ACC_W_BUF] );
-    vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
-    if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
-    {
-        IRQ0_ast;
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-/*=========================================================
-　自動歩数カウントモードにセット
-  todo 他のモードだったら止めたり、復帰させたり
-  割り込みルーチンなどでカウント判定が必要
- ========================================================*/
-task_status_immed acc_hosu_set(  )
-{
-    u8      str_send_buf[4];
-
-    iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI );
-    if( iic_mcu_bus_status == ERR_NOSLAVE )
-    {
-        vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
-#ifdef _MCU_BSR_
-//	    PMK23 = 1;
-#endif
-        return ( ERR_SUCCESS ); // とりあえず、タスクは削除しなくてはならない
-    }else{
-        vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR;
-    }
-
-
-    str_send_buf[1] = 0x00;     // ctrl2  HPF:normal, filterd, HPF for IRQ : dis/dis, HPF coeff:norm
-#ifdef _MODEL_WM0_
-# ifdef _MODEL_WM0_TEG2_CTRC_
-    str_send_buf[2] = 0x02;     //  回路が一部違う
-# else
-
-    str_send_buf[2] = 0x10;     //     3  IRQ pol :Active HI, Drive:Pushpull,
-                                ///       IRQ2flg latch: auto clear after read, IRQ2 conf: IRQ( fall,shock,...)
-                                ///          1         : auto clear after read,      conf: data ready
-# endif
-#else
-# ifdef _MODEL_CTR_JIKKI_
-    str_send_buf[2] = 0x10;
-# else
-    str_send_buf[2] = 0x02;     //     3  IRQ pol :Active HI, Drive:Pushpull,
-                                ///       IRQ2flg latch: auto clear after read, IRQ2 conf: IRQ( fall,shock,...)
-                                ///          1         : auto clear after read,      conf: data ready
-# endif
-#endif
-    str_send_buf[3] = 0x80;     // ctrl3  block update:enable, MSB first, scale: +-2G(default), selftest: dis
-
-    if( ( vreg_ctr[VREG_C_ACC_CONFIG] &
-          ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_ACQ ) ) == 0 )
-    {
-#ifdef _MCU_BSR_
-	    PMK23 = 1;
-#endif
-        // 完全停止
-        str_send_buf[0] =
-            ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | ACC_BITS_ALL_AXIS_ON );
-    }
-    else
-    {
-#ifdef _MCU_BSR_
-	    PMK23 = 0;
-#endif
-        // 100Hz 自動取り込み
-        str_send_buf[0] =
-            ( ACC_BITS_PM_NORM << ACC_bP_PM0
-              | ACC_BITS_DR_100Hz << ACC_bP_DR0
-              | ACC_BITS_ALL_AXIS_ON );
-    }
-    iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, str_send_buf );
-
-    // カラ読み
-    if( ACC_VALID == 1 )
-    {
-        if( system_status.pwr_state == ON )
-        {
-            u8 temp[6];
-            iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6, temp );
-        }
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-/* ========================================================
- 加速度センサ割り込み
-  I2Cが使用中かもしれないので、読み出しタスクの登録を行うのみ
- ======================================================== */
-__interrupt void intp23_ACC_ready(  )
-{
-    EI();
-    if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 )
-    {
-        if( ( system_status.pwr_state == ON ) || ( system_status.pwr_state == SLEEP ) )
-        {
-            if( ACC_VALID )
-            {
-                renge_task_immed_add( tsk_cbk_accero );
-            }
-        }
-    }
-}
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.h
@ -1,14 +0,0 @@
-#ifndef _accero_
-#define _accero_
-
-
-#include "jhl_defs.h"
-#include "pedometer.h"
-
-
-///////////////////////////////////////////////////////////
-task_status_immed tsk_cbk_accero(  );
-task_status_immed acc_hosu_set(  );
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/accero.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.c
@ -1,356 +0,0 @@
-/* ========================================================
-    藤田＠開技
-    nintendo
-    '09 Apr
- ======================================================== */
-#include "incs.h"
-#include "adc.h"
-#include "pm.h"
-
-#include "led.h"
-
-bit     adc_updated;
-
-u8 adc_raw_vol;
-u8 adc_raw_dep;
-
-#define INTERVAL_TSK_ADC  3
-/* ========================================================
- ADC設定と、開始
-
-  以下のピンは主にここで操作・監視されます。
- ・BT_TEMP,_P
- ・ADIN1
- ・VOL
-
-  関係ありそうですが別のところで管理しています
- ・PM_BT_DET,_P		PM_init
-
-  ・8tics毎に呼ばれ、３チャンネル分取り込むとADCを停止します。
-  　タスク起動時、レジスタには前回の取り込み値が入っています。
- ======================================================== */
-/*
-// max -4db
-static const u8 slider_to_codec[64] =
-{
-    127, 125, 124, 123, 121, 120, 119, 117,
-    116, 115, 113, 112, 111, 109, 108, 107,
-    105, 104, 103, 101, 100,  99,  98,  96,
-     95,  94,  92,  91,  90,  88,  87,  86,
-     84,  83,  82,  80,  79,  78,  76,  75,
-     74,  72,  71,  70,  69,  67,  66,  65,
-     63,  62,  61,  59,  58,  57,  55,  54,
-     53,  51,  50,  49,  47,  46,  45,  44
-};
-*/
-
-// max -10db
-static const u8 slider_to_codec[64] =
-{
-    127,  126,  125,  124,  123,  122,  121,  120,
-    119,  118,  117,  116,  115,  114,  113,  112,
-    111,  110,  109,  109,  108,  107,  106,  105,
-    104,  103,  102,  101,  100,   99,   98,   97,
-     96,   95,   94,   93,   92,   91,   90,   89,
-     88,   87,   86,   85,   84,   83,   82,   81,
-     81,   80,   79,   78,   77,   76,   75,   74,
-     73,   72,   71,   70,   69,   68,   67,   66
-};
-
-void tsk_adc(  )
-{
-    static u8 task_interval = 0;
-    static u8 old_tune;
-    static u8 sndvol_codec;
-    static u8 bt_temp_old;
-
-    if( task_interval-- != 0 )
-    {
-        return;
-    }
-    else
-    {
-        task_interval = (u8)( INTERVAL_TSK_ADC / SYS_INTERVAL_TICK );
-    }
-
-
-    if( adc_updated )
-    {
-        if( system_status.pwr_state == ON )
-        {
-            // Tune ///////////////////////////////////////
-            {
-                // 似非ヒステリシス V2
-                //  ガリオームには適さない
-#define KIKAN 32
-                static u8 old_value;
-                static s8 diffs;
-                u8        temp;
-
-                if( abs( adc_raw_dep - old_value ) >= 2 )
-                {
-                    // 大きく離れた
-                    vreg_ctr[ VREG_C_TUNE ] = adc_raw_dep;
-                    old_value = adc_raw_dep;
-#if 0
-                    割り込み入れない;
-                    割り込みを入れるようであれば、ちゃんと変化チェックする;
-
-                    set_irq( VREG_C_IRQ0, REG_BIT_VR_TUNE_CHANGE );
-#endif
-                    diffs = 0;
-                }
-                else
-                {
-                    // 近所の値でも、ある期間でいっぱい偏っていたらそっちに寄せる
-                    static u8 kikan_count = KIKAN;
-                    if( old_value < adc_raw_dep )
-                    {
-                        diffs += 1;
-                    }
-                    else if( old_value > adc_raw_dep )
-                    {
-                        diffs -= 1;
-                    }
-
-                    if( --kikan_count == 0 )
-                    {
-                        if( diffs >= KIKAN && ( diffs < 64 ))
-                        {
-                            old_value += 1;
-                        }
-                        else if( ( diffs <= ( 256 - KIKAN )) && ( diffs > ( 128 + 64 ) ))  // あらー？
-                        {
-                            old_value -= 1;
-                        }
-                        vreg_ctr[ VREG_C_TUNE ] = old_value;
-                        kikan_count = KIKAN;
-                        diffs = 0;
-                    }
-                }
-            }
-            vreg_ctr[ VREG_C_DBG1 ] = vreg_ctr[ VREG_C_TUNE ];
-            vreg_ctr[ VREG_C_DBG2 ] = adc_raw_dep;  // dbg
-
-            // Volume /////////////////////////////////////
-            {
-                // 似非ヒステリシスを付けて64段
-                u8        temp;
-                static u8 vol_old;
-                static u8 force_update_vol;
-
-                if( abs( adc_raw_vol - vol_old ) >= 2 )       // 生値でこれくらいずれたら更新
-                {
-//                    if( vreg_ctr[ VREG_C_SND_VOL ] != ( adc_raw_vol / 4 ) )
-                    {
-                        vol_old = adc_raw_vol;
-                        // レジスタ更新
-                        vreg_ctr[ VREG_C_SND_VOL ] = ( adc_raw_vol / 4 );
-                        vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_raw_vol / ( 256 / 32 );  // ←adc値でよい
-
-                        // codecに伝える
-                        iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] );
-#ifndef _MODEL_CTR_
-                        iic_mcu_write_a_byte( IIC_SLA_DCP, 0, slider_to_codec[ ( 255 - adc_raw_vol ) / 4 ] );  // todo
-#endif
-//                        set_irq( VREG_C_IRQ0, REG_BIT_VR_SNDVOL_CHANGE );  // 割り込み廃止
-                        force_update_vol = 100;
-                    }
-                }
-
-                {
-                    // ポーリング
-                    if( --force_update_vol == 0 )
-                    {
-                        vol_old = adc_raw_vol;
-                        // レジスタ更新
-//                        vreg_ctr[ VREG_C_SND_VOL ] = temp;
-//                        vreg_twl[ REG_TWL_INT_ADRS_VOL ] = adc_raw_vol / ( 256 / 32 );  // ←adc値でよい
-                        // codecに伝える
-                        iic_mcu_write_a_byte( IIC_SLA_CODEC, CODEC_REG_VOL, slider_to_codec[ adc_raw_vol / 4 ] );
-                        force_update_vol = 100;
-                    }
-                }
-            }
-
-
-            // TUNE_LED ///////////////////////////////////
-            // ここで？仕様？
-            {
-                switch ( vreg_ctr[VREG_C_LED_TUNE] )
-                {
-                case LED_TUNE_ILM_ON:
-                    LED_duty_TUNE = vreg_ctr[VREG_C_LED_BRIGHT];
-                    break;
-
-                case LED_TUNE_ILM_SVR:
-                    LED_duty_TUNE = vreg_ctr[VREG_C_TUNE] / 16;
-                    break;
-
-                case LED_TUNE_ILM_OFF:
-                default:
-                    LED_duty_TUNE = 0;
-                    break;
-                }
-            }
-            adc_updated = 0;
-        }
-    }
-
-
-    ADCEN = 1;
-    ADM =  0b00011011;      // セレクトモード、章圧、fCLK/6 ///ここから ↓
-
-    ADPC = 0x06;            // ADCポートのセレクト
-    ADS = ADC_SEL_TUNE;
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    ADCS = 1;               // AD開始。                     /// ここまで　↑　までに1us=8clk以上開ける
-
-    ADIF = 0;
-    ADMK = 0;
-
-}
-
-
-/* ========================================================
-　過去３つのminでもMAXでもない値を返す
- 　突発的なノイズを除く。
- 　根本対策ではないが、これはこれで使い道がある。
-======================================================== */
-static u8 getmean3( u8 * hist )
-{
-    if( *hist > *( hist + 1 ) )
-    {
-        if( *hist > *( hist + 2 ) )
-        {
-            return( ( *( hist + 1 ) > *( hist + 2 ) ) ? *( hist + 1 ) : *( hist + 2 ) );
-        }
-        else
-        {
-            return( *hist );
-        }
-    }else{
-        if( *hist > *( hist + 2 ) )
-        {
-            return( *hist );
-        }
-        else
-        {
-            return( ( *( hist + 1 ) < *( hist + 2 ) ) ? *( hist + 1 ) : *( hist + 2 ) );
-        }
-    }
-}
-
-
-
-/* ========================================================
-　自前で次のチャンネル
-　　一通り終わったら止める
- ======================================================== */
-__interrupt void int_adc(  )
-{
-    static u8 hist_tune[3];
-    static u8 hist_snd_vol[3];
-    static u8 hist_bt_temp[3];
-    static u8 index;
-
-    EI(  );
-    switch ( ADS )
-    {
-/*
-case ( ADC_SEL_AMB_BRIT ):
-        vreg_ctr[ VREG_C_AMBIENT_BRIGHTNESS ] = ADCRH;
-        break;
-*/
-
-    case ( ADC_SEL_TUNE ):
-        hist_tune[index] = ADCRH;
-#ifdef _MODEL_WM0_
-        adc_raw_dep = 255 - getmean3( hist_tune );
-#else
-        adc_raw_dep = getmean3( hist_tune );
-#endif
-        break;
-
-    case ( ADC_SEL_VOL ):
-        hist_snd_vol[index] = ADCRH;
-#ifdef _MODEL_CTR_JIKKI_
-        adc_raw_vol = ( 255 - getmean3( hist_snd_vol ));
-#else
-        adc_raw_vol = getmean3( hist_snd_vol );
-#endif
-        // TWL用レジスタ(32段)の更新。アトミックな処理として扱わないと不都合が。
-        /// 割り込みはHorizonを通してコマンドを発行されるのを待てばよい
-        break;
-
-    case ( ADC_SEL_BATT_TEMP ):
-        hist_bt_temp[index] = ADCRH;
-        raw_adc_temperature = getmean3( hist_bt_temp );
-        renge_task_immed_add( PM_bt_temp_update );
-        break;
-
-    case ( ADC_SEL_BATT_DET ):
-//    vreg_ctr[ VREG_C_DBG_BATT_DET ] = ADCRH;
-        // todo
-        break;
-    }
-
-
-// もっとまともな書き方がありそうだ
-// if( ADS == ADC_SEL_BATT_DET ){
-    if( ADS != ADC_SEL_BATT_TEMP )
-    {                           // 電池判別は電源投入の一回のみ
-        ADS += 1;               // 次のチャンネル
-        BT_TEMP_P = 1;              // 電池温度監視スタート
-    }
-    else
-    {
-        ADCEN = 0;              // 止めてしまう
-        BT_TEMP_P = 0;              // 電池温度監視スタート
-        adc_updated = 1;
-        index = ( index == 2 ) ? 0 : ( index + 1 );
-    }
-}
-
-
-
-/* ========================================================
- tsk_adcと競合することを考慮していません。
- ======================================================== */
-u8 get_adc( u8 ch )
-{
-    u8      temp;
-
-    ADMK = 1;
-    ADIF = 0;
-
-    ADCEN = 1;
-    ADCS = 0;
-    ADM = 0b00100011;          // セレクトモード、昇圧、fCLK/6  ///ここから↓
-
-    ADPC = 0x06;                // ADCポートのセレクト
-    ADS = ch;
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    NOP();
-    ADCS = 1;                   // AD開始。                     /// ここまで↑　に、1us以上開ける
-
-    ADMK = 0;
-    while( ADIF == 0 ){;}
-    temp = ADCRH;
-    ADCEN = 0;
-
-    return ( temp );
-}
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.h
@ -1,43 +0,0 @@
-#ifndef __adc__
-#define __adc__
-
-#include "jhl_defs.h"
-
-///////////////////////////////////////
-// ANI2 P22
-#define ADC_SEL_AMB_BRIT  0x02
-
-/*
-// ANI3 P23
-#define ADC_SEL_GYRO_YAW  0x03
-// ANI4 P24
-#define ADC_SEL_GYRO_PITCH 0x04
-// ANI5 P25
-#define ADC_SEL_GYRO_ROLL 0x05
-*/
-
-// ANI6 P26
-#define ADC_SEL_TUNE      0x06
-// ANI7 P27
-#define ADC_SEL_VOL       0x07
-
-// ANI8 P150
-#define ADC_SEL_BATT_TEMP 0x08
-// ANI9 P151
-#define ADC_SEL_BATT_DET  0x09
-
-
-
-///////////////////////////////////////
-#define CODEC_REG_VOL 0x13
-
-
-
-///////////////////////////////////////
-
-
-///////////////////////////////////////
-u8 get_adc( u8 ch );
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/adc.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/batt_params.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/batt_params.h
@ -1,80 +0,0 @@
-/* ========================================================
-    各社バッテリーパラメータ
- ======================================================== */
-enum BATT_VENDER {
-    BT_PANASONIC,  // open
-    BT_UNKNOWN1,
-    BT_UNKNOWN2,
-    BT_UNKNOWN3,
-    BT_UNKNOWN4,
-    BT_UNKNOWN5,
-    BT_UNKNOWN6,   // gnd
-    BT_MAXELL
-    };
-
-
-static const u8 BT_PARAM[][64] = {
-    // ID = 0 GND 白箱
-    /// パラメータ無し
-    { // ID = 1 120 ohm
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-    },
-    { // ID = 2 360 hom
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-    },
-    { // ID = 3 750 ohm
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-    },
-    { // ID = 4 1.3kohm
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-    },
-    { // ID = 5 2.7kohm パナ
-    0xAD, 0x30, 0xAE, 0x70, 0xB0, 0x00, 0xB3, 0x00,
-    0xB4, 0x70, 0xB5, 0xA0, 0xB7, 0x80, 0xBA, 0x00,
-
-    0xBB, 0x90, 0xBD, 0x00, 0xBE, 0x00, 0xBF, 0xF0,
-    0xC3, 0x00, 0xC5, 0xC0, 0xC8, 0x00, 0xCA, 0xC0,
-
-    0x04, 0x00, 0x12, 0x00, 0x0C, 0x10, 0x24, 0x00,
-    0x10, 0xD0, 0x1B, 0xF0, 0x0A, 0xF0, 0x08, 0xE0,
-
-    0x0C, 0xF0, 0x08, 0xC0, 0x08, 0xB0, 0x07, 0xF0,
-    0x0B, 0x00, 0x05, 0xD0, 0x02, 0x00, 0x09, 0x00
-    },
-    { // ID = 6 8.2kohm
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
-    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-    },
-    { // ID = 7 マクセル
-    0xAD, 0x30, 0xAE, 0x70, 0xB0, 0x00, 0xB3, 0x00,
-    0xB4, 0x70, 0xB5, 0xA0, 0xB7, 0x80, 0xBA, 0x00,
-
-    0xBB, 0x90, 0xBD, 0x00, 0xBE, 0x00, 0xBF, 0xF0,
-    0xC3, 0x00, 0xC5, 0xC0, 0xC8, 0x00, 0xCA, 0xC0,
-
-    0x04, 0x00, 0x12, 0x00, 0x0C, 0x10, 0x24, 0x00,
-    0x10, 0xD0, 0x1B, 0xF0, 0x0A, 0xF0, 0x08, 0xE0,
-
-    0x0C, 0xF0, 0x08, 0xC0, 0x08, 0xB0, 0x07, 0xF0,
-    0x0B, 0x00, 0x05, 0xD0, 0x02, 0x00, 0x09, 0x00
-    }
-};
-
-static const unsigned char  BT_PANA_RCOMP      = 135;
-static const float BT_PANA_TEMPCOUP   = 0.3;
-static const float BT_PANA_TEMPCODN   = 0.5;
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215_2.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215_2.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215_3.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_C2_0B_1215_3.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_T_0B_1215_3.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bin/mcu_T_0B_1215_3.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TEG2.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TEG2.hex
@ -1,982 +0,0 @@
-:02000000C20438
-:02000200FFFFFE
-:0400100053475547B6
-:02001C00D948C1
-:0200240045494C
-:02002A009247FB
-:08003400724A2F4A6D4A4D4744
-:02004A00574716
-:0400C0007EFBFF853F
-:0A00C400FFFFFFFFFFFFFFFFFFFF3C
-:0A00CE00FFFFFFFFFFFFFFFFFFFF32
-:1000D800C7FDC902C736F00071F4C6DE06713018D4
-:1000E800F9EF2B51105FA8FFD1DD13713018F971AA
-:1000F8000300710B2071103EFBFD6201EF1036000A
-:1001080000868767D1DFFB66D1DFF6FD6201360026
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-:10013800EF01E660610786EFD867D161E8FDDB0370
-:10014800FD5302EF8CC6D7717BFACEA016CEA180E4
-:10015800CEA408F5AAFFF5A9FFD78F18F931350AFB
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-:100178000EF520FFCE23F0CE2EFCF401F402F40499
-:10018800F405F406CD0740F40CF408F40FF521FF4C
-:10019800CE22E9CE24FBCE25F3CE26FCCE271FCED9
-:1001A8002CFFCE2FFFCE28FFF53000F53100F533B8
-:1001B80000F53400CF350003CF370019F53C00F5C2
-:1001C8003E00F54300F54700CF530006F55700F60B
-:1001D800BEE0BEE2F5D0FFCBE4FFFFCBE6FFFFCEEB
-:1001E800D4FFCEE8FFCEECFFCEE9FFCEEDFFCEEA9E
-:1001F800FFCEEEFECEEBFFCEEFFFCED8FFCEDCFF7C
-:10020800CE38B1CE3971F537FF7108F20090BFB41E
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-:1002680031040009CF16F902EF03F516F9FD7934C8
-:10027800FDF737FDA402FD2C46713221712BE7FDF5
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-:1002B8000403F6EF01E6603418F9718C8971999995
-:1002C800D7CEABACD78C05318EED830C8C05318E37
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-:10036800DA304000C1FDEA02FDDD02C0D2DD06FD43
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-:104CBA0009FC154D00FD9F06B4DF4ADF80DFCFFCFB
-:104CCA002D4D00FD9F06100AC0317D0514D715BD74
-:104CDA00DA13BDD88DDC9DDDD7C9DA803FC9D8008B
-:104CEA0000F4DDD7118C019DDD11AC02BDD811ACE9
-:104CFA0004BDDA1704060016D78C019DDDAC02BD8F
-:104D0A00D8AC04BDDA1704060016D7A806BDDAA87F
-:104D1A0004BDD888089DDDD7A80C14A80A128809F2
-:104D2A009DDCD7A80CBDDAA80ABDD888099DDDD7B5
-:104D3A00A80635B806A80433B804880861A8DC9820
-:0D4D4A0008D715B80613B8048DDC9808D7FB
-:0A4FF60031363A30383A3139000004
-:00000001FF
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TEG2CTRC.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TEG2CTRC.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TS.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.TS.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.jikki-X3.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.0_10.jikki-X3.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.lmf
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.lmf
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.sym
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr.sym
@ -1,576 +0,0 @@
-#05
-;FF     PUBLIC
-02FFED8@@CPR1
-02FFEDE@@FPRF1
-02FFEDF@@FPRF2
-02FFEDE@@FPRFP
-02FFED8@@FPRS
-02FFEDC@@FPRXD
-02FFEDC@@FPRXP
-02FFEDD@@FPRXS
-0100683@@bbcd
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-0100934@@faddx
-0100A5E@@fdiv
-0100A6E@@fdivx
-01008A4@@finfws
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-0104F87@@flds2
-0104F32@@fldsd
-0104F48@@fldsk_f
-0104F5D@@fldsk_n
-01008C7@@fmthrr
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-01007F8@@fnor
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-0104E84@@fsqrtx
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-0100830@@fstore
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-0000000_@MAA
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-0100E37returnAfterRAMExecution
-02FFCCCset_info_interrupted
-;FF     @cstart
-;FF     loader
-<010015F_hdwinit2
-;FF     pm
-<01022F9_BT_PANA_RCOMP
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-;FF     i2c_ctr
-<0102302_lpf_coeff
-02FF913_reg_adrs
-02FF914_reg_adrs_internal
-02FFC7C_state
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-;FF     main
-<0102332_lpf_coeff
-01002B3_read_dipsw
-;FF     magic
-<0102100_MGC_HEAD
-0100FF6_MGC_LOAD
-0104FF6_MGC_TAIL
-;FF     WDT
-;FF     i2c_mcu
-<0102ED0_iic_mcu_call_slave
-0102EE6_iic_mcu_send_a_byte
-0102F2F_iic_mcu_send_re_st
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-;FF     i2c_twl
-<0102392_lpf_coeff
-;FF     ini_VECT
-;FF     led
-<01023F1_MSG_MAIL
-02FFB2A_blue_to
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-02FFB35_flag_wifi_TX
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-02FFB33_flg_char_space
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-02FFB26_state
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-02FFC7E_state_led_cam
-02FFB37_state_led_cam_twl
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-02FFB30_state_wifi_tx
-02FFB32_task_interval
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-0103058bs_S0172
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-;FF     rtc
-<01023F6_lpf_coeff
-;FF     vreg_ctr
-<0102426_lpf_coeff
-02FFBA0_rsub_temp
-0103536bs_F0101
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-;FF     vreg_twl
-<0102456_lpf_coeff
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-;FF     adc
-<02FFBB6_bt_temp_old
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-01039FFbs_F0074
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-;FF     renge
-<0103C23_renge_task_immed_init
-02FFC98_tasks
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-;FF     accero
-<01024F6_lpf_coeff
-0103DF3bs_F0038
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-;FF     self_flash
-<0100420_FSL_Close
-0100407_FSL_Open
-0100424_firm_duplicate
-01004AC_my_FSL_Init
-01002F4bs_F0061
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-0100310es_S0060
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-;FF     reboot
-;FF     sw
-<02FFCAE_cnt_force_off
-0102528_lpf_coeff
-02FFCAF_task_interval
-0103F1Dbs_F0060
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-;FF     task_debug
-<02FFCB0_count
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-;FF     task_misc
-<010425D_end
-02FFCB2_interval_task_misc_stat
-0102588_lpf_coeff
-02FFBDE_state_old
-01040C2bs_F0060
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-;FF     task_sys
-<010442B_chk_emergencyExit
-01025B8_lpf_coeff
-02FFBE0_state
-02FFCB4_timeout
-010426Ebs_F0057
-010427Aes_F0057
-;FF     pedo_alg_thre_det2
-<0102618_DAYS_FROM_HNY
-02FFBE2_acc_norm
-02FFBE8_acc_norm_temp
-02FFC70_hist_indx
-010465D_hosu_increment
-02FFBEA_interval_hh
-02FFC74_last_hour_fny
-01025E8_lpf_coeff
-02FFBF0_norm_hist
-02FFC76_p_record_buffer
-02FFBEE_peak_h
-02FFBEC_peak_l
-02FFC71_t_rise
-02FFCB6_th_H
-02FFCB8_th_L
-02FFBEB_time_l
-010447Fbs_F0097
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-010449Ees_S0096
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-010447Fes_S0099
-;FF     fsl_block_cmd
-;FF     fsl_block_check
-;FF     fsl_common
-;FF     fsl_reset
-;FF     fsl_si_ibf
-;FF     fsl_phySwap
-;FF     fsl_si_common
-;FF     fsl_swap
-;FF     fsl_write
-;FF     @lumul
-;FF     @isrem
-;FF     @iurem
-;FF     @lsdiv
-;FF     @ludiv
-;FF     @ladd
-;FF     @iscmp
-;FF     @lband
-;FF     @SEGREG
-;FF     @RTARG0
-;FF     @bcdtob
-;FF     @bbcd
-;FF     abs
-;FF     m_fmul
-;FF     m_fcom1
-;FF     m_fcom5
-;FF     m_fcom6
-;FF     m_fsub
-;FF     m_fadd
-;FF     m_fdiv
-;FF     m_frev
-;FF     m_ftols
-;FF     m_ftolu
-;FF     m_lstof
-;FF     m_lutof
-;FF     m_sqrt
-;FF     m_fcom4
-;FF     m_fsqrtx
-;FF     m_fcom3
-;FF     @rom
-=
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_TS_V01.10_0415_1710pcs.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_TS_V01.10_0415_1710pcs.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_k0r.map
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_k0r.map
@ -1,656 +0,0 @@
-
-
-
-78K0R Linker W1.31                            Date:13 Jun 2010 Page:   1
-
-Command:   -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -obsr.l
-           mf ..\..\..\..\Program Files\NEC Electronics Tools\CC78K0R\W2
-           .10\lib78k0r\s0rm.rel -go85h,0FC00h,1024 -gi0FFFFFFFFFFFFFFFF
-           FFFFh -pbsr_k0r.map -nkd -gb7EFBFFh -bC:\Program Files\NEC El
-           ectronics Tools\FSL78K0R_Type02ES\V1.20\lib78k0r\fsl.lib -bcl
-           0rdm.lib -bcl0rm.lib -bcl0rmf.lib -iC:\Program Files\NEC Elec
-           tronics Tools\CC78K0R\W2.10\lib78k0r -dbsr_mcu.dr -s -w0 load
-           er.rel pm.rel i2c_ctr.rel main.rel magic.rel WDT.rel i2c_mcu.
-           rel i2c_twl.rel ini_VECT.rel led.rel rtc.rel vreg_ctr.rel vre
-           g_twl.rel adc.rel renge.rel accero.rel self_flash.rel reboot.
-           rel sw.rel task_debug.rel task_misc.rel task_sys.rel pedo_alg
-           _thre_det2.rel
-Para-file:
-Out-file:  bsr.lmf
-Map-file:  bsr_k0r.map
-Direc-file:bsr_mcu.dr
-
-
-*** Link information ***
-
-    68 output segment(s)
- 3ED6H byte(s) real data
-  4631 symbol(s) defined
-
-
-*** Memory map ***
-
-
-  SPACE=REGULAR
-
-  MEMORY=BCL0
-  BASE ADDRESS=00000H   SIZE=01000H
-         OUTPUT   INPUT    INPUT      BASE      SIZE
-         SEGMENT  SEGMENT  MODULE     ADDRESS
-         @@VECT00                     00000H    00002H  CSEG AT
-                  @@VECT00 @cstart    00000H    00002H
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-                  LDR_CNSL loader     00002H    00000H
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-                  LDR_CNSL main       00002H    00000H
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-                  LDR_CNSL WDT        00002H    00000H
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-                  LDR_CNSL self_flash
-                                      00002H    00000H
-         LDR_CNSL                     00002H    00000H  CSEG PAGE64KP
-                  LDR_CNSL reboot     00002H    00000H
-         ??NMIROM                     00002H    00002H  CSEG
-* gap *                               00004H    0000CH
-         @@VECT10                     00010H    00004H  CSEG AT
-                  @@VECT10 ini_VECT   00010H    00004H
-* gap *                               00014H    00008H
-         @@VECT1C                     0001CH    00002H  CSEG AT
-                  @@VECT1C ini_VECT   0001CH    00002H
-* gap *                               0001EH    00006H
-         @@VECT24                     00024H    00002H  CSEG AT
-                  @@VECT24 ini_VECT   00024H    00002H
-* gap *                               00026H    00004H
-         @@VECT2A                     0002AH    00002H  CSEG AT
-                  @@VECT2A ini_VECT   0002AH    00002H
-* gap *                               0002CH    00008H
-         @@VECT34                     00034H    00008H  CSEG AT
-                  @@VECT34 ini_VECT   00034H    00008H
-* gap *                               0003CH    0000EH
-         @@VECT4A                     0004AH    00002H  CSEG AT
-                  @@VECT4A ini_VECT   0004AH    00002H
-* gap *                               0004CH    0000EH
-         @@VECT5A                     0005AH    00002H  CSEG AT
-                  @@VECT5A ini_VECT   0005AH    00002H
-* gap *                               0005CH    00006H
-         @@VECT62                     00062H    00002H  CSEG AT
-                  @@VECT62 ini_VECT   00062H    00002H
-* gap *                               00064H    0005CH
-         ?CSEGOB0                     000C0H    00004H  CSEG OPT_BYTE
-         @@CODE                       000C4H    00000H  CSEG BASE
-                  @@CODE   magic      000C4H    00000H
-                  @@CODE   ini_VECT   000C4H    00000H
-         LDR_CODL                     000C4H    00000H  CSEG
-                  LDR_CODL loader     000C4H    00000H
-                  LDR_CODL main       000C4H    00000H
-                  LDR_CODL WDT        000C4H    00000H
-                  LDR_CODL self_flash
-                                      000C4H    00000H
-                  LDR_CODL reboot     000C4H    00000H
-         ?CSEGSI                      000C4H    0000AH  CSEG
-         ?OCDSTAD                     000CEH    0000AH  CSEG
-         LDR_CODE                     000D8H    00402H  CSEG
-                  LDR_CODE loader     000D8H    0017EH
-                  LDR_CODE main       00256H    00082H
-                  LDR_CODE WDT        002D8H    00004H
-                  LDR_CODE self_flash
-                                      002DCH    001F2H
-                  LDR_CODE reboot     004CEH    0000CH
-         @@LCODE                      004DAH    007BDH  CSEG
-                  @@LCODE  @cstart    004DAH    0006DH
-                  @@LCODE  @lumul     00547H    0002BH
-                  @@LCODE  @isrem     00572H    00021H
-                  @@LCODE  @iurem     00593H    0002FH
-                  @@LCODE  @lsdiv     005C2H    00039H
-                  @@LCODE  @ludiv     005FBH    0003FH
-                  @@LCODE  @ladd      0063AH    0000FH
-                  @@LCODE  @iscmp     00649H    0000CH
-                  @@LCODE  @lband     00655H    00014H
-                  @@LCODE  @bcdtob    00669H    0001AH
-                  @@LCODE  @bbcd      00683H    00024H
-                  @@LCODE  m_fmul     006A7H    00151H
-                  @@LCODE  m_fcom1    007F8H    000CFH
-                  @@LCODE  m_fcom5    008C7H    0002AH
-                  @@LCODE  m_fcom6    008F1H    0001FH
-                  @@LCODE  m_fsub     00910H    00014H
-                  @@LCODE  m_fadd     00924H    0013AH
-                  @@LCODE  m_fdiv     00A5EH    0012FH
-                  @@LCODE  m_frev     00B8DH    00004H
-                  @@LCODE  m_ftols    00B91H    00078H
-                  @@LCODE  m_ftolu    00C09H    0002BH
-                  @@LCODE  m_lstof    00C34H    00016H
-                  @@LCODE  m_lutof    00C4AH    0004DH
-         FSL_CODE                     00C97H    00322H  CSEG
-                  FSL_CODE fsl_block_cmd
-                                      00C97H    0002BH
-                  FSL_CODE fsl_block_check
-                                      00CC2H    00013H
-                  FSL_CODE fsl_common
-                                      00CD5H    0014FH
-                  FSL_CODE fsl_reset
-                                      00E24H    00001H
-                  FSL_CODE fsl_si_ibf
-                                      00E25H    00064H
-                  FSL_CODE fsl_phySwap
-                                      00E89H    0004DH
-                  FSL_CODE fsl_si_common
-                                      00ED6H    00061H
-                  FSL_CODE fsl_swap   00F37H    00030H
-                  FSL_CODE fsl_write
-                                      00F67H    00052H
-* gap *                               00FB9H    0003DH
-         MGC_LOAD                     00FF6H    0000AH  CSEG AT
-                  MGC_LOAD magic      00FF6H    0000AH
-
-  MEMORY=ROM
-  BASE ADDRESS=02000H   SIZE=03000H
-         OUTPUT   INPUT    INPUT      BASE      SIZE
-         SEGMENT  SEGMENT  MODULE     ADDRESS
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  @cstart    02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  pm         02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  i2c_ctr    02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  i2c_mcu    02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  i2c_twl    02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  ini_VECT   02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  led        02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  rtc        02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  vreg_ctr   02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  vreg_twl   02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  adc        02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  renge      02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  accero     02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  sw         02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  task_debug
-                                      02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  task_misc
-                                      02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  task_sys   02000H    00000H
-         @@CNSTL                      02000H    00000H  CSEG PAGE64KP
-                  @@CNSTL  pedo_alg_thre_det2
-                                      02000H    00000H
-         @@CNSTL                      02000H    0000AH  CSEG PAGE64KP
-                  @@CNSTL  @bcdtob    02000H    0000AH
-         @@CNSTL                      0200AH    00010H  CSEG PAGE64KP
-                  @@CNSTL  @bbcd      0200AH    00010H
-         @@CNSTL                      0201AH    000CEH  CSEG PAGE64KP
-                  @@CNSTL  m_fcom5    0201AH    000CEH
-         @@CNSTL                      020E8H    00014H  CSEG PAGE64KP
-                  @@CNSTL  m_fsqrtx   020E8H    00014H
-         @@R_INIS                     020FCH    00000H  CSEG UNIT64KP
-                  @@R_INIS @cstart    020FCH    00000H
-                  @@R_INIS loader     020FCH    00000H
-                  @@R_INIS pm         020FCH    00000H
-                  @@R_INIS i2c_ctr    020FCH    00000H
-                  @@R_INIS main       020FCH    00000H
-                  @@R_INIS magic      020FCH    00000H
-                  @@R_INIS WDT        020FCH    00000H
-                  @@R_INIS i2c_mcu    020FCH    00000H
-                  @@R_INIS i2c_twl    020FCH    00000H
-                  @@R_INIS ini_VECT   020FCH    00000H
-                  @@R_INIS led        020FCH    00000H
-                  @@R_INIS rtc        020FCH    00000H
-                  @@R_INIS vreg_ctr   020FCH    00000H
-                  @@R_INIS vreg_twl   020FCH    00000H
-                  @@R_INIS adc        020FCH    00000H
-                  @@R_INIS renge      020FCH    00000H
-                  @@R_INIS accero     020FCH    00000H
-                  @@R_INIS self_flash
-                                      020FCH    00000H
-                  @@R_INIS reboot     020FCH    00000H
-                  @@R_INIS sw         020FCH    00000H
-                  @@R_INIS task_debug
-                                      020FCH    00000H
-                  @@R_INIS task_misc
-                                      020FCH    00000H
-                  @@R_INIS task_sys   020FCH    00000H
-                  @@R_INIS pedo_alg_thre_det2
-                                      020FCH    00000H
-                  @@R_INIS @rom       020FCH    00000H
-         @@CALT                       020FCH    00000H  CSEG
-                  @@CALT   @cstart    020FCH    00000H
-                  @@CALT   loader     020FCH    00000H
-                  @@CALT   pm         020FCH    00000H
-                  @@CALT   i2c_ctr    020FCH    00000H
-                  @@CALT   main       020FCH    00000H
-                  @@CALT   magic      020FCH    00000H
-                  @@CALT   WDT        020FCH    00000H
-                  @@CALT   i2c_mcu    020FCH    00000H
-                  @@CALT   i2c_twl    020FCH    00000H
-                  @@CALT   ini_VECT   020FCH    00000H
-                  @@CALT   led        020FCH    00000H
-                  @@CALT   rtc        020FCH    00000H
-                  @@CALT   vreg_ctr   020FCH    00000H
-                  @@CALT   vreg_twl   020FCH    00000H
-                  @@CALT   adc        020FCH    00000H
-                  @@CALT   renge      020FCH    00000H
-                  @@CALT   accero     020FCH    00000H
-                  @@CALT   self_flash
-                                      020FCH    00000H
-                  @@CALT   reboot     020FCH    00000H
-                  @@CALT   sw         020FCH    00000H
-                  @@CALT   task_debug
-                                      020FCH    00000H
-                  @@CALT   task_misc
-                                      020FCH    00000H
-                  @@CALT   task_sys   020FCH    00000H
-                  @@CALT   pedo_alg_thre_det2
-                                      020FCH    00000H
-         @@RLINIT                     020FCH    00000H  CSEG UNIT64KP
-                  @@RLINIT loader     020FCH    00000H
-                  @@RLINIT pm         020FCH    00000H
-                  @@RLINIT i2c_ctr    020FCH    00000H
-                  @@RLINIT main       020FCH    00000H
-                  @@RLINIT magic      020FCH    00000H
-                  @@RLINIT WDT        020FCH    00000H
-                  @@RLINIT i2c_mcu    020FCH    00000H
-                  @@RLINIT i2c_twl    020FCH    00000H
-                  @@RLINIT ini_VECT   020FCH    00000H
-                  @@RLINIT led        020FCH    00000H
-                  @@RLINIT rtc        020FCH    00000H
-                  @@RLINIT vreg_ctr   020FCH    00000H
-                  @@RLINIT vreg_twl   020FCH    00000H
-                  @@RLINIT adc        020FCH    00000H
-                  @@RLINIT renge      020FCH    00000H
-                  @@RLINIT accero     020FCH    00000H
-                  @@RLINIT self_flash
-                                      020FCH    00000H
-                  @@RLINIT reboot     020FCH    00000H
-                  @@RLINIT sw         020FCH    00000H
-                  @@RLINIT task_debug
-                                      020FCH    00000H
-                  @@RLINIT task_misc
-                                      020FCH    00000H
-                  @@RLINIT task_sys   020FCH    00000H
-                  @@RLINIT pedo_alg_thre_det2
-                                      020FCH    00000H
-                  @@RLINIT @rom       020FCH    00000H
-         @@CODEL                      020FCH    00000H  CSEG
-                  @@CODEL  pm         020FCH    00000H
-                  @@CODEL  i2c_ctr    020FCH    00000H
-                  @@CODEL  magic      020FCH    00000H
-                  @@CODEL  i2c_mcu    020FCH    00000H
-                  @@CODEL  i2c_twl    020FCH    00000H
-                  @@CODEL  ini_VECT   020FCH    00000H
-                  @@CODEL  led        020FCH    00000H
-                  @@CODEL  rtc        020FCH    00000H
-                  @@CODEL  vreg_ctr   020FCH    00000H
-                  @@CODEL  vreg_twl   020FCH    00000H
-                  @@CODEL  adc        020FCH    00000H
-                  @@CODEL  renge      020FCH    00000H
-                  @@CODEL  accero     020FCH    00000H
-                  @@CODEL  sw         020FCH    00000H
-                  @@CODEL  task_debug
-                                      020FCH    00000H
-                  @@CODEL  task_misc
-                                      020FCH    00000H
-                  @@CODEL  task_sys   020FCH    00000H
-                  @@CODEL  pedo_alg_thre_det2
-                                      020FCH    00000H
-* gap *                               020FCH    00004H
-         MGC_MIMI                     02100H    0000AH  CSEG AT
-                  MGC_MIMI magic      02100H    0000AH
-         @@CNST                       0210AH    00528H  CSEG
-                  @@CNST   @cstart    0210AH    00000H
-                  @@CNST   loader     0210AH    00000H
-                  @@CNST   pm         0210AH    001F8H
-                  @@CNST   i2c_ctr    02302H    00030H
-                  @@CNST   main       02332H    00030H
-                  @@CNST   magic      02362H    00000H
-                  @@CNST   WDT        02362H    00000H
-                  @@CNST   i2c_mcu    02362H    00030H
-                  @@CNST   i2c_twl    02392H    00030H
-                  @@CNST   ini_VECT   023C2H    00000H
-                  @@CNST   led        023C2H    00034H
-                  @@CNST   rtc        023F6H    00030H
-                  @@CNST   vreg_ctr   02426H    00030H
-                  @@CNST   vreg_twl   02456H    00030H
-                  @@CNST   adc        02486H    00070H
-                  @@CNST   renge      024F6H    00000H
-                  @@CNST   accero     024F6H    00030H
-                  @@CNST   self_flash
-                                      02526H    00002H
-                  @@CNST   reboot     02528H    00000H
-                  @@CNST   sw         02528H    00030H
-                  @@CNST   task_debug
-                                      02558H    00030H
-                  @@CNST   task_misc
-                                      02588H    00030H
-                  @@CNST   task_sys   025B8H    00030H
-                  @@CNST   pedo_alg_thre_det2
-                                      025E8H    0004AH
-         ROM_CODE                     02632H    0223FH  CSEG
-                  ROM_CODE pm         02632H    0068DH
-                  ROM_CODE i2c_ctr    02CBFH    00060H
-                  ROM_CODE i2c_mcu    02D1FH    002DBH
-                  ROM_CODE i2c_twl    02FFAH    0005EH
-                  ROM_CODE led        03058H    003CFH
-                  ROM_CODE rtc        03427H    000E0H
-                  ROM_CODE vreg_ctr   03507H    003B2H
-                  ROM_CODE vreg_twl   038B9H    00132H
-                  ROM_CODE adc        039EBH    001E7H
-                  ROM_CODE renge      03BD2H    00221H
-                  ROM_CODE accero     03DF3H    0012AH
-                  ROM_CODE sw         03F1DH    00167H
-                  ROM_CODE task_debug
-                                      04084H    0003EH
-                  ROM_CODE task_misc
-                                      040C2H    001ACH
-                  ROM_CODE task_sys   0426EH    0020BH
-                  ROM_CODE pedo_alg_thre_det2
-                                      04479H    003F8H
-         @@BASE                       04871H    0055DH  CSEG BASE
-                  @@BASE   loader     04871H    00006H
-                  @@BASE   pm         04877H    0003FH
-                  @@BASE   i2c_ctr    048B6H    00163H
-                  @@BASE   main       04A19H    00000H
-                  @@BASE   magic      04A19H    00000H
-                  @@BASE   WDT        04A19H    00000H
-                  @@BASE   i2c_mcu    04A19H    000D9H
-                  @@BASE   i2c_twl    04AF2H    00117H
-                  @@BASE   ini_VECT   04C09H    0007DH
-                  @@BASE   led        04C86H    00000H
-                  @@BASE   rtc        04C86H    00043H
-                  @@BASE   vreg_ctr   04CC9H    00000H
-                  @@BASE   vreg_twl   04CC9H    00000H
-                  @@BASE   adc        04CC9H    000B5H
-                  @@BASE   renge      04D7EH    00000H
-                  @@BASE   accero     04D7EH    00050H
-                  @@BASE   self_flash
-                                      04DCEH    00000H
-                  @@BASE   reboot     04DCEH    00000H
-                  @@BASE   sw         04DCEH    00000H
-                  @@BASE   task_debug
-                                      04DCEH    00000H
-                  @@BASE   task_misc
-                                      04DCEH    00000H
-                  @@BASE   task_sys   04DCEH    00000H
-                  @@BASE   pedo_alg_thre_det2
-                                      04DCEH    00000H
-         @@R_INIT                     04DCEH    00046H  CSEG UNIT64KP
-                  @@R_INIT @cstart    04DCEH    00000H
-                  @@R_INIT loader     04DCEH    00000H
-                  @@R_INIT pm         04DCEH    00004H
-                  @@R_INIT i2c_ctr    04DD2H    00002H
-                  @@R_INIT main       04DD4H    00000H
-                  @@R_INIT magic      04DD4H    00000H
-                  @@R_INIT WDT        04DD4H    00000H
-                  @@R_INIT i2c_mcu    04DD4H    00000H
-                  @@R_INIT i2c_twl    04DD4H    00000H
-                  @@R_INIT ini_VECT   04DD4H    00000H
-                  @@R_INIT led        04DD4H    00002H
-                  @@R_INIT rtc        04DD6H    00000H
-                  @@R_INIT vreg_ctr   04DD6H    00000H
-                  @@R_INIT vreg_twl   04DD6H    00016H
-                  @@R_INIT adc        04DECH    00002H
-                  @@R_INIT renge      04DEEH    00016H
-                  @@R_INIT accero     04E04H    00000H
-                  @@R_INIT self_flash
-                                      04E04H    00000H
-                  @@R_INIT reboot     04E04H    00000H
-                  @@R_INIT sw         04E04H    00002H
-                  @@R_INIT task_debug
-                                      04E06H    00002H
-                  @@R_INIT task_misc
-                                      04E08H    00002H
-                  @@R_INIT task_sys   04E0AH    00002H
-                  @@R_INIT pedo_alg_thre_det2
-                                      04E0CH    00008H
-                  @@R_INIT @rom       04E14H    00000H
-         @@LCODEL                     04E14H    0019DH  CSEG
-                  @@LCODEL abs        04E14H    00008H
-                  @@LCODEL m_sqrt     04E1CH    00013H
-                  @@LCODEL m_fcom4    04E2FH    00041H
-                  @@LCODEL m_fsqrtx   04E70H    000C2H
-                  @@LCODEL m_fcom3    04F32H    0007FH
-* gap *                               04FB1H    00045H
-         MGC_TAIL                     04FF6H    0000AH  CSEG AT
-                  MGC_TAIL magic      04FF6H    0000AH
-
-  MEMORY=RAM
-  BASE ADDRESS=FF900H   SIZE=00500H
-         OUTPUT   INPUT    INPUT      BASE      SIZE
-         SEGMENT  SEGMENT  MODULE     ADDRESS
-         @@DATA                       FF900H    00378H  DSEG BASEP
-                  @@DATA   @cstart    FF900H    00002H
-                  @@DATA   loader     FF902H    00000H
-                  @@DATA   pm         FF902H    00010H
-                  @@DATA   i2c_ctr    FF912H    00004H
-                  @@DATA   main       FF916H    00204H
-                  @@DATA   magic      FFB1AH    00000H
-                  @@DATA   WDT        FFB1AH    00000H
-                  @@DATA   i2c_mcu    FFB1AH    00008H
-                  @@DATA   i2c_twl    FFB22H    00004H
-                  @@DATA   ini_VECT   FFB26H    00000H
-                  @@DATA   led        FFB26H    00012H
-                  @@DATA   rtc        FFB38H    00008H
-                  @@DATA   vreg_ctr   FFB40H    00062H
-                  @@DATA   vreg_twl   FFBA2H    00010H
-                  @@DATA   adc        FFBB2H    00014H
-                  @@DATA   renge      FFBC6H    00012H
-                  @@DATA   accero     FFBD8H    00000H
-                  @@DATA   self_flash
-                                      FFBD8H    00000H
-                  @@DATA   reboot     FFBD8H    00000H
-                  @@DATA   sw         FFBD8H    00004H
-                  @@DATA   task_debug
-                                      FFBDCH    00002H
-                  @@DATA   task_misc
-                                      FFBDEH    00002H
-                  @@DATA   task_sys   FFBE0H    00002H
-                  @@DATA   pedo_alg_thre_det2
-                                      FFBE2H    00096H
-                  @@DATA   @rom       FFC78H    00000H
-         @@INIT                       FFC78H    00046H  DSEG BASEP
-                  @@INIT   @cstart    FFC78H    00000H
-                  @@INIT   loader     FFC78H    00000H
-                  @@INIT   pm         FFC78H    00004H
-                  @@INIT   i2c_ctr    FFC7CH    00002H
-                  @@INIT   main       FFC7EH    00000H
-                  @@INIT   magic      FFC7EH    00000H
-                  @@INIT   WDT        FFC7EH    00000H
-                  @@INIT   i2c_mcu    FFC7EH    00000H
-                  @@INIT   i2c_twl    FFC7EH    00000H
-                  @@INIT   ini_VECT   FFC7EH    00000H
-                  @@INIT   led        FFC7EH    00002H
-                  @@INIT   rtc        FFC80H    00000H
-                  @@INIT   vreg_ctr   FFC80H    00000H
-                  @@INIT   vreg_twl   FFC80H    00016H
-                  @@INIT   adc        FFC96H    00002H
-                  @@INIT   renge      FFC98H    00016H
-                  @@INIT   accero     FFCAEH    00000H
-                  @@INIT   self_flash
-                                      FFCAEH    00000H
-                  @@INIT   reboot     FFCAEH    00000H
-                  @@INIT   sw         FFCAEH    00002H
-                  @@INIT   task_debug
-                                      FFCB0H    00002H
-                  @@INIT   task_misc
-                                      FFCB2H    00002H
-                  @@INIT   task_sys   FFCB4H    00002H
-                  @@INIT   pedo_alg_thre_det2
-                                      FFCB6H    00008H
-                  @@INIT   @rom       FFCBEH    00000H
-         @@INIS                       FFCBEH    00000H  DSEG UNITP
-                  @@INIS   @cstart    FFCBEH    00000H
-                  @@INIS   loader     FFCBEH    00000H
-                  @@INIS   pm         FFCBEH    00000H
-                  @@INIS   i2c_ctr    FFCBEH    00000H
-                  @@INIS   main       FFCBEH    00000H
-                  @@INIS   magic      FFCBEH    00000H
-                  @@INIS   WDT        FFCBEH    00000H
-                  @@INIS   i2c_mcu    FFCBEH    00000H
-                  @@INIS   i2c_twl    FFCBEH    00000H
-                  @@INIS   ini_VECT   FFCBEH    00000H
-                  @@INIS   led        FFCBEH    00000H
-                  @@INIS   rtc        FFCBEH    00000H
-                  @@INIS   vreg_ctr   FFCBEH    00000H
-                  @@INIS   vreg_twl   FFCBEH    00000H
-                  @@INIS   adc        FFCBEH    00000H
-                  @@INIS   renge      FFCBEH    00000H
-                  @@INIS   accero     FFCBEH    00000H
-                  @@INIS   self_flash
-                                      FFCBEH    00000H
-                  @@INIS   reboot     FFCBEH    00000H
-                  @@INIS   sw         FFCBEH    00000H
-                  @@INIS   task_debug
-                                      FFCBEH    00000H
-                  @@INIS   task_misc
-                                      FFCBEH    00000H
-                  @@INIS   task_sys   FFCBEH    00000H
-                  @@INIS   pedo_alg_thre_det2
-                                      FFCBEH    00000H
-                  @@INIS   @rom       FFCBEH    00000H
-         @@DATS                       FFCBEH    00000H  DSEG UNITP
-                  @@DATS   @cstart    FFCBEH    00000H
-                  @@DATS   loader     FFCBEH    00000H
-                  @@DATS   pm         FFCBEH    00000H
-                  @@DATS   i2c_ctr    FFCBEH    00000H
-                  @@DATS   main       FFCBEH    00000H
-                  @@DATS   magic      FFCBEH    00000H
-                  @@DATS   WDT        FFCBEH    00000H
-                  @@DATS   i2c_mcu    FFCBEH    00000H
-                  @@DATS   i2c_twl    FFCBEH    00000H
-                  @@DATS   ini_VECT   FFCBEH    00000H
-                  @@DATS   led        FFCBEH    00000H
-                  @@DATS   rtc        FFCBEH    00000H
-                  @@DATS   vreg_ctr   FFCBEH    00000H
-                  @@DATS   vreg_twl   FFCBEH    00000H
-                  @@DATS   adc        FFCBEH    00000H
-                  @@DATS   renge      FFCBEH    00000H
-                  @@DATS   accero     FFCBEH    00000H
-                  @@DATS   self_flash
-                                      FFCBEH    00000H
-                  @@DATS   reboot     FFCBEH    00000H
-                  @@DATS   sw         FFCBEH    00000H
-                  @@DATS   task_debug
-                                      FFCBEH    00000H
-                  @@DATS   task_misc
-                                      FFCBEH    00000H
-                  @@DATS   task_sys   FFCBEH    00000H
-                  @@DATS   pedo_alg_thre_det2
-                                      FFCBEH    00000H
-                  @@DATS   @rom       FFCBEH    00000H
-         FSL_DATA                     FFCBEH    00010H  DSEG UNITP
-                  FSL_DATA fsl_common
-                                      FFCBEH    00010H
-         @@INITL                      FFCCEH    00000H  DSEG UNIT64KP
-                  @@INITL  loader     FFCCEH    00000H
-                  @@INITL  pm         FFCCEH    00000H
-                  @@INITL  i2c_ctr    FFCCEH    00000H
-                  @@INITL  main       FFCCEH    00000H
-                  @@INITL  magic      FFCCEH    00000H
-                  @@INITL  WDT        FFCCEH    00000H
-                  @@INITL  i2c_mcu    FFCCEH    00000H
-                  @@INITL  i2c_twl    FFCCEH    00000H
-                  @@INITL  ini_VECT   FFCCEH    00000H
-                  @@INITL  led        FFCCEH    00000H
-                  @@INITL  rtc        FFCCEH    00000H
-                  @@INITL  vreg_ctr   FFCCEH    00000H
-                  @@INITL  vreg_twl   FFCCEH    00000H
-                  @@INITL  adc        FFCCEH    00000H
-                  @@INITL  renge      FFCCEH    00000H
-                  @@INITL  accero     FFCCEH    00000H
-                  @@INITL  self_flash
-                                      FFCCEH    00000H
-                  @@INITL  reboot     FFCCEH    00000H
-                  @@INITL  sw         FFCCEH    00000H
-                  @@INITL  task_debug
-                                      FFCCEH    00000H
-                  @@INITL  task_misc
-                                      FFCCEH    00000H
-                  @@INITL  task_sys   FFCCEH    00000H
-                  @@INITL  pedo_alg_thre_det2
-                                      FFCCEH    00000H
-                  @@INITL  @rom       FFCCEH    00000H
-         @@DATAL                      FFCCEH    00000H  DSEG UNIT64KP
-                  @@DATAL  loader     FFCCEH    00000H
-                  @@DATAL  pm         FFCCEH    00000H
-                  @@DATAL  i2c_ctr    FFCCEH    00000H
-                  @@DATAL  main       FFCCEH    00000H
-                  @@DATAL  magic      FFCCEH    00000H
-                  @@DATAL  WDT        FFCCEH    00000H
-                  @@DATAL  i2c_mcu    FFCCEH    00000H
-                  @@DATAL  i2c_twl    FFCCEH    00000H
-                  @@DATAL  ini_VECT   FFCCEH    00000H
-                  @@DATAL  led        FFCCEH    00000H
-                  @@DATAL  rtc        FFCCEH    00000H
-                  @@DATAL  vreg_ctr   FFCCEH    00000H
-                  @@DATAL  vreg_twl   FFCCEH    00000H
-                  @@DATAL  adc        FFCCEH    00000H
-                  @@DATAL  renge      FFCCEH    00000H
-                  @@DATAL  accero     FFCCEH    00000H
-                  @@DATAL  self_flash
-                                      FFCCEH    00000H
-                  @@DATAL  reboot     FFCCEH    00000H
-                  @@DATAL  sw         FFCCEH    00000H
-                  @@DATAL  task_debug
-                                      FFCCEH    00000H
-                  @@DATAL  task_misc
-                                      FFCCEH    00000H
-                  @@DATAL  task_sys   FFCCEH    00000H
-                  @@DATAL  pedo_alg_thre_det2
-                                      FFCCEH    00000H
-                  @@DATAL  @rom       FFCCEH    00000H
-* gap *                               FFCCEH    00132H
-
-  MEMORY=RAM2
-  BASE ADDRESS=FFE20H   SIZE=000C0H
-         OUTPUT   INPUT    INPUT      BASE      SIZE
-         SEGMENT  SEGMENT  MODULE     ADDRESS
-         @@BITS                       FFE20H    00003H  BSEG
-                  @@BITS   @cstart    FFE20H.0  00000H.0
-                  @@BITS   loader     FFE20H.0  00000H.0
-                  @@BITS   pm         FFE20H.0  00000H.1
-                  @@BITS   i2c_ctr    FFE20H.1  00000H.0
-                  @@BITS   main       FFE20H.1  00000H.1
-                  @@BITS   magic      FFE20H.2  00000H.0
-                  @@BITS   WDT        FFE20H.2  00000H.0
-                  @@BITS   i2c_mcu    FFE20H.2  00000H.3
-                  @@BITS   i2c_twl    FFE20H.5  00000H.0
-                  @@BITS   ini_VECT   FFE20H.5  00000H.0
-                  @@BITS   led        FFE20H.5  00000H.0
-                  @@BITS   rtc        FFE20H.5  00000H.3
-                  @@BITS   vreg_ctr   FFE21H.0  00000H.1
-                  @@BITS   vreg_twl   FFE21H.1  00000H.0
-                  @@BITS   adc        FFE21H.1  00000H.1
-                  @@BITS   renge      FFE21H.2  00000H.3
-                  @@BITS   accero     FFE21H.5  00000H.0
-                  @@BITS   self_flash
-                                      FFE21H.5  00000H.0
-                  @@BITS   reboot     FFE21H.5  00000H.0
-                  @@BITS   sw         FFE21H.5  00000H.4
-                  @@BITS   task_debug
-                                      FFE22H.1  00000H.0
-                  @@BITS   task_misc
-                                      FFE22H.1  00000H.0
-                  @@BITS   task_sys   FFE22H.1  00000H.0
-                  @@BITS   pedo_alg_thre_det2
-                                      FFE22H.1  00000H.1
-* gap *                               FFE23H    000B1H
-         @@SEGREG                     FFED4H    00004H  DSEG AT
-                  @@SEGREG @SEGREG    FFED4H    00004H
-         @@RTARG0                     FFED8H    00008H  DSEG AT
-                  @@RTARG0 @RTARG0    FFED8H    00008H
-
-
- Target chip : uPD79F0104
- Device file : E1.00b
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_mcu.dr
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_mcu.dr
@ -1,52 +0,0 @@
-;;; 領域の定義
-;32kB = 0x7FFF
-MEMORY BCL0:     (00000H, 01000H )
-;MEMORY BCL1:    (01000H, 01000H )          ; バックアップ領域
-MEMORY ROM :     (02000H, 03000H )
-;MEMORY ROM_BKUP:(05000H, 03000H )          ; バックアップ領域
-;MEMORY OCD :(0FC00H, 00400H )          ; OCDが使っているらしい
-
-
-;;; セグメントの割当先設定
-; ブートブロック0に割り当てる
-MERGE LDR_CODE: =BCL0
-MERGE LDR_CODL: =BCL0
-;MERGE @@LCODE : AT( 0E00H ) =BCL0       ; スタートアップルーチン
-MERGE @@LCODE : =BCL0       ; スタートアップルーチン
-
-;MERGE LDR_RINT:=BCL0
-;MERGE LDR_CNST:=BCL0
-MERGE LDR_CNSL:=BCL0
-
-
-; 通常領域にあてる物達
-MERGE ROM_CODE:=ROM
-;MERGE ROM_CNST:=ROM
-
-
-; ちょっと、困るんですが、こうしないと初期値がセットされない
-MERGE @@CNST:    =ROM
-MERGE @@R_INIT:  =ROM
-
-
-
-; 謹製フラッシュライブラリ
-; MERGE FSL_CODE:=FSL
-MERGE FSL_CODE:=BCL0
-
-
-; マジックナンバー
-;; magic.cの中で指定
-
-
-;--- RAM領域 -------------------------------------------------------
-;
-; RAM1,RAM2領域はユーザープログラムで使用しても良いですが、セルフプログラム時は
-; セルフプログラムのライブラリが使用するため、値は破壊されます。
-;
-memory RAM2     : (0FFE20H, 00C0H)     ; セルフプログラム時、使用禁止領域
-;memory SLF_RAM : (0FFE00H, 0020H)     ; Slef Program予約領域[使用禁止]
-memory RAM      : (0FF900H, 0500H)     ; ユーザーＲＡＭ領域
-;memory SLF_RAM : (0FF900H, 0020H)     ; Slef Program予約領域[使用禁止]
-
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_system.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/bsr_system.h
@ -1,56 +0,0 @@
-#ifndef __bsr_system__
-#define __bsr_system__
-
-// イベントループのステート
-enum pwr_state_
-{
-  OFF_TRIG = 0,
-  OFF,
-  ON_TRIG,
-  ON,
-  SLEEP_TRIG,
-  SLEEP,
-//  WAKE,
-  BT_CHARGE,
-};
-
-enum poweron_reason_
-{
-  NONE = 0,
-  PWSW,
-  RTC_ALARM,
-};
-
-
-enum model_
-{
-  MODEL_JIKKI = 0,
-  MODEL_TS_BOARD,
-  MODEL_SHIROBAKO,
-  MODEL_RESERVED1,
-  MODEL_RESERVED2,
-  MODEL_RESERVED3,
-};
-
-
-
-// タスクシステムの状態情報など
-typedef struct
-{
-  enum pwr_state_ pwr_state;
-  enum poweron_reason_ poweron_reason;
-  unsigned char dipsw0:1;
-  unsigned char dipsw1:1;
-  unsigned char dipsw2:1;
-  unsigned char reboot:1;
-  enum  model_ model;
-}
-system_status_;
-
-
-
-extern system_status_ system_status;
-
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/config.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/config.h
@ -1,76 +0,0 @@
-#ifndef __config__
-#define __config__
-
-#define _debug_
-//#define _debug_led_
-
-
-#define MCU_VER_MAJOR    0x00
-#define MCU_VER_MINOR    0x10
-
-#define _OVERCLOCK_
-
-//#define PM_CCIC_TIM
-
-// 古い(C)電源ボード
-//#define _PM_BUG_
-
-//#define _PARRADIUM_
-//#define _MODEL_TEG2_
-      // ↑TEG2 CPU ＋ Type-T
-//#define _MODEL_WM0_
-//#define _MODEL_WM0_TEG2_CTRC_
-
-//#define _MODEL_TS0_
-      // ↑TEG2 CPU ＋ Type-C
-
-#define _MODEL_CTR_TS_
-      // ↑FINAL SoC ＋ Type-C
-
-//#define _MODEL_CTR_JIKKI_
-
-
-//#define _SW_HOME_ENABLE_
-
-// ---------------------------------- //
-#ifdef _MODEL_CTR_TS_
-#ifdef _MODEL_CTR_JIKKI_
-どちらか一方だけセットして下さい。
-#endif
-#endif
-
-#ifdef _MODEL_CTR_TS_
-#define _MODEL_CTR_
-#endif
-
-#ifdef _MODEL_CTR_JIKKI_
-#define _MODEL_CTR_
-#endif
-
-
-// ---------------------------------- //
-#ifdef _MODEL_TEG2_
-#define _PMIC_TWL_
-#define _MCU_KE3_
-#endif
-
-
-#ifdef _MODEL_WM0_
-#define _PMIC_TWL_
-#define _MCU_BSR_
-#define _SW_HOME_ENABLE_
-#endif
-
-
-#ifdef _MODEL_TS0_
-#define _PMIC_CTR_
-#define _MCU_BSR_
-#endif
-
-#ifdef _MODEL_CTR_
-#define _PMIC_CTR_
-#define _MCU_BSR_
-#define _SW_HOME_ENABLE_
-#endif
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/fsl.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/fsl.h
@ -1,362 +0,0 @@
-/*==============================================================================================*/
-/* Project      = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash    */
-/* Module       = fsl.h                                                                         */
-/* Version      = V1.01                                                                         */
-/* Date         = 28.03.2008 11:45:42                                                           */
-/*==============================================================================================*/
-/*                                  COPYRIGHT                                                   */
-/*==============================================================================================*/
-/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH,                                         */
-/*               a company of the NEC Electronics Corporation                                   */
-/*==============================================================================================*/
-/* Purpose:                                                                                     */
-/*              constant, type and function prototype definitions used by the FSL               */
-/*                                                                                              */
-/*==============================================================================================*/
-/*                                                                                              */
-/* Warranty Disclaimer                                                                          */
-/*                                                                                              */
-/* Because the Product(s) is licensed free of charge, there is no warranty of any kind          */
-/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied,        */
-/* including but not limited to those for non-infringement of intellectual property,            */
-/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */
-/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/
-/*                                                                                              */
-/* Each User is solely responsible for determining the appropriateness of using the Product(s)  */
-/* and assumes all risks associated with its exercise of rights under this Agreement,           */
-/* including, but not limited to the risks and costs of program errors, compliance with         */
-/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or     */
-/* interruption of operations.                                                                  */
-/*                                                                                              */
-/* Limitation of Liability                                                                      */
-/*                                                                                              */
-/* In no event shall NEC be liable to the User for any incidental, consequential, indirect,     */
-/* or punitive damage (including but not limited to lost profits) regardless of whether         */
-/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */
-/* failure of essential purpose or otherwise and even if advised of the possibility of          */
-/* such damages. NEC shall not be liable for any services or products provided by third party   */
-/* vendors, developers or consultants identified or referred to the User by NEC in connection   */
-/* with the Product(s) and/or the Application.                                                  */
-/*                                                                                              */
-/*==============================================================================================*/
-/* Environment: PM plus (V6.30)                                                                 */
-/*              RA78K0(V1.20)                                                                   */
-/*              CC78K0(V2.00)                                                                   */
-/*==============================================================================================*/
-
-#ifndef __FSL_H_INCLUDED
-#define __FSL_H_INCLUDED
-
-
-/*==============================================================================================*/
-/* FSL type definitions                                                                         */
-/*==============================================================================================*/
-typedef unsigned char fsl_u08;
-typedef unsigned int fsl_u16;
-typedef unsigned long int fsl_u32;
-
-
-/*==============================================================================================*/
-/* constant definitions                                                                         */
-/*==============================================================================================*/
-
-/*status code definitions returned by the FSL functions                                         */
-#define   FSL_OK                    0x00
-#define   FSL_ERR_FLMD0             0x01
-#define   FSL_ERR_PARAMETER         0x05
-#define   FSL_ERR_PROTECTION        0x10
-#define   FSL_ERR_ERASE             0x1A
-#define   FSL_ERR_BLANKCHECK        0x1B
-#define   FSL_ERR_IVERIFY           0x1B
-#define   FSL_ERR_WRITE             0x1C
-#define   FSL_ERR_EEP_IVERIFY       0x1D
-#define   FSL_ERR_EEP_BLANKCHECK    0x1E
-#define   FSL_ERR_INTERRUPTION      0x1F
-
-
-/*==============================================================================================*/
-/* global function prototypes                                                                   */
-/*==============================================================================================*/
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      initialization of selfprogramming environment                                  */
-/*               After initialization:                                                          */
-/*               - the pointer to the data-buffer is stored                                     */
-/*               - all timing data are re-calculated according to the used system clock         */
-/*                                                                                              */
-/*               CAUTION:                                                                       */
-/*               The FSL_Init(&data_buffer) function is interruptible. Please use the           */
-/*               FSL_Init_cont(&data_buffer) to recall it as long return status is 0x1F.        */
-/*                                                                                              */
-/* Input:        data_buffer_pu08 - pointer to a data buffer of N...256 bytes                   */
-/*                                 (used for data exchange between firmware and application)    */
-/* Output:       -                                                                              */
-/* Returned:     u08, status_code                                                               */
-/*                    = 0x00(FSL_OK), normal and means initialization OK                        */
-/*                    = 0x1F(FSL_ERR_INTERRUPTION), initialization interrupted by user interrupt*/
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_Init( fsl_u08 * data_buffer_pu08 );
-extern fsl_u08 FSL_Init_cont( fsl_u08 * data_buffer_pu08 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      checks the voltage level (high or low) at FLMD0 pin                            */
-/* Input:        -                                                                              */
-/* Output:       -                                                                              */
-/* Returned:     fsl_u08, status_code                                                           */
-/*                    = 0x00(FSL_OK), normal and means FLMD0=HIGH                               */
-/*                    = 0x01(FSL_ERR_FLMD0), error, FLMD0=LOW                                   */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_ModeCheck( void );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      checks if specified block is blank                                             */
-/* Input:        block_u16 - block number has to be checked                                     */
-/* Output:       -                                                                              */
-/* Returned:     fsl_u08, status_code                                                           */
-/*                    = 0x00(FSL_OK), normal and means "block is blank"                         */
-/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
-/*                    = 0x1B(FSL_ERR_BLANKCHECK), blank-check error, means "block not blank"    */
-/*                    = 0x1F(FSL_ERR_INTERRUPTION), blank-check interrupted by user interrupt   */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_BlankCheck( fsl_u16 block_u16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/*  Block type:   FSL command function                                                          */
-/*----------------------------------------------------------------------------------------------*/
-/*  Purpose:      erase specified block                                                         */
-/*  Input:        block_u16 - block number has to be erase                                      */
-/*  Output:       -                                                                             */
-/*  Returned:     fsl_u08, status_code                                                          */
-/*                     = 0x00(FSL_OK), normal and means "block erased successfully"             */
-/*                     = 0x05(FSL_ERR_PARAMETER), parameter error                               */
-/*                     = 0x10(FSL_ERR_PROTECTION), tried to erase protected area                */
-/*                     = 0x1A(FSL_ERR_ERASE), erase error, retry up to max. 255 times           */
-/*                     = 0x1F(FSL_ERR_INTERRUPTION), erasing interrupted by user interrupt      */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_Erase( fsl_u16 block_u16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      performs internal verify on specified block                                    */
-/* Input:        block_u16 - block number has to be verified                                    */
-/* Output:       -                                                                              */
-/* Returned:     fsl_u08, status_code                                                           */
-/*                    = 0x00(FSL_OK), normal and means "block is verified"                      */
-/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
-/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
-/*                    = 0x1F(FSL_ERR_INTERRUPTION), verify interrupted by user interrupt        */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_IVerify( fsl_u16 block_u16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      writes N words from the data buffer into flash                                 */
-/* Input:        s_address_u32 - starting flash address the data has to be written              */
-/*                               See Condition  2) please.                                      */
-/*               my_wordcount_u08  - number of words (4 bytes) has to be written                */
-/* Output:       -                                                                              */
-/* Condition:   1) (s_address_u32 MOD 4 == 0)                                                   */
-/*              2) most significant byte (MSB) of  s_address_u32 has to be 0x00.                */
-/*                 Means: 0x00abcdef 24 bit flash address allowed                               */
-/*              3) (word_count_u08 <= sizeof(data buffer))  NOT CHECKED BY LIBRARY  !!!!!       */
-/* Changed:     -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                   = 0x00(FSL_OK), normal                                                     */
-/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
-/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
-/*                   = 0x1C(FSL_ERR_WRITE), write error                                         */
-/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_Write( fsl_u32 s_address_u32, fsl_u08 word_count_u08 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      writes N words from the data buffer into flash                                 */
-/*               Before "writing" a N-word blankcheck is performed.                             */
-/*               After "writing" a N-Word internal verify is performed.                         */
-/* Input:        s_address_u32 - starting destination address has to be written                 */
-/*               my_wordcount_u08  - number of words (4 bytes) has to be written                */
-/* Output:       -                                                                              */
-/* Condition:   1) (s_address_u32 MOD 4 == 0)                                                   */
-/*              2) (word_count_u08 <= sizeof(data buffer))  NOT CHECKED BY FIRMWARE !!!!!       */
-/* Changed:     -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                   = 0x00(FSL_OK), normal                                                     */
-/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
-/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
-/*                   = 0x1C(FSL_ERR_WRITE), write error                                         */
-/*                   = 0x1D(FSL_ERR_EEP_IVERIFY), verify error                                  */
-/*                   = 0x1E(FSL_ERR_EEP_BLANKCHECK), blankcheck error                           */
-/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_EEPROMWrite( fsl_u32 s_address_u32,
-                                fsl_u08 word_count_u08 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      reads the security information                                                 */
-/* Input:        destination_pu16 - destination address of the security info                    */
-/*               The format of the security info is: "unsigned short int"                       */
-/*                                                                                              */
-/*               Format of the security info:                                                   */
-/*               bit_0 = 0 -> chip erase command disabled, otherwise enabled                    */
-/*               bit_1 = 0 -> block erase command disabled, otherwise enabled                   */
-/*               bit_2 = 0 -> write command disabled, otherwise enabled                         */
-/*               bit_4 = 0 -> boot-area re-programming disabled, otherwise enabled              */
-/*               bit_8...bit_15 = 03H -> last block of the boot-area                            */
-/*               other bits = 1                                                                 */
-/* Output:       -                                                                              */
-/* Changed:      content of the data_buffer                                                     */
-/* Returned:     fsl_u08, status code                                                           */
-/*                  = 0x00(FSL_OK), normal                                                      */
-/*                  = 0x05(FSL_ERR_PARAMETER), parameter error                                  */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_GetSecurityFlags( fsl_u16 * destination_pu16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      read the boot flag i                                                           */
-/* Input:        destination_pu08 - destination address of the bootflag info                    */
-/*               The format of the boot-flag info is: "unsigned char"                           */
-/*               The value of the boot info is 0x00 for cluster 0 and 0x01 for cluster 1.       */
-/* Output:       -                                                                              */
-/* Changed:      content of the data_buffer                                                     */
-/* Returned:     fsl_u08, status code                                                           */
-/*                  = 0x00(FSL_OK), normal                                                      */
-/*                  = 0x05(FSL_ERR_PARAMETER), parameter error                                  */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_GetActiveBootCluster( fsl_u08 * destination_pu08 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:     puts the last address of the specified block into *destination_pu32             */
-/* Input:       *destination_pu32 - destination where the last-block-address                    */
-/*                                  should be stored                                            */
-/*              block_u16         - block number of the last address is needed                  */
-/* Changed:     -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                   = 0x00(FSL_OK), normal                                                     */
-/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_GetBlockEndAddr( fsl_u32 * destination_pu32,
-                                    fsl_u16 block_u16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:     puts the information about the protected flash area into the function parameter */
-/* Input:       *start_block_pu16 - destination where the FSW start block should be stored      */
-/*              *end_block_pu16   - destination where the FSW end block should be stored        */
-/* Changed:     -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                   = 0x00(FSL_OK), normal                                                     */
-/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_GetFlashShieldWindow( fsl_u16 * start_block_pu16,
-                                         fsl_u16 * end_block_pu16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:     defines a new Flash-Shield-Window area inside the flash memory                  */
-/* Input:       start_block_u16 - starting block of the Flash-Shield-Window (FSW)               */
-/*              end_block_u16   - ending block of the flash-Shield-Window (FSW)                 */
-/* Changed:     -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                    = 0x00(FSL_OK), normal                                                    */
-/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
-/*                    = 0x10(FSL_ERR_PROTECTION), protection error                              */
-/*                    = 0x1A(FSL_ERR_ERASE), erase error                                        */
-/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
-/*                    = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt         */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_SetFlashShieldWindow( fsl_u16 start_block_u16,
-                                         fsl_u16 end_block_u16 );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:     Swapping of bootcluster 0 and 1                                                 */
-/*                                                                                              */
-/*              CAUTION !!!!                                                                    */
-/*              After this function the boot cluster are immediately swapped                    */
-/* Input:       -                                                                               */
-/* Output:      -                                                                               */
-/* Returned:    fsl_u08, status code                                                            */
-/*                   = 0x00(FSL_OK), normal                                                     */
-/*                   = 0x05(FSL_ERR_PARAMETER), parameter error                                 */
-/*                   = 0x10(FSL_ERR_PROTECTION), protection error                               */
-/*                   = 0x1A(FSL_ERR_ERASE), erase error                                         */
-/*                   = 0x1B(FSL_ERR_IVERIFY), internal verify error                             */
-/*                   = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt          */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_SwapBootCluster( void );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL command function                                                           */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:      sets specified security flag by dedicated command-function.                    */
-/*                                                                                              */
-/*               There are following security levels:                                           */
-/*               a) chip-erase protection   (cannot be reset by programmer !!!)                 */
-/*               b) block-erase protection  (can be reset by chip-erase on programmer)          */
-/*               c) write protection        (can be reset by chip-erase on programmer)          */
-/*               d) boot-cluster protection (cannot be reset by programmer !!!)                 */
-/*                                                                                              */
-/*               CAUTION !!!!                                                                   */
-/*               Each security flag can be written by the application only once                 */
-/*                                                                                              */
-/* Input:        -                                                                              */
-/* Output:       -                                                                              */
-/* Returned:     fsl_u08, status code                                                           */
-/*                    = 0x00(FSL_OK), normal                                                    */
-/*                    = 0x05(FSL_ERR_PARAMETER), parameter error                                */
-/*                    = 0x10(FSL_ERR_PROTECTION), protection error                              */
-/*                    = 0x1A(FSL_ERR_ERASE), erase error                                        */
-/*                    = 0x1B(FSL_ERR_IVERIFY), internal verify error                            */
-/*                    = 0x1F(FSL_ERR_INTERRUPTION), write interrupted by user interrupt         */
-/*----------------------------------------------------------------------------------------------*/
-extern fsl_u08 FSL_SetChipEraseProtectFlag( void );
-extern fsl_u08 FSL_SetBlockEraseProtectFlag( void );
-extern fsl_u08 FSL_SetWriteProtectFlag( void );
-extern fsl_u08 FSL_SetBootClusterProtectFlag( void );
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* Block type:   FSL function                                                                   */
-/*----------------------------------------------------------------------------------------------*/
-/* Purpose:     defines the firmware operation method after interrupt service (ISR) execution.  */
-/* Input:       mode_u08 = 0x00,  after RETI the firmware is continuing the interrupted command.*/
-/*                       = other, after RETI the firmware is interrupted with status 0x1F.      */
-/* Changed:     -                                                                               */
-/* Returned:    -                                                                               */
-/*----------------------------------------------------------------------------------------------*/
-extern void FSL_SetInterruptMode( fsl_u08 mode_u08 );
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/fsl_user.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/fsl_user.h
@ -1,108 +0,0 @@
-/*==============================================================================================*/
-/* Project      = Selfprogramming library for 78K0R/Ix3/Kx3-L Single Voltage SST (MF2) Flash    */
-/* Module       = fsl_user.h                                                                    */
-/* Version      = V1.01                                                                         */
-/* Date         = 28.03.2008 11:45:55                                                           */
-/*==============================================================================================*/
-/*                                  COPYRIGHT                                                   */
-/*==============================================================================================*/
-/* Copyright (c) 2007 by NEC Electronics (Europe) GmbH,                                         */
-/*               a company of the NEC Electronics Corporation                                   */
-/*==============================================================================================*/
-/* Purpose:                                                                                     */
-/*              user configurable constant/macros of the selfprogramming library                */
-/*                                                                                              */
-/*==============================================================================================*/
-/*                                                                                              */
-/* Warranty Disclaimer                                                                          */
-/*                                                                                              */
-/* Because the Product(s) is licensed free of charge, there is no warranty of any kind          */
-/* whatsoever and expressly disclaimed and excluded by NEC, either expressed or implied,        */
-/* including but not limited to those for non-infringement of intellectual property,            */
-/* merchantability and/or fitness for the particular purpose. NEC shall not have any obligation */
-/* to maintain, service or provide bug fixes for the supplied Product(s) and/or the Application.*/
-/*                                                                                              */
-/* Each User is solely responsible for determining the appropriateness of using the Product(s)  */
-/* and assumes all risks associated with its exercise of rights under this Agreement,           */
-/* including, but not limited to the risks and costs of program errors, compliance with         */
-/* applicable laws, damage to or loss of data, programs or equipment, and unavailability or     */
-/* interruption of operations.                                                                  */
-/*                                                                                              */
-/* Limitation of Liability                                                                      */
-/*                                                                                              */
-/* In no event shall NEC be liable to the User for any incidental, consequential, indirect,     */
-/* or punitive damage (including but not limited to lost profits) regardless of whether         */
-/* such liability is based on breach of contract, tort, strict liability, breach of warranties, */
-/* failure of essential purpose or otherwise and even if advised of the possibility of          */
-/* such damages. NEC shall not be liable for any services or products provided by third party   */
-/* vendors, developers or consultants identified or referred to the User by NEC in connection   */
-/* with the Product(s) and/or the Application.                                                  */
-/*                                                                                              */
-/*==============================================================================================*/
-/* Environment: PM plus (V6.30)                                                                 */
-/*              RA78K0(V1.20)                                                                   */
-/*              CC78K0(V2.00)                                                                   */
-/*==============================================================================================*/
-
-
-#ifndef __FSL_USER_H_INCLUDED
-#define __FSL_USER_H_INCLUDED
-
-
-/*==============================================================================================*/
-/* constant definitions                                                                         */
-/*==============================================================================================*/
-
-
-/* specify the CPU frequency in [Hz], only 2MHz....20MHz allowed  */
-#define   FSL_SYSTEM_FREQUENCY      4000000
-
-/* define whether low-voltage mode is used or not                 */
-/* #define   FSL_LOW_VOLTAGE_MODE                                 */
-
-/* size of the common data buffer expressed in [bytes]                                          */
-/* the data buffer is used for data-exchange between the firmware and the selflib.              */
-//#define   FSL_DATA_BUFFER_SIZE    256
-#define   FSL_DATA_BUFFER_SIZE    0
-
-
-/* customizable interrupt controller configuration during selfprogramming period                */
-/* Bit     --7-------6-------5-------4-------3-------2-------1-------0----------------------    */
-/* MK0L:     PMK5    PMK4    PMK3    PMK2    PMK1    PMK0    LVIMK   WDTIMK                     */
-/* MK0H:     SREMK0  SRMK0*  STMK0*  DMAMK1  DMAMK0  SREMK3  SRMK3   STMK3                      */
-/* MK1L:     TMMK03  TMMK02  TMMK01  TMMK00  IICMK0  SREMK1  SRMK1   STMK1*                     */
-/* MK1H:     TMMK04  SREMK2  SRMK2   STMK2*  KRMK    RTCIMK  RTCMK   ADMK                       */
-/* MK2L:     PMK10   PMK9    PMK8    PMK7    PMK6    TMMK07  TMMK06  TMMK05                     */
-/* MK2H:     1       1       1       1       1       1       1       PMK11                      */
-/*------------------------------------------------------------------------------------------    */
-/*                                                                                              */
-/* Examples:                                                                                    */
-/* =========                                                                                    */
-/*#define   FSL_MK0L_MASK   0xF7   -> allow INTP1 interrupt during selfprogramming              */
-/*#define   FSL_MK0H_MASK   0xEF   -> allow DMA1 interrupt during selfprogramming               */
-/*#define   FSL_MK1L_MASK   0xBF   -> allow TM02 interrupt during selfprogramming               */
-/*#define   FSL_MK1H_MASK   0xFF   -> all interrupts disabled during selfprogramming            */
-/*#define   FSL_MK2L_MASK   0xF7   -> allow INTP6 interrupt during selfprogramming              */
-/*#define   FSL_MK2H_MASK   0xFF   -> all interrupts disabled during selfprogramming            */
-/*------------------------------------------------------------------------------------------    */
-#define   FSL_MK0L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-#define   FSL_MK0H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-#define   FSL_MK1L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-#define   FSL_MK1H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-#define   FSL_MK2L_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-#define   FSL_MK2H_MASK   0xFF  /* all interrupts disabled during selfprogramming              */
-
-
-/* FLMD0 control bit                        */
-#define  FSL_FLMD0_HIGH   {BECTL.7 = 1;}
-#define  FSL_FLMD0_LOW    {BECTL.7 = 0;}
-
-
-/*----------------------------------------------------------------------------------------------*/
-/* switch interrupt backu functionality ON/OFF using #define/#undef                             */
-/*----------------------------------------------------------------------------------------------*/
-/* #define  FSL_INT_BACKUP */
-#undef  FSL_INT_BACKUP
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.1_090819.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.1_090819.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.2_090901.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.2_090901.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.3_090915.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0.3_090915.hex
@ -1,568 +0,0 @@
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--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0R1_090819.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0R1_090819.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0R2_090828_WM2.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_V0R2_090828_WM2.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_k0R_V0.5.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/bsr_k0R_V0.5.hex
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-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/k0r_V0.1_090819.hex
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hex/k0r_V0.1_090819.hex
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TEG2.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TEG2.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TEG2CTRC.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TEG2CTRC.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TS.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10.TS.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10_T3.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10_T3.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10_T3_CodecRevA.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.0_10_T3_CodecRevA.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.bin
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/hoge.bin
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.c
@ -1,261 +0,0 @@
-/* ========================================================
-  対SoC 新規チャンネル I2C通信
-    藤田＠開技.nintendo
-	'09 Apr
- ======================================================== */
-#include "incs.h"
-#include "accero.h"
-
-#ifdef _MCU_BSR_
-// #ifdef _MODEL_TS0_ || _MODEL_WM0_
-
-// ワーキングモデルはI2Cが逆
-// TEGは回路図でテレコ
-#define ACKD       ACKD1
-#define ACKE       ACKE1
-#define COI        COI1
-#define IICAEN     IICA1EN
-#define IICRSV     IICRSV1
-#define IICA       IICA1
-#define IICAIF     IICAIF1
-#define IICAMK     IICAMK1
-#define IICAPR0    IICAPR11
-#define IICAPR1    IICAPR01
-#define IICCTL0    IICCTL10
-#define IICE       IICE1
-#define IICF       IICF1
-#define IICS       IICS1
-#define IICWH      IICWH1
-#define IICWL      IICWL1
-#define LREL       LREL1
-#define SPD        SPD1
-#define SPIE       SPIE1
-#define STCEN      STCEN1
-#define STD        STD1
-#define SVA        SVA1
-#define WREL       WREL1
-#define WTIM       WTIM1
-#define TRC        TRC1
-#define SMC        SMC1
-#define DFC        DFC1
-
-
-#endif
-
-// ==============================================
-extern bit irq_readed;                 // いずれかのIRQレジスタが読まれた
-
-u8 iic_burst_state;
-
-
-/* ========================================================
- ======================================================== */
-enum
-{
-    IIC_IDLE = 0,
-    IIC_RCV_REG_ADRS,
-    IIC_TX_OR_RX,
-    IIC_TX,
-    IIC_RX
-};
-
-
-// 1バイト送受の度に割り込みが発生するバージョン
-__interrupt void int_iic_ctr(  )
-{
-    static u8 state = IIC_IDLE;
-    static u8 reg_adrs;
-    static u8 reg_adrs_internal;
-    static u8 tx_buf;
-    u8 rx_buf;
-
-    EI();
-
-    // 読み出し終了
-    if( !ACKD )                 // 割り込み要因はNAK（データ送信の最後）
-    {
-        state = IIC_IDLE;
-        SPIE = 0;
-        LREL = 1;
-
-        // レジスタリードで、割り込みピンをネゲート
-        // まだ読まれてない割り込みがあれば、再度アサート
-        if( irq_readed )
-        {
-            IRQ0_neg;
-            irq_readed = 0;
-            if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 )
-                   && ( vreg_ctr[VREG_C_IRQ1] == 0 )
-                   && ( vreg_ctr[VREG_C_IRQ2] == 0 )
-                   && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) )
-            {
-                while( !IRQ0 ){;}  // 時間稼ぎ不要かも
-                IRQ0_ast;
-            }
-        }
-
-        // 歩数計読み出し終了
-        hosu_read_end(  );
-        rtc_unlock(  );
-        iic_burst_state = 0;
-        return;
-    }
-
-    if( SPD )                   // 割り込み要因はストップコンディション
-                                // 通信の最後。↑の !ACKD に来たときは割り込み来ない (SPIE = 0 のため )
-    {
-        state = IIC_IDLE;
-        SPIE = 0;
-        // I2C終了時に何かする物 //
-        rtc_unlock(  );
-        return;
-    }
-
-    if( STD )                   // 割り込み要因：スタートコンディション
-    {
-        if( ( state == IIC_TX ) || ( state == IIC_RX )
-            || ( state == IIC_RCV_REG_ADRS )
-            )
-        {
-            state = IIC_IDLE;
-            // no break //
-        }
-    }
-
-    switch ( state )
-    {
-    case ( IIC_IDLE ):
-        // 自局呼び出しに応答。
-        // 初期化など
-        SPIE = 1;
-        state = IIC_RCV_REG_ADRS;
-        WREL = 1;               // ウェイト解除
-        break;
-
-    case ( IIC_RCV_REG_ADRS ):  // ２バイト目（レジスタアドレス）受信後に来る
-        // レジスタアドレス受信
-        reg_adrs = IICA;
-        tx_buf = vreg_ctr_read( reg_adrs );    // データの準備をしておく
-        if( reg_adrs != VREG_C_INFO )
-        {
-            state = IIC_TX_OR_RX;
-        }
-        else
-        {
-            state = IIC_IDLE;
-        }
-        WREL = 1;
-        break;
-
-    case ( IIC_TX_OR_RX ):      // ↑の次に来る割り込み。STなら送信準備、データが来たら書き込まれ
-//    if( TRC ){           // 送信方向フラグ で区別するのは、割り込み遅延時に不具合が起こりえる
-        if( STD )
-        {                       // スタートコンディション検出フラグ
-            // リードされる
-            if( COI )
-            {                   // アドレス一致フラグ
-                state = IIC_TX;
-                // no break, no return //
-            }
-            else
-            {
-                // リスタートで違うデバイスが呼ばれた！
-                state = IIC_IDLE;       // 終了処理
-                SPIE = 0;
-                LREL = 1;       // ウェイト解除?
-                return;
-            }
-        }
-        else
-        {
-            state = IIC_RX;     // データ1バイト受信の割り込みだった
-            // no break, no return //
-        }
-
-    default:                    // バースト R/W でここが何回も呼ばれることになる
-        if( state == IIC_TX )
-        {                       // 送信
-            IICA = tx_buf;
-            vreg_ctr_after_read( reg_adrs );    // 読んだらクリアなどの処理
-        }
-        else
-        {                   // 受信
-            rx_buf = IICA;
-            vreg_ctr_write( reg_adrs, rx_buf );
-            WREL = 1;
-        }
-        // 
-        if( ( reg_adrs != VREG_C_ACC_HOSU_HIST )
-            && ( reg_adrs != VREG_C_INFO ) )
-        {   // この二つのレジスタは特殊なアクセス方法をする。アクセスポインタを進めない。
-            reg_adrs += 1;
-        }
-
-        if( state == IIC_TX )
-        {                       // さらにつぎに送るデータの準備だけシテオク。SPが来て使われないかもしれない
-            tx_buf = vreg_ctr_read( reg_adrs );
-        }
-        break;
-    }
-}
-
-
-
-// ========================================================
-void IIC_ctr_Init( void )
-{
-
-    IICAEN = 1;
-
-    IICE = 0;                   /* IICA disable */
-
-    IICAMK = 1;                 /* INTIICA disable */
-    IICAIF = 0;                 /* clear INTIICA interrupt flag */
-
-    IICAPR0 = 1;                /* set INTIICA high priority */
-    IICAPR1 = 0;                /* set INTIICA high priority */
-
-#ifdef _MODEL_TEG2_
-    P6 &= ~0x3;
-#else
-    P20 &= ~0x3;
-#endif
-
-    SVA = IIC_C_SLAVEADDRESS;
-    IICF = 0x01;
-
-    STCEN = 1;                  // リスタートの許可
-    IICRSV = 1;                 // 通信予約をさせない:スレーブに徹する
-
-    SPIE = 0;                   // ストップコンディションでの割り込みを禁止
-    WTIM = 1;                   // 自動でACKを返した後clkをLに固定する
-    ACKE = 1;                   //  ダメCPUは無視して次の通信をはじめるかもしれないんで早くclkを開放しないといけない
-
-    IICWH = 5;
-    IICWL = 10;                 // L期間の長さ
-
-    SMC = 1;                    // 高速モード
-    DFC = 1;                    // デジタルフィルタon (@fast mode)
-
-    IICAMK = 0;                 // 割り込みを許可
-
-    IICE = 1;
-
-#ifdef _MODEL_TEG2_
-    PM6 &= ~0x3;                /* set clock pin for IICA */
-#else
-    PM20 &= ~0x3;                /* set clock pin for IICA */
-#endif
-}
-
-
-
-// ========================================================
-void IIC_ctr_Stop( void )
-{
-    IICE = 0;                   /* IICA disable */
-    IICAEN = 0;
-}
-
-
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.h
@ -1,210 +0,0 @@
-#ifndef _MDSERIAL_A_
-#define _MDSERIAL_A_
-
-
-/* IIC operation enable	(IICE0)	*/
-#define	IIC0_OPERATION				0x80
-#define	IIC0_OPERATION_DISABLE		0x00    /* stop operation */
-#define	IIC0_OPERATION_ENABLE		0x80    /* enable operation     */
-
-/* Exit	from communications	(LREL0)	*/
-#define	IIC0_COMMUNICATION			0x40
-#define	IIC0_COMMUNICATION_NORMAL	0x00    /* normal operation     */
-#define	IIC0_COMMUNICATION_EXIT		0x40    /* exit from current communication */
-
-/* Wait	cancellation (WREL0) */
-#define	IIC0_WAITCANCEL				0x20
-#define	IIC0_WAIT_NOTCANCEL			0x00    /* do not cancel wait */
-#define	IIC0_WAIT_CANCEL			0x20    /* cancel wait */
-
-/* Generation of interrupt when	stop condition (SPIE0) */
-#define	IIC0_STOPINT				0x10
-#define	IIC0_STOPINT_DISABLE		0x00    /* disable */
-#define	IIC0_STOPINT_ENABLE			0x10    /* enable */
-
-/* Wait	and	interrupt generation (WTIM0) */
-#define	IIC0_WAITINT				0x08
-#define	IIC0_WAITINT_CLK8FALLING	0x00    /* generate     at the eighth clocks falling edge       */
-#define	IIC0_WAITINT_CLK9FALLING	0x08    /* generated at the     ninth clocks falling edge       */
-
-/* Acknowledgement control (ACKE0) */
-#define	IIC0_ACK					0x04
-#define	IIC0_ACK_DISABLE			0x00    /* enable acknowledgement */
-#define	IIC0_ACK_ENABLE				0x04    /* disable acknowledgement */
-
-/* Start condition trigger (STT0) */
-#define	IIC0_STARTCONDITION			0x02
-#define	IIC0_START_NOTGENERATE		0x00    /* do not generate start condition */
-#define	IIC0_START_GENERATE			0x02    /* generate     start condition */
-
-/* Stop	condition trigger (SPT0) */
-#define	IIC0_STOPCONDITION			0x01
-#define	IIC0_STOP_NOTGENERATE		0x00    /* do not generate stop condition */
-#define	IIC0_STOP_GENERATE			0x01    /* generate     stop condition */
-
-/*
-	IIC	Status Register	0 (IICS0)
-*/
-/* Master device status	(MSTS0)	*/
-#define	IIC0_MASTERSTATUS			0x80
-#define	IIC0_STATUS_NOTMASTER		0x00    /* slave device status or communication standby status */
-#define	IIC0_STATUS_MASTER			0x80    /* master device communication status */
-
-/* Detection of	arbitration	loss (ALD0)	*/
-#define	IIC0_ARBITRATION			0x40
-#define	IIC0_ARBITRATION_NO			0x00    /* arbitration win or no arbitration */
-#define	IIC0_ARBITRATION_LOSS		0x40    /* arbitration loss     */
-
-/* Detection of	extension code reception (EXC0)	*/
-#define	IIC0_EXTENSIONCODE			0x20
-#define	IIC0_EXTCODE_NOT			0x00    /* extension code not received */
-#define	IIC0_EXTCODE_RECEIVED		0x20    /* extension code received */
-
-/* Detection of	matching addresses (COI0) */
-#define	IIC0_ADDRESSMATCH			0x10
-#define	IIC0_ADDRESS_NOTMATCH		0x00    /* addresses do not     match */
-#define	IIC0_ADDRESS_MATCH			0x10    /* addresses match */
-
-/* Detection of	transmit/receive status	(TRC0) */
-#define	IIC0_STATUS					0x08
-#define	IIC0_STATUS_RECEIVE			0x00    /* receive status */
-#define	IIC0_STATUS_TRANSMIT		0x08    /* transmit     status */
-
-/* Detection of	acknowledge	signal (ACKD0) */
-#define	IIC0_ACKDETECTION			0x04
-#define	IIC0_ACK_NOTDETECTED		0x00    /* ACK signal was not detected */
-#define	IIC0_ACK_DETECTED			0x04    /* ACK signal was detected */
-
-/* Detection of	start condition	(STD0) */
-#define	IIC0_STARTDETECTION			0x02
-#define	IIC0_START_NOTDETECTED		0x00    /* start condition not detected */
-#define	IIC0_START_DETECTED			0x02    /* start condition detected     */
-
-/* Detection of	stop condition (SPD0) */
-#define	IIC0_STOPDETECTION			0x01
-#define	IIC0_STOP_NOTDETECTED		0x00    /* stop condition not detected */
-#define	IIC0_STOP_DETECTED			0x01    /* stop condition detected */
-
-/*
-	IIC	Flag Register 0	(IICF0)
-*/
-/* STT0	clear flag (STCF) */
-#define	IIC0_STARTFLAG				0x80
-#define	IIC0_STARTFLAG_GENERATE		0x00    /* generate     start condition */
-#define	IIC0_STARTFLAG_UNSUCCESSFUL	0x80    /* start condition generation unsuccessful */
-
-/* IIC bus status flag (IICBSY)	*/
-#define	IIC0_BUSSTATUS				0x40
-#define	IIC0_BUS_RELEASE			0x00    /* bus release status */
-#define	IIC0_BUS_COMMUNICATION		0x40    /* bus communication status     */
-
-/* Initial start enable	trigger	(STCEN)	*/
-#define	IIC0_STARTWITHSTOP			0x02
-#define	IIC0_START_WITHSTOP			0x00    /* generation of a start condition without detecting a stop     condition */
-#define	IIC0_START_WITHOUTSTOP		0x02    /* generation of a start condition upon detection of a stop     condition */
-
-/* Communication reservation function disable bit (IICRSV) */
-#define	IIC0_RESERVATION			0x01
-#define	IIC0_RESERVATION_ENABLE		0x00    /* enable communication reservation     */
-#define	IIC0_RESERVATION_DISABLE	0x01    /* disable communication reservation */
-
-/*
-	IIC	clock selection	register 0 (IICCL0)
-*/
-#define IICCL0_INITIALVALUE   		0x00
-/* Detection of	SCL0 pin level (CLD0) */
-#define	IIC0_SCLLEVEL				0x20
-#define	IIC0_SCL_LOW				0x00    /* clock line at low level */
-#define	IIC0_SCL_HIGH				0x20    /* clock line at high level     */
-
-/* Detection of	SDA0 pin level (DAD0) */
-#define	IIC0_SDALEVEL				0x10
-#define	IIC0_SDA_LOW				0x00    /* data line at low     level */
-#define	IIC0_SDA_HIGH				0x10    /* data line at high level */
-
-/* Operation mode switching	(SMC0) */
-#define	IIC0_OPERATIONMODE			0x08
-#define	IIC0_MODE_STANDARD			0x00    /* operates     in standard     mode */
-#define	IIC0_MODE_HIGHSPEED			0x08    /* operates     in high-speed mode */
-
-/* Digital filter operation	control	(DFC0) */
-#define	IIC0_DIGITALFILTER			0x04
-#define	IIC0_FILTER_OFF				0x00    /* digital filter off */
-#define	IIC0_FILTER_ON				0x04    /* digital filter on */
-
-/* Operation mode switching	(CL01, CL00) */
-#define	IIC0_CLOCKSELECTION			0x03
-
-/*	Combine	of (SMC0, CL01,	CL00)*/
-#define	IIC0_CLOCK0					0x00
-#define	IIC0_CLOCK1					0x01
-#define	IIC0_CLOCK2					0x02
-#define	IIC0_CLOCK3					0x03
-#define	IIC0_CLOCK4					0x08
-#define	IIC0_CLOCK5					0x09
-#define	IIC0_CLOCK6					0x0a
-#define	IIC0_CLOCK7					0x0b
-
-/*
-	IIC	function expansion register	0 (IICX0)
-*/
-/* IIC clock expension (CLX0) */
-#define	IIC0_CLOCKEXPENSION			0x01
-#define	IIC0_EXPENSION0				0x00
-#define	IIC0_EXPENSION1				0x01
-
-/*  Operation clock (CLX0, SMC0, CL01, CL00)
-            |   IIC0_EXPENSION0 |   IIC0_EXPENSION1 |                                
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK0 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/88     |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK1 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/172    |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK2 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/344    |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK3 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
-            |       fw/66       |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK4 |       fprs/2      |       fprs/2      |   selection clock(fw)
-            |       fprs/48     |       fprs/24     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------            
-IIC0_CLOCK5 |       fprs/2      |       fprs/2      |   selection clock(fw)
-            |       fprs/48     |       fprs/24     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK6 |       fprs/4      |       fprs/4      |   selection clock(fw)
-            |       fprs/96     |       fprs/48     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK7 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
-            |       fw/18       |                   |   transfer clock
-            |     high speed    |                   |   mode
------------|-------------------|-------------------|----------------------
-*/
-
-#define ADDRESS_COMPLETE   			0x80
-#define IIC_MASTER_FLAG_CLEAR 		0x00
-
-/******************************************************************************
- *  Macro define
- ******************************************************************************/
-
-
-
-/******************************************************************************
- *  Function define
- ******************************************************************************/
-
-void IIC_ctr_Init( void );
-void IIC_ctr_Stop( void );
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.prn
@ -1,963 +0,0 @@
-
-
-
-78K0R Assembler W1.31                                                                                    Date:13 Jun 2010 Page:   1
-
-
-
-Command:  -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\i2c_ctr.asm
-Para-file:
-In-file:  inter_asm\i2c_ctr.asm
-Obj-file: i2c_ctr.rel
-Prn-file: i2c_ctr.prn
-
-      Assemble list
-
- ALNO  STNO ADRS   OBJECT   M I  SOURCE STATEMENT
-
-    1     1                      ; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-    2     2                      
-    3     3                      ; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-    4     4                      ;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-    5     5                      ;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c
-    6     6                      ; In-file   : i2c_ctr.c
-    7     7                      ; Asm-file  : inter_asm\i2c_ctr.asm
-    8     8                      ; Para-file : 
-    9     9                      
-   10    10                      $PROCESSOR(9F0104)
-   11    11                      $DEBUG
-   12    12                      $NODEBUGA
-   13    13                      $KANJICODE SJIS
-   14    14                      $TOL_INF        03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-   15    15                      
-   16    16                      $DGS    FIL_NAM, .file,         07CH,   0FFFEH, 03FH,   067H,   01H,    00H
-   17    17                      $DGS    AUX_FIL, i2c_ctr.c
-   18    18                      $DGS    MOD_NAM, i2c_ctr,       00H,    0FFFEH, 00H,    077H,   00H,    00H
-   19    19                      $DGS    SEC_NAM, @@BITS,        U,      U,      00H,    078H,   00H,    00H
-   20    20                      $DGS    SEC_NAM, @@CNST,        U,      U,      00H,    078H,   00H,    00H
-   21    21                      $DGS    SEC_NAM, @@R_INIT,      U,      U,      00H,    078H,   00H,    00H
-   22    22                      $DGS    SEC_NAM, @@INIT,        U,      U,      00H,    078H,   00H,    00H
-   23    23                      $DGS    SEC_NAM, @@DATA,        U,      U,      00H,    078H,   00H,    00H
-   24    24                      $DGS    SEC_NAM, @@R_INIS,      U,      U,      00H,    078H,   00H,    00H
-   25    25                      $DGS    SEC_NAM, @@INIS,        U,      U,      00H,    078H,   00H,    00H
-   26    26                      $DGS    SEC_NAM, @@DATS,        U,      U,      00H,    078H,   00H,    00H
-   27    27                      $DGS    SEC_NAM, @@CNSTL,       U,      U,      00H,    078H,   00H,    00H
-   28    28                      $DGS    SEC_NAM, @@RLINIT,      U,      U,      00H,    078H,   00H,    00H
-   29    29                      $DGS    SEC_NAM, @@INITL,       U,      U,      00H,    078H,   00H,    00H
-   30    30                      $DGS    SEC_NAM, @@DATAL,       U,      U,      00H,    078H,   00H,    00H
-   31    31                      $DGS    SEC_NAM, @@CALT,        U,      U,      00H,    078H,   00H,    00H
-   32    32                      $DGS    SEC_NAM, ROM_CODE,      U,      U,      00H,    078H,   00H,    00H
-   33    33                      $DGS    SEC_NAM, @@CODEL,       U,      U,      00H,    078H,   00H,    00H
-   34    34                      $DGS    SEC_NAM, @@BASE,        U,      U,      00H,    078H,   00H,    00H
-   35    35                      $DGS    STA_SYM, _lpf_coeff,    U,      U,      05002H, 03H,    01H,    03H
-   36    36                      $DGS    AUX_STR, 00H,           00H,    02FH,   02FH,   00H,    00H,    00H,    00H
-   37    37                      $DGS    GLV_SYM, _int_iic_ctr,  U,      U,      0E001H, 026H,   01H,    02H
-   38    38                      $DGS    AUX_FUN, 00H,           U,      U,      070H,   00H,    00H
-   39    39                      $DGS    BEG_FUN, ??bf_int_iic_ctr,      U,      U,      00H,    065H,   01H,    00H
-   40    40                      $DGS    AUX_BEG, 041H,          016H,   01EH
-   41    41                      $DGS    STA_SYM, _state,        ?L0003, U,      0CH,    03H,    00H,    00H
-   42    42                      $DGS    STA_SYM, _reg_adrs,     ?L0004, U,      0CH,    03H,    00H,    00H
-   43    43                      $DGS    STA_SYM, _reg_adrs_internal,    ?L0005, U,      0CH,    03H,    00H,    00H
-   44    44                      $DGS    STA_SYM, _tx_buf,       ?L0006, U,      0CH,    03H,    00H,    00H
-   45    45                      $DGS    REG_VAR, _rx_buf,       06H,    0FFFFH, 010CH,  04H,    00H,    00H
-   46    46                      $DGS    BEG_BLK, ??bb00_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   47    47                      $DGS    AUX_BEG, 0CH,           00H,    020H
-   48    48                      $DGS    BEG_BLK, ??bb01_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   49    49                      $DGS    AUX_BEG, 014H,          00H,    022H
-   50    50                      $DGS    BEG_BLK, ??bb02_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   51    51                      $DGS    AUX_BEG, 015H,          00H,    026H
-   52    52                      $DGS    END_BLK, ??eb02_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   53    53                      $DGS    AUX_END, 015H
-   54    54                      $DGS    BEG_BLK, ??bb03_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   55    55                      $DGS    AUX_BEG, 01BH,          00H,    028H
-   56    56                      $DGS    BEG_BLK, ??bb04_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   57    57                      $DGS    AUX_BEG, 01CH,          00H,    02CH
-   58    58                      $DGS    END_BLK, ??eb04_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   59    59                      $DGS    AUX_END, 01CH
-   60    60                      $DGS    BEG_BLK, ??bb05_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   61    61                      $DGS    AUX_BEG, 01DH,          00H,    036H
-   62    62                      $DGS    END_BLK, ??eb05_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   63    63                      $DGS    AUX_END, 01DH
-   64    64                      $DGS    END_BLK, ??eb03_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   65    65                      $DGS    AUX_END, 01EH
-   66    66                      $DGS    END_BLK, ??eb01_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   67    67                      $DGS    AUX_END, 01FH
-   68    68                      $DGS    END_BLK, ??eb00_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   69    69                      $DGS    AUX_END, 026H
-   70    70                      $DGS    BEG_BLK, ??bb06_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   71    71                      $DGS    AUX_BEG, 02AH,          00H,    03AH
-   72    72                      $DGS    END_BLK, ??eb06_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   73    73                      $DGS    AUX_END, 030H
-   74    74                      $DGS    BEG_BLK, ??bb07_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   75    75                      $DGS    AUX_BEG, 033H,          00H,    03CH
-   76    76                      $DGS    BEG_BLK, ??bb08_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   77    77                      $DGS    AUX_BEG, 037H,          00H,    042H
-   78    78                      $DGS    END_BLK, ??eb08_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   79    79                      $DGS    AUX_END, 03AH
-   80    80                      $DGS    END_BLK, ??eb07_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   81    81                      $DGS    AUX_END, 03BH
-   82    82                      $DGS    BEG_BLK, ??bb09_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   83    83                      $DGS    AUX_BEG, 03EH,          00H,    044H
-   84    84                      $DGS    BEG_BLK, ??bb0A_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   85    85                      $DGS    AUX_BEG, 04CH,          00H,    048H
-   86    86                      $DGS    END_BLK, ??eb0A_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   87    87                      $DGS    AUX_END, 04EH
-   88    88                      $DGS    BEG_BLK, ??bb0B_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   89    89                      $DGS    AUX_BEG, 050H,          00H,    04CH
-   90    90                      $DGS    END_BLK, ??eb0B_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   91    91                      $DGS    AUX_END, 052H
-   92    92                      $DGS    BEG_BLK, ??bb0C_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   93    93                      $DGS    AUX_BEG, 059H,          00H,    04EH
-   94    94                      $DGS    BEG_BLK, ??bb0D_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   95    95                      $DGS    AUX_BEG, 05CH,          00H,    052H
-   96    96                      $DGS    END_BLK, ??eb0D_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   97    97                      $DGS    AUX_END, 05FH
-   98    98                      $DGS    BEG_BLK, ??bb0E_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-   99    99                      $DGS    AUX_BEG, 061H,          00H,    058H
-  100   100                      $DGS    END_BLK, ??eb0E_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  101   101                      $DGS    AUX_END, 067H
-  102   102                      $DGS    END_BLK, ??eb0C_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  103   103                      $DGS    AUX_END, 068H
-  104   104                      $DGS    BEG_BLK, ??bb0F_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  105   105                      $DGS    AUX_BEG, 06AH,          00H,    05CH
-  106   106                      $DGS    END_BLK, ??eb0F_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  107   107                      $DGS    AUX_END, 06DH
-  108   108                      $DGS    BEG_BLK, ??bb10_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  109   109                      $DGS    AUX_BEG, 071H,          00H,    060H
-  110   110                      $DGS    END_BLK, ??eb10_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  111   111                      $DGS    AUX_END, 074H
-  112   112                      $DGS    BEG_BLK, ??bb11_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  113   113                      $DGS    AUX_BEG, 076H,          00H,    064H
-  114   114                      $DGS    END_BLK, ??eb11_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  115   115                      $DGS    AUX_END, 07AH
-  116   116                      $DGS    BEG_BLK, ??bb12_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  117   117                      $DGS    AUX_BEG, 07EH,          00H,    068H
-  118   118                      $DGS    END_BLK, ??eb12_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  119   119                      $DGS    AUX_END, 080H
-  120   120                      $DGS    BEG_BLK, ??bb13_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  121   121                      $DGS    AUX_BEG, 083H,          00H,    00H
-  122   122                      $DGS    END_BLK, ??eb13_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  123   123                      $DGS    AUX_END, 085H
-  124   124                      $DGS    END_BLK, ??eb09_int_iic_ctr,    U,      U,      00H,    064H,   01H,    00H
-  125   125                      $DGS    AUX_END, 087H
-  126   126                      $DGS    END_FUN, ??ef_int_iic_ctr,      U,      U,      00H,    065H,   01H,    00H
-  127   127                      $DGS    AUX_END, 088H
-  128   128                      $DGS    GLV_SYM, _IIC_ctr_Init, U,      U,      01H,    026H,   01H,    02H
-  129   129                      $DGS    AUX_FUN, 00H,           U,      U,      076H,   00H,    00H
-  130   130                      $DGS    BEG_FUN, ??bf_IIC_ctr_Init,     U,      U,      00H,    065H,   01H,    00H
-  131   131                      $DGS    AUX_BEG, 0CEH,          00H,    076H
-  132   132                      $DGS    END_FUN, ??ef_IIC_ctr_Init,     U,      U,      00H,    065H,   01H,    00H
-  133   133                      $DGS    AUX_END, 02CH
-  134   134                      $DGS    GLV_SYM, _IIC_ctr_Stop, U,      U,      01H,    026H,   01H,    02H
-  135   135                      $DGS    AUX_FUN, 00H,           U,      U,      07CH,   00H,    00H
-  136   136                      $DGS    BEG_FUN, ??bf_IIC_ctr_Stop,     U,      U,      00H,    065H,   01H,    00H
-  137   137                      $DGS    AUX_BEG, 0FFH,          00H,    07CH
-  138   138                      $DGS    END_FUN, ??ef_IIC_ctr_Stop,     U,      U,      00H,    065H,   01H,    00H
-  139   139                      $DGS    AUX_END, 04H
-  140   140                      $DGS    GLV_SYM, _iic_burst_state,      U,      U,      0CH,    026H,   00H,    00H
-  141   141                      $DGS    GLV_SYM, _@SEGAX,       U,      U,      00H,    02H,    00H,    00H
-  142   142                      $DGS    GLV_SYM, _irq_readed,   U,      U,      034CH,  02H,    00H,    00H
-  143   143                      $DGS    GLV_SYM, _vreg_ctr,     U,      U,      0CH,    02H,    01H,    03H
-  144   144                      $DGS    AUX_STR, 00H,           00H,    01H,    01H,    00H,    00H,    00H,    00H
-  145   145                      $DGS    GLV_SYM, _hosu_read_end,        U,      U,      01H,    02H,    01H,    02H
-  146   146                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  147   147                      $DGS    GLV_SYM, _rtc_unlock,   U,      U,      01H,    02H,    01H,    02H
-  148   148                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  149   149                      $DGS    GLV_SYM, _vreg_ctr_read,        U,      U,      0CH,    02H,    01H,    02H
-  150   150                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  151   151                      $DGS    GLV_SYM, _vreg_ctr_after_read,  U,      U,      01H,    02H,    01H,    02H
-  152   152                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  153   153                      $DGS    GLV_SYM, _vreg_ctr_write,       U,      U,      01H,    02H,    01H,    02H
-  154   154                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  155   155                      $DGS    GLV_SYM, _@SEGDE,       U,      U,      00H,    02H,    00H,    00H
-  156   156                      $DGS    GLV_SYM, _@RTARG0,      U,      U,      00H,    02H,    00H,    00H
-  157   157                      
-  158   158                              EXTRN   _@SEGAX
-  159   159                              EXTRN   _@SEGDE
-  160   160                              EXTRN   _@RTARG0
-  161   161                              EXTRN   _vreg_ctr
-  162   162                              EXTRN   _hosu_read_end
-  163   163                              EXTRN   _rtc_unlock
-  164   164                              EXTRN   _vreg_ctr_read
-  165   165                              EXTRN   _vreg_ctr_after_read
-  166   166                              EXTRN   _vreg_ctr_write
-  167   167                              EXTBIT  _irq_readed
-  168   168                              PUBLIC  _iic_burst_state
-  169   169                              PUBLIC  _int_iic_ctr
-  170   170                              PUBLIC  _IIC_ctr_Init
-  171   171                              PUBLIC  _IIC_ctr_Stop
-  172   172                      
-  173   173 -----                @@BITS  BSEG
-  174   174                      
-  175   175 -----                @@CNST  CSEG    MIRRORP
-  176   176 00000  01            _lpf_coeff:     DB      01H     ; 1
-  177   177 00001  02                    DB      02H     ; 2
-  178   178 00002  02                    DB      02H     ; 2
-  179   179 00003  03                    DB      03H     ; 3
-  180   180 00004  03                    DB      03H     ; 3
-  181   181 00005  02                    DB      02H     ; 2
-  182   182 00006  00                    DB      00H     ; 0
-  183   183 00007  FE                    DB      0FEH    ; 254
-  184   184 00008  FB                    DB      0FBH    ; 251
-  185   185 00009  F7                    DB      0F7H    ; 247
-  186   186 0000A  F3                    DB      0F3H    ; 243
-  187   187 0000B  F0                    DB      0F0H    ; 240
-  188   188 0000C  F0                    DB      0F0H    ; 240
-  189   189 0000D  F3                    DB      0F3H    ; 243
-  190   190 0000E  FA                    DB      0FAH    ; 250
-  191   191 0000F  04                    DB      04H     ; 4
-  192   192 00010  12                    DB      012H    ; 18
-  193   193 00011  25                    DB      025H    ; 37
-  194   194 00012  38                    DB      038H    ; 56
-  195   195 00013  4D                    DB      04DH    ; 77
-  196   196 00014  5F                    DB      05FH    ; 95
-  197   197 00015  6E                    DB      06EH    ; 110
-  198   198 00016  77                    DB      077H    ; 119
-  199   199 00017  7A                    DB      07AH    ; 122
-  200   200 00018  77                    DB      077H    ; 119
-  201   201 00019  6E                    DB      06EH    ; 110
-  202   202 0001A  5F                    DB      05FH    ; 95
-  203   203 0001B  4D                    DB      04DH    ; 77
-  204   204 0001C  38                    DB      038H    ; 56
-  205   205 0001D  25                    DB      025H    ; 37
-  206   206 0001E  12                    DB      012H    ; 18
-  207   207 0001F  04                    DB      04H     ; 4
-  208   208 00020  FA                    DB      0FAH    ; 250
-  209   209 00021  F3                    DB      0F3H    ; 243
-  210   210 00022  F0                    DB      0F0H    ; 240
-  211   211 00023  F0                    DB      0F0H    ; 240
-  212   212 00024  F3                    DB      0F3H    ; 243
-  213   213 00025  F7                    DB      0F7H    ; 247
-  214   214 00026  FB                    DB      0FBH    ; 251
-  215   215 00027  FE                    DB      0FEH    ; 254
-  216   216 00028  00                    DB      00H     ; 0
-  217   217 00029  02                    DB      02H     ; 2
-  218   218 0002A  03                    DB      03H     ; 3
-  219   219 0002B  03                    DB      03H     ; 3
-  220   220 0002C  02                    DB      02H     ; 2
-  221   221 0002D  02                    DB      02H     ; 2
-  222   222 0002E  01                    DB      01H     ; 1
-  223   223 0002F  00                    DB      (1)
-  224   224                      
-  225   225 -----                @@R_INIT        CSEG    UNIT64KP
-  226   226 00000  00                    DB      00H     ; 0
-  227   227 00001  00                    DB      (1)
-  228   228                      
-  229   229 -----                @@INIT  DSEG    BASEP
-  230   230 00000                ?L0003: DS      (1)
-  231   231 00001                        DS      (1)
-  232   232                      
-  233   233 -----                @@DATA  DSEG    BASEP
-  234   234 00000                _iic_burst_state:       DS      (1)
-  235   235 00001                ?L0004: DS      (1)
-  236   236 00002                ?L0005: DS      (1)
-  237   237 00003                ?L0006: DS      (1)
-  238   238                      
-  239   239 -----                @@R_INIS        CSEG    UNIT64KP
-  240   240                      
-  241   241 -----                @@INIS  DSEG    SADDRP
-  242   242                      
-  243   243 -----                @@DATS  DSEG    SADDRP
-  244   244                      
-  245   245 -----                @@CNSTL CSEG    PAGE64KP
-  246   246                      
-  247   247 -----                @@RLINIT        CSEG    UNIT64KP
-  248   248                      
-  249   249 -----                @@INITL DSEG    UNIT64KP
-  250   250                      
-  251   251 -----                @@DATAL DSEG    UNIT64KP
-  252   252                      
-  253   253 -----                @@CALT  CSEG    CALLT0
-  254   254                      
-  255   255                      ; line     1 : /* ========================================================
-  256   256                      ; line     2 :   対SoC 新規チャンネル I2C通信
-  257   257                      ; line     3 :     藤田＠開技.nintendo
-  258   258                      ; line     4 :  '09 Apr
-  259   259                      ; line     5 :  ======================================================== */
-  260   260                      ; line     6 : #include "incs.h"
-  261   261                      ; line     7 : #include "accero.h"
-  262   262                      ; line     8 : 
-  263   263                      ; line     9 : #ifdef _MCU_BSR_
-  264   264                      ; line    10 : // #ifdef _MODEL_TS0_ || _MODEL_WM0_
-  265   265                      ; line    11 : 
-  266   266                      ; line    12 : // ワーキングモデルはI2Cが逆
-  267   267                      ; line    13 : // TEGは回路図でテレコ
-  268   268                      ; line    14 : #define ACKD       ACKD1
-  269   269                      ; line    15 : #define ACKE       ACKE1
-  270   270                      ; line    16 : #define COI        COI1
-  271   271                      ; line    17 : #define IICAEN     IICA1EN
-  272   272                      ; line    18 : #define IICRSV     IICRSV1
-  273   273                      ; line    19 : #define IICA       IICA1
-  274   274                      ; line    20 : #define IICAIF     IICAIF1
-  275   275                      ; line    21 : #define IICAMK     IICAMK1
-  276   276                      ; line    22 : #define IICAPR0    IICAPR11
-  277   277                      ; line    23 : #define IICAPR1    IICAPR01
-  278   278                      ; line    24 : #define IICCTL0    IICCTL10
-  279   279                      ; line    25 : #define IICE       IICE1
-  280   280                      ; line    26 : #define IICF       IICF1
-  281   281                      ; line    27 : #define IICS       IICS1
-  282   282                      ; line    28 : #define IICWH      IICWH1
-  283   283                      ; line    29 : #define IICWL      IICWL1
-  284   284                      ; line    30 : #define LREL       LREL1
-  285   285                      ; line    31 : #define SPD        SPD1
-  286   286                      ; line    32 : #define SPIE       SPIE1
-  287   287                      ; line    33 : #define STCEN      STCEN1
-  288   288                      ; line    34 : #define STD        STD1
-  289   289                      ; line    35 : #define SVA        SVA1
-  290   290                      ; line    36 : #define WREL       WREL1
-  291   291                      ; line    37 : #define WTIM       WTIM1
-  292   292                      ; line    38 : #define TRC        TRC1
-  293   293                      ; line    39 : #define SMC        SMC1
-  294   294                      ; line    40 : #define DFC        DFC1
-  295   295                      ; line    41 : 
-  296   296                      ; line    42 : 
-  297   297                      ; line    43 : #endif
-  298   298                      ; line    44 : 
-  299   299                      ; line    45 : // ==============================================
-  300   300                      ; line    46 : extern bit irq_readed;                 // いずれかのIRQレジスタが
-  301   301                      ;              読まれた
-  302   302                      ; line    47 : 
-  303   303                      ; line    48 : u8 iic_burst_state;
-  304   304                      ; line    49 : 
-  305   305                      ; line    50 : 
-  306   306                      ; line    51 : /* ========================================================
-  307   307                      ; line    52 :  ======================================================== */
-  308   308                      ; line    53 : enum
-  309   309                      ; line    54 : {
-  310   310                      ; line    55 :     IIC_IDLE = 0,
-  311   311                      ; line    56 :     IIC_RCV_REG_ADRS,
-  312   312                      ; line    57 :     IIC_TX_OR_RX,
-  313   313                      ; line    58 :     IIC_TX,
-  314   314                      ; line    59 :     IIC_RX
-  315   315                      ; line    60 : };
-  316   316                      ; line    61 : 
-  317   317                      ; line    62 : 
-  318   318                      ; line    63 : // 1バイト送受の度に割り込みが発生するバージョン
-  319   319                      ; line    64 : __interrupt void int_iic_ctr(  )
-  320   320                      ; line    65 : {
-  321   321                      
-  322   322 -----                @@BASE  CSEG    BASE
-  323   323 00000                _int_iic_ctr:
-  324   324                      $DGL    1,21
-  325   325 00000  C1                    push    ax                                              ;[INF] 1, 1
-  326   326 00001  C3                    push    bc                                              ;[INF] 1, 1
-  327   327 00002  C5                    push    de                                              ;[INF] 1, 1
-  328   328 00003  C7                    push    hl                                              ;[INF] 1, 1
-  329   329 00004  520C                  mov     c,#0CH                                          ;[INF] 2, 1
-  330   330 00006  92                    dec     c                                               ;[INF] 1, 1
-  331   331 00007  92                    dec     c                                               ;[INF] 1, 1
-  332   332 00008 R690000                movw    ax,_@SEGAX[c]                                   ;[INF] 3, 1
-  333   333 0000B  C1                    push    ax                                              ;[INF] 1, 1
-  334   334 0000C  DFF8                  bnz     $$-6                                            ;[INF] 2, 4
-  335   335 0000E  8EFD                  mov     a,ES                                            ;[INF] 2, 1
-  336   336 00010  70                    mov     x,a                                             ;[INF] 1, 1
-  337   337 00011  8EFC                  mov     a,CS                                            ;[INF] 2, 1
-  338   338 00013  C1                    push    ax                                              ;[INF] 1, 1
-  339   339 00014                ??bf_int_iic_ctr:
-  340   340                      ; line    66 :     static u8 state = IIC_IDLE;
-  341   341                      ; line    67 :     static u8 reg_adrs;
-  342   342                      ; line    68 :     static u8 reg_adrs_internal;
-  343   343                      ; line    69 :     static u8 tx_buf;
-  344   344                      ; line    70 :     u8 rx_buf;
-  345   345                      ; line    71 : 
-  346   346                      ; line    72 :     EI();
-  347   347                      $DGL    0,8
-  348   348 00014  717AFA                ei                                                      ;[INF] 3, 4
-  349   349                      ; line    73 : 
-  350   350                      ; line    74 :     // 読み出し終了
-  351   351                      ; line    75 :     if( !ACKD )                 // 割り込み要因はNAK（データ送信
-  352   352                      ;              の最後）
-  353   353                      $DGL    0,11
-  354   354 00017  C7                    push    hl                                              ;[INF] 1, 1
-  355   355 00018  364105                movw    hl,#0541H       ; 1345                          ;[INF] 3, 1
-  356   356 0001B  71A4                  mov1    CY,[hl].2                                       ;[INF] 2, 1
-  357   357 0001D  C6                    pop     hl                                              ;[INF] 1, 1
-  358   358 0001E  DC41                  bc      $?L0007                                         ;[INF] 2, 4
-  359   359                      ; line    76 :     {
-  360   360 00020                ??bb00_int_iic_ctr:
-  361   361                      ; line    77 :         state = IIC_IDLE;
-  362   362                      $DGL    0,13
-  363   363 00020 RF50000                clrb    !?L0003 ; state                                 ;[INF] 3, 1
-  364   364                      ; line    78 :         SPIE = 0;
-  365   365                      $DGL    0,14
-  366   366 00023  71485005              clr1    !IICCTL01.4                                     ;[INF] 4, 2
-  367   367                      ; line    79 :         LREL = 1;
-  368   368                      $DGL    0,15
-  369   369 00027  71605005              set1    !IICCTL01.6                                     ;[INF] 4, 2
-  370   370                      ; line    80 : 
-  371   371                      ; line    81 :         // レジスタリードで、割り込みピンをネゲート
-  372   372                      ; line    82 :         // まだ読まれてない割り込みがあれば、再度アサート
-  373   373                      ; line    83 :         if( irq_readed )
-  374   374                      $DGL    0,19
-  375   375 0002B R31040026              bf      _irq_readed,$?L0011                             ;[INF] 4, 5
-  376   376                      ; line    84 :         {
-  377   377 0002F                ??bb01_int_iic_ctr:
-  378   378                      ; line    85 :             IRQ0_neg;
-  379   379                      $DGL    0,21
-  380   380 0002F                ??bb02_int_iic_ctr:
-  381   381 0002F  716A27                set1    PM7.6                                           ;[INF] 3, 2
-  382   382 00032                ??eb02_int_iic_ctr:
-  383   383                      ; line    86 :             irq_readed = 0;
-  384   384                      $DGL    0,22
-  385   385 00032 R710300                clr1    _irq_readed                                     ;[INF] 3, 2
-  386   386                      ; line    87 :             if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 )
-  387   387                      ; line    88 :                    && ( vreg_ctr[VREG_C_IRQ1] == 0 )
-  388   388                      ; line    89 :                    && ( vreg_ctr[VREG_C_IRQ2] == 0 )
-  389   389                      ; line    90 :                    && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) )
-  390   390                      $DGL    0,26
-  391   391 00035 RD51000                cmp0    !_vreg_ctr+16                                   ;[INF] 3, 1
-  392   392 00038  DF0F                  bnz     $?L0013                                         ;[INF] 2, 4
-  393   393 0003A RD51100                cmp0    !_vreg_ctr+17                                   ;[INF] 3, 1
-  394   394 0003D  DF0A                  bnz     $?L0013                                         ;[INF] 2, 4
-  395   395 0003F RD51200                cmp0    !_vreg_ctr+18                                   ;[INF] 3, 1
-  396   396 00042  DF05                  bnz     $?L0013                                         ;[INF] 2, 4
-  397   397 00044 RD51300                cmp0    !_vreg_ctr+19                                   ;[INF] 3, 1
-  398   398 00047  DD0C                  bz      $?L0011                                         ;[INF] 2, 4
-  399   399 00049                ?L0013:
-  400   400                      ; line    91 :             {
-  401   401 00049                ??bb03_int_iic_ctr:
-  402   402                      ; line    92 :                 while( !IRQ0 ){;}  // 時間稼ぎ不要かも
-  403   403                      $DGL    0,28
-  404   404 00049  31620702              bt      P7.6,$?L0015                                    ;[INF] 4, 5
-  405   405 0004D                ??bb04_int_iic_ctr:
-  406   406 0004D                ??eb04_int_iic_ctr:
-  407   407 0004D  EFFA                  br      $?L0013                                         ;[INF] 2, 3
-  408   408 0004F                ?L0015:
-  409   409                      ; line    93 :                 IRQ0_ast;
-  410   410                      $DGL    0,29
-  411   411 0004F                ??bb05_int_iic_ctr:
-  412   412 0004F  716307                clr1    P7.6                                            ;[INF] 3, 2
-  413   413 00052  716B27                clr1    PM7.6                                           ;[INF] 3, 2
-  414   414 00055                ??eb05_int_iic_ctr:
-  415   415 00055                ??eb03_int_iic_ctr:
-  416   416                      ; line    94 :             }
-  417   417 00055                ?L0011:
-  418   418 00055                ??eb01_int_iic_ctr:
-  419   419                      ; line    95 :         }
-  420   420                      ; line    96 : 
-  421   421                      ; line    97 :         // 歩数計読み出し終了
-  422   422                      ; line    98 :         hosu_read_end(  );
-  423   423                      $DGL    0,34
-  424   424 00055 RFD0000                call    !_hosu_read_end                                 ;[INF] 3, 3
-  425   425                      ; line    99 :         rtc_unlock(  );
-  426   426                      $DGL    0,35
-  427   427 00058 RFD0000                call    !_rtc_unlock                                    ;[INF] 3, 3
-  428   428                      ; line   100 :         iic_burst_state = 0;
-  429   429                      $DGL    0,36
-  430   430 0005B RF50000                clrb    !_iic_burst_state                               ;[INF] 3, 1
-  431   431                      ; line   101 :         return;
-  432   432                      $DGL    0,37
-  433   433 0005E RED4B01                br      !?L0023                                         ;[INF] 3, 3
-  434   434 00061                ??eb00_int_iic_ctr:
-  435   435                      ; line   102 :     }
-  436   436 00061                ?L0007:
-  437   437                      ; line   103 : 
-  438   438                      ; line   104 :     if( SPD )                   // 割り込み要因はストップコンディ
-  439   439                      ;              ション
-  440   440                      $DGL    0,40
-  441   441 00061  C7                    push    hl                                              ;[INF] 1, 1
-  442   442 00062  364105                movw    hl,#0541H       ; 1345                          ;[INF] 3, 1
-  443   443 00065  7184                  mov1    CY,[hl].0                                       ;[INF] 2, 1
-  444   444 00067  C6                    pop     hl                                              ;[INF] 1, 1
-  445   445 00068  DE0D                  bnc     $?L0016                                         ;[INF] 2, 4
-  446   446                      ; line   105 :                                 // 通信の最後。↑の !ACKD に来た
-  447   447                      ;              ときは割り込み来ない (SPIE = 0 のため )
-  448   448                      ; line   106 :     {
-  449   449 0006A                ??bb06_int_iic_ctr:
-  450   450                      ; line   107 :         state = IIC_IDLE;
-  451   451                      $DGL    0,43
-  452   452 0006A RF50000                clrb    !?L0003 ; state                                 ;[INF] 3, 1
-  453   453                      ; line   108 :         SPIE = 0;
-  454   454                      $DGL    0,44
-  455   455 0006D  71485005              clr1    !IICCTL01.4                                     ;[INF] 4, 2
-  456   456                      ; line   109 :         // I2C終了時に何かする物 //
-  457   457                      ; line   110 :         rtc_unlock(  );
-  458   458                      $DGL    0,46
-  459   459 00071 RFD0000                call    !_rtc_unlock                                    ;[INF] 3, 3
-  460   460                      ; line   111 :         return;
-  461   461                      $DGL    0,47
-  462   462 00074 RED4B01                br      !?L0023                                         ;[INF] 3, 3
-  463   463 00077                ??eb06_int_iic_ctr:
-  464   464                      ; line   112 :     }
-  465   465 00077                ?L0016:
-  466   466                      ; line   113 : 
-  467   467                      ; line   114 :     if( STD )                   // 割り込み要因：スタートコンディ
-  468   468                      ;              ション
-  469   469                      $DGL    0,50
-  470   470 00077  C7                    push    hl                                              ;[INF] 1, 1
-  471   471 00078  364105                movw    hl,#0541H       ; 1345                          ;[INF] 3, 1
-  472   472 0007B  7194                  mov1    CY,[hl].1                                       ;[INF] 2, 1
-  473   473 0007D  C6                    pop     hl                                              ;[INF] 1, 1
-  474   474 0007E  DE15                  bnc     $?L0020                                         ;[INF] 2, 4
-  475   475                      ; line   115 :     {
-  476   476 00080                ??bb07_int_iic_ctr:
-  477   477                      ; line   116 :         if( ( state == IIC_TX ) || ( state == IIC_RX )
-  478   478                      ; line   117 :             || ( state == IIC_RCV_REG_ADRS )
-  479   479                      $DGL    0,53
-  480   480 00080 R40000003              cmp     !?L0003,#03H    ; state,3                       ;[INF] 4, 1
-  481   481 00084  DD0C                  bz      $?L0022                                         ;[INF] 2, 4
-  482   482 00086 R40000004              cmp     !?L0003,#04H    ; state,4                       ;[INF] 4, 1
-  483   483 0008A  DD06                  bz      $?L0022                                         ;[INF] 2, 4
-  484   484 0008C R40000001              cmp     !?L0003,#01H    ; state,1                       ;[INF] 4, 1
-  485   485 00090  61F8                  sknz                                                    ;[INF] 2, 1
-  486   486 00092                ?L0022:
-  487   487                      ; line   118 :             )
-  488   488                      ; line   119 :         {
-  489   489 00092                ??bb08_int_iic_ctr:
-  490   490                      ; line   120 :             state = IIC_IDLE;
-  491   491                      $DGL    0,56
-  492   492 00092 RF50000                clrb    !?L0003 ; state                                 ;[INF] 3, 1
-  493   493 00095                ??eb08_int_iic_ctr:
-  494   494                      ; line   121 :             // no break //
-  495   495                      ; line   122 :         }
-  496   496 00095                ?L0020:
-  497   497 00095                ??eb07_int_iic_ctr:
-  498   498                      ; line   123 :     }
-  499   499                      ; line   124 : 
-  500   500                      ; line   125 :     switch ( state )
-  501   501                      $DGL    0,61
-  502   502 00095 RD90000                mov     x,!?L0003       ; state                         ;[INF] 3, 1
-  503   503 00098  F1                    clrb    a                                               ;[INF] 1, 1
-  504   504 00099  E7                    onew    bc                                              ;[INF] 1, 1
-  505   505 0009A  240000                subw    ax,#00H ; 0                                     ;[INF] 3, 1
-  506   506 0009D  DD08                  bz      $?L0024                                         ;[INF] 2, 4
-  507   507 0009F  23                    subw    ax,bc                                           ;[INF] 1, 1
-  508   508 000A0  DD13                  bz      $?L0025                                         ;[INF] 2, 4
-  509   509 000A2  23                    subw    ax,bc                                           ;[INF] 1, 1
-  510   510 000A3  DD36                  bz      $?L0026                                         ;[INF] 2, 4
-  511   511 000A5  EF5D                  br      $?L0033                                         ;[INF] 2, 3
-  512   512                      ; line   126 :     {
-  513   513 000A7                ??bb09_int_iic_ctr:
-  514   514                      ; line   127 :     case ( IIC_IDLE ):
-  515   515 000A7                ?L0024:
-  516   516                      ; line   128 :         // 自局呼び出しに応答。
-  517   517                      ; line   129 :         // 初期化など
-  518   518                      ; line   130 :         SPIE = 1;
-  519   519                      $DGL    0,66
-  520   520 000A7  71405005              set1    !IICCTL01.4                                     ;[INF] 4, 2
-  521   521                      ; line   131 :         state = IIC_RCV_REG_ADRS;
-  522   522                      $DGL    0,67
-  523   523 000AB RE50000                oneb    !?L0003 ; state                                 ;[INF] 3, 1
-  524   524                      ; line   132 :         WREL = 1;               // ウェイト解除
-  525   525                      $DGL    0,68
-  526   526 000AE  71505005              set1    !IICCTL01.5                                     ;[INF] 4, 2
-  527   527                      ; line   133 :         break;
-  528   528                      $DGL    0,69
-  529   529 000B2 RED4B01                br      !?L0023                                         ;[INF] 3, 3
-  530   530                      ; line   134 : 
-  531   531                      ; line   135 :     case ( IIC_RCV_REG_ADRS ):  // ２バイト目（レジスタアドレス）
-  532   532                      ;              受信後に来る
-  533   533 000B5                ?L0025:
-  534   534                      ; line   136 :         // レジスタアドレス受信
-  535   535                      ; line   137 :         reg_adrs = IICA;
-  536   536                      $DGL    0,73
-  537   537 000B5  8F4005                mov     a,!IICA1                                        ;[INF] 3, 1
-  538   538 000B8 R9F0100                mov     !?L0004,a       ; reg_adrs                      ;[INF] 3, 1
-  539   539                      ; line   138 :         tx_buf = vreg_ctr_read( reg_adrs );    // データの準備を
-  540   540                      ;              しておく
-  541   541                      $DGL    0,74
-  542   542 000BB RD90100                mov     x,!?L0004       ; reg_adrs                      ;[INF] 3, 1
-  543   543 000BE  F1                    clrb    a                                               ;[INF] 1, 1
-  544   544 000BF RFD0000                call    !_vreg_ctr_read                                 ;[INF] 3, 3
-  545   545 000C2  62                    mov     a,c                                             ;[INF] 1, 1
-  546   546 000C3 R9F0300                mov     !?L0006,a       ; tx_buf                        ;[INF] 3, 1
-  547   547                      ; line   139 :         if( reg_adrs != VREG_C_INFO )
-  548   548                      $DGL    0,75
-  549   549 000C6 R4001007F              cmp     !?L0004,#07FH   ; reg_adrs,127                  ;[INF] 4, 1
-  550   550 000CA  DD06                  bz      $?L0030                                         ;[INF] 2, 4
-  551   551                      ; line   140 :         {
-  552   552 000CC                ??bb0A_int_iic_ctr:
-  553   553                      ; line   141 :             state = IIC_TX_OR_RX;
-  554   554                      $DGL    0,77
-  555   555 000CC RCF000002              mov     !?L0003,#02H    ; state,2                       ;[INF] 4, 1
-  556   556 000D0                ??eb0A_int_iic_ctr:
-  557   557                      ; line   142 :         }
-  558   558                      $DGL    0,78
-  559   559 000D0  EF03                  br      $?L0031                                         ;[INF] 2, 3
-  560   560 000D2                ?L0030:
-  561   561                      ; line   143 :         else
-  562   562                      ; line   144 :         {
-  563   563 000D2                ??bb0B_int_iic_ctr:
-  564   564                      ; line   145 :             state = IIC_IDLE;
-  565   565                      $DGL    0,81
-  566   566 000D2 RF50000                clrb    !?L0003 ; state                                 ;[INF] 3, 1
-  567   567 000D5                ??eb0B_int_iic_ctr:
-  568   568                      ; line   146 :         }
-  569   569 000D5                ?L0031:
-  570   570                      ; line   147 :         WREL = 1;
-  571   571                      $DGL    0,83
-  572   572 000D5  71505005              set1    !IICCTL01.5                                     ;[INF] 4, 2
-  573   573                      ; line   148 :         break;
-  574   574                      $DGL    0,84
-  575   575 000D9  EF70                  br      $?L0023                                         ;[INF] 2, 3
-  576   576                      ; line   149 : 
-  577   577                      ; line   150 :     case ( IIC_TX_OR_RX ):      // ↑の次に来る割り込み。STなら送
-  578   578                      ;              信準備、データが来たら書き込まれ
-  579   579 000DB                ?L0026:
-  580   580                      ; line   151 : //    if( TRC ){           // 送信方向フラグ で区別するのは、割り
-  581   581                      ;              込み遅延時に不具合が起こりえる
-  582   582                      ; line   152 :         if( STD )
-  583   583                      $DGL    0,88
-  584   584 000DB  C7                    push    hl                                              ;[INF] 1, 1
-  585   585 000DC  364105                movw    hl,#0541H       ; 1345                          ;[INF] 3, 1
-  586   586 000DF  7194                  mov1    CY,[hl].1                                       ;[INF] 2, 1
-  587   587 000E1  C6                    pop     hl                                              ;[INF] 1, 1
-  588   588 000E2  DE1C                  bnc     $?L0032                                         ;[INF] 2, 4
-  589   589                      ; line   153 :         {                       // スタートコンディション検出フラ
-  590   590                      ;              グ
-  591   591 000E4                ??bb0C_int_iic_ctr:
-  592   592                      ; line   154 :             // リードされる
-  593   593                      ; line   155 :             if( COI )
-  594   594                      $DGL    0,91
-  595   595 000E4  C7                    push    hl                                              ;[INF] 1, 1
-  596   596 000E5  364105                movw    hl,#0541H       ; 1345                          ;[INF] 3, 1
-  597   597 000E8  71C4                  mov1    CY,[hl].4                                       ;[INF] 2, 1
-  598   598 000EA  C6                    pop     hl                                              ;[INF] 1, 1
-  599   599 000EB  DE06                  bnc     $?L0034                                         ;[INF] 2, 4
-  600   600                      ; line   156 :             {                   // アドレス一致フラグ
-  601   601 000ED                ??bb0D_int_iic_ctr:
-  602   602                      ; line   157 :                 state = IIC_TX;
-  603   603                      $DGL    0,93
-  604   604 000ED RCF000003              mov     !?L0003,#03H    ; state,3                       ;[INF] 4, 1
-  605   605 000F1                ??eb0D_int_iic_ctr:
-  606   606                      ; line   158 :                 // no break, no return //
-  607   607                      ; line   159 :             }
-  608   608                      $DGL    0,95
-  609   609 000F1  EF11                  br      $?L0033                                         ;[INF] 2, 3
-  610   610 000F3                ?L0034:
-  611   611                      ; line   160 :             else
-  612   612                      ; line   161 :             {
-  613   613 000F3                ??bb0E_int_iic_ctr:
-  614   614                      ; line   162 :                 // リスタートで違うデバイスが呼ばれた！
-  615   615                      ; line   163 :                 state = IIC_IDLE;       // 終了処理
-  616   616                      $DGL    0,99
-  617   617 000F3 RF50000                clrb    !?L0003 ; state                                 ;[INF] 3, 1
-  618   618                      ; line   164 :                 SPIE = 0;
-  619   619                      $DGL    0,100
-  620   620 000F6  71485005              clr1    !IICCTL01.4                                     ;[INF] 4, 2
-  621   621                      ; line   165 :                 LREL = 1;       // ウェイト解除?
-  622   622                      $DGL    0,101
-  623   623 000FA  71605005              set1    !IICCTL01.6                                     ;[INF] 4, 2
-  624   624                      ; line   166 :                 return;
-  625   625                      $DGL    0,102
-  626   626 000FE  EF4B                  br      $?L0023                                         ;[INF] 2, 3
-  627   627 00100                ??eb0E_int_iic_ctr:
-  628   628                      ; line   167 :             }
-  629   629                      ; line   168 :         }
-  630   630 00100                ??eb0C_int_iic_ctr:
-  631   631 00100                ?L0032:
-  632   632                      ; line   169 :         else
-  633   633                      ; line   170 :         {
-  634   634 00100                ??bb0F_int_iic_ctr:
-  635   635                      ; line   171 :             state = IIC_RX;     // データ1バイト受信の割り込みだ
-  636   636                      ;              った
-  637   637                      $DGL    0,107
-  638   638 00100 RCF000004              mov     !?L0003,#04H    ; state,4                       ;[INF] 4, 1
-  639   639 00104                ??eb0F_int_iic_ctr:
-  640   640                      ; line   172 :             // no break, no return //
-  641   641                      ; line   173 :         }
-  642   642 00104                ?L0033:
-  643   643                      ; line   174 : 
-  644   644                      ; line   175 :     default:                    // バースト R/W でここが何回も呼
-  645   645                      ;              ばれることになる
-  646   646                      ; line   176 :         if( state == IIC_TX )
-  647   647                      $DGL    0,112
-  648   648 00104 R40000003              cmp     !?L0003,#03H    ; state,3                       ;[INF] 4, 1
-  649   649 00108  DF0F                  bnz     $?L0036                                         ;[INF] 2, 4
-  650   650                      ; line   177 :         {                       // 送信
-  651   651 0010A                ??bb10_int_iic_ctr:
-  652   652                      ; line   178 :             IICA = tx_buf;
-  653   653                      $DGL    0,114
-  654   654 0010A R8F0300                mov     a,!?L0006       ; tx_buf                        ;[INF] 3, 1
-  655   655 0010D  9F4005                mov     !IICA1,a                                        ;[INF] 3, 1
-  656   656                      ; line   179 :             vreg_ctr_after_read( reg_adrs );    // 読んだらクリア
-  657   657                      ;              などの処理
-  658   658                      $DGL    0,115
-  659   659 00110 RD90100                mov     x,!?L0004       ; reg_adrs                      ;[INF] 3, 1
-  660   660 00113  F1                    clrb    a                                               ;[INF] 1, 1
-  661   661 00114 RFD0000                call    !_vreg_ctr_after_read                           ;[INF] 3, 3
-  662   662 00117                ??eb10_int_iic_ctr:
-  663   663                      ; line   180 :         }
-  664   664                      $DGL    0,116
-  665   665 00117  EF12                  br      $?L0037                                         ;[INF] 2, 3
-  666   666 00119                ?L0036:
-  667   667                      ; line   181 :         else
-  668   668                      ; line   182 :         {                   // 受信
-  669   669 00119                ??bb11_int_iic_ctr:
-  670   670                      ; line   183 :             rx_buf = IICA;
-  671   671                      $DGL    0,119
-  672   672 00119  8F4005                mov     a,!IICA1                                        ;[INF] 3, 1
-  673   673 0011C  76                    mov     l,a                                             ;[INF] 1, 1
-  674   674                      ; line   184 :             vreg_ctr_write( reg_adrs, rx_buf );
-  675   675                      $DGL    0,120
-  676   676 0011D  17                    movw    ax,hl                                           ;[INF] 1, 1
-  677   677 0011E  F1                    clrb    a                                               ;[INF] 1, 1
-  678   678 0011F  C1                    push    ax                                              ;[INF] 1, 1
-  679   679 00120 RD90100                mov     x,!?L0004       ; reg_adrs                      ;[INF] 3, 1
-  680   680 00123 RFD0000                call    !_vreg_ctr_write                                ;[INF] 3, 3
-  681   681 00126  C0                    pop     ax                                              ;[INF] 1, 1
-  682   682                      ; line   185 :             WREL = 1;
-  683   683                      $DGL    0,121
-  684   684 00127  71505005              set1    !IICCTL01.5                                     ;[INF] 4, 2
-  685   685 0012B                ??eb11_int_iic_ctr:
-  686   686                      ; line   186 :         }
-  687   687 0012B                ?L0037:
-  688   688                      ; line   187 :         // 
-  689   689                      ; line   188 :         if( ( reg_adrs != VREG_C_ACC_HOSU_HIST )
-  690   690                      ; line   189 :             && ( reg_adrs != VREG_C_INFO ) )
-  691   691                      $DGL    0,125
-  692   692 0012B R4001004F              cmp     !?L0004,#04FH   ; reg_adrs,79                   ;[INF] 4, 1
-  693   693 0012F  DD09                  bz      $?L0038                                         ;[INF] 2, 4
-  694   694 00131 R4001007F              cmp     !?L0004,#07FH   ; reg_adrs,127                  ;[INF] 4, 1
-  695   695 00135  61E8                  skz                                                     ;[INF] 2, 1
-  696   696                      ; line   190 :         {   // この二つのレジスタは特殊なアクセス方法をする。アク
-  697   697                      ;              セスポインタを進めない。
-  698   698 00137                ??bb12_int_iic_ctr:
-  699   699                      ; line   191 :             reg_adrs += 1;
-  700   700                      $DGL    0,127
-  701   701 00137 RA00100                inc     !?L0004 ; reg_adrs                              ;[INF] 3, 2
-  702   702 0013A                ??eb12_int_iic_ctr:
-  703   703                      ; line   192 :         }
-  704   704 0013A                ?L0038:
-  705   705                      ; line   193 : 
-  706   706                      ; line   194 :         if( state == IIC_TX )
-  707   707                      $DGL    0,130
-  708   708 0013A R40000003              cmp     !?L0003,#03H    ; state,3                       ;[INF] 4, 1
-  709   709 0013E  DF0B                  bnz     $?L0023                                         ;[INF] 2, 4
-  710   710                      ; line   195 :         {                       // さらにつぎに送るデータの準備だ
-  711   711                      ;              けシテオク。SPが来て使われないかもしれない
-  712   712 00140                ??bb13_int_iic_ctr:
-  713   713                      ; line   196 :             tx_buf = vreg_ctr_read( reg_adrs );
-  714   714                      $DGL    0,132
-  715   715 00140 RD90100                mov     x,!?L0004       ; reg_adrs                      ;[INF] 3, 1
-  716   716 00143  F1                    clrb    a                                               ;[INF] 1, 1
-  717   717 00144 RFD0000                call    !_vreg_ctr_read                                 ;[INF] 3, 3
-  718   718 00147  62                    mov     a,c                                             ;[INF] 1, 1
-  719   719 00148 R9F0300                mov     !?L0006,a       ; tx_buf                        ;[INF] 3, 1
-  720   720 0014B                ??eb13_int_iic_ctr:
-  721   721                      ; line   197 :         }
-  722   722                      ; line   198 :         break;
-  723   723 0014B                ??eb09_int_iic_ctr:
-  724   724                      ; line   199 :     }
-  725   725 0014B                ?L0023:
-  726   726                      ; line   200 : }
-  727   727                      $DGL    0,136
-  728   728 0014B                ??ef_int_iic_ctr:
-  729   729 0014B  C0                    pop     ax                                              ;[INF] 1, 1
-  730   730 0014C  9EFC                  mov     CS,a                                            ;[INF] 2, 1
-  731   731 0014E  60                    mov     a,x                                             ;[INF] 1, 1
-  732   732 0014F  9EFD                  mov     ES,a                                            ;[INF] 2, 1
-  733   733 00151 R340000                movw    de,#_@SEGAX                                     ;[INF] 3, 1
-  734   734 00154  5206                  mov     c,#06H                                          ;[INF] 2, 1
-  735   735 00156  C0                    pop     ax                                              ;[INF] 1, 1
-  736   736 00157  B9                    movw    [de],ax                                         ;[INF] 1, 1
-  737   737 00158  A5                    incw    de                                              ;[INF] 1, 1
-  738   738 00159  A5                    incw    de                                              ;[INF] 1, 1
-  739   739 0015A  92                    dec     c                                               ;[INF] 1, 1
-  740   740 0015B  DFF9                  bnz     $$-5                                            ;[INF] 2, 4
-  741   741 0015D  C6                    pop     hl                                              ;[INF] 1, 1
-  742   742 0015E  C4                    pop     de                                              ;[INF] 1, 1
-  743   743 0015F  C2                    pop     bc                                              ;[INF] 1, 1
-  744   744 00160  C0                    pop     ax                                              ;[INF] 1, 1
-  745   745 00161  61FC                  reti                                                    ;[INF] 2, 6
-  746   746 00163                ??ee_int_iic_ctr:
-  747   747                      ; line   201 : 
-  748   748                      ; line   202 : 
-  749   749                      ; line   203 : 
-  750   750                      ; line   204 : // ========================================================
-  751   751                      ; line   205 : void IIC_ctr_Init( void )
-  752   752                      ; line   206 : {
-  753   753                      
-  754   754 -----                ROM_CODE        CSEG    BASE
-  755   755 00000                _IIC_ctr_Init:
-  756   756                      $DGL    1,112
-  757   757 00000                ??bf_IIC_ctr_Init:
-  758   758                      ; line   207 : 
-  759   759                      ; line   208 :     IICAEN = 1;
-  760   760                      $DGL    0,3
-  761   761 00000  71000105              set1    !PER3.0                                         ;[INF] 4, 2
-  762   762                      ; line   209 : 
-  763   763                      ; line   210 :     IICE = 0;                   /* IICA disable */
-  764   764                      $DGL    0,5
-  765   765 00004  71785005              clr1    !IICCTL01.7                                     ;[INF] 4, 2
-  766   766                      ; line   211 : 
-  767   767                      ; line   212 :     IICAMK = 1;                 /* INTIICA disable */
-  768   768                      $DGL    0,7
-  769   769 00008  713AD5                set1    MK2H.3                                          ;[INF] 3, 2
-  770   770                      ; line   213 :     IICAIF = 0;                 /* clear INTIICA interrupt flag 
-  771   771                      ;              */
-  772   772                      $DGL    0,8
-  773   773 0000B  713BD1                clr1    IF2H.3                                          ;[INF] 3, 2
-  774   774                      ; line   214 : 
-  775   775                      ; line   215 :     IICAPR0 = 1;                /* set INTIICA high priority */
-  776   776                      $DGL    0,10
-  777   777 0000E  713ADD                set1    PR12H.3                                         ;[INF] 3, 2
-  778   778                      ; line   216 :     IICAPR1 = 0;                /* set INTIICA high priority */
-  779   779                      $DGL    0,11
-  780   780 00011  713BD9                clr1    PR02H.3                                         ;[INF] 3, 2
-  781   781                      ; line   217 : 
-  782   782                      ; line   218 : #ifdef _MODEL_TEG2_
-  783   783                      ; line   219 :     P6 &= ~0x3;
-  784   784                      ; line   220 : #else
-  785   785                      ; line   221 :     P20 &= ~0x3;
-  786   786                      $DGL    0,16
-  787   787 00014  8F1005                mov     a,!P20                                          ;[INF] 3, 1
-  788   788 00017  5CFC                  and     a,#0FCH ; 252                                   ;[INF] 2, 1
-  789   789 00019  9F1005                mov     !P20,a                                          ;[INF] 3, 1
-  790   790                      ; line   222 : #endif
-  791   791                      ; line   223 : 
-  792   792                      ; line   224 :     SVA = IIC_C_SLAVEADDRESS;
-  793   793                      $DGL    0,19
-  794   794 0001C  CF54054A              mov     !SVA1,#04AH     ; 74                            ;[INF] 4, 1
-  795   795                      ; line   225 :     IICF = 0x01;
-  796   796                      $DGL    0,20
-  797   797 00020  E54205                oneb    !IICF1                                          ;[INF] 3, 1
-  798   798                      ; line   226 : 
-  799   799                      ; line   227 :     STCEN = 1;                  // リスタートの許可
-  800   800                      $DGL    0,22
-  801   801 00023  71104205              set1    !IICF1.1                                        ;[INF] 4, 2
-  802   802                      ; line   228 :     IICRSV = 1;                 // 通信予約をさせない:スレーブに
-  803   803                      ;              徹する
-  804   804                      $DGL    0,23
-  805   805 00027  71004205              set1    !IICF1.0                                        ;[INF] 4, 2
-  806   806                      ; line   229 : 
-  807   807                      ; line   230 :     SPIE = 0;                   // ストップコンディションでの割り
-  808   808                      ;              込みを禁止
-  809   809                      $DGL    0,25
-  810   810 0002B  71485005              clr1    !IICCTL01.4                                     ;[INF] 4, 2
-  811   811                      ; line   231 :     WTIM = 1;                   // 自動でACKを返した後clkをLに固
-  812   812                      ;              定する
-  813   813                      $DGL    0,26
-  814   814 0002F  71305005              set1    !IICCTL01.3                                     ;[INF] 4, 2
-  815   815                      ; line   232 :     ACKE = 1;                   //  ダメCPUは無視して次の通信をは
-  816   816                      ;              じめるかもしれないんで早くclkを開放しないといけない
-  817   817                      $DGL    0,27
-  818   818 00033  71205005              set1    !IICCTL01.2                                     ;[INF] 4, 2
-  819   819                      ; line   233 : 
-  820   820                      ; line   234 :     IICWH = 5;
-  821   821                      $DGL    0,29
-  822   822 00037  CF530505              mov     !IICWH1,#05H    ; 5                             ;[INF] 4, 1
-  823   823                      ; line   235 :     IICWL = 10;                 // L期間の長さ
-  824   824                      $DGL    0,30
-  825   825 0003B  CF52050A              mov     !IICWL1,#0AH    ; 10                            ;[INF] 4, 1
-  826   826                      ; line   236 : 
-  827   827                      ; line   237 :     SMC = 1;                    // 高速モード
-  828   828                      $DGL    0,32
-  829   829 0003F  71305105              set1    !IICCTL11.3                                     ;[INF] 4, 2
-  830   830                      ; line   238 :     DFC = 1;                    // デジタルフィルタon (@fast mod
-  831   831                      ;              e)
-  832   832                      $DGL    0,33
-  833   833 00043  71205105              set1    !IICCTL11.2                                     ;[INF] 4, 2
-  834   834                      ; line   239 : 
-  835   835                      ; line   240 :     IICAMK = 0;                 // 割り込みを許可
-  836   836                      $DGL    0,35
-  837   837 00047  713BD5                clr1    MK2H.3                                          ;[INF] 3, 2
-  838   838                      ; line   241 : 
-  839   839                      ; line   242 :     IICE = 1;
-  840   840                      $DGL    0,37
-  841   841 0004A  71705005              set1    !IICCTL01.7                                     ;[INF] 4, 2
-  842   842                      ; line   243 : 
-  843   843                      ; line   244 : #ifdef _MODEL_TEG2_
-  844   844                      ; line   245 :     PM6 &= ~0x3;                /* set clock pin for IICA */
-  845   845                      ; line   246 : #else
-  846   846                      ; line   247 :     PM20 &= ~0x3;                /* set clock pin for IICA */
-  847   847                      $DGL    0,42
-  848   848 0004E  8F1105                mov     a,!PM20                                         ;[INF] 3, 1
-  849   849 00051  5CFC                  and     a,#0FCH ; 252                                   ;[INF] 2, 1
-  850   850 00053  9F1105                mov     !PM20,a                                         ;[INF] 3, 1
-  851   851                      ; line   248 : #endif
-  852   852                      ; line   249 : }
-  853   853                      $DGL    0,44
-  854   854 00056                ??ef_IIC_ctr_Init:
-  855   855 00056  D7                    ret                                                     ;[INF] 1, 6
-  856   856 00057                ??ee_IIC_ctr_Init:
-  857   857                      ; line   250 : 
-  858   858                      ; line   251 : 
-  859   859                      ; line   252 : 
-  860   860                      ; line   253 : // ========================================================
-  861   861                      ; line   254 : void IIC_ctr_Stop( void )
-  862   862                      ; line   255 : {
-  863   863 00057                _IIC_ctr_Stop:
-  864   864                      $DGL    1,118
-  865   865 00057                ??bf_IIC_ctr_Stop:
-  866   866                      ; line   256 :     IICE = 0;                   /* IICA disable */
-  867   867                      $DGL    0,2
-  868   868 00057  71785005              clr1    !IICCTL01.7                                     ;[INF] 4, 2
-  869   869                      ; line   257 :     IICAEN = 0;
-  870   870                      $DGL    0,3
-  871   871 0005B  71080105              clr1    !PER3.0                                         ;[INF] 4, 2
-  872   872                      ; line   258 : }
-  873   873                      $DGL    0,4
-  874   874 0005F                ??ef_IIC_ctr_Stop:
-  875   875 0005F  D7                    ret                                                     ;[INF] 1, 6
-  876   876 00060                ??ee_IIC_ctr_Stop:
-  877   877                      
-  878   878 -----                @@CODEL CSEG
-  879   879                              END
-  880   880                      
-  881   881                      
-  882   882                      ; *** Code Information ***
-  883   883                      ;
-  884   884                      ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c
-  885   885                      ;
-  886   886                      ; $FUNC int_iic_ctr(65)
-  887   887                      ;       void=(void)
-  888   888                      ;       CODE SIZE= 355 bytes, CLOCK_SIZE= 278 clocks, STACK_SIZE= 28 bytes
-  889   889                      ;
-  890   890                      ; $CALL hosu_read_end(98)
-  891   891                      ;       void=(void)
-  892   892                      ;
-  893   893                      ; $CALL rtc_unlock(99)
-  894   894                      ;       void=(void)
-  895   895                      ;
-  896   896                      ; $CALL rtc_unlock(110)
-  897   897                      ;       void=(void)
-  898   898                      ;
-  899   899                      ; $CALL vreg_ctr_read(138)
-  900   900                      ;       bc=(int:ax)
-  901   901                      ;
-  902   902                      ; $CALL vreg_ctr_after_read(179)
-  903   903                      ;       void=(int:ax)
-  904   904                      ;
-  905   905                      ; $CALL vreg_ctr_write(184)
-  906   906                      ;       void=(int:ax, int:[sp+4])
-  907   907                      ;
-  908   908                      ; $CALL vreg_ctr_read(196)
-  909   909                      ;       bc=(int:ax)
-  910   910                      ;
-  911   911                      ; $FUNC IIC_ctr_Init(206)
-  912   912                      ;       void=(void)
-  913   913                      ;       CODE SIZE= 87 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
-  914   914                      ;
-  915   915                      ; $FUNC IIC_ctr_Stop(255)
-  916   916                      ;       void=(void)
-  917   917                      ;       CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
-  918   918                      
-  919   919                      ; Target chip : uPD79F0104
-  920   920                      ; Device file : E1.00b
-
-Segment informations:
-
-ADRS  LEN      NAME
-
-00000 00000H.0 @@BITS
-00000 00030H   @@CNST
-00000 00002H   @@R_INIT
-00000 00002H   @@INIT
-00000 00004H   @@DATA
-00000 00000H   @@R_INIS
-00000 00000H   @@INIS
-00000 00000H   @@DATS
-00000 00000H   @@CNSTL
-00000 00000H   @@RLINIT
-00000 00000H   @@INITL
-00000 00000H   @@DATAL
-00000 00000H   @@CALT
-00000 00163H   @@BASE
-00000 00060H   ROM_CODE
-00000 00000H   @@CODEL
-
- Target chip : uPD79F0104
- Device file : E1.00b
-Assembly complete,     0 error(s) and     0 warning(s) found. (    0)
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_ctr.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.c
@ -1,734 +0,0 @@
-/* ========================================================
-  簡易I2C（内蔵ペリフェラル使用）通信
-    de JHL 藤田＠開技
-    '09 Feb -
- ======================================================== */
-#pragma sfr
-#pragma di
-#pragma ei
-#pragma nop
-#pragma inline                  // memcpy()をインライン展開する
-
-#include "incs.h"
-#include "i2c_mcu.h"
-
-
-
-// ========================================================
-// レジスタのビット名
-// プリフィックスbだが、一部のビット名がレジスタ名にかぶるため...
-// SMR0n
-#define bCKS0    ( 1 << 15 )
-#define bCCS0    ( 1 << 14 )
-#define bSTS0    ( 1 << 8 )
-#define bSIS0    ( 1 << 6 )
-#define bMD0n2   ( 1 << 2 )
-#define bMD0n1   ( 1 << 1 )
-#define bMD0n0   ( 1 << 0 )
-#define bSMR0n_FIXEDBIT  ( 1 << 5 )
-
-// SSR0n
-#define bit_TSF0   6
-#define PEF0       ( 1 << 1 )
-
-// SIR0n
-#define PECT0      ( 1 << 1 )
-
-// SCR0n
-#define TXE0       ( 1 << 15 )
-#define RXE0       ( 1 << 14 )
-#define SLC02      4
-#define DLS02      0
-#define TSF0       ( 1 << 6 )
-
-// SOn
-#define TAUS_MASK  0b0000101100001011;
-
-// DMCn
-#define DRS        ( 1 << 6 )
-
-
-
-
-// ========================================================
-static void iic_mcu_send_st(  );
-static void iic_mcu_send_re_st(  );
-static void iic_mcu_send_sp(  );
-static err iic_mcu_send_a_byte( u8 );
-static err iic_mcu_call_slave( u8 slave );
-
-
-
-// ========================================================
-bit     iic_mcu_wo_dma;
-volatile bit iic_mcu_busy;
-volatile bit iic_mcu_initialized;
-
-
-u8      iic_send_work[4];
-u8     *p_iic_send_wo_dma_dat;
-u8      iic_send_wo_dma_len;
-
-u8      iic_mcu_bus_status;     // 一文字リードの時はデータを返す。
-                                // ステータスが必要ならこっちを呼んで
-
-void nop8()
-{
-}
-
-
-
-/* ========================================================
-  スレーブからの 『1文字』 リード
-  返値がデータそのものです。
-  エラー判定ができません。
- ======================================================== */
-u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs )
-{
-    u8      dat;
-
-    if( iic_mcu_initialized == 0 )
-    {
-#ifdef _debug_
-        iic_mcu_start(  );
-#else
-        while( 1 )
-        {
-        }
-#endif
-    }
-
-    while( iic_mcu_busy )
-    {
-        NOP(  );
-    }
-    iic_mcu_busy = 1;
-
-    iic_mcu_bus_status = ERR_OK;
-
-    // スタートコンディションとスレーブの呼び出し、レジスタアドレスの送信
-    if( iic_mcu_call_slave( SLA ) != 0 )
-    {
-        iic_mcu_bus_status = ERR_NOSLAVE;
-        iic_mcu_busy = 0;
-        return ( 0 );
-    }
-
-    // レジスタアドレスの送信
-    iic_mcu_send_a_byte( adrs );        // 終わるまで帰ってこない
-    // if( err != ERR_SUCCESS )～
-
-    // データ受信 //
-    iic_mcu_send_re_st(  );     // リスタートコンディション
-    iic_mcu_send_a_byte( SLA | 0x01 );  // 送信完了まで戻ってきません。
-
-    ST0 = 0x0004;               // 受信モードに設定を変えるのでロジック停止
-    SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02;     // 受信設定
-    SS0 = 0x0004;               // 通信待機
-
-    SOE0 = 0x0000;              // 1バイト送信なので、最後のNAKを送る
-    IICIF10 = 0;
-    SIO10 = 0xFF;               // ダミーデータを書くと受信開始
-
-    while( IICIF10 == 0 )
-    {                           // 受信完了待ち
-        ;
-    }
-    dat = SIO10;
-
-    iic_mcu_send_sp(  );
-    IICIF10 = 0;                // 後を濁さないこと
-    iic_mcu_busy = 0;
-    return ( dat );
-}
-
-
-
-/* ========================================================
-  スレーブからのリード
-  0 正常終了
-  1 スレーブが応答しない
-  2 バスが誰かに占有されていてタイムアウト
-  3 意味不明エラー
-  【注】
-  スレーブがウェイトコンディションを出すことは禁止です。
-  その場合でもエラー検出などできません
- ======================================================== */
-err iic_mcu_read( u8 slave, u8 adrs, u8 len, u8 * dest )
-{
-
-//*
-    // 使用中なら待つ
-    if( iic_mcu_initialized == 0 )
-    {
-#ifdef _debug_
-        iic_mcu_start(  );
-#else
-        while( 1 )
-        {
-        }
-#endif
-    }
-    while( iic_mcu_busy )
-    {
-        NOP(  );
-    }
-/*/
-  // 使用中なら帰る
-  if( iic_mcu_initialized == 0 ){
-    return(0x80);
-  }
-  if( iic_mcu_busy != 0 ){
-    return( 3 );
-  }
-//*/
-
-    iic_mcu_busy = 1;
-    // スタートコンディションとスレーブの呼び出し、レジスタアドレスの送信
-    if( iic_mcu_call_slave( slave ) != 0 )
-    {
-        iic_mcu_busy = 0;
-        return ( ERR_NOSLAVE );
-    }
-
-    // レジスタアドレスの送信
-    iic_mcu_send_a_byte( adrs );        // 終わるまで帰ってこない
-    // if( err != ERR_SUCCESS )～
-
-    // データ受信 //
-    iic_mcu_send_re_st(  );     // リスタートコンディション
-    iic_mcu_send_a_byte( slave | 0x01 );        // 送信完了まで戻ってきません。
-
-    // データ受信
-    ST0 = 0x0004;               // 受信モードに設定を変えるのでロジック停止
-    SCR02 = RXE0 | 1 << SLC02 | 7 << DLS02;     // 受信設定
-    SS0 = 0x0004;               // 通信待機
-
-    do
-    {
-        if( len == 1 )
-        {
-            SOE0 = 0x0000;      // 最後のNAK
-        }
-        IICIF10 = 0;
-        SIO10 = 0xFF;           // ダミーデータを書くと受信開始
-        while( IICIF10 == 0 )
-        {                       // 受信完了待ち
-            ;
-        }
-        *dest = SIO10;
-        dest++;
-        len--;
-    }
-    while( len != 0 );
-
-    iic_mcu_send_sp(  );
-
-    IICIF10 = 0;
-    iic_mcu_busy = 0;
-    return ( ERR_SUCCESS );
-}
-
-
-
-
-/* ========================================================
-  スレーブへ 『１バイト』 ライト
-  前の転送が終わるのを待って、ライトします。
-  返値　iic_mcu_write　に同じ
-
- ======================================================== */
-err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat )
-{
-
-    if( iic_mcu_initialized == 0 )
-    {
-#ifdef _debug_
-        iic_mcu_start(  );
-#else
-        while( 1 )
-        {
-        }
-#endif
-    }
-    while( iic_mcu_busy )
-    {
-        NOP(  );
-    }
-    iic_mcu_busy = 1;
-#if 0
-    temp = dat;
-    return ( iic_mcu_write( SLA, adrs, 1, &temp ) );
-}
-#else
-    // スタートコンディションとスレーブの呼び出し...
-    IICMK10 = 1;
-    if( iic_mcu_call_slave( SLA ) != 0 )
-    {
-        iic_mcu_busy = 0;
-        return ( ERR_NAK );
-    }
-    iic_mcu_send_a_byte( adrs );
-    iic_mcu_send_a_byte( dat );
-    iic_mcu_send_sp(  );
-    iic_mcu_busy = 0;
-    return ( ERR_SUCCESS );
-#endif
-}
-
-
-
-/* ========================================================
-  スレーブへライト
- レジスタ adrs を先頭に、
- *strから
- len文字書きます。
-
-   0 正常終了
-   1 スレーブが応答しない
-   2 バスが誰かに占有されていてタイムアウト
-   3 前に指示された通信がまだ終わってない
-  【注】
-  スレーブがウェイトコンディションを出すことは禁止です。
-  その場合でもエラー検出などできません
-  DMA1を使用します。
- ******************************************************************************/
-err iic_mcu_write( u8 slave, u8 adrs, u8 len, void * src )
-{
-//*
-    // 使用中なら待つ
-    if( iic_mcu_initialized == 0 )
-    {
-#ifdef _debug_
-        iic_mcu_start(  );
-#else
-        while( 1 )
-        {
-        }
-#endif
-    }
-    while( iic_mcu_busy )
-    {
-        NOP(  );
-    }
-/*/
-  // 使用中なら帰る
-  if( iic_mcu_initialized == 0 ){
-    return(0x80);
-  }
-  if( iic_mcu_busy != 0 ){
-    return( 3 );
-  }
-//*/
-    iic_mcu_busy = 1;
-    // スタートコンディションとスレーブの呼び出し...
-    IICMK10 = 1;
-    IICIF10 = 0;
-    if( iic_mcu_call_slave( slave ) != 0 )
-    {
-        iic_mcu_busy = 0;
-        EI(  );
-        return ( ERR_NAK );
-    }
-
-    IICIF10 = 0;
-    if( !iic_mcu_wo_dma )
-    {
-        // DMAを使用する（通常）
-
-        // レジスタアドレスを送り、データの準備
-        memcpy( iic_send_work, src, 4 );        //バッファとして4バイトしか用意して無いため。
-        // DMAセット
-        while( DST1 )
-        {;
-        }
-
-        DEN1 = 1;
-        DSA1 = ( u8 ) ( &SIO10 );
-        DRA1 = ( u16 ) iic_send_work;
-        DBC1 = len;
-        DMC1 = DRS | 8;         // RAM -> SFR, 8bit, IRQ, IIC10
-
-        DMAIF1 = 0;
-        DMAMK1 = 0;
-        DST1 = 1;
-
-        SIO10 = adrs;           // 書きっぱなし！ 割り込みが発生してDMAスタート
-        // 残りは割り込みルーチン内で
-    }
-    else
-    {
-        // DMAを使用しない //
-
-        // レジスタアドレスの送信
-        SIO10 = adrs;
-
-        IICMK10 = 0;
-        iic_send_wo_dma_len = len;
-        p_iic_send_wo_dma_dat = src;
-        // 残りは割り込みルーチン内で
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-
-/* ========================================================
-  DMA１転送終了割り込み
-  IIC_mcu の送信完了コールバック関数のようなもの
-  注：DMA転送が終わっただけで、I2Cの転送は終わってません
-　  割り込み中などで、DMA1の処理が遅延した場合、
-  IIC10の割り込みの準備ができずに、割り込みを発生させられなくなる
-  恐れがあります。また、回避方法も特にありません。
-  　そのため、DMA仕様の差異は、最後のバイトは送信完了を
-  フラグのポーリングで確認します。
- ======================================================== */
-__interrupt void int_dma1(  )
-{
-    u16     i = 0;
-
-    EI();
-
-    DMAMK1 = 1;
-    DEN1 = 0;
-    while( ( SSR02L & TSF0 ) != 0 )
-    {
-        if( ++i == 0 )  // タイムアウト？
-        {
-            break;
-        }
-    }
-
-//  iic_mcu_send_sp();  // ISR中で外の関数を呼ぶのは都合が悪いので展開
-    {
-        ST0 = 0x0004;
-        SOE0 = 0;               // 受信の時はもっと前に「も」設定してる。(NACK出力)
-        SO0 = 0x0000 | TAUS_MASK;       // SCL
-        nop8();
-/*
-    NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-        SO0 = 0x0400 | TAUS_MASK;       // SCL
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-        SO0 = 0x0404 | TAUS_MASK;
-    }
-    IICMK10 = 1;
-    iic_mcu_busy = 0;
-}
-
-
-
-/* ========================================================
-  IIC MCUのバイト送出完了割り込み
-  ※DMA使用時は使用されません。
-  　他の割り込み処理中でDMAの割り込みにすぐ飛ばない場合、
-  　IIC割り込みのセットが間に合わず困ることがあります。
- ======================================================== */
-__interrupt void int_iic10(  )
-{
-    EI();
-    if( iic_send_wo_dma_len != 0 )
-    {
-        SIO10 = *p_iic_send_wo_dma_dat;
-        p_iic_send_wo_dma_dat++;
-        iic_send_wo_dma_len--;
-        return;
-    }
-
-    // 最後のバイト送信完了
-    IICMK10 = 1;
-//  iic_mcu_send_sp();    // ISR中で外の関数を呼ぶのは都合が悪いので展開
-    {
-        ST0 = 0x0004;
-        SOE0 = 0;               // 受信の時はもっと前に「も」設定してる。(NACK出力)
-        SO0 = 0x0000 | TAUS_MASK;       // SCL
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-        SO0 = 0x0400 | TAUS_MASK;       // SCL
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-        SO0 = 0x0404 | TAUS_MASK;
-    }
-    iic_mcu_wo_dma = 0;
-    iic_mcu_busy = 0;
-}
-
-
-
-/* ========================================================
-  スレーブの呼び出し
-　スレーブアドレスを呼んで、ACKの確認。
-  ACK　→　　　　　　　　　　　　　　　　　返：0
-　NACK →　ストップコンディションを出す。　返：1
- ======================================================== */
-static err iic_mcu_call_slave( u8 slave )
-{
-    iic_mcu_send_st(  );
-
-//  SIR02 = SSR02;              // NAKエラーのフラグクリア
-    if( iic_mcu_send_a_byte( slave ) != ERR_SUCCESS )
-    {
-        iic_mcu_send_sp(  );
-        return ( ERR_NAK );     // 指定のスレーブがいない / busy
-    }
-
-    return ( ERR_SUCCESS );
-}
-
-
-
-/* ========================================================
-  ほんとに１バイト書くのみ
-  書き終わるまで帰りません
- ======================================================== */
-static err iic_mcu_send_a_byte( u8 dat )
-{
-    IICMK10 = 1;
-    IICIF10 = 0;
-    SIO10 = dat;
-    while( IICIF10 == 0 )
-    {
-        NOP(  );
-    }                           // 通信中
-    if( SSR02 != 0 )
-    {
-        SIR02 = SSR02;
-        return ( ERR_NAK );
-    }
-    return ( ERR_SUCCESS );
-}
-
-
-
-/* ========================================================
-  スタートコンディションを発行
-  ソフトウェア制御
- ======================================================== */
-static void iic_mcu_send_st(  )
-{
-    SO0 &= ~0x0004;             // SDA
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    SO0 &= ~0x0400;             // SCL
-    SOE0 = 0x0004;              // ハード制御へ
-
-    SCR02 = TXE0 | 1 << SLC02 | 7 << DLS02;     // 送信許可、データは８ビット単位
-    SS0 = 0x0004;               // 通信待機
-}
-
-
-
-/* ========================================================
-  リスタート発行
- ======================================================== */
-static void iic_mcu_send_re_st(  )
-{
-    ST0 |= 0x0004;
-    SO0 |= 0x0400 | TAUS_MASK;  // ( SDA = H ), SCL -> H
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    SOE0 &= ~0x0004;            // ( SCL = H ), SDA -> L
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    iic_mcu_send_st(  );
-}
-
-
-
-/* ========================================================
-  ストップコンディション発行
-  この前に、「最後のバイトの送受信」の時に前準備が必要です。
- ======================================================== */
-static void iic_mcu_send_sp(  )
-{
-    ST0 = 0x0004;
-    SOE0 = 0;                   // 受信の時はもっと前に「も」設定してる。(NACK出力)
-    SO0 = 0x0000 | TAUS_MASK;   // SCL
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    SO0 = 0x0400 | TAUS_MASK;   // SCL
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    SO0 = 0x0404 | TAUS_MASK;
-}
-
-
-
-
-/* ========================================================
-  ペリフェラルモジュールの初期化
- ======================================================== */
-void iic_mcu_start(  )
-{
-    DST1 = 0;
-    NOP(  );                    // 2clkもしくは、DSTn==0をポーリング
-    NOP(  );
-    DEN1 = 0;
-    I2C_PU_on();
-    SAU0EN = 1;
-        nop8();
-/*
-        NOP(  );
-        NOP(  );
-        NOP(  );
-        NOP(  );
-#ifdef _OVERCLOCK_
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-    NOP(  );
-#endif
-*/
-    SPS0 = 0x0000;              // シリアルユニットのクロック０。(8M/2)/1
-    SMR02 = bSMR0n_FIXEDBIT | bMD0n2;	// 簡易I2Cに設定
-#ifdef _OVERCLOCK_
-    SDR02 = 12 << 9;             // ボーレート設定 (8M/2)/1/(x+1)/2
-#else
-    SDR02 = 5 << 9;             // ボーレート設定 (8M/2)/1/(x+1)/2
-#endif
-
-    SO0 = 0x0404 | TAUS_MASK;   // 最初はHH
-    iic_mcu_busy = 0;
-    iic_mcu_wo_dma = 0;
-
-
-    // バスのリセット
-    IICIF10 = 0;
-    IICMK10 = 1;
-
-    iic_mcu_send_st();
-
-    SIO10 = 0xFF;
-    while( IICIF10 == 0 ){}                           // 通信中
-    iic_mcu_send_sp();
-
-    SIR02 = SSR02;
-
-    iic_mcu_initialized = 1;
-}
-
-
-
-/* ========================================================
-  モジュールの停止
-  再度使うときは初期化が必要
- ======================================================== */
-void iic_mcu_stop(  )
-{
-    while( iic_mcu_busy )
-    {;
-    }                           // DMA動作中はもう少し待つ
-    iic_mcu_send_re_st(  );     // SCL,SDAをLLにする
-    I2C_PU_off();
-    SAU0EN = 0;
-    iic_mcu_initialized = 0;
-}
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.h
@ -1,34 +0,0 @@
-#ifndef __ic2_mcu__
-#define __ic2_mcu__
-
-
-// ========================================================
-#define ERR_OK  0
-#define ERR_NAK 1
-#define ERR_NOSLAVE 2
-
-
-
-// ========================================================
-extern volatile bit iic_mcu_busy;
-extern bit iic_mcu_wo_dma;
-
-extern u8 iic_mcu_bus_status;
-
-
-
-// ========================================================
-err iic_mcu_read( u8 SLA, u8 adrs, u8 len, u8 * dest );
-u8 iic_mcu_read_a_byte( u8 SLA, u8 adrs );
-
-err iic_mcu_write( u8 SLA, u8 adrs, u8 len, void * src );
-err iic_mcu_write_a_byte( u8 SLA, u8 adrs, u8 dat );
-
-// ↓その通信が完了したら解除されます。
-#define iic_mcu_set_wo_dma()           { while( iic_mcu_busy ){;} iic_mcu_wo_dma = 1; }
-
-void iic_mcu_start(  );
-void iic_mcu_stop(  );
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_mcu.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.c
@ -1,206 +0,0 @@
-#pragma sfr                     /* 特殊機能レジスタ使用 */
-
-
-
-/*============================================================================*/
-#include "incs.h"
-#include "i2c_twl_defs.h"
-
-
-extern u8 vreg_twl[];
-
-#ifdef _MCU_BSR_
-//#ifdef _MODEL_TS0_ || _MODEL_WM0_
-
-// ワーキングモデルはI2Cが逆
-#define ACKD       ACKD0
-#define ACKE       ACKE0
-#define COI        COI0
-#define IICAEN     IICA0EN
-#define IICRSV     IICRSV0
-#define IICA       IICA0
-#define IICAIF     IICAIF0
-#define IICAMK     IICAMK0
-#define IICAPR0    IICAPR00
-#define IICAPR1    IICAPR10
-#define IICCTL0    IICCTL00
-#define IICE       IICE0
-#define IICF       IICF0
-#define IICS       IICS0
-#define IICWH      IICWH0
-#define IICWL      IICWL0
-#define LREL       LREL0
-#define SPD        SPD0
-#define SPIE       SPIE0
-#define STCEN      STCEN0
-#define STD        STD0
-#define SVA        SVA0
-#define WREL       WREL0
-#define WTIM       WTIM0
-#define SMC        SMC0
-
-#endif
-
-#ifndef _MCU_BSR_
-
-// ke3の時はダミー関数
-void IIC_twl_Stop( void )
-{
-}
-void IIC_twl_Init( void )
-{
-}
-#else
-
-
-/*============================================================================*/
-u8      vreg_adrs;
-u8      pre_dat;
-
-
-u16     tot;
-
-
-// 注！　↓はマクロなので、returnはメインループに戻ります。
-#define wait_next {                                    \
-    tot = 0;                                             \
-  while( IICAIF != 1 ){                                \
-    if( SPD ){                                         \
-      LREL = 1;                                        \
-      return;                                          \
-    }                                                  \
-    tot++;                                             \
-    if( tot == 0 ){                                    \
-      LREL = 1;                                        \
-      return;                                          \
-    }                                                  \
-  }                                                    \
-}
-
-
-__interrupt void int_iic_twl(  )
-{
-    u8      temp;
-    u16     tot;
-
-//  WDT_Restart();
-    // フラグ１回目    スレーブアドレス,R/W
-/* COI != 1 なら、割り込みはいらない
-  if( COI != 1 ){               // 被呼び出し？
-    LREL = 1;                   // 呼ばれたのは他のID
-    return;
-  }else{
-    ACKE0 = 1;                // 自動でackを返すようにする
-    WREL = 1;                 // ウェイト解除して次のバイトを待つ
-  }
-  */
-    WREL = 1;                   // ウェイト解除して次のバイトを待つ
-    wait_next;                  // １バイト受信完了を待つ
-
-    // ２回目           R/W レジスタアドレス
-    temp = IICA;
-    IICAIF = 0;
-    WREL = 1;
-
-    vreg_adrs = adrs_table_twl_ext2int( temp );
-
-    // ３回目
-    // スタートコンディションか、データ受信完了フラグ待ち
-
-    while( 1 )
-    {
-        u8 my_iics = IICS;
-
-        if( my_iics & 0x01 )    // SPD
-        {                       // 強制終了
-            LREL = 1;
-            return;
-        }
-        else if( my_iics & 0x02 )  // ( STD && !SPD )
-        {
-            // 送信 // (スタートコンディション検出)
-            pre_dat = vreg_twl_read( vreg_adrs );       // mcu内部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除
-
-            // 自局をRで呼ばれるのを待つ
-            wait_next;
-            IICAIF = 0;
-            if( COI != 1 )
-            {                   // 被呼び出し？
-                LREL = 1;       // 呼ばれたのは他のID（あれ？）
-                return;
-            }
-            IICA = pre_dat;     // データを送る。ウェイトも解除される。
-
-            wait_next;
-            // ４回目。(送信データ後の、ACK/NACK後)　どうしても発生してしまう。
-            IICAIF = 0;         // おしまい
-            LREL = 1;
-            return;
-        }
-        else if( IICAIF && (( my_iics & 0x03 ) == 0 ))   // !STD && !SPD )
-        {
-            // 受信 //
-            IICAIF = 0;
-            temp = IICA;
-            WREL = 1;
-
-            // 通常アクセス(ライト) //
-            LREL = 1;           // スタートコンディション待ちへ(連続書き込み未対応のため)
-            vreg_twl_write( vreg_adrs, temp );
-            return;             // 受信おしまい //
-        }
-    }
-}
-
-
-
-/*****************************************************/
-void IIC_twl_Init( void )
-{
-
-    IICAEN = 1;
-
-    IICE = 0;                   /* IICA disable */
-
-    IICAMK = 1;                 /* INTIICA disable */
-    IICAIF = 0;                 /* clear INTIICA interrupt flag */
-
-    IICAPR0 = 0;                /* set INTIICA high priority */
-    IICAPR1 = 0;                /* set INTIICA high priority */
-    P20 &= ~0x3;
-
-    SVA = IIC_T_SLAVEADDRESS;
-    IICF = 0x01;
-
-    STCEN = 1;                  // リスタートの許可
-    IICRSV = 1;                 // 通信予約をさせない:スレーブに徹する
-
-    SPIE = 0;                   // ストップコンディションでの割り込みを禁止
-    WTIM = 1;                   // 自動でACKを返した後clkをLに固定する
-    ACKE = 1;                   //  ダメCPUは無視して次の通信をはじめるかもしれないんで早くclkを開放しないといけない
-
-    IICWH = 5;
-    IICWL = 10;                 // L期間の長さ（？）
-
-    SMC = 1;
-
-    IICAMK = 0;                 // 割り込みを許可
-
-    IICE = 1;
-
-    PM20 &= ~0x3;               /* set clock pin for IICA */
-
-    LREL = 1;
-}
-
-
-
-//****************************************************************************
-void IIC_twl_Stop( void )
-{
-    IICE = 0;                   /* IICA disable */
-    IICAEN = 0;
-}
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.h
@ -1,7 +0,0 @@
-#ifndef _iic_twl_
-#define _iic_twl_
-
-void IIC_twl_Init( void );
-void IIC_twl_Stop( void );
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.prn
@ -1,797 +0,0 @@
-
-
-
-78K0R Assembler W1.31                                                                                    Date:13 Jun 2010 Page:   1
-
-
-
-Command:  -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\i2c_twl.asm
-Para-file:
-In-file:  inter_asm\i2c_twl.asm
-Obj-file: i2c_twl.rel
-Prn-file: i2c_twl.prn
-
-      Assemble list
-
- ALNO  STNO ADRS   OBJECT   M I  SOURCE STATEMENT
-
-    1     1                      ; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24
-    2     2                      
-    3     3                      ; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-    4     4                      ;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-    5     5                      ;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c
-    6     6                      ; In-file   : i2c_twl.c
-    7     7                      ; Asm-file  : inter_asm\i2c_twl.asm
-    8     8                      ; Para-file : 
-    9     9                      
-   10    10                      $PROCESSOR(9F0104)
-   11    11                      $DEBUG
-   12    12                      $NODEBUGA
-   13    13                      $KANJICODE SJIS
-   14    14                      $TOL_INF        03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-   15    15                      
-   16    16                      $DGS    FIL_NAM, .file,         06FH,   0FFFEH, 03FH,   067H,   01H,    00H
-   17    17                      $DGS    AUX_FIL, i2c_twl.c
-   18    18                      $DGS    MOD_NAM, i2c_twl,       00H,    0FFFEH, 00H,    077H,   00H,    00H
-   19    19                      $DGS    SEC_NAM, @@BITS,        U,      U,      00H,    078H,   00H,    00H
-   20    20                      $DGS    SEC_NAM, @@CNST,        U,      U,      00H,    078H,   00H,    00H
-   21    21                      $DGS    SEC_NAM, @@R_INIT,      U,      U,      00H,    078H,   00H,    00H
-   22    22                      $DGS    SEC_NAM, @@INIT,        U,      U,      00H,    078H,   00H,    00H
-   23    23                      $DGS    SEC_NAM, @@DATA,        U,      U,      00H,    078H,   00H,    00H
-   24    24                      $DGS    SEC_NAM, @@R_INIS,      U,      U,      00H,    078H,   00H,    00H
-   25    25                      $DGS    SEC_NAM, @@INIS,        U,      U,      00H,    078H,   00H,    00H
-   26    26                      $DGS    SEC_NAM, @@DATS,        U,      U,      00H,    078H,   00H,    00H
-   27    27                      $DGS    SEC_NAM, @@CNSTL,       U,      U,      00H,    078H,   00H,    00H
-   28    28                      $DGS    SEC_NAM, @@RLINIT,      U,      U,      00H,    078H,   00H,    00H
-   29    29                      $DGS    SEC_NAM, @@INITL,       U,      U,      00H,    078H,   00H,    00H
-   30    30                      $DGS    SEC_NAM, @@DATAL,       U,      U,      00H,    078H,   00H,    00H
-   31    31                      $DGS    SEC_NAM, @@CALT,        U,      U,      00H,    078H,   00H,    00H
-   32    32                      $DGS    SEC_NAM, ROM_CODE,      U,      U,      00H,    078H,   00H,    00H
-   33    33                      $DGS    SEC_NAM, @@CODEL,       U,      U,      00H,    078H,   00H,    00H
-   34    34                      $DGS    SEC_NAM, @@BASE,        U,      U,      00H,    078H,   00H,    00H
-   35    35                      $DGS    STA_SYM, _lpf_coeff,    U,      U,      05002H, 03H,    01H,    03H
-   36    36                      $DGS    AUX_STR, 00H,           00H,    02FH,   02FH,   00H,    00H,    00H,    00H
-   37    37                      $DGS    GLV_SYM, _int_iic_twl,  U,      U,      0E001H, 026H,   01H,    02H
-   38    38                      $DGS    AUX_FUN, 00H,           U,      U,      063H,   00H,    00H
-   39    39                      $DGS    BEG_FUN, ??bf_int_iic_twl,      U,      U,      00H,    065H,   01H,    00H
-   40    40                      $DGS    AUX_BEG, 052H,          01CH,   01BH
-   41    41                      $DGS    AUT_VAR, _temp,         05H,    0FFFFH, 0CH,    01H,    00H,    00H
-   42    42                      $DGS    AUT_VAR, _tot,          02H,    0FFFFH, 0DH,    01H,    00H,    00H
-   43    43                      $DGS    BEG_BLK, ??bb00_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   44    44                      $DGS    AUX_BEG, 011H,          00H,    01DH
-   45    45                      $DGS    BEG_BLK, ??bb01_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   46    46                      $DGS    AUX_BEG, 011H,          00H,    01FH
-   47    47                      $DGS    BEG_BLK, ??bb02_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   48    48                      $DGS    AUX_BEG, 011H,          00H,    023H
-   49    49                      $DGS    END_BLK, ??eb02_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   50    50                      $DGS    AUX_END, 011H
-   51    51                      $DGS    BEG_BLK, ??bb03_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   52    52                      $DGS    AUX_BEG, 011H,          00H,    02BH
-   53    53                      $DGS    END_BLK, ??eb03_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   54    54                      $DGS    AUX_END, 011H
-   55    55                      $DGS    END_BLK, ??eb01_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   56    56                      $DGS    AUX_END, 011H
-   57    57                      $DGS    END_BLK, ??eb00_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   58    58                      $DGS    AUX_END, 011H
-   59    59                      $DGS    BEG_BLK, ??bb04_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   60    60                      $DGS    AUX_BEG, 01EH,          00H,    02FH
-   61    61                      $DGS    AUT_VAR, _my_iics,      01H,    0FFFFH, 0CH,    01H,    01H,    00H
-   62    62                      $DGS    AUX_STR, 00H,           01FH,   01H,    00H,    00H,    00H,    00H,    00H
-   63    63                      $DGS    BEG_BLK, ??bb05_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   64    64                      $DGS    AUX_BEG, 022H,          00H,    033H
-   65    65                      $DGS    END_BLK, ??eb05_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   66    66                      $DGS    AUX_END, 025H
-   67    67                      $DGS    BEG_BLK, ??bb06_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   68    68                      $DGS    AUX_BEG, 027H,          00H,    035H
-   69    69                      $DGS    BEG_BLK, ??bb07_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   70    70                      $DGS    AUX_BEG, 02CH,          00H,    037H
-   71    71                      $DGS    BEG_BLK, ??bb08_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   72    72                      $DGS    AUX_BEG, 02CH,          00H,    039H
-   73    73                      $DGS    BEG_BLK, ??bb09_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   74    74                      $DGS    AUX_BEG, 02CH,          00H,    03DH
-   75    75                      $DGS    END_BLK, ??eb09_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   76    76                      $DGS    AUX_END, 02CH
-   77    77                      $DGS    BEG_BLK, ??bb0A_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   78    78                      $DGS    AUX_BEG, 02CH,          00H,    045H
-   79    79                      $DGS    END_BLK, ??eb0A_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   80    80                      $DGS    AUX_END, 02CH
-   81    81                      $DGS    END_BLK, ??eb08_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   82    82                      $DGS    AUX_END, 02CH
-   83    83                      $DGS    END_BLK, ??eb07_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   84    84                      $DGS    AUX_END, 02CH
-   85    85                      $DGS    BEG_BLK, ??bb0B_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   86    86                      $DGS    AUX_BEG, 02FH,          00H,    049H
-   87    87                      $DGS    END_BLK, ??eb0B_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   88    88                      $DGS    AUX_END, 032H
-   89    89                      $DGS    BEG_BLK, ??bb0C_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   90    90                      $DGS    AUX_BEG, 035H,          00H,    04BH
-   91    91                      $DGS    BEG_BLK, ??bb0D_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   92    92                      $DGS    AUX_BEG, 035H,          00H,    04DH
-   93    93                      $DGS    BEG_BLK, ??bb0E_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   94    94                      $DGS    AUX_BEG, 035H,          00H,    051H
-   95    95                      $DGS    END_BLK, ??eb0E_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   96    96                      $DGS    AUX_END, 035H
-   97    97                      $DGS    BEG_BLK, ??bb0F_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-   98    98                      $DGS    AUX_BEG, 035H,          00H,    05BH
-   99    99                      $DGS    END_BLK, ??eb0F_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  100   100                      $DGS    AUX_END, 035H
-  101   101                      $DGS    END_BLK, ??eb0D_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  102   102                      $DGS    AUX_END, 035H
-  103   103                      $DGS    END_BLK, ??eb0C_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  104   104                      $DGS    AUX_END, 035H
-  105   105                      $DGS    END_BLK, ??eb06_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  106   106                      $DGS    AUX_END, 03AH
-  107   107                      $DGS    BEG_BLK, ??bb10_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  108   108                      $DGS    AUX_BEG, 03CH,          00H,    00H
-  109   109                      $DGS    END_BLK, ??eb10_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  110   110                      $DGS    AUX_END, 046H
-  111   111                      $DGS    END_BLK, ??eb04_int_iic_twl,    U,      U,      00H,    064H,   01H,    00H
-  112   112                      $DGS    AUX_END, 047H
-  113   113                      $DGS    END_FUN, ??ef_int_iic_twl,      U,      U,      00H,    065H,   01H,    00H
-  114   114                      $DGS    AUX_END, 048H
-  115   115                      $DGS    GLV_SYM, _IIC_twl_Init, U,      U,      01H,    026H,   01H,    02H
-  116   116                      $DGS    AUX_FUN, 00H,           U,      U,      069H,   00H,    00H
-  117   117                      $DGS    BEG_FUN, ??bf_IIC_twl_Init,     U,      U,      00H,    065H,   01H,    00H
-  118   118                      $DGS    AUX_BEG, 09FH,          00H,    069H
-  119   119                      $DGS    END_FUN, ??ef_IIC_twl_Init,     U,      U,      00H,    065H,   01H,    00H
-  120   120                      $DGS    AUX_END, 024H
-  121   121                      $DGS    GLV_SYM, _IIC_twl_Stop, U,      U,      01H,    026H,   01H,    02H
-  122   122                      $DGS    AUX_FUN, 00H,           U,      U,      06FH,   00H,    00H
-  123   123                      $DGS    BEG_FUN, ??bf_IIC_twl_Stop,     U,      U,      00H,    065H,   01H,    00H
-  124   124                      $DGS    AUX_BEG, 0C8H,          00H,    06FH
-  125   125                      $DGS    END_FUN, ??ef_IIC_twl_Stop,     U,      U,      00H,    065H,   01H,    00H
-  126   126                      $DGS    AUX_END, 04H
-  127   127                      $DGS    GLV_SYM, _vreg_adrs,    U,      U,      0CH,    026H,   00H,    00H
-  128   128                      $DGS    GLV_SYM, _pre_dat,      U,      U,      0CH,    026H,   00H,    00H
-  129   129                      $DGS    GLV_SYM, _tot,          U,      U,      0DH,    026H,   00H,    00H
-  130   130                      $DGS    GLV_SYM, _@SEGAX,       U,      U,      00H,    02H,    00H,    00H
-  131   131                      $DGS    GLV_SYM, _adrs_table_twl_ext2int,       U,      U,      0CH,    02H,    01H,    02H
-  132   132                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  133   133                      $DGS    GLV_SYM, _vreg_twl_read,        U,      U,      0CH,    02H,    01H,    02H
-  134   134                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  135   135                      $DGS    GLV_SYM, _vreg_twl_write,       U,      U,      01H,    02H,    01H,    02H
-  136   136                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  137   137                      $DGS    GLV_SYM, _@SEGDE,       U,      U,      00H,    02H,    00H,    00H
-  138   138                      $DGS    GLV_SYM, _@RTARG0,      U,      U,      00H,    02H,    00H,    00H
-  139   139                      
-  140   140                              EXTRN   _@SEGAX
-  141   141                              EXTRN   _@SEGDE
-  142   142                              EXTRN   _@RTARG0
-  143   143                              EXTRN   _adrs_table_twl_ext2int
-  144   144                              EXTRN   _vreg_twl_read
-  145   145                              EXTRN   _vreg_twl_write
-  146   146                              PUBLIC  _vreg_adrs
-  147   147                              PUBLIC  _pre_dat
-  148   148                              PUBLIC  _tot
-  149   149                              PUBLIC  _int_iic_twl
-  150   150                              PUBLIC  _IIC_twl_Init
-  151   151                              PUBLIC  _IIC_twl_Stop
-  152   152                      
-  153   153 -----                @@BITS  BSEG
-  154   154                      
-  155   155 -----                @@CNST  CSEG    MIRRORP
-  156   156 00000  01            _lpf_coeff:     DB      01H     ; 1
-  157   157 00001  02                    DB      02H     ; 2
-  158   158 00002  02                    DB      02H     ; 2
-  159   159 00003  03                    DB      03H     ; 3
-  160   160 00004  03                    DB      03H     ; 3
-  161   161 00005  02                    DB      02H     ; 2
-  162   162 00006  00                    DB      00H     ; 0
-  163   163 00007  FE                    DB      0FEH    ; 254
-  164   164 00008  FB                    DB      0FBH    ; 251
-  165   165 00009  F7                    DB      0F7H    ; 247
-  166   166 0000A  F3                    DB      0F3H    ; 243
-  167   167 0000B  F0                    DB      0F0H    ; 240
-  168   168 0000C  F0                    DB      0F0H    ; 240
-  169   169 0000D  F3                    DB      0F3H    ; 243
-  170   170 0000E  FA                    DB      0FAH    ; 250
-  171   171 0000F  04                    DB      04H     ; 4
-  172   172 00010  12                    DB      012H    ; 18
-  173   173 00011  25                    DB      025H    ; 37
-  174   174 00012  38                    DB      038H    ; 56
-  175   175 00013  4D                    DB      04DH    ; 77
-  176   176 00014  5F                    DB      05FH    ; 95
-  177   177 00015  6E                    DB      06EH    ; 110
-  178   178 00016  77                    DB      077H    ; 119
-  179   179 00017  7A                    DB      07AH    ; 122
-  180   180 00018  77                    DB      077H    ; 119
-  181   181 00019  6E                    DB      06EH    ; 110
-  182   182 0001A  5F                    DB      05FH    ; 95
-  183   183 0001B  4D                    DB      04DH    ; 77
-  184   184 0001C  38                    DB      038H    ; 56
-  185   185 0001D  25                    DB      025H    ; 37
-  186   186 0001E  12                    DB      012H    ; 18
-  187   187 0001F  04                    DB      04H     ; 4
-  188   188 00020  FA                    DB      0FAH    ; 250
-  189   189 00021  F3                    DB      0F3H    ; 243
-  190   190 00022  F0                    DB      0F0H    ; 240
-  191   191 00023  F0                    DB      0F0H    ; 240
-  192   192 00024  F3                    DB      0F3H    ; 243
-  193   193 00025  F7                    DB      0F7H    ; 247
-  194   194 00026  FB                    DB      0FBH    ; 251
-  195   195 00027  FE                    DB      0FEH    ; 254
-  196   196 00028  00                    DB      00H     ; 0
-  197   197 00029  02                    DB      02H     ; 2
-  198   198 0002A  03                    DB      03H     ; 3
-  199   199 0002B  03                    DB      03H     ; 3
-  200   200 0002C  02                    DB      02H     ; 2
-  201   201 0002D  02                    DB      02H     ; 2
-  202   202 0002E  01                    DB      01H     ; 1
-  203   203 0002F  00                    DB      (1)
-  204   204                      
-  205   205 -----                @@R_INIT        CSEG    UNIT64KP
-  206   206                      
-  207   207 -----                @@INIT  DSEG    BASEP
-  208   208                      
-  209   209 -----                @@DATA  DSEG    BASEP
-  210   210 00000                _vreg_adrs:     DS      (1)
-  211   211 00001                _pre_dat:       DS      (1)
-  212   212 00002                _tot:   DS      (2)
-  213   213                      
-  214   214 -----                @@R_INIS        CSEG    UNIT64KP
-  215   215                      
-  216   216 -----                @@INIS  DSEG    SADDRP
-  217   217                      
-  218   218 -----                @@DATS  DSEG    SADDRP
-  219   219                      
-  220   220 -----                @@CNSTL CSEG    PAGE64KP
-  221   221                      
-  222   222 -----                @@RLINIT        CSEG    UNIT64KP
-  223   223                      
-  224   224 -----                @@INITL DSEG    UNIT64KP
-  225   225                      
-  226   226 -----                @@DATAL DSEG    UNIT64KP
-  227   227                      
-  228   228 -----                @@CALT  CSEG    CALLT0
-  229   229                      
-  230   230                      ; line     1 : #pragma sfr                     /* 特殊機能レジスタ使用 */
-  231   231                      ; line     2 : 
-  232   232                      ; line     3 : 
-  233   233                      ; line     4 : 
-  234   234                      ; line     5 : /*==============================================================
-  235   235                      ;              ==============*/
-  236   236                      ; line     6 : #include "incs.h"
-  237   237                      ; line     7 : #include "i2c_twl_defs.h"
-  238   238                      ; line     8 : 
-  239   239                      ; line     9 : 
-  240   240                      ; line    10 : extern u8 vreg_twl[];
-  241   241                      ; line    11 : 
-  242   242                      ; line    12 : #ifdef _MCU_BSR_
-  243   243                      ; line    13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_
-  244   244                      ; line    14 : 
-  245   245                      ; line    15 : // ワーキングモデルはI2Cが逆
-  246   246                      ; line    16 : #define ACKD       ACKD0
-  247   247                      ; line    17 : #define ACKE       ACKE0
-  248   248                      ; line    18 : #define COI        COI0
-  249   249                      ; line    19 : #define IICAEN     IICA0EN
-  250   250                      ; line    20 : #define IICRSV     IICRSV0
-  251   251                      ; line    21 : #define IICA       IICA0
-  252   252                      ; line    22 : #define IICAIF     IICAIF0
-  253   253                      ; line    23 : #define IICAMK     IICAMK0
-  254   254                      ; line    24 : #define IICAPR0    IICAPR00
-  255   255                      ; line    25 : #define IICAPR1    IICAPR10
-  256   256                      ; line    26 : #define IICCTL0    IICCTL00
-  257   257                      ; line    27 : #define IICE       IICE0
-  258   258                      ; line    28 : #define IICF       IICF0
-  259   259                      ; line    29 : #define IICS       IICS0
-  260   260                      ; line    30 : #define IICWH      IICWH0
-  261   261                      ; line    31 : #define IICWL      IICWL0
-  262   262                      ; line    32 : #define LREL       LREL0
-  263   263                      ; line    33 : #define SPD        SPD0
-  264   264                      ; line    34 : #define SPIE       SPIE0
-  265   265                      ; line    35 : #define STCEN      STCEN0
-  266   266                      ; line    36 : #define STD        STD0
-  267   267                      ; line    37 : #define SVA        SVA0
-  268   268                      ; line    38 : #define WREL       WREL0
-  269   269                      ; line    39 : #define WTIM       WTIM0
-  270   270                      ; line    40 : #define SMC        SMC0
-  271   271                      ; line    41 : 
-  272   272                      ; line    42 : #endif
-  273   273                      ; line    43 : 
-  274   274                      ; line    44 : #ifndef _MCU_BSR_
-  275   275                      ; line    45 : 
-  276   276                      ; line    46 : // ke3の時はダミー関数
-  277   277                      ; line    47 : void IIC_twl_Stop( void )
-  278   278                      ; line    48 : {
-  279   279                      ; line    49 : }
-  280   280                      ; line    50 : void IIC_twl_Init( void )
-  281   281                      ; line    51 : {
-  282   282                      ; line    52 : }
-  283   283                      ; line    53 : #else
-  284   284                      ; line    54 : 
-  285   285                      ; line    55 : 
-  286   286                      ; line    56 : /*==============================================================
-  287   287                      ;              ==============*/
-  288   288                      ; line    57 : u8      vreg_adrs;
-  289   289                      ; line    58 : u8      pre_dat;
-  290   290                      ; line    59 : 
-  291   291                      ; line    60 : 
-  292   292                      ; line    61 : u16     tot;
-  293   293                      ; line    62 : 
-  294   294                      ; line    63 : 
-  295   295                      ; line    64 : // 注！　↓はマクロなので、returnはメインループに戻ります。
-  296   296                      ; line    65 : #define wait_next {                                    \
-  297   297                      ; line    66 :     tot = 0;                                             \
-  298   298                      ; line    67 :   while( IICAIF != 1 ){                                \
-  299   299                      ; line    68 :     if( SPD ){                                         \
-  300   300                      ; line    69 :       LREL = 1;                                        \
-  301   301                      ; line    70 :       return;                                          \
-  302   302                      ; line    71 :     }                                                  \
-  303   303                      ; line    72 :     tot++;                                             \
-  304   304                      ; line    73 :     if( tot == 0 ){                                    \
-  305   305                      ; line    74 :       LREL = 1;                                        \
-  306   306                      ; line    75 :       return;                                          \
-  307   307                      ; line    76 :     }                                                  \
-  308   308                      ; line    77 :   }                                                    \
-  309   309                      ; line    78 : }
-  310   310                      ; line    79 : 
-  311   311                      ; line    80 : 
-  312   312                      ; line    81 : __interrupt void int_iic_twl(  )
-  313   313                      ; line    82 : {
-  314   314                      
-  315   315 -----                @@BASE  CSEG    BASE
-  316   316 00000                _int_iic_twl:
-  317   317                      $DGL    1,21
-  318   318 00000  C1                    push    ax                                              ;[INF] 1, 1
-  319   319 00001  C3                    push    bc                                              ;[INF] 1, 1
-  320   320 00002  C5                    push    de                                              ;[INF] 1, 1
-  321   321 00003  C7                    push    hl                                              ;[INF] 1, 1
-  322   322 00004  520C                  mov     c,#0CH                                          ;[INF] 2, 1
-  323   323 00006  92                    dec     c                                               ;[INF] 1, 1
-  324   324 00007  92                    dec     c                                               ;[INF] 1, 1
-  325   325 00008 R690000                movw    ax,_@SEGAX[c]                                   ;[INF] 3, 1
-  326   326 0000B  C1                    push    ax                                              ;[INF] 1, 1
-  327   327 0000C  DFF8                  bnz     $$-6                                            ;[INF] 2, 4
-  328   328 0000E  8EFD                  mov     a,ES                                            ;[INF] 2, 1
-  329   329 00010  70                    mov     x,a                                             ;[INF] 1, 1
-  330   330 00011  8EFC                  mov     a,CS                                            ;[INF] 2, 1
-  331   331 00013  C1                    push    ax                                              ;[INF] 1, 1
-  332   332 00014  2006                  subw    sp,#06H                                         ;[INF] 2, 1
-  333   333 00016  FBF8FF                movw    hl,sp                                           ;[INF] 3, 1
-  334   334 00019                ??bf_int_iic_twl:
-  335   335                      ; line    83 :     u8      temp;
-  336   336                      ; line    84 :     u16     tot;
-  337   337                      ; line    85 : 
-  338   338                      ; line    86 : //  WDT_Restart();
-  339   339                      ; line    87 :     // フラグ１回目    スレーブアドレス,R/W
-  340   340                      ; line    88 : /* COI != 1 なら、割り込みはいらない
-  341   341                      ; line    89 :   if( COI != 1 ){               // 被呼び出し？
-  342   342                      ; line    90 :     LREL = 1;                   // 呼ばれたのは他のID
-  343   343                      ; line    91 :     return;
-  344   344                      ; line    92 :   }else{
-  345   345                      ; line    93 :     ACKE0 = 1;                // 自動でackを返すようにする
-  346   346                      ; line    94 :     WREL = 1;                 // ウェイト解除して次のバイトを待つ
-  347   347                      ; line    95 :   }
-  348   348                      ; line    96 :   */
-  349   349                      ; line    97 :     WREL = 1;                   // ウェイト解除して次のバイトを待
-  350   350                      ;              つ
-  351   351                      $DGL    0,16
-  352   352 00019  71503002              set1    !IICCTL00.5                                     ;[INF] 4, 2
-  353   353                      ; line    98 :     wait_next;                  // １バイト受信完了を待つ
-  354   354                      $DGL    0,17
-  355   355 0001D                ??bb00_int_iic_twl:
-  356   356 0001D  F6                    clrw    ax                                              ;[INF] 1, 1
-  357   357 0001E  BC02                  movw    [hl+2],ax       ; tot                           ;[INF] 2, 1
-  358   358 00020                ?L0003:
-  359   359 00020  31B2E21B              bt      IF1L.3,$?L0004                                  ;[INF] 4, 5
-  360   360 00024                ??bb01_int_iic_twl:
-  361   361 00024  31845107              bf      IICS0.0,$?L0005                                 ;[INF] 4, 5
-  362   362 00028                ??bb02_int_iic_twl:
-  363   363 00028  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  364   364 0002C REDFD00                br      !?L0010                                         ;[INF] 3, 3
-  365   365 0002F                ??eb02_int_iic_twl:
-  366   366 0002F                ?L0005:
-  367   367 0002F  617902                incw    [hl+2]  ; tot                                   ;[INF] 3, 2
-  368   368 00032  F6                    clrw    ax                                              ;[INF] 1, 1
-  369   369 00033  614902                cmpw    ax,[hl+2]       ; tot                           ;[INF] 3, 1
-  370   370 00036  DFE8                  bnz     $?L0003                                         ;[INF] 2, 4
-  371   371 00038                ??bb03_int_iic_twl:
-  372   372 00038  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  373   373 0003C REDFD00                br      !?L0010                                         ;[INF] 3, 3
-  374   374 0003F                ??eb03_int_iic_twl:
-  375   375 0003F                ??eb01_int_iic_twl:
-  376   376 0003F                ?L0004:
-  377   377 0003F                ??eb00_int_iic_twl:
-  378   378                      ; line    99 : 
-  379   379                      ; line   100 :     // ２回目           R/W レジスタアドレス
-  380   380                      ; line   101 :     temp = IICA;
-  381   381                      $DGL    0,20
-  382   382 0003F  8E50                  mov     a,IICA0                                         ;[INF] 2, 1
-  383   383 00041  9C05                  mov     [hl+5],a        ; temp                          ;[INF] 2, 1
-  384   384                      ; line   102 :     IICAIF = 0;
-  385   385                      $DGL    0,21
-  386   386 00043  713BE2                clr1    IF1L.3                                          ;[INF] 3, 2
-  387   387                      ; line   103 :     WREL = 1;
-  388   388                      $DGL    0,22
-  389   389 00046  71503002              set1    !IICCTL00.5                                     ;[INF] 4, 2
-  390   390                      ; line   104 : 
-  391   391                      ; line   105 :     vreg_adrs = adrs_table_twl_ext2int( temp );
-  392   392                      $DGL    0,24
-  393   393 0004A  8C05                  mov     a,[hl+5]        ; temp                          ;[INF] 2, 1
-  394   394 0004C  318E                  shrw    ax,8                                            ;[INF] 2, 1
-  395   395 0004E RFD0000                call    !_adrs_table_twl_ext2int                        ;[INF] 3, 3
-  396   396 00051  62                    mov     a,c                                             ;[INF] 1, 1
-  397   397 00052 R9F0000                mov     !_vreg_adrs,a                                   ;[INF] 3, 1
-  398   398                      ; line   106 : 
-  399   399                      ; line   107 :     // ３回目
-  400   400                      ; line   108 :     // スタートコンディションか、データ受信完了フラグ待ち
-  401   401                      ; line   109 : 
-  402   402                      ; line   110 :     while( 1 )
-  403   403 00055                ?L0009:
-  404   404                      ; line   111 :     {
-  405   405 00055                ??bb04_int_iic_twl:
-  406   406                      ; line   112 :         u8 my_iics = IICS;
-  407   407                      $DGL    0,31
-  408   408 00055  8E51                  mov     a,IICS0                                         ;[INF] 2, 1
-  409   409 00057  9C01                  mov     [hl+1],a        ; my_iics                       ;[INF] 2, 1
-  410   410                      ; line   113 : 
-  411   411                      ; line   114 :         if( my_iics & 0x01 )    // SPD
-  412   412                      $DGL    0,33
-  413   413 00059  5C01                  and     a,#01H  ; 1                                     ;[INF] 2, 1
-  414   414 0005B  D1                    cmp0    a                                               ;[INF] 1, 1
-  415   415 0005C  DD07                  bz      $?L0011                                         ;[INF] 2, 4
-  416   416                      ; line   115 :         {                       // 強制終了
-  417   417 0005E                ??bb05_int_iic_twl:
-  418   418                      ; line   116 :             LREL = 1;
-  419   419                      $DGL    0,35
-  420   420 0005E  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  421   421                      ; line   117 :             return;
-  422   422                      $DGL    0,36
-  423   423 00062 REDFD00                br      !?L0010                                         ;[INF] 3, 3
-  424   424 00065                ??eb05_int_iic_twl:
-  425   425                      ; line   118 :         }
-  426   426 00065                ?L0011:
-  427   427                      ; line   119 :         else if( my_iics & 0x02 )  // ( STD && !SPD )
-  428   428                      $DGL    0,38
-  429   429 00065  8C01                  mov     a,[hl+1]        ; my_iics                       ;[INF] 2, 1
-  430   430 00067  5C02                  and     a,#02H  ; 2                                     ;[INF] 2, 1
-  431   431 00069  D1                    cmp0    a                                               ;[INF] 1, 1
-  432   432 0006A  DD66                  bz      $?L0013                                         ;[INF] 2, 4
-  433   433                      ; line   120 :         {
-  434   434 0006C                ??bb06_int_iic_twl:
-  435   435                      ; line   121 :             // 送信 // (スタートコンディション検出)
-  436   436                      ; line   122 :             pre_dat = vreg_twl_read( vreg_adrs );       // mcu内
-  437   437                      ;              部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除
-  438   438                      $DGL    0,41
-  439   439 0006C RD90000                mov     x,!_vreg_adrs                                   ;[INF] 3, 1
-  440   440 0006F  F1                    clrb    a                                               ;[INF] 1, 1
-  441   441 00070 RFD0000                call    !_vreg_twl_read                                 ;[INF] 3, 3
-  442   442 00073  62                    mov     a,c                                             ;[INF] 1, 1
-  443   443 00074 R9F0100                mov     !_pre_dat,a                                     ;[INF] 3, 1
-  444   444                      ; line   123 : 
-  445   445                      ; line   124 :             // 自局をRで呼ばれるのを待つ
-  446   446                      ; line   125 :             wait_next;
-  447   447                      $DGL    0,44
-  448   448 00077                ??bb07_int_iic_twl:
-  449   449 00077  F6                    clrw    ax                                              ;[INF] 1, 1
-  450   450 00078  BC02                  movw    [hl+2],ax       ; tot                           ;[INF] 2, 1
-  451   451 0007A                ?L0015:
-  452   452 0007A  31B2E219              bt      IF1L.3,$?L0016                                  ;[INF] 4, 5
-  453   453 0007E                ??bb08_int_iic_twl:
-  454   454 0007E  31845106              bf      IICS0.0,$?L0017                                 ;[INF] 4, 5
-  455   455 00082                ??bb09_int_iic_twl:
-  456   456 00082  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  457   457 00086  EF75                  br      $?L0010                                         ;[INF] 2, 3
-  458   458 00088                ??eb09_int_iic_twl:
-  459   459 00088                ?L0017:
-  460   460 00088  617902                incw    [hl+2]  ; tot                                   ;[INF] 3, 2
-  461   461 0008B  F6                    clrw    ax                                              ;[INF] 1, 1
-  462   462 0008C  614902                cmpw    ax,[hl+2]       ; tot                           ;[INF] 3, 1
-  463   463 0008F  DFE9                  bnz     $?L0015                                         ;[INF] 2, 4
-  464   464 00091                ??bb0A_int_iic_twl:
-  465   465 00091  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  466   466 00095  EF66                  br      $?L0010                                         ;[INF] 2, 3
-  467   467 00097                ??eb0A_int_iic_twl:
-  468   468                      ; line   126 :             IICAIF = 0;
-  469   469                      $DGL    0,45
-  470   470 00097                ??eb08_int_iic_twl:
-  471   471 00097                ?L0016:
-  472   472 00097                ??eb07_int_iic_twl:
-  473   473 00097  713BE2                clr1    IF1L.3                                          ;[INF] 3, 2
-  474   474                      ; line   127 :             if( COI != 1 )
-  475   475                      $DGL    0,46
-  476   476 0009A  31C25106              bt      IICS0.4,$?L0021                                 ;[INF] 4, 5
-  477   477                      ; line   128 :             {                   // 被呼び出し？
-  478   478 0009E                ??bb0B_int_iic_twl:
-  479   479                      ; line   129 :                 LREL = 1;       // 呼ばれたのは他のID（あれ？）
-  480   480                      $DGL    0,48
-  481   481 0009E  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  482   482                      ; line   130 :                 return;
-  483   483                      $DGL    0,49
-  484   484 000A2  EF59                  br      $?L0010                                         ;[INF] 2, 3
-  485   485 000A4                ??eb0B_int_iic_twl:
-  486   486                      ; line   131 :             }
-  487   487 000A4                ?L0021:
-  488   488                      ; line   132 :             IICA = pre_dat;     // データを送る。ウェイトも解除さ
-  489   489                      ;              れる。
-  490   490                      $DGL    0,51
-  491   491 000A4 R8F0100                mov     a,!_pre_dat                                     ;[INF] 3, 1
-  492   492 000A7  9E50                  mov     IICA0,a                                         ;[INF] 2, 1
-  493   493                      ; line   133 : 
-  494   494                      ; line   134 :             wait_next;
-  495   495                      $DGL    0,53
-  496   496 000A9                ??bb0C_int_iic_twl:
-  497   497 000A9  F6                    clrw    ax                                              ;[INF] 1, 1
-  498   498 000AA  BC02                  movw    [hl+2],ax       ; tot                           ;[INF] 2, 1
-  499   499 000AC                ?L0023:
-  500   500 000AC  31B2E219              bt      IF1L.3,$?L0024                                  ;[INF] 4, 5
-  501   501 000B0                ??bb0D_int_iic_twl:
-  502   502 000B0  31845106              bf      IICS0.0,$?L0025                                 ;[INF] 4, 5
-  503   503 000B4                ??bb0E_int_iic_twl:
-  504   504 000B4  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  505   505 000B8  EF43                  br      $?L0010                                         ;[INF] 2, 3
-  506   506 000BA                ??eb0E_int_iic_twl:
-  507   507 000BA                ?L0025:
-  508   508 000BA  617902                incw    [hl+2]  ; tot                                   ;[INF] 3, 2
-  509   509 000BD  F6                    clrw    ax                                              ;[INF] 1, 1
-  510   510 000BE  614902                cmpw    ax,[hl+2]       ; tot                           ;[INF] 3, 1
-  511   511 000C1  DFE9                  bnz     $?L0023                                         ;[INF] 2, 4
-  512   512 000C3                ??bb0F_int_iic_twl:
-  513   513 000C3  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  514   514 000C7  EF34                  br      $?L0010                                         ;[INF] 2, 3
-  515   515 000C9                ??eb0F_int_iic_twl:
-  516   516                      ; line   135 :             // ４回目。(送信データ後の、ACK/NACK後)　どうしても発
-  517   517                      ;              生してしまう。
-  518   518 000C9                ??eb0D_int_iic_twl:
-  519   519 000C9                ?L0024:
-  520   520 000C9                ??eb0C_int_iic_twl:
-  521   521                      ; line   136 :             IICAIF = 0;         // おしまい
-  522   522                      $DGL    0,55
-  523   523 000C9  713BE2                clr1    IF1L.3                                          ;[INF] 3, 2
-  524   524                      ; line   137 :             LREL = 1;
-  525   525                      $DGL    0,56
-  526   526 000CC  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  527   527                      ; line   138 :             return;
-  528   528                      $DGL    0,57
-  529   529 000D0  EF2B                  br      $?L0010                                         ;[INF] 2, 3
-  530   530 000D2                ??eb06_int_iic_twl:
-  531   531                      ; line   139 :         }
-  532   532 000D2                ?L0013:
-  533   533                      ; line   140 :         else if( IICAIF && (( my_iics & 0x03 ) == 0 ))   // !STD
-  534   534                      ;               && !SPD )
-  535   535                      $DGL    0,59
-  536   536 000D2  31B4E224              bf      IF1L.3,$?L0029                                  ;[INF] 4, 5
-  537   537 000D6  8C01                  mov     a,[hl+1]        ; my_iics                       ;[INF] 2, 1
-  538   538 000D8  5C03                  and     a,#03H  ; 3                                     ;[INF] 2, 1
-  539   539 000DA  D1                    cmp0    a                                               ;[INF] 1, 1
-  540   540 000DB  DF1D                  bnz     $?L0029                                         ;[INF] 2, 4
-  541   541                      ; line   141 :         {
-  542   542 000DD                ??bb10_int_iic_twl:
-  543   543                      ; line   142 :             // 受信 //
-  544   544                      ; line   143 :             IICAIF = 0;
-  545   545                      $DGL    0,62
-  546   546 000DD  713BE2                clr1    IF1L.3                                          ;[INF] 3, 2
-  547   547                      ; line   144 :             temp = IICA;
-  548   548                      $DGL    0,63
-  549   549 000E0  8E50                  mov     a,IICA0                                         ;[INF] 2, 1
-  550   550 000E2  9C05                  mov     [hl+5],a        ; temp                          ;[INF] 2, 1
-  551   551                      ; line   145 :             WREL = 1;
-  552   552                      $DGL    0,64
-  553   553 000E4  71503002              set1    !IICCTL00.5                                     ;[INF] 4, 2
-  554   554                      ; line   146 : 
-  555   555                      ; line   147 :             // 通常アクセス(ライト) //
-  556   556                      ; line   148 :             LREL = 1;           // スタートコンディション待ちへ(
-  557   557                      ;              連続書き込み未対応のため)
-  558   558                      $DGL    0,67
-  559   559 000E8  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  560   560                      ; line   149 :             vreg_twl_write( vreg_adrs, temp );
-  561   561                      $DGL    0,68
-  562   562 000EC  8C05                  mov     a,[hl+5]        ; temp                          ;[INF] 2, 1
-  563   563 000EE  318E                  shrw    ax,8                                            ;[INF] 2, 1
-  564   564 000F0  C1                    push    ax                                              ;[INF] 1, 1
-  565   565 000F1 RD90000                mov     x,!_vreg_adrs                                   ;[INF] 3, 1
-  566   566 000F4 RFD0000                call    !_vreg_twl_write                                ;[INF] 3, 3
-  567   567 000F7  C0                    pop     ax                                              ;[INF] 1, 1
-  568   568                      ; line   150 :             return;             // 受信おしまい //
-  569   569                      $DGL    0,69
-  570   570 000F8  EF03                  br      $?L0010                                         ;[INF] 2, 3
-  571   571 000FA                ??eb10_int_iic_twl:
-  572   572                      ; line   151 :         }
-  573   573 000FA                ?L0029:
-  574   574 000FA                ??eb04_int_iic_twl:
-  575   575                      ; line   152 :     }
-  576   576                      $DGL    0,71
-  577   577 000FA RED5500                br      !?L0009                                         ;[INF] 3, 3
-  578   578 000FD                ?L0010:
-  579   579                      ; line   153 : }
-  580   580                      $DGL    0,72
-  581   581 000FD                ??ef_int_iic_twl:
-  582   582 000FD  1006                  addw    sp,#06H                                         ;[INF] 2, 1
-  583   583 000FF  C0                    pop     ax                                              ;[INF] 1, 1
-  584   584 00100  9EFC                  mov     CS,a                                            ;[INF] 2, 1
-  585   585 00102  60                    mov     a,x                                             ;[INF] 1, 1
-  586   586 00103  9EFD                  mov     ES,a                                            ;[INF] 2, 1
-  587   587 00105 R340000                movw    de,#_@SEGAX                                     ;[INF] 3, 1
-  588   588 00108  5206                  mov     c,#06H                                          ;[INF] 2, 1
-  589   589 0010A  C0                    pop     ax                                              ;[INF] 1, 1
-  590   590 0010B  B9                    movw    [de],ax                                         ;[INF] 1, 1
-  591   591 0010C  A5                    incw    de                                              ;[INF] 1, 1
-  592   592 0010D  A5                    incw    de                                              ;[INF] 1, 1
-  593   593 0010E  92                    dec     c                                               ;[INF] 1, 1
-  594   594 0010F  DFF9                  bnz     $$-5                                            ;[INF] 2, 4
-  595   595 00111  C6                    pop     hl                                              ;[INF] 1, 1
-  596   596 00112  C4                    pop     de                                              ;[INF] 1, 1
-  597   597 00113  C2                    pop     bc                                              ;[INF] 1, 1
-  598   598 00114  C0                    pop     ax                                              ;[INF] 1, 1
-  599   599 00115  61FC                  reti                                                    ;[INF] 2, 6
-  600   600 00117                ??ee_int_iic_twl:
-  601   601                      ; line   154 : 
-  602   602                      ; line   155 : 
-  603   603                      ; line   156 : 
-  604   604                      ; line   157 : /*****************************************************/
-  605   605                      ; line   158 : void IIC_twl_Init( void )
-  606   606                      ; line   159 : {
-  607   607                      
-  608   608 -----                ROM_CODE        CSEG    BASE
-  609   609 00000                _IIC_twl_Init:
-  610   610                      $DGL    1,99
-  611   611 00000                ??bf_IIC_twl_Init:
-  612   612                      ; line   160 : 
-  613   613                      ; line   161 :     IICAEN = 1;
-  614   614                      $DGL    0,3
-  615   615 00000  7140F000              set1    !PER0.4                                         ;[INF] 4, 2
-  616   616                      ; line   162 : 
-  617   617                      ; line   163 :     IICE = 0;                   /* IICA disable */
-  618   618                      $DGL    0,5
-  619   619 00004  71783002              clr1    !IICCTL00.7                                     ;[INF] 4, 2
-  620   620                      ; line   164 : 
-  621   621                      ; line   165 :     IICAMK = 1;                 /* INTIICA disable */
-  622   622                      $DGL    0,7
-  623   623 00008  713AE6                set1    MK1L.3                                          ;[INF] 3, 2
-  624   624                      ; line   166 :     IICAIF = 0;                 /* clear INTIICA interrupt flag 
-  625   625                      ;              */
-  626   626                      $DGL    0,8
-  627   627 0000B  713BE2                clr1    IF1L.3                                          ;[INF] 3, 2
-  628   628                      ; line   167 : 
-  629   629                      ; line   168 :     IICAPR0 = 0;                /* set INTIICA high priority */
-  630   630                      $DGL    0,10
-  631   631 0000E  713BEA                clr1    PR01L.3                                         ;[INF] 3, 2
-  632   632                      ; line   169 :     IICAPR1 = 0;                /* set INTIICA high priority */
-  633   633                      $DGL    0,11
-  634   634 00011  713BEE                clr1    PR11L.3                                         ;[INF] 3, 2
-  635   635                      ; line   170 :     P20 &= ~0x3;
-  636   636                      $DGL    0,12
-  637   637 00014  8F1005                mov     a,!P20                                          ;[INF] 3, 1
-  638   638 00017  5CFC                  and     a,#0FCH ; 252                                   ;[INF] 2, 1
-  639   639 00019  9F1005                mov     !P20,a                                          ;[INF] 3, 1
-  640   640                      ; line   171 : 
-  641   641                      ; line   172 :     SVA = IIC_T_SLAVEADDRESS;
-  642   642                      $DGL    0,14
-  643   643 0001C  CF34024A              mov     !SVA0,#04AH     ; 74                            ;[INF] 4, 1
-  644   644                      ; line   173 :     IICF = 0x01;
-  645   645                      $DGL    0,15
-  646   646 00020  E552FF                oneb    !IICF0                                          ;[INF] 3, 1
-  647   647                      ; line   174 : 
-  648   648                      ; line   175 :     STCEN = 1;                  // リスタートの許可
-  649   649                      $DGL    0,17
-  650   650 00023  711A52                set1    IICF0.1                                         ;[INF] 3, 2
-  651   651                      ; line   176 :     IICRSV = 1;                 // 通信予約をさせない:スレーブに
-  652   652                      ;              徹する
-  653   653                      $DGL    0,18
-  654   654 00026  710A52                set1    IICF0.0                                         ;[INF] 3, 2
-  655   655                      ; line   177 : 
-  656   656                      ; line   178 :     SPIE = 0;                   // ストップコンディションでの割り
-  657   657                      ;              込みを禁止
-  658   658                      $DGL    0,20
-  659   659 00029  71483002              clr1    !IICCTL00.4                                     ;[INF] 4, 2
-  660   660                      ; line   179 :     WTIM = 1;                   // 自動でACKを返した後clkをLに固
-  661   661                      ;              定する
-  662   662                      $DGL    0,21
-  663   663 0002D  71303002              set1    !IICCTL00.3                                     ;[INF] 4, 2
-  664   664                      ; line   180 :     ACKE = 1;                   //  ダメCPUは無視して次の通信をは
-  665   665                      ;              じめるかもしれないんで早くclkを開放しないといけない
-  666   666                      $DGL    0,22
-  667   667 00031  71203002              set1    !IICCTL00.2                                     ;[INF] 4, 2
-  668   668                      ; line   181 : 
-  669   669                      ; line   182 :     IICWH = 5;
-  670   670                      $DGL    0,24
-  671   671 00035  CF330205              mov     !IICWH0,#05H    ; 5                             ;[INF] 4, 1
-  672   672                      ; line   183 :     IICWL = 10;                 // L期間の長さ（？）
-  673   673                      $DGL    0,25
-  674   674 00039  CF32020A              mov     !IICWL0,#0AH    ; 10                            ;[INF] 4, 1
-  675   675                      ; line   184 : 
-  676   676                      ; line   185 :     SMC = 1;
-  677   677                      $DGL    0,27
-  678   678 0003D  71303102              set1    !IICCTL10.3                                     ;[INF] 4, 2
-  679   679                      ; line   186 : 
-  680   680                      ; line   187 :     IICAMK = 0;                 // 割り込みを許可
-  681   681                      $DGL    0,29
-  682   682 00041  713BE6                clr1    MK1L.3                                          ;[INF] 3, 2
-  683   683                      ; line   188 : 
-  684   684                      ; line   189 :     IICE = 1;
-  685   685                      $DGL    0,31
-  686   686 00044  71703002              set1    !IICCTL00.7                                     ;[INF] 4, 2
-  687   687                      ; line   190 : 
-  688   688                      ; line   191 :     PM20 &= ~0x3;               /* set clock pin for IICA */
-  689   689                      $DGL    0,33
-  690   690 00048  8F1105                mov     a,!PM20                                         ;[INF] 3, 1
-  691   691 0004B  5CFC                  and     a,#0FCH ; 252                                   ;[INF] 2, 1
-  692   692 0004D  9F1105                mov     !PM20,a                                         ;[INF] 3, 1
-  693   693                      ; line   192 : 
-  694   694                      ; line   193 :     LREL = 1;
-  695   695                      $DGL    0,35
-  696   696 00050  71603002              set1    !IICCTL00.6                                     ;[INF] 4, 2
-  697   697                      ; line   194 : }
-  698   698                      $DGL    0,36
-  699   699 00054                ??ef_IIC_twl_Init:
-  700   700 00054  D7                    ret                                                     ;[INF] 1, 6
-  701   701 00055                ??ee_IIC_twl_Init:
-  702   702                      ; line   195 : 
-  703   703                      ; line   196 : 
-  704   704                      ; line   197 : 
-  705   705                      ; line   198 : //**************************************************************
-  706   706                      ;              **************
-  707   707                      ; line   199 : void IIC_twl_Stop( void )
-  708   708                      ; line   200 : {
-  709   709 00055                _IIC_twl_Stop:
-  710   710                      $DGL    1,105
-  711   711 00055                ??bf_IIC_twl_Stop:
-  712   712                      ; line   201 :     IICE = 0;                   /* IICA disable */
-  713   713                      $DGL    0,2
-  714   714 00055  71783002              clr1    !IICCTL00.7                                     ;[INF] 4, 2
-  715   715                      ; line   202 :     IICAEN = 0;
-  716   716                      $DGL    0,3
-  717   717 00059  7148F000              clr1    !PER0.4                                         ;[INF] 4, 2
-  718   718                      ; line   203 : }
-  719   719                      $DGL    0,4
-  720   720 0005D                ??ef_IIC_twl_Stop:
-  721   721 0005D  D7                    ret                                                     ;[INF] 1, 6
-  722   722 0005E                ??ee_IIC_twl_Stop:
-  723   723                      
-  724   724 -----                @@CODEL CSEG
-  725   725                              END
-  726   726                      
-  727   727                      
-  728   728                      ; *** Code Information ***
-  729   729                      ;
-  730   730                      ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c
-  731   731                      ;
-  732   732                      ; $FUNC int_iic_twl(82)
-  733   733                      ;       void=(void)
-  734   734                      ;       CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes
-  735   735                      ;
-  736   736                      ; $CALL adrs_table_twl_ext2int(105)
-  737   737                      ;       bc=(int:ax)
-  738   738                      ;
-  739   739                      ; $CALL vreg_twl_read(122)
-  740   740                      ;       bc=(int:ax)
-  741   741                      ;
-  742   742                      ; $CALL vreg_twl_write(149)
-  743   743                      ;       void=(int:ax, int:[sp+4])
-  744   744                      ;
-  745   745                      ; $FUNC IIC_twl_Init(159)
-  746   746                      ;       void=(void)
-  747   747                      ;       CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
-  748   748                      ;
-  749   749                      ; $FUNC IIC_twl_Stop(200)
-  750   750                      ;       void=(void)
-  751   751                      ;       CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
-  752   752                      
-  753   753                      ; Target chip : uPD79F0104
-  754   754                      ; Device file : E1.00b
-
-Segment informations:
-
-ADRS  LEN      NAME
-
-00000 00000H.0 @@BITS
-00000 00030H   @@CNST
-00000 00000H   @@R_INIT
-00000 00000H   @@INIT
-00000 00004H   @@DATA
-00000 00000H   @@R_INIS
-00000 00000H   @@INIS
-00000 00000H   @@DATS
-00000 00000H   @@CNSTL
-00000 00000H   @@RLINIT
-00000 00000H   @@INITL
-00000 00000H   @@DATAL
-00000 00000H   @@CALT
-00000 00117H   @@BASE
-00000 0005EH   ROM_CODE
-00000 00000H   @@CODEL
-
- Target chip : uPD79F0104
- Device file : E1.00b
-Assembly complete,     0 error(s) and     0 warning(s) found. (    0)
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl_defs.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/i2c_twl_defs.h
@ -1,196 +0,0 @@
-#ifndef _MDSERIAL_
-#define _MDSERIAL_
-
-
-/* IIC operation enable	(IICE0)	*/
-#define	IIC0_OPERATION				0x80
-#define	IIC0_OPERATION_DISABLE		0x00    /* stop operation */
-#define	IIC0_OPERATION_ENABLE		0x80    /* enable operation     */
-
-/* Exit	from communications	(LREL0)	*/
-#define	IIC0_COMMUNICATION			0x40
-#define	IIC0_COMMUNICATION_NORMAL	0x00    /* normal operation     */
-#define	IIC0_COMMUNICATION_EXIT		0x40    /* exit from current communication */
-
-/* Wait	cancellation (WREL0) */
-#define	IIC0_WAITCANCEL				0x20
-#define	IIC0_WAIT_NOTCANCEL			0x00    /* do not cancel wait */
-#define	IIC0_WAIT_CANCEL			0x20    /* cancel wait */
-
-/* Generation of interrupt when	stop condition (SPIE0) */
-#define	IIC0_STOPINT				0x10
-#define	IIC0_STOPINT_DISABLE		0x00    /* disable */
-#define	IIC0_STOPINT_ENABLE			0x10    /* enable */
-
-/* Wait	and	interrupt generation (WTIM0) */
-#define	IIC0_WAITINT				0x08
-#define	IIC0_WAITINT_CLK8FALLING	0x00    /* generate     at the eighth clocks falling edge       */
-#define	IIC0_WAITINT_CLK9FALLING	0x08    /* generated at the     ninth clocks falling edge       */
-
-/* Acknowledgement control (ACKE0) */
-#define	IIC0_ACK					0x04
-#define	IIC0_ACK_DISABLE			0x00    /* enable acknowledgement */
-#define	IIC0_ACK_ENABLE				0x04    /* disable acknowledgement */
-
-/* Start condition trigger (STT0) */
-#define	IIC0_STARTCONDITION			0x02
-#define	IIC0_START_NOTGENERATE		0x00    /* do not generate start condition */
-#define	IIC0_START_GENERATE			0x02    /* generate     start condition */
-
-/* Stop	condition trigger (SPT0) */
-#define	IIC0_STOPCONDITION			0x01
-#define	IIC0_STOP_NOTGENERATE		0x00    /* do not generate stop condition */
-#define	IIC0_STOP_GENERATE			0x01    /* generate     stop condition */
-
-/*
-	IIC	Status Register	0 (IICS0)
-*/
-/* Master device status	(MSTS0)	*/
-#define	IIC0_MASTERSTATUS			0x80
-#define	IIC0_STATUS_NOTMASTER		0x00    /* slave device status or communication standby status */
-#define	IIC0_STATUS_MASTER			0x80    /* master device communication status */
-
-/* Detection of	arbitration	loss (ALD0)	*/
-#define	IIC0_ARBITRATION			0x40
-#define	IIC0_ARBITRATION_NO			0x00    /* arbitration win or no arbitration */
-#define	IIC0_ARBITRATION_LOSS		0x40    /* arbitration loss     */
-
-/* Detection of	extension code reception (EXC0)	*/
-#define	IIC0_EXTENSIONCODE			0x20
-#define	IIC0_EXTCODE_NOT			0x00    /* extension code not received */
-#define	IIC0_EXTCODE_RECEIVED		0x20    /* extension code received */
-
-/* Detection of	matching addresses (COI0) */
-#define	IIC0_ADDRESSMATCH			0x10
-#define	IIC0_ADDRESS_NOTMATCH		0x00    /* addresses do not     match */
-#define	IIC0_ADDRESS_MATCH			0x10    /* addresses match */
-
-/* Detection of	transmit/receive status	(TRC0) */
-#define	IIC0_STATUS					0x08
-#define	IIC0_STATUS_RECEIVE			0x00    /* receive status */
-#define	IIC0_STATUS_TRANSMIT		0x08    /* transmit     status */
-
-/* Detection of	acknowledge	signal (ACKD0) */
-#define	IIC0_ACKDETECTION			0x04
-#define	IIC0_ACK_NOTDETECTED		0x00    /* ACK signal was not detected */
-#define	IIC0_ACK_DETECTED			0x04    /* ACK signal was detected */
-
-/* Detection of	start condition	(STD0) */
-#define	IIC0_STARTDETECTION			0x02
-#define	IIC0_START_NOTDETECTED		0x00    /* start condition not detected */
-#define	IIC0_START_DETECTED			0x02    /* start condition detected     */
-
-/* Detection of	stop condition (SPD0) */
-#define	IIC0_STOPDETECTION			0x01
-#define	IIC0_STOP_NOTDETECTED		0x00    /* stop condition not detected */
-#define	IIC0_STOP_DETECTED			0x01    /* stop condition detected */
-
-/*
-	IIC	Flag Register 0	(IICF0)
-*/
-/* STT0	clear flag (STCF) */
-#define	IIC0_STARTFLAG				0x80
-#define	IIC0_STARTFLAG_GENERATE		0x00    /* generate     start condition */
-#define	IIC0_STARTFLAG_UNSUCCESSFUL	0x80    /* start condition generation unsuccessful */
-
-/* IIC bus status flag (IICBSY)	*/
-#define	IIC0_BUSSTATUS				0x40
-#define	IIC0_BUS_RELEASE			0x00    /* bus release status */
-#define	IIC0_BUS_COMMUNICATION		0x40    /* bus communication status     */
-
-/* Initial start enable	trigger	(STCEN)	*/
-#define	IIC0_STARTWITHSTOP			0x02
-#define	IIC0_START_WITHSTOP			0x00    /* generation of a start condition without detecting a stop     condition */
-#define	IIC0_START_WITHOUTSTOP		0x02    /* generation of a start condition upon detection of a stop     condition */
-
-/* Communication reservation function disable bit (IICRSV) */
-#define	IIC0_RESERVATION			0x01
-#define	IIC0_RESERVATION_ENABLE		0x00    /* enable communication reservation     */
-#define	IIC0_RESERVATION_DISABLE	0x01    /* disable communication reservation */
-
-/*
-	IIC	clock selection	register 0 (IICCL0)
-*/
-#define IICCL0_INITIALVALUE   		0x00
-/* Detection of	SCL0 pin level (CLD0) */
-#define	IIC0_SCLLEVEL				0x20
-#define	IIC0_SCL_LOW				0x00    /* clock line at low level */
-#define	IIC0_SCL_HIGH				0x20    /* clock line at high level     */
-
-/* Detection of	SDA0 pin level (DAD0) */
-#define	IIC0_SDALEVEL				0x10
-#define	IIC0_SDA_LOW				0x00    /* data line at low     level */
-#define	IIC0_SDA_HIGH				0x10    /* data line at high level */
-
-/* Operation mode switching	(SMC0) */
-#define	IIC0_OPERATIONMODE			0x08
-#define	IIC0_MODE_STANDARD			0x00    /* operates     in standard     mode */
-#define	IIC0_MODE_HIGHSPEED			0x08    /* operates     in high-speed mode */
-
-/* Digital filter operation	control	(DFC0) */
-#define	IIC0_DIGITALFILTER			0x04
-#define	IIC0_FILTER_OFF				0x00    /* digital filter off */
-#define	IIC0_FILTER_ON				0x04    /* digital filter on */
-
-/* Operation mode switching	(CL01, CL00) */
-#define	IIC0_CLOCKSELECTION			0x03
-
-/*	Combine	of (SMC0, CL01,	CL00)*/
-#define	IIC0_CLOCK0					0x00
-#define	IIC0_CLOCK1					0x01
-#define	IIC0_CLOCK2					0x02
-#define	IIC0_CLOCK3					0x03
-#define	IIC0_CLOCK4					0x08
-#define	IIC0_CLOCK5					0x09
-#define	IIC0_CLOCK6					0x0a
-#define	IIC0_CLOCK7					0x0b
-
-/*
-	IIC	function expansion register	0 (IICX0)
-*/
-/* IIC clock expension (CLX0) */
-#define	IIC0_CLOCKEXPENSION			0x01
-#define	IIC0_EXPENSION0				0x00
-#define	IIC0_EXPENSION1				0x01
-
-/*  Operation clock (CLX0, SMC0, CL01, CL00)
-            |   IIC0_EXPENSION0 |   IIC0_EXPENSION1 |                                
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK0 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/88     |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK1 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/172    |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK2 |       fprs/2      |       prohibited  |   selection clock(fw)
-            |       fprs/344    |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK3 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
-            |       fw/66       |                   |   transfer clock
-            |       normal      |                   |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK4 |       fprs/2      |       fprs/2      |   selection clock(fw)
-            |       fprs/48     |       fprs/24     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------            
-IIC0_CLOCK5 |       fprs/2      |       fprs/2      |   selection clock(fw)
-            |       fprs/48     |       fprs/24     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK6 |       fprs/4      |       fprs/4      |   selection clock(fw)
-            |       fprs/96     |       fprs/48     |   transfer clock
-            |     high speed    |       high speed  |   mode
------------|-------------------|-------------------|----------------------
-IIC0_CLOCK7 |prohibited/fexscl0 |       prohibited  |   selection clock(fw)
-            |       fw/18       |                   |   transfer clock
-            |     high speed    |                   |   mode
------------|-------------------|-------------------|----------------------
-*/
-
-#define ADDRESS_COMPLETE   			0x80
-#define IIC_MASTER_FLAG_CLEAR 		0x00
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/incs.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/incs.h
@ -1,36 +0,0 @@
-#pragma SFR
-#pragma di
-#pragma ei
-#pragma nop
-#pragma stop
-#pragma halt
-
-#pragma section @@CODE ROM_CODE
-//#pragma section @@CNST ROM_CNST
-
-//=========================================================
-#ifndef _incs_h_
-#define _incs_h_
-
-#define _mcu_
-
-#include "jhl_defs.h"
-#include "user_define.h"
-
-#include "bsr_system.h"
-#include "renge.h"
-
-#include "vreg_ctr.h"
-#include "vreg_twl.h"
-
-#include "i2c_mcu.h"
-
-#include "rtc.h"
-
-#include "accero.h"
-
-
-//=========================================================
-err firm_update(  );
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/incs_loader.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/incs_loader.h
@ -1,38 +0,0 @@
-#pragma SFR
-#pragma di
-#pragma ei
-#pragma nop
-#pragma stop
-#pragma halt
-
-
-#pragma section @@CODE       LDR_CODE
-#pragma section @@CODEL      LDR_CODL
-
-//#pragma section @@R_INIT     FSL_RINT  // これやるとスタートアップルーチンが初期値を
-//#pragma section @@CNST       FSL_CNST  // セットしてくれない
-#pragma section @@CNSTL      LDR_CNSL
-
-
-
-//=========================================================
-#include "jhl_defs.h"
-#include "user_define.h"
-
-#include "bsr_system.h"
-#include "renge.h"
-
-#include "vreg_ctr.h"
-#include "vreg_twl.h"
-
-#include "loader.h"
-
-#include "i2c_mcu.h"
-
-#include "WDT.h"
-
-
-
-//=========================================================
-err firm_update(  );
-err firm_restore(  );
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.c
@ -1,283 +0,0 @@
-#pragma nop
-
-
-#include "config.h"
-
-//#pragma interrupt INTWDTI     fn_intwdti  // 未使用
-//#pragma interrupt INTLVI      fn_intlvi   // 未使用
-
-//#pragma interrupt INTP0		intp0_slp       // SLP (CPUより、要求) ポーリング
-//#pragma interrupt INTP1               fn_intp1 // (I2C)
-//#pragma interrupt INTP2               fn_intp2 // (I2C)
-//#pragma interrupt INTP3               fn_intp3 // 未搭載
-#pragma interrupt INTP4		intp4_extdc     // EXTDC, ただし電源offから起こすのみ。通常はポーリング
-#pragma interrupt INTP5		intp5_shell     // SHELL_CLOSE, ただし電源offから起こすのみ。通常はポーリング
-#pragma interrupt INTP6		intp6_PM_irq    // CODEC経由で旧PMICへのコマンド書き込み
-
-//#ifdef _MCU_BSR_                          // 割り込みそのものは使いません
-//#pragma interrupt INTP21	intp21_RFTx     // 電波送信パルス
-//#else
-//#pragma interrupt INTP7		intp21_RFTx
-//#endif
-
-#ifdef _MCU_BSR_
-#pragma interrupt INTP23	intp23_ACC_ready        // 加速度センサ、データ準備完了
-#endif
-
-//#pragma interrupt INTCMP0     fn_intcmp0
-//#pragma interrupt INTCMP1     fn_intcmp1
-//#pragma interrupt INTDMA0     fn_intdma0
-#pragma interrupt INTDMA1	int_dma1
-
-//#pragma interrupt INTST0      fn_intst0
-/* #pragma interrupt INTCSI00	fn_intcsi00 */
-//#pragma interrupt INTSR0      fn_intsr0
-/* #pragma interrupt INTCSI01	fn_intcsi01 */
-//#pragma interrupt INTSRE0     fn_intsre0
-
-//#pragma interrupt INTST1      fn_intst1
-/* #pragma interrupt INTCSI10	fn_intcsi10 */
-#pragma interrupt INTIIC10	int_iic10
-//#pragma interrupt INTSR1      fn_intsr1
-//#pragma interrupt INTSRE1     fn_intsre1
-
-
-#ifdef _MCU_KE3_
-#pragma interrupt INTIICA	int_iic_ctr     // CTR側
-#else
-
-// TSはマザボでテレコ、WMは回路図がテレコで結局一致…
-#pragma interrupt INTIICA0	int_iic_twl
-#pragma interrupt INTIICA1	int_iic_ctr
-#endif
-
-//#pragma interrupt INTTM00     fn_inttm00
-//#pragma interrupt INTTM01     fn_inttm01
-//#pragma interrupt INTTM02     fn_inttm02
-//#pragma interrupt INTTM03     fn_inttm03
-
-#pragma interrupt INTAD		int_adc
-#pragma interrupt INTRTC	int_rtc
-#pragma interrupt INTRTCI	int_rtc_int
-#pragma interrupt INTKR		int_kr
-//#pragma interrupt INTMD               fn_intmd
-
-//#pragma interrupt INTTM04     fn_inttm04
-//#pragma interrupt INTTM05     fn_inttm05
-//#pragma interrupt INTTM06     fn_inttm06
-//#pragma interrupt INTTM07     fn_inttm07
-
-
-/****************************************************/
-/*  未使用時のダミー関数定義                        */
-/****************************************************/
-__interrupt void fn_intwdti(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_intlvi(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_intp0(){
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_intp1(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}                               //
-__interrupt void fn_intp2(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_intp3(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-
-__interrupt void intp21_RFTx(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-
-//__interrupt   void    fn_intp4(){ while(1){} } // pm.c
-//__interrupt   void    fn_intp5(){ while(1){} } // pm.c
-//__interrupt   void    fn_intp6(){ while(1){} } // pm.c
-//__interrupt   void    fn_intp7(){ while(1){} } // led.c
-//__interrupt   void    fn_intp21(){ while(1){} } // led.c
-
-__interrupt void fn_intcmp0(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_intcmp1(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_intdma0(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-//__interrupt   void    fn_intdma1(){}  // i2c_mcu.cにある
-
-__interrupt void fn_intst0(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-/* __interrupt	void	fn_intcsi00(){} */
-__interrupt void fn_intsr0(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-/* __interrupt	void	fn_intcsi01(){} */
-__interrupt void fn_intsre0(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_intst1(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-/* __interrupt	void	fn_intcsi10(){} */
-//__interrupt   void    fn_intiic10(){ while(1){} }
-__interrupt void fn_intsr1(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_intsre1(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-//__interrupt   void    fn_intiica(){} // i2c.cにある
-/* __interrupt	void	fn_inttm00(){} *//* sub.cにて定義 */
-__interrupt void fn_inttm01(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_inttm02(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-__interrupt void fn_inttm03(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-//__interrupt   void    fn_intad(){ while(1){} }  // adc.c
-__interrupt void fn_intrtc(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-//__interrupt   void    int_rtcint(){} // rtc.cにある
-//__interrupt   void    fn_intkr(){}  // main.c
-__interrupt void fn_intmd(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_inttm04(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_inttm05(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_inttm06(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
-
-__interrupt void fn_inttm07(  )
-{
-    while( 1 )
-    {
-        NOP();
-    }
-}
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/ini_VECT.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/WDT.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/WDT.asm
@ -1,111 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no WDT.c
-; In-file   : WDT.c
-; Asm-file  : inter_asm\WDT.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		019H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, WDT.c
-$DGS	MOD_NAM, WDT,		00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CNSL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	GLV_SYM, _WDT_Restart,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	019H,	00H,	00H
-$DGS	BEG_FUN, ??bf_WDT_Restart,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0CH,		00H,	019H
-$DGS	END_FUN, ??ef_WDT_Restart,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 03H
-
-	PUBLIC	_WDT_Restart
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-LDR_CNSL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : #pragma sfr
-; line     2 : 
-; line     3 : 
-; line     4 : #include "incs_loader.h"
-; line     5 : 
-; line     6 : 
-; line     7 : 
-; line     8 : //=========================================================
-; line     9 : // ウォッチドッグタイマのリスタート
-; line    10 : //   0xACはマジック
-; line    11 : void WDT_Restart( void )
-; line    12 : {
-
-LDR_CODE	CSEG	BASE
-_WDT_Restart:
-$DGL	1,19
-??bf_WDT_Restart:
-; line    13 :     WDTE = WDT_RESTART_MAGIC;
-$DGL	0,2
-	mov	WDTE,#0ACH	; 172 				;[INF] 3, 1
-; line    14 : }
-$DGL	0,3
-??ef_WDT_Restart:
-	ret							;[INF] 1, 6
-??ee_WDT_Restart:
-
-LDR_CODL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\WDT.c
-;
-; $FUNC WDT_Restart(12)
-;	void=(void)
-;	CODE SIZE= 4 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/accero.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/accero.asm
@ -1,984 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no accero.c
-; In-file   : accero.c
-; Asm-file  : inter_asm\accero.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		0B7H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, accero.c
-$DGS	MOD_NAM, accero,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	ENM_TAG, _pwr_state_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		01EH
-$DGS	MEB_ENM, _OFF_TRIG,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _OFF,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON_TRIG,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON,		03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP_TRIG,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _BT_CHARGE,	06H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 013H,		01H
-$DGS	ENM_TAG, _poweron_reason_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		025H
-$DGS	MEB_ENM, _NONE,		00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _PWSW,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _RTC_ALARM,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 01EH,		01H
-$DGS	ENM_TAG, _model_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		02FH
-$DGS	MEB_ENM, _MODEL_JIKKI,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_TS_BOARD,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_SHIROBAKO,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED1,	03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED2,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED3,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 025H,		01H
-$DGS	STR_STR, .0fake,	00H,	0FFFEH,	08H,	0AH,	01H,	00H
-$DGS	AUX_TAG, 04H,		041H
-$DGS	MEB_STR, _pwr_state,	00H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 013H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	MEB_STR, _poweron_reason,	01H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 01EH,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BIT_FLD, _dipsw0,	010H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw1,	011H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw2,	012H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _reboot,	013H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	MEB_STR, _model,	03H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 025H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	END_STR, .eos,		04H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 02FH,		04H
-$DGS	ENM_TAG, .2fake,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		047H
-$DGS	MEB_ENM, _ERR_FINISED,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ERR_CONTINUE,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 041H,		01H
-$DGS	LAB_SYM, bs_F0038,	U,	U,	00H,	06H,	00H,	00H
-$DGS	LAB_SYM, es_F0038,	U,	U,	00H,	06H,	00H,	00H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_cbk_accero,	U,	U,	0AH,	026H,	01H,	02H
-$DGS	AUX_FUN, 041H,		U,	U,	067H,	00H,	00H
-$DGS	BEG_FUN, ??bf_tsk_cbk_accero,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 042H,		06H,	04FH
-$DGS	BEG_BLK, ??bb00_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0EH,		00H,	053H
-$DGS	END_BLK, ??eb00_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 014H
-$DGS	BEG_BLK, ??bb01_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 016H,		00H,	055H
-$DGS	BEG_BLK, ??bb02_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01CH,		00H,	057H
-$DGS	BEG_BLK, ??bb03_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 020H,		00H,	05FH
-$DGS	AUT_VAR, _temp,		00H,	0FFFFH,	0CH,	01H,	01H,	03H
-$DGS	AUX_STR, 00H,		021H,	06H,	06H,	00H,	00H,	00H,	00H
-$DGS	END_BLK, ??eb03_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 023H
-$DGS	END_BLK, ??eb02_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 024H
-$DGS	BEG_BLK, ??bb04_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 029H,		00H,	00H
-$DGS	END_BLK, ??eb04_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02DH
-$DGS	END_BLK, ??eb01_tsk_cbk_accero,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02EH
-$DGS	END_FUN, ??ef_tsk_cbk_accero,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 030H
-$DGS	GLV_SYM, _acc_read,	U,	U,	0AH,	026H,	01H,	02H
-$DGS	AUX_FUN, 041H,		U,	U,	075H,	00H,	00H
-$DGS	BEG_FUN, ??bf_acc_read,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 07BH,		00H,	06BH
-$DGS	BEG_BLK, ??bb00_acc_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	06DH
-$DGS	BEG_BLK, ??bb01_acc_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07H,		00H,	00H
-$DGS	END_BLK, ??eb01_acc_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07H
-$DGS	END_BLK, ??eb00_acc_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 08H
-$DGS	END_FUN, ??ef_acc_read,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 0AH
-$DGS	GLV_SYM, _acc_write,	U,	U,	0AH,	026H,	01H,	02H
-$DGS	AUX_FUN, 041H,		U,	U,	083H,	00H,	00H
-$DGS	BEG_FUN, ??bf_acc_write,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 08CH,		00H,	079H
-$DGS	BEG_BLK, ??bb00_acc_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 05H,		00H,	07BH
-$DGS	BEG_BLK, ??bb01_acc_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	00H
-$DGS	END_BLK, ??eb01_acc_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 06H
-$DGS	END_BLK, ??eb00_acc_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07H
-$DGS	END_FUN, ??ef_acc_write,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 09H
-$DGS	GLV_SYM, _acc_hosu_set,	U,	U,	0AH,	026H,	01H,	02H
-$DGS	AUX_FUN, 041H,		U,	U,	0A5H,	00H,	00H
-$DGS	BEG_FUN, ??bf_acc_hosu_set,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 09EH,		0AH,	089H
-$DGS	AUT_VAR, _str_send_buf,	06H,	0FFFFH,	0CH,	01H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	04H,	04H,	00H,	00H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	08DH
-$DGS	END_BLK, ??eb00_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0CH
-$DGS	BEG_BLK, ??bb01_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0CH,		00H,	091H
-$DGS	END_BLK, ??eb01_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0EH
-$DGS	BEG_BLK, ??bb02_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 028H,		00H,	095H
-$DGS	END_BLK, ??eb02_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02FH
-$DGS	BEG_BLK, ??bb03_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 031H,		00H,	099H
-$DGS	END_BLK, ??eb03_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 03AH
-$DGS	BEG_BLK, ??bb04_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03FH,		00H,	09BH
-$DGS	BEG_BLK, ??bb05_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 041H,		00H,	00H
-$DGS	AUT_VAR, _temp,		00H,	0FFFFH,	0CH,	01H,	01H,	03H
-$DGS	AUX_STR, 00H,		042H,	06H,	06H,	00H,	00H,	00H,	00H
-$DGS	END_BLK, ??eb05_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 044H
-$DGS	END_BLK, ??eb04_acc_hosu_set,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 045H
-$DGS	END_FUN, ??ef_acc_hosu_set,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 047H
-$DGS	GLV_SYM, _intp23_ACC_ready,	U,	U,	0E001H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	0B7H,	00H,	00H
-$DGS	BEG_FUN, ??bf_intp23_ACC_ready,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0EDH,		016H,	0A9H
-$DGS	BEG_BLK, ??bb00_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 04H,		00H,	0ABH
-$DGS	BEG_BLK, ??bb01_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	0ADH
-$DGS	BEG_BLK, ??bb02_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 08H,		00H,	00H
-$DGS	END_BLK, ??eb02_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0AH
-$DGS	END_BLK, ??eb01_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0BH
-$DGS	END_BLK, ??eb00_intp23_ACC_ready,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0CH
-$DGS	END_FUN, ??ef_intp23_ACC_ready,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 0DH
-$DGS	GLV_SYM, _iic_mcu_read,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _system_status,	U,	U,	08H,	02H,	01H,	00H
-$DGS	AUX_STR, 02FH,		00H,	04H,	00H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _set_irq,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _pedometer,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_read_a_byte,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_write_a_byte,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_bus_status,	U,	U,	0CH,	02H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_write,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _@SEGAX,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _renge_task_immed_add,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _@SEGDE,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _@RTARG0,	U,	U,	00H,	02H,	00H,	00H
-
-	EXTRN	_iic_mcu_read
-	EXTRN	_vreg_ctr
-	EXTRN	_system_status
-	EXTRN	_set_irq
-	EXTRN	_pedometer
-	EXTRN	_iic_mcu_read_a_byte
-	EXTRN	_iic_mcu_write_a_byte
-	EXTRN	_iic_mcu_bus_status
-	EXTRN	_iic_mcu_write
-	EXTRN	_@SEGAX
-	EXTRN	_@SEGDE
-	EXTRN	_@RTARG0
-	EXTRN	_renge_task_immed_add
-	PUBLIC	_tsk_cbk_accero
-	PUBLIC	_acc_read
-	PUBLIC	_acc_write
-	PUBLIC	_acc_hosu_set
-	PUBLIC	_intp23_ACC_ready
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; Sub-Routines created by CC78K0R
-
-ROM_CODE	CSEG	BASE
-bs_F0038:
-	push	ax						;[INF] 1, 1
-	movw	ax,#06H	; 6 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#0A8H	; 168 					;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_read					;[INF] 3, 3
-	addw	sp,#06H	; 6 					;[INF] 2, 1
-	ret							;[INF] 1, 6
-es_F0038:
-
-; *** Sub-Routine Information ***
-;
-; $SUB bs_F0038
-;      CODE SIZE= 16 bytes
-
-; End of Sub-Routines
-
-; line     1 : /* ========================================================
-; line     2 : 　加速度センサ関係
-; line     3 : ・データ更新完了でデータを吸い上げ手レジスタを更新、CPUに割り込み
-; line     4 : ・フラグが立っていれば歩数カウント
-; line     5 : ・加速度センサ割り込みからタスクを登録して下さい。（I2Cの競合回避
-;              などがあるので）
-; line     6 : 
-; line     7 :  ======================================================== */
-; line     8 : #pragma SFR
-; line     9 : #pragma NOP
-; line    10 : #pragma HALT
-; line    11 : #pragma STOP
-; line    12 : #pragma ROT
-; line    13 : // rorb, rolb, rorw, rolw
-; line    14 : #pragma MUL
-; line    15 : #pragma BCD
-; line    16 : 
-; line    17 : #include "incs.h"
-; line    18 : #include <math.h>
-; line    19 : 
-; line    20 : // ========================================================
-; line    21 : // レジスタ名
-; line    22 : #define ACC_REG_WHOAMI 0x0F
-; line    23 : #define ACC_REG_CTRL1  0x20
-; line    24 : #define ACC_REG_CTRL5  0x24
-; line    25 : #define ACC_REG_X      0x28
-; line    26 : 
-; line    27 : // ビット位置
-; line    28 : #define ACC_bP_PM0    5
-; line    29 : #define ACC_bP_DR0    3
-; line    30 : 
-; line    31 : // ビット設定値
-; line    32 : #define ACC_BITS_PM_PDN   0
-; line    33 : #define ACC_BITS_PM_NORM  1
-; line    34 : #define ACC_BITS_PM_LP0R5 2
-; line    35 : #define ACC_BITS_PM_LP1   3
-; line    36 : #define ACC_BITS_PM_LP2   4
-; line    37 : #define ACC_BITS_PM_LP5   5
-; line    38 : #define ACC_BITS_PM_LP10  6
-; line    39 : 
-; line    40 : #define ACC_BITS_DR_50Hz   0
-; line    41 : #define ACC_BITS_DR_100Hz  1
-; line    42 : #define ACC_BITS_DR_400Hz  2
-; line    43 : #define ACC_BITS_DR_1000Hz 3
-; line    44 : 
-; line    45 : #define ACC_BITS_ALL_AXIS_ON 7
-; line    46 : 
-; line    47 : 
-; line    48 : #define VREG_BITMASK_ACC_CONF_ACQ  ( 1 << 0 )
-; line    49 : #define VREG_BITMASK_ACC_CONF_HOSU ( 1 << 1 )
-; line    50 : 
-; line    51 : 
-; line    52 : 
-; line    53 : 
-; line    54 : // ========================================================
-; line    55 : task_status tsk_soft_int(  );
-; line    56 : 
-; line    57 : 
-; line    58 : 
-; line    59 : /* ========================================================
-; line    60 : 　・割り込みを確認してデータを吸い上げ、レジスタに書き出します
-; line    61 :   ・本当であればコールバック関数を登録しておけばいいじゃんとなる
-;              のですが、
-; line    62 :   I2Cが使用中だったら？とか考えると私ではそこまでできないのです。
-; line    63 :   ・自動歩数計とかでも結局
-; line    64 :  ======================================================== */
-; line    65 : task_status_immed tsk_cbk_accero(  )
-; line    66 : {                               // （疑似）isrから登録されます
-
-ROM_CODE	CSEG	BASE
-_tsk_cbk_accero:
-$DGL	1,75
-	push	hl						;[INF] 1, 1
-	subw	sp,#06H						;[INF] 2, 1
-	movw	hl,sp						;[INF] 3, 1
-??bf_tsk_cbk_accero:
-; line    67 : 
-; line    68 : /*
-; line    69 :     if(( system_status.pwr_state == OFF ) || ( system_status.pwr
-;              _state == BT_CHARGE ) )
-; line    70 :     {
-; line    71 :         return ( ERR_SUCCESS );
-; line    72 :     }
-; line    73 :     else
-; line    74 :     {
-; line    75 : */
-; line    76 :         // 加速度センサデータレジスタへの反映
-; line    77 :         if( iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6
-;              , &vreg_ctr[VREG_C_ACC_XL] )
-; line    78 :         != ERR_SUCCESS )
-$DGL	0,13
-	movw	de,#loww (_vreg_ctr+69)				;[INF] 3, 1
-	push	de						;[INF] 1, 1
-	movw	ax,#06H	; 6 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#0A8H	; 168 					;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_read					;[INF] 3, 3
-	addw	sp,#06H	; 6 					;[INF] 2, 1
-	cmp0	c						;[INF] 1, 1
-	bz	$?L0003						;[INF] 2, 4
-; line    79 :     {
-??bb00_tsk_cbk_accero:
-; line    80 :         // 加速度センサが異常になったので止める
-; line    81 :         vreg_ctr[VREG_C_ACC_CONFIG] &= ~( VREG_BITMASK_ACC_CONF_
-;              HOSU | VREG_BITMASK_ACC_CONF_ACQ );
-$DGL	0,16
-	movw	de,#loww (_vreg_ctr+64)				;[INF] 3, 1
-	mov	a,[de]						;[INF] 1, 1
-	and	a,#0FCH	; 252 					;[INF] 2, 1
-	mov	[de],a						;[INF] 1, 1
-; line    82 : //        vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
-; line    83 :         acc_hosu_set();
-$DGL	0,18
-	call	!_acc_hosu_set					;[INF] 3, 3
-; line    84 :         return ( ERR_SUCCESS ); // タスクの削除は必要
-$DGL	0,19
-	clrw	bc						;[INF] 1, 1
-	br	$?L0002						;[INF] 2, 3
-??eb00_tsk_cbk_accero:
-; line    85 :     }
-?L0003:
-; line    86 :     else
-; line    87 :         {
-??bb01_tsk_cbk_accero:
-; line    88 :         // 正常時パス //
-; line    89 :         // 加速度更新＆割り込み
-; line    90 :         if( (( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO
-;              NF_ACQ ) != 0 ) &&
-$DGL	0,25
-	mov	a,!_vreg_ctr+64					;[INF] 3, 1
-	and	a,#01H	; 1 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0007						;[INF] 2, 4
-; line    91 :             ( system_status.pwr_state == ON )
-$DGL	0,26
-	cmp	!_system_status,#03H	; 3 			;[INF] 4, 1
-	bnz	$?L0007						;[INF] 2, 4
-; line    92 :             )
-; line    93 :             {
-??bb02_tsk_cbk_accero:
-; line    94 :                 set_irq( VREG_C_IRQ1, REG_BIT_ACC_DAT_RDY );
-$DGL	0,29
-	movw	ax,#010H	; 16 				;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	incw	ax						;[INF] 1, 1
-	call	!_set_irq					;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line    95 :             // ゴミデータのカラ読み
-; line    96 :             if( ACC_VALID == 1 )
-$DGL	0,31
-	push	hl						;[INF] 1, 1
-	movw	hl,#0510H	; 1296 				;[INF] 3, 1
-	mov1	CY,[hl].5					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0007						;[INF] 2, 4
-; line    97 :             {
-??bb03_tsk_cbk_accero:
-; line    98 :                 u8 temp[6];
-; line    99 :                 iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 
-;              ), 6, temp );
-$DGL	0,34
-	movw	ax,hl						;[INF] 1, 1
-	call	!bs_F0038					;[INF] 3, 3
-??eb03_tsk_cbk_accero:
-; line   100 :             }
-?L0007:
-??eb02_tsk_cbk_accero:
-; line   101 :         }
-; line   102 :         if(( system_status.pwr_state != OFF ) &&
-; line   103 :            ( system_status.pwr_state != BT_CHARGE ) &&
-$DGL	0,38
-	cmp	!_system_status,#01H	; 1 			;[INF] 4, 1
-	bz	$?L0009						;[INF] 2, 4
-	cmp	!_system_status,#06H	; 6 			;[INF] 4, 1
-	bz	$?L0009						;[INF] 2, 4
-; line   104 :            ( ( vreg_ctr[VREG_C_ACC_CONFIG] & VREG_BITMASK_ACC_CO
-;              NF_HOSU ) != 0 )
-$DGL	0,39
-	mov	a,!_vreg_ctr+64					;[INF] 3, 1
-	and	a,#02H	; 2 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	skz							;[INF] 2, 1
-; line   105 :            )
-; line   106 :         {
-??bb04_tsk_cbk_accero:
-; line   107 :     DBG_LED_WIFI_2_on;
-; line   108 :     pedometer();    // 歩数計
-$DGL	0,43
-	call	!_pedometer					;[INF] 3, 3
-; line   109 :     DBG_LED_WIFI_2_off;
-??eb04_tsk_cbk_accero:
-; line   110 :         }
-?L0009:
-??eb01_tsk_cbk_accero:
-; line   111 :     }
-; line   112 :     return ( ERR_SUCCESS );
-$DGL	0,47
-	clrw	bc						;[INF] 1, 1
-; line   113 : }
-?L0002:
-$DGL	0,48
-??ef_tsk_cbk_accero:
-	addw	sp,#06H						;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_tsk_cbk_accero:
-; line   114 : 
-; line   115 : 
-; line   116 : 
-; line   117 : 
-; line   118 : 
-; line   119 : /*=======================================================
-; line   120 : 　加速度センサ透過アクセス　リード
-; line   121 :  ========================================================*/
-; line   122 : task_status_immed acc_read(  )
-; line   123 : {
-_acc_read:
-$DGL	1,103
-??bf_acc_read:
-; line   124 :     vreg_ctr[VREG_C_ACC_W_BUF] = iic_mcu_read_a_byte( IIC_SLA_AC
-;              CEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
-$DGL	0,2
-	mov	x,!_vreg_ctr+65					;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_read_a_byte				;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-	mov	a,c						;[INF] 1, 1
-	mov	!_vreg_ctr+68,a					;[INF] 3, 1
-; line   125 : //  vreg_ctr[ VREG_C_ACC_R_BUF ] = iic_mcu_read_a_byte( IIC_SLA_
-;              ACCEL, vreg_ctr[VREG_C_ACC_R_ADRS] );
-; line   126 :     vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
-$DGL	0,4
-	set1	!_vreg_ctr+17.3					;[INF] 4, 2
-; line   127 :     if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
-$DGL	0,5
-	mov	a,!_vreg_ctr+25					;[INF] 3, 1
-	and	a,#08H	; 8 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bnz	$?L0013						;[INF] 2, 4
-; line   128 :     {
-??bb00_acc_read:
-; line   129 :         IRQ0_ast;
-$DGL	0,7
-??bb01_acc_read:
-	clr1	P7.6						;[INF] 3, 2
-	clr1	PM7.6						;[INF] 3, 2
-??eb01_acc_read:
-??eb00_acc_read:
-; line   130 :     }
-?L0013:
-; line   131 :     return ( ERR_SUCCESS );
-$DGL	0,9
-	clrw	bc						;[INF] 1, 1
-; line   132 : }
-$DGL	0,10
-??ef_acc_read:
-	ret							;[INF] 1, 6
-??ee_acc_read:
-; line   133 : 
-; line   134 : 
-; line   135 : 
-; line   136 : /*=========================================================
-; line   137 : 　加速度センサ透過アクセス　ライト
-; line   138 :  ========================================================*/
-; line   139 : task_status_immed acc_write(  )
-; line   140 : {
-_acc_write:
-$DGL	1,117
-??bf_acc_write:
-; line   141 :     iic_mcu_write_a_byte( IIC_SLA_ACCEL, vreg_ctr[VREG_C_ACC_W_A
-;              DRS], vreg_ctr[VREG_C_ACC_W_BUF] );
-$DGL	0,2
-	mov	x,!_vreg_ctr+68					;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	mov	x,!_vreg_ctr+67					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_write_a_byte				;[INF] 3, 3
-	addw	sp,#04H	; 4 					;[INF] 2, 1
-; line   142 :     vreg_ctr[VREG_C_IRQ1] |= REG_BIT_ACC_ACK;
-$DGL	0,3
-	set1	!_vreg_ctr+17.3					;[INF] 4, 2
-; line   143 :     if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_ACC_ACK ) == 0 )
-$DGL	0,4
-	mov	a,!_vreg_ctr+25					;[INF] 3, 1
-	and	a,#08H	; 8 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bnz	$?L0017						;[INF] 2, 4
-; line   144 :     {
-??bb00_acc_write:
-; line   145 :         IRQ0_ast;
-$DGL	0,6
-??bb01_acc_write:
-	clr1	P7.6						;[INF] 3, 2
-	clr1	PM7.6						;[INF] 3, 2
-??eb01_acc_write:
-??eb00_acc_write:
-; line   146 :     }
-?L0017:
-; line   147 :     return ( ERR_SUCCESS );
-$DGL	0,8
-	clrw	bc						;[INF] 1, 1
-; line   148 : }
-$DGL	0,9
-??ef_acc_write:
-	ret							;[INF] 1, 6
-??ee_acc_write:
-; line   149 : 
-; line   150 : 
-; line   151 : 
-; line   152 : /*=========================================================
-; line   153 : 　自動歩数カウントモードにセット
-; line   154 :   todo 他のモードだったら止めたり、復帰させたり
-; line   155 :   割り込みルーチンなどでカウント判定が必要
-; line   156 :  ========================================================*/
-; line   157 : task_status_immed acc_hosu_set(  )
-; line   158 : {
-_acc_hosu_set:
-$DGL	1,131
-	push	hl						;[INF] 1, 1
-	subw	sp,#0AH						;[INF] 2, 1
-	movw	hl,sp						;[INF] 3, 1
-??bf_acc_hosu_set:
-; line   159 :     u8      str_send_buf[4];
-; line   160 : 
-; line   161 :     iic_mcu_read_a_byte( IIC_SLA_ACCEL, ACC_REG_WHOAMI );
-$DGL	0,4
-	movw	ax,#0FH	; 15 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_read_a_byte				;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line   162 :     if( iic_mcu_bus_status == ERR_NOSLAVE )
-$DGL	0,5
-	cmp	!_iic_mcu_bus_status,#02H	; 2 		;[INF] 4, 1
-	bnz	$?L0021						;[INF] 2, 4
-; line   163 :     {
-??bb00_acc_hosu_set:
-; line   164 :         vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_ACCERO_ERR;
-$DGL	0,7
-	set1	!_vreg_ctr+14.1					;[INF] 4, 2
-; line   165 : #ifdef _MCU_BSR_
-; line   166 : //	    PMK23 = 1;
-; line   167 : #endif
-; line   168 :         return ( ERR_SUCCESS ); // とりあえず、タスクは削除しなく
-;              てはならない
-$DGL	0,11
-	clrw	bc						;[INF] 1, 1
-	br	$?L0020						;[INF] 2, 3
-??eb00_acc_hosu_set:
-; line   169 :     }else{
-?L0021:
-??bb01_acc_hosu_set:
-; line   170 :         vreg_ctr[ VREG_C_STATUS_1 ] &= ~REG_BIT_ACCERO_ERR;
-$DGL	0,13
-	clr1	!_vreg_ctr+14.1					;[INF] 4, 2
-??eb01_acc_hosu_set:
-; line   171 :     }
-; line   172 : 
-; line   173 : 
-; line   174 :     str_send_buf[1] = 0x00;     // ctrl2  HPF:normal, filterd, H
-;              PF for IRQ : dis/dis, HPF coeff:norm
-$DGL	0,17
-	mov	[hl+7],#00H	; str_send_buf,0 		;[INF] 3, 1
-; line   175 : #ifdef _MODEL_WM0_
-; line   176 : # ifdef _MODEL_WM0_TEG2_CTRC_
-; line   177 :     str_send_buf[2] = 0x02;     //  回路が一部違う
-; line   178 : # else
-; line   179 : 
-; line   180 :     str_send_buf[2] = 0x10;     //     3  IRQ pol :Active HI, Dr
-;              ive:Pushpull,
-; line   181 :                                 ///       IRQ2flg latch: auto cl
-;              ear after read, IRQ2 conf: IRQ( fall,shock,...)
-; line   182 :                                 ///          1         : auto cl
-;              ear after read,      conf: data ready
-; line   183 : # endif
-; line   184 : #else
-; line   185 : # ifdef _MODEL_CTR_JIKKI_
-; line   186 :     str_send_buf[2] = 0x10;
-; line   187 : # else
-; line   188 :     str_send_buf[2] = 0x02;     //     3  IRQ pol :Active HI, Dr
-;              ive:Pushpull,
-$DGL	0,31
-	mov	[hl+8],#02H	; str_send_buf,2 		;[INF] 3, 1
-; line   189 :                                 ///       IRQ2flg latch: auto cl
-;              ear after read, IRQ2 conf: IRQ( fall,shock,...)
-; line   190 :                                 ///          1         : auto cl
-;              ear after read,      conf: data ready
-; line   191 : # endif
-; line   192 : #endif
-; line   193 :     str_send_buf[3] = 0x80;     // ctrl3  block update:enable, M
-;              SB first, scale: +-2G(default), selftest: dis
-$DGL	0,36
-	mov	[hl+9],#080H	; str_send_buf,128 		;[INF] 3, 1
-; line   194 : 
-; line   195 :     if( ( vreg_ctr[VREG_C_ACC_CONFIG] &
-; line   196 :           ( VREG_BITMASK_ACC_CONF_HOSU | VREG_BITMASK_ACC_CONF_A
-;              CQ ) ) == 0 )
-$DGL	0,39
-	mov	a,!_vreg_ctr+64					;[INF] 3, 1
-	and	a,#03H	; 3 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bnz	$?L0023						;[INF] 2, 4
-; line   197 :     {
-??bb02_acc_hosu_set:
-; line   198 : #ifdef _MCU_BSR_
-; line   199 : 	    PMK23 = 1;
-$DGL	0,42
-	set1	MK2H.7						;[INF] 3, 2
-; line   200 : #endif
-; line   201 :         // 完全停止
-; line   202 :         str_send_buf[0] =
-; line   203 :             ( ACC_BITS_PM_PDN << ACC_bP_PM0 | 0 << ACC_bP_DR0 | 
-;              ACC_BITS_ALL_AXIS_ON );
-$DGL	0,46
-	mov	[hl+6],#07H	; str_send_buf,7 		;[INF] 3, 1
-??eb02_acc_hosu_set:
-; line   204 :     }
-$DGL	0,47
-	br	$?L0024						;[INF] 2, 3
-?L0023:
-; line   205 :     else
-; line   206 :     {
-??bb03_acc_hosu_set:
-; line   207 : #ifdef _MCU_BSR_
-; line   208 : 	    PMK23 = 0;
-$DGL	0,51
-	clr1	MK2H.7						;[INF] 3, 2
-; line   209 : #endif
-; line   210 :         // 100Hz 自動取り込み
-; line   211 :         str_send_buf[0] =
-; line   212 :             ( ACC_BITS_PM_NORM << ACC_bP_PM0
-; line   213 :               | ACC_BITS_DR_100Hz << ACC_bP_DR0
-; line   214 :               | ACC_BITS_ALL_AXIS_ON );
-$DGL	0,57
-	mov	[hl+6],#02FH	; str_send_buf,47 		;[INF] 3, 1
-??eb03_acc_hosu_set:
-; line   215 :     }
-?L0024:
-; line   216 :     iic_mcu_write( IIC_SLA_ACCEL, ( ACC_REG_CTRL1 | 0x80 ), 4, s
-;              tr_send_buf );
-$DGL	0,59
-	movw	ax,hl						;[INF] 1, 1
-	addw	ax,#06H						;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	movw	ax,#04H	; 4 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#0A0H	; 160 					;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#030H	; 48 					;[INF] 2, 1
-	call	!_iic_mcu_write					;[INF] 3, 3
-	addw	sp,#06H	; 6 					;[INF] 2, 1
-; line   217 : 
-; line   218 :     // カラ読み
-; line   219 :     if( ACC_VALID == 1 )
-$DGL	0,62
-	push	hl						;[INF] 1, 1
-	movw	hl,#0510H	; 1296 				;[INF] 3, 1
-	mov1	CY,[hl].5					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0027						;[INF] 2, 4
-; line   220 :     {
-??bb04_acc_hosu_set:
-; line   221 :         if( system_status.pwr_state == ON )
-$DGL	0,64
-	cmp	!_system_status,#03H	; 3 			;[INF] 4, 1
-	bnz	$?L0027						;[INF] 2, 4
-; line   222 :         {
-??bb05_acc_hosu_set:
-; line   223 :             u8 temp[6];
-; line   224 :             iic_mcu_read( IIC_SLA_ACCEL, ( ACC_REG_X | 0x80 ), 6
-;              , temp );
-$DGL	0,67
-	movw	ax,hl						;[INF] 1, 1
-	call	!bs_F0038					;[INF] 3, 3
-??eb05_acc_hosu_set:
-; line   225 :         }
-?L0027:
-??eb04_acc_hosu_set:
-; line   226 :     }
-; line   227 :     return ( ERR_SUCCESS );
-$DGL	0,70
-	clrw	bc						;[INF] 1, 1
-; line   228 : }
-?L0020:
-$DGL	0,71
-??ef_acc_hosu_set:
-	addw	sp,#0AH						;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_acc_hosu_set:
-; line   229 : 
-; line   230 : 
-; line   231 : 
-; line   232 : /* ========================================================
-; line   233 :  加速度センサ割り込み
-; line   234 :   I2Cが使用中かもしれないので、読み出しタスクの登録を行うのみ
-; line   235 :  ======================================================== */
-; line   236 : __interrupt void intp23_ACC_ready(  )
-; line   237 : {
-
-@@BASE	CSEG	BASE
-_intp23_ACC_ready:
-$DGL	1,165
-	push	ax						;[INF] 1, 1
-	push	bc						;[INF] 1, 1
-	push	de						;[INF] 1, 1
-	push	hl						;[INF] 1, 1
-	mov	c,#0CH						;[INF] 2, 1
-	dec	c						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	movw	ax,_@SEGAX[c]					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	bnz	$$-6						;[INF] 2, 4
-	mov	a,ES						;[INF] 2, 1
-	mov	x,a						;[INF] 1, 1
-	mov	a,CS						;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-??bf_intp23_ACC_ready:
-; line   238 :     EI();
-$DGL	0,2
-	ei							;[INF] 3, 4
-; line   239 :     if( ( vreg_ctr[VREG_C_ACC_CONFIG] & 0x03 ) != 0x00 )
-$DGL	0,3
-	mov	a,!_vreg_ctr+64					;[INF] 3, 1
-	and	a,#03H	; 3 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0036						;[INF] 2, 4
-; line   240 :     {
-??bb00_intp23_ACC_ready:
-; line   241 :         if( ( system_status.pwr_state == ON ) || ( system_status
-;              .pwr_state == SLEEP ) )
-$DGL	0,5
-	cmp	!_system_status,#03H	; 3 			;[INF] 4, 1
-	bz	$?L0035						;[INF] 2, 4
-	cmp	!_system_status,#05H	; 5 			;[INF] 4, 1
-	bnz	$?L0036						;[INF] 2, 4
-?L0035:
-; line   242 :         {
-??bb01_intp23_ACC_ready:
-; line   243 :             if( ACC_VALID )
-$DGL	0,7
-	movw	hl,#0510H	; 1296 				;[INF] 3, 1
-	mov1	CY,[hl].5					;[INF] 2, 1
-	bnc	$?L0036						;[INF] 2, 4
-; line   244 :             {
-??bb02_intp23_ACC_ready:
-; line   245 :                 renge_task_immed_add( tsk_cbk_accero );
-$DGL	0,9
-	movw	ax,#loww (_tsk_cbk_accero)			;[INF] 3, 1
-	call	!_renge_task_immed_add				;[INF] 3, 3
-??eb02_intp23_ACC_ready:
-; line   246 :             }
-?L0036:
-??eb01_intp23_ACC_ready:
-; line   247 :         }
-??eb00_intp23_ACC_ready:
-; line   248 :     }
-; line   249 : }
-$DGL	0,13
-??ef_intp23_ACC_ready:
-	pop	ax						;[INF] 1, 1
-	mov	CS,a						;[INF] 2, 1
-	mov	a,x						;[INF] 1, 1
-	mov	ES,a						;[INF] 2, 1
-	movw	de,#_@SEGAX					;[INF] 3, 1
-	mov	c,#06H						;[INF] 2, 1
-	pop	ax						;[INF] 1, 1
-	movw	[de],ax						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$$-5						;[INF] 2, 4
-	pop	hl						;[INF] 1, 1
-	pop	de						;[INF] 1, 1
-	pop	bc						;[INF] 1, 1
-	pop	ax						;[INF] 1, 1
-	reti							;[INF] 2, 6
-??ee_intp23_ACC_ready:
-
-@@CODEL	CSEG
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\accero.c
-;
-; $FUNC tsk_cbk_accero(66)
-;	bc=(void)
-;	CODE SIZE= 104 bytes, CLOCK_SIZE= 103 clocks, STACK_SIZE= 22 bytes
-;
-; $CALL iic_mcu_read(78)
-;	bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
-;
-; $CALL acc_hosu_set(83)
-;	bc=(void)
-;
-; $CALL set_irq(94)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL iic_mcu_read(99)
-;	bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
-;
-; $CALL pedometer(108)
-;	void=(void)
-;
-; $FUNC acc_read(123)
-;	bc=(void)
-;	CODE SIZE= 35 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 6 bytes
-;
-; $CALL iic_mcu_read_a_byte(124)
-;	bc=(int:ax, int:[sp+4])
-;
-; $FUNC acc_write(140)
-;	bc=(void)
-;	CODE SIZE= 36 bytes, CLOCK_SIZE= 30 clocks, STACK_SIZE= 8 bytes
-;
-; $CALL iic_mcu_write_a_byte(141)
-;	bc=(int:ax, int:[sp+4], int:[sp+6])
-;
-; $FUNC acc_hosu_set(158)
-;	bc=(void)
-;	CODE SIZE= 107 bytes, CLOCK_SIZE= 96 clocks, STACK_SIZE= 26 bytes
-;
-; $CALL iic_mcu_read_a_byte(161)
-;	bc=(int:ax, int:[sp+4])
-;
-; $CALL iic_mcu_write(216)
-;	bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
-;
-; $CALL iic_mcu_read(224)
-;	bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
-;
-; $FUNC intp23_ACC_ready(237)
-;	void=(void)
-;	CODE SIZE= 80 bytes, CLOCK_SIZE= 73 clocks, STACK_SIZE= 26 bytes
-;
-; $CALL renge_task_immed_add(245)
-;	bc=(pointer:ax)
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/adc.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/adc.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_ctr.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_ctr.asm
@ -1,920 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_ctr.c
-; In-file   : i2c_ctr.c
-; Asm-file  : inter_asm\i2c_ctr.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		07CH,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, i2c_ctr.c
-$DGS	MOD_NAM, i2c_ctr,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _int_iic_ctr,	U,	U,	0E001H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	070H,	00H,	00H
-$DGS	BEG_FUN, ??bf_int_iic_ctr,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 041H,		016H,	01EH
-$DGS	STA_SYM, _state,	?L0003,	U,	0CH,	03H,	00H,	00H
-$DGS	STA_SYM, _reg_adrs,	?L0004,	U,	0CH,	03H,	00H,	00H
-$DGS	STA_SYM, _reg_adrs_internal,	?L0005,	U,	0CH,	03H,	00H,	00H
-$DGS	STA_SYM, _tx_buf,	?L0006,	U,	0CH,	03H,	00H,	00H
-$DGS	REG_VAR, _rx_buf,	06H,	0FFFFH,	010CH,	04H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0CH,		00H,	020H
-$DGS	BEG_BLK, ??bb01_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 014H,		00H,	022H
-$DGS	BEG_BLK, ??bb02_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 015H,		00H,	026H
-$DGS	END_BLK, ??eb02_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 015H
-$DGS	BEG_BLK, ??bb03_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01BH,		00H,	028H
-$DGS	BEG_BLK, ??bb04_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01CH,		00H,	02CH
-$DGS	END_BLK, ??eb04_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01CH
-$DGS	BEG_BLK, ??bb05_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01DH,		00H,	036H
-$DGS	END_BLK, ??eb05_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01DH
-$DGS	END_BLK, ??eb03_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01EH
-$DGS	END_BLK, ??eb01_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01FH
-$DGS	END_BLK, ??eb00_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 026H
-$DGS	BEG_BLK, ??bb06_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02AH,		00H,	03AH
-$DGS	END_BLK, ??eb06_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 030H
-$DGS	BEG_BLK, ??bb07_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 033H,		00H,	03CH
-$DGS	BEG_BLK, ??bb08_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 037H,		00H,	042H
-$DGS	END_BLK, ??eb08_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 03AH
-$DGS	END_BLK, ??eb07_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 03BH
-$DGS	BEG_BLK, ??bb09_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03EH,		00H,	044H
-$DGS	BEG_BLK, ??bb0A_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 04CH,		00H,	048H
-$DGS	END_BLK, ??eb0A_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 04EH
-$DGS	BEG_BLK, ??bb0B_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 050H,		00H,	04CH
-$DGS	END_BLK, ??eb0B_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 052H
-$DGS	BEG_BLK, ??bb0C_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 059H,		00H,	04EH
-$DGS	BEG_BLK, ??bb0D_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 05CH,		00H,	052H
-$DGS	END_BLK, ??eb0D_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 05FH
-$DGS	BEG_BLK, ??bb0E_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 061H,		00H,	058H
-$DGS	END_BLK, ??eb0E_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 067H
-$DGS	END_BLK, ??eb0C_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 068H
-$DGS	BEG_BLK, ??bb0F_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06AH,		00H,	05CH
-$DGS	END_BLK, ??eb0F_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 06DH
-$DGS	BEG_BLK, ??bb10_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 071H,		00H,	060H
-$DGS	END_BLK, ??eb10_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 074H
-$DGS	BEG_BLK, ??bb11_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 076H,		00H,	064H
-$DGS	END_BLK, ??eb11_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07AH
-$DGS	BEG_BLK, ??bb12_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	068H
-$DGS	END_BLK, ??eb12_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	BEG_BLK, ??bb13_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 083H,		00H,	00H
-$DGS	END_BLK, ??eb13_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 085H
-$DGS	END_BLK, ??eb09_int_iic_ctr,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 087H
-$DGS	END_FUN, ??ef_int_iic_ctr,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 088H
-$DGS	GLV_SYM, _IIC_ctr_Init,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	076H,	00H,	00H
-$DGS	BEG_FUN, ??bf_IIC_ctr_Init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0CEH,		00H,	076H
-$DGS	END_FUN, ??ef_IIC_ctr_Init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 02CH
-$DGS	GLV_SYM, _IIC_ctr_Stop,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	07CH,	00H,	00H
-$DGS	BEG_FUN, ??bf_IIC_ctr_Stop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0FFH,		00H,	07CH
-$DGS	END_FUN, ??ef_IIC_ctr_Stop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 04H
-$DGS	GLV_SYM, _iic_burst_state,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _@SEGAX,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _irq_readed,	U,	U,	034CH,	02H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _hosu_read_end,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _rtc_unlock,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr_read,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr_after_read,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr_write,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _@SEGDE,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _@RTARG0,	U,	U,	00H,	02H,	00H,	00H
-
-	EXTRN	_@SEGAX
-	EXTRN	_@SEGDE
-	EXTRN	_@RTARG0
-	EXTRN	_vreg_ctr
-	EXTRN	_hosu_read_end
-	EXTRN	_rtc_unlock
-	EXTRN	_vreg_ctr_read
-	EXTRN	_vreg_ctr_after_read
-	EXTRN	_vreg_ctr_write
-	EXTBIT	_irq_readed
-	PUBLIC	_iic_burst_state
-	PUBLIC	_int_iic_ctr
-	PUBLIC	_IIC_ctr_Init
-	PUBLIC	_IIC_ctr_Stop
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-	DB	00H	; 0
-	DB	(1)
-
-@@INIT	DSEG	BASEP
-?L0003:	DS	(1)
-	DS	(1)
-
-@@DATA	DSEG	BASEP
-_iic_burst_state:	DS	(1)
-?L0004:	DS	(1)
-?L0005:	DS	(1)
-?L0006:	DS	(1)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : /* ========================================================
-; line     2 :   対SoC 新規チャンネル I2C通信
-; line     3 :     藤田＠開技.nintendo
-; line     4 : 	'09 Apr
-; line     5 :  ======================================================== */
-; line     6 : #include "incs.h"
-; line     7 : #include "accero.h"
-; line     8 : 
-; line     9 : #ifdef _MCU_BSR_
-; line    10 : // #ifdef _MODEL_TS0_ || _MODEL_WM0_
-; line    11 : 
-; line    12 : // ワーキングモデルはI2Cが逆
-; line    13 : // TEGは回路図でテレコ
-; line    14 : #define ACKD       ACKD1
-; line    15 : #define ACKE       ACKE1
-; line    16 : #define COI        COI1
-; line    17 : #define IICAEN     IICA1EN
-; line    18 : #define IICRSV     IICRSV1
-; line    19 : #define IICA       IICA1
-; line    20 : #define IICAIF     IICAIF1
-; line    21 : #define IICAMK     IICAMK1
-; line    22 : #define IICAPR0    IICAPR11
-; line    23 : #define IICAPR1    IICAPR01
-; line    24 : #define IICCTL0    IICCTL10
-; line    25 : #define IICE       IICE1
-; line    26 : #define IICF       IICF1
-; line    27 : #define IICS       IICS1
-; line    28 : #define IICWH      IICWH1
-; line    29 : #define IICWL      IICWL1
-; line    30 : #define LREL       LREL1
-; line    31 : #define SPD        SPD1
-; line    32 : #define SPIE       SPIE1
-; line    33 : #define STCEN      STCEN1
-; line    34 : #define STD        STD1
-; line    35 : #define SVA        SVA1
-; line    36 : #define WREL       WREL1
-; line    37 : #define WTIM       WTIM1
-; line    38 : #define TRC        TRC1
-; line    39 : #define SMC        SMC1
-; line    40 : #define DFC        DFC1
-; line    41 : 
-; line    42 : 
-; line    43 : #endif
-; line    44 : 
-; line    45 : // ==============================================
-; line    46 : extern bit irq_readed;                 // いずれかのIRQレジスタが
-;              読まれた
-; line    47 : 
-; line    48 : u8 iic_burst_state;
-; line    49 : 
-; line    50 : 
-; line    51 : /* ========================================================
-; line    52 :  ======================================================== */
-; line    53 : enum
-; line    54 : {
-; line    55 :     IIC_IDLE = 0,
-; line    56 :     IIC_RCV_REG_ADRS,
-; line    57 :     IIC_TX_OR_RX,
-; line    58 :     IIC_TX,
-; line    59 :     IIC_RX
-; line    60 : };
-; line    61 : 
-; line    62 : 
-; line    63 : // 1バイト送受の度に割り込みが発生するバージョン
-; line    64 : __interrupt void int_iic_ctr(  )
-; line    65 : {
-
-@@BASE	CSEG	BASE
-_int_iic_ctr:
-$DGL	1,21
-	push	ax						;[INF] 1, 1
-	push	bc						;[INF] 1, 1
-	push	de						;[INF] 1, 1
-	push	hl						;[INF] 1, 1
-	mov	c,#0CH						;[INF] 2, 1
-	dec	c						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	movw	ax,_@SEGAX[c]					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	bnz	$$-6						;[INF] 2, 4
-	mov	a,ES						;[INF] 2, 1
-	mov	x,a						;[INF] 1, 1
-	mov	a,CS						;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-??bf_int_iic_ctr:
-; line    66 :     static u8 state = IIC_IDLE;
-; line    67 :     static u8 reg_adrs;
-; line    68 :     static u8 reg_adrs_internal;
-; line    69 :     static u8 tx_buf;
-; line    70 :     u8 rx_buf;
-; line    71 : 
-; line    72 :     EI();
-$DGL	0,8
-	ei							;[INF] 3, 4
-; line    73 : 
-; line    74 :     // 読み出し終了
-; line    75 :     if( !ACKD )                 // 割り込み要因はNAK（データ送信
-;              の最後）
-$DGL	0,11
-	push	hl						;[INF] 1, 1
-	movw	hl,#0541H	; 1345 				;[INF] 3, 1
-	mov1	CY,[hl].2					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bc	$?L0007						;[INF] 2, 4
-; line    76 :     {
-??bb00_int_iic_ctr:
-; line    77 :         state = IIC_IDLE;
-$DGL	0,13
-	clrb	!?L0003	; state 				;[INF] 3, 1
-; line    78 :         SPIE = 0;
-$DGL	0,14
-	clr1	!IICCTL01.4					;[INF] 4, 2
-; line    79 :         LREL = 1;
-$DGL	0,15
-	set1	!IICCTL01.6					;[INF] 4, 2
-; line    80 : 
-; line    81 :         // レジスタリードで、割り込みピンをネゲート
-; line    82 :         // まだ読まれてない割り込みがあれば、再度アサート
-; line    83 :         if( irq_readed )
-$DGL	0,19
-	bf	_irq_readed,$?L0011				;[INF] 4, 5
-; line    84 :         {
-??bb01_int_iic_ctr:
-; line    85 :             IRQ0_neg;
-$DGL	0,21
-??bb02_int_iic_ctr:
-	set1	PM7.6						;[INF] 3, 2
-??eb02_int_iic_ctr:
-; line    86 :             irq_readed = 0;
-$DGL	0,22
-	clr1	_irq_readed					;[INF] 3, 2
-; line    87 :             if( !( ( vreg_ctr[VREG_C_IRQ0] == 0 )
-; line    88 :                    && ( vreg_ctr[VREG_C_IRQ1] == 0 )
-; line    89 :                    && ( vreg_ctr[VREG_C_IRQ2] == 0 )
-; line    90 :                    && ( vreg_ctr[VREG_C_IRQ3] == 0 ) ) )
-$DGL	0,26
-	cmp0	!_vreg_ctr+16					;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-	cmp0	!_vreg_ctr+17					;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-	cmp0	!_vreg_ctr+18					;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-	cmp0	!_vreg_ctr+19					;[INF] 3, 1
-	bz	$?L0011						;[INF] 2, 4
-?L0013:
-; line    91 :             {
-??bb03_int_iic_ctr:
-; line    92 :                 while( !IRQ0 ){;}  // 時間稼ぎ不要かも
-$DGL	0,28
-	bt	P7.6,$?L0015					;[INF] 4, 5
-??bb04_int_iic_ctr:
-??eb04_int_iic_ctr:
-	br	$?L0013						;[INF] 2, 3
-?L0015:
-; line    93 :                 IRQ0_ast;
-$DGL	0,29
-??bb05_int_iic_ctr:
-	clr1	P7.6						;[INF] 3, 2
-	clr1	PM7.6						;[INF] 3, 2
-??eb05_int_iic_ctr:
-??eb03_int_iic_ctr:
-; line    94 :             }
-?L0011:
-??eb01_int_iic_ctr:
-; line    95 :         }
-; line    96 : 
-; line    97 :         // 歩数計読み出し終了
-; line    98 :         hosu_read_end(  );
-$DGL	0,34
-	call	!_hosu_read_end					;[INF] 3, 3
-; line    99 :         rtc_unlock(  );
-$DGL	0,35
-	call	!_rtc_unlock					;[INF] 3, 3
-; line   100 :         iic_burst_state = 0;
-$DGL	0,36
-	clrb	!_iic_burst_state				;[INF] 3, 1
-; line   101 :         return;
-$DGL	0,37
-	br	!?L0023						;[INF] 3, 3
-??eb00_int_iic_ctr:
-; line   102 :     }
-?L0007:
-; line   103 : 
-; line   104 :     if( SPD )                   // 割り込み要因はストップコンディ
-;              ション
-$DGL	0,40
-	push	hl						;[INF] 1, 1
-	movw	hl,#0541H	; 1345 				;[INF] 3, 1
-	mov1	CY,[hl].0					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0016						;[INF] 2, 4
-; line   105 :                                 // 通信の最後。↑の !ACKD に来た
-;              ときは割り込み来ない (SPIE = 0 のため )
-; line   106 :     {
-??bb06_int_iic_ctr:
-; line   107 :         state = IIC_IDLE;
-$DGL	0,43
-	clrb	!?L0003	; state 				;[INF] 3, 1
-; line   108 :         SPIE = 0;
-$DGL	0,44
-	clr1	!IICCTL01.4					;[INF] 4, 2
-; line   109 :         // I2C終了時に何かする物 //
-; line   110 :         rtc_unlock(  );
-$DGL	0,46
-	call	!_rtc_unlock					;[INF] 3, 3
-; line   111 :         return;
-$DGL	0,47
-	br	!?L0023						;[INF] 3, 3
-??eb06_int_iic_ctr:
-; line   112 :     }
-?L0016:
-; line   113 : 
-; line   114 :     if( STD )                   // 割り込み要因：スタートコンディ
-;              ション
-$DGL	0,50
-	push	hl						;[INF] 1, 1
-	movw	hl,#0541H	; 1345 				;[INF] 3, 1
-	mov1	CY,[hl].1					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0020						;[INF] 2, 4
-; line   115 :     {
-??bb07_int_iic_ctr:
-; line   116 :         if( ( state == IIC_TX ) || ( state == IIC_RX )
-; line   117 :             || ( state == IIC_RCV_REG_ADRS )
-$DGL	0,53
-	cmp	!?L0003,#03H	; state,3 			;[INF] 4, 1
-	bz	$?L0022						;[INF] 2, 4
-	cmp	!?L0003,#04H	; state,4 			;[INF] 4, 1
-	bz	$?L0022						;[INF] 2, 4
-	cmp	!?L0003,#01H	; state,1 			;[INF] 4, 1
-	sknz							;[INF] 2, 1
-?L0022:
-; line   118 :             )
-; line   119 :         {
-??bb08_int_iic_ctr:
-; line   120 :             state = IIC_IDLE;
-$DGL	0,56
-	clrb	!?L0003	; state 				;[INF] 3, 1
-??eb08_int_iic_ctr:
-; line   121 :             // no break //
-; line   122 :         }
-?L0020:
-??eb07_int_iic_ctr:
-; line   123 :     }
-; line   124 : 
-; line   125 :     switch ( state )
-$DGL	0,61
-	mov	x,!?L0003	; state 			;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	onew	bc						;[INF] 1, 1
-	subw	ax,#00H	; 0 					;[INF] 3, 1
-	bz	$?L0024						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0025						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0026						;[INF] 2, 4
-	br	$?L0033						;[INF] 2, 3
-; line   126 :     {
-??bb09_int_iic_ctr:
-; line   127 :     case ( IIC_IDLE ):
-?L0024:
-; line   128 :         // 自局呼び出しに応答。
-; line   129 :         // 初期化など
-; line   130 :         SPIE = 1;
-$DGL	0,66
-	set1	!IICCTL01.4					;[INF] 4, 2
-; line   131 :         state = IIC_RCV_REG_ADRS;
-$DGL	0,67
-	oneb	!?L0003	; state 				;[INF] 3, 1
-; line   132 :         WREL = 1;               // ウェイト解除
-$DGL	0,68
-	set1	!IICCTL01.5					;[INF] 4, 2
-; line   133 :         break;
-$DGL	0,69
-	br	!?L0023						;[INF] 3, 3
-; line   134 : 
-; line   135 :     case ( IIC_RCV_REG_ADRS ):  // ２バイト目（レジスタアドレス）
-;              受信後に来る
-?L0025:
-; line   136 :         // レジスタアドレス受信
-; line   137 :         reg_adrs = IICA;
-$DGL	0,73
-	mov	a,!IICA1					;[INF] 3, 1
-	mov	!?L0004,a	; reg_adrs 			;[INF] 3, 1
-; line   138 :         tx_buf = vreg_ctr_read( reg_adrs );    // データの準備を
-;              しておく
-$DGL	0,74
-	mov	x,!?L0004	; reg_adrs 			;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	call	!_vreg_ctr_read					;[INF] 3, 3
-	mov	a,c						;[INF] 1, 1
-	mov	!?L0006,a	; tx_buf 			;[INF] 3, 1
-; line   139 :         if( reg_adrs != VREG_C_INFO )
-$DGL	0,75
-	cmp	!?L0004,#07FH	; reg_adrs,127 			;[INF] 4, 1
-	bz	$?L0030						;[INF] 2, 4
-; line   140 :         {
-??bb0A_int_iic_ctr:
-; line   141 :             state = IIC_TX_OR_RX;
-$DGL	0,77
-	mov	!?L0003,#02H	; state,2 			;[INF] 4, 1
-??eb0A_int_iic_ctr:
-; line   142 :         }
-$DGL	0,78
-	br	$?L0031						;[INF] 2, 3
-?L0030:
-; line   143 :         else
-; line   144 :         {
-??bb0B_int_iic_ctr:
-; line   145 :             state = IIC_IDLE;
-$DGL	0,81
-	clrb	!?L0003	; state 				;[INF] 3, 1
-??eb0B_int_iic_ctr:
-; line   146 :         }
-?L0031:
-; line   147 :         WREL = 1;
-$DGL	0,83
-	set1	!IICCTL01.5					;[INF] 4, 2
-; line   148 :         break;
-$DGL	0,84
-	br	$?L0023						;[INF] 2, 3
-; line   149 : 
-; line   150 :     case ( IIC_TX_OR_RX ):      // ↑の次に来る割り込み。STなら送
-;              信準備、データが来たら書き込まれ
-?L0026:
-; line   151 : //    if( TRC ){           // 送信方向フラグ で区別するのは、割り
-;              込み遅延時に不具合が起こりえる
-; line   152 :         if( STD )
-$DGL	0,88
-	push	hl						;[INF] 1, 1
-	movw	hl,#0541H	; 1345 				;[INF] 3, 1
-	mov1	CY,[hl].1					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0032						;[INF] 2, 4
-; line   153 :         {                       // スタートコンディション検出フラ
-;              グ
-??bb0C_int_iic_ctr:
-; line   154 :             // リードされる
-; line   155 :             if( COI )
-$DGL	0,91
-	push	hl						;[INF] 1, 1
-	movw	hl,#0541H	; 1345 				;[INF] 3, 1
-	mov1	CY,[hl].4					;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	bnc	$?L0034						;[INF] 2, 4
-; line   156 :             {                   // アドレス一致フラグ
-??bb0D_int_iic_ctr:
-; line   157 :                 state = IIC_TX;
-$DGL	0,93
-	mov	!?L0003,#03H	; state,3 			;[INF] 4, 1
-??eb0D_int_iic_ctr:
-; line   158 :                 // no break, no return //
-; line   159 :             }
-$DGL	0,95
-	br	$?L0033						;[INF] 2, 3
-?L0034:
-; line   160 :             else
-; line   161 :             {
-??bb0E_int_iic_ctr:
-; line   162 :                 // リスタートで違うデバイスが呼ばれた！
-; line   163 :                 state = IIC_IDLE;       // 終了処理
-$DGL	0,99
-	clrb	!?L0003	; state 				;[INF] 3, 1
-; line   164 :                 SPIE = 0;
-$DGL	0,100
-	clr1	!IICCTL01.4					;[INF] 4, 2
-; line   165 :                 LREL = 1;       // ウェイト解除?
-$DGL	0,101
-	set1	!IICCTL01.6					;[INF] 4, 2
-; line   166 :                 return;
-$DGL	0,102
-	br	$?L0023						;[INF] 2, 3
-??eb0E_int_iic_ctr:
-; line   167 :             }
-; line   168 :         }
-??eb0C_int_iic_ctr:
-?L0032:
-; line   169 :         else
-; line   170 :         {
-??bb0F_int_iic_ctr:
-; line   171 :             state = IIC_RX;     // データ1バイト受信の割り込みだ
-;              った
-$DGL	0,107
-	mov	!?L0003,#04H	; state,4 			;[INF] 4, 1
-??eb0F_int_iic_ctr:
-; line   172 :             // no break, no return //
-; line   173 :         }
-?L0033:
-; line   174 : 
-; line   175 :     default:                    // バースト R/W でここが何回も呼
-;              ばれることになる
-; line   176 :         if( state == IIC_TX )
-$DGL	0,112
-	cmp	!?L0003,#03H	; state,3 			;[INF] 4, 1
-	bnz	$?L0036						;[INF] 2, 4
-; line   177 :         {                       // 送信
-??bb10_int_iic_ctr:
-; line   178 :             IICA = tx_buf;
-$DGL	0,114
-	mov	a,!?L0006	; tx_buf 			;[INF] 3, 1
-	mov	!IICA1,a					;[INF] 3, 1
-; line   179 :             vreg_ctr_after_read( reg_adrs );    // 読んだらクリア
-;              などの処理
-$DGL	0,115
-	mov	x,!?L0004	; reg_adrs 			;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	call	!_vreg_ctr_after_read				;[INF] 3, 3
-??eb10_int_iic_ctr:
-; line   180 :         }
-$DGL	0,116
-	br	$?L0037						;[INF] 2, 3
-?L0036:
-; line   181 :         else
-; line   182 :         {                   // 受信
-??bb11_int_iic_ctr:
-; line   183 :             rx_buf = IICA;
-$DGL	0,119
-	mov	a,!IICA1					;[INF] 3, 1
-	mov	l,a						;[INF] 1, 1
-; line   184 :             vreg_ctr_write( reg_adrs, rx_buf );
-$DGL	0,120
-	movw	ax,hl						;[INF] 1, 1
-	clrb	a						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	mov	x,!?L0004	; reg_adrs 			;[INF] 3, 1
-	call	!_vreg_ctr_write				;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line   185 :             WREL = 1;
-$DGL	0,121
-	set1	!IICCTL01.5					;[INF] 4, 2
-??eb11_int_iic_ctr:
-; line   186 :         }
-?L0037:
-; line   187 :         // 
-; line   188 :         if( ( reg_adrs != VREG_C_ACC_HOSU_HIST )
-; line   189 :             && ( reg_adrs != VREG_C_INFO ) )
-$DGL	0,125
-	cmp	!?L0004,#04FH	; reg_adrs,79 			;[INF] 4, 1
-	bz	$?L0038						;[INF] 2, 4
-	cmp	!?L0004,#07FH	; reg_adrs,127 			;[INF] 4, 1
-	skz							;[INF] 2, 1
-; line   190 :         {   // この二つのレジスタは特殊なアクセス方法をする。アク
-;              セスポインタを進めない。
-??bb12_int_iic_ctr:
-; line   191 :             reg_adrs += 1;
-$DGL	0,127
-	inc	!?L0004	; reg_adrs 				;[INF] 3, 2
-??eb12_int_iic_ctr:
-; line   192 :         }
-?L0038:
-; line   193 : 
-; line   194 :         if( state == IIC_TX )
-$DGL	0,130
-	cmp	!?L0003,#03H	; state,3 			;[INF] 4, 1
-	bnz	$?L0023						;[INF] 2, 4
-; line   195 :         {                       // さらにつぎに送るデータの準備だ
-;              けシテオク。SPが来て使われないかもしれない
-??bb13_int_iic_ctr:
-; line   196 :             tx_buf = vreg_ctr_read( reg_adrs );
-$DGL	0,132
-	mov	x,!?L0004	; reg_adrs 			;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	call	!_vreg_ctr_read					;[INF] 3, 3
-	mov	a,c						;[INF] 1, 1
-	mov	!?L0006,a	; tx_buf 			;[INF] 3, 1
-??eb13_int_iic_ctr:
-; line   197 :         }
-; line   198 :         break;
-??eb09_int_iic_ctr:
-; line   199 :     }
-?L0023:
-; line   200 : }
-$DGL	0,136
-??ef_int_iic_ctr:
-	pop	ax						;[INF] 1, 1
-	mov	CS,a						;[INF] 2, 1
-	mov	a,x						;[INF] 1, 1
-	mov	ES,a						;[INF] 2, 1
-	movw	de,#_@SEGAX					;[INF] 3, 1
-	mov	c,#06H						;[INF] 2, 1
-	pop	ax						;[INF] 1, 1
-	movw	[de],ax						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$$-5						;[INF] 2, 4
-	pop	hl						;[INF] 1, 1
-	pop	de						;[INF] 1, 1
-	pop	bc						;[INF] 1, 1
-	pop	ax						;[INF] 1, 1
-	reti							;[INF] 2, 6
-??ee_int_iic_ctr:
-; line   201 : 
-; line   202 : 
-; line   203 : 
-; line   204 : // ========================================================
-; line   205 : void IIC_ctr_Init( void )
-; line   206 : {
-
-ROM_CODE	CSEG	BASE
-_IIC_ctr_Init:
-$DGL	1,112
-??bf_IIC_ctr_Init:
-; line   207 : 
-; line   208 :     IICAEN = 1;
-$DGL	0,3
-	set1	!PER3.0						;[INF] 4, 2
-; line   209 : 
-; line   210 :     IICE = 0;                   /* IICA disable */
-$DGL	0,5
-	clr1	!IICCTL01.7					;[INF] 4, 2
-; line   211 : 
-; line   212 :     IICAMK = 1;                 /* INTIICA disable */
-$DGL	0,7
-	set1	MK2H.3						;[INF] 3, 2
-; line   213 :     IICAIF = 0;                 /* clear INTIICA interrupt flag 
-;              */
-$DGL	0,8
-	clr1	IF2H.3						;[INF] 3, 2
-; line   214 : 
-; line   215 :     IICAPR0 = 1;                /* set INTIICA high priority */
-$DGL	0,10
-	set1	PR12H.3						;[INF] 3, 2
-; line   216 :     IICAPR1 = 0;                /* set INTIICA high priority */
-$DGL	0,11
-	clr1	PR02H.3						;[INF] 3, 2
-; line   217 : 
-; line   218 : #ifdef _MODEL_TEG2_
-; line   219 :     P6 &= ~0x3;
-; line   220 : #else
-; line   221 :     P20 &= ~0x3;
-$DGL	0,16
-	mov	a,!P20						;[INF] 3, 1
-	and	a,#0FCH	; 252 					;[INF] 2, 1
-	mov	!P20,a						;[INF] 3, 1
-; line   222 : #endif
-; line   223 : 
-; line   224 :     SVA = IIC_C_SLAVEADDRESS;
-$DGL	0,19
-	mov	!SVA1,#04AH	; 74 				;[INF] 4, 1
-; line   225 :     IICF = 0x01;
-$DGL	0,20
-	oneb	!IICF1						;[INF] 3, 1
-; line   226 : 
-; line   227 :     STCEN = 1;                  // リスタートの許可
-$DGL	0,22
-	set1	!IICF1.1					;[INF] 4, 2
-; line   228 :     IICRSV = 1;                 // 通信予約をさせない:スレーブに
-;              徹する
-$DGL	0,23
-	set1	!IICF1.0					;[INF] 4, 2
-; line   229 : 
-; line   230 :     SPIE = 0;                   // ストップコンディションでの割り
-;              込みを禁止
-$DGL	0,25
-	clr1	!IICCTL01.4					;[INF] 4, 2
-; line   231 :     WTIM = 1;                   // 自動でACKを返した後clkをLに固
-;              定する
-$DGL	0,26
-	set1	!IICCTL01.3					;[INF] 4, 2
-; line   232 :     ACKE = 1;                   //  ダメCPUは無視して次の通信をは
-;              じめるかもしれないんで早くclkを開放しないといけない
-$DGL	0,27
-	set1	!IICCTL01.2					;[INF] 4, 2
-; line   233 : 
-; line   234 :     IICWH = 5;
-$DGL	0,29
-	mov	!IICWH1,#05H	; 5 				;[INF] 4, 1
-; line   235 :     IICWL = 10;                 // L期間の長さ
-$DGL	0,30
-	mov	!IICWL1,#0AH	; 10 				;[INF] 4, 1
-; line   236 : 
-; line   237 :     SMC = 1;                    // 高速モード
-$DGL	0,32
-	set1	!IICCTL11.3					;[INF] 4, 2
-; line   238 :     DFC = 1;                    // デジタルフィルタon (@fast mod
-;              e)
-$DGL	0,33
-	set1	!IICCTL11.2					;[INF] 4, 2
-; line   239 : 
-; line   240 :     IICAMK = 0;                 // 割り込みを許可
-$DGL	0,35
-	clr1	MK2H.3						;[INF] 3, 2
-; line   241 : 
-; line   242 :     IICE = 1;
-$DGL	0,37
-	set1	!IICCTL01.7					;[INF] 4, 2
-; line   243 : 
-; line   244 : #ifdef _MODEL_TEG2_
-; line   245 :     PM6 &= ~0x3;                /* set clock pin for IICA */
-; line   246 : #else
-; line   247 :     PM20 &= ~0x3;                /* set clock pin for IICA */
-$DGL	0,42
-	mov	a,!PM20						;[INF] 3, 1
-	and	a,#0FCH	; 252 					;[INF] 2, 1
-	mov	!PM20,a						;[INF] 3, 1
-; line   248 : #endif
-; line   249 : }
-$DGL	0,44
-??ef_IIC_ctr_Init:
-	ret							;[INF] 1, 6
-??ee_IIC_ctr_Init:
-; line   250 : 
-; line   251 : 
-; line   252 : 
-; line   253 : // ========================================================
-; line   254 : void IIC_ctr_Stop( void )
-; line   255 : {
-_IIC_ctr_Stop:
-$DGL	1,118
-??bf_IIC_ctr_Stop:
-; line   256 :     IICE = 0;                   /* IICA disable */
-$DGL	0,2
-	clr1	!IICCTL01.7					;[INF] 4, 2
-; line   257 :     IICAEN = 0;
-$DGL	0,3
-	clr1	!PER3.0						;[INF] 4, 2
-; line   258 : }
-$DGL	0,4
-??ef_IIC_ctr_Stop:
-	ret							;[INF] 1, 6
-??ee_IIC_ctr_Stop:
-
-@@CODEL	CSEG
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_ctr.c
-;
-; $FUNC int_iic_ctr(65)
-;	void=(void)
-;	CODE SIZE= 355 bytes, CLOCK_SIZE= 278 clocks, STACK_SIZE= 28 bytes
-;
-; $CALL hosu_read_end(98)
-;	void=(void)
-;
-; $CALL rtc_unlock(99)
-;	void=(void)
-;
-; $CALL rtc_unlock(110)
-;	void=(void)
-;
-; $CALL vreg_ctr_read(138)
-;	bc=(int:ax)
-;
-; $CALL vreg_ctr_after_read(179)
-;	void=(int:ax)
-;
-; $CALL vreg_ctr_write(184)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL vreg_ctr_read(196)
-;	bc=(int:ax)
-;
-; $FUNC IIC_ctr_Init(206)
-;	void=(void)
-;	CODE SIZE= 87 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
-;
-; $FUNC IIC_ctr_Stop(255)
-;	void=(void)
-;	CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_mcu.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_mcu.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_twl.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/i2c_twl.asm
@ -1,754 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c
-; In-file   : i2c_twl.c
-; Asm-file  : inter_asm\i2c_twl.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		06FH,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, i2c_twl.c
-$DGS	MOD_NAM, i2c_twl,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _int_iic_twl,	U,	U,	0E001H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	063H,	00H,	00H
-$DGS	BEG_FUN, ??bf_int_iic_twl,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 052H,		01CH,	01BH
-$DGS	AUT_VAR, _temp,		05H,	0FFFFH,	0CH,	01H,	00H,	00H
-$DGS	AUT_VAR, _tot,		02H,	0FFFFH,	0DH,	01H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 011H,		00H,	01DH
-$DGS	BEG_BLK, ??bb01_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 011H,		00H,	01FH
-$DGS	BEG_BLK, ??bb02_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 011H,		00H,	023H
-$DGS	END_BLK, ??eb02_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	BEG_BLK, ??bb03_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 011H,		00H,	02BH
-$DGS	END_BLK, ??eb03_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	END_BLK, ??eb01_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	END_BLK, ??eb00_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	BEG_BLK, ??bb04_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01EH,		00H,	02FH
-$DGS	AUT_VAR, _my_iics,	01H,	0FFFFH,	0CH,	01H,	01H,	00H
-$DGS	AUX_STR, 00H,		01FH,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BEG_BLK, ??bb05_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 022H,		00H,	033H
-$DGS	END_BLK, ??eb05_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 025H
-$DGS	BEG_BLK, ??bb06_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 027H,		00H,	035H
-$DGS	BEG_BLK, ??bb07_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02CH,		00H,	037H
-$DGS	BEG_BLK, ??bb08_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02CH,		00H,	039H
-$DGS	BEG_BLK, ??bb09_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02CH,		00H,	03DH
-$DGS	END_BLK, ??eb09_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02CH
-$DGS	BEG_BLK, ??bb0A_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02CH,		00H,	045H
-$DGS	END_BLK, ??eb0A_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02CH
-$DGS	END_BLK, ??eb08_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02CH
-$DGS	END_BLK, ??eb07_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02CH
-$DGS	BEG_BLK, ??bb0B_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02FH,		00H,	049H
-$DGS	END_BLK, ??eb0B_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 032H
-$DGS	BEG_BLK, ??bb0C_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 035H,		00H,	04BH
-$DGS	BEG_BLK, ??bb0D_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 035H,		00H,	04DH
-$DGS	BEG_BLK, ??bb0E_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 035H,		00H,	051H
-$DGS	END_BLK, ??eb0E_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 035H
-$DGS	BEG_BLK, ??bb0F_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 035H,		00H,	05BH
-$DGS	END_BLK, ??eb0F_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 035H
-$DGS	END_BLK, ??eb0D_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 035H
-$DGS	END_BLK, ??eb0C_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 035H
-$DGS	END_BLK, ??eb06_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 03AH
-$DGS	BEG_BLK, ??bb10_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03CH,		00H,	00H
-$DGS	END_BLK, ??eb10_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 046H
-$DGS	END_BLK, ??eb04_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 047H
-$DGS	END_FUN, ??ef_int_iic_twl,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 048H
-$DGS	GLV_SYM, _IIC_twl_Init,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	069H,	00H,	00H
-$DGS	BEG_FUN, ??bf_IIC_twl_Init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 09FH,		00H,	069H
-$DGS	END_FUN, ??ef_IIC_twl_Init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 024H
-$DGS	GLV_SYM, _IIC_twl_Stop,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	06FH,	00H,	00H
-$DGS	BEG_FUN, ??bf_IIC_twl_Stop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0C8H,		00H,	06FH
-$DGS	END_FUN, ??ef_IIC_twl_Stop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 04H
-$DGS	GLV_SYM, _vreg_adrs,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _pre_dat,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _tot,		U,	U,	0DH,	026H,	00H,	00H
-$DGS	GLV_SYM, _@SEGAX,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _adrs_table_twl_ext2int,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_twl_read,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_twl_write,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _@SEGDE,	U,	U,	00H,	02H,	00H,	00H
-$DGS	GLV_SYM, _@RTARG0,	U,	U,	00H,	02H,	00H,	00H
-
-	EXTRN	_@SEGAX
-	EXTRN	_@SEGDE
-	EXTRN	_@RTARG0
-	EXTRN	_adrs_table_twl_ext2int
-	EXTRN	_vreg_twl_read
-	EXTRN	_vreg_twl_write
-	PUBLIC	_vreg_adrs
-	PUBLIC	_pre_dat
-	PUBLIC	_tot
-	PUBLIC	_int_iic_twl
-	PUBLIC	_IIC_twl_Init
-	PUBLIC	_IIC_twl_Stop
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-_vreg_adrs:	DS	(1)
-_pre_dat:	DS	(1)
-_tot:	DS	(2)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : #pragma sfr                     /* 特殊機能レジスタ使用 */
-; line     2 : 
-; line     3 : 
-; line     4 : 
-; line     5 : /*==============================================================
-;              ==============*/
-; line     6 : #include "incs.h"
-; line     7 : #include "i2c_twl_defs.h"
-; line     8 : 
-; line     9 : 
-; line    10 : extern u8 vreg_twl[];
-; line    11 : 
-; line    12 : #ifdef _MCU_BSR_
-; line    13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_
-; line    14 : 
-; line    15 : // ワーキングモデルはI2Cが逆
-; line    16 : #define ACKD       ACKD0
-; line    17 : #define ACKE       ACKE0
-; line    18 : #define COI        COI0
-; line    19 : #define IICAEN     IICA0EN
-; line    20 : #define IICRSV     IICRSV0
-; line    21 : #define IICA       IICA0
-; line    22 : #define IICAIF     IICAIF0
-; line    23 : #define IICAMK     IICAMK0
-; line    24 : #define IICAPR0    IICAPR00
-; line    25 : #define IICAPR1    IICAPR10
-; line    26 : #define IICCTL0    IICCTL00
-; line    27 : #define IICE       IICE0
-; line    28 : #define IICF       IICF0
-; line    29 : #define IICS       IICS0
-; line    30 : #define IICWH      IICWH0
-; line    31 : #define IICWL      IICWL0
-; line    32 : #define LREL       LREL0
-; line    33 : #define SPD        SPD0
-; line    34 : #define SPIE       SPIE0
-; line    35 : #define STCEN      STCEN0
-; line    36 : #define STD        STD0
-; line    37 : #define SVA        SVA0
-; line    38 : #define WREL       WREL0
-; line    39 : #define WTIM       WTIM0
-; line    40 : #define SMC        SMC0
-; line    41 : 
-; line    42 : #endif
-; line    43 : 
-; line    44 : #ifndef _MCU_BSR_
-; line    45 : 
-; line    46 : // ke3の時はダミー関数
-; line    47 : void IIC_twl_Stop( void )
-; line    48 : {
-; line    49 : }
-; line    50 : void IIC_twl_Init( void )
-; line    51 : {
-; line    52 : }
-; line    53 : #else
-; line    54 : 
-; line    55 : 
-; line    56 : /*==============================================================
-;              ==============*/
-; line    57 : u8      vreg_adrs;
-; line    58 : u8      pre_dat;
-; line    59 : 
-; line    60 : 
-; line    61 : u16     tot;
-; line    62 : 
-; line    63 : 
-; line    64 : // 注！　↓はマクロなので、returnはメインループに戻ります。
-; line    65 : #define wait_next {                                    \
-; line    66 :     tot = 0;                                             \
-; line    67 :   while( IICAIF != 1 ){                                \
-; line    68 :     if( SPD ){                                         \
-; line    69 :       LREL = 1;                                        \
-; line    70 :       return;                                          \
-; line    71 :     }                                                  \
-; line    72 :     tot++;                                             \
-; line    73 :     if( tot == 0 ){                                    \
-; line    74 :       LREL = 1;                                        \
-; line    75 :       return;                                          \
-; line    76 :     }                                                  \
-; line    77 :   }                                                    \
-; line    78 : }
-; line    79 : 
-; line    80 : 
-; line    81 : __interrupt void int_iic_twl(  )
-; line    82 : {
-
-@@BASE	CSEG	BASE
-_int_iic_twl:
-$DGL	1,21
-	push	ax						;[INF] 1, 1
-	push	bc						;[INF] 1, 1
-	push	de						;[INF] 1, 1
-	push	hl						;[INF] 1, 1
-	mov	c,#0CH						;[INF] 2, 1
-	dec	c						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	movw	ax,_@SEGAX[c]					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	bnz	$$-6						;[INF] 2, 4
-	mov	a,ES						;[INF] 2, 1
-	mov	x,a						;[INF] 1, 1
-	mov	a,CS						;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-	subw	sp,#06H						;[INF] 2, 1
-	movw	hl,sp						;[INF] 3, 1
-??bf_int_iic_twl:
-; line    83 :     u8      temp;
-; line    84 :     u16     tot;
-; line    85 : 
-; line    86 : //  WDT_Restart();
-; line    87 :     // フラグ１回目    スレーブアドレス,R/W
-; line    88 : /* COI != 1 なら、割り込みはいらない
-; line    89 :   if( COI != 1 ){               // 被呼び出し？
-; line    90 :     LREL = 1;                   // 呼ばれたのは他のID
-; line    91 :     return;
-; line    92 :   }else{
-; line    93 :     ACKE0 = 1;                // 自動でackを返すようにする
-; line    94 :     WREL = 1;                 // ウェイト解除して次のバイトを待つ
-; line    95 :   }
-; line    96 :   */
-; line    97 :     WREL = 1;                   // ウェイト解除して次のバイトを待
-;              つ
-$DGL	0,16
-	set1	!IICCTL00.5					;[INF] 4, 2
-; line    98 :     wait_next;                  // １バイト受信完了を待つ
-$DGL	0,17
-??bb00_int_iic_twl:
-	clrw	ax						;[INF] 1, 1
-	movw	[hl+2],ax	; tot 				;[INF] 2, 1
-?L0003:
-	bt	IF1L.3,$?L0004					;[INF] 4, 5
-??bb01_int_iic_twl:
-	bf	IICS0.0,$?L0005					;[INF] 4, 5
-??bb02_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	!?L0010						;[INF] 3, 3
-??eb02_int_iic_twl:
-?L0005:
-	incw	[hl+2]	; tot 					;[INF] 3, 2
-	clrw	ax						;[INF] 1, 1
-	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
-	bnz	$?L0003						;[INF] 2, 4
-??bb03_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	!?L0010						;[INF] 3, 3
-??eb03_int_iic_twl:
-??eb01_int_iic_twl:
-?L0004:
-??eb00_int_iic_twl:
-; line    99 : 
-; line   100 :     // ２回目           R/W レジスタアドレス
-; line   101 :     temp = IICA;
-$DGL	0,20
-	mov	a,IICA0						;[INF] 2, 1
-	mov	[hl+5],a	; temp 				;[INF] 2, 1
-; line   102 :     IICAIF = 0;
-$DGL	0,21
-	clr1	IF1L.3						;[INF] 3, 2
-; line   103 :     WREL = 1;
-$DGL	0,22
-	set1	!IICCTL00.5					;[INF] 4, 2
-; line   104 : 
-; line   105 :     vreg_adrs = adrs_table_twl_ext2int( temp );
-$DGL	0,24
-	mov	a,[hl+5]	; temp 				;[INF] 2, 1
-	shrw	ax,8						;[INF] 2, 1
-	call	!_adrs_table_twl_ext2int			;[INF] 3, 3
-	mov	a,c						;[INF] 1, 1
-	mov	!_vreg_adrs,a					;[INF] 3, 1
-; line   106 : 
-; line   107 :     // ３回目
-; line   108 :     // スタートコンディションか、データ受信完了フラグ待ち
-; line   109 : 
-; line   110 :     while( 1 )
-?L0009:
-; line   111 :     {
-??bb04_int_iic_twl:
-; line   112 :         u8 my_iics = IICS;
-$DGL	0,31
-	mov	a,IICS0						;[INF] 2, 1
-	mov	[hl+1],a	; my_iics 			;[INF] 2, 1
-; line   113 : 
-; line   114 :         if( my_iics & 0x01 )    // SPD
-$DGL	0,33
-	and	a,#01H	; 1 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0011						;[INF] 2, 4
-; line   115 :         {                       // 強制終了
-??bb05_int_iic_twl:
-; line   116 :             LREL = 1;
-$DGL	0,35
-	set1	!IICCTL00.6					;[INF] 4, 2
-; line   117 :             return;
-$DGL	0,36
-	br	!?L0010						;[INF] 3, 3
-??eb05_int_iic_twl:
-; line   118 :         }
-?L0011:
-; line   119 :         else if( my_iics & 0x02 )  // ( STD && !SPD )
-$DGL	0,38
-	mov	a,[hl+1]	; my_iics 			;[INF] 2, 1
-	and	a,#02H	; 2 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0013						;[INF] 2, 4
-; line   120 :         {
-??bb06_int_iic_twl:
-; line   121 :             // 送信 // (スタートコンディション検出)
-; line   122 :             pre_dat = vreg_twl_read( vreg_adrs );       // mcu内
-;              部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除
-$DGL	0,41
-	mov	x,!_vreg_adrs					;[INF] 3, 1
-	clrb	a						;[INF] 1, 1
-	call	!_vreg_twl_read					;[INF] 3, 3
-	mov	a,c						;[INF] 1, 1
-	mov	!_pre_dat,a					;[INF] 3, 1
-; line   123 : 
-; line   124 :             // 自局をRで呼ばれるのを待つ
-; line   125 :             wait_next;
-$DGL	0,44
-??bb07_int_iic_twl:
-	clrw	ax						;[INF] 1, 1
-	movw	[hl+2],ax	; tot 				;[INF] 2, 1
-?L0015:
-	bt	IF1L.3,$?L0016					;[INF] 4, 5
-??bb08_int_iic_twl:
-	bf	IICS0.0,$?L0017					;[INF] 4, 5
-??bb09_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	$?L0010						;[INF] 2, 3
-??eb09_int_iic_twl:
-?L0017:
-	incw	[hl+2]	; tot 					;[INF] 3, 2
-	clrw	ax						;[INF] 1, 1
-	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
-	bnz	$?L0015						;[INF] 2, 4
-??bb0A_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	$?L0010						;[INF] 2, 3
-??eb0A_int_iic_twl:
-; line   126 :             IICAIF = 0;
-$DGL	0,45
-??eb08_int_iic_twl:
-?L0016:
-??eb07_int_iic_twl:
-	clr1	IF1L.3						;[INF] 3, 2
-; line   127 :             if( COI != 1 )
-$DGL	0,46
-	bt	IICS0.4,$?L0021					;[INF] 4, 5
-; line   128 :             {                   // 被呼び出し？
-??bb0B_int_iic_twl:
-; line   129 :                 LREL = 1;       // 呼ばれたのは他のID（あれ？）
-$DGL	0,48
-	set1	!IICCTL00.6					;[INF] 4, 2
-; line   130 :                 return;
-$DGL	0,49
-	br	$?L0010						;[INF] 2, 3
-??eb0B_int_iic_twl:
-; line   131 :             }
-?L0021:
-; line   132 :             IICA = pre_dat;     // データを送る。ウェイトも解除さ
-;              れる。
-$DGL	0,51
-	mov	a,!_pre_dat					;[INF] 3, 1
-	mov	IICA0,a						;[INF] 2, 1
-; line   133 : 
-; line   134 :             wait_next;
-$DGL	0,53
-??bb0C_int_iic_twl:
-	clrw	ax						;[INF] 1, 1
-	movw	[hl+2],ax	; tot 				;[INF] 2, 1
-?L0023:
-	bt	IF1L.3,$?L0024					;[INF] 4, 5
-??bb0D_int_iic_twl:
-	bf	IICS0.0,$?L0025					;[INF] 4, 5
-??bb0E_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	$?L0010						;[INF] 2, 3
-??eb0E_int_iic_twl:
-?L0025:
-	incw	[hl+2]	; tot 					;[INF] 3, 2
-	clrw	ax						;[INF] 1, 1
-	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
-	bnz	$?L0023						;[INF] 2, 4
-??bb0F_int_iic_twl:
-	set1	!IICCTL00.6					;[INF] 4, 2
-	br	$?L0010						;[INF] 2, 3
-??eb0F_int_iic_twl:
-; line   135 :             // ４回目。(送信データ後の、ACK/NACK後)　どうしても発
-;              生してしまう。
-??eb0D_int_iic_twl:
-?L0024:
-??eb0C_int_iic_twl:
-; line   136 :             IICAIF = 0;         // おしまい
-$DGL	0,55
-	clr1	IF1L.3						;[INF] 3, 2
-; line   137 :             LREL = 1;
-$DGL	0,56
-	set1	!IICCTL00.6					;[INF] 4, 2
-; line   138 :             return;
-$DGL	0,57
-	br	$?L0010						;[INF] 2, 3
-??eb06_int_iic_twl:
-; line   139 :         }
-?L0013:
-; line   140 :         else if( IICAIF && (( my_iics & 0x03 ) == 0 ))   // !STD
-;               && !SPD )
-$DGL	0,59
-	bf	IF1L.3,$?L0029					;[INF] 4, 5
-	mov	a,[hl+1]	; my_iics 			;[INF] 2, 1
-	and	a,#03H	; 3 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bnz	$?L0029						;[INF] 2, 4
-; line   141 :         {
-??bb10_int_iic_twl:
-; line   142 :             // 受信 //
-; line   143 :             IICAIF = 0;
-$DGL	0,62
-	clr1	IF1L.3						;[INF] 3, 2
-; line   144 :             temp = IICA;
-$DGL	0,63
-	mov	a,IICA0						;[INF] 2, 1
-	mov	[hl+5],a	; temp 				;[INF] 2, 1
-; line   145 :             WREL = 1;
-$DGL	0,64
-	set1	!IICCTL00.5					;[INF] 4, 2
-; line   146 : 
-; line   147 :             // 通常アクセス(ライト) //
-; line   148 :             LREL = 1;           // スタートコンディション待ちへ(
-;              連続書き込み未対応のため)
-$DGL	0,67
-	set1	!IICCTL00.6					;[INF] 4, 2
-; line   149 :             vreg_twl_write( vreg_adrs, temp );
-$DGL	0,68
-	mov	a,[hl+5]	; temp 				;[INF] 2, 1
-	shrw	ax,8						;[INF] 2, 1
-	push	ax						;[INF] 1, 1
-	mov	x,!_vreg_adrs					;[INF] 3, 1
-	call	!_vreg_twl_write				;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line   150 :             return;             // 受信おしまい //
-$DGL	0,69
-	br	$?L0010						;[INF] 2, 3
-??eb10_int_iic_twl:
-; line   151 :         }
-?L0029:
-??eb04_int_iic_twl:
-; line   152 :     }
-$DGL	0,71
-	br	!?L0009						;[INF] 3, 3
-?L0010:
-; line   153 : }
-$DGL	0,72
-??ef_int_iic_twl:
-	addw	sp,#06H						;[INF] 2, 1
-	pop	ax						;[INF] 1, 1
-	mov	CS,a						;[INF] 2, 1
-	mov	a,x						;[INF] 1, 1
-	mov	ES,a						;[INF] 2, 1
-	movw	de,#_@SEGAX					;[INF] 3, 1
-	mov	c,#06H						;[INF] 2, 1
-	pop	ax						;[INF] 1, 1
-	movw	[de],ax						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$$-5						;[INF] 2, 4
-	pop	hl						;[INF] 1, 1
-	pop	de						;[INF] 1, 1
-	pop	bc						;[INF] 1, 1
-	pop	ax						;[INF] 1, 1
-	reti							;[INF] 2, 6
-??ee_int_iic_twl:
-; line   154 : 
-; line   155 : 
-; line   156 : 
-; line   157 : /*****************************************************/
-; line   158 : void IIC_twl_Init( void )
-; line   159 : {
-
-ROM_CODE	CSEG	BASE
-_IIC_twl_Init:
-$DGL	1,99
-??bf_IIC_twl_Init:
-; line   160 : 
-; line   161 :     IICAEN = 1;
-$DGL	0,3
-	set1	!PER0.4						;[INF] 4, 2
-; line   162 : 
-; line   163 :     IICE = 0;                   /* IICA disable */
-$DGL	0,5
-	clr1	!IICCTL00.7					;[INF] 4, 2
-; line   164 : 
-; line   165 :     IICAMK = 1;                 /* INTIICA disable */
-$DGL	0,7
-	set1	MK1L.3						;[INF] 3, 2
-; line   166 :     IICAIF = 0;                 /* clear INTIICA interrupt flag 
-;              */
-$DGL	0,8
-	clr1	IF1L.3						;[INF] 3, 2
-; line   167 : 
-; line   168 :     IICAPR0 = 0;                /* set INTIICA high priority */
-$DGL	0,10
-	clr1	PR01L.3						;[INF] 3, 2
-; line   169 :     IICAPR1 = 0;                /* set INTIICA high priority */
-$DGL	0,11
-	clr1	PR11L.3						;[INF] 3, 2
-; line   170 :     P20 &= ~0x3;
-$DGL	0,12
-	mov	a,!P20						;[INF] 3, 1
-	and	a,#0FCH	; 252 					;[INF] 2, 1
-	mov	!P20,a						;[INF] 3, 1
-; line   171 : 
-; line   172 :     SVA = IIC_T_SLAVEADDRESS;
-$DGL	0,14
-	mov	!SVA0,#04AH	; 74 				;[INF] 4, 1
-; line   173 :     IICF = 0x01;
-$DGL	0,15
-	oneb	!IICF0						;[INF] 3, 1
-; line   174 : 
-; line   175 :     STCEN = 1;                  // リスタートの許可
-$DGL	0,17
-	set1	IICF0.1						;[INF] 3, 2
-; line   176 :     IICRSV = 1;                 // 通信予約をさせない:スレーブに
-;              徹する
-$DGL	0,18
-	set1	IICF0.0						;[INF] 3, 2
-; line   177 : 
-; line   178 :     SPIE = 0;                   // ストップコンディションでの割り
-;              込みを禁止
-$DGL	0,20
-	clr1	!IICCTL00.4					;[INF] 4, 2
-; line   179 :     WTIM = 1;                   // 自動でACKを返した後clkをLに固
-;              定する
-$DGL	0,21
-	set1	!IICCTL00.3					;[INF] 4, 2
-; line   180 :     ACKE = 1;                   //  ダメCPUは無視して次の通信をは
-;              じめるかもしれないんで早くclkを開放しないといけない
-$DGL	0,22
-	set1	!IICCTL00.2					;[INF] 4, 2
-; line   181 : 
-; line   182 :     IICWH = 5;
-$DGL	0,24
-	mov	!IICWH0,#05H	; 5 				;[INF] 4, 1
-; line   183 :     IICWL = 10;                 // L期間の長さ（？）
-$DGL	0,25
-	mov	!IICWL0,#0AH	; 10 				;[INF] 4, 1
-; line   184 : 
-; line   185 :     SMC = 1;
-$DGL	0,27
-	set1	!IICCTL10.3					;[INF] 4, 2
-; line   186 : 
-; line   187 :     IICAMK = 0;                 // 割り込みを許可
-$DGL	0,29
-	clr1	MK1L.3						;[INF] 3, 2
-; line   188 : 
-; line   189 :     IICE = 1;
-$DGL	0,31
-	set1	!IICCTL00.7					;[INF] 4, 2
-; line   190 : 
-; line   191 :     PM20 &= ~0x3;               /* set clock pin for IICA */
-$DGL	0,33
-	mov	a,!PM20						;[INF] 3, 1
-	and	a,#0FCH	; 252 					;[INF] 2, 1
-	mov	!PM20,a						;[INF] 3, 1
-; line   192 : 
-; line   193 :     LREL = 1;
-$DGL	0,35
-	set1	!IICCTL00.6					;[INF] 4, 2
-; line   194 : }
-$DGL	0,36
-??ef_IIC_twl_Init:
-	ret							;[INF] 1, 6
-??ee_IIC_twl_Init:
-; line   195 : 
-; line   196 : 
-; line   197 : 
-; line   198 : //**************************************************************
-;              **************
-; line   199 : void IIC_twl_Stop( void )
-; line   200 : {
-_IIC_twl_Stop:
-$DGL	1,105
-??bf_IIC_twl_Stop:
-; line   201 :     IICE = 0;                   /* IICA disable */
-$DGL	0,2
-	clr1	!IICCTL00.7					;[INF] 4, 2
-; line   202 :     IICAEN = 0;
-$DGL	0,3
-	clr1	!PER0.4						;[INF] 4, 2
-; line   203 : }
-$DGL	0,4
-??ef_IIC_twl_Stop:
-	ret							;[INF] 1, 6
-??ee_IIC_twl_Stop:
-
-@@CODEL	CSEG
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c
-;
-; $FUNC int_iic_twl(82)
-;	void=(void)
-;	CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes
-;
-; $CALL adrs_table_twl_ext2int(105)
-;	bc=(int:ax)
-;
-; $CALL vreg_twl_read(122)
-;	bc=(int:ax)
-;
-; $CALL vreg_twl_write(149)
-;	void=(int:ax, int:[sp+4])
-;
-; $FUNC IIC_twl_Init(159)
-;	void=(void)
-;	CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
-;
-; $FUNC IIC_twl_Stop(200)
-;	void=(void)
-;	CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/ini_VECT.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/ini_VECT.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/led.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/led.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/loader.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/loader.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/magic.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/magic.asm
@ -1,115 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:47
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no magic.c
-; In-file   : magic.c
-; Asm-file  : inter_asm\magic.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		01BH,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, magic.c
-$DGS	MOD_NAM, magic,		00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, MGC_MIMI,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, MGC_TAIL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, MGC_LOAD,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	STA_SYM, _MGC_LOAD,	U,	U,	0D00CH,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	09H,	09H,	00H,	00H,	00H,	00H
-$DGS	STA_SYM, _MGC_HEAD,	U,	U,	0500CH,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	09H,	09H,	00H,	00H,	00H,	00H
-$DGS	STA_SYM, _MGC_TAIL,	U,	U,	0500CH,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	09H,	09H,	00H,	00H,	00H,	00H
-
-
-@@BITS	BSEG
-
-MGC_MIMI	CSEG	AT 2100H
-_MGC_HEAD:	DB	'19:31:47'
-	DB	00H
-	DB	(1)
-
-MGC_TAIL	CSEG	AT 4FF6H
-_MGC_TAIL:	DB	'19:31:47'
-	DB	00H
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-MGC_LOAD	CSEG	AT 0FF6H
-_MGC_LOAD:	DB	'19:31:47'
-	DB	00H
-	DB	(1)
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : /***************************************************************
-;              **************
-; line     2 : ビルド時刻を埋め込みます。
-; line     3 : ビルドの度に更新されるようにする必要があります。
-; line     4 : (touchしてね)
-; line     5 :  ***************************************************************
-;              *************/
-; line     6 : #include "config.h"
-; line     7 : 
-; line     8 : // V0.5 (ニセ0.1改)
-; line     9 : #pragma section @@CNSTL MGC_LOAD AT 0x0FF6
-; line    10 : __far static const unsigned char MGC_LOAD[] = __TIME__;
-; line    11 : 
-; line    12 : #pragma section @@CNST MGC_MIMI AT 0x2100
-; line    13 : static const unsigned char MGC_HEAD[] = __TIME__;
-; line    14 : 
-; line    15 : #pragma section @@CNST MGC_TAIL AT 0x4FF6
-; line    16 : static const unsigned char MGC_TAIL[] = __TIME__;
-
-@@CODE	CSEG	BASE
-
-@@CODEL	CSEG
-
-@@BASE	CSEG	BASE
-
-@@CNST	CSEG	MIRRORP
-
-	END
-
-
-; *** Code Information ***
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/main.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/main.asm
@ -1,525 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no main.c
-; In-file   : main.c
-; Asm-file  : inter_asm\main.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		063H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, main.c
-$DGS	MOD_NAM, main,		00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CNSL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	ENM_TAG, _pwr_state_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		01EH
-$DGS	MEB_ENM, _OFF_TRIG,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _OFF,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON_TRIG,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON,		03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP_TRIG,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _BT_CHARGE,	06H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 013H,		01H
-$DGS	ENM_TAG, _poweron_reason_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		025H
-$DGS	MEB_ENM, _NONE,		00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _PWSW,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _RTC_ALARM,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 01EH,		01H
-$DGS	ENM_TAG, _model_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		02FH
-$DGS	MEB_ENM, _MODEL_JIKKI,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_TS_BOARD,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_SHIROBAKO,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED1,	03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED2,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED3,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 025H,		01H
-$DGS	STR_STR, .0fake,	00H,	0FFFEH,	08H,	0AH,	01H,	00H
-$DGS	AUX_TAG, 04H,		041H
-$DGS	MEB_STR, _pwr_state,	00H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 013H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	MEB_STR, _poweron_reason,	01H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 01EH,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BIT_FLD, _dipsw0,	010H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw1,	011H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw2,	012H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _reboot,	013H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	MEB_STR, _model,	03H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 025H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	END_STR, .eos,		04H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 02FH,		04H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _main_loop,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	05DH,	00H,	00H
-$DGS	BEG_FUN, ??bf_main_loop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 021H,		00H,	047H
-$DGS	BEG_BLK, ??bb00_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0EH,		00H,	049H
-$DGS	BEG_BLK, ??bb01_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 014H,		00H,	04FH
-$DGS	END_BLK, ??eb01_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 016H
-$DGS	END_BLK, ??eb00_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 017H
-$DGS	BEG_BLK, ??bb02_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 019H,		00H,	053H
-$DGS	END_BLK, ??eb02_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01CH
-$DGS	BEG_BLK, ??bb03_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02EH,		00H,	055H
-$DGS	BEG_BLK, ??bb04_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 032H,		00H,	00H
-$DGS	END_BLK, ??eb04_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 034H
-$DGS	END_BLK, ??eb03_main_loop,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 038H
-$DGS	END_FUN, ??ef_main_loop,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 039H
-$DGS	STA_SYM, _read_dipsw,	U,	U,	01H,	03H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	063H,	00H,	00H
-$DGS	BEG_FUN, ??bf_read_dipsw,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 05FH,		00H,	063H
-$DGS	END_FUN, ??ef_read_dipsw,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 07H
-$DGS	GLV_SYM, _system_status,	U,	U,	08H,	026H,	01H,	00H
-$DGS	AUX_STR, 02FH,		00H,	04H,	00H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _update,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _pool,		U,	U,	0DH,	026H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	0200H,	0100H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _RTC_init,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_init,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_start,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _PM_init,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_read_a_byte,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr_init,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_twl_init,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _clear_hosu_hist,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_task_interval_run_force,	U,	U,	034CH,	02H,	00H,	00H
-$DGS	GLV_SYM, _WDT_Restart,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_task_interval_run,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_task_immed_run,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-
-	EXTRN	_RTC_init
-	EXTRN	_renge_init
-	EXTRN	_iic_mcu_start
-	EXTRN	_PM_init
-	EXTRN	_iic_mcu_read_a_byte
-	EXTRN	_vreg_ctr_init
-	EXTRN	_vreg_twl_init
-	EXTRN	_clear_hosu_hist
-	EXTRN	_WDT_Restart
-	EXTRN	_renge_task_interval_run
-	EXTRN	_renge_task_immed_run
-	EXTBIT	_renge_task_interval_run_force
-	PUBLIC	_system_status
-	PUBLIC	_update
-	PUBLIC	_pool
-	PUBLIC	_main_loop
-
-@@BITS	BSEG
-_update	DBIT
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-_system_status:	DS	(4)
-_pool:	DS	(512)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-LDR_CNSL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : /* ========================================================
-; line     2 :   MCU CTR BSR
-; line     3 :                                        2008,2009 nintendo
-; line     4 :                                        開発技術部　藤田
-; line     5 :  ======================================================== */
-; line     6 : 
-; line     7 : 
-; line     8 : // ========================================================
-; line     9 : #include "incs_loader.h"
-; line    10 : 
-; line    11 : #include "WDT.h"
-; line    12 : #include "rtc.h"
-; line    13 : #include "pm.h"
-; line    14 : #include "accero.h"
-; line    15 : #include "led.h"
-; line    16 : #include "adc.h"
-; line    17 : 
-; line    18 : 
-; line    19 : // ========================================================
-; line    20 : static void read_dipsw(  );
-; line    21 : 
-; line    22 : 
-; line    23 : // ========================================================
-; line    24 : system_status_ system_status;
-; line    25 : bit update;
-; line    26 : 
-; line    27 : 
-; line    28 : u16 pool[256];                   // アップデート時のワークエリア
-;               兼 歩数計データ
-; line    29 : /* ========================================================
-; line    30 :  本当のエントリ関数は loader.c にあります
-; line    31 :  ======================================================== */
-; line    32 : void main_loop( void )
-; line    33 : {
-
-LDR_CODE	CSEG	BASE
-_main_loop:
-$DGL	1,67
-??bf_main_loop:
-; line    34 : 
-; line    35 :     // 電池投入時、ファームアップデート後のみ
-; line    36 :     RTC_init(  );               // 内部でリブートか判定しています
-$DGL	0,4
-	call	!_RTC_init					;[INF] 3, 3
-; line    37 : 
-; line    38 :     renge_init(  );
-$DGL	0,6
-	call	!_renge_init					;[INF] 3, 3
-; line    39 : 
-; line    40 :     iic_mcu_start(  );
-$DGL	0,8
-	call	!_iic_mcu_start					;[INF] 3, 3
-; line    41 :     EI(  );
-$DGL	0,9
-	ei							;[INF] 3, 4
-; line    42 : 
-; line    43 :     PM_init();
-$DGL	0,11
-	call	!_PM_init					;[INF] 3, 3
-; line    44 : 
-; line    45 :     if( system_status.reboot )
-$DGL	0,13
-	mov	a,!_system_status+2				;[INF] 3, 1
-	bf	a.3,$?L0003					;[INF] 3, 5
-; line    46 :     {
-??bb00_main_loop:
-; line    47 : #ifdef _PMIC_TWL_
-; line    48 :         if( RESET1_n )
-; line    49 : #else
-; line    50 :         if( PM_chk_LDSW() != 0 )
-$DGL	0,18
-	movw	ax,#03H	; 3 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#084H	; 132 					;[INF] 2, 1
-	call	!_iic_mcu_read_a_byte				;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-	mov	a,c						;[INF] 1, 1
-	and	a,#01H	; 1 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0004						;[INF] 2, 4
-; line    51 : #endif
-; line    52 :         {
-??bb01_main_loop:
-; line    53 :             system_status.pwr_state = ON_TRIG;
-$DGL	0,21
-	mov	!_system_status,#02H	; 2 			;[INF] 4, 1
-??eb01_main_loop:
-; line    54 :         }
-; line    55 :     }
-$DGL	0,23
-??eb00_main_loop:
-	br	$?L0004						;[INF] 2, 3
-?L0003:
-; line    56 :     else
-; line    57 :     {
-??bb02_main_loop:
-; line    58 :         // リブート時は実行されない
-; line    59 :         system_status.pwr_state = OFF_TRIG;
-$DGL	0,27
-	clrb	!_system_status					;[INF] 3, 1
-??eb02_main_loop:
-; line    60 :     }
-?L0004:
-; line    61 : 
-; line    62 : #ifdef _PARRADIUM_
-; line    63 :         system_status.pwr_state = OFF;
-; line    64 : #endif
-; line    65 :     vreg_ctr_init(  );
-$DGL	0,33
-	call	!_vreg_ctr_init					;[INF] 3, 3
-; line    66 :     vreg_twl_init(  );
-$DGL	0,34
-	call	!_vreg_twl_init					;[INF] 3, 3
-; line    67 : 
-; line    68 :     read_dipsw(  );    // 特定スイッチで何かするか？
-$DGL	0,36
-	call	!_read_dipsw					;[INF] 3, 3
-; line    69 : 
-; line    70 :     clear_hosu_hist(); // 履歴クリア
-$DGL	0,38
-	call	!_clear_hosu_hist				;[INF] 3, 3
-; line    71 : 
-; line    72 :     renge_task_interval_run_force = 1;
-$DGL	0,40
-	set1	_renge_task_interval_run_force			;[INF] 3, 2
-; line    73 : 
-; line    74 :     RTCIMK = 0;                 /* 割り込み(アラーム&インターバル
-;              )許可 */
-$DGL	0,42
-	clr1	MK1H.2						;[INF] 3, 2
-; line    75 : 
-; line    76 :     // メインループ //
-; line    77 :     while( 1 )
-?L0007:
-; line    78 :     {                           // システムtick、または割り込みで
-;              廻ります。
-??bb03_main_loop:
-; line    79 :         WDT_Restart(  );
-$DGL	0,47
-	call	!_WDT_Restart					;[INF] 3, 3
-; line    80 :         renge_task_interval_run(  );    // 内部で、システムtickま
-;              たは強制起動します
-$DGL	0,48
-	call	!_renge_task_interval_run			;[INF] 3, 3
-; line    81 :         while( renge_task_interval_run_force != 0 )
-$DGL	0,49
-?L0009:
-	bf	_renge_task_interval_run_force,$?L0010		;[INF] 4, 5
-; line    82 :         {
-??bb04_main_loop:
-; line    83 :             renge_task_interval_run(  );
-$DGL	0,51
-	call	!_renge_task_interval_run			;[INF] 3, 3
-??eb04_main_loop:
-; line    84 :         }
-$DGL	0,52
-	br	$?L0009						;[INF] 2, 3
-?L0010:
-; line    85 :         WDT_Restart(  );
-$DGL	0,53
-	call	!_WDT_Restart					;[INF] 3, 3
-; line    86 :         while( renge_task_immed_run(  ) != ERR_SUCCESS );       
-;              // ここのループが廻る度に実行されます
-$DGL	0,54
-?L0011:
-	call	!_renge_task_immed_run				;[INF] 3, 3
-	cmp0	c						;[INF] 1, 1
-	bnz	$?L0011						;[INF] 2, 4
-; line    87 :         HALT(  );
-$DGL	0,55
-	halt							;[INF] 2, 3
-??eb03_main_loop:
-; line    88 :     }
-$DGL	0,56
-	br	$?L0007						;[INF] 2, 3
-; line    89 : }
-$DGL	0,57
-??ef_main_loop:
-	ret							;[INF] 1, 6
-??ee_main_loop:
-; line    90 : 
-; line    91 : 
-; line    92 : /* ========================================================
-; line    93 :  ======================================================== */
-; line    94 : static void read_dipsw(  )
-; line    95 : {
-_read_dipsw:
-$DGL	1,93
-??bf_read_dipsw:
-; line    96 :     // ソフトディップスイッチ読み込み
-; line    97 : //  PU4 |= 0x03; // dip sw 0,1
-; line    98 :     system_status.dipsw0 = ( DIPSW_0 == 0 ) ? 0 : 1;
-$DGL	0,4
-	bt	P4.0,$?L0015					;[INF] 4, 5
-	clrw	ax						;[INF] 1, 1
-	br	$?L0016						;[INF] 2, 3
-?L0015:
-	onew	ax						;[INF] 1, 1
-?L0016:
-	mov	a,x						;[INF] 1, 1
-	movw	de,#loww (_system_status+2)			;[INF] 3, 1
-	mov1	CY,a.0						;[INF] 2, 1
-	mov	a,[de]						;[INF] 1, 1
-	mov1	a.0,CY						;[INF] 2, 1
-	mov	[de],a						;[INF] 1, 1
-; line    99 :     system_status.dipsw1 = ( DIPSW_1 == 0 ) ? 0 : 1;
-$DGL	0,5
-	bt	P4.1,$?L0017					;[INF] 4, 5
-	clrw	ax						;[INF] 1, 1
-	br	$?L0018						;[INF] 2, 3
-?L0017:
-	onew	ax						;[INF] 1, 1
-?L0018:
-	mov	a,x						;[INF] 1, 1
-	movw	de,#loww (_system_status+2)			;[INF] 3, 1
-	mov1	CY,a.0						;[INF] 2, 1
-	mov	a,[de]						;[INF] 1, 1
-	mov1	a.1,CY						;[INF] 2, 1
-	mov	[de],a						;[INF] 1, 1
-; line   100 : //  PU4 &= ~0x03;
-; line   101 : }
-$DGL	0,7
-??ef_read_dipsw:
-	ret							;[INF] 1, 6
-??ee_read_dipsw:
-
-LDR_CODL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c
-;
-; $FUNC main_loop(33)
-;	void=(void)
-;	CODE SIZE= 93 bytes, CLOCK_SIZE= 97 clocks, STACK_SIZE= 6 bytes
-;
-; $CALL RTC_init(36)
-;	void=(void)
-;
-; $CALL renge_init(38)
-;	void=(void)
-;
-; $CALL iic_mcu_start(40)
-;	void=(void)
-;
-; $CALL PM_init(43)
-;	void=(void)
-;
-; $CALL iic_mcu_read_a_byte(50)
-;	bc=(int:ax, int:[sp+4])
-;
-; $CALL vreg_ctr_init(65)
-;	void=(void)
-;
-; $CALL vreg_twl_init(66)
-;	void=(void)
-;
-; $CALL read_dipsw(68)
-;	void=(void)
-;
-; $CALL clear_hosu_hist(70)
-;	void=(void)
-;
-; $CALL WDT_Restart(79)
-;	void=(void)
-;
-; $CALL renge_task_interval_run(80)
-;	bc=(void)
-;
-; $CALL renge_task_interval_run(83)
-;	bc=(void)
-;
-; $CALL WDT_Restart(85)
-;	void=(void)
-;
-; $CALL renge_task_immed_run(86)
-;	bc=(void)
-;
-; $FUNC read_dipsw(95)
-;	void=(void)
-;	CODE SIZE= 37 bytes, CLOCK_SIZE= 38 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/pedo_alg_thre_det2.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/pedo_alg_thre_det2.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/pm.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/pm.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/reboot.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/reboot.asm
@ -1,134 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:25
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no reboot.c
-; In-file   : reboot.c
-; Asm-file  : inter_asm\reboot.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 02H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		019H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, reboot.c
-$DGS	MOD_NAM, reboot,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CNSL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, LDR_CODL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	GLV_SYM, _my_reboot,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	019H,	00H,	00H
-$DGS	BEG_FUN, ??bf_my_reboot,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0EH,		00H,	019H
-$DGS	END_FUN, ??ef_my_reboot,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 0BH
-
-	PUBLIC	_my_reboot
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-LDR_CNSL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : /********************************************************//*
-; line     2 : 
-; line     3 :   むりやりリブート
-; line     4 : 
-; line     5 :   ファイル中にインラインアセンブラがあると、
-; line     6 :   そのモジュール全部最適化が聞かなくなるため追い出した
-; line     7 : 
-; line     8 :  **********************************************************/
-; line     9 : #pragma SFR
-; line    10 : 
-; line    11 : #include "incs_loader.h"
-; line    12 : 
-; line    13 : 
-; line    14 : void my_reboot(){
-
-LDR_CODE	CSEG	BASE
-_my_reboot:
-$DGL	1,19
-??bf_my_reboot:
-; line    15 : #asm
-
-$DGL	0,4
-    MOV     PSW,#06H                ; ダミーのPSWをセット
-$DGL	0,5
-    MOVW    AX,#000d0h                ; リセットのベクタ値を取り込んでいます。
-$DGL	0,6
-    PUSH    PSW
-$DGL	0,7
-    PUSH    AX                      ; これでRETIのためのスタックを準備
-$DGL	0,8
-    RETI                            ; これでリセット・ベクタに分岐
-
-; line    16 : 
-; line    17 :     MOV     PSW,#06H                ; ダミーのPSWをセット
-; line    18 :     MOVW    AX,#000d0h                ; リセットのベクタ値を取り
-;              込んでいます。
-; line    19 :     PUSH    PSW
-; line    20 :     PUSH    AX                      ; これでRETIのためのスタック
-;              を準備
-; line    21 :     RETI                            ; これでリセット・ベクタに分
-;              岐
-; line    22 : 
-; line    23 : #endasm
-; line    24 : }
-$DGL	0,11
-??ef_my_reboot:
-	ret							;[INF] 1, 6
-??ee_my_reboot:
-
-LDR_CODL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c
-;
-; $FUNC my_reboot(14)
-;	void=(void)
-;	CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/renge.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/renge.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/rtc.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/rtc.asm
@ -1,760 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no rtc.c
-; In-file   : rtc.c
-; Asm-file  : inter_asm\rtc.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		099H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, rtc.c
-$DGS	MOD_NAM, rtc,		00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	ENM_TAG, _pwr_state_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		01EH
-$DGS	MEB_ENM, _OFF_TRIG,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _OFF,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON_TRIG,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON,		03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP_TRIG,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _BT_CHARGE,	06H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 013H,		01H
-$DGS	ENM_TAG, _poweron_reason_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		025H
-$DGS	MEB_ENM, _NONE,		00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _PWSW,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _RTC_ALARM,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 01EH,		01H
-$DGS	ENM_TAG, _model_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		02FH
-$DGS	MEB_ENM, _MODEL_JIKKI,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_TS_BOARD,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_SHIROBAKO,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED1,	03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED2,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED3,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 025H,		01H
-$DGS	STR_STR, .0fake,	00H,	0FFFEH,	08H,	0AH,	01H,	00H
-$DGS	AUX_TAG, 04H,		041H
-$DGS	MEB_STR, _pwr_state,	00H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 013H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	MEB_STR, _poweron_reason,	01H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 01EH,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BIT_FLD, _dipsw0,	010H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw1,	011H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw2,	012H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _reboot,	013H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	MEB_STR, _model,	03H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 025H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	END_STR, .eos,		04H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 02FH,		04H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _RTC_init,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	051H,	00H,	00H
-$DGS	BEG_FUN, ??bf_RTC_init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 017H,		02H,	047H
-$DGS	BEG_BLK, ??bb00_RTC_init,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 04H,		00H,	04BH
-$DGS	END_BLK, ??eb00_RTC_init,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 017H
-$DGS	BEG_BLK, ??bb01_RTC_init,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 022H,		00H,	00H
-$DGS	END_BLK, ??eb01_RTC_init,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 023H
-$DGS	END_FUN, ??ef_RTC_init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 029H
-$DGS	GLV_SYM, _int_rtc,	U,	U,	0E001H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	067H,	00H,	00H
-$DGS	BEG_FUN, ??bf_int_rtc,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 048H,		02H,	055H
-$DGS	BEG_BLK, ??bb00_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	057H
-$DGS	BEG_BLK, ??bb01_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 08H,		00H,	059H
-$DGS	BEG_BLK, ??bb02_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0AH,		00H,	05DH
-$DGS	END_BLK, ??eb02_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0AH
-$DGS	BEG_BLK, ??bb03_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0EH,		00H,	00H
-$DGS	END_BLK, ??eb03_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 010H
-$DGS	END_BLK, ??eb01_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	END_BLK, ??eb00_int_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 012H
-$DGS	END_FUN, ??ef_int_rtc,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 013H
-$DGS	GLV_SYM, _rtc_buf_reflesh,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	075H,	00H,	00H
-$DGS	BEG_FUN, ??bf_rtc_buf_reflesh,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 063H,		02H,	06BH
-$DGS	BEG_BLK, ??bb00_rtc_buf_reflesh,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03H,		00H,	06DH
-$DGS	BEG_BLK, ??bb01_rtc_buf_reflesh,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07H,		00H,	00H
-$DGS	END_BLK, ??eb01_rtc_buf_reflesh,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 08H
-$DGS	END_BLK, ??eb00_rtc_buf_reflesh,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0DH
-$DGS	END_FUN, ??ef_rtc_buf_reflesh,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 0EH
-$DGS	GLV_SYM, _set_rtc,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	081H,	00H,	00H
-$DGS	BEG_FUN, ??bf_set_rtc,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 07BH,		02H,	07BH
-$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	REG_PAR, _data,		07H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_set_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03H,		00H,	00H
-$DGS	END_BLK, ??eb00_set_rtc,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07H
-$DGS	END_FUN, ??ef_set_rtc,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 09H
-$DGS	GLV_SYM, _rtc_unlock,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	093H,	00H,	00H
-$DGS	BEG_FUN, ??bf_rtc_unlock,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 08CH,		02H,	085H
-$DGS	BEG_BLK, ??bb00_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 09H,		00H,	087H
-$DGS	BEG_BLK, ??bb01_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0DH,		00H,	08DH
-$DGS	END_BLK, ??eb01_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0EH
-$DGS	END_BLK, ??eb00_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	BEG_BLK, ??bb02_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 015H,		00H,	00H
-$DGS	END_BLK, ??eb02_rtc_unlock,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01BH
-$DGS	END_FUN, ??ef_rtc_unlock,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 01CH
-$DGS	GLV_SYM, _int_rtc_int,	U,	U,	0E001H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	099H,	00H,	00H
-$DGS	BEG_FUN, ??bf_int_rtc_int,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 0B2H,		00H,	099H
-$DGS	END_FUN, ??ef_int_rtc_int,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 03H
-$DGS	GLV_SYM, _rtc_work,	U,	U,	0CH,	026H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	07H,	07H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _rtc_lock,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _rtc_dirty,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _rtc_alarm_dirty,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _system_status,	U,	U,	08H,	02H,	01H,	00H
-$DGS	AUX_STR, 02FH,		00H,	04H,	00H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_flg_interval,	U,	U,	034CH,	02H,	00H,	00H
-
-	EXTRN	_vreg_ctr
-	EXTRN	_system_status
-	EXTBIT	_renge_flg_interval
-	PUBLIC	_rtc_work
-	PUBLIC	_rtc_lock
-	PUBLIC	_rtc_dirty
-	PUBLIC	_rtc_alarm_dirty
-	PUBLIC	_RTC_init
-	PUBLIC	_int_rtc
-	PUBLIC	_rtc_buf_reflesh
-	PUBLIC	_set_rtc
-	PUBLIC	_rtc_unlock
-	PUBLIC	_int_rtc_int
-
-@@BITS	BSEG
-_rtc_lock	DBIT
-_rtc_dirty	DBIT
-_rtc_alarm_dirty	DBIT
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-
-@@INIT	DSEG	BASEP
-
-@@DATA	DSEG	BASEP
-_rtc_work:	DS	(7)
-	DS	(1)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : /* ========================================================
-; line     2 :   RTC
-; line     3 :  ======================================================== */
-; line     4 : #pragma sfr
-; line     5 : #pragma inline
-; line     6 : 
-; line     7 : 
-; line     8 : #include "incs.h"
-; line     9 : 
-; line    10 : 
-; line    11 : 
-; line    12 : // ========================================================
-; line    13 : u8      rtc_work[7];
-; line    14 : bit     rtc_lock;
-; line    15 : bit     rtc_dirty;
-; line    16 : bit     rtc_alarm_dirty;
-; line    17 : 
-; line    18 : /* ========================================================
-; line    19 :  ペリフェラルの初期化
-; line    20 :  レジスタの電池交換ビットのセット
-; line    21 :  ======================================================== */
-; line    22 : void RTC_init( void )
-; line    23 : {
-
-ROM_CODE	CSEG	BASE
-_RTC_init:
-$DGL	1,67
-	push	hl						;[INF] 1, 1
-??bf_RTC_init:
-; line    24 : 
-; line    25 :     if( !RTCEN )            // ビットが立っていたらリブート
-$DGL	0,3
-	movw	hl,#0F0H	; 240 				;[INF] 3, 1
-	mov1	CY,[hl].7					;[INF] 2, 1
-	bc	$?L0003						;[INF] 2, 4
-; line    26 :     {
-??bb00_RTC_init:
-; line    27 :         RTCEN = 1;              // モジュールON
-$DGL	0,5
-	set1	!PER0.7						;[INF] 4, 2
-; line    28 : 
-; line    29 :         // RTC設定
-; line    30 :         RTCC0 = 0b00001000;    /* 動作停止、24時間制、32k出力「ま
-;              だなし」、定周期割り込みなし */
-$DGL	0,8
-	mov	RTCC0,#08H	; 8 				;[INF] 3, 1
-; line    31 :         RTCC1 = 0b11000000;    /* アラーム割り込み有効＆動作開始
-;               */
-$DGL	0,9
-	mov	RTCC1,#0C0H	; 192 				;[INF] 3, 1
-; line    32 :         RTCC2 = 0b10000000;    /* インターバル:32k/2^6=2ms、RTCD
-;              IV出力なし */
-$DGL	0,10
-	mov	RTCC2,#080H	; 128 				;[INF] 3, 1
-; line    33 : 
-; line    34 :         SEC   = 0x00;
-$DGL	0,12
-	clrb	!SEC						;[INF] 3, 1
-; line    35 :         MIN   = 0x00;
-$DGL	0,13
-	clrb	!MIN						;[INF] 3, 1
-; line    36 :         HOUR  = 0x15;
-$DGL	0,14
-	mov	HOUR,#015H	; 21 				;[INF] 3, 1
-; line    37 :         DAY   = 0x01;
-$DGL	0,15
-	oneb	!DAY						;[INF] 3, 1
-; line    38 :         WEEK  = 0x00;
-$DGL	0,16
-	clrb	!WEEK						;[INF] 3, 1
-; line    39 :         MONTH = 0x11;
-$DGL	0,17
-	mov	MONTH,#011H	; 17 				;[INF] 3, 1
-; line    40 :         YEAR  = 0x09;
-$DGL	0,18
-	mov	YEAR,#09H	; 9 				;[INF] 3, 1
-; line    41 : 
-; line    42 :         ALARMWW = 0x7F;
-$DGL	0,20
-	mov	ALARMWW,#07FH	; 127 				;[INF] 3, 1
-; line    43 : 
-; line    44 :         vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT;
-$DGL	0,22
-	set1	!_vreg_ctr+2.0					;[INF] 4, 2
-??eb00_RTC_init:
-; line    45 :     }
-?L0003:
-; line    46 :     // 割り込み設定
-; line    47 :     RTCIF = 0;
-$DGL	0,25
-	clr1	IF1H.1						;[INF] 3, 2
-; line    48 :     RTCIIF = 0;
-$DGL	0,26
-	clr1	IF1H.2						;[INF] 3, 2
-; line    49 :     RTCMK = 1;                  /* 割り込み(定周期)禁止 */
-$DGL	0,27
-	set1	MK1H.1						;[INF] 3, 2
-; line    50 :     RTCIMK = 0;                 /* 割り込み(アラーム&インターバル
-;              )許可 */
-$DGL	0,28
-	clr1	MK1H.2						;[INF] 3, 2
-; line    51 : 
-; line    52 :     RTCE = 1;                   /* 動作開始 */
-$DGL	0,30
-	set1	RTCC0.7						;[INF] 3, 2
-; line    53 : 
-; line    54 :     RWAIT = 1;
-$DGL	0,32
-	set1	RTCC1.0						;[INF] 3, 2
-; line    55 :     while( !RWST )
-$DGL	0,33
-?L0005:
-	bt	RTCC1.1,$?L0006					;[INF] 4, 5
-; line    56 :     {;
-??bb01_RTC_init:
-??eb01_RTC_init:
-; line    57 :     }
-$DGL	0,35
-	br	$?L0005						;[INF] 2, 3
-?L0006:
-; line    58 :     RWAIT = 0;
-$DGL	0,36
-	clr1	RTCC1.0						;[INF] 3, 2
-; line    59 : 
-; line    60 :     rtc_lock = 0;
-$DGL	0,38
-	clr1	_rtc_lock					;[INF] 3, 2
-; line    61 :     rtc_dirty = 0;
-$DGL	0,39
-	clr1	_rtc_dirty					;[INF] 3, 2
-; line    62 :     rtc_alarm_dirty = 0;
-$DGL	0,40
-	clr1	_rtc_alarm_dirty				;[INF] 3, 2
-; line    63 : }
-$DGL	0,41
-??ef_RTC_init:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_RTC_init:
-; line    64 : 
-; line    65 : 
-; line    66 : 
-; line    67 : /* ========================================================
-; line    68 :  RTC アラーム割り込み
-; line    69 :   2^6/fXT（1.953125 ms）
-; line    70 :  ======================================================== */
-; line    71 : __interrupt void int_rtc(  )
-; line    72 : {
-
-@@BASE	CSEG	BASE
-_int_rtc:
-$DGL	1,81
-	push	ax						;[INF] 1, 1
-??bf_int_rtc:
-; line    73 :     // 日付も指定日で
-; line    74 :     if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY )
-; line    75 :         && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH )
-; line    76 :         && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) )
-$DGL	0,5
-	mov	a,!_vreg_ctr+58					;[INF] 3, 1
-	cmp	a,!DAY						;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-	mov	a,!_vreg_ctr+59					;[INF] 3, 1
-	cmp	a,!MONTH					;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-	mov	a,!_vreg_ctr+60					;[INF] 3, 1
-	cmp	a,!YEAR						;[INF] 3, 1
-	bnz	$?L0013						;[INF] 2, 4
-; line    77 :     {
-??bb00_int_rtc:
-; line    78 :         if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) =
-;              = 0 )
-$DGL	0,7
-	mov	a,!_vreg_ctr+25					;[INF] 3, 1
-	and	a,#04H	; 4 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bnz	$?L0013						;[INF] 2, 4
-; line    79 :         {
-??bb01_int_rtc:
-; line    80 :             vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM;
-$DGL	0,9
-	set1	!_vreg_ctr+17.2					;[INF] 4, 2
-; line    81 :             IRQ0_ast;
-$DGL	0,10
-??bb02_int_rtc:
-	clr1	P7.6						;[INF] 3, 2
-	clr1	PM7.6						;[INF] 3, 2
-??eb02_int_rtc:
-; line    82 :             // マスクをしてあったら、電源を入れません
-; line    83 :             if(( system_status.pwr_state == BT_CHARGE ) ||
-$DGL	0,12
-	cmp	!_system_status,#06H	; 6 			;[INF] 4, 1
-	bz	$?L0015						;[INF] 2, 4
-; line    84 :                ( system_status.pwr_state == OFF ))
-$DGL	0,13
-	cmp	!_system_status,#01H	; 1 			;[INF] 4, 1
-	sknz							;[INF] 2, 1
-?L0015:
-; line    85 :             {
-??bb03_int_rtc:
-; line    86 :                 system_status.poweron_reason = RTC_ALARM;
-$DGL	0,15
-	mov	!_system_status+1,#02H	; 2 			;[INF] 4, 1
-??eb03_int_rtc:
-; line    87 :             }
-?L0013:
-??eb01_int_rtc:
-; line    88 :         }
-??eb00_int_rtc:
-; line    89 :     }
-; line    90 : }
-$DGL	0,19
-??ef_int_rtc:
-	pop	ax						;[INF] 1, 1
-	reti							;[INF] 2, 6
-??ee_int_rtc:
-; line    91 : 
-; line    92 : 
-; line    93 : 
-; line    94 : /* ========================================================
-; line    95 :  RTC のリード
-; line    96 :   レジスタは、sec,min,hour,week,day,month,year の順
-; line    97 :  ======================================================== */
-; line    98 : void rtc_buf_reflesh(  )
-; line    99 : {
-
-ROM_CODE	CSEG	BASE
-_rtc_buf_reflesh:
-$DGL	1,103
-	push	hl						;[INF] 1, 1
-??bf_rtc_buf_reflesh:
-; line   100 :     if( rtc_lock == 0 )
-$DGL	0,2
-	bt	_rtc_lock,$?L0018				;[INF] 4, 5
-; line   101 :     {
-??bb00_rtc_buf_reflesh:
-; line   102 :         rtc_lock = 1;
-$DGL	0,4
-	set1	_rtc_lock					;[INF] 3, 2
-; line   103 :         RWAIT = 1;
-$DGL	0,5
-	set1	RTCC1.0						;[INF] 3, 2
-; line   104 :         while( !RWST )
-$DGL	0,6
-?L0020:
-	bt	RTCC1.1,$?L0021					;[INF] 4, 5
-; line   105 :         {;
-??bb01_rtc_buf_reflesh:
-??eb01_rtc_buf_reflesh:
-; line   106 :         }
-$DGL	0,8
-	br	$?L0020						;[INF] 2, 3
-?L0021:
-; line   107 : 
-; line   108 :         memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 );
-$DGL	0,10
-	movw	de,#loww (_vreg_ctr+48)				;[INF] 3, 1
-	movw	hl,#0FF92H	; -110 				;[INF] 3, 1
-	mov	c,#07H	; 7 					;[INF] 2, 1
-?L0022:
-	mov	a,[hl]						;[INF] 1, 1
-	mov	[de],a						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	hl						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$?L0022						;[INF] 2, 4
-; line   109 :         RWAIT = 0;
-$DGL	0,11
-	clr1	RTCC1.0						;[INF] 3, 2
-??eb00_rtc_buf_reflesh:
-; line   110 : //    renge_task_immed_add( tski_rtc_close );
-; line   111 :     }
-?L0018:
-; line   112 : }
-$DGL	0,14
-??ef_rtc_buf_reflesh:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_rtc_buf_reflesh:
-; line   113 : 
-; line   114 : 
-; line   115 : 
-; line   116 : /* ========================================================
-; line   117 :  RTC のライト
-; line   118 :   set_rtc_close と対で使って下さい。
-; line   119 :   こいつはバッファにコピーするだけで、
-; line   120 :   実際にRTCにセットするのはset_rtc_close()です。
-; line   121 :  ======================================================== */
-; line   122 : void set_rtc( u8 adrs, u8 data )
-; line   123 : {
-_set_rtc:
-$DGL	1,117
-	push	hl						;[INF] 1, 1
-	mov	a,[sp+6]					;[INF] 2, 1
-	movw	hl,ax						;[INF] 1, 1
-??bf_set_rtc:
-; line   124 :     if( rtc_dirty == 0 )
-$DGL	0,2
-	bt	_rtc_dirty,$?L0026				;[INF] 4, 5
-; line   125 :     {
-??bb00_set_rtc:
-; line   126 :         rtc_dirty = 1;
-$DGL	0,4
-	set1	_rtc_dirty					;[INF] 3, 2
-; line   127 :         memcpy( rtc_work, &SEC, 7 );
-$DGL	0,5
-	push	hl						;[INF] 1, 1
-	movw	de,#loww (_rtc_work)				;[INF] 3, 1
-	movw	ax,#0FF92H	; -110 				;[INF] 3, 1
-	movw	hl,ax						;[INF] 1, 1
-	mov	c,#07H	; 7 					;[INF] 2, 1
-?L0028:
-	mov	a,[hl]						;[INF] 1, 1
-	mov	[de],a						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	hl						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$?L0028						;[INF] 2, 4
-	pop	hl						;[INF] 1, 1
-??eb00_set_rtc:
-; line   128 : //    renge_task_immed_add( tski_rtc_close );  // I2C終了時に行う
-; line   129 :     }
-?L0026:
-; line   130 :     rtc_work[adrs] = data;
-$DGL	0,8
-	mov	a,l						;[INF] 1, 1
-	mov	b,a						;[INF] 1, 1
-	mov	a,h						;[INF] 1, 1
-	mov	_rtc_work[b],a					;[INF] 3, 1
-; line   131 : }
-$DGL	0,9
-??ef_set_rtc:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_set_rtc:
-; line   132 : 
-; line   133 : 
-; line   134 : 
-; line   135 : /* ========================================================
-; line   136 :  必要ならば、RTCレジスタの更新
-; line   137 :  ======================================================== */
-; line   138 : // task_status_immed tski_rtc_close(){
-; line   139 : void rtc_unlock(  )
-; line   140 : {
-_rtc_unlock:
-$DGL	1,129
-	push	hl						;[INF] 1, 1
-??bf_rtc_unlock:
-; line   141 :     // リードロック
-; line   142 : //  if( rtc_lock != 0 ){
-; line   143 :     rtc_lock = 0;
-$DGL	0,4
-	clr1	_rtc_lock					;[INF] 3, 2
-; line   144 : //  }
-; line   145 : 
-; line   146 :     // ライトロック
-; line   147 :     if( rtc_dirty != 0 )
-$DGL	0,8
-	bf	_rtc_dirty,$?L0032				;[INF] 4, 5
-; line   148 :     {
-??bb00_rtc_unlock:
-; line   149 :         rtc_dirty = 0;
-$DGL	0,10
-	clr1	_rtc_dirty					;[INF] 3, 2
-; line   150 :         RWAIT = 1;
-$DGL	0,11
-	set1	RTCC1.0						;[INF] 3, 2
-; line   151 :         while( !RWST )
-$DGL	0,12
-?L0034:
-	bt	RTCC1.1,$?L0035					;[INF] 4, 5
-; line   152 :         {;
-??bb01_rtc_unlock:
-??eb01_rtc_unlock:
-; line   153 :         }
-$DGL	0,14
-	br	$?L0034						;[INF] 2, 3
-?L0035:
-; line   154 :         memcpy( &SEC, rtc_work, 7 );
-$DGL	0,15
-	movw	de,#0FF92H	; -110 				;[INF] 3, 1
-	movw	hl,#loww (_rtc_work)				;[INF] 3, 1
-	mov	c,#07H	; 7 					;[INF] 2, 1
-?L0036:
-	mov	a,[hl]						;[INF] 1, 1
-	mov	[de],a						;[INF] 1, 1
-	incw	de						;[INF] 1, 1
-	incw	hl						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-	bnz	$?L0036						;[INF] 2, 4
-; line   155 :         RWAIT = 0;
-$DGL	0,16
-	clr1	RTCC1.0						;[INF] 3, 2
-??eb00_rtc_unlock:
-; line   156 :     }
-?L0032:
-; line   157 : 
-; line   158 :     // アラームセット
-; line   159 :     if( rtc_alarm_dirty )
-$DGL	0,20
-	bf	_rtc_alarm_dirty,$?L0038			;[INF] 4, 5
-; line   160 :     {
-??bb02_rtc_unlock:
-; line   161 :         WALE = 0;
-$DGL	0,22
-	clr1	RTCC1.7						;[INF] 3, 2
-; line   162 :         ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN];
-$DGL	0,23
-	mov	a,!_vreg_ctr+56					;[INF] 3, 1
-	mov	ALARMWM,a					;[INF] 2, 1
-; line   163 :         ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR];
-$DGL	0,24
-	mov	a,!_vreg_ctr+57					;[INF] 3, 1
-	mov	ALARMWH,a					;[INF] 2, 1
-; line   164 :         rtc_dirty = 0;
-$DGL	0,25
-	clr1	_rtc_dirty					;[INF] 3, 2
-; line   165 :         WALE = 1;
-$DGL	0,26
-	set1	RTCC1.7						;[INF] 3, 2
-??eb02_rtc_unlock:
-; line   166 :     }
-?L0038:
-; line   167 : }
-$DGL	0,28
-??ef_rtc_unlock:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_rtc_unlock:
-; line   168 : 
-; line   169 : 
-; line   170 : 
-; line   171 : 
-; line   172 : 
-; line   173 : /* ========================================================
-; line   174 :  RTC システムチックタイマ割り込みベクタ
-; line   175 :   2^6/fXT（1.953125 ms）
-; line   176 :  ======================================================== */
-; line   177 : __interrupt void int_rtc_int(  )
-; line   178 : {
-
-@@BASE	CSEG	BASE
-_int_rtc_int:
-$DGL	1,147
-??bf_int_rtc_int:
-; line   179 :     renge_flg_interval = 1;
-$DGL	0,2
-	set1	_renge_flg_interval				;[INF] 3, 2
-; line   180 : }
-$DGL	0,3
-??ef_int_rtc_int:
-	reti							;[INF] 2, 6
-??ee_int_rtc_int:
-
-@@CODEL	CSEG
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c
-;
-; $FUNC RTC_init(23)
-;	void=(void)
-;	CODE SIZE= 87 bytes, CLOCK_SIZE= 57 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC int_rtc(72)
-;	void=(void)
-;	CODE SIZE= 62 bytes, CLOCK_SIZE= 47 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC rtc_buf_reflesh(99)
-;	void=(void)
-;	CODE SIZE= 37 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC set_rtc(123)
-;	void=(unsigned char adrs:x, unsigned char data:[sp+6])
-;	CODE SIZE= 37 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 4 bytes
-;
-; $FUNC rtc_unlock(140)
-;	void=(void)
-;	CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC int_rtc_int(178)
-;	void=(void)
-;	CODE SIZE= 5 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/self_flash.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/self_flash.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/sw.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/sw.asm
@ -1,859 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:25
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no sw.c
-; In-file   : sw.c
-; Asm-file  : inter_asm\sw.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		0CDH,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, sw.c
-$DGS	MOD_NAM, sw,		00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	ENM_TAG, _pwr_state_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		01EH
-$DGS	MEB_ENM, _OFF_TRIG,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _OFF,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON_TRIG,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON,		03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP_TRIG,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _BT_CHARGE,	06H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 013H,		01H
-$DGS	ENM_TAG, _poweron_reason_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		025H
-$DGS	MEB_ENM, _NONE,		00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _PWSW,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _RTC_ALARM,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 01EH,		01H
-$DGS	ENM_TAG, _model_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		02FH
-$DGS	MEB_ENM, _MODEL_JIKKI,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_TS_BOARD,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_SHIROBAKO,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED1,	03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED2,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED3,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 025H,		01H
-$DGS	STR_STR, .0fake,	00H,	0FFFEH,	08H,	0AH,	01H,	00H
-$DGS	AUX_TAG, 04H,		041H
-$DGS	MEB_STR, _pwr_state,	00H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 013H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	MEB_STR, _poweron_reason,	01H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 01EH,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BIT_FLD, _dipsw0,	010H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw1,	011H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw2,	012H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _reboot,	013H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	MEB_STR, _model,	03H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 025H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	END_STR, .eos,		04H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 02FH,		04H
-$DGS	LAB_SYM, bs_F0060,	U,	U,	00H,	06H,	00H,	00H
-$DGS	LAB_SYM, es_F0060,	U,	U,	00H,	06H,	00H,	00H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_sw,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	0CDH,	00H,	00H
-$DGS	BEG_FUN, ??bf_tsk_sw,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 038H,		02H,	04BH
-$DGS	STA_SYM, _cnt_force_off,	?L0003,	U,	0CH,	03H,	00H,	00H
-$DGS	STA_SYM, _task_interval,	?L0004,	U,	0CH,	03H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	04FH
-$DGS	END_BLK, ??eb00_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 014H
-$DGS	BEG_BLK, ??bb01_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 017H,		00H,	053H
-$DGS	END_BLK, ??eb01_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 019H
-$DGS	BEG_BLK, ??bb02_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 01BH,		00H,	057H
-$DGS	END_BLK, ??eb02_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01DH
-$DGS	BEG_BLK, ??bb03_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 021H,		00H,	059H
-$DGS	BEG_BLK, ??bb04_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 028H,		00H,	05BH
-$DGS	BEG_BLK, ??bb05_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02AH,		00H,	061H
-$DGS	END_BLK, ??eb05_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 030H
-$DGS	END_BLK, ??eb04_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 031H
-$DGS	BEG_BLK, ??bb06_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 033H,		00H,	065H
-$DGS	END_BLK, ??eb06_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 039H
-$DGS	BEG_BLK, ??bb07_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03BH,		00H,	069H
-$DGS	END_BLK, ??eb07_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 03FH
-$DGS	BEG_BLK, ??bb08_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 043H,		00H,	06BH
-$DGS	BEG_BLK, ??bb09_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 046H,		00H,	071H
-$DGS	END_BLK, ??eb09_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 04AH
-$DGS	END_BLK, ??eb08_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 04BH
-$DGS	BEG_BLK, ??bb0A_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 04DH,		00H,	075H
-$DGS	END_BLK, ??eb0A_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 04FH
-$DGS	BEG_BLK, ??bb0B_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 053H,		00H,	079H
-$DGS	END_BLK, ??eb0B_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 05FH
-$DGS	BEG_BLK, ??bb0C_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 062H,		00H,	07BH
-$DGS	BEG_BLK, ??bb0D_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 064H,		00H,	081H
-$DGS	END_BLK, ??eb0D_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 066H
-$DGS	END_BLK, ??eb0C_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 067H
-$DGS	BEG_BLK, ??bb0E_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 069H,		00H,	085H
-$DGS	END_BLK, ??eb0E_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 06BH
-$DGS	BEG_BLK, ??bb0F_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06FH,		00H,	08BH
-$DGS	END_BLK, ??eb0F_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 071H
-$DGS	END_BLK, ??eb03_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 074H
-$DGS	BEG_BLK, ??bb10_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07DH,		00H,	08DH
-$DGS	BEG_BLK, ??bb11_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	08FH
-$DGS	BEG_BLK, ??bb12_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	093H
-$DGS	END_BLK, ??eb12_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07EH
-$DGS	BEG_BLK, ??bb13_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	095H
-$DGS	BEG_BLK, ??bb14_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	099H
-$DGS	END_BLK, ??eb14_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07EH
-$DGS	BEG_BLK, ??bb15_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 07EH,		00H,	0A1H
-$DGS	END_BLK, ??eb15_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07EH
-$DGS	END_BLK, ??eb13_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07EH
-$DGS	END_BLK, ??eb11_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 07EH
-$DGS	BEG_BLK, ??bb16_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 080H,		00H,	0A3H
-$DGS	BEG_BLK, ??bb17_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 080H,		00H,	0A7H
-$DGS	END_BLK, ??eb17_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	BEG_BLK, ??bb18_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 080H,		00H,	0A9H
-$DGS	BEG_BLK, ??bb19_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 080H,		00H,	0ADH
-$DGS	END_BLK, ??eb19_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	BEG_BLK, ??bb1A_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 080H,		00H,	0B5H
-$DGS	END_BLK, ??eb1A_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	END_BLK, ??eb18_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	END_BLK, ??eb16_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 080H
-$DGS	BEG_BLK, ??bb1B_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 082H,		00H,	0B7H
-$DGS	BEG_BLK, ??bb1C_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 082H,		00H,	0BBH
-$DGS	END_BLK, ??eb1C_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 082H
-$DGS	BEG_BLK, ??bb1D_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 082H,		00H,	0BDH
-$DGS	BEG_BLK, ??bb1E_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 082H,		00H,	0C1H
-$DGS	END_BLK, ??eb1E_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 082H
-$DGS	BEG_BLK, ??bb1F_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 082H,		00H,	00H
-$DGS	END_BLK, ??eb1F_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 082H
-$DGS	END_BLK, ??eb1D_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 082H
-$DGS	END_BLK, ??eb1B_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 082H
-$DGS	END_BLK, ??eb10_tsk_sw,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 083H
-$DGS	END_FUN, ??ef_tsk_sw,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 086H
-$DGS	GLV_SYM, _SW_pow_count,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _SW_home_count,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _SW_wifi_count,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _SW_pow_mask,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _SW_home_mask,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _SW_wifi_mask,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _SW_HOME_n,	U,	U,	034CH,	027H,	00H,	00H
-$DGS	GLV_SYM, _set_irq,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _system_status,	U,	U,	08H,	02H,	01H,	00H
-$DGS	AUX_STR, 02FH,		00H,	04H,	00H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _renge_task_interval_run_force,	U,	U,	034CH,	02H,	00H,	00H
-
-	EXTRN	_set_irq
-	EXTRN	_system_status
-	EXTRN	_vreg_ctr
-	EXTBIT	_renge_task_interval_run_force
-	PUBLIC	_SW_pow_count
-	PUBLIC	_SW_home_count
-	PUBLIC	_SW_wifi_count
-	PUBLIC	_SW_pow_mask
-	PUBLIC	_SW_home_mask
-	PUBLIC	_SW_wifi_mask
-	PUBLIC	_SW_HOME_n
-	PUBLIC	_tsk_sw
-
-@@BITS	BSEG
-_SW_pow_mask	DBIT
-_SW_home_mask	DBIT
-_SW_wifi_mask	DBIT
-_SW_HOME_n	DBIT
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-	DB	00H	; 0
-	DB	00H	; 0
-
-@@INIT	DSEG	BASEP
-?L0003:	DS	(1)
-?L0004:	DS	(1)
-
-@@DATA	DSEG	BASEP
-_SW_pow_count:	DS	(1)
-_SW_home_count:	DS	(1)
-_SW_wifi_count:	DS	(1)
-	DS	(1)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; Sub-Routines created by CC78K0R
-
-ROM_CODE	CSEG	BASE
-bs_F0060:
-	push	ax						;[INF] 1, 1
-	mov	x,#010H	; 16 					;[INF] 2, 1
-	call	!_set_irq					;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-	ret							;[INF] 1, 6
-es_F0060:
-
-; *** Sub-Routine Information ***
-;
-; $SUB bs_F0060
-;      CODE SIZE= 8 bytes
-
-; End of Sub-Routines
-
-; line     1 : #pragma SFR
-; line     2 : #pragma NOP
-; line     3 : #pragma HALT
-; line     4 : #pragma STOP
-; line     5 : 
-; line     6 : #include "incs.h"
-; line     7 : 
-; line     8 : #include "i2c_twl.h"
-; line     9 : #include "i2c_ctr.h"
-; line    10 : #include "led.h"
-; line    11 : #include "accero.h"
-; line    12 : #include "pm.h"
-; line    13 : #include "rtc.h"
-; line    14 : 
-; line    15 : 
-; line    16 : 
-; line    17 : //=========================================================
-; line    18 : #define INTERVAL_TSK_SW  16
-; line    19 : #define CLICK_THRESHOLD  1
-; line    20 : #define HOLD_THREASHOLD (u8)( 600 / INTERVAL_TSK_SW )
-; line    21 : 
-; line    22 : 
-; line    23 : 
-; line    24 : //=========================================================
-; line    25 : u8      SW_pow_count, SW_home_count, SW_wifi_count;
-; line    26 : bit     SW_pow_mask, SW_home_mask, SW_wifi_mask;
-; line    27 : 
-; line    28 : bit     SW_HOME_n;
-; line    29 : 
-; line    30 : 
-; line    31 : //=========================================================
-; line    32 : // 押した時間を数える。押しっぱなしでも0に戻らない
-; line    33 : // maskが非0の時は、一度離すまで無視する
-; line    34 : #define count_sw_n( sw, counter, mask )   \
-; line    35 :   {                                       \
-; line    36 :     if( sw ){                             \
-; line    37 :       mask = 0;                           \
-; line    38 :       counter = 0;                        \
-; line    39 :     }else{                                \
-; line    40 :       if( mask != 0 ){                    \
-; line    41 :         counter = 0;                      \
-; line    42 :       }else{                              \
-; line    43 :         counter += 1;                     \
-; line    44 :         if( counter == 0 ) counter = 255; \
-; line    45 :       }                                   \
-; line    46 :     }                                     \
-; line    47 :   }
-; line    48 : 
-; line    49 : 
-; line    50 : 
-; line    51 : /* ========================================================
-; line    52 :  スイッチの監視
-; line    53 :   　チャタリングをはねたり、長押しや、押したトリガなどの検出など
-; line    54 :  ======================================================== */
-; line    55 : void tsk_sw(  )
-; line    56 : {
-
-ROM_CODE	CSEG	BASE
-_tsk_sw:
-$DGL	1,69
-	push	hl						;[INF] 1, 1
-??bf_tsk_sw:
-; line    57 :     static u8 cnt_force_off = 0;
-; line    58 :     static u8 task_interval = 0;
-; line    59 : 
-; line    60 :     switch ( system_status.pwr_state )
-$DGL	0,5
-	mov	a,!_system_status				;[INF] 3, 1
-	sarw	ax,8						;[INF] 2, 1
-	clrw	bc						;[INF] 1, 1
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0006						;[INF] 2, 4
-	subw	ax,#02H	; 2 					;[INF] 3, 1
-	bz	$?L0007						;[INF] 2, 4
-	br	$?L0005						;[INF] 2, 3
-; line    61 :     {
-??bb00_tsk_sw:
-; line    62 :     case ( OFF_TRIG ):
-?L0006:
-; line    63 :         SW_pow_count = 0;
-$DGL	0,8
-	clrb	!_SW_pow_count					;[INF] 3, 1
-; line    64 :         SW_wifi_count = 0;
-$DGL	0,9
-	clrb	!_SW_wifi_count					;[INF] 3, 1
-; line    65 :         SW_home_count = 0;
-$DGL	0,10
-	clrb	!_SW_home_count					;[INF] 3, 1
-; line    66 :         cnt_force_off = 0;
-$DGL	0,11
-	clrb	!?L0003	; cnt_force_off 			;[INF] 3, 1
-; line    67 :         break;
-$DGL	0,12
-	br	$?L0005						;[INF] 2, 3
-; line    68 : 
-; line    69 :     case ( ON_TRIG ):
-?L0007:
-; line    70 :         // 電源投入
-; line    71 :         SW_pow_mask = 1;
-$DGL	0,16
-	set1	_SW_pow_mask					;[INF] 3, 2
-; line    72 :         SW_home_mask = 1;
-$DGL	0,17
-	set1	_SW_home_mask					;[INF] 3, 2
-; line    73 :         SW_wifi_mask = 1;
-$DGL	0,18
-	set1	_SW_wifi_mask					;[INF] 3, 2
-; line    74 :         break;
-??eb00_tsk_sw:
-; line    75 :     }
-?L0005:
-; line    76 : 
-; line    77 :     if( task_interval-- != 0 )
-$DGL	0,22
-	mov	a,!?L0004	; task_interval 		;[INF] 3, 1
-	dec	!?L0004	; task_interval 			;[INF] 3, 2
-	cmp0	a						;[INF] 1, 1
-	skz							;[INF] 2, 1
-	br	!?L0058						;[INF] 3, 3
-; line    78 :     {
-??bb01_tsk_sw:
-; line    79 :         return;
-??eb01_tsk_sw:
-; line    80 :     }
-; line    81 :     else
-; line    82 :     {
-??bb02_tsk_sw:
-; line    83 :         task_interval = (u8)( INTERVAL_TSK_SW / SYS_INTERVAL_TIC
-;              K );
-$DGL	0,28
-	mov	!?L0004,#08H	; task_interval,8 		;[INF] 4, 1
-??eb02_tsk_sw:
-; line    84 :     }
-; line    85 : 
-; line    86 : 
-; line    87 :     switch ( system_status.pwr_state )
-$DGL	0,32
-	mov	a,!_system_status				;[INF] 3, 1
-	sarw	ax,8						;[INF] 2, 1
-	onew	bc						;[INF] 1, 1
-	movw	de,#02H	; 2 					;[INF] 3, 1
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0013						;[INF] 2, 4
-	subw	ax,de						;[INF] 1, 1
-	bz	$?L0013						;[INF] 2, 4
-	subw	ax,de						;[INF] 1, 1
-	subw	ax,bc						;[INF] 1, 1
-	sknh							;[INF] 2, 1
-	br	!?L0012						;[INF] 3, 3
-; line    88 :     {
-??bb03_tsk_sw:
-; line    89 :     case ( ON ):
-?L0013:
-; line    90 :     case ( SLEEP ):
-; line    91 :     case ( BT_CHARGE ):
-; line    92 :     case ( OFF ):
-; line    93 :         // 電源スイッチの監視 //
-; line    94 :         if( SW_POW_n )
-$DGL	0,39
-	bf	P7.3,$?L0016					;[INF] 4, 5
-; line    95 :         {
-??bb04_tsk_sw:
-; line    96 :             if( ( CLICK_THRESHOLD < SW_pow_count ) && ( SW_pow_c
-;              ount <= HOLD_THREASHOLD ) )
-$DGL	0,41
-	cmp	!_SW_pow_count,#02H	; 2 			;[INF] 4, 1
-	bc	$?L0022						;[INF] 2, 4
-	cmp	!_SW_pow_count,#026H	; 38 			;[INF] 4, 1
-	bnc	$?L0022						;[INF] 2, 4
-; line    97 :             {
-??bb05_tsk_sw:
-; line    98 : #ifdef _SW_HOME_ENABLE_
-; line    99 :                 set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_CLICK );
-$DGL	0,44
-	onew	ax						;[INF] 1, 1
-	call	!bs_F0060					;[INF] 3, 3
-??eb05_tsk_sw:
-; line   100 : #else
-; line   101 :                 set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK );
-; line   102 : #endif
-; line   103 :             }
-; line   104 :         }
-$DGL	0,49
-??eb04_tsk_sw:
-	br	$?L0022						;[INF] 2, 3
-?L0016:
-; line   105 :         else if( SW_pow_count == HOLD_THREASHOLD )
-$DGL	0,50
-	cmp	!_SW_pow_count,#025H	; 37 			;[INF] 4, 1
-	bnz	$?L0020						;[INF] 2, 4
-; line   106 :         {
-??bb06_tsk_sw:
-; line   107 : #ifdef _SW_HOME_ENABLE_
-; line   108 :             set_irq( VREG_C_IRQ0, REG_BIT_SW_POW_HOLD );
-$DGL	0,53
-	onew	ax						;[INF] 1, 1
-	incw	ax						;[INF] 1, 1
-	call	!bs_F0060					;[INF] 3, 3
-??eb06_tsk_sw:
-; line   109 : #else
-; line   110 :             set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD );
-; line   111 : #endif
-; line   112 :         }
-$DGL	0,57
-	br	$?L0022						;[INF] 2, 3
-?L0020:
-; line   113 :         else if( SW_pow_count == ( HOLD_THREASHOLD * 4 ) )
-$DGL	0,58
-	cmp	!_SW_pow_count,#094H	; 148 			;[INF] 4, 1
-	bnz	$?L0022						;[INF] 2, 4
-; line   114 :         {                       // todo
-??bb07_tsk_sw:
-; line   115 :             vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RED;
-$DGL	0,60
-	mov	!_vreg_ctr+41,#04H	; 4 			;[INF] 4, 1
-; line   116 :             system_status.pwr_state = OFF_TRIG;
-$DGL	0,61
-	clrb	!_system_status					;[INF] 3, 1
-; line   117 :             renge_task_interval_run_force = 1;
-$DGL	0,62
-	set1	_renge_task_interval_run_force			;[INF] 3, 2
-??eb07_tsk_sw:
-; line   118 :         }
-?L0022:
-; line   119 : 
-; line   120 :         // 電源OFF割り込みを入れたが…
-; line   121 :         if( ( vreg_ctr[VREG_C_IRQ0] & REG_BIT_SW_POW_HOLD ) != 0
-;               )
-$DGL	0,66
-	mov	a,!_vreg_ctr+16					;[INF] 3, 1
-	and	a,#02H	; 2 					;[INF] 2, 1
-	cmp0	a						;[INF] 1, 1
-	bz	$?L0024						;[INF] 2, 4
-; line   122 :         {
-??bb08_tsk_sw:
-; line   123 :             cnt_force_off += 1;
-$DGL	0,68
-	inc	!?L0003	; cnt_force_off 			;[INF] 3, 2
-; line   124 :             if( cnt_force_off >= 13 )
-$DGL	0,69
-	cmp	!?L0003,#0DH	; cnt_force_off,13 		;[INF] 4, 1
-	bc	$?L0025						;[INF] 2, 4
-; line   125 :             {                   // …返事がない。強制的に切る。
-??bb09_tsk_sw:
-; line   126 :                 vreg_ctr[ VREG_C_LED_POW ] = LED_POW_ILM_ONLY_RE
-;              D;
-$DGL	0,71
-	mov	!_vreg_ctr+41,#04H	; 4 			;[INF] 4, 1
-; line   127 :                 system_status.pwr_state = OFF_TRIG;
-$DGL	0,72
-	clrb	!_system_status					;[INF] 3, 1
-; line   128 :                 renge_task_interval_run_force = 1;
-$DGL	0,73
-	set1	_renge_task_interval_run_force			;[INF] 3, 2
-??eb09_tsk_sw:
-; line   129 :             }
-; line   130 :         }
-$DGL	0,75
-??eb08_tsk_sw:
-	br	$?L0025						;[INF] 2, 3
-?L0024:
-; line   131 :         else
-; line   132 :         {
-??bb0A_tsk_sw:
-; line   133 :             cnt_force_off = 0;
-$DGL	0,78
-	clrb	!?L0003	; cnt_force_off 			;[INF] 3, 1
-??eb0A_tsk_sw:
-; line   134 :         }
-?L0025:
-; line   135 : 
-; line   136 :         // HOME スイッチ //
-; line   137 :         switch( system_status.model )
-$DGL	0,82
-	mov	a,!_system_status+3				;[INF] 3, 1
-	sarw	ax,8						;[INF] 2, 1
-	onew	bc						;[INF] 1, 1
-	subw	ax,#00H	; 0 					;[INF] 3, 1
-	bz	$?L0029						;[INF] 2, 4
-	decw	ax						;[INF] 1, 1
-	subw	ax,bc						;[INF] 1, 1
-	bnh	$?L0030						;[INF] 3, 4
-	br	$?L0031						;[INF] 2, 3
-; line   138 :         {
-??bb0B_tsk_sw:
-; line   139 : #ifdef _MODEL_CTR_
-; line   140 :             case( MODEL_JIKKI ):
-?L0029:
-; line   141 :                 SW_HOME_n = SW_HOME_n_JIKKI;
-$DGL	0,86
-	movw	hl,#0510H	; 1296 				;[INF] 3, 1
-	mov1	CY,[hl].4					;[INF] 2, 1
-	mov1	_SW_HOME_n,CY					;[INF] 3, 2
-; line   142 :                 break;
-$DGL	0,87
-	br	$?L0028						;[INF] 2, 3
-; line   143 : #endif
-; line   144 :             case( MODEL_TS_BOARD ):
-?L0030:
-; line   145 :             case( MODEL_SHIROBAKO ):
-; line   146 :                 SW_HOME_n = SW_HOME_n_TSBOARD;
-$DGL	0,91
-	mov1	CY,P2.0						;[INF] 3, 1
-	mov1	_SW_HOME_n,CY					;[INF] 3, 2
-; line   147 :                 break;
-$DGL	0,92
-	br	$?L0028						;[INF] 2, 3
-; line   148 :             default:
-?L0031:
-; line   149 :                 SW_HOME_n = 1;
-$DGL	0,94
-	set1	_SW_HOME_n					;[INF] 3, 2
-??eb0B_tsk_sw:
-; line   150 :         }
-?L0028:
-; line   151 : 
-; line   152 :         if( SW_HOME_n )
-$DGL	0,97
-	bf	_SW_HOME_n,$?L0034				;[INF] 4, 5
-; line   153 :         {
-??bb0C_tsk_sw:
-; line   154 :             if( ( CLICK_THRESHOLD < SW_home_count ) && ( SW_home
-;              _count <= HOLD_THREASHOLD ) )
-$DGL	0,99
-	cmp	!_SW_home_count,#02H	; 2 			;[INF] 4, 1
-	bc	$?L0038						;[INF] 2, 4
-	cmp	!_SW_home_count,#026H	; 38 			;[INF] 4, 1
-	bnc	$?L0038						;[INF] 2, 4
-; line   155 :             {
-??bb0D_tsk_sw:
-; line   156 :                 set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_CLICK );
-$DGL	0,101
-	movw	ax,#04H	; 4 					;[INF] 3, 1
-	call	!bs_F0060					;[INF] 3, 3
-??eb0D_tsk_sw:
-; line   157 :             }
-; line   158 :         }
-$DGL	0,103
-??eb0C_tsk_sw:
-	br	$?L0038						;[INF] 2, 3
-?L0034:
-; line   159 :         else if( SW_home_count == HOLD_THREASHOLD )
-$DGL	0,104
-	cmp	!_SW_home_count,#025H	; 37 			;[INF] 4, 1
-	bnz	$?L0038						;[INF] 2, 4
-; line   160 :         {
-??bb0E_tsk_sw:
-; line   161 :             set_irq( VREG_C_IRQ0, REG_BIT_SW_HOME_HOLD );
-$DGL	0,106
-	movw	ax,#08H	; 8 					;[INF] 3, 1
-	call	!bs_F0060					;[INF] 3, 3
-??eb0E_tsk_sw:
-; line   162 :         }
-?L0038:
-; line   163 : 
-; line   164 :         // wifi sw //
-; line   165 :         if( SW_wifi_count == CLICK_THRESHOLD )
-$DGL	0,110
-	cmp	!_SW_wifi_count,#01H	; 1 			;[INF] 4, 1
-	bnz	$?L0012						;[INF] 2, 4
-; line   166 :         {
-??bb0F_tsk_sw:
-; line   167 :             set_irq( VREG_C_IRQ0, REG_BIT_SW_WIFI_CLICK );
-$DGL	0,112
-	movw	ax,#010H	; 16 				;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	call	!_set_irq					;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-??eb0F_tsk_sw:
-; line   168 :         }
-; line   169 : 
-; line   170 :         break;
-??eb03_tsk_sw:
-; line   171 :     }
-?L0012:
-; line   172 : 
-; line   173 :     // ボタン押し時間のカウント
-; line   174 : /*
-; line   175 : if( ( system_status.pwr_state == ON )
-; line   176 :     || ( system_status.pwr_state == OFF )
-; line   177 :     || ( system_status.pwr_state == BT_CHARGE ) )
-; line   178 :     */
-; line   179 : 
-; line   180 :     {
-??bb10_tsk_sw:
-; line   181 :         count_sw_n( SW_POW_n, SW_pow_count, SW_pow_mask );
-$DGL	0,126
-??bb11_tsk_sw:
-	bf	P7.3,$?L0042					;[INF] 4, 5
-??bb12_tsk_sw:
-	clr1	_SW_pow_mask					;[INF] 3, 2
-	clrb	!_SW_pow_count					;[INF] 3, 1
-??eb12_tsk_sw:
-	br	$?L0046						;[INF] 2, 3
-?L0042:
-??bb13_tsk_sw:
-	bf	_SW_pow_mask,$?L0044				;[INF] 4, 5
-??bb14_tsk_sw:
-	clrb	!_SW_pow_count					;[INF] 3, 1
-??eb14_tsk_sw:
-	br	$?L0046						;[INF] 2, 3
-?L0044:
-??bb15_tsk_sw:
-	inc	!_SW_pow_count					;[INF] 3, 2
-	cmp0	!_SW_pow_count					;[INF] 3, 1
-	sknz							;[INF] 2, 1
-	mov	!_SW_pow_count,#0FFH	; 255 			;[INF] 4, 1
-?L0046:
-??eb15_tsk_sw:
-??eb13_tsk_sw:
-??eb11_tsk_sw:
-; line   182 : #ifdef  _SW_HOME_ENABLE_
-; line   183 :         count_sw_n( SW_HOME_n, SW_home_count, SW_home_mask );
-$DGL	0,128
-??bb16_tsk_sw:
-	bf	_SW_HOME_n,$?L0048				;[INF] 4, 5
-??bb17_tsk_sw:
-	clr1	_SW_home_mask					;[INF] 3, 2
-	clrb	!_SW_home_count					;[INF] 3, 1
-??eb17_tsk_sw:
-	br	$?L0052						;[INF] 2, 3
-?L0048:
-??bb18_tsk_sw:
-	bf	_SW_home_mask,$?L0050				;[INF] 4, 5
-??bb19_tsk_sw:
-	clrb	!_SW_home_count					;[INF] 3, 1
-??eb19_tsk_sw:
-	br	$?L0052						;[INF] 2, 3
-?L0050:
-??bb1A_tsk_sw:
-	inc	!_SW_home_count					;[INF] 3, 2
-	cmp0	!_SW_home_count					;[INF] 3, 1
-	sknz							;[INF] 2, 1
-	mov	!_SW_home_count,#0FFH	; 255 			;[INF] 4, 1
-?L0052:
-??eb1A_tsk_sw:
-??eb18_tsk_sw:
-??eb16_tsk_sw:
-; line   184 : #endif
-; line   185 :         count_sw_n( SW_WIFI_n, SW_wifi_count, SW_wifi_mask );
-$DGL	0,130
-??bb1B_tsk_sw:
-	bf	P7.4,$?L0054					;[INF] 4, 5
-??bb1C_tsk_sw:
-	clr1	_SW_wifi_mask					;[INF] 3, 2
-	clrb	!_SW_wifi_count					;[INF] 3, 1
-??eb1C_tsk_sw:
-	br	$?L0058						;[INF] 2, 3
-?L0054:
-??bb1D_tsk_sw:
-	bf	_SW_wifi_mask,$?L0056				;[INF] 4, 5
-??bb1E_tsk_sw:
-	clrb	!_SW_wifi_count					;[INF] 3, 1
-??eb1E_tsk_sw:
-	br	$?L0058						;[INF] 2, 3
-?L0056:
-??bb1F_tsk_sw:
-	inc	!_SW_wifi_count					;[INF] 3, 2
-	cmp0	!_SW_wifi_count					;[INF] 3, 1
-	sknz							;[INF] 2, 1
-	mov	!_SW_wifi_count,#0FFH	; 255 			;[INF] 4, 1
-?L0058:
-??eb1F_tsk_sw:
-??eb1D_tsk_sw:
-??eb1B_tsk_sw:
-??eb10_tsk_sw:
-; line   186 :     }
-; line   187 : 
-; line   188 :     return;
-; line   189 : }
-$DGL	0,134
-??ef_tsk_sw:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_tsk_sw:
-
-@@CODEL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\sw.c
-;
-; $FUNC tsk_sw(56)
-;	void=(void)
-;	CODE SIZE= 351 bytes, CLOCK_SIZE= 329 clocks, STACK_SIZE= 12 bytes
-;
-; $CALL set_irq(99)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL set_irq(108)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL set_irq(156)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL set_irq(161)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL set_irq(167)
-;	void=(int:ax, int:[sp+4])
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_debug.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_debug.asm
@ -1,369 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:25
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_debug.c
-; In-file   : task_debug.c
-; Asm-file  : inter_asm\task_debug.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		05CH,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, task_debug.c
-$DGS	MOD_NAM, task_debug,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	ENM_TAG, _pwr_state_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		01EH
-$DGS	MEB_ENM, _OFF_TRIG,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _OFF,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON_TRIG,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _ON,		03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP_TRIG,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _SLEEP,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _BT_CHARGE,	06H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 013H,		01H
-$DGS	ENM_TAG, _poweron_reason_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		025H
-$DGS	MEB_ENM, _NONE,		00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _PWSW,		01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _RTC_ALARM,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 01EH,		01H
-$DGS	ENM_TAG, _model_,	00H,	0FFFEH,	0AH,	0FH,	01H,	00H
-$DGS	AUX_TAG, 01H,		02FH
-$DGS	MEB_ENM, _MODEL_JIKKI,	00H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_TS_BOARD,	01H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_SHIROBAKO,	02H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED1,	03H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED2,	04H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	MEB_ENM, _MODEL_RESERVED3,	05H,	0FFFFH,	04H,	010H,	00H,	00H
-$DGS	END_STR, .eos,		01H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 025H,		01H
-$DGS	STR_STR, .0fake,	00H,	0FFFEH,	08H,	0AH,	01H,	00H
-$DGS	AUX_TAG, 04H,		041H
-$DGS	MEB_STR, _pwr_state,	00H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 013H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	MEB_STR, _poweron_reason,	01H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 01EH,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	BIT_FLD, _dipsw0,	010H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw1,	011H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _dipsw2,	012H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	BIT_FLD, _reboot,	013H,	0FFFFH,	0CH,	012H,	01H,	00H
-$DGS	AUX_BIT, 00H,		01H
-$DGS	MEB_STR, _model,	03H,	0FFFFH,	0AH,	08H,	01H,	00H
-$DGS	AUX_STR, 025H,		00H,	01H,	00H,	00H,	00H,	00H,	00H
-$DGS	END_STR, .eos,		04H,	0FFFFH,	00H,	066H,	01H,	00H
-$DGS	AUX_EOS, 02FH,		04H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_debug,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	050H,	00H,	00H
-$DGS	BEG_FUN, ??bf_tsk_debug,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 010H,		02H,	04AH
-$DGS	REG_VAR, _temp,		06H,	0FFFFH,	010CH,	04H,	00H,	00H
-$DGS	STA_SYM, _count,	?L0003,	U,	0CH,	03H,	00H,	00H
-$DGS	STA_SYM, _task_interval,	?L0004,	U,	0CH,	03H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_tsk_debug,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 06H,		00H,	00H
-$DGS	END_BLK, ??eb00_tsk_debug,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 015H
-$DGS	END_FUN, ??ef_tsk_debug,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 017H
-$DGS	GLV_SYM, _tsk_debug2,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	05CH,	00H,	00H
-$DGS	BEG_FUN, ??bf_tsk_debug2,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 02BH,		04H,	056H
-$DGS	AUT_VAR, _str,		00H,	0FFFFH,	0CH,	01H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	04H,	04H,	00H,	00H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_tsk_debug2,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 05H,		00H,	00H
-$DGS	END_BLK, ??eb00_tsk_debug2,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 01CH
-$DGS	END_FUN, ??ef_tsk_debug2,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 01EH
-$DGS	GLV_SYM, _temp_debug_3,	U,	U,	0CH,	026H,	00H,	00H
-$DGS	GLV_SYM, _system_status,	U,	U,	08H,	02H,	01H,	00H
-$DGS	AUX_STR, 02FH,		00H,	04H,	00H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _iic_mcu_write,	U,	U,	0CH,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-
-	EXTRN	_system_status
-	EXTRN	_vreg_ctr
-	EXTRN	_iic_mcu_write
-	PUBLIC	_tsk_debug
-	PUBLIC	_temp_debug_3
-	PUBLIC	_tsk_debug2
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-	DB	00H	; 0
-	DB	(1)
-
-@@INIT	DSEG	BASEP
-?L0003:	DS	(1)
-	DS	(1)
-
-@@DATA	DSEG	BASEP
-?L0004:	DS	(1)
-_temp_debug_3:	DS	(1)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; line     1 : #pragma SFR
-; line     2 : #pragma NOP
-; line     3 : #pragma HALT
-; line     4 : #pragma STOP
-; line     5 : 
-; line     6 : #include "incs.h"
-; line     7 : #include "renge.h"
-; line     8 : #include "pm.h"
-; line     9 : 
-; line    10 : #include "accero.h"
-; line    11 : 
-; line    12 : 
-; line    13 : /* ========================================================
-; line    14 :  ======================================================== */
-; line    15 : void tsk_debug(  )
-; line    16 : {
-
-ROM_CODE	CSEG	BASE
-_tsk_debug:
-$DGL	1,67
-	push	hl						;[INF] 1, 1
-??bf_tsk_debug:
-; line    17 :     u8      temp;
-; line    18 :     static u8 count = 0;
-; line    19 :     static u8 task_interval;
-; line    20 : 
-; line    21 :     if( system_status.pwr_state == ON_TRIG ){
-$DGL	0,6
-	cmp	!_system_status,#02H	; 2 			;[INF] 4, 1
-??bb00_tsk_debug:
-??eb00_tsk_debug:
-; line    22 : 
-; line    23 : #ifdef _MODEL_WM0_
-; line    24 :         PM_CHG_TIMEOUT_DISABLE();                            // 
-;              /WL_RST に配線されています
-; line    25 : #endif
-; line    26 : #ifndef _MODEL_CTR_
-; line    27 :         iic_mcu_write_a_byte( IIC_SLA_DCP, 0x08, 0x80 );     // 
-;              ACR←0x80 揮発モードへ
-; line    28 : #endif
-; line    29 : 
-; line    30 :     /*
-; line    31 :        temp = iic_mcu_read_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_
-;              DO );
-; line    32 :        count += 1;
-; line    33 :        iic_mcu_write_a_byte( IIC_SLA_8LEDS, IIC_8LEDS_REG_DO, co
-;              unt );
-; line    34 :        iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, count );
-; line    35 :      */
-; line    36 :     }
-; line    37 :     return;
-; line    38 : }
-$DGL	0,23
-??ef_tsk_debug:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_tsk_debug:
-; line    39 : 
-; line    40 : u8 temp_debug_3;
-; line    41 : 
-; line    42 : void tsk_debug2(  )
-; line    43 : {
-_tsk_debug2:
-$DGL	1,80
-	push	hl						;[INF] 1, 1
-	subw	sp,#04H						;[INF] 2, 1
-	movw	hl,sp						;[INF] 3, 1
-??bf_tsk_debug2:
-; line    44 :     u8      str[4];
-; line    45 : 
-; line    46 :     if( ( system_status.pwr_state == ON ) || ( system_status.pwr
-;              _state == SLEEP ) )
-$DGL	0,4
-	cmp	!_system_status,#03H	; 3 			;[INF] 4, 1
-	bz	$?L0011						;[INF] 2, 4
-	cmp	!_system_status,#05H	; 5 			;[INF] 4, 1
-	bnz	$?L0009						;[INF] 2, 4
-?L0011:
-; line    47 :     {
-??bb00_tsk_debug2:
-; line    48 : /*
-; line    49 :         str[3] = vreg_ctr[ VREG_C_FREE0 ];
-; line    50 :         str[2] = vreg_ctr[ VREG_C_FREE1 ];
-; line    51 :         str[1] = vreg_ctr[ VREG_C_STATUS ];
-; line    52 :         str[0] = vreg_ctr[ VREG_C_RTC_SEC ];
-; line    53 : */
-; line    54 :         str[3] = vreg_ctr[ VREG_C_SND_VOL ];
-$DGL	0,12
-	mov	a,!_vreg_ctr+9					;[INF] 3, 1
-	mov	[hl+3],a	; str 				;[INF] 2, 1
-; line    55 :         str[2] = vreg_ctr[ VREG_C_TUNE ];
-$DGL	0,13
-	mov	a,!_vreg_ctr+8					;[INF] 3, 1
-	mov	[hl+2],a	; str 				;[INF] 2, 1
-; line    56 :         str[1] = vreg_ctr[ VREG_C_ACC_CONFIG ];
-$DGL	0,14
-	mov	a,!_vreg_ctr+64					;[INF] 3, 1
-	mov	[hl+1],a	; str 				;[INF] 2, 1
-; line    57 :         str[0] = SEC;
-$DGL	0,15
-	mov	a,SEC						;[INF] 2, 1
-	mov	[hl],a	; str 					;[INF] 1, 1
-; line    58 : 
-; line    59 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR
-;              EG_C_IRQ1 ] );
-; line    60 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, boot_ura );
-; line    61 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
-;              EG_C_SND_VOL ] );
-; line    62 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
-;              EG_TUNE ] );
-; line    63 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR
-;              EG_C_ACC_ZH ] );
-; line    64 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 3, vreg_ctr[ VR
-;              EG_C_TUNE ] );
-; line    65 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 2, vreg_ctr[ VR
-;              EG_C_SND_VOL ] );
-; line    66 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 1, vreg_ctr[ VR
-;              EG_C_STATUS ] );
-; line    67 : //    iic_mcu_write_a_byte( IIC_SLA_DBG_MONITOR, 0, vreg_ctr[ VR
-;              EG_C_ACC_ZH ] );
-; line    68 : 
-; line    69 :         iic_mcu_write( IIC_SLA_DBG_MONITOR, 0, 4, &str[0] );
-$DGL	0,27
-	movw	ax,hl						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	movw	ax,#04H	; 4 					;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	clrw	ax						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#044H	; 68 					;[INF] 2, 1
-	call	!_iic_mcu_write					;[INF] 3, 3
-	addw	sp,#06H	; 6 					;[INF] 2, 1
-??eb00_tsk_debug2:
-; line    70 :     }
-?L0009:
-; line    71 :     return;
-; line    72 : }
-$DGL	0,30
-??ef_tsk_debug2:
-	addw	sp,#04H						;[INF] 2, 1
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_tsk_debug2:
-
-@@CODEL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_debug.c
-;
-; $FUNC tsk_debug(16)
-;	void=(void)
-;	CODE SIZE= 7 bytes, CLOCK_SIZE= 9 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC tsk_debug2(43)
-;	void=(void)
-;	CODE SIZE= 55 bytes, CLOCK_SIZE= 40 clocks, STACK_SIZE= 16 bytes
-;
-; $CALL iic_mcu_write(69)
-;	bc=(int:ax, int:[sp+4], int:[sp+6], pointer:[sp+8])
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_misc.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_misc.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_sys.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/task_sys.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/vreg_ctr.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/vreg_ctr.asm
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/vreg_twl.asm
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/inter_asm/vreg_twl.asm
@ -1,738 +0,0 @@
-; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24
-
-; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c
-; In-file   : vreg_twl.c
-; Asm-file  : inter_asm\vreg_twl.asm
-; Para-file : 
-
-$PROCESSOR(9F0104)
-$DEBUG
-$NODEBUGA
-$KANJICODE SJIS
-$TOL_INF	03FH, 0210H, 02H, 00H, 00H, 00H, 00H
-
-$DGS	FIL_NAM, .file,		062H,	0FFFEH,	03FH,	067H,	01H,	00H
-$DGS	AUX_FIL, vreg_twl.c
-$DGS	MOD_NAM, vreg_twl,	00H,	0FFFEH,	00H,	077H,	00H,	00H
-$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
-$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
-$DGS	LAB_SYM, bs_S0051,	U,	U,	00H,	06H,	00H,	00H
-$DGS	LAB_SYM, es_S0051,	U,	U,	00H,	06H,	00H,	00H
-$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
-$DGS	STA_SYM, _tasks,	U,	U,	01H,	03H,	01H,	027H
-$DGS	AUX_STR, 00H,		00H,	016H,	0BH,	00H,	00H,	00H,	04H
-$DGS	GLV_SYM, _vreg_twl_init,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	01FH,	00H,	00H
-$DGS	BEG_FUN, ??bf_vreg_twl_init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 019H,		00H,	01FH
-$DGS	END_FUN, ??ef_vreg_twl_init,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 03H
-$DGS	GLV_SYM, _vreg_twl_write,	U,	U,	01H,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	033H,	00H,	00H
-$DGS	BEG_FUN, ??bf_vreg_twl_write,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 023H,		02H,	025H
-$DGS	REG_PAR, _adrs,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	REG_PAR, _data,		07H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 03H,		00H,	027H
-$DGS	BEG_BLK, ??bb01_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 05H,		00H,	02BH
-$DGS	END_BLK, ??eb01_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 08H
-$DGS	BEG_BLK, ??bb02_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 027H,		00H,	00H
-$DGS	END_BLK, ??eb02_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02AH
-$DGS	END_BLK, ??eb00_vreg_twl_write,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 02BH
-$DGS	END_FUN, ??ef_vreg_twl_write,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 02DH
-$DGS	GLV_SYM, _vreg_twl_read,	U,	U,	0CH,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	057H,	00H,	00H
-$DGS	BEG_FUN, ??bf_vreg_twl_read,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 059H,		02H,	039H
-$DGS	REG_PAR, _phy_adrs,	06H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	REG_VAR, _temp,		07H,	0FFFFH,	010CH,	04H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 04H,		00H,	03BH
-$DGS	BEG_BLK, ??bb01_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 09H,		00H,	03FH
-$DGS	END_BLK, ??eb01_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0BH
-$DGS	BEG_BLK, ??bb02_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0BH,		00H,	043H
-$DGS	END_BLK, ??eb02_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0DH
-$DGS	BEG_BLK, ??bb03_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0DH,		00H,	047H
-$DGS	END_BLK, ??eb03_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0FH
-$DGS	BEG_BLK, ??bb04_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 0FH,		00H,	04BH
-$DGS	END_BLK, ??eb04_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 011H
-$DGS	BEG_BLK, ??bb05_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 011H,		00H,	04FH
-$DGS	END_BLK, ??eb05_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 013H
-$DGS	BEG_BLK, ??bb06_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 013H,		00H,	00H
-$DGS	END_BLK, ??eb06_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 015H
-$DGS	END_BLK, ??eb00_vreg_twl_read,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 023H
-$DGS	END_FUN, ??ef_vreg_twl_read,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 024H
-$DGS	GLV_SYM, _adrs_table_twl_ext2int,	U,	U,	0CH,	026H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	062H,	00H,	00H
-$DGS	BEG_FUN, ??bf_adrs_table_twl_ext2int,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_BEG, 084H,		02H,	05CH
-$DGS	REG_PAR, _img,		06H,	0FFFFH,	010CH,	011H,	00H,	00H
-$DGS	BEG_BLK, ??bb00_adrs_table_twl_ext2int,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_BEG, 02H,		00H,	00H
-$DGS	END_BLK, ??eb00_adrs_table_twl_ext2int,	U,	U,	00H,	064H,	01H,	00H
-$DGS	AUX_END, 0EH
-$DGS	END_FUN, ??ef_adrs_table_twl_ext2int,	U,	U,	00H,	065H,	01H,	00H
-$DGS	AUX_END, 0FH
-$DGS	GLV_SYM, _vreg_twl,	U,	U,	0CH,	026H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	0FH,	0FH,	00H,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_sw,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_adc,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_batt,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_led_pow,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_led_wifi,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_led_notify,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_led_cam,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_misc_stat,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_debug,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_debug2,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _tsk_sys,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _set_irq,	U,	U,	01H,	02H,	01H,	02H
-$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
-$DGS	GLV_SYM, _vreg_ctr,	U,	U,	0CH,	02H,	01H,	03H
-$DGS	AUX_STR, 00H,		00H,	01H,	01H,	00H,	00H,	00H,	00H
-
-	EXTRN	_tsk_sw
-	EXTRN	_tsk_adc
-	EXTRN	_tsk_batt
-	EXTRN	_tsk_led_pow
-	EXTRN	_tsk_led_wifi
-	EXTRN	_tsk_led_notify
-	EXTRN	_tsk_led_cam
-	EXTRN	_tsk_misc_stat
-	EXTRN	_tsk_debug
-	EXTRN	_tsk_debug2
-	EXTRN	_tsk_sys
-	EXTRN	_set_irq
-	EXTRN	_vreg_ctr
-	PUBLIC	_vreg_twl
-	PUBLIC	_vreg_twl_init
-	PUBLIC	_vreg_twl_write
-	PUBLIC	_vreg_twl_read
-	PUBLIC	_adrs_table_twl_ext2int
-
-@@BITS	BSEG
-
-@@CNST	CSEG	MIRRORP
-_lpf_coeff:	DB	01H	; 1
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	00H	; 0
-	DB	0FEH	; 254
-	DB	0FBH	; 251
-	DB	0F7H	; 247
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0FAH	; 250
-	DB	04H	; 4
-	DB	012H	; 18
-	DB	025H	; 37
-	DB	038H	; 56
-	DB	04DH	; 77
-	DB	05FH	; 95
-	DB	06EH	; 110
-	DB	077H	; 119
-	DB	07AH	; 122
-	DB	077H	; 119
-	DB	06EH	; 110
-	DB	05FH	; 95
-	DB	04DH	; 77
-	DB	038H	; 56
-	DB	025H	; 37
-	DB	012H	; 18
-	DB	04H	; 4
-	DB	0FAH	; 250
-	DB	0F3H	; 243
-	DB	0F0H	; 240
-	DB	0F0H	; 240
-	DB	0F3H	; 243
-	DB	0F7H	; 247
-	DB	0FBH	; 251
-	DB	0FEH	; 254
-	DB	00H	; 0
-	DB	02H	; 2
-	DB	03H	; 3
-	DB	03H	; 3
-	DB	02H	; 2
-	DB	02H	; 2
-	DB	01H	; 1
-	DB	(1)
-
-@@R_INIT	CSEG	UNIT64KP
-	DW	loww (_tsk_sw)
-	DW	loww (_tsk_adc)
-	DW	loww (_tsk_batt)
-	DW	loww (_tsk_led_pow)
-	DW	loww (_tsk_led_wifi)
-	DW	loww (_tsk_led_notify)
-	DW	loww (_tsk_led_cam)
-	DW	loww (_tsk_misc_stat)
-	DW	loww (_tsk_debug)
-	DW	loww (_tsk_debug2)
-	DW	loww (_tsk_sys)
-
-@@INIT	DSEG	BASEP
-_tasks:	DS	(22)
-
-@@DATA	DSEG	BASEP
-_vreg_twl:	DS	(15)
-	DS	(1)
-
-@@R_INIS	CSEG	UNIT64KP
-
-@@INIS	DSEG	SADDRP
-
-@@DATS	DSEG	SADDRP
-
-@@CNSTL	CSEG	PAGE64KP
-
-@@RLINIT	CSEG	UNIT64KP
-
-@@INITL	DSEG	UNIT64KP
-
-@@DATAL	DSEG	UNIT64KP
-
-@@CALT	CSEG	CALLT0
-
-; Sub-Routines created by CC78K0R
-
-ROM_CODE	CSEG	BASE
-bs_S0051:
-	mov	a,h						;[INF] 1, 1
-	and	a,#03H	; 3 					;[INF] 2, 1
-	mov	c,a						;[INF] 1, 1
-	mov	a,l						;[INF] 1, 1
-	mov	b,a						;[INF] 1, 1
-	mov	a,c						;[INF] 1, 1
-	mov	_vreg_twl[b],a					;[INF] 3, 1
-	ret							;[INF] 1, 6
-es_S0051:
-
-; *** Sub-Routine Information ***
-;
-; $SUB bs_S0051
-;      CODE SIZE= 11 bytes
-
-; End of Sub-Routines
-
-; line     1 : /* ========================================================
-; line     2 : 
-; line     3 : TWL互換側のI2Cレジスタ
-; line     4 : 
-; line     5 :  ======================================================== */
-; line     6 : #include "incs.h"
-; line     7 : #include "jhl_defs.h"
-; line     8 : #include "vreg_twl.h"
-; line     9 : 
-; line    10 : #include "vreg_ctr.h"
-; line    11 : #include "renge\renge_task_intval.h"
-; line    12 : 
-; line    13 : // ========================================================
-; line    14 : #define TWL_REG_VER_INFO               0x35
-; line    15 : #define NON_EXIST_REG                  0xFF
-; line    16 : 
-; line    17 : // ========================================================
-; line    18 : u8      vreg_twl[_REG_TWL_INT_ADRS_ENDMARK];
-; line    19 : 
-; line    20 : 
-; line    21 : /* ========================================================
-; line    22 :   仮想レジスタの初期化
-; line    23 :  ======================================================== */
-; line    24 : void vreg_twl_init(  )
-; line    25 : {
-
-ROM_CODE	CSEG	BASE
-_vreg_twl_init:
-$DGL	1,25
-??bf_vreg_twl_init:
-; line    26 :     vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03;
-$DGL	0,2
-	mov	!_vreg_twl+3,#03H	; 3 			;[INF] 4, 1
-; line    27 : }
-$DGL	0,3
-??ef_vreg_twl_init:
-	ret							;[INF] 1, 6
-??ee_vreg_twl_init:
-; line    28 : 
-; line    29 : 
-; line    30 : // ========================================================
-; line    31 : // I2C仮想レジスタに書く・何かアクションする
-; line    32 : //　引数 adrs は内部アドレス
-; line    33 : //  　存在しないアドレスにアクセスした場合、何もしません。
-; line    34 : void vreg_twl_write( u8 adrs, u8 data )
-; line    35 : {
-_vreg_twl_write:
-$DGL	1,31
-	push	hl						;[INF] 1, 1
-	mov	a,[sp+6]					;[INF] 2, 1
-	movw	hl,ax						;[INF] 1, 1
-??bf_vreg_twl_write:
-; line    36 :     switch ( adrs )
-$DGL	0,2
-	movw	ax,hl						;[INF] 1, 1
-	clrb	a						;[INF] 1, 1
-	onew	bc						;[INF] 1, 1
-	movw	de,#02H	; 2 					;[INF] 3, 1
-	subw	ax,de						;[INF] 1, 1
-	bz	$?L0010						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0007						;[INF] 2, 4
-	subw	ax,de						;[INF] 1, 1
-	bz	$?L0008						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0006						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0009						;[INF] 2, 4
-	br	$?L0013						;[INF] 2, 3
-; line    37 :     {
-??bb00_vreg_twl_write:
-; line    38 :       case ( REG_TWL_INT_ADRS_VOL ):
-?L0006:
-; line    39 :         {
-??bb01_vreg_twl_write:
-; line    40 :             set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE );
-$DGL	0,6
-	movw	ax,#040H	; 64 				;[INF] 3, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#012H	; 18 					;[INF] 2, 1
-	call	!_set_irq					;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line    41 :             break;
-$DGL	0,7
-	br	$?L0013						;[INF] 2, 3
-??eb01_vreg_twl_write:
-; line    42 :         }
-; line    43 : 
-; line    44 :       case ( REG_TWL_INT_ADRS_MODE ):
-?L0007:
-; line    45 :         vreg_twl[adrs] = ( data & 0x03 );
-$DGL	0,11
-	call	!bs_S0051					;[INF] 3, 3
-; line    46 :         break;
-$DGL	0,12
-	br	$?L0013						;[INF] 2, 3
-; line    47 : 
-; line    48 :       case ( REG_TWL_INT_ADRS_CAM ):
-?L0008:
-; line    49 :         vreg_twl[adrs] = ( data & 0x03 );
-$DGL	0,15
-	call	!bs_S0051					;[INF] 3, 3
-; line    50 :         tsk_led_cam();  // todo 大丈夫？
-$DGL	0,16
-	call	!_tsk_led_cam					;[INF] 3, 3
-; line    51 :         break;
-$DGL	0,17
-	br	$?L0013						;[INF] 2, 3
-; line    52 : 
-; line    53 :       case ( REG_TWL_INT_ADRS_TEMP0 ):
-?L0009:
-; line    54 :         vreg_twl[adrs] = data;
-$DGL	0,20
-	mov	a,l						;[INF] 1, 1
-	mov	b,a						;[INF] 1, 1
-	mov	a,h						;[INF] 1, 1
-	mov	_vreg_twl[b],a					;[INF] 3, 1
-; line    55 :         break;
-$DGL	0,21
-	br	$?L0013						;[INF] 2, 3
-; line    56 : 
-; line    57 :       case ( REG_TWL_INT_ADRS_COMMAND ):
-?L0010:
-; line    58 : /*
-; line    59 :         if( data <= 2 ){
-; line    60 :             if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 )
-; line    61 :             {
-; line    62 :                 set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );    
-;                // OFFも実装していたらしい。
-; line    63 :                 break;
-; line    64 :             }
-; line    65 :             else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 )
-; line    66 :             {
-; line    67 :                 set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );  
-;                  //リセットしかない。他のは、SPIから来ます。
-; line    68 :                 break;
-; line    69 :             }
-; line    70 :           }
-; line    71 : */
-; line    72 :         if( data == REG_BIT_TWL_RESET_REQ )
-$DGL	0,38
-	mov	a,h						;[INF] 1, 1
-	dec	a						;[INF] 1, 1
-	bnz	$?L0013						;[INF] 2, 4
-; line    73 :         {
-??bb02_vreg_twl_write:
-; line    74 :             set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );      
-;              //リセットしかない。他のは、SPIから来ます。
-$DGL	0,40
-	onew	ax						;[INF] 1, 1
-	push	ax						;[INF] 1, 1
-	mov	x,#012H	; 18 					;[INF] 2, 1
-	call	!_set_irq					;[INF] 3, 3
-	pop	ax						;[INF] 1, 1
-; line    75 :             break;
-??eb02_vreg_twl_write:
-; line    76 :         }
-?L0013:
-??eb00_vreg_twl_write:
-; line    77 :     }
-; line    78 :     return;
-; line    79 : }
-$DGL	0,45
-??ef_vreg_twl_write:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_vreg_twl_write:
-; line    80 : 
-; line    81 : 
-; line    82 : 
-; line    83 : // ========================================================
-; line    84 : // I2C仮想レジスタから読みます。
-; line    85 : //　引数 adrs 外から見たときの、アドレス
-; line    86 : //　戻り   xx データ
-; line    87 : //  　存在しないアドレスにアクセスした場合、戻り値は0x5A
-; line    88 : u8 vreg_twl_read( u8 phy_adrs )
-; line    89 : {
-_vreg_twl_read:
-$DGL	1,51
-	push	hl						;[INF] 1, 1
-	movw	hl,ax						;[INF] 1, 1
-??bf_vreg_twl_read:
-; line    90 :     u8 temp;
-; line    91 : 
-; line    92 :     switch( phy_adrs ){
-$DGL	0,4
-	movw	ax,hl						;[INF] 1, 1
-	clrb	a						;[INF] 1, 1
-	onew	bc						;[INF] 1, 1
-	subw	ax,#00H	; 0 					;[INF] 3, 1
-	bz	$?L0018						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0020						;[INF] 2, 4
-	subw	ax,#03H	; 3 					;[INF] 3, 1
-	bz	$?L0019						;[INF] 2, 4
-	subw	ax,#0FBH	; 251 				;[INF] 3, 1
-	bz	$?L0022						;[INF] 2, 4
-	br	$?L0021						;[INF] 2, 3
-??bb00_vreg_twl_read:
-; line    93 :       case( REG_TWL_INT_ADRS_VER_INFO ):
-?L0018:
-; line    94 :           return( TWL_REG_VER_INFO );
-$DGL	0,6
-	movw	bc,#035H	; 53 				;[INF] 3, 1
-	br	$?L0017						;[INF] 2, 3
-; line    95 : 
-; line    96 :       case( REG_TWL_INT_ADRS_POWER_INFO ):
-?L0019:
-; line    97 :           if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){
-$DGL	0,9
-	cmp	!_vreg_ctr+11,#05BH	; 91 			;[INF] 4, 1
-	bc	$?L0025						;[INF] 2, 4
-??bb01_vreg_twl_read:
-; line    98 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F;
-$DGL	0,10
-	mov	!_vreg_twl+4,#0FH	; 15 			;[INF] 4, 1
-??eb01_vreg_twl_read:
-; line    99 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){
-$DGL	0,11
-	br	$?L0034						;[INF] 2, 3
-?L0025:
-	cmp	!_vreg_ctr+11,#04CH	; 76 			;[INF] 4, 1
-	bc	$?L0027						;[INF] 2, 4
-??bb02_vreg_twl_read:
-; line   100 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B;
-$DGL	0,12
-	mov	!_vreg_twl+4,#0BH	; 11 			;[INF] 4, 1
-??eb02_vreg_twl_read:
-; line   101 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){
-$DGL	0,13
-	br	$?L0034						;[INF] 2, 3
-?L0027:
-	cmp	!_vreg_ctr+11,#033H	; 51 			;[INF] 4, 1
-	bc	$?L0029						;[INF] 2, 4
-??bb03_vreg_twl_read:
-; line   102 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07;
-$DGL	0,14
-	mov	!_vreg_twl+4,#07H	; 7 			;[INF] 4, 1
-??eb03_vreg_twl_read:
-; line   103 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){
-$DGL	0,15
-	br	$?L0034						;[INF] 2, 3
-?L0029:
-	cmp	!_vreg_ctr+11,#01AH	; 26 			;[INF] 4, 1
-	bc	$?L0031						;[INF] 2, 4
-??bb04_vreg_twl_read:
-; line   104 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03;
-$DGL	0,16
-	mov	!_vreg_twl+4,#03H	; 3 			;[INF] 4, 1
-??eb04_vreg_twl_read:
-; line   105 :           }else if( vreg_ctr[ VREG_C_BT_REMAIN ] >  5 ){
-$DGL	0,17
-	br	$?L0034						;[INF] 2, 3
-?L0031:
-	cmp	!_vreg_ctr+11,#06H	; 6 			;[INF] 4, 1
-	bc	$?L0033						;[INF] 2, 4
-??bb05_vreg_twl_read:
-; line   106 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01;
-$DGL	0,18
-	oneb	!_vreg_twl+4					;[INF] 3, 1
-??eb05_vreg_twl_read:
-; line   107 :           }else{
-$DGL	0,19
-	br	$?L0034						;[INF] 2, 3
-?L0033:
-??bb06_vreg_twl_read:
-; line   108 :               vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00;
-$DGL	0,20
-	clrb	!_vreg_twl+4					;[INF] 3, 1
-??eb06_vreg_twl_read:
-; line   109 :           }
-?L0034:
-; line   110 : 
-; line   111 :           return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !B
-;              T_CHG_n ? 0x80: 0x00 ) );  // アダプタbit
-$DGL	0,23
-	bt	P5.1,$?L0035					;[INF] 4, 5
-	movw	ax,#080H	; 128 				;[INF] 3, 1
-	br	$?L0036						;[INF] 2, 3
-?L0035:
-	clrw	ax						;[INF] 1, 1
-?L0036:
-	xch	a,x						;[INF] 1, 1
-	or	a,!_vreg_twl+4					;[INF] 3, 1
-	xch	a,x						;[INF] 1, 1
-	movw	bc,ax						;[INF] 1, 1
-	br	$?L0017						;[INF] 2, 3
-; line   112 : 
-; line   113 :       case( REG_TWL_INT_ADRS_IRQ ):
-?L0020:
-; line   114 :           temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ];
-$DGL	0,26
-	mov	a,!_vreg_twl+1					;[INF] 3, 1
-; line   115 :           vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;
-$DGL	0,27
-	clrb	!_vreg_twl+1					;[INF] 3, 1
-; line   116 :           return( temp );
-$DGL	0,28
-	shrw	ax,8						;[INF] 2, 1
-	movw	bc,ax						;[INF] 1, 1
-	br	$?L0017						;[INF] 2, 3
-; line   117 : 
-; line   118 :       default:
-?L0021:
-; line   119 :           return( vreg_twl[ phy_adrs ] );
-$DGL	0,31
-	mov	a,l						;[INF] 1, 1
-	mov	b,a						;[INF] 1, 1
-	mov	a,_vreg_twl[b]					;[INF] 3, 1
-	shrw	ax,8						;[INF] 2, 1
-	movw	bc,ax						;[INF] 1, 1
-	br	$?L0017						;[INF] 2, 3
-; line   120 : 
-; line   121 :       case( REG_TWL_ADRS_NON_EXIST ):
-?L0022:
-; line   122 :           return( 0x00 );
-$DGL	0,34
-	clrw	bc						;[INF] 1, 1
-??eb00_vreg_twl_read:
-; line   123 :     }
-?L0017:
-; line   124 : }
-$DGL	0,36
-??ef_vreg_twl_read:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_vreg_twl_read:
-; line   125 : 
-; line   126 : 
-; line   127 : 
-; line   128 : // ========================================================
-; line   129 : // 外部から見える虫食いアドレスを、内部の連続アドレスに読み替える
-; line   130 : // 0xFFは存在しないアドレス。
-; line   131 : u8 adrs_table_twl_ext2int( u8 img )
-; line   132 : {
-_adrs_table_twl_ext2int:
-$DGL	1,87
-	push	hl						;[INF] 1, 1
-	movw	hl,ax						;[INF] 1, 1
-??bf_adrs_table_twl_ext2int:
-; line   133 :     switch( img ){
-$DGL	0,2
-	movw	ax,hl						;[INF] 1, 1
-	clrb	a						;[INF] 1, 1
-	onew	bc						;[INF] 1, 1
-	subw	ax,#00H	; 0 					;[INF] 3, 1
-	bz	$?L0046						;[INF] 2, 4
-	subw	ax,#010H	; 16 				;[INF] 3, 1
-	bz	$?L0040						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0041						;[INF] 2, 4
-	subw	ax,bc						;[INF] 1, 1
-	bz	$?L0047						;[INF] 2, 4
-	subw	ax,#0EH	; 14 					;[INF] 3, 1
-	bz	$?L0042						;[INF] 2, 4
-	subw	ax,#011H	; 17 				;[INF] 3, 1
-	bz	$?L0043						;[INF] 2, 4
-	subw	ax,#0FH	; 15 					;[INF] 3, 1
-	bz	$?L0044						;[INF] 2, 4
-	subw	ax,#030H	; 48 				;[INF] 3, 1
-	bz	$?L0045						;[INF] 2, 4
-	br	$?L0048						;[INF] 2, 3
-??bb00_adrs_table_twl_ext2int:
-; line   134 :       case( REG_TWL_ADRS_IRQ ):        return( REG_TWL_INT_ADRS_
-;              IRQ );
-$DGL	0,3
-?L0040:
-	onew	bc						;[INF] 1, 1
-	br	$?L0039						;[INF] 2, 3
-; line   135 :       case( REG_TWL_ADRS_COMMAND ):    return( REG_TWL_INT_ADRS_
-;              COMMAND );
-$DGL	0,4
-?L0041:
-	onew	bc						;[INF] 1, 1
-	incw	bc						;[INF] 1, 1
-	br	$?L0039						;[INF] 2, 3
-; line   136 :       case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_
-;              POWER_INFO );
-$DGL	0,5
-?L0042:
-	movw	bc,#04H	; 4 					;[INF] 3, 1
-	br	$?L0039						;[INF] 2, 3
-; line   137 :       case( REG_TWL_ADRS_CAM ):        return( REG_TWL_INT_ADRS_
-;              CAM );
-$DGL	0,6
-?L0043:
-	movw	bc,#05H	; 5 					;[INF] 3, 1
-	br	$?L0039						;[INF] 2, 3
-; line   138 :       case( REG_TWL_ADRS_VOL ):        return( REG_TWL_INT_ADRS_
-;              VOL );
-$DGL	0,7
-?L0044:
-	movw	bc,#06H	; 6 					;[INF] 3, 1
-	br	$?L0039						;[INF] 2, 3
-; line   139 :       case( REG_TWL_ADRS_TEMP0 ):      return( REG_TWL_INT_ADRS_
-;              TEMP0 );
-$DGL	0,8
-?L0045:
-	movw	bc,#07H	; 7 					;[INF] 3, 1
-	br	$?L0039						;[INF] 2, 3
-; line   140 :       case( REG_TWL_ADRS_VER_INFO ):   return( REG_TWL_INT_ADRS_
-;              VER_INFO );
-$DGL	0,9
-?L0046:
-	clrw	bc						;[INF] 1, 1
-	br	$?L0039						;[INF] 2, 3
-; line   141 :       case( REG_TWL_ADRS_MODE ):       return( REG_TWL_INT_ADRS_
-;              MODE );
-$DGL	0,10
-?L0047:
-	movw	bc,#03H	; 3 					;[INF] 3, 1
-	br	$?L0039						;[INF] 2, 3
-; line   142 :       default:                         return( REG_TWL_ADRS_NON_
-;              EXIST );
-$DGL	0,11
-?L0048:
-	clrw	bc						;[INF] 1, 1
-	dec	c						;[INF] 1, 1
-??eb00_adrs_table_twl_ext2int:
-; line   143 : //      0が読めればよい、書けなくて良い
-; line   144 : //      case( REG_TWL_ADRS_WIFI ):       return( REG_TWL_INT_ADR
-;              S_WIFI );
-; line   145 :     }
-?L0039:
-; line   146 : }
-$DGL	0,15
-??ef_adrs_table_twl_ext2int:
-	pop	hl						;[INF] 1, 1
-	ret							;[INF] 1, 6
-??ee_adrs_table_twl_ext2int:
-
-@@CODEL	CSEG
-
-@@BASE	CSEG	BASE
-	END
-
-
-; *** Code Information ***
-;
-; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c
-;
-; $FUNC vreg_twl_init(25)
-;	void=(void)
-;	CODE SIZE= 5 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
-;
-; $FUNC vreg_twl_write(35)
-;	void=(unsigned char adrs:x, unsigned char data:[sp+6])
-;	CODE SIZE= 74 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 8 bytes
-;
-; $CALL set_irq(40)
-;	void=(int:ax, int:[sp+4])
-;
-; $CALL tsk_led_cam(50)
-;	void=(void)
-;
-; $CALL set_irq(74)
-;	void=(int:ax, int:[sp+4])
-;
-; $FUNC vreg_twl_read(89)
-;	bc=(unsigned char phy_adrs:x)
-;	CODE SIZE= 134 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 2 bytes
-;
-; $FUNC adrs_table_twl_ext2int(132)
-;	bc=(unsigned char img:x)
-;	CODE SIZE= 82 bytes, CLOCK_SIZE= 90 clocks, STACK_SIZE= 2 bytes
-
-; Target chip : uPD79F0104
-; Device file : E1.00b
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/jhl_defs.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/jhl_defs.h
@ -1,26 +0,0 @@
-#ifndef __jhl_defs_h__
-#define __jhl_defs_h__
-
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-
-typedef unsigned char err;
-
-
-#include "config.h"
-
-
-
-#define set_bit( cond, reg, pos ) \
-{                                 \
-  if( cond ){                     \
-    reg |= pos;                   \
-  }else{                          \
-    reg &= ~pos;                  \
-  }                               \
-}
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.c
@ -1,618 +0,0 @@
-/* ========================================================
-  LED.c
-
- ======================================================== */
-#pragma sfr
-
-
-#include "incs.h"
-#include "led.h"
-
-
-
-// ========================================================
-// TPS0
-#define BIT_PRS012             ( 1 << 2 )
-#define BIT_PRS002             ( 1 << 6 )
-
-// TMR0
-#define BIT_CKS0             15
-#define BIT_CCS0             12
-#define BIT_MASTER0          11
-#define BIT_STS0              8
-#define BIT_CIS0              6
-#define BIT_MD123             1
-#define BIT_MD0               0
-
-// ========================================================
-static void led_pow_normal(  );
-static void led_pow_hotaru(  );
-
-
-
-// ========================================================
-static const char MSG_MAIL[] = { 0b11110110, 0b11011010, 0b01101110, 0b10010100 };
-#define MSG_SPD    60
-// ↑255/3以下であること！
-
-// ========================================================
-void LED_init(  )
-{
-/**
-  PWMのセット、とりあえず全部消灯
-
-  マスタチャネル：０　(P01:/reset2)　マスターは偶数チャネルしかできない
-  スレーブ　　　　１　ＳＬＴＯ。(３Ｄ ＬＥＤ？)
-  　　　　　　　　２　カメラ
-  　　　　　　　　３　WiFi
-  　　　　　　　　４　(ピンはＲＴＣ32kHz out に使用)
-  　　　　　　　　５　充電
-  　　　　　　　　６　電源 Ｌ
-  　　　　　　　　７　電源 Ｈ
- */
-    TAU0EN = 1;
-    TPS0 = BIT_PRS012 | BIT_PRS002;     // マスタークロックはCK01,8M/2 /2^4 = 250kHz
-
-    TMR00 =
-        1 << BIT_CKS0 | 0 << BIT_CCS0 | 1 << BIT_MASTER0 | 0 << BIT_STS0 | 0
-        << BIT_CIS0 | 0 << BIT_MD123 | 1 << BIT_MD0;
-    TMR01 = TMR02 = TMR03 = TMR04 = TMR05 = TMR06 = TMR07 =
-        1 << BIT_CKS0 | 0 << BIT_CCS0 | 0 << BIT_MASTER0 | 4 << BIT_STS0 | 0
-        << BIT_CIS0 | 4 << BIT_MD123 | 1 << BIT_MD0;
-    ISC = 0;
-    TOM0 = 0b0000000011111110; // 出力モード。4はPWM出力しないが1にしないとTO5以降にクロックが届かない
-
-#ifdef _MCU_BSR_
-    TOL0 = 0b0000000000000000; // 出力を反転させるかフラグ
-#else
-    TOL0 = 0b0000000000000100; // 出力を反転させるかフラグ
-#endif
-
-    TO0 = 0;                    // タイマー動作中で、タイマー出力にしてないときのピンのラッチ。タイマー出力を使わないなら０
-    TOE0 = 0b0000000011101110; // TOxをタイマーモジュールが制御？
-    TS0 = 0b0000000011101111;  // 動作開始
-
-    TDR00 = LED_BRIGHT_MAX - 1; // 10bit, 周期
-
-    if( system_status.reboot )
-    {
-        vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO;
-        LED_duty_pow_H = LED_BRIGHT_MAX;
-    }
-}
-
-
-
-void LED_stop(  )
-{
-    TT0 = 0b0000000011101111;  // 一斉停止（しないとだめ）
-    TOE0 = 0b0000000000000000; // TOxをタイマーモジュールが制御？(GPIOになる)
-    TAU0EN = 0;
-}
-
-
-
-
-/* ========================================================
-  // 電源LED
-  LED_POW_B,R         6,7
-
-  TDR00　周期(0x03FF。TPS0で250kHzでカウントアップ。10bitなら250Hz位になる)
-  TDR0x　Duty 0で消灯、TDR00(より大 =0x03FF以上)で点灯です。
-
-  enum pwr_state_{
-  OFF_TRIG = 0,
-  OFF,
-  ON_TRIG,
-  ON,
-  SLEEP_TRIG,
-  SLEEP
-};
-
-enum LED_ILUM_MODE{
-  LED_POW_ILM_AUTO,
-  LED_POW_ILM_ON,
-  LED_POW_ILM_HOTARU,
-  LED_POW_ILM_CEOFF
-};
- ======================================================== */
-void tsk_led_pow(  )
-{
-    switch ( vreg_ctr[VREG_C_LED_POW] )
-    {
-        // 自動切り替え
-    case ( LED_POW_ILM_AUTO ):
-        switch ( system_status.pwr_state )
-        {
-        case SLEEP:
-            led_pow_hotaru(  );
-            break;
-
-        case ON:
-            led_pow_normal(  );
-            break;
-
-        default:
-            break;
-        }
-        break;
-
-        // 強制
-    case ( LED_POW_ILM_OFF ):
-        LED_duty_pow_H -= ( LED_duty_pow_H == 0x0000 ) ? 0 : 1;
-        LED_duty_pow_L -= ( LED_duty_pow_L == 0x0000 ) ? 0 : 1;
-        break;
-
-    case ( LED_POW_ILM_HOTARU ):
-        led_pow_hotaru(  );
-        break;
-
-    case ( LED_POW_ILM_ON ):
-    default:
-        led_pow_normal(  );
-        break;
-
-    case ( LED_POW_ILM_ONLY_RED ):
-        LED_duty_pow_H = 0x0000;
-        LED_duty_pow_L = LED_BRIGHT_MAX;
-        break;
-
-    case ( LED_POW_ILM_ONLY_BLUE ):
-        LED_duty_pow_H = LED_BRIGHT_MAX;
-        LED_duty_pow_L = 0x0000;
-        break;
-    }
-
-}
-
-
-
-/* ========================================================
-  電池残量で、　青→赤→赤点滅
- ======================================================== */
-static void led_pow_normal(  )
-{
-    static u8 state;
-
-    if( vreg_ctr[VREG_C_BT_REMAIN] < 3 )
-    {
-        // 赤点滅
-        state++;
-        if( state < 127 )
-        {
-            LED_duty_pow_H = 0x0000;
-            LED_duty_pow_L = 0x0000;
-        }
-        else
-        {
-            LED_duty_pow_L = vreg_ctr[VREG_C_LED_BRIGHT];
-        }
-        return;
-
-    }
-    else if( vreg_ctr[VREG_C_BT_REMAIN] < 12 )
-    {
-        // 赤点灯
-        if( LED_duty_pow_H != 0x0000 )
-        {                       // 青フェードアウト
-            LED_duty_pow_H -= 1;
-        }
-        if( LED_duty_pow_L != vreg_ctr[VREG_C_LED_BRIGHT] )
-        {                       // 赤フェードイン
-            LED_duty_pow_L += ( LED_duty_pow_L < vreg_ctr[VREG_C_LED_BRIGHT] ) ? 1 : -1;
-        }
-        return;
-
-    }
-    else
-    {
-        // 青点灯
-        if( LED_duty_pow_H != vreg_ctr[VREG_C_LED_BRIGHT] )
-        {
-            LED_duty_pow_H += ( LED_duty_pow_H < vreg_ctr[VREG_C_LED_BRIGHT] ) ? 1 : -1;
-        }
-        if( LED_duty_pow_L != 0x0000 )
-        {
-            LED_duty_pow_L -= 1;
-        }
-    }
-
-    return;
-}
-
-
-
-/* ========================================================
-  ホタルパターン
- ======================================================== */
-static void led_pow_hotaru(  )
-{
-    static u8 delay;
-    static u8 state;
-    static u16 blue_to;
-    static u16 red_to;
-
-    if( delay != 0 )
-    {
-        delay -= 1;
-        return;
-    }
-    else
-    {
-        delay = 10;
-    }
-
-    if( LED_duty_pow_L != red_to )
-    {
-        if( LED_duty_pow_L > red_to )
-        {
-            LED_duty_pow_L -= 1;
-        }
-        else
-        {
-            LED_duty_pow_L += 2;
-        }
-    }
-
-    if( LED_duty_pow_H != blue_to )
-    {
-        if( LED_duty_pow_H > blue_to )
-        {
-            LED_duty_pow_H -= 1;
-        }
-        else
-        {
-            LED_duty_pow_H += 2;
-        }
-    }
-
-    switch ( state )
-    {
-        // フェードイン
-    case ( 0 ):
-    case ( 2 ):
-    case ( 4 ):
-        if( vreg_ctr[VREG_C_BT_REMAIN] < 12 )
-        {
-            // 赤いとき
-            blue_to = 0;
-            red_to = vreg_ctr[VREG_C_LED_BRIGHT];
-        }
-        else
-        {
-            blue_to = vreg_ctr[VREG_C_LED_BRIGHT];
-            red_to = 0;
-        }
-        break;
-
-    default:
-        // フェードアウト
-        if( vreg_ctr[VREG_C_BT_REMAIN] < 12 )
-        {
-            red_to = 2;
-        }
-        else
-        {
-            blue_to = 2;
-        }
-        break;
-    }
-
-    if( ( LED_duty_pow_H == blue_to ) && ( LED_duty_pow_L == red_to ) )
-    {
-        state += 1;
-    }
-    return;
-}
-
-
-
-/* ========================================================
-  * 割り込みそのものは使いません *
-  LED_Wifi           3
-  todo 直書きの点滅間隔など
- ======================================================== */
-void tsk_led_wifi(  )
-{
-    static u8 task_interval;
-    static u8 remain_wifi_tx;
-    static u8 state_wifi_tx;
-    static u8 flag_wifi_TX;
-
-
-    if( task_interval-- != 0 )
-    {
-        return;
-    }
-
-    // 送信パルスのラッチ
-    if( vreg_ctr[VREG_C_LED_WIFI] == WIFI_LED_TXAUTO )
-    {
-        if( WIFI_txLatch )
-        {
-            WIFI_txLatch = 0;
-            flag_wifi_TX = 2;
-        }
-    }
-    else
-    {
-        flag_wifi_TX = 0;
-    }
-
-
-    switch ( vreg_ctr[VREG_C_LED_WIFI] )
-    {
-      case ( WIFI_LED_OFF ):
-      default:
-        LED_duty_WiFi = 0;
-        state_wifi_tx = 0;
-        remain_wifi_tx = 0;
-        break;
-
-      case ( WIFI_LED_ON ):
-        LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT];
-        state_wifi_tx = 0;
-        remain_wifi_tx = 0;
-        break;
-
-      case ( WIFI_LED_TXAUTO ):
-        if( flag_wifi_TX != 0 ) // 短いパルスを捕まえるために、割り込みフラグを見る
-        {
-            // 送信パターン
-            switch ( state_wifi_tx )
-            {
-              case ( 1 ):
-              case ( 3 ):
-              case ( 5 ):
-                LED_duty_WiFi = 0;
-                break;
-              default:
-                LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT];
-            }
-            state_wifi_tx++;
-            if( state_wifi_tx == 32 )
-            {
-                state_wifi_tx = 0;
-                flag_wifi_TX -= 1;
-            }
-            task_interval = 22;
-            return;
-        }
-        else
-        {
-            // 送信フラグ待ち
-            LED_duty_WiFi = vreg_ctr[VREG_C_LED_BRIGHT];
-            task_interval = 200;
-            return;
-        }
-        break;
-
-    }
-}
-
-
-
-
-/* ========================================================
-  * 割り込みそのものは使いません *
-  LED_Wifi2          P24 （未）
- ======================================================== */
-void tsk_led_notify(  )
-{
-    static u8 task_interval;
-    static u8 flg_char_space;
-    static u8 state_notify_led; // 点灯パターンの進行具合
-    static u8 flag_wifi_TX;
-
-
-    if( task_interval-- != 0 )
-    {
-        return;
-    }
-
-    switch ( vreg_ctr[VREG_C_LED_NOTIFY] )
-    {
-      case ( NOTIFY_LED_OFF ):
-      default:
-        LED_duty_NOTIFY = 0;
-        state_notify_led = 0;
-        flg_char_space = 0;
-        break;
-
-      case ( NOTIFY_LED_ON ):
-        LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT];
-        state_notify_led = 0;
-        flg_char_space = 0;
-        break;
-
-      case ( NOTIFY_LED_PTN0 ):
-        // ゆっくりバースト
-        switch ( state_notify_led )
-        {
-          case ( 1 ):
-          case ( 3 ):
-          case ( 5 ):
-            LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT];
-            break;
-          default:
-            LED_duty_NOTIFY = 0;
-        }
-        state_notify_led++;
-        if( state_notify_led == 16 )
-        {
-            state_notify_led = 0;
-        }
-        task_interval = 50;
-        return;
-
-    case ( NOTIFY_LED_PTN1 ):
-        // データテーブルに従って点滅
-        {
-            u8      dat;
-
-            task_interval = MSG_SPD; // 共通のため。場合によって上書き
-
-            if( flg_char_space != 0 )
-            {
-                LED_duty_NOTIFY = 0;
-                flg_char_space = 0;
-                return;
-            }
-
-            // データバッファの見る位置の更新
-            dat = ( MSG_MAIL[state_notify_led / 4] << ( ( state_notify_led % 4 ) * 2 ) ) & 0xC0;
-            if( dat == 0 )
-            {
-                state_notify_led = 0;
-            }
-            else
-            {
-                state_notify_led += 1;
-            }
-
-            flg_char_space = 1;
-            if(( dat & 0b10000000 ) != 0 )
-            {
-                // 点灯はさせる
-                LED_duty_NOTIFY = vreg_ctr[VREG_C_LED_BRIGHT];
-                if(( dat & 0b01000000 ) == 0 )
-                {
-                    // 短
-                    // nothing to do
-                }
-                else
-                {
-                    // 長
-                    task_interval = ( MSG_SPD * 3 );
-                }
-                // 次は単語間休み、とかの判定をさせたかったが
-                /// １バイトに２ビットずつデータが並んでおり、次のバイトに
-                /// またがるようなときが面倒なのでやめる
-                return;
-            }
-            else
-            {
-                if(( dat & 0b01000000 ) == 0 )
-                {
-                    // 一文終了
-                    task_interval = ( MSG_SPD * 3 );
-                }
-                else
-                {
-                    // 単語間
-                    // nothing to do
-                }
-                return;
-            }
-        }
-    }
-}
-
-
-
-
-/******************************************************//**
-  LED_Cam          TO02
-\n  BLINK,*_PLUSE の時は、1周期分は必ずその状態になります。
-\n  その間に OFF→BLINK などされると、OFFが無視されます。
- *********************************************************/
-void tsk_led_cam(  )
-{
-    static u8 state_led_cam = 0;
-    static u8 task_interval;
-    static u8 state_led_cam_twl;
-
-    if( task_interval != 0 )
-    {
-        task_interval -= 1;
-        return;
-    }
-
-    // ブリンクのように待たせたいとき以外は毎週起動する
-    //  (レジスタの変更にすぐに反応する)
-
-    switch ( vreg_ctr[VREG_C_LED_CAM] )
-    {
-    case ( CAM_LED_OFF ):
-    default:
-        LED_duty_CAM = 0;
-        state_led_cam = 0;
-        break;
-
-    case ( CAM_LED_ON ):
-        LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT];
-        state_led_cam = 0;
-        break;
-
-    case ( CAM_LED_BLINK ):
-        if( state_led_cam == 0 )
-        {
-            LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT];
-            state_led_cam = 1;
-        }
-        else
-        {
-            LED_duty_CAM = 0;
-            state_led_cam = 0;
-        }
-        task_interval = 250;
-        break;
-
-    case ( CAM_LED_ON_PLUSE ):
-        if( state_led_cam == 0 )
-        {
-            LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT];
-            state_led_cam = 1;
-            task_interval = 250;
-        }
-        else
-        {
-            vreg_ctr[VREG_C_LED_CAM] = CAM_LED_OFF;
-        }
-        break;
-
-    case ( CAM_LED_OFF_PLUSE ):
-        if( state_led_cam == 0 )
-        {
-            LED_duty_CAM = 0;
-            state_led_cam = 1;
-            task_interval = 250;
-        }
-        else
-        {
-            vreg_ctr[VREG_C_LED_CAM] = CAM_LED_ON;
-        }
-        break;
-
-    case ( CAM_LED_BY_TWL ):
-        switch ( vreg_twl[ REG_TWL_INT_ADRS_CAM ] ){  // switchのネストとか…
-          case( TWL_CAMLED_OFF ):
-                LED_duty_CAM = 0;
-                state_led_cam = 0;
-                break;
-
-          case( TWL_CAMLED_BLINK ):
-                if( state_led_cam == 0 )
-                {
-                    LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT];
-                    state_led_cam = 1;
-                }
-                else
-                {
-                    LED_duty_CAM = 0;
-                    state_led_cam = 0;
-                }
-                task_interval = 250;
-                break;
-
-          case( TWL_CAMLED_ON ):
-          case( TWL_CAMLED_DEF_ON ):
-          default:
-                LED_duty_CAM = vreg_ctr[VREG_C_LED_BRIGHT];
-                state_led_cam = 1;
-                break;
-        }
-    }
-    return;
-}
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.h
@ -1,90 +0,0 @@
-#ifndef __led__
-#define __led__
-
-
-// ====================================
-
-// LED_DUTY
-#define LED_duty_pow_L       TDR07
-#define LED_duty_pow_H       TDR06
-#define LED_duty_WiFi        TDR03
-#define LED_duty_NOTIFY      TDR05
-#define LED_duty_CAM         TDR02
-#define LED_duty_TUNE        TDR01
-// wifi2はPWMできません。
-
-
-#define LED_BRIGHT_MAX      0x00FF
-
-
-// ====================================
-#ifdef _MCU_BSR_                            // 電波送信パルス
-#define WIFI_txLatch PIF21
-#else
-#define WIFI_txLatch PIF7
-#endif
-
-
-
-// ====================================
-enum LED_ILUM_MODE
-{
-  LED_POW_ILM_AUTO = 0,
-  LED_POW_ILM_ON,
-  LED_POW_ILM_HOTARU,
-  LED_POW_ILM_OFF,
-  LED_POW_ILM_ONLY_RED,
-  LED_POW_ILM_ONLY_BLUE
-};
-
-
-enum LED_MODE_TUNE
-{
-  LED_TUNE_ILM_OFF = 0,
-  LED_TUNE_ILM_ON,
-  LED_TUNE_ILM_SVR
-};
-
-
-// VREG_C_WIFI_LED
-enum
-{
-  WIFI_LED_OFF = 0,
-  WIFI_LED_ON,
-  WIFI_LED_TXAUTO,
-  WIFI_LED_PTN0,
-  WIFI_LED_PTN1
-};
-
-
-// VREG_C_WIFI_NOTIFY
-enum
-{
-  NOTIFY_LED_OFF = 0,
-  NOTIFY_LED_ON,
-  NOTIFY_LED_PTN0,
-  NOTIFY_LED_PTN1,
-  NOTIFY_LED_PTN2
-};
-
-
-// VREG_C_CAM_LED
-enum
-{
-  CAM_LED_OFF = 0,
-  CAM_LED_BLINK,
-  CAM_LED_ON,
-  CAM_LED_BY_TWL,
-  CAM_LED_ON_PLUSE,
-  CAM_LED_OFF_PLUSE
-};
-
-
-
-// ====================================
-void LED_init(  );
-void LED_stop(  );
-
-
-
-#endif
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/led.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.c
@ -1,396 +0,0 @@
-/* ========================================================
-  MCU CTR BSR
-  2009/03/30
-  開発技術部 藤田
-
-  ブートローダー部
-  ホストの通信と、自己書き換え、ファームのチェックを行う。
-
- ======================================================== */
-#pragma SFR
-#pragma di
-#pragma ei
-#pragma nop
-#pragma stop
-#pragma halt
-#pragma opc
-
-
-#include "incs_loader.h"
-
-#include "fsl.h"
-#include "fsl_user.h"
-
-#include "i2c_ctr.h"
-#include "i2c_mcu.h"
-#include "pm.h"
-#include "rtc.h"
-
-#include "reboot.h"
-
-
-// ========================================================
-#if (FSL_DATA_BUFFER_SIZE>0)
-fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE];
-#endif
-
-
-
-#ifdef   FSL_INT_BACKUP
-static fsl_u08 fsl_MK0L_bak_u08;        /*    if (interrupt backup required)            */
-static fsl_u08 fsl_MK0H_bak_u08;        /*    {                                         */
-static fsl_u08 fsl_MK1L_bak_u08;        /*      reserve space for backup information    */
-static fsl_u08 fsl_MK1H_bak_u08;        /*      of interrupt mask flags                 */
-static fsl_u08 fsl_MK2L_bak_u08;        /*                                              */
-static fsl_u08 fsl_MK2H_bak_u08;        /*    }                                         */
-#endif
-
-
-
-// magic.c の記述と違わないように注意！
-#define MGC_LOAD   0x0FF6
-#define MGC_FOOT   0x4FF6
-
-
-
-// ========================================================
-void    FSL_Open( void );
-void    FSL_Close( void );
-void    hdwinit( void );
-void    power_save(  );
-static void hdwinit2(  );
-
-extern void main_loop(  );
-
-
-
-// ========================================================
-void main(  )
-{
-    while( 1 )
-    {
-        WDT_Restart(  );
-        if( RTCEN )
-        {
-            system_status.reboot = 1;
-        }
-        else if( ( RESF & 0x10 ) != 0)   // WDRF,WDTでリセット
-        {
-            system_status.reboot = 1;
-#ifdef _PMIC_TWL_
-            // 暴走してしまうので再起動させる
-            PM_reset_ast();
-            /// hdwinit2ないでリセット解除される。続きに続行してよい（頭痛が痛い的）
-#endif
-            vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_RESET;
-            // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
-            // ↑I2Cの初期化後に行う
-            hdwinit2(  );
-        }
-        else
-        {
-            u8      pwup_delay0 = 0;
-            u8      pwup_delay1 = 0;
-
-            do
-            {                   // 電池接続時、16ms待ってみる(チャタリング対策)
-                pwup_delay0 += 1;
-                do
-                {
-                    pwup_delay1 += 1;
-                }
-                while( pwup_delay1 != 0 );      // u16にするとコンパイラが怒るんだが…。
-            }
-            while( pwup_delay0 != 0 );
-
-	        hdwinit2(  );
-        }
-
-        // ファームの整合性チェック //
-        {
-            u8      i;
-            u8      comp = 0;
-
-            // ローダーと本体は同じバージョンか？
-            /// 次へのアップデートの途中で終わってないか？
-            for( i = 0; i < sizeof( __TIME__ ); i++ )      // sizeof( __TIME__ ) = 8 らし
-            {
-                comp += ( *( __far u8 * )( MGC_LOAD + i ) == *( u8 * )( MGC_FOOT + i ) ) ? 0 : 1;
-            }
-
-            if( comp != 0 )
-            {
-                // ファームリストアを試みる
-                firm_restore(  );
-                // 帰ってこない。リセットをかける。
-            }
-        }
-
-        // 通常運転
-        main_loop(  );
-    }
-}
-
-
-
-/* ========================================================
-  キーリターン割り込み
- ======================================================== */
-__interrupt void int_kr(  )
-{
-}
-
-
-
-/* ========================================================
-  ext dc
- ======================================================== */
-__interrupt void intp4(  )
-{
-}
-
-
-/* ========================================================
- shell close
- ======================================================== */
-__interrupt void intp5(  )
-{
-}
-
-
-
-// ========================================================
-void hdwinit( void )
-{                               // スタートアップルーチンが勝手に呼びます
-    DI(  );                     /* マスタ割り込み禁止 */
-
-    CMC = 0b00010110;          /* X1発振せず(入力ポート)、XT1使用、推奨の推奨で超低電力発振 */
-    CSC = 0b10000000;          /* X1発振なし、XT1発振あり、高速内蔵発振動作 */
-#ifdef _MCU_BSR_
-    OSMC = 0x01;               /* 隠しレジスタ */
-#endif
-#ifdef _OVERCLOCK_
-    CKC = 0b00001000;          /* CPU/周辺クロック=fMAIN、fMAIN=fMX、fCLK=fMX */
-#else
-    // CKC デフォルトでよい
-#endif
-
-  /*--- 低電圧検出回路の設定 ---*/
-    /* リセット解除時のデフォルトは、オプション・バイトにて指定される */
-    LVIS = 0b00000000;         /* VLVI = 4.22±0.1V */
-    LVIM = 0b00000000;         /* LVI動作禁止 */
-    /* 電源電圧(VDD)＜検出電圧(VLVI)時に割込発生 */
-    /* 電源電圧(VDD)≧検出電圧<VLVI)、または動作禁止時に低電圧検出 */
-}
-
-
-void hdwinit2(  )
-{
-    // ポート設定 /////////////////////////////////////////
-    if( system_status.reboot )  // リセットピンだけはすぐにセットする
-    {
-#ifdef _MODEL_TEG2_
-        P0  = 0b00000011;
-        P3  = 0b00000110;           // 簡易I2Cは出力ラッチを1にする
-        P14 = 0b00000001;
-#endif
-#ifdef _MODEL_WM0_
-        P0  = 0b00000011;
-        P3  = 0b00000110;           // 簡易I2Cは出力ラッチを1にする
-        P14 = 0b00000001;
-#endif
-#ifdef _MODEL_TS0_
-        P0  = 0b00000001;
-        P3  = 0b00000111;           // 簡易I2Cは出力ラッチを1にする
-        P14 = 0b00000000;
-#endif
-#ifdef _MODEL_CTR_
-        P0  = 0b00000001;
-        P3  = 0b00000111;           // 簡易I2Cは出力ラッチを1にする
-        P14 = 0b00000000;
-#endif
-    }
-    else
-    {
-        P0 = 0b00000000;
-        P3 = 0b00000110;           // 簡易I2Cは出力ラッチを1にする
-        P14 = 0b00000000;
-    }
-
-#ifdef _MCU_BSR_
-    PM0 = 0b11111111;          // BSRマイコンでは、reset1は監視のみになる。
-#else
-    PM0 = 0b00000000;          // 0で出力
-#endif
-    PM3 = 0b11110000;          // P31,32は簡易I2C
-    PM14 = 0b11111100;         // debugger[1] とりあえず出力
-
-    P1 = 0b00000000;
-    P2 = 0b00000000;
-    P4 = 0b00000000;
-    P5 = 0b00000000;
-    P6 = 0b00000000;
-    P7 = 0b01000000;
-    P12 = 0b00000000;
-
-#ifdef _MCU_BSR_
-    P20 = 0b00000000;
-#else
-    P8 = 0b00000000;
-#endif
-
-    P15 = 0b00000000;
-
-
-    PM1 = 0b00000000;
-    PM2 = 0b11101001;
-
-#ifdef _PMIC_CTR_
-    PM4 = 0b11110111;
-#else
-    PM4 = 0b11111011;
-#endif
-
-    PM5 = 0b11110011;
-    PM6 = 0b11111100;          // I2CのラインがL出力になってしまうが、システムがOFFなのでかまわない
-#ifdef _MODEL_CTR_
-    PM7 = 0b01011111;
-#else
-    PM7 = 0b00011111;
-#endif
-    PM12 = 0b11111111;         // 32kHzクロックのピン設定はどっちでもよい
-    PM15 = 0b11111111;
-
-#ifdef _MCU_BSR_
-#ifdef _MODEL_CTR_
-    PM20 = 0b11111101;
-#else
-    PM20 = 0b11111100;
-#endif
-#else
-    PM8 = 0b11111111;
-#endif
-
-    // プルアップ /////////////////////////////////////////
-    PU0 = 0b00000000;          // バッテリ認証後にそれぞれセット
-    PU1 = 0b00000000;
-    PU3 = 0b00000000;          // 外部でプルアップしないと具合が悪い。CPUがプルアップする
-    PU4 = 0b00000000;          // 外部でプルアップしてほしいtool0,1)
-    PU5 = 0b00000011;
-    PU7 = 0b00011001;
-    PU12 = 0b00000000;
-    PU14 = 0b00000000;
-
-#ifdef _MCU_BSR_
-#ifdef _MODEL_CTR_
-#ifdef _SW_HOME_ENABLE_
-    PU20 = 0b00010001;
-#else
-    PU20 = 0b00000001;
-#endif
-#else
-    PU20 = 0b00000000;
-#endif
-#endif
-
-    // ポート入力モード・レジスタ設定 /////////////////////
-    // [0:通常入力バッファ 1:TTL入力バッファ]
-    PIM3 = 0b00000000;
-    PIM7 = 0b00000000;
-
-    // ポート出力モード・レジスタ設定
-    // [0:通常出力モード 1:N-chオープン・ドレーン出力]
-    POM3 = 0b00000110;
-    POM7 = 0b00000000;
-
-  /*--- 割り込み設定 ---------*/
-    IF0 = 0x0000;               /* 割り込み要求フラグクリア */
-    IF1 = 0x0000;
-#ifdef _MCU_BSR_
-    IF2 = 0x0000;
-#else
-    IF2L = 0x00;
-#endif
-
-    MK0 = 0xFFFF;               /* 割り込み禁止 */
-    MK1 = 0xFFFF;
-
-#ifdef _MCU_BSR_
-    MK2 = 0xFFFF;
-#else
-    MK2L = 0xFF;
-#endif
-
-    PR00L = 0b11111111;        /* 割り込み優先順位、全て低位(LV3) */
-    PR10L = 0b11111111;
-    PR00H = 0b11111111;
-    PR10H = 0b11111111;
-    PR01L = 0b11111111;
-    PR11L = 0b11111110;
-    PR01H = 0b11111111;
-    PR11H = 0b11111111;
-    PR02L = 0b11111111;
-    PR12L = 0b11111111;
-
-  /*--- 外部割込の有効エッジ設定 ---*/
-#ifdef _MCU_BSR_
-    EGP0 = 0b00110001;
-    EGN0 = 0b01110001;
-    EGP2 = 0b00001010;
-    EGN2 = 0b00000000;
-#else
-    EGP0 = 0b10110001;
-    EGN0 = 0b01110001;
-#endif
-  /*--- キー割り込み設定 ---*/
-    KRM = 0b00000000;          /* 全キー割り込み信号を検出しない */
-
-  /*--- タイマ・アレイ・ユニットの動作停止 ---*/
-    TAU0EN = 0;                 /* タイマ・アレイ・ユニットへのクロック供給停止 */
-    TT0 = 0x00ff;               /* 全タイマ・チャネルの動作停止 */
-
-  /*--- RTCの動作停止 ---*/
-    //    RTCEN = 0;                      /* RTCへのクロック供給停止 */
-    //    RTCC0 = 0b00000000;     /* カウンタ動作停止 */
-    // 別途初期化関数
-
-#ifndef _MCU_BSR_
-  /*--- コンパレータ/プログラマブル・ゲイン・アップの動作停止 ---*/
-    OACMPEN = 0;                /* クロック供給停止 */
-    OAM = 0x00;                 /* プログラマブル・ゲイン・アップの動作停止 */
-    C0CTL = 0x00;               /* コンパレータ0動作停止 */
-    C1CTL = 0x00;               /* コンパレータ1動作停止 */
-#endif
-
-  /*--- クロック出力/ブザー出力停止 ---*/
-    CKS0 = 0b00000000;
-    CKS1 = 0b00000000;
-
-  /*--- ADCの動作停止 ---*/
-    ADCEN = 0;                  /* ADCへのクロック供給停止 */
-    ADM = 0b00000000;          /* 変換動作停止 */
-
-  /*--- シリアル・アレイ・ユニットの動作停止 ---*/
-    SAU0EN = 0;                 /* シリアル・アレイ・ユニット0へのクロック供給停止 */
-    SCR00 = 0x0087;             /* 各チャンネルの通信禁止 */
-    SCR01 = 0x0087;
-    SCR02 = 0x0087;
-    SCR03 = 0x0087;
-
-#ifdef _MCU_BSR_
-    // IICの動作停止
-    IICA0EN = 0;                /* IICA0(CTR)へのクロック供給停止 */
-    IICCTL00 = 0x00;            /* IICA1動作停止 */
-    IICA1EN = 0;                // IICA1(TWL)へのクロック供給停止
-    IICCTL01 = 0x00;            // IICA1動作停止
-
-#else
-  /*--- IICAの動作停止 ---*/
-    IICAEN = 0;                 /* IICAへのクロック供給停止 */
-    IICCTL0 = 0x00;             /* IICA動作停止 */
-#endif
-
-  /*--- DMAの動作停止 ---*/
-    DRC0 = 0b00000000;         /* DMAチャネル0の動作禁止 */
-    DRC1 = 0b00000000;         /* DMAチャネル1の動作禁止 */
-}
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.h
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.h
@ -1,4 +0,0 @@
-#include "jhl_defs.h"
-
-
-err firm_update(  );
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.prn
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/loader.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.c
@ -1,65 +0,0 @@
-/*****************************************************************************
-ビルド時刻を埋め込みます。
-ビルドの度に更新されるようにする必要があります。
-(touchしてね)
- ****************************************************************************/
-#include "config.h"
-
-// V0.5 (ニセ0.1改)
-#pragma section @@CNSTL MGC_LOAD AT 0x0FF6
-__far static const unsigned char MGC_LOAD[] = __TIME__;
-
-#pragma section @@CNST MGC_MIMI AT 0x2100
-static const unsigned char MGC_HEAD[] = __TIME__;
-
-#pragma section @@CNST MGC_TAIL AT 0x4FF6
-static const unsigned char MGC_TAIL[] = __TIME__;
-
-
-// 0Dまでこれを使用
-// #define SIG { 0x30, 0x38, 0x3A, 0x34, 0x35, 0x3A, 0x33, 0x39, 0x00, 0x00 }
-
-
-// あーあ。
-/*
-// V0.5 (ニセ0.1改)
-#define SIG { 0x30, 0x38, 0x3A, 0x34, 0x35, 0x3A, 0x33, 0x39, 0x00, 0x00 }
-*/
-
-/*
-メモ
-(未使用)
-V0.2の署名		31 34 3A 33 35 3A 33 35 00 00
-#define SIG { 0x31, 0x34, 0x3A, 0x33, 0x35, 0x3A, 0x33, 0x35, 0x00, 0x00 };
-
-ctr_wm0
-  31373A30353A32310000
-#define SIG { 0x31, 0x37, 0x3A, 0x30, 0x35, 0x3A, 0x32, 0x31, 0x00, 0x00 };
-
-ctr_wm0_2
-  31303A34393A35390000
-#define SIG { 0x31, 0x30, 0x3A, 0x34, 0x39, 0x3A, 0x35, 0x39, 0x00, 0x00 };
-
-bsr_V0.2_090828_WM2
-  31323A35393A32350000
-#define SIG { 0x31, 0x32, 0x3A, 0x35, 0x39, 0x3A, 0x32, 0x35, 0x00, 0x00 };
-*/
-
-
-/*
-// V0.1の署名（日付）	30 38 3A 34 35 3A 33 39 00 00
-#pragma section @@CNSTL MGC_LOAD AT 0x0FF6
-__far static const unsigned char MGC_LOAD[] =
-#define SIG { 0x30, 0x38, 0x3A, 0x34, 0x35, 0x3A, 0x33, 0x39, 0x00, 0x00 }
-
-
-// V0.4以降
-#pragma section @@CNSTL MGC_LOAD AT 0x0FF6
-__far static const unsigned char MGC_LOAD[] = __TIME__;
-
-#pragma section @@CNST MGC_MIMI AT 0x2100
-static const unsigned char MGC_HEAD[] = __TIME__;
-
-#pragma section @@CNST MGC_TAIL AT 0x47F6
-static const unsigned char MGC_TAIL[] = __TIME__;
-*/
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.prn
@ -1,163 +0,0 @@
-
-
-
-78K0R Assembler W1.31                                                                                    Date:13 Jun 2010 Page:   1
-
-
-
-Command:  -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\magic.asm
-Para-file:
-In-file:  inter_asm\magic.asm
-Obj-file: magic.rel
-Prn-file: magic.prn
-
-      Assemble list
-
- ALNO  STNO ADRS   OBJECT   M I  SOURCE STATEMENT
-
-    1     1                      ; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:47
-    2     2                      
-    3     3                      ; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-    4     4                      ;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-    5     5                      ;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no magic.c
-    6     6                      ; In-file   : magic.c
-    7     7                      ; Asm-file  : inter_asm\magic.asm
-    8     8                      ; Para-file : 
-    9     9                      
-   10    10                      $PROCESSOR(9F0104)
-   11    11                      $DEBUG
-   12    12                      $NODEBUGA
-   13    13                      $KANJICODE SJIS
-   14    14                      $TOL_INF        03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-   15    15                      
-   16    16                      $DGS    FIL_NAM, .file,         01BH,   0FFFEH, 03FH,   067H,   01H,    00H
-   17    17                      $DGS    AUX_FIL, magic.c
-   18    18                      $DGS    MOD_NAM, magic,         00H,    0FFFEH, 00H,    077H,   00H,    00H
-   19    19                      $DGS    SEC_NAM, @@BITS,        U,      U,      00H,    078H,   00H,    00H
-   20    20                      $DGS    SEC_NAM, @@CNST,        U,      U,      00H,    078H,   00H,    00H
-   21    21                      $DGS    SEC_NAM, MGC_MIMI,      U,      U,      00H,    078H,   00H,    00H
-   22    22                      $DGS    SEC_NAM, MGC_TAIL,      U,      U,      00H,    078H,   00H,    00H
-   23    23                      $DGS    SEC_NAM, @@R_INIT,      U,      U,      00H,    078H,   00H,    00H
-   24    24                      $DGS    SEC_NAM, @@INIT,        U,      U,      00H,    078H,   00H,    00H
-   25    25                      $DGS    SEC_NAM, @@DATA,        U,      U,      00H,    078H,   00H,    00H
-   26    26                      $DGS    SEC_NAM, @@R_INIS,      U,      U,      00H,    078H,   00H,    00H
-   27    27                      $DGS    SEC_NAM, @@INIS,        U,      U,      00H,    078H,   00H,    00H
-   28    28                      $DGS    SEC_NAM, @@DATS,        U,      U,      00H,    078H,   00H,    00H
-   29    29                      $DGS    SEC_NAM, MGC_LOAD,      U,      U,      00H,    078H,   00H,    00H
-   30    30                      $DGS    SEC_NAM, @@RLINIT,      U,      U,      00H,    078H,   00H,    00H
-   31    31                      $DGS    SEC_NAM, @@INITL,       U,      U,      00H,    078H,   00H,    00H
-   32    32                      $DGS    SEC_NAM, @@DATAL,       U,      U,      00H,    078H,   00H,    00H
-   33    33                      $DGS    SEC_NAM, @@CALT,        U,      U,      00H,    078H,   00H,    00H
-   34    34                      $DGS    SEC_NAM, @@CODE,        U,      U,      00H,    078H,   00H,    00H
-   35    35                      $DGS    SEC_NAM, @@CODEL,       U,      U,      00H,    078H,   00H,    00H
-   36    36                      $DGS    SEC_NAM, @@BASE,        U,      U,      00H,    078H,   00H,    00H
-   37    37                      $DGS    STA_SYM, _MGC_LOAD,     U,      U,      0D00CH, 03H,    01H,    03H
-   38    38                      $DGS    AUX_STR, 00H,           00H,    09H,    09H,    00H,    00H,    00H,    00H
-   39    39                      $DGS    STA_SYM, _MGC_HEAD,     U,      U,      0500CH, 03H,    01H,    03H
-   40    40                      $DGS    AUX_STR, 00H,           00H,    09H,    09H,    00H,    00H,    00H,    00H
-   41    41                      $DGS    STA_SYM, _MGC_TAIL,     U,      U,      0500CH, 03H,    01H,    03H
-   42    42                      $DGS    AUX_STR, 00H,           00H,    09H,    09H,    00H,    00H,    00H,    00H
-   43    43                      
-   44    44                      
-   45    45 -----                @@BITS  BSEG
-   46    46                      
-   47    47 -----                MGC_MIMI        CSEG    AT 2100H
-   48    48 02100  31393A33      _MGC_HEAD:      DB      '19:31:47'
-            02104  313A3437
-   49    49 02108  00                    DB      00H
-   50    50 02109  00                    DB      (1)
-   51    51                      
-   52    52 -----                MGC_TAIL        CSEG    AT 4FF6H
-   53    53 04FF6  31393A33      _MGC_TAIL:      DB      '19:31:47'
-            04FFA  313A3437
-   54    54 04FFE  00                    DB      00H
-   55    55 04FFF  00                    DB      (1)
-   56    56                      
-   57    57 -----                @@R_INIT        CSEG    UNIT64KP
-   58    58                      
-   59    59 -----                @@INIT  DSEG    BASEP
-   60    60                      
-   61    61 -----                @@DATA  DSEG    BASEP
-   62    62                      
-   63    63 -----                @@R_INIS        CSEG    UNIT64KP
-   64    64                      
-   65    65 -----                @@INIS  DSEG    SADDRP
-   66    66                      
-   67    67 -----                @@DATS  DSEG    SADDRP
-   68    68                      
-   69    69 -----                MGC_LOAD        CSEG    AT 0FF6H
-   70    70 00FF6  31393A33      _MGC_LOAD:      DB      '19:31:47'
-            00FFA  313A3437
-   71    71 00FFE  00                    DB      00H
-   72    72 00FFF  00                    DB      (1)
-   73    73                      
-   74    74 -----                @@RLINIT        CSEG    UNIT64KP
-   75    75                      
-   76    76 -----                @@INITL DSEG    UNIT64KP
-   77    77                      
-   78    78 -----                @@DATAL DSEG    UNIT64KP
-   79    79                      
-   80    80 -----                @@CALT  CSEG    CALLT0
-   81    81                      
-   82    82                      ; line     1 : /***************************************************************
-   83    83                      ;              **************
-   84    84                      ; line     2 : ビルド時刻を埋め込みます。
-   85    85                      ; line     3 : ビルドの度に更新されるようにする必要があります。
-   86    86                      ; line     4 : (touchしてね)
-   87    87                      ; line     5 :  ***************************************************************
-   88    88                      ;              *************/
-   89    89                      ; line     6 : #include "config.h"
-   90    90                      ; line     7 : 
-   91    91                      ; line     8 : // V0.5 (ニセ0.1改)
-   92    92                      ; line     9 : #pragma section @@CNSTL MGC_LOAD AT 0x0FF6
-   93    93                      ; line    10 : __far static const unsigned char MGC_LOAD[] = __TIME__;
-   94    94                      ; line    11 : 
-   95    95                      ; line    12 : #pragma section @@CNST MGC_MIMI AT 0x2100
-   96    96                      ; line    13 : static const unsigned char MGC_HEAD[] = __TIME__;
-   97    97                      ; line    14 : 
-   98    98                      ; line    15 : #pragma section @@CNST MGC_TAIL AT 0x4FF6
-   99    99                      ; line    16 : static const unsigned char MGC_TAIL[] = __TIME__;
-  100   100                      
-  101   101 -----                @@CODE  CSEG    BASE
-  102   102                      
-  103   103 -----                @@CODEL CSEG
-  104   104                      
-  105   105 -----                @@BASE  CSEG    BASE
-  106   106                      
-  107   107 -----                @@CNST  CSEG    MIRRORP
-  108   108                      
-  109   109                              END
-  110   110                      
-  111   111                      
-  112   112                      ; *** Code Information ***
-  113   113                      
-  114   114                      ; Target chip : uPD79F0104
-  115   115                      ; Device file : E1.00b
-
-Segment informations:
-
-ADRS  LEN      NAME
-
-00000 00000H.0 @@BITS
-02100 0000AH   MGC_MIMI
-04FF6 0000AH   MGC_TAIL
-00000 00000H   @@R_INIT
-00000 00000H   @@INIT
-00000 00000H   @@DATA
-00000 00000H   @@R_INIS
-00000 00000H   @@INIS
-00000 00000H   @@DATS
-00FF6 0000AH   MGC_LOAD
-00000 00000H   @@RLINIT
-00000 00000H   @@INITL
-00000 00000H   @@DATAL
-00000 00000H   @@CALT
-00000 00000H   @@CODE
-00000 00000H   @@CODEL
-00000 00000H   @@BASE
-00000 00000H   @@CNST
-
- Target chip : uPD79F0104
- Device file : E1.00b
-Assembly complete,     0 error(s) and     0 warning(s) found. (    0)
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.rel
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/magic.rel
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/main.c
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/main.c
@ -1,103 +0,0 @@
-/* ========================================================
-  MCU CTR BSR
-                                       2008,2009 nintendo
-                                       開発技術部　藤田
- ======================================================== */
-
-
-// ========================================================
-#include "incs_loader.h"
-
-#include "WDT.h"
-#include "rtc.h"
-#include "pm.h"
-#include "accero.h"
-#include "led.h"
-#include "adc.h"
-
-
-// ========================================================
-static void read_dipsw(  );
-
-
-// ========================================================
-system_status_ system_status;
-bit update;
-
-
-u16 pool[256];                   // アップデート時のワークエリア 兼 歩数計データ
-/* ========================================================
- 本当のエントリ関数は loader.c にあります
- ======================================================== */
-void main_loop( void )
-{
-
-    // 電池投入時、ファームアップデート後のみ
-    RTC_init(  );               // 内部でリブートか判定しています
-
-    renge_init(  );
-
-    iic_mcu_start(  );
-    EI(  );
-
-    PM_init();
-
-    if( system_status.reboot )
-    {
-#ifdef _PMIC_TWL_
-        if( RESET1_n )
-#else
-        if( PM_chk_LDSW() != 0 )
-#endif
-        {
-            system_status.pwr_state = ON_TRIG;
-        }
-    }
-    else
-    {
-        // リブート時は実行されない
-        system_status.pwr_state = OFF_TRIG;
-    }
-
-#ifdef _PARRADIUM_
-        system_status.pwr_state = OFF;
-#endif
-    vreg_ctr_init(  );
-    vreg_twl_init(  );
-
-    read_dipsw(  );    // 特定スイッチで何かするか？
-
-    clear_hosu_hist(); // 履歴クリア
-
-    renge_task_interval_run_force = 1;
-
-    RTCIMK = 0;                 /* 割り込み(アラーム&インターバル)許可 */
-
-    // メインループ //
-    while( 1 )
-    {                           // システムtick、または割り込みで廻ります。
-        WDT_Restart(  );
-        renge_task_interval_run(  );    // 内部で、システムtickまたは強制起動します
-        while( renge_task_interval_run_force != 0 )
-        {
-            renge_task_interval_run(  );
-        }
-        WDT_Restart(  );
-        while( renge_task_immed_run(  ) != ERR_SUCCESS );       // ここのループが廻る度に実行されます
-        HALT(  );
-    }
-}
-
-
-/* ========================================================
- ======================================================== */
-static void read_dipsw(  )
-{
-    // ソフトディップスイッチ読み込み
-//  PU4 |= 0x03; // dip sw 0,1
-    system_status.dipsw0 = ( DIPSW_0 == 0 ) ? 0 : 1;
-    system_status.dipsw1 = ( DIPSW_1 == 0 ) ? 0 : 1;
-//  PU4 &= ~0x03;
-}
-
-
--- a/branches/2.2A_SDK5(4thNUP)/0.10(X3)/main.prn
+++ b/branches/2.2A_SDK5(4thNUP)/0.10(X3)/main.prn
@ -1,568 +0,0 @@
-
-
-
-78K0R Assembler W1.31                                                                                    Date:13 Jun 2010 Page:   1
-
-
-
-Command:  -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\main.asm
-Para-file:
-In-file:  inter_asm\main.asm
-Obj-file: main.rel
-Prn-file: main.prn
-
-      Assemble list
-
- ALNO  STNO ADRS   OBJECT   M I  SOURCE STATEMENT
-
-    1     1                      ; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:23
-    2     2                      
-    3     3                      ; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
-    4     4                      ;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
-    5     5                      ;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no main.c
-    6     6                      ; In-file   : main.c
-    7     7                      ; Asm-file  : inter_asm\main.asm
-    8     8                      ; Para-file : 
-    9     9                      
-   10    10                      $PROCESSOR(9F0104)
-   11    11                      $DEBUG
-   12    12                      $NODEBUGA
-   13    13                      $KANJICODE SJIS
-   14    14                      $TOL_INF        03FH, 0210H, 00H, 00H, 00H, 00H, 00H
-   15    15                      
-   16    16                      $DGS    FIL_NAM, .file,         063H,   0FFFEH, 03FH,   067H,   01H,    00H
-   17    17                      $DGS    AUX_FIL, main.c
-   18    18                      $DGS    MOD_NAM, main,          00H,    0FFFEH, 00H,    077H,   00H,    00H
-   19    19                      $DGS    SEC_NAM, @@BITS,        U,      U,      00H,    078H,   00H,    00H
-   20    20                      $DGS    SEC_NAM, @@CNST,        U,      U,      00H,    078H,   00H,    00H
-   21    21                      $DGS    SEC_NAM, @@R_INIT,      U,      U,      00H,    078H,   00H,    00H
-   22    22                      $DGS    SEC_NAM, @@INIT,        U,      U,      00H,    078H,   00H,    00H
-   23    23                      $DGS    SEC_NAM, @@DATA,        U,      U,      00H,    078H,   00H,    00H
-   24    24                      $DGS    SEC_NAM, @@R_INIS,      U,      U,      00H,    078H,   00H,    00H
-   25    25                      $DGS    SEC_NAM, @@INIS,        U,      U,      00H,    078H,   00H,    00H
-   26    26                      $DGS    SEC_NAM, @@DATS,        U,      U,      00H,    078H,   00H,    00H
-   27    27                      $DGS    SEC_NAM, LDR_CNSL,      U,      U,      00H,    078H,   00H,    00H
-   28    28                      $DGS    SEC_NAM, @@RLINIT,      U,      U,      00H,    078H,   00H,    00H
-   29    29                      $DGS    SEC_NAM, @@INITL,       U,      U,      00H,    078H,   00H,    00H
-   30    30                      $DGS    SEC_NAM, @@DATAL,       U,      U,      00H,    078H,   00H,    00H
-   31    31                      $DGS    SEC_NAM, @@CALT,        U,      U,      00H,    078H,   00H,    00H
-   32    32                      $DGS    SEC_NAM, LDR_CODE,      U,      U,      00H,    078H,   00H,    00H
-   33    33                      $DGS    SEC_NAM, LDR_CODL,      U,      U,      00H,    078H,   00H,    00H
-   34    34                      $DGS    SEC_NAM, @@BASE,        U,      U,      00H,    078H,   00H,    00H
-   35    35                      $DGS    ENM_TAG, _pwr_state_,   00H,    0FFFEH, 0AH,    0FH,    01H,    00H
-   36    36                      $DGS    AUX_TAG, 01H,           01EH
-   37    37                      $DGS    MEB_ENM, _OFF_TRIG,     00H,    0FFFFH, 04H,    010H,   00H,    00H
-   38    38                      $DGS    MEB_ENM, _OFF,          01H,    0FFFFH, 04H,    010H,   00H,    00H
-   39    39                      $DGS    MEB_ENM, _ON_TRIG,      02H,    0FFFFH, 04H,    010H,   00H,    00H
-   40    40                      $DGS    MEB_ENM, _ON,           03H,    0FFFFH, 04H,    010H,   00H,    00H
-   41    41                      $DGS    MEB_ENM, _SLEEP_TRIG,   04H,    0FFFFH, 04H,    010H,   00H,    00H
-   42    42                      $DGS    MEB_ENM, _SLEEP,        05H,    0FFFFH, 04H,    010H,   00H,    00H
-   43    43                      $DGS    MEB_ENM, _BT_CHARGE,    06H,    0FFFFH, 04H,    010H,   00H,    00H
-   44    44                      $DGS    END_STR, .eos,          01H,    0FFFFH, 00H,    066H,   01H,    00H
-   45    45                      $DGS    AUX_EOS, 013H,          01H
-   46    46                      $DGS    ENM_TAG, _poweron_reason_,      00H,    0FFFEH, 0AH,    0FH,    01H,    00H
-   47    47                      $DGS    AUX_TAG, 01H,           025H
-   48    48                      $DGS    MEB_ENM, _NONE,         00H,    0FFFFH, 04H,    010H,   00H,    00H
-   49    49                      $DGS    MEB_ENM, _PWSW,         01H,    0FFFFH, 04H,    010H,   00H,    00H
-   50    50                      $DGS    MEB_ENM, _RTC_ALARM,    02H,    0FFFFH, 04H,    010H,   00H,    00H
-   51    51                      $DGS    END_STR, .eos,          01H,    0FFFFH, 00H,    066H,   01H,    00H
-   52    52                      $DGS    AUX_EOS, 01EH,          01H
-   53    53                      $DGS    ENM_TAG, _model_,       00H,    0FFFEH, 0AH,    0FH,    01H,    00H
-   54    54                      $DGS    AUX_TAG, 01H,           02FH
-   55    55                      $DGS    MEB_ENM, _MODEL_JIKKI,  00H,    0FFFFH, 04H,    010H,   00H,    00H
-   56    56                      $DGS    MEB_ENM, _MODEL_TS_BOARD,       01H,    0FFFFH, 04H,    010H,   00H,    00H
-   57    57                      $DGS    MEB_ENM, _MODEL_SHIROBAKO,      02H,    0FFFFH, 04H,    010H,   00H,    00H
-   58    58                      $DGS    MEB_ENM, _MODEL_RESERVED1,      03H,    0FFFFH, 04H,    010H,   00H,    00H
-   59    59                      $DGS    MEB_ENM, _MODEL_RESERVED2,      04H,    0FFFFH, 04H,    010H,   00H,    00H
-   60    60                      $DGS    MEB_ENM, _MODEL_RESERVED3,      05H,    0FFFFH, 04H,    010H,   00H,    00H
-   61    61                      $DGS    END_STR, .eos,          01H,    0FFFFH, 00H,    066H,   01H,    00H
-   62    62                      $DGS    AUX_EOS, 025H,          01H
-   63    63                      $DGS    STR_STR, .0fake,        00H,    0FFFEH, 08H,    0AH,    01H,    00H
-   64    64                      $DGS    AUX_TAG, 04H,           041H
-   65    65                      $DGS    MEB_STR, _pwr_state,    00H,    0FFFFH, 0AH,    08H,    01H,    00H
-   66    66                      $DGS    AUX_STR, 013H,          00H,    01H,    00H,    00H,    00H,    00H,    00H
-   67    67                      $DGS    MEB_STR, _poweron_reason,       01H,    0FFFFH, 0AH,    08H,    01H,    00H
-   68    68                      $DGS    AUX_STR, 01EH,          00H,    01H,    00H,    00H,    00H,    00H,    00H
-   69    69                      $DGS    BIT_FLD, _dipsw0,       010H,   0FFFFH, 0CH,    012H,   01H,    00H
-   70    70                      $DGS    AUX_BIT, 00H,           01H
-   71    71                      $DGS    BIT_FLD, _dipsw1,       011H,   0FFFFH, 0CH,    012H,   01H,    00H
-   72    72                      $DGS    AUX_BIT, 00H,           01H
-   73    73                      $DGS    BIT_FLD, _dipsw2,       012H,   0FFFFH, 0CH,    012H,   01H,    00H
-   74    74                      $DGS    AUX_BIT, 00H,           01H
-   75    75                      $DGS    BIT_FLD, _reboot,       013H,   0FFFFH, 0CH,    012H,   01H,    00H
-   76    76                      $DGS    AUX_BIT, 00H,           01H
-   77    77                      $DGS    MEB_STR, _model,        03H,    0FFFFH, 0AH,    08H,    01H,    00H
-   78    78                      $DGS    AUX_STR, 025H,          00H,    01H,    00H,    00H,    00H,    00H,    00H
-   79    79                      $DGS    END_STR, .eos,          04H,    0FFFFH, 00H,    066H,   01H,    00H
-   80    80                      $DGS    AUX_EOS, 02FH,          04H
-   81    81                      $DGS    STA_SYM, _lpf_coeff,    U,      U,      05002H, 03H,    01H,    03H
-   82    82                      $DGS    AUX_STR, 00H,           00H,    02FH,   02FH,   00H,    00H,    00H,    00H
-   83    83                      $DGS    GLV_SYM, _main_loop,    U,      U,      01H,    026H,   01H,    02H
-   84    84                      $DGS    AUX_FUN, 00H,           U,      U,      05DH,   00H,    00H
-   85    85                      $DGS    BEG_FUN, ??bf_main_loop,        U,      U,      00H,    065H,   01H,    00H
-   86    86                      $DGS    AUX_BEG, 021H,          00H,    047H
-   87    87                      $DGS    BEG_BLK, ??bb00_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   88    88                      $DGS    AUX_BEG, 0EH,           00H,    049H
-   89    89                      $DGS    BEG_BLK, ??bb01_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   90    90                      $DGS    AUX_BEG, 014H,          00H,    04FH
-   91    91                      $DGS    END_BLK, ??eb01_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   92    92                      $DGS    AUX_END, 016H
-   93    93                      $DGS    END_BLK, ??eb00_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   94    94                      $DGS    AUX_END, 017H
-   95    95                      $DGS    BEG_BLK, ??bb02_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   96    96                      $DGS    AUX_BEG, 019H,          00H,    053H
-   97    97                      $DGS    END_BLK, ??eb02_main_loop,      U,      U,      00H,    064H,   01H,    00H
-   98    98                      $DGS    AUX_END, 01CH
-   99    99                      $DGS    BEG_BLK, ??bb03_main_loop,      U,      U,      00H,    064H,   01H,    00H
-  100   100                      $DGS    AUX_BEG, 02EH,          00H,    055H
-  101   101                      $DGS    BEG_BLK, ??bb04_main_loop,      U,      U,      00H,    064H,   01H,    00H
-  102   102                      $DGS    AUX_BEG, 032H,          00H,    00H
-  103   103                      $DGS    END_BLK, ??eb04_main_loop,      U,      U,      00H,    064H,   01H,    00H
-  104   104                      $DGS    AUX_END, 034H
-  105   105                      $DGS    END_BLK, ??eb03_main_loop,      U,      U,      00H,    064H,   01H,    00H
-  106   106                      $DGS    AUX_END, 038H
-  107   107                      $DGS    END_FUN, ??ef_main_loop,        U,      U,      00H,    065H,   01H,    00H
-  108   108                      $DGS    AUX_END, 039H
-  109   109                      $DGS    STA_SYM, _read_dipsw,   U,      U,      01H,    03H,    01H,    02H
-  110   110                      $DGS    AUX_FUN, 00H,           U,      U,      063H,   00H,    00H
-  111   111                      $DGS    BEG_FUN, ??bf_read_dipsw,       U,      U,      00H,    065H,   01H,    00H
-  112   112                      $DGS    AUX_BEG, 05FH,          00H,    063H
-  113   113                      $DGS    END_FUN, ??ef_read_dipsw,       U,      U,      00H,    065H,   01H,    00H
-  114   114                      $DGS    AUX_END, 07H
-  115   115                      $DGS    GLV_SYM, _system_status,        U,      U,      08H,    026H,   01H,    00H
-  116   116                      $DGS    AUX_STR, 02FH,          00H,    04H,    00H,    00H,    00H,    00H,    00H
-  117   117                      $DGS    GLV_SYM, _update,       U,      U,      034CH,  027H,   00H,    00H
-  118   118                      $DGS    GLV_SYM, _pool,         U,      U,      0DH,    026H,   01H,    03H
-  119   119                      $DGS    AUX_STR, 00H,           00H,    0200H,  0100H,  00H,    00H,    00H,    00H
-  120   120                      $DGS    GLV_SYM, _RTC_init,     U,      U,      01H,    02H,    01H,    02H
-  121   121                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  122   122                      $DGS    GLV_SYM, _renge_init,   U,      U,      01H,    02H,    01H,    02H
-  123   123                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  124   124                      $DGS    GLV_SYM, _iic_mcu_start,        U,      U,      01H,    02H,    01H,    02H
-  125   125                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  126   126                      $DGS    GLV_SYM, _PM_init,      U,      U,      01H,    02H,    01H,    02H
-  127   127                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  128   128                      $DGS    GLV_SYM, _iic_mcu_read_a_byte,  U,      U,      0CH,    02H,    01H,    02H
-  129   129                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  130   130                      $DGS    GLV_SYM, _vreg_ctr_init,        U,      U,      01H,    02H,    01H,    02H
-  131   131                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  132   132                      $DGS    GLV_SYM, _vreg_twl_init,        U,      U,      01H,    02H,    01H,    02H
-  133   133                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  134   134                      $DGS    GLV_SYM, _clear_hosu_hist,      U,      U,      01H,    02H,    01H,    02H
-  135   135                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  136   136                      $DGS    GLV_SYM, _renge_task_interval_run_force,        U,      U,      034CH,  02H,    00H,    00H
-  137   137                      $DGS    GLV_SYM, _WDT_Restart,  U,      U,      01H,    02H,    01H,    02H
-  138   138                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  139   139                      $DGS    GLV_SYM, _renge_task_interval_run,      U,      U,      0CH,    02H,    01H,    02H
-  140   140                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  141   141                      $DGS    GLV_SYM, _renge_task_immed_run, U,      U,      0CH,    02H,    01H,    02H
-  142   142                      $DGS    AUX_FUN, 00H,           U,      U,      00H,    00H,    00H
-  143   143                      
-  144   144                              EXTRN   _RTC_init
-  145   145                              EXTRN   _renge_init
-  146   146                              EXTRN   _iic_mcu_start
-  147   147                              EXTRN   _PM_init
-  148   148                              EXTRN   _iic_mcu_read_a_byte
-  149   149                              EXTRN   _vreg_ctr_init
-  150   150                              EXTRN   _vreg_twl_init
-  151   151                              EXTRN   _clear_hosu_hist
-  152   152                              EXTRN   _WDT_Restart
-  153   153                              EXTRN   _renge_task_interval_run
-  154   154                              EXTRN   _renge_task_immed_run
-  155   155                              EXTBIT  _renge_task_interval_run_force
-  156   156                              PUBLIC  _system_status
-  157   157                              PUBLIC  _update
-  158   158                              PUBLIC  _pool
-  159   159                              PUBLIC  _main_loop
-  160   160                      
-  161   161 -----                @@BITS  BSEG
-  162   162 00000.0              _update DBIT
-  163   163                      
-  164   164 -----                @@CNST  CSEG    MIRRORP
-  165   165 00000  01            _lpf_coeff:     DB      01H     ; 1
-  166   166 00001  02                    DB      02H     ; 2
-  167   167 00002  02                    DB      02H     ; 2
-  168   168 00003  03                    DB      03H     ; 3
-  169   169 00004  03                    DB      03H     ; 3
-  170   170 00005  02                    DB      02H     ; 2
-  171   171 00006  00                    DB      00H     ; 0
-  172   172 00007  FE                    DB      0FEH    ; 254
-  173   173 00008  FB                    DB      0FBH    ; 251
-  174   174 00009  F7                    DB      0F7H    ; 247
-  175   175 0000A  F3                    DB      0F3H    ; 243
-  176   176 0000B  F0                    DB      0F0H    ; 240
-  177   177 0000C  F0                    DB      0F0H    ; 240
-  178   178 0000D  F3                    DB      0F3H    ; 243
-  179   179 0000E  FA                    DB      0FAH    ; 250
-  180   180 0000F  04                    DB      04H     ; 4
-  181   181 00010  12                    DB      012H    ; 18
-  182   182 00011  25                    DB      025H    ; 37
-  183   183 00012  38                    DB      038H    ; 56
-  184   184 00013  4D                    DB      04DH    ; 77
-  185   185 00014  5F                    DB      05FH    ; 95
-  186   186 00015  6E                    DB      06EH    ; 110
-  187   187 00016  77                    DB      077H    ; 119
-  188   188 00017  7A                    DB      07AH    ; 122
-  189   189 00018  77                    DB      077H    ; 119
-  190   190 00019  6E                    DB      06EH    ; 110
-  191   191 0001A  5F                    DB      05FH    ; 95
-  192   192 0001B  4D                    DB      04DH    ; 77
-  193   193 0001C  38                    DB      038H    ; 56
-  194   194 0001D  25                    DB      025H    ; 37
-  195   195 0001E  12                    DB      012H    ; 18
-  196   196 0001F  04                    DB      04H     ; 4
-  197   197 00020  FA                    DB      0FAH    ; 250
-  198   198 00021  F3                    DB      0F3H    ; 243
-  199   199 00022  F0                    DB      0F0H    ; 240
-  200   200 00023  F0                    DB      0F0H    ; 240
-  201   201 00024  F3                    DB      0F3H    ; 243
-  202   202 00025  F7                    DB      0F7H    ; 247
-  203   203 00026  FB                    DB      0FBH    ; 251
-  204   204 00027  FE                    DB      0FEH    ; 254
-  205   205 00028  00                    DB      00H     ; 0
-  206   206 00029  02                    DB      02H     ; 2
-  207   207 0002A  03                    DB      03H     ; 3
-  208   208 0002B  03                    DB      03H     ; 3
-  209   209 0002C  02                    DB      02H     ; 2
-  210   210 0002D  02                    DB      02H     ; 2
-  211   211 0002E  01                    DB      01H     ; 1
-  212   212 0002F  00                    DB      (1)
-  213   213                      
-  214   214 -----                @@R_INIT        CSEG    UNIT64KP
-  215   215                      
-  216   216 -----                @@INIT  DSEG    BASEP
-  217   217                      
-  218   218 -----                @@DATA  DSEG    BASEP
-  219   219 00000                _system_status: DS      (4)
-  220   220 00004                _pool:  DS      (512)
-  221   221                      
-  222   222 -----                @@R_INIS        CSEG    UNIT64KP
-  223   223                      
-  224   224 -----                @@INIS  DSEG    SADDRP
-  225   225                      
-  226   226 -----                @@DATS  DSEG    SADDRP
-  227   227                      
-  228   228 -----                LDR_CNSL        CSEG    PAGE64KP
-  229   229                      
-  230   230 -----                @@RLINIT        CSEG    UNIT64KP
-  231   231                      
-  232   232 -----                @@INITL DSEG    UNIT64KP
-  233   233                      
-  234   234 -----                @@DATAL DSEG    UNIT64KP
-  235   235                      
-  236   236 -----                @@CALT  CSEG    CALLT0
-  237   237                      
-  238   238                      ; line     1 : /* ========================================================
-  239   239                      ; line     2 :   MCU CTR BSR
-  240   240                      ; line     3 :                                        2008,2009 nintendo
-  241   241                      ; line     4 :                                        開発技術部　藤田
-  242   242                      ; line     5 :  ======================================================== */
-  243   243                      ; line     6 : 
-  244   244                      ; line     7 : 
-  245   245                      ; line     8 : // ========================================================
-  246   246                      ; line     9 : #include "incs_loader.h"
-  247   247                      ; line    10 : 
-  248   248                      ; line    11 : #include "WDT.h"
-  249   249                      ; line    12 : #include "rtc.h"
-  250   250                      ; line    13 : #include "pm.h"
-  251   251                      ; line    14 : #include "accero.h"
-  252   252                      ; line    15 : #include "led.h"
-  253   253                      ; line    16 : #include "adc.h"
-  254   254                      ; line    17 : 
-  255   255                      ; line    18 : 
-  256   256                      ; line    19 : // ========================================================
-  257   257                      ; line    20 : static void read_dipsw(  );
-  258   258                      ; line    21 : 
-  259   259                      ; line    22 : 
-  260   260                      ; line    23 : // ========================================================
-  261   261                      ; line    24 : system_status_ system_status;
-  262   262                      ; line    25 : bit update;
-  263   263                      ; line    26 : 
-  264   264                      ; line    27 : 
-  265   265                      ; line    28 : u16 pool[256];                   // アップデート時のワークエリア
-  266   266                      ;               兼 歩数計データ
-  267   267                      ; line    29 : /* ========================================================
-  268   268                      ; line    30 :  本当のエントリ関数は loader.c にあります
-  269   269                      ; line    31 :  ======================================================== */
-  270   270                      ; line    32 : void main_loop( void )
-  271   271                      ; line    33 : {
-  272   272                      
-  273   273 -----                LDR_CODE        CSEG    BASE
-  274   274 00000                _main_loop:
-  275   275                      $DGL    1,67
-  276   276 00000                ??bf_main_loop:
-  277   277                      ; line    34 : 
-  278   278                      ; line    35 :     // 電池投入時、ファームアップデート後のみ
-  279   279                      ; line    36 :     RTC_init(  );               // 内部でリブートか判定しています
-  280   280                      $DGL    0,4
-  281   281 00000 RFD0000                call    !_RTC_init                                      ;[INF] 3, 3
-  282   282                      ; line    37 : 
-  283   283                      ; line    38 :     renge_init(  );
-  284   284                      $DGL    0,6
-  285   285 00003 RFD0000                call    !_renge_init                                    ;[INF] 3, 3
-  286   286                      ; line    39 : 
-  287   287                      ; line    40 :     iic_mcu_start(  );
-  288   288                      $DGL    0,8
-  289   289 00006 RFD0000                call    !_iic_mcu_start                                 ;[INF] 3, 3
-  290   290                      ; line    41 :     EI(  );
-  291   291                      $DGL    0,9
-  292   292 00009  717AFA                ei                                                      ;[INF] 3, 4
-  293   293                      ; line    42 : 
-  294   294                      ; line    43 :     PM_init();
-  295   295                      $DGL    0,11
-  296   296 0000C RFD0000                call    !_PM_init                                       ;[INF] 3, 3
-  297   297                      ; line    44 : 
-  298   298                      ; line    45 :     if( system_status.reboot )
-  299   299                      $DGL    0,13
-  300   300 0000F R8F0200                mov     a,!_system_status+2                             ;[INF] 3, 1
-  301   301 00012  313516                bf      a.3,$?L0003                                     ;[INF] 3, 5
-  302   302                      ; line    46 :     {
-  303   303 00015                ??bb00_main_loop:
-  304   304                      ; line    47 : #ifdef _PMIC_TWL_
-  305   305                      ; line    48 :         if( RESET1_n )
-  306   306                      ; line    49 : #else
-  307   307                      ; line    50 :         if( PM_chk_LDSW() != 0 )
-  308   308                      $DGL    0,18
-  309   309 00015  300300                movw    ax,#03H ; 3                                     ;[INF] 3, 1
-  310   310 00018  C1                    push    ax                                              ;[INF] 1, 1
-  311   311 00019  5084                  mov     x,#084H ; 132                                   ;[INF] 2, 1
-  312   312 0001B RFD0000                call    !_iic_mcu_read_a_byte                           ;[INF] 3, 3
-  313   313 0001E  C0                    pop     ax                                              ;[INF] 1, 1
-  314   314 0001F  62                    mov     a,c                                             ;[INF] 1, 1
-  315   315 00020  5C01                  and     a,#01H  ; 1                                     ;[INF] 2, 1
-  316   316 00022  D1                    cmp0    a                                               ;[INF] 1, 1
-  317   317 00023  DD09                  bz      $?L0004                                         ;[INF] 2, 4
-  318   318                      ; line    51 : #endif
-  319   319                      ; line    52 :         {
-  320   320 00025                ??bb01_main_loop:
-  321   321                      ; line    53 :             system_status.pwr_state = ON_TRIG;
-  322   322                      $DGL    0,21
-  323   323 00025 RCF000002              mov     !_system_status,#02H    ; 2                     ;[INF] 4, 1
-  324   324 00029                ??eb01_main_loop:
-  325   325                      ; line    54 :         }
-  326   326                      ; line    55 :     }
-  327   327                      $DGL    0,23
-  328   328 00029                ??eb00_main_loop:
-  329   329 00029  EF03                  br      $?L0004                                         ;[INF] 2, 3
-  330   330 0002B                ?L0003:
-  331   331                      ; line    56 :     else
-  332   332                      ; line    57 :     {
-  333   333 0002B                ??bb02_main_loop:
-  334   334                      ; line    58 :         // リブート時は実行されない
-  335   335                      ; line    59 :         system_status.pwr_state = OFF_TRIG;
-  336   336                      $DGL    0,27
-  337   337 0002B RF50000                clrb    !_system_status                                 ;[INF] 3, 1
-  338   338 0002E                ??eb02_main_loop:
-  339   339                      ; line    60 :     }
-  340   340 0002E                ?L0004:
-  341   341                      ; line    61 : 
-  342   342                      ; line    62 : #ifdef _PARRADIUM_
-  343   343                      ; line    63 :         system_status.pwr_state = OFF;
-  344   344                      ; line    64 : #endif
-  345   345                      ; line    65 :     vreg_ctr_init(  );
-  346   346                      $DGL    0,33
-  347   347 0002E RFD0000                call    !_vreg_ctr_init                                 ;[INF] 3, 3
-  348   348                      ; line    66 :     vreg_twl_init(  );
-  349   349                      $DGL    0,34
-  350   350 00031 RFD0000                call    !_vreg_twl_init                                 ;[INF] 3, 3
-  351   351                      ; line    67 : 
-  352   352                      ; line    68 :     read_dipsw(  );    // 特定スイッチで何かするか？
-  353   353                      $DGL    0,36
-  354   354 00034 RFD5D00                call    !_read_dipsw                                    ;[INF] 3, 3
-  355   355                      ; line    69 : 
-  356   356                      ; line    70 :     clear_hosu_hist(); // 履歴クリア
-  357   357                      $DGL    0,38
-  358   358 00037 RFD0000                call    !_clear_hosu_hist                               ;[INF] 3, 3
-  359   359                      ; line    71 : 
-  360   360                      ; line    72 :     renge_task_interval_run_force = 1;
-  361   361                      $DGL    0,40
-  362   362 0003A R710200                set1    _renge_task_interval_run_force                  ;[INF] 3, 2
-  363   363                      ; line    73 : 
-  364   364                      ; line    74 :     RTCIMK = 0;                 /* 割り込み(アラーム&インターバル
-  365   365                      ;              )許可 */
-  366   366                      $DGL    0,42
-  367   367 0003D  712BE7                clr1    MK1H.2                                          ;[INF] 3, 2
-  368   368                      ; line    75 : 
-  369   369                      ; line    76 :     // メインループ //
-  370   370                      ; line    77 :     while( 1 )
-  371   371 00040                ?L0007:
-  372   372                      ; line    78 :     {                           // システムtick、または割り込みで
-  373   373                      ;              廻ります。
-  374   374 00040                ??bb03_main_loop:
-  375   375                      ; line    79 :         WDT_Restart(  );
-  376   376                      $DGL    0,47
-  377   377 00040 RFD0000                call    !_WDT_Restart                                   ;[INF] 3, 3
-  378   378                      ; line    80 :         renge_task_interval_run(  );    // 内部で、システムtickま
-  379   379                      ;              たは強制起動します
-  380   380                      $DGL    0,48
-  381   381 00043 RFD0000                call    !_renge_task_interval_run                       ;[INF] 3, 3
-  382   382                      ; line    81 :         while( renge_task_interval_run_force != 0 )
-  383   383                      $DGL    0,49
-  384   384 00046                ?L0009:
-  385   385 00046 R31040005              bf      _renge_task_interval_run_force,$?L0010          ;[INF] 4, 5
-  386   386                      ; line    82 :         {
-  387   387 0004A                ??bb04_main_loop:
-  388   388                      ; line    83 :             renge_task_interval_run(  );
-  389   389                      $DGL    0,51
-  390   390 0004A RFD0000                call    !_renge_task_interval_run                       ;[INF] 3, 3
-  391   391 0004D                ??eb04_main_loop:
-  392   392                      ; line    84 :         }
-  393   393                      $DGL    0,52
-  394   394 0004D  EFF7                  br      $?L0009                                         ;[INF] 2, 3
-  395   395 0004F                ?L0010:
-  396   396                      ; line    85 :         WDT_Restart(  );
-  397   397                      $DGL    0,53
-  398   398 0004F RFD0000                call    !_WDT_Restart                                   ;[INF] 3, 3
-  399   399                      ; line    86 :         while( renge_task_immed_run(  ) != ERR_SUCCESS );       
-  400   400                      ;              // ここのループが廻る度に実行されます
-  401   401                      $DGL    0,54
-  402   402 00052                ?L0011:
-  403   403 00052 RFD0000                call    !_renge_task_immed_run                          ;[INF] 3, 3
-  404   404 00055  D2                    cmp0    c                                               ;[INF] 1, 1
-  405   405 00056  DFFA                  bnz     $?L0011                                         ;[INF] 2, 4
-  406   406                      ; line    87 :         HALT(  );
-  407   407                      $DGL    0,55
-  408   408 00058  61ED                  halt                                                    ;[INF] 2, 3
-  409   409 0005A                ??eb03_main_loop:
-  410   410                      ; line    88 :     }
-  411   411                      $DGL    0,56
-  412   412 0005A  EFE4                  br      $?L0007                                         ;[INF] 2, 3
-  413   413                      ; line    89 : }
-  414   414                      $DGL    0,57
-  415   415 0005C                ??ef_main_loop:
-  416   416 0005C  D7                    ret                                                     ;[INF] 1, 6
-  417   417 0005D                ??ee_main_loop:
-  418   418                      ; line    90 : 
-  419   419                      ; line    91 : 
-  420   420                      ; line    92 : /* ========================================================
-  421   421                      ; line    93 :  ======================================================== */
-  422   422                      ; line    94 : static void read_dipsw(  )
-  423   423                      ; line    95 : {
-  424   424 0005D                _read_dipsw:
-  425   425                      $DGL    1,93
-  426   426 0005D                ??bf_read_dipsw:
-  427   427                      ; line    96 :     // ソフトディップスイッチ読み込み
-  428   428                      ; line    97 : //  PU4 |= 0x03; // dip sw 0,1
-  429   429                      ; line    98 :     system_status.dipsw0 = ( DIPSW_0 == 0 ) ? 0 : 1;
-  430   430                      $DGL    0,4
-  431   431 0005D  31020403              bt      P4.0,$?L0015                                    ;[INF] 4, 5
-  432   432 00061  F6                    clrw    ax                                              ;[INF] 1, 1
-  433   433 00062  EF01                  br      $?L0016                                         ;[INF] 2, 3
-  434   434 00064                ?L0015:
-  435   435 00064  E6                    onew    ax                                              ;[INF] 1, 1
-  436   436 00065                ?L0016:
-  437   437 00065  60                    mov     a,x                                             ;[INF] 1, 1
-  438   438 00066 R340200                movw    de,#loww (_system_status+2)                     ;[INF] 3, 1
-  439   439 00069  718C                  mov1    CY,a.0                                          ;[INF] 2, 1
-  440   440 0006B  89                    mov     a,[de]                                          ;[INF] 1, 1
-  441   441 0006C  7189                  mov1    a.0,CY                                          ;[INF] 2, 1
-  442   442 0006E  99                    mov     [de],a                                          ;[INF] 1, 1
-  443   443                      ; line    99 :     system_status.dipsw1 = ( DIPSW_1 == 0 ) ? 0 : 1;
-  444   444                      $DGL    0,5
-  445   445 0006F  31120403              bt      P4.1,$?L0017                                    ;[INF] 4, 5
-  446   446 00073  F6                    clrw    ax                                              ;[INF] 1, 1
-  447   447 00074  EF01                  br      $?L0018                                         ;[INF] 2, 3
-  448   448 00076                ?L0017:
-  449   449 00076  E6                    onew    ax                                              ;[INF] 1, 1
-  450   450 00077                ?L0018:
-  451   451 00077  60                    mov     a,x                                             ;[INF] 1, 1
-  452   452 00078 R340200                movw    de,#loww (_system_status+2)                     ;[INF] 3, 1
-  453   453 0007B  718C                  mov1    CY,a.0                                          ;[INF] 2, 1
-  454   454 0007D  89                    mov     a,[de]                                          ;[INF] 1, 1
-  455   455 0007E  7199                  mov1    a.1,CY                                          ;[INF] 2, 1
-  456   456 00080  99                    mov     [de],a                                          ;[INF] 1, 1
-  457   457                      ; line   100 : //  PU4 &= ~0x03;
-  458   458                      ; line   101 : }
-  459   459                      $DGL    0,7
-  460   460 00081                ??ef_read_dipsw:
-  461   461 00081  D7                    ret                                                     ;[INF] 1, 6
-  462   462 00082                ??ee_read_dipsw:
-  463   463                      
-  464   464 -----                LDR_CODL        CSEG
-  465   465                      
-  466   466 -----                @@BASE  CSEG    BASE
-  467   467                              END
-  468   468                      
-  469   469                      
-  470   470                      ; *** Code Information ***
-  471   471                      ;
-  472   472                      ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c
-  473   473                      ;
-  474   474                      ; $FUNC main_loop(33)
-  475   475                      ;       void=(void)
-  476   476                      ;       CODE SIZE= 93 bytes, CLOCK_SIZE= 97 clocks, STACK_SIZE= 6 bytes
-  477   477                      ;
-  478   478                      ; $CALL RTC_init(36)
-  479   479                      ;       void=(void)
-  480   480                      ;
-  481   481                      ; $CALL renge_init(38)
-  482   482                      ;       void=(void)
-  483   483                      ;
-  484   484                      ; $CALL iic_mcu_start(40)
-  485   485                      ;       void=(void)
-  486   486                      ;
-  487   487                      ; $CALL PM_init(43)
-  488   488                      ;       void=(void)
-  489   489                      ;
-  490   490                      ; $CALL iic_mcu_read_a_byte(50)
-  491   491                      ;       bc=(int:ax, int:[sp+4])
-  492   492                      ;
-  493   493                      ; $CALL vreg_ctr_init(65)
-  494   494                      ;       void=(void)
-  495   495                      ;
-  496   496                      ; $CALL vreg_twl_init(66)
-  497   497                      ;       void=(void)
-  498   498                      ;
-  499   499                      ; $CALL read_dipsw(68)
-  500   500                      ;       void=(void)
-  501   501                      ;
-  502   502                      ; $CALL clear_hosu_hist(70)
-  503   503                      ;       void=(void)
-  504   504                      ;
-  505   505                      ; $CALL WDT_Restart(79)
-  506   506                      ;       void=(void)
-  507   507                      ;
-  508   508                      ; $CALL renge_task_interval_run(80)
-  509   509                      ;       bc=(void)
-  510   510                      ;
-  511   511                      ; $CALL renge_task_interval_run(83)
-  512   512                      ;       bc=(void)
-  513   513                      ;
-  514   514                      ; $CALL WDT_Restart(85)
-  515   515                      ;       void=(void)
-  516   516                      ;
-  517   517                      ; $CALL renge_task_immed_run(86)
-  518   518                      ;       bc=(void)
-  519   519                      ;
-  520   520                      ; $FUNC read_dipsw(95)
-  521   521                      ;       void=(void)
-  522   522                      ;       CODE SIZE= 37 bytes, CLOCK_SIZE= 38 clocks, STACK_SIZE= 0 bytes
-  523   523                      
-  524   524                      ; Target chip : uPD79F0104
-  525   525                      ; Device file : E1.00b
-
-Segment informations:
-
-ADRS  LEN      NAME
-
-00000 00000H.1 @@BITS
-00000 00030H   @@CNST
-00000 00000H   @@R_INIT
-00000 00000H   @@INIT
-00000 00204H   @@DATA
-00000 00000H   @@R_INIS
-00000 00000H   @@INIS
-00000 00000H   @@DATS
-00000 00000H   LDR_CNSL
-00000 00000H   @@RLINIT
-00000 00000H   @@INITL
-00000 00000H   @@DATAL
-00000 00000H   @@CALT
-00000 00082H   LDR_CODE
-00000 00000H   LDR_CODL
-00000 00000H   @@BASE
-
- Target chip : uPD79F0104
- Device file : E1.00b
-Assembly complete,     0 error(s) and     0 warning(s) found. (    0)
-
--- a/Show More
+++ b/Show More