mirror of
https://github.com/rvtr/ctr_firmware.git
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aabb6fb400
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@205 b871894f-2f95-9b40-918c-086798483c85
481 lines
13 KiB
C
481 lines
13 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrBrom - library - init
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File: crt0_misc.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/os.h>
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#ifdef SDK_NE1EMU
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/*---------------------------------------------------------------------------*
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Name: i_stupInitDDR2
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Description: Initialize DDR2 for NE1-TBoard
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupInitDDR2( void )
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{
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INASM_EXTERN( i_osWaitCpuCycles )
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mov r3, lr
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ldr r0, =HW_NE1EXBUS_REG
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ldr r1, =0x0000004A
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str r1, [r0, #REG_EXBUS_PCS0_OFFSET]
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ldr r1, =0x08000049
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str r1, [r0, #REG_EXBUS_PCS1_OFFSET]
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ldr r1, =0x0600004E
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str r1, [r0, #REG_EXBUS_PCS2_OFFSET]
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ldr r1, =0x0400004B
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str r1, [r0, #REG_EXBUS_PCS3_OFFSET]
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ldr r1, =0x1000004A
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str r1, [r0, #REG_EXBUS_PCS4_OFFSET]
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ldr r1, =0x1400000A
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str r1, [r0, #REG_EXBUS_PCS5_OFFSET]
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ldr r1, =0x10388E7F
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str r1, [r0, #REG_EXBUS_PCS0TIM_OFFSET]
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ldr r1, =0x10388E7E
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str r1, [r0, #REG_EXBUS_PCS1TIM_OFFSET]
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ldr r1, =0x10388E7E
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str r1, [r0, #REG_EXBUS_PCS2TIM_OFFSET]
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ldr r1, =0x10388E7F
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str r1, [r0, #REG_EXBUS_PCS3TIM_OFFSET]
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ldr r1, =0x10388E7E
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str r1, [r0, #REG_EXBUS_PCS4TIM_OFFSET]
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ldr r1, =0x10388E7E
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str r1, [r0, #REG_EXBUS_PCS5TIM_OFFSET]
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// Check device version
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// ES1.0 : go to ContinueBoot
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ldr r0, =HW_NE1SYS_REG
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ldr r1, [r0, #REG_SYS_VERSION_OFFSET]
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ldr r2, =0x00000001
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cmp r1, r2
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bne ContinueBoot
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// Check reset cause
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// Software reset : ContinueBoot
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ldr r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]
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and r1, r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
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mov r2, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
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cmp r1, r2
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beq ContinueBoot
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// Check BTM
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// DSW1_7 OFF : ContinueBoot
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ldr r1, [r0, #REG_SYS_BOOT_ID_OFFSET]
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and r1, r1, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK
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mov r2, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK
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cmp r1, r2
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bne ContinueBoot
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// Change WTOP normal mode setting
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ldr r1, [r0, #REG_SYS_WTOP_MODE_OFFSET]
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and r1, r1, #0xFFFFFFFE
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str r1, [r0, #REG_SYS_WTOP_MODE_OFFSET]
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// Do Software reset
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mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_MASK
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str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]
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wait_reset
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b wait_reset
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ContinueBoot
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// Clear Software reset
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mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
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str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]
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// Setup DDR2
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ldr r0, =HW_NE1DDR2_REG
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ldr r1, =0x30022123
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str r1, [r0, #REG_MIF_SDC_CFG2_OFFSET]
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mov r1, #0x1
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str r1, [r0, #REG_MIF_DLL_CFG_OFFSET]
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mov r1, #0x20
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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// wait 480ns
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ldr r0, =__cpp(OS_USEC_TO_TICK32(10))
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bl i_osWaitCpuCycles
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ldr r0, =HW_NE1DDR2_REG
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ldr r1, =0x10000004
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x00010002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x00018002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x00008002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x1D480002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x10000004
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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mov r1, #0x1
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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mov r1, #0x1
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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// wait 1080ns
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ldr r0, =__cpp(OS_USEC_TO_TICK32(10))
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bl i_osWaitCpuCycles
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ldr r0, =HW_NE1DDR2_REG
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ldr r1, =0x19480002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x01308002
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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mov r1, #0x100
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str r1, [r0, #REG_MIF_INIT_OFFSET]
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ldr r1, =0x1485A912
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str r1, [r0, #REG_MIF_SDC_CFG1_OFFSET]
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ldr r1, =0x00000121
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str r1, [r0, #REG_MIF_REF_CFG_OFFSET]
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mov lr, r3
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bx lr
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}
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#endif // SDK_NE1EMU
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/*---------------------------------------------------------------------------*
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Name: stupDisableCP15
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Description: Disable Coprocessor 15
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void stupDisableCP15( void )
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{
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// MMU/Caches/BranchPrediction disable
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
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| HW_C1_FORCE_AP_BIT \
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| HW_C1_TEX_CB_REMAP \
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| HW_C1_EXCEPT_BIG_ENDIAN \
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| HW_C1_BR_PREDICT_ENABLE \
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| HW_C1_LD_INTERWORK_DISABLE \
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| HW_C1_UNALIGN_ACCESS_ENABLE \
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| HW_C1_ALIGN_FAULT_ENABLE \
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| HW_C1_ROM_PROTECT_ENABLE \
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| HW_C1_MMU_PROTECT_ENABLE \
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| HW_C1_MMU_ENABLE
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#ifndef SDK_MG20EMU
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orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
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#endif // SDK_MG20EMU
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bic r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 1
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ldr r1, =HW_C1_SMP_MODE \
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| HW_C1_EXCLUSIVE_L1C_L2C \
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| HW_C1_BR_FOLDING_ENABLE \
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| HW_C1_SBR_PREDICT_ENABLE \
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| HW_C1_DBR_PREDICT_ENABLE \
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| HW_C1_RETURN_STACK_ENABLE
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bic r0, r0, r1
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mcr p15, 0, r0, c1, c0, 1
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// Invalidate Caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // Inst Cache
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mcr p15, 0, r0, c7, c6, 0 // Data cache
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// Wait for write buffer empty
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: stupEnableCP15
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Description: Enable Coprocessor 15
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void stupEnableCP15( void )
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{
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//
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// Auxiliary Control
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//
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mrc p15, 0, r0, c1, c0, 1
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ldr r1, =HW_C1_AMP_MODE \
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| HW_C1_BR_FOLDING_ENABLE \
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| HW_C1_SBR_PREDICT_ENABLE \
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| HW_C1_DBR_PREDICT_ENABLE \
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| HW_C1_RETURN_STACK_ENABLE
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 1
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//
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// Master Control
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//
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, = 0 \
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| HW_C1_EXCEPT_LITTLE_ENDIAN \
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| HW_C1_UNALIGN_ACCESS_ENABLE \
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| HW_C1_BR_PREDICT_ENABLE \
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| HW_C1_MMU_V6 \
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| HW_C1_IC_ENABLE \
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| HW_C1_DC_ENABLE \
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| HW_C1_MMU_ENABLE
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#ifdef SDK_MG20EMU
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orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
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#endif // SDK_MG20EMU
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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// Invalidate Caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // Inst Cache
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mcr p15, 0, r0, c7, c6, 0 // Data cache
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// Wait for write buffer empty
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: __user_initial_stackheap
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Description: called from __scatterload
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void __user_initial_stackheap( void )
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{
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#ifdef BROM_ENABLE_INITIAL_STACKHEAP
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INASM_EXTERN( |Image$$ZI$$ZI$$Limit| )
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ldr r0, =|Image$$ZI$$ZI$$Limit| // heap base
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ldr r1, =HW_BROM_IRQ_STACK_END
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sub r1, r1, #HW_BROM_IRQ_STACK_SIZE
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mov r2, r0
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mov r3, r0
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#endif // BROM_ENABLE_INITIAL_STACKHEAP
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitSections
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Description: Initialize Sections
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void stupInitSections( void )
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{
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b stupInitStaticSections
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitStaticSections
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Description: Initialize Static Sections
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void stupInitStaticSections( void )
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{
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#ifdef BROM_TARGET_BROM
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INASM_EXTERN( |Image$$SEC_RO$$Limit| )
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ldr r0, =|Image$$SEC_RO$$Limit|
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#else // BROM_TARGET_NORFIRM || BROM_TARGET_APP
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INASM_EXTERN( |Image$$RO$$Limit| )
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ldr r0, =|Image$$RO$$Limit|
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#endif // BROM_TARGET_NORFIRM || BROM_TARGET_APP
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INASM_EXTERN( |Image$$RW$$Base| )
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INASM_EXTERN( |Image$$ZI$$ZI$$Base| )
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INASM_EXTERN( |Image$$ZI$$ZI$$Limit| )
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ldr r1, =|Image$$RW$$Base|
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ldr r3, =|Image$$ZI$$ZI$$Base|
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cmp r0, r1
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beq FSYM(20)
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LSYM(10)
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cmp r1, r3
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ldrcc r2, [r0], #4
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strcc r2, [r1], #4
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bcc BSYM(10)
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LSYM(20)
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ldr r1, =|Image$$ZI$$ZI$$Limit|
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mov r2, #0
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LSYM(30)
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cmp r3, r1
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strcc r2, [r3], #4
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bcc BSYM(30)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: i_stupCpuCopy32
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Description: copy memory by CPU
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32bit version
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Arguments: srcp : source address
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destp : destination address
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size : size (byte)
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupCpuCopy32( const void *srcp, void *destp, u32 size )
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{
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add r12, r1, r2
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LSYM(10)
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cmp r1, r12
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ldmltia r0!, {r2}
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stmltia r1!, {r2}
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blt BSYM(10)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: i_stupCpuClear32
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Description: fill memory with specified data.
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32bit version
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Arguments: data : fill data
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destp : destination address
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size : size (byte)
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupCpuClear32( u32 data, void *destp, u32 size )
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{
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add r12, r1, r2
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LSYM(10)
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cmp r1, r12
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stmltia r1!, {r0}
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blt BSYM(10)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: i_stupNotifyToARM9
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Description: notify 4bit id to ARM9
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Arguments: id notifying id
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupNotifyToARM9( u32 id )
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{
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ldr r3, =REG_SUBPINTF_ADDR
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mov r0, r0, lsl #REG_PXI_SUBPINTF_A11STATUS_SHIFT
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and r0, r0, #REG_PXI_SUBPINTF_A11STATUS_MASK
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str r0, [r3]
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: i_stupWaitARM9
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Description: Wait 4bit id from ARM9
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Arguments: id waiting id
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupWaitARM9( u32 id )
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{
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ldr r3, =REG_SUBPINTF_ADDR
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LSYM(10)
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ldr r1, [r3]
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and r1, r1, #REG_PXI_SUBPINTF_A9STATUS_MASK
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cmp r0, r1
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bne BSYM(10)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: i_stupWaitCpuCycles
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Description: Loop and Wait for specified CPU cycles at least
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Arguments: cycles waiting CPU cycle
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void i_stupWaitCpuCycles( u32 cycle )
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{
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sub r0, r0, #(6-2) // subtract call-return overhead and add the margin of 2 cycles
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LSYM(10)
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subs r0, r0, #4 // 1 cycle
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bcs BSYM(10) // 3 cycle
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bx lr
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}
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