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https://github.com/rvtr/ctr_firmware.git
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fd439a38ea
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@135 b871894f-2f95-9b40-918c-086798483c85
124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrBrom - library - init
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File: crt0.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/os.h>
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void _start(void);
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/*---------------------------------------------------------------------------*
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Name: _start
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Description: Start up
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Arguments: None
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Returns: None.
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*---------------------------------------------------------------------------*/
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asm void _start( void )
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{
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PRESERVE8
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CODE32 // for _start reference
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INASM_EXTERN( i_stupIrqVeneer )
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INASM_EXTERN( i_stupFiqVeneer )
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INASM_EXTERN( i_stupSwiVeneer )
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INASM_EXTERN( i_stupUndefInstVeneer )
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INASM_EXTERN( i_stupPrefetchAbortVeneer )
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INASM_EXTERN( i_stupDataAbortVeneer )
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b stupStartHandlerVeneer // don't change for NULL access compatibility
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undef b i_stupUndefInstVeneer
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swi b i_stupSwiVeneer
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iabt b i_stupPrefetchAbortVeneer
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dabt b i_stupDataAbortVeneer
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reserve b reserve
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irq b i_stupIrqVeneer
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fiq b i_stupFiqVeneer
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#ifdef SDK_MG20EMU
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// MG20_CONFIG
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DCD 0x3105
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#endif // SDK_MG20EMU
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INASM_EXTERN( i_stupSwiHandler )
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DCD i_stupSwiHandler
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#ifdef SDK_MG20EMU
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SPACE 0x20 - 8
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#endif // SDK_MG20EMU
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stupStartHandlerVeneer
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// NULLジャンプ時のデータアボート有効時はリテラルプールアクセスにてアボート
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ldr r12, =HW_BROM_SEC
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// NULLデータアボート無効時はセキュアROM切り離しチェック
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ldr r12, [r12]
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cmp r12, #0
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cmpne r12, #~0
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LSYM(1) beq BSYM(1)
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//---- enable performance monitor
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mrc p15, 0, r0, c15, c12, 0
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ldr r1, =HW_C15_PMN_ENABLE | HW_C15_CYCLE_COUNT_RESET | HW_C15_COUNT01_RESET | \
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(HW_C15_EVT_INC_EACH_CYCLE << HW_C15_COUNT0_EVT_SFT) | \
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(HW_C15_EVT_INC_EACH_CYCLE << HW_C15_COUNT1_EVT_SFT) | \
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HW_C15_CYCLE_COUNT_D64
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orr r0, r0, r1
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// bic r0, r0, #HW_C15_CYCLE_COUNT_D64
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mcr p15, 0, r0, c15, c12, 0
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//---- check CPU-ID
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mrc p15,0, r0, c0, c0, 5
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tst r0, #HW_C0_AP_CPU_ID_MASK
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beq core0_start
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//---- Wait for IPI
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#ifdef BROM_USE_MPCORE_EXTEND_OP
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cpsid i
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#else
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mrs r0, cpsr
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orr r1, r0, #HW_PSR_IRQ_DISABLE
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msr cpsr_c, r1
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#endif
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ldr r3, =REG_IDR_CNT_ADDR
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mov r0, #REG_OS_IDR_CNT_E_MASK
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str r0, [r3]
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ldr r3, =REG_IDR_CLR_PND0_ADDR
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ldr r1, =REG_OS_IDR_CLR_PND0_IPI_ALL_MASK
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mov r0, #~0
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str r0, [r3]
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LSYM(10)
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ldr r0, [r3]
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tst r0, r1
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wfieq
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nop
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beq BSYM(10)
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ldr lr, =HW_START_VECTOR1_BUF
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ldr lr, [lr]
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bx lr
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core0_start
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INASM_EXTERN( i_stupStartHandler )
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b i_stupStartHandler
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LTORG
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}
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