ctr_firmware/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
nakasima 1e31ea5b8b NE1EMUでのブートROMのミラーリングへ対応。
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@231 b871894f-2f95-9b40-918c-086798483c85
2009-01-29 06:45:19 +00:00

109 lines
3.2 KiB
C

/*---------------------------------------------------------------------------*
Project: CtrBrom - library - init
File: crt0_secure.c
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: $
$Rev$
$Author$
*---------------------------------------------------------------------------*/
#include <brom/code32.h>
#include <brom/os.h>
/*---------------------------------------------------------------------------*
Name: i_stupStartHandler
Description: start handler
Arguments: None
Returns: None.
*---------------------------------------------------------------------------*/
asm void i_stupStartHandler( void )
{
PRESERVE8
INASM_EXTERN( stupInitExceptions )
INASM_EXTERN( BromMain )
INASM_EXTERN( main )
// jump from image address to physical address
ldr pc, =image_to_physical
image_to_physical
//---- initialize stack pointer
// SVC mode
mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr sp, =HW_BROM_SVC_STACK_END
// IRQ mode
mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_IRQ_STACK_END
mov sp, r0
// System mode
mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_SYS_STACK_END
mov sp, r0
#ifdef SDK_NE1EMU
//---- initialize DDR2
bl i_stupInitDDR2
#endif // SDK_NE1EMU
//---- initialize exceptions
bl stupInitExceptions
//---- disable cp15
bl stupDisableCP15
//---- initialize MMU
ldr r0, =HW_BROM_MMU_T1
ldr r1, =HW_BROM_MMU_T2
bl stupInitMMU
//---- enable cp15
bl stupEnableCP15
//---- clear wram
// 4KB
mov r0, #0
ldr r1, =HW_AXI_WRAM_SHARED_SYS
ldr r2, =HW_EXCP_VENEER_BUF
sub r2, r2, r1
bl i_stupCpuClear32
ldr r1, =HW_EXCP_VENEER_BUF_END
rsb r2, r1, #HW_AXI_WRAM_END
bl i_stupCpuClear32
//---- lnitialize sections
bl stupInitSections
//---- start (to 16bit code)
ldr r1, =BromMain
adr lr, terminate
bx r1
terminate
b terminate
}
#ifdef SDK_NE1EMU
#include <./crt0_ne1.c>
#endif // SDK_NE1EMU
#include <./crt0_mmu.c>
#include <./crt0_misc.c>