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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@223 b871894f-2f95-9b40-918c-086798483c85
81 lines
3.7 KiB
C
81 lines
3.7 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrFirm - HW - include
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File: mmap_axi_wram.h
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#ifndef CTR_HW_ARM11_AXI_WRAM_H_
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#define CTR_HW_ARM11_AXI_WRAM_H_
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#include <ctr/hw/common/mmap_shared.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---- system reserved area
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#define HW_AXI_WRAM_SYSRV HW_AXI_WRAM_SHARED_SYS_A11
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#define HW_AXI_WRAM_SYSRV_END HW_AXI_WRAM_SHARED_SYS_A11_END
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#define HW_AXI_WRAM_SYSRV_SIZE HW_AXI_WRAM_SHARED_SYS_A11_SIZE
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//---- offset in system reserved area
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#ifdef SDK_ARM11
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// FCRAMまで命令プリフェッチしないように配置（MPCoreは8段パイプライン）
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_VENEER 0x00
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#define HW_AXI_WRAM_SYSRV_OFS_FIQ_VENEER 0x08
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#define HW_AXI_WRAM_SYSRV_OFS_SWI_VENEER 0x10
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#define HW_AXI_WRAM_SYSRV_OFS_UNDEF_VENEER 0x18
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#define HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER 0x20
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#define HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER 0x28
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#endif // SDK_ARM11
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#define HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF 0x30 // for firmware
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#define HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF 0x34 // for firmware
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#ifdef SDK_ARM11
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#define HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1 0x3c
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1 0x40
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0 0x50
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#endif // SDK_ARM11
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//---- system reserved area
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#ifdef SDK_ARM11
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#define HW_EXCP_VENEER_BUF (HW_INTR_VENEER_BUF)
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#define HW_EXCP_VENEER_BUF_END (HW_EXCP_VENEER_BUF + HW_EXCP_VENEER_BUF_SIZE)
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#define HW_EXCP_VENEER_BUF_SIZE (8 * 6)
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#define HW_INTR_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_VENEER)
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#define HW_INTR_VECTOR_BUF (HW_INTR_VENEER_BUF + 4)
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#define HW_FIQ_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_FIQ_VENEER)
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#define HW_FIQ_VECTOR_BUF (HW_FIQ_VENEER_BUF + 4)
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#define HW_SWI_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_SWI_VENEER)
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#define HW_SWI_VECTOR_BUF (HW_SWI_VENEER_BUF + 4)
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#define HW_UNDEF_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_UNDEF_VENEER)
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#define HW_UNDEF_VECTOR_BUF (HW_UNDEF_VENEER_BUF + 4)
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#define HW_IABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER)
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#define HW_IABT_VECTOR_BUF (HW_IABT_VENEER_BUF + 4)
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#define HW_DABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER)
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#define HW_DABT_VECTOR_BUF (HW_DABT_VENEER_BUF + 4)
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#endif // SDK_ARM11
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#define HW_INIT_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF)
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#define HW_CARD_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF)
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#ifdef SDK_ARM11
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#define HW_START_VECTOR1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
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#define HW_INTR_CHECK1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)
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#define HW_INTR_CHECK0_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0)
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#endif // SDK_ARM11
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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/* CTR_HW_ARM11_AXI_WRAM_H_ */
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#endif
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