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https://github.com/rvtr/ctr_firmware.git
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01c59b7756
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@192 b871894f-2f95-9b40-918c-086798483c85
141 lines
5.4 KiB
C
141 lines
5.4 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrFirm - include - ctr - HW - ARM11
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File: mmap_global.h
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#ifndef CTR_HW_ARM11_MMAP_GLOBAL_H_
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#define CTR_HW_ARM11_MMAP_GLOBAL_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*
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GLOBAL MEMORY MAP
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*---------------------------------------------------------------------------*/
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//----------------------------- MAIN
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#ifndef SDK_NE1EMU
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#define HW_MAIN_MEM 0x20000000
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#else // SDK_NE1EMU
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#define HW_MAIN_MEM 0x80000000
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#define HW_MAIN_MEM_NE1EMU_SIZE 0x10000000 // 256MB
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#endif // SDK_NE1EMU
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#define HW_MAIN_MEM_EX HW_MAIN_MEM_END
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#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE)
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#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE)
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#define HW_MAIN_MEM_SIZE 0x04000000 // 64MB
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#define HW_MAIN_MEM_EX_SIZE 0x08000000 // 128MB
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#if !defined(SDK_MG20EMU) && !defined(SDK_NE1EMU)
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//----------------------------- AXI-WRAM
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#define HW_AXI_WRAM 0x1ff80000
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#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE)
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#define HW_AXI_WRAM_SIZE 0x80000 // 512KB
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//----------------------------- DSP-WRAM
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#define HW_DSP_WRAM 0x1ff00000
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#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE)
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#define HW_DSP_WRAM_SIZE 0x80000 // 512KB
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//----------------------------- VRAM
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#define HW_VRAM 0x18000000
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#define HW_VRAM_END (HW_MAIN_MEM + HW_VRAM_SIZE)
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#define HW_VRAM_SIZE 0x400000 // 4MB
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#else // SDK_MG20EMU || SDK_NE1EMU
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//----------------------------- AXI-WRAM
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#define HW_AXI_WRAM (HW_AXI_WRAM_END - HW_AXI_WRAM_SIZE)
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#ifdef SDK_MG20EMU
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#define HW_AXI_WRAM_END HW_MAIN_MEM_END
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#else // SDK_NE1EMU
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#define HW_AXI_WRAM_END (HW_MAIN_MEM + HW_MAIN_MEM_NE1EMU_SIZE)
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#endif // SDK_NE1EMU
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#define HW_AXI_WRAM_SIZE 0x80000 // 512KB
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//----------------------------- DSP-WRAM
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#define HW_DSP_WRAM (HW_DSP_WRAM_END - HW_DSP_WRAM_SIZE)
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#define HW_DSP_WRAM_END HW_AXI_WRAM
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#define HW_DSP_WRAM_SIZE 0x80000 // 512KB
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//----------------------------- VRAM
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#ifdef SDK_MG20EMU
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#define HW_VRAM 0x1e000000
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#else // SDK_NE1EMU
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#define HW_VRAM HW_IOREG_END
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#endif // SDK_NE1EMU
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#define HW_VRAM_END (HW_VRAM + HW_VRAM_SIZE)
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#define HW_VRAM_SIZE 0x400000 // 4MB
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#endif // SDK_MG20EMU || SDK_NE1EMU
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//----------------------------- IOs
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#ifndef SDK_NE1EMU
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#define HW_IOREG 0x10000000
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#else // SDK_NE1EMU
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#define HW_IOREG HW_MAIN_MEM_EX_END
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#endif // SDK_NE1EMU
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#define HW_IOREG_END (HW_IOREG + HW_IOREG_SIZE)
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#define HW_IOREG_SIZE 0x01000000 // 16MB
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#define HW_REG_BASE HW_IOREG // alias
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#define HW_AHBP_REG (HW_IOREG + 0x00100000)
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#define HW_APB_REG (HW_IOREG + 0x00200000)
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#define HW_AHBML_REG (HW_IOREG + 0x00300000)
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#define HW_GPU_REG (HW_IOREG + 0x00400000)
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#if !defined(SDK_MG20EMU) && !defined(SDK_NE1EMU)
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#define HW_MPCORE_REG (HW_IOREG + 0x07e00000)
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#else // SDK_MG20EMU || SDK_NE1EMU
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#ifdef SDK_MG20EMU
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#define HW_MPCORE_REG 0xff000000
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#else // SDK_NE1EMU
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#define HW_MPCORE_REG 0xc0000000
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#define HW_NE1SYS_REG 0x18037c00
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#define HW_NE1EXBUS_REG 0x1801a000
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#define HW_NE1DDR2_REG 0x18021000
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#endif // SDK_NE1EMU
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#endif // SDK_MG20EMU || SDK_NE1EMU
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#define HW_AHBP_REG_END (HW_AHBP_REG + HW_AHBP_REG_SIZE)
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#define HW_APB_REG_END (HW_APB_REG + HW_APB_REG_SIZE)
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#define HW_AHBML_REG_END (HW_AHBML_REG + HW_AHBML_REG_SIZE)
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#define HW_GPU_REG_END (HW_GPU_REG + HW_GPU_REG_SIZE)
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#define HW_MPCORE_REG_REG (HW_MPCORE_REG + HW_MPCORE_REG_SIZE)
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#define HW_AHBP_REG_SIZE 0x80000 // 512KB
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#define HW_APB_REG_SIZE 0x100000 // 1MB
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#define HW_AHBML_REG_SIZE 0x40000 // 256KB
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#define HW_GPU_REG_SIZE 0x100000 // 1MB
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#define HW_MPCORE_REG_SIZE 0x20000 // 128KB
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//----------------------------- System ROM
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#ifdef SDK_MG20EMU
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#define HW_BIOS_IMG 0xfffe0000
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#define HW_BIOS 0xffff0000
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#else // include SDK_NE1EMU
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#define HW_BIOS_IMG 0x00000000
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#ifdef SDK_NE1EMU
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#define HW_BIOS 0x00000000
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#else // SDK_NE1EMU
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#define HW_BIOS 0x00010000
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#endif // SDK_NE1EMU
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#endif // include SDK_NE1EMU
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#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
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#define HW_BIOS_SIZE 0x8000 // 32KB
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/*---------------------------------------------------------------------------*/
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif /* CTR_HW_ARM11_MMAP_GLOBAL_H_ */
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