/*---------------------------------------------------------------------------*
  Project:  CtrBrom - libraries - OS
  File:     os_cache.c

  Copyright 2008 Nintendo.  All rights reserved.

  These coded instructions, statements, and computer programs contain
  proprietary information of Nintendo of America Inc. and/or Nintendo
  Company Ltd., and are protected by Federal copyright law.  They may
  not be disclosed to third parties or copied or duplicated in any form,
  in whole or in part, without the prior written consent of Nintendo.

  $Date::            $
  $Rev$
  $Author$
 *---------------------------------------------------------------------------*/
#include <brom/os.h>
#include <brom/code32.h>

//===========================================================================
//              DATA CACHE CONTROL
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osEnableDCache

  Description:  enable data cache

  Arguments:    None

  Returns:      previous state
 *---------------------------------------------------------------------------*/
asm BOOL osEnableDCache( void )
{
        PRESERVE8

        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_DC_ENABLE
        mov     r0, r0, LSR #HW_C1_DC_ENABLE_SFT
        orr     r1, r1, #HW_C1_DC_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osDisableDCache

  Description:  disable data cache

  Arguments:    None

  Returns:      previous stats
 *---------------------------------------------------------------------------*/
asm BOOL osDisableDCache( void )
{
        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_DC_ENABLE
        mov     r0, r0, LSR #HW_C1_DC_ENABLE_SFT
        bic     r1, r1, #HW_C1_DC_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osRestoreDCache

  Description:  set state of data cache

  Arguments:    data cache state to be set

  Returns:      previous state
 *---------------------------------------------------------------------------*/
asm BOOL osRestoreDCache( BOOL enable )
{
        //---- 引数処理
        cmp     r0, #0
        moveq   r2, #0
        movne   r2, #HW_C1_DC_ENABLE

        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_DC_ENABLE
        mov     r0, r0, LSR #HW_C1_DC_ENABLE_SFT
        bic     r1, r1, #HW_C1_DC_ENABLE
        orr     r1, r1, r2
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

//===========================================================================
//              DATA CACHE (for all range)
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osInvalidateDCacheAll

  Description:  invalidate all data cache

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateDCacheAll( void )
{
        mov     r0, #0
        mcr     p15, 0, r0, c7, c6, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osStoreDCacheAll

  Description:  clean all data cache
                (write cache data to memory)

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osStoreDCacheAll( void )
{
        mov     r1, #0
LSYM(1)
        mov     r0, #0
LSYM(2)
        orr     r2, r1, r0
        mcr     p15, 0, r2, c7, c10, 2
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, #HW_DC_SIZE/4
        blt     BSYM(2)

        add     r1, r1, #1<<HW_C7_CACHE_WAY_NO_SFT
        cmp     r1, #0
        bne     BSYM(1)

        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osFlushDCacheAll

  Description:  clean and invalidate all data cache
                (write cache data to memory, and invalidate cache)

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osFlushDCacheAll( void )
{
        mov     r12, #0
        mov     r1, #0          // r1: セットＮｏカウンタ（0 〜 3）

LSYM(1)
        mov     r0, #0          // r0: ラインカウンタ（0 〜 DCACHE_SIZE/4）

LSYM(2)
        orr     r2, r1, r0
        mcr     p15, 0, r12, c7, c10, 4 /* wait write buffer empty */
        mcr     p15, 0, r2, c7, c14, 2  /* flush */
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, #HW_DC_SIZE/4
        blt     BSYM(2)

        add     r1, r1, #1<<HW_C7_CACHE_WAY_NO_SFT
        cmp     r1, #0
        bne     BSYM(1)

        bx      lr
}

//===========================================================================
//              DATA CACHE (for specified range)
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osInvalidateDCacheRange

  Description:  invalidate data cache in specified range

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateDCacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1

LSYM(1)
        mcr     p15, 0, r0, c7, c6, 1
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osStoreDCacheRange

  Description:  clean data cache in specified range
                (write cache data to memory)

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osStoreDCacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1

LSYM(1)
        mcr     p15, 0, r0, c7, c10, 1
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osFlushDCacheRange

  Description:  clean and invalidate data cache in specified range
                (write cache data to memory, and invalidate cache)

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osFlushDCacheRange( void* startAddr, u32 nBytes )
{
        mov     r12, #0
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1
LSYM(1)
        mcr     p15, 0, r12, c7, c10, 4 /* wait write buffer empty */
        mcr     p15, 0, r0, c7, c14, 1 /* flush */
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)

        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osInvalidateDCacheRangeOrAll

  Description:  invalidate data cache in specified range or all

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osInvalidateDCacheRangeOrAll( void* startAddr, u32 nBytes )
{
    if ( nBytes < HW_DC_SIZE )
    {
        osInvalidateDCacheRange( startAddr, nBytes );
	}
	else
	{
        osInvalidateDCacheAll();
	}
}

/*---------------------------------------------------------------------------*
  Name:         osStoreDCacheRangeOrAll

  Description:  clean data cache in specified range
                (write cache data to memory)

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osStoreDCacheRangeOrAll( void* startAddr, u32 nBytes )
{
    if ( nBytes < HW_DC_SIZE )
    {
        osStoreDCacheRange( startAddr, nBytes );
	}
	else
	{
        osStoreDCacheAll();
	}
}

/*---------------------------------------------------------------------------*
  Name:         osFlushDCacheRangeOrAll

  Description:  clean data cache in specified range
                (write cache data to memory)

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osFlushDCacheRangeOrAll( void* startAddr, u32 nBytes )
{
    if ( nBytes < HW_DC_SIZE )
    {
        osFlushDCacheRange( startAddr, nBytes );
	}
	else
	{
        osFlushDCacheAll();
	}
}

//===========================================================================
//              DATA CACHE (for specified range)
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osLockdownDCacheRange

  Description:  lock specified area to prevent not to release data cache

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osLockdownDCacheRange( void* startAddr, u32 nBytes )
{
#ifdef SDK_ARM9
        INASM_EXTERN( osDisableInterrupts )
        INASM_EXTERN( osRestoreInterrupts )

        add     r1, r1, r0                              // r1: エンドアドレス
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1
        mrc     p15, 0, r3, c9, c0, 0
        and     r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK     // r3: カレントセットＮｏ
        cmp     r3, #3                                  // ３セットをロックダウンしていればエラー
        mvneq   r0, #0
        bxeq    lr

        stmfd   sp!, { lr, r0, r1 }
        ldr     r0,  =osDisableInterrupts
        blx     r0
        mov     r2, r0
        ldmfd   sp!, { lr, r0, r1 }

        orr     r3, r3, #HW_C9_LOCKDOWN_LOAD_MODE       // キャッシュロックダウン・ロードモード
        mcr     p15, 0, r3, c9, c0, 0

LSYM(1)
        mcr     p15, 0, r0, c7, c14, 1                  // キャッシュに乗っているデータを一旦クリーン／無効化する
        ldr     r12, [r0]                               // データを読み込みキャッシュに乗せる
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        add     r3, r3, #1                              // キャッシュ通常モード ＆ セットＮｏのインクリメント
        bic     r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE
        mcr     p15, 0, r3, c9, c0, 0

        stmfd   sp!, { lr }
        mov     r0, r2
        ldr     r1, =osRestoreInterrupts
        blx     r1
        ldmfd   sp!, { lr }

        bx          lr
#else // SDK_ARM11
#endif
}


/*---------------------------------------------------------------------------*
  Name:         osUnlockdownDCacheAll

  Description:  unlock all data cache to enable to release

  Arguments:    none.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osUnlockdownDCacheAll( void )
{
#ifdef SDK_ARM9
        mov     r3, #0
        mcr     p15, 0, r3, c9, c0, 0
        bx      lr
#else // SDK_ARM11
#endif
}

/*---------------------------------------------------------------------------*
  Name:         osUnlockdownDCache

  Description:  unlock any data cache to enable to release

  Arguments:    num  - specify number of datablock to unlock.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osUnlockdownDCache( u32 num )
{
#ifdef SDK_ARM9
        mrc     p15, 0, r3, c9, c0, 0
        and     r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK
        subs    r3, r3, r0
        movmi   r3, #0
        mcr     p15, 0, r3, c9, c0, 0
        bx      lr
#else // SDK_ARM11
#endif
}


/*---------------------------------------------------------------------------*
  Name:         osWaitWriteBufferEmpty

  Description:  wait till write buffer becomes to be empty

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osWaitWriteBufferEmpty( void )
{
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4
        bx      lr
}


/*---------------------------------------------------------------------------*
  Name:         osTouchDCacheRange

  Description:  include specified area to data cache in advance

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osTouchDCacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1

LSYM(1)
#ifdef SDK_ARM11
        pld     [r0]
#else // SDK_ARM9
        ldr     r2, [r0]
#endif // SDK_ARM9
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

#ifdef SDK_ARM11

/*---------------------------------------------------------------------------*
  Name:         osKeepDataAccessOrder

  Description:  keep data access order

  Arguments:    None

  Returns:      None
 *---------------------------------------------------------------------------*/
asm void osKeepDataAccessOrder( void )
{
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 5
        bx      lr
}

#endif // SDK_ARM11


//===========================================================================
//              INSTRUCTION CACHE CONTROL
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osEnableICache

  Description:  enable instruction cache

  Arguments:    None

  Returns:      previous state
 *---------------------------------------------------------------------------*/
asm BOOL osEnableICache( void )
{
        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_IC_ENABLE
        mov     r0, r0, LSR #HW_C1_IC_ENABLE_SFT
        orr     r1, r1, #HW_C1_IC_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osDisableICache

  Description:  disable instruction cache

  Arguments:    None

  Returns:      previous stats
 *---------------------------------------------------------------------------*/
asm BOOL osDisableICache( void )
{
        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_IC_ENABLE
        mov     r0, r0, LSR #HW_C1_IC_ENABLE_SFT
        bic     r1, r1, #HW_C1_IC_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osRestoreICache

  Description:  set state of instruction cache

  Arguments:    instruction cache state to be set

  Returns:      previous stats
 *---------------------------------------------------------------------------*/
asm BOOL osRestoreICache( BOOL enable )
{
        //---- 引数処理
        cmp     r0, #0
        moveq   r2, #0
        movne   r2, #HW_C1_IC_ENABLE

        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_IC_ENABLE
        mov     r0, r0, LSR #HW_C1_IC_ENABLE_SFT
        bic     r1, r1, #HW_C1_IC_ENABLE
        orr     r1, r1, r2
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

//===========================================================================
//              INSTRUCTION CACHE
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osInvalidateICacheAll

  Description:  invalidate all instruction cache

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateICacheAll( void )
{
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osInvalidateICacheRange

  Description:  invalidate instruction cache in specified range

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateICacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1

LSYM(1)
        mcr     p15, 0, r0, c7, c5, 1
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osInvalidateICacheRangeOrAll

  Description:  invalidate instruction cache in specified range or all

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osInvalidateICacheRangeOrAll( void* startAddr, u32 nBytes )
{
    if ( nBytes < HW_DC_SIZE )
    {
        osInvalidateICacheRange( startAddr, nBytes );
	}
	else
	{
        osInvalidateICacheAll();
	}
}

#ifdef SDK_ARM9

/*---------------------------------------------------------------------------*
  Name:         osLockdownICacheRange

  Description:  lock specified area to prevent not to release instruction cache

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osLockdownICacheRange( void* startAddr, u32 nBytes )
{
        INASM_EXTERN( osDisableInterrupts )
        INASM_EXTERN( osRestoreInterrupts )

        add     r1, r1, r0                              // r1: エンドアドレス
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1
        mrc     p15, 0, r3, c9, c0, 1
        and     r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK     // r3: カレントセットＮｏ
        cmp     r3, #3                                  // ３セットをロックダウンしていればエラー
        mvneq   r0, #0
        bxeq        lr

        stmfd   sp!, { lr, r0, r1 }
        ldr     r0,  =osDisableInterrupts
        blx     r0
        mov     r2, r0
        ldmfd   sp!, { lr, r0, r1 }

        orr     r3, r3, #HW_C9_LOCKDOWN_LOAD_MODE       // キャッシュロックダウン・ロードモード
        mcr     p15, 0, r3, c9, c0, 1

LSYM(1)
        mcr     p15, 0, r0, c7, c5, 1                   // キャッシュから一旦無効化
        mcr     p15, 0, r0, c7, c13, 1                  // プリフェッチ
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        add     r3, r3, #1                              // キャッシュ通常モード ＆ セットＮｏのインクリメント
        bic     r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE
        mcr     p15, 0, r3, c9, c0, 1

        stmfd   sp!, { lr }
        mov     r0, r2
        ldr     r1, =osRestoreInterrupts
        blx     r1
        ldmfd   sp!, { lr }

        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osUnlockdownICacheAll

  Description:  unlock all instruction cache to enable to release

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osUnlockdownICacheAll( void )
{
        mov     r3, #0
        mcr     p15, 0, r3, c9, c0, 1
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osUnlockdownICache

  Description:  unlock any instruction cache to enable to release

  Arguments:    num  - specify number of datablock to unlock.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osUnlockdownICache( u32 num )
{
        mrc     p15, 0, r3, c9, c0, 1
        and     r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK
        subs    r3, r3, r0
        movmi   r3, #0
        mcr     p15, 0, r3, c9, c0, 1
        bx      lr
}

#else // SDK_ARM11

/*---------------------------------------------------------------------------*
  Name:         osPrefetchICacheRange

  Description:  include specified area to instruction cache in advance

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osPrefetchICacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #HW_CACHE_LINE_SIZE - 1

LSYM(1)
        mcr     p15, 0, r0, c7, c13, 1
        add     r0, r0, #HW_CACHE_LINE_SIZE
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osInvalidateInstPrefetchBuffer

  Description:  invalidate instruction prefetch buffer

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateInstPrefetchBuffer( void )
{
        mov     r3, #0
        mcr     p15, 0, r3, c7, c5, 4
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osDoInstMemoryBarrierAll

  Description:  do all Instruction Memory Barrier

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osDoInstMemoryBarrierAll( void )
{
    osStoreDCacheAll();
    osWaitWriteBufferEmpty();
    osInvalidateICacheAll();
    osInvalidateInstPrefetchBuffer();
    osInvalidateBCacheAll();
}

/*---------------------------------------------------------------------------*
  Name:         osDoInstMemoryBarrierRange

  Description:  do Instruction Memory Barrier in specified range

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
void osDoInstMemoryBarrierRange( void* startAddr, u32 nBytes )
{
    osStoreDCacheRange( startAddr, nBytes );
    osWaitWriteBufferEmpty();
    osInvalidateICacheRange( startAddr, nBytes );
    osInvalidateInstPrefetchBuffer();
    osInvalidateBCacheRange( startAddr, nBytes );
}

//===========================================================================
//              BRANCH TARGET ADDRESS CACHE CONTROL
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osEnableBCache

  Description:  enable branch target address cache

  Arguments:    None

  Returns:      previous state
 *---------------------------------------------------------------------------*/
asm u32 osEnableBCache( void )
{
        PRESERVE8

        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        orr     r1, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osDisableBCache

  Description:  disable branch target address cache

  Arguments:    None

  Returns:      previous stats
 *---------------------------------------------------------------------------*/
asm u32 osDisableBCache( void )
{
        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        bic     r1, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osRestoreBCache

  Description:  set state of branch target address cache

  Arguments:    branch target address cache state to be set

  Returns:      previous state
 *---------------------------------------------------------------------------*/
asm u32 osRestoreBCache( u32 state )
{
        //---- 引数処理
        cmp     r0, #0
        moveq   r2, #0
        movne   r2, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE

        mrc     p15, 0, r1, c1, c0, 0
        and     r0, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        bic     r1, r1, #HW_C1_BR_FOLDING_ENABLE | HW_C1_SBR_PREDICT_ENABLE | HW_C1_DBR_PREDICT_ENABLE | HW_C1_RETURN_STACK_ENABLE
        orr     r1, r1, r2
        mcr     p15, 0, r1, c1, c0, 0
        bx      lr
}

//===========================================================================
//              BRANCH TARGET ADDRESS CACHE
//===========================================================================
/*---------------------------------------------------------------------------*
  Name:         osInvalidateBCacheAll

  Description:  invalidate all branch target address cache

  Arguments:    None.

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateBCacheAll( void )
{
        mov     r3, #0
        mcr     p15, 0, r3, c7, c5, 6
        bx      lr
}

/*---------------------------------------------------------------------------*
  Name:         osInvalidateBCacheRange

  Description:  invalidate branch target address cache in specified range

  Arguments:    startAddr     start address
                nBytes        size (in byte)

  Returns:      None.
 *---------------------------------------------------------------------------*/
asm void osInvalidateBCacheRange( void* startAddr, u32 nBytes )
{
        add     r1, r1, r0
        bic     r0, r0, #1

LSYM(1)
        mcr     p15, 0, r0, c7, c5, 7
        add     r0, r0, #2
        cmp     r0, r1
        blt     BSYM(1)
        bx      lr
}

#endif // SDK_ARM11


#include <brom/codereset.h>