/*---------------------------------------------------------------------------*
  Project:  CtrBrom - library - init
  File:     crt0_ne1.c

  Copyright 2008 Nintendo.  All rights reserved.

  These coded instructions, statements, and computer programs contain
  proprietary information of Nintendo of America Inc. and/or Nintendo
  Company Ltd., and are protected by Federal copyright law.  They may
  not be disclosed to third parties or copied or duplicated in any form,
  in whole or in part, without the prior written consent of Nintendo.

  $Date::            $
  $Rev$
  $Author$
 *---------------------------------------------------------------------------*/
#include <brom/code32.h>
#include <brom/os.h>


/*---------------------------------------------------------------------------*
  Name:         i_stupInitDDR2

  Description:  Initialize DDR2 for NE1-TBoard

  Arguments:    None

  Returns:      None
 *---------------------------------------------------------------------------*/
asm void i_stupInitDDR2( void )
{
    INASM_EXTERN( i_osWaitCpuCycles )

	mov	r3, lr

	ldr	r0, =HW_NE1EXBUS_REG

	ldr	r1, =0x0000004A
	str	r1, [r0, #REG_EXBUS_PCS0_OFFSET]

	ldr	r1, =0x08000049
	str	r1, [r0, #REG_EXBUS_PCS1_OFFSET]

	ldr	r1, =0x0600004E
	str	r1, [r0, #REG_EXBUS_PCS2_OFFSET]

	ldr	r1, =0x0400004B
	str	r1, [r0, #REG_EXBUS_PCS3_OFFSET]

	ldr	r1, =0x1000004A
	str	r1, [r0, #REG_EXBUS_PCS4_OFFSET]

	ldr	r1, =0x1400000A
	str	r1, [r0, #REG_EXBUS_PCS5_OFFSET]

	ldr	r1, =0x10388E7F
	str	r1, [r0, #REG_EXBUS_PCS0TIM_OFFSET]

	ldr	r1, =0x10388E7E
	str	r1, [r0, #REG_EXBUS_PCS1TIM_OFFSET]

	ldr	r1, =0x10388E7E
	str	r1, [r0, #REG_EXBUS_PCS2TIM_OFFSET]

	ldr	r1, =0x10388E7F
	str	r1, [r0, #REG_EXBUS_PCS3TIM_OFFSET]

	ldr	r1, =0x10388E7E
	str	r1, [r0, #REG_EXBUS_PCS4TIM_OFFSET]

	ldr	r1, =0x10388E7E
	str	r1, [r0, #REG_EXBUS_PCS5TIM_OFFSET]

	// Check device version
	// ES1.0 : go to ContinueBoot
	ldr	r0, =HW_NE1SYS_REG
	ldr	r1, [r0, #REG_SYS_VERSION_OFFSET]
	ldr	r2, =0x00000001
	cmp	r1, r2
	bne	ContinueBoot

	// Check reset cause
	// Software reset : ContinueBoot
	ldr	r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]
	and	r1, r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
	mov	r2, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
	cmp	r1, r2
	beq	ContinueBoot

	// Check BTM
	// DSW1_7 OFF : ContinueBoot
	ldr	r1, [r0, #REG_SYS_BOOT_ID_OFFSET]
	and	r1, r1, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK
	mov	r2, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK
	cmp	r1, r2
	bne	ContinueBoot

	// Change WTOP normal mode setting
	ldr	r1, [r0, #REG_SYS_WTOP_MODE_OFFSET]
	and	r1, r1, #0xFFFFFFFE
	str	r1, [r0, #REG_SYS_WTOP_MODE_OFFSET]

	// Do Software reset
	mov	r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_MASK
	str	r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]

wait_reset
    b   wait_reset

ContinueBoot
	// Clear Software reset
	mov	r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK
	str	r1, [r0, #REG_SYS_RESET_STATUS_OFFSET]

    // Setup DDR2
	ldr	r0, =HW_NE1DDR2_REG

	ldr	r1, =0x30022123
	str	r1, [r0, #REG_MIF_SDC_CFG2_OFFSET]

	mov	r1, #0x1
	str	r1, [r0, #REG_MIF_DLL_CFG_OFFSET]

	mov	r1, #0x20
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

// wait 480ns
	ldr	r0, =__cpp(OS_USEC_TO_TICK32(10))
    bl  i_osWaitCpuCycles

	ldr	r0, =HW_NE1DDR2_REG

	ldr	r1, =0x10000004
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x00010002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x00018002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x00008002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x1D480002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x10000004
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	mov	r1, #0x1
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	mov	r1, #0x1
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

// wait 1080ns
	ldr	r0, =__cpp(OS_USEC_TO_TICK32(10))
    bl  i_osWaitCpuCycles

	ldr	r0, =HW_NE1DDR2_REG

	ldr	r1, =0x19480002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x01308002
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	mov	r1, #0x100
	str	r1, [r0, #REG_MIF_INIT_OFFSET]

	ldr	r1, =0x1485A912
	str	r1, [r0, #REG_MIF_SDC_CFG1_OFFSET]

	ldr	r1, =0x00000121
	str	r1, [r0, #REG_MIF_REF_CFG_OFFSET]

	mov	lr, r3
    bx  lr
}