mirror of
https://github.com/rvtr/ctr_firmware.git
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NE1用ROM生成ルールを追加。
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@191 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima
parent
9abe3a4b0c
commit
e544a75616
403
trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c
Normal file
403
trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c
Normal file
@ -0,0 +1,403 @@
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/*---------------------------------------------------------------------------*
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Project: CtrBrom - library - init
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File: crt0_secure.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/os.h>
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#define STUPi_HW_DTCM |Image$$DTCM$$Base|
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void stupInitMMUTable( void );
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/*---------------------------------------------------------------------------*
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Name: i_stupStartHandler
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Description: start handler
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Arguments: None
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Returns: None.
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*---------------------------------------------------------------------------*/
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asm void i_stupStartHandler( void )
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{
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PRESERVE8
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INASM_EXTERN( stupInitExceptions )
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INASM_EXTERN( i_osFinalize )
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//---- initialize stack pointer
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// SVC mode
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mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr sp, =HW_BROM_SVC_STACK_END
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// IRQ mode
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mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr r0, =HW_BROM_IRQ_STACK_END
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mov sp, r0
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// System mode
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mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr r0, =HW_BROM_SYS_STACK_END
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mov sp, r0
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//---- initialize exceptions
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bl stupInitExceptions
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//---- disable cp15
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bl stupDisableCP15
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#ifdef SDK_NE1EMU
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//---- initialize DDR2
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INASM_EXTERN( i_stupInitDDR2 )
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bl i_stupInitDDR2
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#endif // SDK_NE1EMU
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//---- clear wram
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// 4KB
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mov r0, #0
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ldr r1, =HW_AXI_WRAM_SHARED_SYS
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ldr r2, =HW_EXCP_VENEER_BUF
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sub r2, r2, r1
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bl i_stupCpuClear32
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ldr r1, =HW_EXCP_VENEER_BUF_END
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rsb r2, r1, #HW_AXI_WRAM_END
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bl i_stupCpuClear32
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// os finalize
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bl i_osFinalize
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terminate
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b terminate
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitMMU
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Description: Initialize MMU
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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asm void stupInitMMU( void )
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{
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stmfd sp!, {r4, lr} // stack requires 8byte alignment
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// Invalidate ITLB DTLB
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mov r0, #0
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mcr p15, 0, r0, c8, c5, 0
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mcr p15, 0, r0, c8, c6, 0
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ldr r0, =HW_BROM_MMU_T1
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mov r2, #HW_C2_V5_T1_BOUNBARY_16KB
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// MMU L1 Table Base
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ldr r1, =HW_C2_0_T1_BASE_MASK_MIN
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mov r1, r1, ASR r2
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and r1 ,r1, r0
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orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
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| HW_C2_WALK_ON_SHARED_MEM
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mcr p15, 0, r1, c2, c0, 0
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ldr r1, =HW_C2_1_T1_BASE_MASK
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and r1 ,r1, r0
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orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
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| HW_C2_WALK_ON_SHARED_MEM
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mcr p15, 0, r1, c2, c0, 1
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// MMU L1 Table Boundary
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mcr p15, 0, r2, c2, c0, 2
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// Domain Access Permission
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#if 1 // miya
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ldr r1, =0x00000001
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#else
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ldr r1, = HW_C3_DOMAIN_PACK( \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER \
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)
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#endif
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mcr p15, 0, r1, c3, c0, 0
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// VFP Access Permission
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ldr r1, =HW_C1_VFP_AP_PACK( \
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HW_C1_AP_PRIV, HW_C1_AP_PRIV )
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mcr p15, 0, r1, c1, c0, 2
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// Initialize MMU Table
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bl __cpp(stupInitMMUTable)
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ldmfd sp!, {r4, pc} // stack requires 8byte alignment
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitMMUTable
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Description: Initialize MMU Table
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void stupInitMMUTable( void )
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{
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u32* t1Base = (u32* )HW_BROM_MMU_T1;
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u32* t2Base = (u32* )HW_BROM_MMU_T2;
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u32* table;
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u32 paddr = (u32 )NULL;
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// Initialize as Access Prohibition
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table = t1Base;
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for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; )
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{
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_APX_NA,
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HW_MMU6_T1_RGT_STRONG_ORDER,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN,
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0);
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}
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table = t2Base;
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for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; )
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{
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*table++ = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_NA,
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HW_MMU6_T2_LP_RGT_STRONG_ORDER,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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HW_MMU6_T2_SP_XN);
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}
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// Main Memory Region (128MB cached)
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paddr = HW_MAIN_MEM;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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while ( paddr < HW_MAIN_MEM_END )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_L1C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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#ifndef SDK_MG20EMU
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// MG20には拡張メインメモリは無い
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while ( paddr < HW_MAIN_MEM_EX_END )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_ALL,
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HW_MMU6_T1_RGT_L1C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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#else // SDK_MG20EMU
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// for AXI-WRAM & DSP-WRAM Emulation
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paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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while ( paddr < HW_MAIN_MEM_END )
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{
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_L1C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN,
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0);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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#endif // SDK_MG20EMU
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// IO Registers Region (16MB)
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paddr = HW_IOREG;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_SHARED_DEV,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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// MPCore Registers Region (1MB)
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paddr = HW_MPCORE_REG;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_NSHARED_DEV,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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HW_MMU6_T1_XN,
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0);
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// VRAM Region (4MB cached)
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paddr = HW_VRAM;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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while ( paddr < HW_VRAM_END )
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{
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_L1C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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HW_MMU6_T1_SHARED,
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HW_MMU6_T1_XN,
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0);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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#ifdef SDK_NE1EMU
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// NE1-TB DDR2 Registers Region (1MB)
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paddr = HW_NE1DDR2_REG;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_NSHARED_DEV,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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HW_MMU6_T1_XN,
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0);
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#endif // SDK_NE1EMU
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// AXI-WRAM & DSP-WRAM Region (1MB cached & uncached)
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paddr = HW_DSP_WRAM;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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*table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 );
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// T2 for Page
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table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE];
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while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) )
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{
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*table++ = HW_MMU6_T2_LP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_LP_RGT_L1C_WB_WA,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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HW_MMU6_T2_LP_XN);
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paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
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}
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while ( paddr < HW_BROM_MMU_TBL )
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{
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*table++ = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_SP_RGT_L1C_WB_WA,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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HW_MMU6_T2_SP_XN);
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paddr += HW_MMU6_T2_SP_SIZE;
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}
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// HW_BROM_MMU_TBL
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while ( paddr < HW_BROM_MMU_TBL_END )
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{
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*table++ = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_SP_RGT_SHARED_DEV,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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HW_MMU6_T2_SP_XN);
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paddr += HW_MMU6_T2_SP_SIZE;
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}
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// HW_AXI_WRAM_SHARED
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while ( paddr < HW_AXI_WRAM_SHARED_END )
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{
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*table++ = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_SP_RGT_SHARED_DEV,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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FALSE); // for exception veneer
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paddr += HW_MMU6_T2_SP_SIZE;
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}
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// Coarse page is 1KB boundary
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t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
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// BROM Region (64KBx2 cached)
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paddr = HW_BROM_IMG;
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table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
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*table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 );
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// T2 for Page
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table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE];
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while ( paddr != HW_BROM_END )
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{
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*table++ = HW_MMU6_T2_LP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_LP_RGT_L1C_WB_WA,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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FALSE);
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paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
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}
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// Coarse page is 1KB boundary
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t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
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}
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#include <./../../../../libraries/init/ARM11/crt0_misc.c>
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@ -84,7 +84,11 @@ $(BINDIR)/$(TARGET_BIN_BASENAME).sbin: $(BINDIR)/$(TARGET_BIN_BASENAME).axf $(BI
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# .padbin
|
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$(BINDIR)/$(TARGET_BIN_BASENAME).padbin: $(BINDIR)/$(TARGET_BIN_BASENAME).sbin
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objcopy -I binary -O binary --pad-to $(EXO_SBIN_SIZE) --gap-fill 0x00 $< $@
|
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|
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ifeq ($(CTR_PLATFORM),NE1EMU)
|
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ifeq ($(CTR_PROC),ARM11)
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cat $@ $@ > $(basename $@).ne1.padbin
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endif
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endif
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# .txt
|
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$(BINDIR)/$(TARGET_BIN_BASENAME).txt: $(BINDIR)/$(TARGET_BIN_BASENAME).axf
|
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|
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