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A9-PU初期化。

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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@45 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-01 05:28:25 +00:00
parent 93b55e83bb
commit d483e939bb
7 changed files with 466 additions and 35 deletions
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4
trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c
View File

@ -34,8 +34,8 @@ ASM void __user_initial_stackheap( void )
INASM_EXTERN( |Image$$ZI$$ZI$$Limit| )
ldr r0, =|Image$$ZI$$ZI$$Limit| // heap base
ldr r1, =HW_PRV_WRAM_IRQ_STACK_END
sub r1, r1, #HW_IRQ_STACK_SIZE
ldr r1, =HW_BROM_IRQ_STACK_END
sub r1, r1, #HW_BROM_IRQ_STACK_SIZE
mov r2, r0
mov r3, r0

184
trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c
View File

@ -17,7 +17,9 @@
#include <brom/os.h>
//#include <brom/mi.h>
//#define BROM_ENABLE_BOOTROM_WRITE
#define BROM_ENABLE_BOOTROM_WRITE
#define STUPi_HW_DTCM |Image$$DTCM$$Base|
/*---------------------------------------------------------------------------*
Name: STUPi_StartHandler
@ -32,7 +34,7 @@ asm void STUPi_StartHandler( void )
{
PRESERVE8
INASM_EXTERN( SWI_TableEnd )
INASM_EXTERN( STUPi_HW_DTCM )
INASM_EXTERN( BromSpMain )
INASM_EXTERN( main )
@ -45,6 +47,9 @@ asm void STUPi_StartHandler( void )
#endif // BROM_ENABLE_BOOTROM_WRITE
//---- initialize cp15
bl STUPi_InitCP15
//---- initialize stack pointer
// SVC mode
mov r0, #HW_PSR_SVC_MODE
@ -64,6 +69,12 @@ asm void STUPi_StartHandler( void )
mov sp, r0
//---- clear wram
// DTCM (16KB)
mov r0, #0
ldr r1, =STUPi_HW_DTCM
mov r2, #HW_DTCM_SIZE
bl STUPi_CpuClear32
// 1KB
mov r0, #0
ldr r1, =HW_PRV_WRAM_END
@ -84,5 +95,174 @@ terminate
b terminate
}
//-----------------------------------------------------------------------
// システム制御コプロセッサ 初期化
//-----------------------------------------------------------------------
asm void STUPi_InitCP15(void)
{
// プロテクションユニット/キャッシュ/TCM ディセーブル
mrc p15, 0, r0, c1, c0, 0
ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \
| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
| HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \
| HW_C1_LD_INTERWORK_DISABLE \
| HW_C1_PROTECT_UNIT_ENABLE
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
// キャッシュ無効化
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ
mcr p15, 0, r0, c7, c6, 0 // データキャッシュ
// ライトバッファ エンプティ待ち
mcr p15, 0, r0, c7, c10, 4
/*
; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA
; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW
; Region 3: RESERVED: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW
; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO
; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW
*/
#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE)
#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0
#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7))
#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28))
#define NA 0
#define RW 1
#define RO 5
//
// メモリリージョン初期化
//
//---- メインメモリ
SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB )
SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB )
//---- I/Oレジスタ & VRAM & AXI-WRAM
SET_PROTECTION_A( c1, HW_IOREG, 256MB )
SET_PROTECTION_B( c1, HW_IOREG, 256MB )
//---- PRV_WRAM
SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB )
SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB )
//---- 予約
SET_PROTECTION_A( c3, HW_MAIN_MEM_END, 4KB )
SET_PROTECTION_B( c3, HW_MAIN_MEM_END, 4KB )
//---- データ TCM
ldr r0, =STUPi_HW_DTCM
orr r0, r0, #HW_C6_PR_16KB
orr r0, r0, #HW_C6_PR_ENABLE
SET_PROTECTION_B( c4, HW_DTCM, 16KB )
//---- 命令 TCM
// データ TCM より優先が高い
SET_PROTECTION_A( c5, HW_ITCM, 32KB )
SET_PROTECTION_B( c5, HW_ITCM, 32KB )
//---- BIOS
SET_PROTECTION_A( c6, HW_BIOS, 64KB )
SET_PROTECTION_B( c6, HW_BIOS, 64KB )
//---- SHARED CPU 間通信ワーク領域
SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB )
SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB )
//
// 命令ＴＣＭ 設定
//
mov r0, #HW_C9_TCMR_128MB
mcr p15, 0, r0, c9, c1, 1
//
// データＴＣＭ 設定
//
ldr r0, =STUPi_HW_DTCM
orr r0, r0, #HW_C9_TCMR_16KB
mcr p15, 0, r0, c9, c1, 0
//
// 命令キャッシュ イネーブル (リージョン設定)
// 6: BIOS
//
mov r0, #REGION_BIT(0,0,0,0,0,0,1,0)
mcr p15, 0, r0, c2, c0, 1
//
// データキャッシュ イネーブル (リージョン設定)
// 0: HW_MAIN_MEM
// 2: PRV_WRAM
// 6: BIOS
//
mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
mcr p15, 0, r0, c2, c0, 0
//
// ライトバッファ イネーブル(リージョン設定)
// 0: HW_MAIN_MEM
// 2: PRV_WRAM
// 6: BIOS
//
mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
mcr p15, 0, r0, c3, c0, 0
//
// 命令アクセス許可 (リージョン設定)
// MAIN_MEM : NA
// IO_AXIRAM : NA
// PRV_WRAM : NA
// DTCM : NA
// ITCM : RO
// BIOS : RO
// SHARED : NA
//
ldr r0, =REGION_ACC(NA,NA,NA,NA,NA,RO,RO,NA)
mcr p15, 0, r0, c5, c0, 3
//
// データアクセス許可（リージョン設定）
// MAIN_MEM : RW
// IO_AXIRAM : RW
// PRV_WRAM : NA
// DTCM : RW
// ITCM : RW
// BIOS : RO
// SHARED : NA
//
#ifdef BROM_ENABLE_BOOTROM_WRITE
ldr r0, =REGION_ACC(RW,RW,NA,NA,RW,RW,RW,NA)
#else // BROM_ENABLE_BOOTROM_WRITE
ldr r0, =REGION_ACC(RW,RW,NA,NA,RW,RW,RO,NA)
#endif // BROM_ENABLE_BOOTROM_WRITE
mcr p15, 0, r0, c5, c0, 2
//
// システム制御コプロセッサ マスター設定
//
mrc p15, 0, r0, c1, c0, 0
ldr r1,=HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE | HW_C1_CACHE_ROUND_ROBIN \
| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
| HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \
| HW_C1_PROTECT_UNIT_ENABLE
orr r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
bx lr
LTORG
EXPORT STUPi_InitCP15_End
STUPi_InitCP15_End
}
#include <./crt0_misc_sp.c>

18
trunk/bootrom/include/brom/hw/common/mmap_shared.h
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@ -21,6 +21,24 @@
extern "C" {
#endif
//----------------------------------------------------------------------
// MEMORY MAP of SYSTEM SHARED AREA
//----------------------------------------------------------------------
//
#define HW_AXI_WRAM_SHARED (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE)
#define HW_AXI_WRAM_SHARED_END (HW_MAIN_MEM)
#define HW_AXI_WRAM_SHARED_SIZE (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_USR_SIZE) // 8KB
#define HW_AXI_WRAM_SHARED_USR (HW_AXI_WRAM_SHARED_USR_END - HW_AXI_WRAM_SHARED_USR_SIZE)
#define HW_AXI_WRAM_SHARED_USR_END HW_AXI_WRAM_SHARED_END
#define HW_AXI_WRAM_SHARED_USR_SIZE 0x1000 // 4KB
#define HW_AXI_WRAM_SHARED_SYS (HW_AXI_WRAM_SHARED_SYS_END - HW_AXI_WRAM_SHARED_SIZE)
#define HW_AXI_WRAM_SHARED_SYS_END HW_AXI_WRAM_SHARED_USR
#define HW_AXI_WRAM_SHARED_SYS_SIZE 0x1000 // 4KB
#ifdef __cplusplus
} /* extern "C" */
#endif

105
trunk/bootrom/include/brom/specfiles/ARM11-TEG.ldscript.template Normal file
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@ -0,0 +1,105 @@
//
// Scatter Loading Description File Templete
//
#define SDK_ASM
#include <brom/hw/ARM11/mmap_brom.h>
LOAD_NORMAL HW_BROM_NML HW_BROM_NML_SIZE
{
STUP_ENTRY +0
{
*crt0.*o (.emb_text, +FIRST)
}
NML_RO +0
{
*libos*.brom*.a (:gdef:OSi_Boot)
*libos*.brom*.a (:gdef:OSi_BootCore)
*libos*.brom*.a (:gdef:OSi_ClearWorkArea)
*libos*.brom*.a (:gdef:OS_DisableInterrupts)
*libos*.brom*.a (:gdef:OS_RestoreInterrupts)
*libmi*.brom*.a (+RO)
*libswi*.brom*.a (+RO)
*libpxi*.brom*.a (+RO)
*libacsign*.brom*.a (+RO)
* (Veneer$$Code)
}
RO +0
{
* (+RO)
}
}
LOAD_SECURE HW_BROM_SEC HW_BROM_SEC_SIZE
{
SEC_RO +0
{
*crt0_secure_sp.o (.emb_text, +FIRST)
#ifdef BROM_DEF_LINK_SCATLD
*crt0scat.*o (.emb_text)
__main.o (+RO)
* (Region$$Table)
* (ZISection$$$Table)
* (!!!scatter)
* (!!handler_copy)
* (!!handler_zi)
* (x$fpl$fpinit)
#endif // BROM_DEF_LINK_SCATLD
*main.o (+RO)
*libos*.brom*.a (:gdef:OSi_KeyBinPack)
*libpad*.brom*.a (:gdef:PAD_Read)
*libpad*.brom*.a (:gdef:PAD_DetectFold)
*libmi*.brom*.a (:gdef:MI_Init)
*libmi*.brom*.a (:gdef:MI_ReadStream)
*libmi*.brom*.a (:gdef:MIi_PreMappingWram)
*libmi*.brom*.a (:gdef:MIi_MappingWramForARM9)
*libmi*.brom*.a (:gdef:MIi_MappingWramForARM7)
*libmi*.brom*.a (i.MIi_AdjustWramMapParam)
*libmi*.brom*.a (:gdef:MIi_SetExDmaArbitration)
*libmi*.brom*.a (:gdef:MIi_SetExDmaYieldCycles)
*libmi*.brom*.a (:gdef:MIi_SetExDmaParams)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecv)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecvCore)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecvAsyncCore)
*libmi*.brom*.a (:gdef:MIi_WaitExDma)
*libmi*.brom*.a (:gdef:MIi_StopExDma)
*libmi*.brom*.a (:gdef:MIi_StopExDmaAsync)
*libpxi*.brom*.a (:gdef:PXI_InitFifoBROM)
*libpxi*.brom*.a (:gdef:PXI_SendDataByFifo)
*libpxi*.brom*.a (:gdef:PXI_RecvDataByFifo)
*libpxi*.brom*.a (:gdef:PXI_SendStream)
*libpxi*.brom*.a (:gdef:PXI_RecvStream)
*libpxi*.brom*.a (:gdef:PXIi_InitReadStream)
*libpxi*.brom*.a (:gdef:PXIi_ReadByteStream)
*libpxi*.brom*.a (:gdef:PXIi_ReadWordStream)
*libpxi*.brom*.a (:gdef:PXIi_TerminateReadStream)
*libos*.brom*.a (+RO)
*libnvram*.brom*.a (+RO)
*libromsd*.brom*.a (+RO)
*libgcd*.brom*.a (+RO)
*libpm*.brom*.a (+RO)
*libaes*.brom*.a (+RO)
}
RW HW_BROM_WRAM HW_BROM_WRAM_SIZE
{
* (+RW)
}
ZI +0
{
* (+ZI)
}
BUF_OVER_BARRIER HW_BROM_WRAM_END EMPTY 0
{
}
TO_FIRM HW_BROM_TO_FIRM_BUF EMPTY HW_BROM_TO_FIRM_BUF_SIZE
{
}
}

133
trunk/bootrom/include/brom/specfiles/ARM9-TEG.ldscript.template Normal file
View File

@ -0,0 +1,133 @@
//
// Scatter Loading Description File Templete
//
#define SDK_ASM
#include <brom/hw/ARM9/mmap_brom.h>
LOAD_NORMAL HW_BROM_NML HW_BROM_NML_SIZE
{
STUP_ENTRY +0
{
*crt0.*o (.emb_text, +FIRST)
}
NML_RO +0
{
*libos*.brom*.a (:gdef:OSi_Boot)
*libos*.brom*.a (:gdef:OSi_BootCore)
*libos*.brom*.a (:gdef:OSi_ClearWorkArea)
*libos*.brom*.a (:gdef:OS_DisableInterrupts)
*libos*.brom*.a (:gdef:OS_RestoreInterrupts)
*libmi*.brom*.a (+RO)
*libswi*.brom*.a (+RO)
*libpxi*.brom*.a (+RO)
*libacsign*.brom*.a (+RO)
* (Veneer$$Code)
}
RO +0
{
* (+RO)
}
SVC_RW HW_ITCM_END EMPTY 0
{
}
#ifndef BROM_DEF_LINK_SCATLD
DTCM HW_DTCM EMPTY 0
{
}
#else // BROM_DEF_LINK_SCATLD
ITCM (HW_ITCM + 0x100) (HW_ITCM_SIZE - 0x100)
{
* (.itcm)
* (.itcm.bss)
}
DTCM HW_DTCM HW_DTCM_SIZE
{
* (.dtcm)
* (.dtcm.bss)
}
#endif // BROM_DEF_LINK_SCATLD
}
LOAD_SECURE HW_BROM_SEC HW_BROM_SEC_SIZE
{
SEC_RO +0
{
*crt0_secure.o (.emb_text, +FIRST)
#ifdef BROM_DEF_LINK_SCATLD
*crt0scat.*o (.emb_text)
__main.o (+RO)
* (Region$$Table)
* (ZISection$$$Table)
* (!!!scatter)
* (!!handler_copy)
* (!!handler_zi)
* (x$fpl$fpinit)
#endif // BROM_DEF_LINK_SCATLD
*main.o (+RO)
*libos*.brom*.a (:gdef:OSi_KeyBinPack)
*libpad*.brom*.a (:gdef:PAD_Read)
*libpad*.brom*.a (:gdef:PAD_DetectFold)
*libmi*.brom*.a (:gdef:MI_Init)
*libmi*.brom*.a (:gdef:MI_ReadStream)
*libmi*.brom*.a (:gdef:MIi_PreMappingWram)
*libmi*.brom*.a (:gdef:MIi_MappingWramForARM9)
*libmi*.brom*.a (:gdef:MIi_MappingWramForARM7)
*libmi*.brom*.a (i.MIi_AdjustWramMapParam)
*libmi*.brom*.a (:gdef:MIi_SetExDmaArbitration)
*libmi*.brom*.a (:gdef:MIi_SetExDmaYieldCycles)
*libmi*.brom*.a (:gdef:MIi_SetExDmaParams)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecv)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecvCore)
*libmi*.brom*.a (:gdef:MIi_ExDmaRecvAsyncCore)
*libmi*.brom*.a (:gdef:MIi_WaitExDma)
*libmi*.brom*.a (:gdef:MIi_StopExDma)
*libmi*.brom*.a (:gdef:MIi_StopExDmaAsync)
*libpxi*.brom*.a (:gdef:PXI_InitFifoBROM)
*libpxi*.brom*.a (:gdef:PXI_SendDataByFifo)
*libpxi*.brom*.a (:gdef:PXI_RecvDataByFifo)
*libpxi*.brom*.a (:gdef:PXI_SendStream)
*libpxi*.brom*.a (:gdef:PXI_RecvStream)
*libpxi*.brom*.a (:gdef:PXIi_InitReadStream)
*libpxi*.brom*.a (:gdef:PXIi_ReadByteStream)
*libpxi*.brom*.a (:gdef:PXIi_ReadWordStream)
*libpxi*.brom*.a (:gdef:PXIi_TerminateReadStream)
*libos*.brom*.a (+RO)
*libnvram*.brom*.a (+RO)
*libromsd*.brom*.a (+RO)
*libgcd*.brom*.a (+RO)
*libpm*.brom*.a (+RO)
*libprint_hex*.brom*.a (+RO)
}
RW HW_BROM_WRAM HW_BROM_WRAM_SIZE
{
* (+RW)
}
ZI +0
{
* (+ZI)
}
BUF_OVER_BARRIER HW_BROM_WRAM_END EMPTY 0
{
}
TO_FIRM HW_BROM_TO_FIRM_BUF EMPTY HW_BROM_TO_FIRM_BUF_SIZE
{
}
}

31
trunk/include/ctr/hw/ARM11/mmap_global.h
View File

@ -27,31 +27,26 @@ extern "C" {
//----------------------------- MAIN
#define HW_MAIN_MEM 0x20000000
#define HW_MAIN_MEM_SIZE 0x04000000
#define HW_MAIN_MEM_EX_SIZE 0x08000000
#define HW_MAIN_MEM_EX HW_MAIN_MEM_END
#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE)
#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE)
#define HW_MAIN_MEM_SIZE 0x04000000 // 64MB
#define HW_MAIN_MEM_EX_SIZE 0x08000000 // 128MB
//----------------------------- AXI-WRAM
#define HW_AXI_WRAM 0x1ff80000
#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE)
#define HW_AXI_WRAM_SIZE 0x80000
#define HW_AXI_WRAM_SIZE 0x80000 // 512KB
//----------------------------- DSP-WRAM
//----------------------------- DSP-WRAM (only DMAC2)
#define HW_DSP_WRAM 0x1ff00000
#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE)
#define HW_DSP_WRAM_SIZE 0x80000
#define HW_DSP_WRAM_SIZE 0x80000 // 512KB
//----------------------------- VRAM
#define HW_VRAM 0x18000000
#define HW_VRAM_END (HW_VRAM + HW_VRAM_SIZE)
#define HW_VRAM_SIZE 0x400000
//----------------------------- Private WRAM
#define HW_PRV_WRAM 0x08000000
#define HW_PRV_WRAM_END (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
#define HW_PRV_WRAM_SIZE 0x100000
#define HW_VRAM_SIZE 0x400000 // 4MB
//----------------------------- IOs
#define HW_IOREG 0x10000000
@ -68,19 +63,19 @@ extern "C" {
#define HW_AHBML_REG_END (HW_AHBML_REG + HW_AHBML_REG_SIZE)
#define HW_GPU_REG_END (HW_GPU_REG + HW_GPU_REG_SIZE)
#define HW_MPCORE_REG_REG (HW_MPCORE_REG + HW_MPCORE_REG_SIZE)
#define HW_AHBP_REG_SIZE 0x80000
#define HW_APB_REG_SIZE 0x100000
#define HW_AHBML_REG_SIZE 0x40000
#define HW_GPU_REG_SIZE 0x100000
#define HW_MPCORE_REG_SIZE 0x20000
#define HW_AHBP_REG_SIZE 0x80000 // 512KB
#define HW_APB_REG_SIZE 0x100000 // 1MB
#define HW_AHBML_REG_SIZE 0x40000 // 256KB
#define HW_GPU_REG_SIZE 0x100000 // 1MB
#define HW_MPCORE_REG_SIZE 0x20000 // 128KB
//----------------------------- System ROM
#define HW_BIOS 0xffff0000
#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
#define HW_BIOS_EX HW_BIOS_END
#define HW_BIOS_EX_END (HW_BIOS_EX + HW_BIOS_EX_SIZE)
#define HW_BIOS_SIZE 0x00008000
#define HW_BIOS_EX_SIZE 0x00008000
#define HW_BIOS_SIZE 0x8000 // 32KB
#define HW_BIOS_EX_SIZE 0x10000 // 64KB
#define HW_RESET_VECTOR HW_BIOS

26
trunk/include/ctr/hw/ARM9/mmap_global.h
View File

@ -29,41 +29,41 @@ extern "C" {
//----------------------------- ITCM
#define HW_ITCM_IMAGE 0x01000000
#define HW_ITCM 0x01ff8000
#define HW_ITCM_SIZE 0x8000
#define HW_ITCM_SIZE 0x8000 // 32KB
#define HW_ITCM_END (HW_ITCM + HW_ITCM_SIZE)
//----------------------------- DTCM
#define HW_DTCM (HW_BIOS - HW_DTCM_SIZE*2)
#define HW_DTCM (HW_BIOS - HW_DTCM_SIZE*4)
#define HW_DTCM_END (HW_DTCM + HW_DTCM_SIZE)
#define HW_DTCM_SIZE 0x4000
#define HW_DTCM_SIZE 0x4000 // 16KB
//----------------------------- MAIN
#define HW_MAIN_MEM 0x20000000
#define HW_MAIN_MEM_SIZE 0x04000000
#define HW_MAIN_MEM_EX_SIZE 0x08000000
#define HW_MAIN_MEM_EX HW_MAIN_MEM_END
#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE)
#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE)
#define HW_MAIN_MEM_SIZE 0x04000000 // 64MB
#define HW_MAIN_MEM_EX_SIZE 0x08000000 // 128MB
//----------------------------- AXI-WRAM
#define HW_AXI_WRAM 0x1ff80000
#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE)
#define HW_AXI_WRAM_SIZE 0x80000
#define HW_AXI_WRAM_SIZE 0x80000 // 512KB
//----------------------------- DSP-WRAM (only DMAC2)
#define HW_DSP_WRAM 0x1ff00000
#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE)
#define HW_DSP_WRAM_SIZE 0x80000
#define HW_DSP_WRAM_SIZE 0x80000 // 512KB
//----------------------------- VRAM
#define HW_VRAM 0x18000000
#define HW_VRAM_END (HW_VRAM + HW_VRAM_SIZE)
#define HW_VRAM_SIZE 0x400000
#define HW_VRAM_SIZE 0x400000 // 4MB
//----------------------------- Private WRAM
#define HW_PRV_WRAM 0x08000000
#define HW_PRV_WRAM_END (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
#define HW_PRV_WRAM_SIZE 0x100000
#define HW_PRV_WRAM_SIZE 0x100000 // 1MB
//----------------------------- IOs
#define HW_IOREG 0x10000000
@ -74,16 +74,16 @@ extern "C" {
#define HW_AHBP_REG (HW_IOREG + 0x00100000)
#define HW_PRV_REG_END (HW_PRV_REG + HW_PRV_REG_SIZE)
#define HW_AHBP_REG_END (HW_AHBP_REG + HW_AHBP_REG_SIZE)
#define HW_PRV_REG_SIZE 0x20000
#define HW_AHBP_REG_SIZE 0x80000
#define HW_PRV_REG_SIZE 0x20000 // 128MB
#define HW_AHBP_REG_SIZE 0x80000 // 512MB
//----------------------------- System ROM
#define HW_BIOS 0xffff0000
#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
#define HW_BIOS_EX HW_BIOS_END
#define HW_BIOS_EX_END (HW_BIOS_EX + HW_BIOS_EX_SIZE)
#define HW_BIOS_SIZE 0x00008000
#define HW_BIOS_EX_SIZE 0x00008000
#define HW_BIOS_SIZE 0x8000 // 32KB
#define HW_BIOS_EX_SIZE 0x10000 // 64KB
#define HW_RESET_VECTOR HW_BIOS