rvtr/ctr_firmware
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SMPモードへ初期化。

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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@217 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2009-01-27 07:28:48 +00:00
parent 5d0ced34ea
commit d08f115de8
2 changed files with 13 additions and 6 deletions
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13
trunk/bootrom/build/libraries/init/ARM11/crt0_mmu.c
View File

@ -51,8 +51,7 @@ asm void stupDisableCP15( void )
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_SMP_MODE \
| HW_C1_EXCLUSIVE_L1C_L2C \
ldr r1, =HW_C1_EXCLUSIVE_L1C_L2C \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \
@ -83,11 +82,19 @@ asm void stupDisableCP15( void )
*---------------------------------------------------------------------------*/
asm void stupEnableCP15( void )
{
//
// Snoop Control Unit
//
ldr r3, =REG_SCU_CNT_ADDR
ldr r0, [r3]
orr r0, r0, #REG_OS_SCU_CNT_E_MASK
str r0, [r3]
//
// Auxiliary Control
//
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_AMP_MODE \
ldr r1, =HW_C1_SMP_MODE \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \

6
trunk/include/ctr/hw/ARM11/arm11_reg.h
View File

@ -88,7 +88,7 @@ extern "C" {
#define HW_C1_UNALIGN_ACCESS_ENABLE 0x00400000 // Unaligned data and mixed-endian data access enable
#define HW_C1_LD_INTERWORK_DISABLE 0x00008000 // Loads to PC do not set the T bit (ARMv4 behavior)
#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // High exception vectors selected (CTR default)
#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // High exception vectors selected
#define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // Low exception vectors selected
#define HW_C1_IC_ENABLE 0x00001000 // Instruction Cache enabled
#define HW_C1_DC_ENABLE 0x00000004 // Data Cache enabled
@ -105,8 +105,8 @@ extern "C" {
// Register 1.1 : Auxiliary Control
#define HW_C1_SMP_MODE 0x00000020 // SMP mode (Invalid for CTR)
#define HW_C1_AMP_MODE 0x00000000 // AMP mode (Invalid for CTR)
#define HW_C1_SMP_MODE 0x00000020 // Symmetric Multi Processing mode
#define HW_C1_AMP_MODE 0x00000000 // Asymmetric Multi Processing mode
#define HW_C1_EXCLUSIVE_L1C_L2C 0x00000010 // L1 and L2 caches are exclusive (Invalid for CTR)
#define HW_C1_BR_FOLDING_ENABLE 0x00000008 // Branch instruction folding enable
#define HW_C1_SBR_PREDICT_ENABLE 0x00000004 // Static branch prediction enable