From b3c5a5343f4bd9085e2b45a37c08184785cbfefa Mon Sep 17 00:00:00 2001 From: nakasima Date: Tue, 2 Dec 2008 04:34:45 +0000 Subject: [PATCH] =?UTF-8?q?MMU=E8=A8=AD=E5=AE=9A=E3=81=AB=E3=81=A6?= =?UTF-8?q?=EF=BC=B3=EF=BC=A8=EF=BC=A1=EF=BC=B2=EF=BC=A5=EF=BC=A4=E9=A0=98?= =?UTF-8?q?=E5=9F=9F=E3=82=92=E8=80=83=E6=85=AE=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@59 b871894f-2f95-9b40-918c-086798483c85 --- .../build/libraries/init/ARM11/crt0_secure.c | 156 +++++++----------- .../include/brom/hw/ARM11/mmap_axi_wram.h | 4 +- 2 files changed, 65 insertions(+), 95 deletions(-) diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c index ef7f3c0..78aadb5 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c @@ -107,6 +107,7 @@ ASM void stupDisableCP15( void ) | HW_C1_FORCE_AP_BIT \ | HW_C1_TEX_CB_REMAP \ | HW_C1_NMFI_FIQ \ + | HW_C1_EXCEPT_VEC_UPPER \ | HW_C1_EXCEPT_BIG_ENDIAN \ | HW_C1_BR_PREDICT_ENABLE \ | HW_C1_LD_INTERWORK_DISABLE \ @@ -176,8 +177,8 @@ ASM void stupEnableCP15( void ) | HW_C1_BR_PREDICT_ENABLE \ | HW_C1_MMU_V6 \ | HW_C1_IC_ENABLE \ - | HW_C1_DC_ENABLE \ - | HW_C1_MMU_ENABLE + | HW_C1_DC_ENABLE \ + | HW_C1_MMU_ENABLE orr r0, r0, r1 @@ -225,12 +226,12 @@ ASM void stupInitMMU( void ) mov r1, r1, ASR r2 and r1 ,r1, r0 orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT - mcr p15, 0, r1, c2, c0, 0 + mcr p15, 0, r1, c2, c0, 0 ldr r1, =HW_C2_1_T1_BASE_MASK and r1 ,r1, r0 orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT - mcr p15, 0, r1, c2, c0, 1 + mcr p15, 0, r1, c2, c0, 1 // MMU L1 Table Boundary @@ -294,7 +295,6 @@ void stupInitMMUTable( void ) u32* t1Base = (u32* )HW_BROM_MMU_T1; u32* t2Base = (u32* )HW_BROM_MMU_T2; - u32* table; u32 paddr = (u32 )NULL; @@ -302,28 +302,28 @@ void stupInitMMUTable( void ) table = &t1Base[0]; for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_APX_NA, - HW_MMU6_T1_RGT_STRONG_ORDER, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_APX_NA, + HW_MMU6_T1_RGT_STRONG_ORDER, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } table = &t2Base[0]; for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_NA, - HW_MMU6_T2_LP_RGT_STRONG_ORDER, - HW_MMU6_T2_GLOBAL, - FALSE, + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_NA, + HW_MMU6_T2_LP_RGT_STRONG_ORDER, + HW_MMU6_T2_GLOBAL, + FALSE, HW_MMU6_T2_SP_XN); - } + } // BROM Region (64KBx2 cached) @@ -335,12 +335,12 @@ void stupInitMMUTable( void ) for ( paddr = HW_BIOS_IMG; paddr < HW_BROM_END; ) { *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_ALL, + paddr, + HW_MMU6_T2_APX_ALL, HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, - HW_MMU6_T2_GLOBAL, - FALSE, - FALSE); + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); paddr += HW_MMU6_T2_LP_ALIAS_SIZE; } // Coarse page is 1KB boundary @@ -353,7 +353,7 @@ void stupInitMMUTable( void ) *table++ = HW_MMU6_T1_SUSEC_PACK( paddr, - HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_APX_ALL, HW_MMU6_T1_RGT_SHARED_DEV, HW_MMU6_T1_GLOBAL, FALSE, @@ -378,21 +378,7 @@ void stupInitMMUTable( void ) table = &t1Base[HW_VRAM/HW_MMU6_T1_SEC_SIZE]; for ( paddr = HW_VRAM; paddr < HW_VRAM_END; ) { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_ALL, - HW_MMU6_T1_RGT_L1L2C_WB_WA, - HW_MMU6_T1_GLOBAL, - FALSE, - FALSE, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // AXI-WRAM & DSP-WRAM Region (1MB cached) - table = &t1Base[HW_DSP_WRAM/HW_MMU6_T1_SEC_SIZE]; - paddr = HW_DSP_WRAM; - *table++ = HW_MMU6_T1_SEC_PACK( + *table++ = HW_MMU6_T1_SEC_PACK( paddr, HW_MMU6_T1_APX_ALL, HW_MMU6_T1_RGT_L1L2C_WB_WA, @@ -400,6 +386,39 @@ void stupInitMMUTable( void ) FALSE, FALSE, 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) + table = &t1Base[HW_DSP_WRAM/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_DSP_WRAM; + *table = HW_MMU6_T1_COURSE_PACK( paddr, 0 ); + // T2 for Page + table = &t2Base[0]; + for ( paddr = HW_DSP_WRAM; paddr < HW_BROM_MMU_TBL; ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_ALL, + HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + for ( paddr = HW_BROM_MMU_TBL; paddr < HW_AXI_WRAM_SHARED_END; ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_ALL, + HW_MMU6_T1_RGT_SHARED_DEV, + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + // Coarse page is 1KB boundary + t2Base += MATH_ROUNDUP(HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); // Main Memory Region (128MB cached) table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE]; @@ -408,7 +427,7 @@ void stupInitMMUTable( void ) *table++ = HW_MMU6_T1_SUSEC_PACK( paddr, - HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_APX_ALL, HW_MMU6_T1_RGT_L1L2C_WB_WA, HW_MMU6_T1_GLOBAL, FALSE, @@ -416,55 +435,6 @@ void stupInitMMUTable( void ) ); paddr += HW_MMU6_T1_SEC_SIZE; } - -#if 0 - -#ifdef MIYA_MMU - *table = HW_MMU6_T1_COURSE_PACK( paddr, 0 ); - // T2 for Page - table = &t2Base[0]; - for ( paddr = HW_MAIN_MEM_LP; paddr < HW_MAIN_MEM_LP_END; ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_ALL, - //miya HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, - HW_MMU6_T2_LP_RGT_L1L2C_NC, - HW_MMU6_T2_GLOBAL, - FALSE, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - for ( paddr = HW_MAIN_MEM_SP_NA; paddr < HW_MAIN_MEM_SP_NA_END; ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T1_APX_ALL, - // miya HW_MMU6_T2_SP_RGT_STRONG_ORDER, - HW_MMU6_T2_SP_RGT_L1L2C_NC, - HW_MMU6_T2_GLOBAL, - FALSE, - FALSE); - paddr += HW_MMU6_T2_SP_SIZE; - } - - for ( paddr = HW_MAIN_MEM_SP; paddr < HW_MAIN_MEM_SP_END; ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_ALL, - // HW_MMU6_T2_SP_RGT_STRONG_ORDER, - HW_MMU6_T2_SP_RGT_L1L2C_NC, - HW_MMU6_T2_GLOBAL, - FALSE, - FALSE); - paddr += HW_MMU6_T2_SP_SIZE; - } - - t2Base += HW_MMU6_T1_CORS_SIZE/sizeof(t2Base[0]); -#endif - -#endif } diff --git a/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h index 7f7de84..ecf52b4 100644 --- a/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h +++ b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h @@ -53,9 +53,9 @@ extern "C" { //------------------------------------- BROM_SYSRV -#define HW_BROM_SYSRV HW_PRV_WRAM +#define HW_BROM_SYSRV HW_AXI_WRAM_SHARED_USR #define HW_BROM_SYSRV_END (HW_BROM_SYSRV + HW_BROM_SYSRV_SIZE) -#define HW_BROM_SYSRV_SIZE 0x1000 // 4KB +#define HW_BROM_SYSRV_SIZE HW_AXI_WRAM_SHARED_USR_SIZE #define HW_BROM_SYSRV_IOFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) #define HW_BROM_SYSRV_IOFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK)