NE1-TB用DDR2レジスタリージョン追加。

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@161 b871894f-2f95-9b40-918c-086798483c85

trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c

@@ -17,7 +17,7 @@
 #include <brom/code32.h>
 #include <brom/os.h>
 
-#ifdef SDK_NE1ENU
+#ifdef SDK_NE1EMU
 
 /*---------------------------------------------------------------------------*
   Name:         i_stupInitDDR2
@@ -54,7 +54,7 @@ void i_stupInitDDR2( void )
     reg_NE1_MIF_REF_CFG = 0x00000121;
 }
 
-#endif // SDK_NE1ENU
+#endif // SDK_NE1EMU
 
 /*---------------------------------------------------------------------------*
   Name:         __user_initial_stackheap

trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c

@@ -67,11 +67,11 @@ asm void i_stupStartHandler( void )
         //---- initialize MMU
         bl              stupInitMMU
 
-#ifdef SDK_NE1ENU
+#ifdef SDK_NE1EMU
         //---- initialize DDR2
         INASM_EXTERN( i_stupInitDDR2 )
         bl              i_stupInitDDR2
-#endif // SDK_NE1ENU
+#endif // SDK_NE1EMU
 
         //---- enable cp15
         bl              stupEnableCP15
@@ -432,6 +432,20 @@ void stupInitMMUTable( void )
         paddr += HW_MMU6_T1_SEC_SIZE;
     }
 
+#ifdef SDK_NE1EMU
+    // NE1-TB DDR2 Registers Region (1MB)
+    paddr = HW_NE1DDR2_REG; 
+    table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
+    *table++ = HW_MMU6_T1_SEC_PACK(
+                  paddr,
+                  HW_MMU6_T1_APX_S_RW_U_NA,
+                  HW_MMU6_T1_RGT_NSHARED_DEV,
+                  HW_MMU6_T1_GLOBAL,
+                  FALSE,
+                  HW_MMU6_T1_XN,
+                  0);
+#endif // SDK_NE1EMU
+
     // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached)
     paddr = HW_DSP_WRAM;
     table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];

trunk/include/ctr/hw/ARM11/mmap_global.h

@@ -56,7 +56,11 @@ extern  "C" {
 #else // SDK_MG20EMU || SDK_NE1EMU
 //----------------------------- AXI-WRAM
 #define HW_AXI_WRAM             (HW_AXI_WRAM_END - HW_AXI_WRAM_SIZE)
+#ifdef SDK_MG20EMU
 #define HW_AXI_WRAM_END         HW_MAIN_MEM_END
+#else // SDK_NE1EMU
+#define HW_AXI_WRAM_END         HW_MAIN_MEM_EX_END
+#endif // SDK_NE1EMU
 #define HW_AXI_WRAM_SIZE        0x80000 // 512KB
 
 //----------------------------- DSP-WRAM

trunk/setup

@@ -8,10 +8,12 @@
 export CTRFIRM_ROOT=`cygpath -m $PWD`
 export CTRBROM_ROOT=$CTRFIRM_ROOT/bootrom
 export CTRSDK_ROOT=$CTRFIRM_ROOT
+export BROM_PLATFORM='MG20EMU'
 export CYGPATH_NOCMD='TRUE'
 
 echo "Set CTRFIRM_ROOT: $CTRFIRM_ROOT"
 echo "Set CTRBROM_ROOT: $CTRBROM_ROOT"
 echo "Set CTRSDK_ROOT: $CTRSDK_ROOT"
+echo "Set BROM_PLATFORM: $BROM_PLATFORM"
 echo "Set CYGPATH_NOCMD: $CYGPATH_NOCMD"