From 9061515269a36dedfb427107c0c18e7b1206be44 Mon Sep 17 00:00:00 2001 From: nakasima Date: Mon, 1 Dec 2008 07:15:43 +0000 Subject: [PATCH] =?UTF-8?q?ARM11=E3=82=B9=E3=82=BF=E3=83=BC=E3=83=88?= =?UTF-8?q?=E3=82=A2=E3=83=83=E3=83=97=E8=BF=BD=E5=8A=A0=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@48 b871894f-2f95-9b40-918c-086798483c85 --- .../build/libraries/init/ARM11/Makefile | 54 ++ .../bootrom/build/libraries/init/ARM11/crt0.c | 61 ++ .../build/libraries/init/ARM11/crt0_app.c | 109 ++++ .../build/libraries/init/ARM11/crt0_misc.c | 207 +++++++ .../build/libraries/init/ARM11/crt0_scat.c | 50 ++ .../build/libraries/init/ARM11/crt0_secure.c | 580 ++++++++++++++++++ .../bootrom/build/libraries/init/ARM9/crt0.c | 7 + .../build/libraries/init/ARM9/crt0_misc_sp.c | 56 ++ trunk/bootrom/build/libraries/init/Makefile | 2 +- .../build/libraries/swi/common/swi_table.c | 5 - .../include/brom/hw/ARM11/mmap_axi_wram.h | 74 +++ .../bootrom/include/brom/hw/ARM11/mmap_brom.h | 60 ++ .../bootrom/include/brom/hw/ARM9/mmap_brom.h | 36 +- trunk/bootrom/include/brom/hw/ARM9/mmap_tcm.h | 62 ++ .../include/brom/hw/common/mmap_shared.h | 1 - trunk/bootrom/include/brom/memorymap.h | 10 +- trunk/build/buildtools/commondefs.cctype.RVCT | 4 +- 17 files changed, 1327 insertions(+), 51 deletions(-) create mode 100644 trunk/bootrom/build/libraries/init/ARM11/Makefile create mode 100644 trunk/bootrom/build/libraries/init/ARM11/crt0.c create mode 100644 trunk/bootrom/build/libraries/init/ARM11/crt0_app.c create mode 100644 trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c create mode 100644 trunk/bootrom/build/libraries/init/ARM11/crt0_scat.c create mode 100644 trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c create mode 100644 trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h create mode 100644 trunk/bootrom/include/brom/hw/ARM11/mmap_brom.h create mode 100644 trunk/bootrom/include/brom/hw/ARM9/mmap_tcm.h diff --git a/trunk/bootrom/build/libraries/init/ARM11/Makefile b/trunk/bootrom/build/libraries/init/ARM11/Makefile new file mode 100644 index 0000000..627f035 --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/Makefile @@ -0,0 +1,54 @@ +#! make -f +#---------------------------------------------------------------------------- +# Project: CtrBrom - libraries_sp - init +# File: Makefile +# +# Copyright 2008 Nintendo. All rights reserved. +# +# These coded instructions, statements, and computer programs contain +# proprietary information of Nintendo of America Inc. and/or Nintendo +# Company Ltd., and are protected by Federal copyright law. They may +# not be disclosed to third parties or copied or duplicated in any form, +# in whole or in part, without the prior written consent of Nintendo. +# +# $Date:: 2008-12-1#$ +# $Rev: 46 $ +# $Author: nakasima $ +#---------------------------------------------------------------------------- + +SUBDIRS = + + +#---------------------------------------------------------------------------- + +# build ARM & THUMB libraries +BROM_CODEGEN_ALL ?= True + +# Codegen for sub processer +BROM_PROC = ARM11 + +SRCDIR = ../common . + +SRCS = crt0.c crt0_secure.c crt0_scat.c # crt0_app.c +TARGET_OBJ = crt0.o crt0_secure.o crt0_scat.o # crt0_app.o + + +#---------------------------------------------------------------------------- + +include $(CTRBROM_ROOT)/build/buildtools/commondefs + +INSTALL_TARGETS = $(TARGETS) +INSTALL_DIR = $(BROM_INSTALL_LIBDIR) + +MACRO_FLAGS += -DSDK_NOINIT + + +#---------------------------------------------------------------------------- + +do-build: $(TARGETS) # $(TARGETS) + + +include $(CTRBROM_ROOT)/build/buildtools/modulerules + + +#===== End of Makefile ===== diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0.c b/trunk/bootrom/build/libraries/init/ARM11/crt0.c new file mode 100644 index 0000000..35848c0 --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0.c @@ -0,0 +1,61 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-11-28#$ + $Rev: 41 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include +#include +//#include + +void _start(void); + +/*---------------------------------------------------------------------------* + Name: _start + + Description: Start up + + Arguments: None + + Returns: None. + *---------------------------------------------------------------------------*/ +asm void _start( void ) +{ + PRESERVE8 + + CODE32 // for _start reference + + INASM_EXTERN( STUPi_StartHandler ) + + b stupStartHandlerVeneer // don't change for NULL access compatibility +undef b STUPi_DbgHandler +swi b STUPi_SwiHandler +iabt b STUPi_DbgHandler +dabt b STUPi_DbgHandler +reserve b reserve +irq b STUPi_IrqHandler +fiq b STUPi_DbgHandler + +stupStartHandlerVeneer + b STUPi_StartHandler + DCD 0 + + INASM_EXTERN( |Image$$SVC_RW$$Base| ) + INASM_EXTERN( |Load$$SVC_RW$$Base| ) + + DCD |Image$$SVC_RW$$Base| + DCD |Load$$SVC_RW$$Base| +} + +#include <../common/crt0_excpHandler.c> + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c new file mode 100644 index 0000000..2227dde --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c @@ -0,0 +1,109 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_app.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 46 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include +#include +//#include + +void _start(void); + +/*---------------------------------------------------------------------------* + Name: _start + + Description: Start up + + Arguments: None + + Returns: None. + *---------------------------------------------------------------------------*/ +asm void _start( void ) +{ + PRESERVE8 + + b stupStartHandlerVeneer // don't change for NULL access compatibility + +stupStartHandlerVeneer + b STUPi_StartHandler +} + +/*---------------------------------------------------------------------------* + Name: STUPi_StartHandler + + Description: start handler + + Arguments: None + + Returns: None. + *---------------------------------------------------------------------------*/ +asm void STUPi_StartHandler( void ) +{ + INASM_EXTERN( BromSpMain ) + INASM_EXTERN( main ) + +#ifndef BROM_ENABLE_BOOTROM_WRITE + + ldr r3, =REG_ROM_ADDR + ldrb r1, [r3] + bic r1, #REG_SCFG_ROM_WE_MASK + strb r1, [r3] + +#endif // BROM_ENABLE_BOOTROM_WRITE + + //---- set IME = 0 + // ( use that LSB of HW_REG_BASE equal to 0 ) + mov r12, #HW_REG_BASE + str r12, [r12, #REG_IME_OFFSET] + + // init BROM prot + ldr r3, =REG_PROT_ADDR + ldr r1, =4*8 // 0x1204 + strh r1, [r3] + + //---- initialize stack pointer + // SVC mode + mov r0, #HW_PSR_SVC_MODE + msr cpsr_c, r0 + ldr sp, =HW_PRV_WRAM_SVC_STACK_END + + // IRQ mode + mov r0, #HW_PSR_IRQ_MODE + msr cpsr_c, r0 + ldr r0, =HW_PRV_WRAM_IRQ_STACK_END + mov sp, r0 + + // System mode + ldr r1, =HW_IRQ_STACK_SIZE + sub r1, r0, r1 + mov r0, #HW_PSR_SYS_MODE + msr cpsr_csfx, r0 + sub sp, r1, #4 // 4byte for stack check code + + //---- lnitialize sections + bl stupInitSections + + //---- start (to 16bit code) + ldr r1, =BromSpMain + adr lr, terminate + + bx r1 + +terminate + b terminate +} + +#undef BROM_TARGET_BROM +#include <./crt0_misc_sp.c> + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c new file mode 100644 index 0000000..49ad618 --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c @@ -0,0 +1,207 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_misc.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 46 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include +#include +//#include + + +/*---------------------------------------------------------------------------* + Name: __user_initial_stackheap + + Description: called from __scatterload + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void __user_initial_stackheap( void ) +{ +#ifdef BROM_ENABLE_INITIAL_STACKHEAP + + INASM_EXTERN( |Image$$ZI$$ZI$$Limit| ) + + ldr r0, =|Image$$ZI$$ZI$$Limit| // heap base + ldr r1, =HW_BROM_IRQ_STACK_END + sub r1, r1, #HW_BROM_IRQ_STACK_SIZE + mov r2, r0 + mov r3, r0 + +#endif // BROM_ENABLE_INITIAL_STACKHEAP + + bx lr +} + +/*---------------------------------------------------------------------------* + Name: stupInitSections + + Description: Initialize Sections + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void stupInitSections( void ) +{ + b stupInitStaticSections +} + +/*---------------------------------------------------------------------------* + Name: stupInitStaticSections + + Description: Initialize Static Sections + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +ASM void stupInitStaticSections( void ) +{ +#ifdef BROM_TARGET_BROM + INASM_EXTERN( |Image$$SEC_RO$$Limit| ) + ldr r0, =|Image$$SEC_RO$$Limit| + +#else // BROM_TARGET_NORFIRM || BROM_TARGET_APP + INASM_EXTERN( |Image$$RO$$Limit| ) + ldr r0, =|Image$$RO$$Limit| + +#endif // BROM_TARGET_NORFIRM || BROM_TARGET_APP + + INASM_EXTERN( |Image$$RW$$Base| ) + INASM_EXTERN( |Image$$ZI$$ZI$$Base| ) + INASM_EXTERN( |Image$$ZI$$ZI$$Limit| ) + + ldr r1, =|Image$$RW$$Base| + ldr r3, =|Image$$ZI$$ZI$$Base| + cmp r0, r1 + beq FSYM(20) +LSYM(10) + cmp r1, r3 + ldrcc r2, [r0], #4 + strcc r2, [r1], #4 + bcc BSYM(10) +LSYM(20) + ldr r1, =|Image$$ZI$$ZI$$Limit| + mov r2, #0 +LSYM(30) + cmp r3, r1 + strcc r2, [r3], #4 + bcc BSYM(30) + bx lr +} + +/*---------------------------------------------------------------------------* + Name: STUPi_CpuCopy32 + + Description: copy memory by CPU + 32bit version + + Arguments: srcp : source address + destp : destination address + size : size (byte) + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void STUPi_CpuCopy32( const void *srcp, void *destp, u32 size ) +{ + add r12, r1, r2 +LSYM(10) + cmp r1, r12 + ldmltia r0!, {r2} + stmltia r1!, {r2} + blt BSYM(10) + bx lr +} + +/*---------------------------------------------------------------------------* + Name: STUPi_CpuClear32 + + Description: fill memory with specified data. + 32bit version + + Arguments: data : fill data + destp : destination address + size : size (byte) + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void STUPi_CpuClear32( u32 data, void *destp, u32 size ) +{ + add r12, r1, r2 +LSYM(10) + cmp r1, r12 + stmltia r1!, {r0} + blt BSYM(10) + bx lr +} + +/*---------------------------------------------------------------------------* + Name: STUPi_NotifyToARM9 + + Description: notify 4bit id to ARM9 + + Arguments: id notifying id + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void STUPi_NotifyToARM9( u32 id ) +{ + ldr r3, =REG_SUBPINTF_ADDR + mov r0, r0, lsl #REG_PXI_SUBPINTF_A11STATUS_SHIFT + and r0, r0, #REG_PXI_SUBPINTF_A11STATUS_MASK + str r0, [r3] + bx lr +} + +/*---------------------------------------------------------------------------* + Name: STUPi_WaitARM9 + + Description: Wait 4bit id from ARM9 + + Arguments: id waiting id + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void STUPi_WaitARM9( u32 id ) +{ + ldr r3, =REG_SUBPINTF_ADDR +LSYM(10) + ldr r1, [r3] + and r1, r1, #REG_PXI_SUBPINTF_A9STATUS_MASK + cmp r0, r1 + bne BSYM(10) + bx lr +} + +/*---------------------------------------------------------------------------* + Name: STUPi_WaitCpuCycles + + Description: Loop and Wait for specified CPU cycles at least + + Arguments: cycles waiting CPU cycle + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void STUPi_WaitCpuCycles( u32 cycle ) +{ + sub r0, r0, #(6-2) // subtract call-return overhead and add the margin of 2 cycles +LSYM(10) + subs r0, r0, #4 // 1 cycle + bcs BSYM(10) // 3 cycle + bx lr +} + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_scat.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_scat.c new file mode 100644 index 0000000..4accc7b --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_scat.c @@ -0,0 +1,50 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_scat.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 46 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include +#include + +/*---------------------------------------------------------------------------* + Name: $Sub$$stupInitSections + + Description: Initialize Sections Patch + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +ASM void $Sub$$stupInitSections(void) +{ + INASM_EXTERN( __main ) + + b __main // call __scatterload and __rt_entry +} + +/*---------------------------------------------------------------------------* + Name: main + + Description: BromMain hook for scatterload + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +int main( void ) +{ + BromMain(); + return 0; +} + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c new file mode 100644 index 0000000..518532e --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c @@ -0,0 +1,580 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_secure.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 46 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include +#include +//#include + +#define BROM_ENABLE_BOOTROM_WRITE + +#define STUPi_HW_DTCM |Image$$DTCM$$Base| + +void stupInitMMUTable( void ); + + +/*---------------------------------------------------------------------------* + Name: STUPi_StartHandler + + Description: start handler + + Arguments: None + + Returns: None. + *---------------------------------------------------------------------------*/ +asm void STUPi_StartHandler( void ) +{ + PRESERVE8 + + INASM_EXTERN( STUPi_HW_DTCM ) + INASM_EXTERN( BromMain ) + INASM_EXTERN( main ) + +#ifndef BROM_ENABLE_BOOTROM_WRITE + + ldr r3, =REG_ROM_ADDR + ldrb r1, [r3] + bic r1, #REG_SCFG_ROM_WE_MASK + strb r1, [r3] + +#endif // BROM_ENABLE_BOOTROM_WRITE + + //---- disable cp15 + bl stupDisableCP15 + + //---- initialize MMU + bl stupInitMMU + + //---- enable cp15 + bl stupEnableCP15 + + //---- initialize stack pointer + // SVC mode + mov r0, #HW_PSR_SVC_MODE + msr cpsr_c, r0 + ldr sp, =HW_BROM_SVC_STACK_END + + // IRQ mode + mov r0, #HW_PSR_IRQ_MODE + msr cpsr_c, r0 + ldr r0, =HW_BROM_IRQ_STACK_END + mov sp, r0 + + // System mode + mov r0, #HW_PSR_SYS_MODE + msr cpsr_csfx, r0 + ldr r0, =HW_BROM_SYS_STACK_END + mov sp, r0 + + //---- clear wram + // 1KB + mov r0, #0 + ldr r1, =HW_AXI_WRAM_END + mov r2, #0x0400 + sub r1, r1, r2 + bl STUPi_CpuClear32 + + //---- lnitialize sections + bl stupInitSections + + //---- start (to 16bit code) + ldr r1, =BromMain + adr lr, terminate + + bx r1 + +terminate + b terminate +} + +/*---------------------------------------------------------------------------* + Name: stupDisableCP15 + + Description: Disable Coprocessor 15 + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +ASM void stupDisableCP15( void ) +{ + // MMU/Caches/BranchPrediction disable + + mrc p15, 0, r0, c1, c0, 0 + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ + | HW_C1_FORCE_AP_BIT \ + | HW_C1_TEX_CB_REMAP \ + | HW_C1_NMFI_FIQ \ + | HW_C1_EXCEPT_BIG_ENDIAN \ + | HW_C1_BR_PREDICT_ENABLE \ + | HW_C1_LD_INTERWORK_DISABLE \ + | HW_C1_UNALIGN_ACCESS_ENABLE \ + | HW_C1_ALIGN_FAULT_ENABLE \ + | HW_C1_ROM_PROTECT_ENABLE \ + | HW_C1_MMU_PROTECT_ENABLE \ + | HW_C1_MMU_ENABLE + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c1, c0, 1 + ldr r1, =HW_C1_SMP_MODE \ + | HW_C1_EXCLUSIVE_L1C_L2C \ + | HW_C1_BR_FOLDING_ENABLE \ + | HW_C1_SBR_PREDICT_ENABLE \ + | HW_C1_DBR_PREDICT_ENABLE \ + | HW_C1_RETURN_STACK_ENABLE + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 1 +#if 0 + // Invalidate Caches + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // Inst Cache + mcr p15, 0, r0, c7, c6, 0 // Data cache +#endif + // Wait for write buffer empty + mcr p15, 0, r0, c7, c10, 4 + + bx lr +} + + +/*---------------------------------------------------------------------------* + Name: stupEnableCP15 + + Description: Enable Coprocessor 15 + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +ASM void stupEnableCP15( void ) +{ + // + // Auxiliary Control + // + mrc p15, 0, r0, c1, c0, 1 + ldr r1, =HW_C1_AMP_MODE \ + | HW_C1_BR_FOLDING_ENABLE \ + | HW_C1_SBR_PREDICT_ENABLE \ + | HW_C1_DBR_PREDICT_ENABLE \ + | HW_C1_RETURN_STACK_ENABLE + orr r0, r0, r1 + + mcr p15, 0, r0, c1, c0, 1 + + // + // Master Control + // + mrc p15, 0, r0, c1, c0, 0 + + +#if 1 // 0 -> 1 miya + ldr r1, =HW_C1_EXCEPT_VEC_UPPER \ + | HW_C1_FORCE_AP_BIT \ + | HW_C1_UNALIGN_ACCESS_ENABLE \ + | HW_C1_BR_PREDICT_ENABLE \ + | HW_C1_MMU_V6 \ + | HW_C1_IC_ENABLE \ + | HW_C1_DC_ENABLE \ + | HW_C1_MMU_ENABLE +#else + ldr r1, =HW_C1_0_SB1 \ + | HW_C1_EXCEPT_LITTLE_ENDIAN \ + | HW_C1_EXCEPT_VEC_UPPER \ + | HW_C1_UNALIGN_ACCESS_ENABLE \ + | HW_C1_BR_PREDICT_ENABLE \ + | HW_C1_MMU_V6 \ + | HW_C1_IC_ENABLE \ + | HW_C1_DC_ENABLE \ + | HW_C1_MMU_ENABLE +#endif + + orr r0, r0, r1 + + mcr p15, 0, r0, c1, c0, 0 + + // Invalidate Caches + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // Inst Cache + mcr p15, 0, r0, c7, c6, 0 // Data cache + + // Wait for write buffer empty + mcr p15, 0, r0, c7, c10, 4 + + + bx lr + +} + +/*---------------------------------------------------------------------------* + Name: stupInitMMU + + Description: Initialize MMU + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +ASM void stupInitMMU( void ) +{ + stmfd sp!, {r4, lr} // stack requires 8byte alignment + + // Invalidate ITLB DTLB + mov r0, #0 + mcr p15, 0, r0, c8, c5, 0 + mcr p15, 0, r0, c8, c6, 0 + + ldr r0, =HW_BROM_MMU_T1 + + mov r2, #HW_C2_V5_T1_BOUNBRY_16KB + + // MMU L1 Table Base + + ldr r1, =HW_C2_0_T1_BASE_MASK_MIN + mov r1, r1, ASR r2 + and r1 ,r1, r0 + orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT + mcr p15, 0, r1, c2, c0, 0 + + ldr r1, =HW_C2_1_T1_BASE_MASK + and r1 ,r1, r0 + orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT + mcr p15, 0, r1, c2, c0, 1 + + // MMU L1 Table Boundary + + mcr p15, 0, r2, c2, c0, 2 + + // Domain Access Permission +#if 1 // miya + ldr r1, =0x00000001 +#else + ldr r1, = HW_C3_DOMAIN_PACK( \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER \ + ) +#endif + + + mcr p15, 0, r1, c3, c0, 0 + + // VFP Access Permission + + ldr r1, =HW_C1_VFP_AP_PACK( \ + HW_C1_AP_PRIV, HW_C1_AP_PRIV ) + mcr p15, 0, r1, c1, c0, 2 + + // Initialize MMU Table + + bl __cpp(stupInitMMUTable) + + ldmfd sp!, {r4, pc} // stack requires 8byte alignment +} + + +/*---------------------------------------------------------------------------* + Name: stupInitMMUTable + + Description: Initialize MMU Table + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +void stupInitMMUTable( void ) +{ + + + u32* t1Base = (u32* )HW_BROM_MMU_T1; + u32* t2Base = (u32* )HW_BROM_MMU_T2; + + + u32* table; + u32 paddr = (u32 )NULL; + + // Initialize as Access Prohibition + table = &t1Base[0]; + for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_APX_NA, + HW_MMU6_T1_RGT_STRONG_ORDER, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + +#if 0 + table = &t2Base[0]; + for ( paddr = (u32 )NULL; table < (void *)HW_MAIN_MEM_MMU_T2_END; ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_NA, + HW_MMU6_T2_LP_RGT_STRONG_ORDER, + HW_MMU6_T2_GLOBAL, + FALSE, + HW_MMU6_T2_SP_XN); + } + + + + // EDRAM Region (4MB uncache) + table = &t1Base[HW_EDRAM/HW_MMU6_T1_SEC_SIZE]; + for ( paddr = HW_EDRAM; paddr < HW_EDRAM_END; ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_NC, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // EDRAM Region (4MB cache) + table = &t1Base[HW_EDRAM_CACHED/HW_MMU6_T1_SEC_SIZE]; + for ( paddr = HW_EDRAM; paddr < HW_EDRAM_END; ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_WB_WA, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // Main Memory Region (64MB uncache) + table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE]; + + +#ifdef MIYA_MMU + for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_SEC_END; ) +#else + for ( paddr = HW_MAIN_MEM; paddr < (HW_MAIN_MEM +( 64 * 1024 *1024 )); ) +#endif + { + + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_NC, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + + // Main Memory Region (64MB cache) + table = &t1Base[HW_MAIN_MEM_CACHED/HW_MMU6_T1_SEC_SIZE]; +#ifdef MIYA_MMU + for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_SEC_END; ) +#else + for ( paddr = HW_MAIN_MEM; paddr < (HW_MAIN_MEM +( 64 * 1024 *1024 )); ) +#endif + { + + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_WB_WA, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + +#ifdef MIYA_MMU + *table = HW_MMU6_T1_COURSE_PACK( paddr, 0 ); + // T2 for Page + table = &t2Base[0]; + for ( paddr = HW_MAIN_MEM_LP; paddr < HW_MAIN_MEM_LP_END; ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_ALL, + //miya HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, + HW_MMU6_T2_LP_RGT_L1L2C_NC, + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + for ( paddr = HW_MAIN_MEM_SP_NA; paddr < HW_MAIN_MEM_SP_NA_END; ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + // miya HW_MMU6_T2_SP_RGT_STRONG_ORDER, + HW_MMU6_T2_SP_RGT_L1L2C_NC, + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); + paddr += HW_MMU6_T2_SP_SIZE; + } + + for ( paddr = HW_MAIN_MEM_SP; paddr < HW_MAIN_MEM_SP_END; ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_ALL, + // HW_MMU6_T2_SP_RGT_STRONG_ORDER, + HW_MMU6_T2_SP_RGT_L1L2C_NC, + HW_MMU6_T2_GLOBAL, + FALSE, + FALSE); + paddr += HW_MMU6_T2_SP_SIZE; + } + + t2Base += HW_MMU6_T1_CORS_SIZE/sizeof(t2Base[0]); +#endif + + // IO Registers Region (4MB) + // IOPIF (4MB) 0x40000000 + table = &t1Base[HW_IOPIF/HW_MMU6_T1_SEC_SIZE]; + for ( paddr = HW_IOPIF; paddr < (HW_IOPIF + 0x00100000 * 16) ; ) // HW_IOPIF_END + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // APBIF (64KB) 0x44100000 + table = &t1Base[HW_APBIF/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_APBIF; + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + // GPUIF (64MB) 0x48000000 + table = &t1Base[HW_GPUIF/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_GPUIF; + *table = HW_MMU6_T1_SUSEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE); + + // CONFIF (64KB) 0xfe000000 mmio cfg. + table = &t1Base[HW_CONFIF/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_CONFIF; + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + + // MPCore Registers Region (8KB) 0xff000000 + table = &t1Base[HW_MPCORE_REG/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_MPCORE_REG; + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + + + // TCRAM Region (4KB) + table = &t1Base[HW_TCRAM/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_TCRAM; + + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_NC, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + + + + // BIOS Region (32KB) 0xffff0000 + table = &t1Base[HW_BIOS/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_BIOS; + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1L2C_WB_WA, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); + + + // MSelect Region (4KB) = 0xfdff0000 + table = &t1Base[HW_MSEL_VIRTUAL/HW_MMU6_T1_SEC_SIZE]; + paddr = HW_BIOS; + *table = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_STRONG_ORDER, + HW_MMU6_T1_GLOBAL, + FALSE, + FALSE, + 0); +#endif +} + + +#include <./crt0_misc.c> + diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0.c b/trunk/bootrom/build/libraries/init/ARM9/crt0.c index 4eabf2f..35848c0 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0.c @@ -48,6 +48,13 @@ fiq b STUPi_DbgHandler stupStartHandlerVeneer b STUPi_StartHandler + DCD 0 + + INASM_EXTERN( |Image$$SVC_RW$$Base| ) + INASM_EXTERN( |Load$$SVC_RW$$Base| ) + + DCD |Image$$SVC_RW$$Base| + DCD |Load$$SVC_RW$$Base| } #include <../common/crt0_excpHandler.c> diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c index 433b2b2..8ff1ec6 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c @@ -104,6 +104,62 @@ LSYM(30) bx lr } +/*---------------------------------------------------------------------------* + Name: STUPi_EnableTCM + + Description: enable ITCM and DTCM + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void STUPi_EnableTCM( void ) +{ + // プロテクションユニット/キャッシュ/TCM ディセーブル + + mrc p15, 0, r0, c1, c0, 0 + ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ + | HW_C1_LD_INTERWORK_DISABLE \ + | HW_C1_PROTECT_UNIT_ENABLE + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + // キャッシュ無効化 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ + mcr p15, 0, r0, c7, c6, 0 // データキャッシュ + + // ライトバッファ エンプティ待ち + mcr p15, 0, r0, c7, c10, 4 + + // + // 命令ＴＣＭ 設定 + // + mov r0, #HW_C9_TCMR_32MB + mcr p15, 0, r0, c9, c1, 1 + + // + // データＴＣＭ 設定 + // + ldr r0, =STUPi_HW_DTCM + orr r0, r0, #HW_C9_TCMR_16KB + mcr p15, 0, r0, c9, c1, 0 + + // + // システム制御コプロセッサ マスター設定 + // + mrc p15, 0, r0, c1, c0, 0 + ldr r1,=0 \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_SB1_BITSET + orr r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + bx lr +} + /*---------------------------------------------------------------------------* Name: STUPi_CpuCopy32 diff --git a/trunk/bootrom/build/libraries/init/Makefile b/trunk/bootrom/build/libraries/init/Makefile index 76b0138..7006370 100644 --- a/trunk/bootrom/build/libraries/init/Makefile +++ b/trunk/bootrom/build/libraries/init/Makefile @@ -19,7 +19,7 @@ include $(CTRBROM_ROOT)/build/buildtools/commondefs #---------------------------------------------------------------------------- -SUBDIRS = # ARM11 +SUBDIRS = ARM11 #ifdef CTR_WITH_ARM9 SUBDIRS += ARM9 diff --git a/trunk/bootrom/build/libraries/swi/common/swi_table.c b/trunk/bootrom/build/libraries/swi/common/swi_table.c index 70216ec..7559fdf 100644 --- a/trunk/bootrom/build/libraries/swi/common/swi_table.c +++ b/trunk/bootrom/build/libraries/swi/common/swi_table.c @@ -73,13 +73,8 @@ SWI_Table DCW SWI_WaitIntr // 4 DCW SWI_WaitVBlankIntr // 5 DCW SWI_Halt // 6 -#ifdef SDK_ARM9 DCW SWIi_Terminate // 7 DCW SWIi_Terminate // 8 -#else // SDK_ARM7 - DCW SWI_Sleep // 7 - DCW SWI_ChangeSoundBias+1 // 8 -#endif // SDK_ARM7 DCW SWI_DivS32 // 9 DCW SWIi_Terminate // 10 DCW SWI_CpuSet+1 // 11 diff --git a/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h new file mode 100644 index 0000000..70ccfa7 --- /dev/null +++ b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h @@ -0,0 +1,74 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - HW - include + File: mmap_axi_wram.h + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 47 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#ifndef BROM_HW_ARM11_AXI_WRAM_H_ +#define BROM_HW_ARM11_AXI_WRAM_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------- HW_BROM_STACK +#define HW_BROM_STACK (HW_BROM_STACK_END - HW_BROM_STACK_SIZE) +#define HW_BROM_STACK_END HW_BROM_MMU_TBL +#define HW_BROM_STACK_SIZE 0x4000 // 16KB + +#define HW_BROM_SVC_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) +#define HW_BROM_SVC_STACK_END HW_BROM_STACK_END +#define HW_BROM_SVC_STACK_SIZE 0x100 // 256B + +#define HW_BROM_IRQ_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) +#define HW_BROM_IRQ_STACK_END HW_BROM_SVC_STACK +#define HW_BROM_IRQ_STACK_SIZE (0x1000 - HW_BROM_SVC_STACK_SIZE) // 4KB - 256B + +#define HW_BROM_SYS_STACK (HW_BROM_SYS_STACK_END - HW_BROM_SYS_STACK_SIZE) +#define HW_BROM_SYS_STACK_END HW_BROM_IRQ_STACK +#define HW_BROM_SYS_STACK_SIZE (HW_BROM_STACK_SIZE - HW_BROM_IRQ_STACK_SIZE - HW_BROM_SVC_STACK_SIZE) // 12KB + +//------------------------------------- HW_BROM_MMU_TBL +#define HW_BROM_MMU_TBL (HW_BROM_MMU_TBL_END - HW_BROM_MMU_TBL_SIZE) +#define HW_BROM_MMU_TBL_END HW_AXI_WRAM_SHARED +#define HW_BROM_MMU_TBL_SIZE (HW_BROM_MMU_T1_SIZE + HW_BROM_MMU_T2_SIZE) // 24KB + +#define HW_BROM_MMU_T1 HW_BROM_MMU_TBL +#define HW_BROM_MMU_T2 HW_BROM_MMU_T1_END +#define HW_BROM_MMU_T1_END (HW_BROM_MMU_T1 + HW_BROM_MMU_T1_SIZE) +#define HW_BROM_MMU_T2_END (HW_BROM_MMU_T2 + HW_BROM_MMU_T2_SIZE) +#define HW_BROM_MMU_T1_SIZE 0x4000 // 16KB +#define HW_BROM_MMU_T2_SIZE 0x2000 // 8KB + + +//------------------------------------- BROM_SYSRV +#define HW_BROM_SYSRV HW_PRV_WRAM +#define HW_BROM_SYSRV_END (HW_BROM_SYSRV + HW_BROM_SYSRV_SIZE) +#define HW_BROM_SYSRV_SIZE 0x1000 // 4KB + +#define HW_BROM_SYSRV_IOFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) +#define HW_BROM_SYSRV_IOFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) +#define HW_BROM_SYSRV_IOFS_INTR_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) + +//------------------------------------- HW_BROM_TO_FIRM_BUF +#define HW_BROM_TO_FIRM_BUF HW_FIRM_FROM_BROM_BUF // defined in mmap_firm.h +#define HW_BROM_TO_FIRM_BUF_END HW_FIRM_FROM_BROM_BUF_END +#define HW_BROM_TO_FIRM_BUF_SIZE HW_FIRM_FROM_BROM_BUF_SIZE // 12KB + + +#ifdef __cplusplus +} /* extern "C" */ +#endif +/* BROM_HW_ARM11_AXI_WRAM_H_ */ +#endif diff --git a/trunk/bootrom/include/brom/hw/ARM11/mmap_brom.h b/trunk/bootrom/include/brom/hw/ARM11/mmap_brom.h new file mode 100644 index 0000000..3267055 --- /dev/null +++ b/trunk/bootrom/include/brom/hw/ARM11/mmap_brom.h @@ -0,0 +1,60 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - HW - include + File: mmap_brom.h + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 47 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#ifndef BROM_HW_ARM11_MMAP_BROM_H_ +#define BROM_HW_ARM11_MMAP_BROM_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------- BROM +#ifdef BROM_ENABLE_WRAMEMU +#define HW_BROM HW_WRAM +#else // BROM_ENABLE_WRAMEMU +#define HW_BROM HW_BIOS +#endif +#define HW_BROM_END (HW_BROM + HW_BROM_SIZE) +#define HW_BROM_SIZE 0x10000 // 64KB + +#define HW_BROM_NML HW_BROM +#define HW_BROM_NML_END (HW_BROM_NML + HW_BROM_NML_SIZE) +#define HW_BROM_NML_SIZE 0x8000 // 32KB +#define HW_BROM_SEC HW_BROM_NML_END +#define HW_BROM_SEC_END (HW_BROM_SEC + HW_BROM_SEC_SIZE) +#define HW_BROM_SEC_SIZE 0x8000 // 32KB + +//------------------------------------- BROM_TEMP +#define HW_BROM_TEMP (HW_BROM_TEMP_END - HW_BROM_TEMP_SIZE) +#define HW_BROM_TEMP_END HW_BROM_WRAM +#define HW_BROM_TEMP_SIZE 0x1000 // 4KB + +//------------------------------------- BROM_WRAM +#define HW_BROM_WRAM (HW_BROM_WRAM_END - HW_BROM_WRAM_SIZE) +#define HW_BROM_WRAM_END HW_BROM_TO_FIRM_BUF +#define HW_BROM_WRAM_SIZE 0xB000 // 44KB + + +#ifdef __cplusplus +} /* extern "C" */ +#endif +/* BROM_HW_ARM11_MMAP_BROM_H_ */ +#endif diff --git a/trunk/bootrom/include/brom/hw/ARM9/mmap_brom.h b/trunk/bootrom/include/brom/hw/ARM9/mmap_brom.h index 4a36c72..dd555f4 100644 --- a/trunk/bootrom/include/brom/hw/ARM9/mmap_brom.h +++ b/trunk/bootrom/include/brom/hw/ARM9/mmap_brom.h @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -51,41 +52,6 @@ extern "C" { #define HW_BROM_WRAM_END HW_BROM_TO_FIRM_BUF #define HW_BROM_WRAM_SIZE 0xB000 // 44KB -//------------------------------------- HW_BROM_TO_FIRM_BUF -#define HW_BROM_TO_FIRM_BUF HW_FIRM_FROM_BROM_BUF // defined in mmap_firm.h -#define HW_BROM_TO_FIRM_BUF_END HW_FIRM_FROM_BROM_BUF_END -#define HW_BROM_TO_FIRM_BUF_SIZE HW_FIRM_FROM_BROM_BUF_SIZE // 12KB - -//------------------------------------- HW_BROM_STACK -#define HW_BROM_STACK (HW_BROM_STACK_END - HW_BROM_STACK_SIZE) -#define HW_BROM_STACK_END HW_DTCM_END -#define HW_BROM_STACK_SIZE HW_DTCM_SIZE // 16KB - -#define HW_BROM_SVC_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) -#define HW_BROM_SVC_STACK_END HW_BROM_STACK_END -#define HW_BROM_SVC_STACK_SIZE 0x100 // 256B - -#define HW_BROM_IRQ_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) -#define HW_BROM_IRQ_STACK_END HW_BROM_SVC_STACK -#define HW_BROM_IRQ_STACK_SIZE (0x1000 - HW_BROM_SVC_STACK_SIZE) // 4KB - 256B - -#define HW_BROM_SYS_STACK (HW_BROM_SYS_STACK_END - HW_BROM_SYS_STACK_SIZE) -#define HW_BROM_SYS_STACK_END HW_BROM_IRQ_STACK -#define HW_BROM_SYS_STACK_SIZE (HW_BROM_STACK_SIZE - HW_BROM_IRQ_STACK_SIZE - HW_BROM_SVC_STACK_SIZE) // 12KB - - -//------------------------------------- BROM_SYSRV -#define HW_BROM_SYSRV HW_PRV_WRAM -#define HW_BROM_SYSRV_END (HW_BROM_SYSRV + HW_BROM_SYSRV_SIZE) -#define HW_BROM_SYSRV_SIZE 0x1000 // 4KB - -#define HW_BROM_SYSRV_IOFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) -#define HW_BROM_SYSRV_IOFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) -#define HW_BROM_SYSRV_IOFS_INTR_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) - -//------------------------------------- BIOS_ENTRY -#define HW_BIOS_ENTRY (HW_BIOS + 0x00bc) - #ifdef __cplusplus } /* extern "C" */ diff --git a/trunk/bootrom/include/brom/hw/ARM9/mmap_tcm.h b/trunk/bootrom/include/brom/hw/ARM9/mmap_tcm.h new file mode 100644 index 0000000..70d5e1c --- /dev/null +++ b/trunk/bootrom/include/brom/hw/ARM9/mmap_tcm.h @@ -0,0 +1,62 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - HW - include + File: mmap_tcm.h + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2008-12-1#$ + $Rev: 47 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#ifndef BROM_HW_ARM9_MMAP_TCM_H_ +#define BROM_HW_ARM9_MMAP_TCM_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------- HW_BROM_STACK +#define HW_BROM_STACK (HW_BROM_STACK_END - HW_BROM_STACK_SIZE) +#define HW_BROM_STACK_END HW_DTCM_END +#define HW_BROM_STACK_SIZE HW_DTCM_SIZE // 16KB + +#define HW_BROM_SVC_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) +#define HW_BROM_SVC_STACK_END HW_BROM_STACK_END +#define HW_BROM_SVC_STACK_SIZE 0x100 // 256B + +#define HW_BROM_IRQ_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) +#define HW_BROM_IRQ_STACK_END HW_BROM_SVC_STACK +#define HW_BROM_IRQ_STACK_SIZE (0x1000 - HW_BROM_SVC_STACK_SIZE) // 4KB - 256B + +#define HW_BROM_SYS_STACK (HW_BROM_SYS_STACK_END - HW_BROM_SYS_STACK_SIZE) +#define HW_BROM_SYS_STACK_END HW_BROM_IRQ_STACK +#define HW_BROM_SYS_STACK_SIZE (HW_BROM_STACK_SIZE - HW_BROM_IRQ_STACK_SIZE - HW_BROM_SVC_STACK_SIZE) // 12KB + + +//------------------------------------- BROM_SYSRV +#define HW_BROM_SYSRV HW_PRV_WRAM +#define HW_BROM_SYSRV_END (HW_BROM_SYSRV + HW_BROM_SYSRV_SIZE) +#define HW_BROM_SYSRV_SIZE 0x1000 // 4KB + +#define HW_BROM_SYSRV_IOFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) +#define HW_BROM_SYSRV_IOFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) +#define HW_BROM_SYSRV_IOFS_INTR_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) + +//------------------------------------- HW_BROM_TO_FIRM_BUF +#define HW_BROM_TO_FIRM_BUF HW_FIRM_FROM_BROM_BUF // defined in mmap_firm.h +#define HW_BROM_TO_FIRM_BUF_END HW_FIRM_FROM_BROM_BUF_END +#define HW_BROM_TO_FIRM_BUF_SIZE HW_FIRM_FROM_BROM_BUF_SIZE // 12KB + + +#ifdef __cplusplus +} /* extern "C" */ +#endif +/* BROM_HW_ARM9_MMAP_BROM_H_ */ +#endif diff --git a/trunk/bootrom/include/brom/hw/common/mmap_shared.h b/trunk/bootrom/include/brom/hw/common/mmap_shared.h index b22e65f..3300edf 100644 --- a/trunk/bootrom/include/brom/hw/common/mmap_shared.h +++ b/trunk/bootrom/include/brom/hw/common/mmap_shared.h @@ -24,7 +24,6 @@ extern "C" { //---------------------------------------------------------------------- // MEMORY MAP of SYSTEM SHARED AREA //---------------------------------------------------------------------- -// #define HW_AXI_WRAM_SHARED (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE) #define HW_AXI_WRAM_SHARED_END (HW_MAIN_MEM) diff --git a/trunk/bootrom/include/brom/memorymap.h b/trunk/bootrom/include/brom/memorymap.h index 6037593..e6b0215 100644 --- a/trunk/bootrom/include/brom/memorymap.h +++ b/trunk/bootrom/include/brom/memorymap.h @@ -24,16 +24,12 @@ extern "C" { #ifdef SDK_ARM9 #include #include -//#include -//#include -//#include #include #else //SDK_ARM11 -#include -#include -#include -//#include +#include +#include +#include #include #endif diff --git a/trunk/build/buildtools/commondefs.cctype.RVCT b/trunk/build/buildtools/commondefs.cctype.RVCT index 2a9c71b..f1a6d13 100644 --- a/trunk/build/buildtools/commondefs.cctype.RVCT +++ b/trunk/build/buildtools/commondefs.cctype.RVCT @@ -86,8 +86,8 @@ MACRO_FLAGS_CC += -DSDK_CODE_$(CODEGEN_CC) #-------------------------------------- CODEGEN_PROC ARM11/ARM9/ARM7 ifeq ($(CODEGEN_PROC),ARM11) -CCFLAGS_PROC := --cpu ARM11 -ASFLAGS_PROC := --cpu ARM11 +CCFLAGS_PROC := --cpu MPCore +ASFLAGS_PROC := --cpu MPCore else # ($(CODEGEN_PROC),ARM9) ifeq ($(CODEGEN_PROC),ARM9) CCFLAGS_PROC := --cpu ARM946E-S