rvtr/ctr_firmware
1
Fork 0
mirror of https://github.com/rvtr/ctr_firmware.git synced 2025-10-31 07:51:08 -04:00
Code Issues Actions Packages Projects Releases Wiki Activity

コード整理。

Browse Source 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@142 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-25 10:54:45 +00:00
parent 94ac873d2c
commit 8a41dac559
1 changed files with 31 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
trunk/bootrom/build/libraries/os/common/os_exception.c
View File

@ -32,7 +32,14 @@ void i_osUndefInstHandler( void );
void osInitException( void ) void osInitException( void )
{ {
#ifdef SDK_ARM11 #ifdef SDK_ARM11
static BOOL isInit;
if ( isInit == FALSE )
{
isInit = TRUE;
*(OSExcpHandler*)HW_UDEF_VECTOR_BUF = i_osUndefInstHandler; *(OSExcpHandler*)HW_UDEF_VECTOR_BUF = i_osUndefInstHandler;
}
#endif // SDK_ARM11 #endif // SDK_ARM11
} }
@ -77,18 +84,18 @@ ASM void i_osUndefInstHandler( void )
adr lr, i_return adr lr, i_return
tst r0, #HW_PSR_THUMB_STATE tst r0, #HW_PSR_THUMB_STATE
bne i_stupUndefInstHandlerDummy bne i_osUndefInstTerminate
tst r0, #HW_PSR_JAVA_STATE tst r0, #HW_PSR_JAVA_STATE
bne i_stupUndefInstHandlerDummy bne i_osUndefInstTerminate
ldr r0, [r12, #0] // called from ARM ldr r0, [r12, #0] // called from ARM
mov r12, r0, lsl #4 mov r12, r0, lsl #4
sub r12, r12, #0xC0000000 sub r12, r12, #0xC0000000
cmp r12, #0x30000000 cmp r12, #0x30000000
bhs i_stupUndefInstHandlerDummy bhs i_osUndefInstTerminate
adr r12, i_return adr r12, i_osUndefCPHandlerTable
and r0, r0, #0x00000F00 and r0, r0, #0x00000F00
ldr pc, [r12, r0, lsr #8-2] ldr pc, [r12, r0, lsr #8-2]
@ -99,26 +106,26 @@ i_return
INASM_EXTERN( _VFP_Computation_Engine ) INASM_EXTERN( _VFP_Computation_Engine )
i_stupUndefCPHandlerTable i_osUndefCPHandlerTable
DCD i_stupUndefInstHandlerDummy // CP 0 DCD i_osUndefInstTerminate // CP 0
DCD i_stupUndefInstHandlerDummy // CP 1 DCD i_osUndefInstTerminate // CP 1
DCD i_stupUndefInstHandlerDummy // CP 2 DCD i_osUndefInstTerminate // CP 2
DCD i_stupUndefInstHandlerDummy // CP 3 DCD i_osUndefInstTerminate // CP 3
DCD i_stupUndefInstHandlerDummy // CP 4 DCD i_osUndefInstTerminate // CP 4
DCD i_stupUndefInstHandlerDummy // CP 5 DCD i_osUndefInstTerminate // CP 5
DCD i_stupUndefInstHandlerDummy // CP 6 DCD i_osUndefInstTerminate // CP 6
DCD i_stupUndefInstHandlerDummy // CP 7 DCD i_osUndefInstTerminate // CP 7
DCD i_stupUndefInstHandlerDummy // CP 8 DCD i_osUndefInstTerminate // CP 8
DCD i_stupUndefInstHandlerDummy // CP 9 DCD i_osUndefInstTerminate // CP 9
DCD i_vfpUndefInstHandler // CP 10 DCD i_osUndefInstHandlerVFP // CP 10
DCD i_vfpUndefInstHandler // CP 11 DCD i_osUndefInstHandlerVFP // CP 11
DCD i_stupUndefInstHandlerDummy // CP 12 DCD i_osUndefInstTerminate // CP 12
DCD i_stupUndefInstHandlerDummy // CP 13 DCD i_osUndefInstTerminate // CP 13
DCD i_stupUndefInstHandlerDummy // CP 14 DCD i_osUndefInstTerminate // CP 14
DCD i_stupUndefInstHandlerDummy // CP 15 DCD i_osUndefInstTerminate // CP 15
} }
ASM void i_vfpUndefInstHandler( void ) ASM void i_osUndefInstHandlerVFP( void )
{ {
// VFP enable // VFP enable
fmrx r12, fpexc fmrx r12, fpexc
@ -142,7 +149,7 @@ LSYM(1)
bx lr bx lr
} }
ASM void i_stupUndefInstHandlerDummy( void ) ASM void i_osUndefInstTerminate( void )
{ {
LSYM(1) LSYM(1)
b BSYM(1) b BSYM(1)