アプリケーションのMMUテーブルとスタックをメインメモリへ移動。

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@250 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2009-02-04 09:30:21 +00:00
parent d258ddc83f
commit 847aa44731
9 changed files with 165 additions and 47 deletions

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@ -16,7 +16,7 @@
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
#include <brom/code32.h> #include <brom/code32.h>
#include <brom/os.h> #include <brom/os.h>
//#include <brom/mi.h> #include <app/memorymap.h>
#undef BROM_TARGET_BROM #undef BROM_TARGET_BROM
#define BROM_TARGET_APP #define BROM_TARGET_APP
@ -43,26 +43,28 @@ asm void _start( void )
// SVC mode // SVC mode
mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0 msr cpsr_fsxc, r0
ldr sp, =HW_BROM_SVC_STACK_END ldr sp, =HW_APP_SVC_STACK_END
// IRQ mode // IRQ mode
mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0 msr cpsr_fsxc, r0
ldr r0, =HW_BROM_IRQ_STACK_END ldr r0, =HW_APP_IRQ_STACK_END
mov sp, r0 mov sp, r0
// System mode // System mode
mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0 msr cpsr_fsxc, r0
ldr r0, =HW_BROM_SYS_STACK_END ldr r0, =HW_APP_SYS_STACK_END
mov sp, r0 mov sp, r0
//---- disable cp15 //---- disable cp15
bl stupDisableCP15 bl stupDisableCP15
//---- initialize MMU //---- initialize MMU
ldr r0, =HW_BROM_MMU_T1 ldr r0, =HW_APP_MMU_T1
ldr r1, =HW_BROM_MMU_T2 ldr r1, =HW_APP_MMU_T1_END
ldr r2, =HW_APP_MMU_T2
ldr r3, =HW_APP_MMU_T2_END
bl stupInitMMU bl stupInitMMU
//---- enable cp15 //---- enable cp15

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@ -62,7 +62,9 @@ asm void _start( void )
//---- initialize MMU //---- initialize MMU
ldr r0, =HW_FIRM_MMU_T1 ldr r0, =HW_FIRM_MMU_T1
ldr r1, =HW_FIRM_MMU_T2 ldr r1, =HW_FIRM_MMU_T1_END
ldr r2, =HW_FIRM_MMU_T2
ldr r3, =HW_FIRM_MMU_T2_END
bl stupInitMMU bl stupInitMMU
//---- enable cp15 //---- enable cp15

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@ -17,7 +17,7 @@
#include <brom/code32.h> #include <brom/code32.h>
#include <brom/os.h> #include <brom/os.h>
void stupInitMMUTable( u32* t1Base, u32* t2Base ); void stupInitMMUTable( u32* t1Base, u32* t1End, u32* t2Base, u32* t2End );
/*---------------------------------------------------------------------------* /*---------------------------------------------------------------------------*
Name: stupDisableCP15 Name: stupDisableCP15
@ -145,41 +145,41 @@ asm void stupEnableCP15( void )
Returns: None Returns: None
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
asm void stupInitMMU( u32* t1Base, u32* t2Base ) asm void stupInitMMU( u32* t1Base, u32* t1End, u32* t2Base, u32* t2End )
{ {
stmfd sp!, {r4, lr} // stack requires 8byte alignment stmfd sp!, {r4, lr} // stack requires 8byte alignment
// Invalidate ITLB DTLB // Invalidate ITLB DTLB
mov r3, #0 mov r4, #0
mcr p15, 0, r3, c8, c5, 0 mcr p15, 0, r4, c8, c5, 0
mcr p15, 0, r3, c8, c6, 0 mcr p15, 0, r4, c8, c6, 0
mov r2, #HW_C2_V5_T1_BOUNBARY_16KB mov r12, #HW_C2_V5_T1_BOUNBARY_16KB
// MMU L1 Table Base // MMU L1 Table Base
ldr r3, =HW_C2_0_T1_BASE_MASK_MIN ldr r4, =HW_C2_0_T1_BASE_MASK_MIN
mov r3, r3, ASR r2 mov r4, r4, ASR r12
and r3 ,r3, r0 and r4 ,r4, r0
orr r3, r3, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ orr r4, r4, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
| HW_C2_WALK_ON_SHARED_MEM | HW_C2_WALK_ON_SHARED_MEM
mcr p15, 0, r3, c2, c0, 0 mcr p15, 0, r4, c2, c0, 0
ldr r3, =HW_C2_1_T1_BASE_MASK ldr r4, =HW_C2_1_T1_BASE_MASK
and r3 ,r3, r0 and r4 ,r4, r0
orr r3, r3, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ orr r4, r4, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
| HW_C2_WALK_ON_SHARED_MEM | HW_C2_WALK_ON_SHARED_MEM
mcr p15, 0, r3, c2, c0, 1 mcr p15, 0, r4, c2, c0, 1
// MMU L1 Table Boundary // MMU L1 Table Boundary
mcr p15, 0, r2, c2, c0, 2 mcr p15, 0, r12, c2, c0, 2
// Domain Access Permission // Domain Access Permission
#if 1 // miya #if 1 // miya
ldr r3, =0x00000001 ldr r4, =0x00000001
#else #else
ldr r3, = HW_C3_DOMAIN_PACK( \ ldr r4, = HW_C3_DOMAIN_PACK( \
HW_C3_DM_AP_CLIENT, \ HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \ HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \ HW_C3_DM_AP_CLIENT, \
@ -200,13 +200,13 @@ asm void stupInitMMU( u32* t1Base, u32* t2Base )
#endif #endif
mcr p15, 0, r3, c3, c0, 0 mcr p15, 0, r4, c3, c0, 0
// VFP Access Permission // VFP Access Permission
ldr r3, =HW_C1_VFP_AP_PACK( \ ldr r4, =HW_C1_VFP_AP_PACK( \
HW_C1_AP_PRIV, HW_C1_AP_PRIV ) HW_C1_AP_PRIV, HW_C1_AP_PRIV )
mcr p15, 0, r3, c1, c0, 2 mcr p15, 0, r4, c1, c0, 2
// Initialize MMU Table // Initialize MMU Table
@ -225,14 +225,14 @@ asm void stupInitMMU( u32* t1Base, u32* t2Base )
Returns: None Returns: None
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void stupInitMMUTable( u32* t1Base, u32* t2Base ) void stupInitMMUTable( u32* t1Base, u32* t1End, u32* t2Base, u32* t2End )
{ {
u32* table; u32* table;
u32 paddr = (u32 )NULL; u32 paddr = (u32 )NULL;
// Initialize as Access Prohibition // Initialize as Access Prohibition
table = t1Base; table = t1Base;
for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) for ( paddr = (u32 )NULL; table < t1End; )
{ {
*table++ = HW_MMU6_T1_SEC_PACK( *table++ = HW_MMU6_T1_SEC_PACK(
paddr, paddr,
@ -245,7 +245,7 @@ void stupInitMMUTable( u32* t1Base, u32* t2Base )
} }
table = t2Base; table = t2Base;
for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) for ( paddr = (u32 )NULL; table < t2End; )
{ {
*table++ = HW_MMU6_T2_SP_PACK( *table++ = HW_MMU6_T2_SP_PACK(
paddr, paddr,

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@ -70,7 +70,9 @@ image_to_physical
//---- initialize MMU //---- initialize MMU
ldr r0, =HW_BROM_MMU_T1 ldr r0, =HW_BROM_MMU_T1
ldr r1, =HW_BROM_MMU_T2 ldr r1, =HW_BROM_MMU_T1_END
ldr r2, =HW_BROM_MMU_T2
ldr r3, =HW_BROM_MMU_T2_END
bl stupInitMMU bl stupInitMMU
//---- enable cp15 //---- enable cp15

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@ -0,0 +1,65 @@
/*---------------------------------------------------------------------------*
Project: CtrBrom - HW - include
File: mmap_app.h
Copyright 2009 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: $
$Rev$
$Author$
*---------------------------------------------------------------------------*/
#ifndef BROM_HW_ARM11_MMAP_APP_H_
#define BROM_HW_ARM11_MMAP_APP_H_
#include <brom/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
//------------------------------------- HW_APP
#define HW_APP HW_MAIN_MEM
#define HW_APP_END HW_APP_STACK
#define HW_APP_SIZE (HW_APP_STACK - HW_MAIN_MEM)
//------------------------------------- HW_APP_STACK
#define HW_APP_STACK (HW_APP_STACK_END - HW_APP_STACK_SIZE)
#define HW_APP_STACK_END HW_APP_MMU_TBL
#define HW_APP_STACK_SIZE 0x4000 // 16KB
#define HW_APP_SVC_STACK (HW_APP_SVC_STACK_END - HW_APP_SVC_STACK_SIZE)
#define HW_APP_SVC_STACK_END HW_APP_STACK_END
#define HW_APP_SVC_STACK_SIZE 0x100 // 256B
#define HW_APP_IRQ_STACK (HW_APP_IRQ_STACK_END - HW_APP_IRQ_STACK_SIZE)
#define HW_APP_IRQ_STACK_END HW_APP_SVC_STACK
#define HW_APP_IRQ_STACK_SIZE (0x1000 - HW_APP_SVC_STACK_SIZE) // 4KB - 256B
#define HW_APP_SYS_STACK (HW_APP_SYS_STACK_END - HW_APP_SYS_STACK_SIZE)
#define HW_APP_SYS_STACK_END HW_APP_IRQ_STACK
#define HW_APP_SYS_STACK_SIZE (HW_APP_STACK_SIZE - HW_APP_IRQ_STACK_SIZE - HW_APP_SVC_STACK_SIZE) // 12KB
//------------------------------------- HW_APP_MMU_TBL
#define HW_APP_MMU_TBL (HW_APP_MMU_TBL_END - HW_APP_MMU_TBL_SIZE)
#define HW_APP_MMU_TBL_END HW_MAIN_MEM_END
#define HW_APP_MMU_TBL_SIZE (HW_APP_MMU_T1_SIZE + HW_APP_MMU_T2_SIZE) // 32KB
#define HW_APP_MMU_T1 HW_APP_MMU_TBL
#define HW_APP_MMU_T2 HW_APP_MMU_T1_END
#define HW_APP_MMU_T1_END (HW_APP_MMU_T1 + HW_APP_MMU_T1_SIZE)
#define HW_APP_MMU_T2_END (HW_APP_MMU_T2 + HW_APP_MMU_T2_SIZE)
#define HW_APP_MMU_T1_SIZE 0x4000 // 16KB
#define HW_APP_MMU_T2_SIZE 0x4000 // 16KB
#ifdef __cplusplus
} /* extern "C" */
#endif
/* BROM_HW_ARM11_MMAP_APP_H_ */
#endif

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@ -0,0 +1,38 @@
/*---------------------------------------------------------------------------*
Project: CtrBrom - include - HW
File: memorymap.h
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: $
$Rev$
$Author$
*---------------------------------------------------------------------------*/
#ifndef APP_MEMORYMAP_H_
#define APP_MEMORYMAP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <brom/memorymap.h>
#ifdef SDK_ARM11
#include <app/hw/ARM11/mmap_app.h>
#else //SDK_ARM9
#include <app/hw/ARM9/mmap_app.h>
#endif
#ifdef __cplusplus
} /* extern "C" */
#endif
/* APP_MEMORYMAP_H_ */
#endif

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@ -0,0 +1,23 @@
/*---------------------------------------------------------------------------*
Project: CtrBrom - include - HW
File: memorymap_sp.h
Copyright 2009 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: $
$Rev$
$Author$
*---------------------------------------------------------------------------*/
#ifndef SDK_ARM9
#define SDK_ARM9
#endif
#ifdef SDK_ARM11
#undef SDK_ARM11
#endif
#include <app/memorymap.h>

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@ -27,25 +27,15 @@
extern "C" { extern "C" {
#endif #endif
//#define BROM_TARGET_PHASE1
//------------------------------------- BROM //------------------------------------- BROM
#define HW_BROM_IMG HW_BIOS_IMG #define HW_BROM_IMG HW_BIOS_IMG
#define HW_BROM HW_BIOS #define HW_BROM HW_BIOS
#define HW_BROM_END (HW_BROM + HW_BROM_SIZE) #define HW_BROM_END (HW_BROM + HW_BROM_SIZE)
#ifdef BROM_TARGET_PHASE1
#define HW_BROM_SIZE 0x8000 // 32KB
#else // BROM_TARGET_PHASE1
#define HW_BROM_SIZE 0x10000 // 64KB #define HW_BROM_SIZE 0x10000 // 64KB
#endif // BROM_TARGET_PHASE1
#define HW_BROM_NML HW_BROM #define HW_BROM_NML HW_BROM
#define HW_BROM_NML_END (HW_BROM_NML + HW_BROM_NML_SIZE) #define HW_BROM_NML_END (HW_BROM_NML + HW_BROM_NML_SIZE)
#ifdef BROM_TARGET_PHASE1
#define HW_BROM_NML_SIZE 0x4000 // 16KB
#else // BROM_TARGET_PHASE1
#define HW_BROM_NML_SIZE 0x8000 // 32KB #define HW_BROM_NML_SIZE 0x8000 // 32KB
#endif // BROM_TARGET_PHASE1
#define HW_BROM_NML_ABT HW_BROM_NML #define HW_BROM_NML_ABT HW_BROM_NML
#define HW_BROM_NML_ABT_END (HW_BROM_NML_ABT + HW_BROM_NML_ABT_SIZE) #define HW_BROM_NML_ABT_END (HW_BROM_NML_ABT + HW_BROM_NML_ABT_SIZE)
#define HW_BROM_NML_ABT_SIZE 0x1000 // 4KB #define HW_BROM_NML_ABT_SIZE 0x1000 // 4KB

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@ -19,11 +19,7 @@
// //
#define SDK_ASM #define SDK_ASM
#include <brom/hw/ARM11/mmap_brom.h> #include <app/hw/ARM11/mmap_app.h>
#define HW_APP HW_MAIN_MEM
#define HW_APP_END (HW_APP + HW_APP_SIZE)
#define HW_APP_SIZE HW_MAIN_MEM_SIZE
LOAD_STATIC HW_APP HW_APP_SIZE LOAD_STATIC HW_APP HW_APP_SIZE