mirror of
https://github.com/rvtr/ctr_firmware.git
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コア0でロードしたコア１のアプリケーションのブートへ対応
（ただしPARTNER環境ではコア1のデバッガをブート前に起動しておかないとホストIOで例外発生）。 git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@293 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima
parent
a8254d2a24
commit
732f6943f8
@ -16,6 +16,7 @@
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*---------------------------------------------------------------------------*/
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/code32.h>
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#include <brom/os.h>
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#include <brom/os.h>
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#include <app/memorymap.h>
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/*---------------------------------------------------------------------------*
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/*---------------------------------------------------------------------------*
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@ -85,6 +86,10 @@ image_to_physical
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mov r2, #HW_AXI_WRAM_SHARED_SYS_A11_SIZE
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mov r2, #HW_AXI_WRAM_SHARED_SYS_A11_SIZE
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bl i_stupCpuCopy32
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bl i_stupCpuCopy32
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ldr r3, =HW_START_VECTOR1_BUF
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ldr r0, =HW_APP
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str r0, [r3]
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// os finalize
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// os finalize
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bl i_osFinalize
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bl i_osFinalize
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@ -2,7 +2,7 @@
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Project: CtrFirm - HW - include
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Project: CtrFirm - HW - include
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File: mmap_shared.h
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File: mmap_shared.h
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Copyright 2008 Nintendo. All rights reserved.
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Copyright 2008-2009 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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proprietary information of Nintendo of America Inc. and/or Nintendo
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@ -25,6 +25,8 @@ extern "C" {
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// MEMORY MAP of SYSTEM SHARED AREA
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// MEMORY MAP of SYSTEM SHARED AREA
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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//---- AXI-WRAMシステム領域（最上位）
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#define HW_AXI_WRAM_SHARED (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE)
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#define HW_AXI_WRAM_SHARED (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE)
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#define HW_AXI_WRAM_SHARED_END (HW_AXI_WRAM_END)
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#define HW_AXI_WRAM_SHARED_END (HW_AXI_WRAM_END)
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#define HW_AXI_WRAM_SHARED_SIZE (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_GBL_SIZE) // 8KB
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#define HW_AXI_WRAM_SHARED_SIZE (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_GBL_SIZE) // 8KB
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@ -44,6 +46,23 @@ extern "C" {
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#define HW_AXI_WRAM_SHARED_GBL_SIZE 0x1000 // 4KB
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#define HW_AXI_WRAM_SHARED_GBL_SIZE 0x1000 // 4KB
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//---- メインメモリ・システム領域（最下位）
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#define HW_MAIN_MEM_SHARED HW_MAIN_MEM
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#define HW_MAIN_MEM_SHARED_END (HW_MAIN_MEM_SHARED + HW_MAIN_MEM_SHARED_SIZE)
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#define HW_MAIN_MEM_SHARED_SIZE (HW_MAIN_MEM_SHARED_SYS_SIZE + HW_MAIN_MEM_SHARED_PRV_SIZE) // 128KB
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// ユーザへ公開するシステム領域（ROMヘッダ等）
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#define HW_MAIN_MEM_SHARED_SYS HW_MAIN_MEM_SHARED
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#define HW_MAIN_MEM_SHARED_SYS_END (HW_MAIN_MEM_SHARED_SYS + HW_MAIN_MEM_SHARED_SYS_SIZE)
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#define HW_MAIN_MEM_SHARED_SYS_SIZE 0x10000 // 64KB
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// ユーザ非公開のシステム領域（コア間共有データ等）
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#define HW_MAIN_MEM_SHARED_PRV HW_MAIN_MEM_SHARED_SYS_END
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#define HW_MAIN_MEM_SHARED_PRV_END (HW_MAIN_MEM_SHARED_PRV + HW_MAIN_MEM_SHARED_PRV_SIZE)
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#define HW_MAIN_MEM_SHARED_PRV_SIZE 0x10000 // 64KB
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#ifdef __cplusplus
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#ifdef __cplusplus
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} /* extern "C" */
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} /* extern "C" */
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#endif
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#endif
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -8,244 +8,33 @@ Image Symbol Table
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Symbol Name Value Ov Type Size Object(Section)
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Symbol Name Value Ov Type Size Object(Section)
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../../memcpset.s 0x00000000 Number 0 rt_memcpy.o ABSOLUTE
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crt0.c 0x00000000 Number 0 crt0.o ABSOLUTE
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../../memcpset.s 0x00000000 Number 0 rt_memcpy_w_mpc.o ABSOLUTE
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crt0.c 0x00000000 Number 0 crt0.o ABSOLUTE
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../../memcpset.s 0x00000000 Number 0 memcpy.o ABSOLUTE
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.emb_text 0x00000000 Section 131072 crt0.o(.emb_text)
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\init\\ARM11\\crt0.c 0x00000000 Number 0 crt0.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\init\\common\\crt0_excp.c 0x00000000 Number 0 crt0_excp.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\mi\\common\\mi_memory.c 0x00000000 Number 0 mi_memory.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\os\\common\\os_boot.c 0x00000000 Number 0 os_boot.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\os\\common\\os_cache.c 0x00000000 Number 0 os_cache.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\os\\common\\os_interrupt.c 0x00000000 Number 0 os_interrupt.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\os\\common\\os_irqHandler.c 0x00000000 Number 0 os_irqHandler.o ABSOLUTE
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c:\\nctr\\ctr_firmware_bak\\bootrom\\build\\libraries\\os\\common\\os_system.c 0x00000000 Number 0 os_system.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\init\ARM11\crt0.c 0x00000000 Number 0 crt0.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\init\common\crt0_excp.c 0x00000000 Number 0 crt0_excp.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\mi\common\mi_memory.c 0x00000000 Number 0 mi_memory.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\os\common\os_boot.c 0x00000000 Number 0 os_boot.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\os\common\os_cache.c 0x00000000 Number 0 os_cache.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\os\common\os_interrupt.c 0x00000000 Number 0 os_interrupt.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\os\common\os_irqHandler.c 0x00000000 Number 0 os_irqHandler.o ABSOLUTE
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c:\nctr\ctr_firmware_bak\bootrom\build\libraries\os\common\os_system.c 0x00000000 Number 0 os_system.o ABSOLUTE
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crt0_secure.c 0x00000000 Number 0 crt0_secure.o ABSOLUTE
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crt0_secure.c 0x00000000 Number 0 crt0_secure.o ABSOLUTE
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os_mmu.c 0x00000000 Number 0 os_mmu.o ABSOLUTE
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os_mmu.c 0x00000000 Number 0 os_mmu.o ABSOLUTE
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$v0 0x00010000 ARM Code 0 crt0.o(.emb_text)
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.emb_text 0x00010000 Section 200 crt0.o(.emb_text)
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$v0 0x00011000 ARM Code 0 crt0_excp.o(.emb_text)
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.emb_text 0x00011000 Section 334 crt0_excp.o(.emb_text)
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i.osDisableInterrupts 0x0001114e Section 8 os_interrupt.o(i.osDisableInterrupts)
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.text 0x00011158 Section 16 memcpy.o(.text)
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.text 0x00011168 Section 116 rt_memcpy_w_mpc.o(.text)
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.text 0x000111dc Section 212 rt_memcpy.o(.text)
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i.stupInitMMUTable 0x000112b0 Section 492 crt0_secure.o(i.stupInitMMUTable)
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$v0 0x00018000 ARM Code 0 crt0_secure.o(.emb_text)
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.emb_text 0x00018000 Section 976 crt0_secure.o(.emb_text)
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image_to_physical 0x00018004 ARM Code 0 crt0_secure.o(.emb_text)
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$v0 0x000183d0 ARM Code 0 os_system.o(.emb_text)
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.emb_text 0x000183d0 Section 44 os_system.o(.emb_text)
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$v0 0x000183fc ARM Code 0 os_interrupt.o(.emb_text)
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.emb_text 0x000183fc Section 192 os_interrupt.o(.emb_text)
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$v0 0x000184bc ARM Code 0 os_cache.o(.emb_text)
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.emb_text 0x000184bc Section 624 os_cache.o(.emb_text)
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$v0 0x0001872c ARM Code 0 os_mmu.o(.emb_text)
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.emb_text 0x0001872c Section 544 os_mmu.o(.emb_text)
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i.i_osFinalize 0x0001894c Section 104 os_boot.o(i.i_osFinalize)
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i.osClearInterruptPendingMask 0x000189b4 Section 64 os_interrupt.o(i.osClearInterruptPendingMask)
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i.osDisableInterruptMask 0x000189f4 Section 64 os_interrupt.o(i.osDisableInterruptMask)
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.constdata$1 0x00018a34 Data 0 os_boot.o(.constdata)
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.constdata 0x00018a34 Section 16 os_boot.o(.constdata)
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Global Symbols
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Global Symbols
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Symbol Name Value Ov Type Size Object(Section)
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Symbol Name Value Ov Type Size Object(Section)
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BuildAttributes$$THUMB_ISAv3$ARM_ISAv6$M$E$P$VFPv2$PE$FZ_POSZERO$PLD1$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
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BuildAttributes$$THUMB_ISAv3$ARM_ISAv6$M$E$P$VFPv2$PE$FZ_POSZERO$PLD1$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
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_start 0x00010000 ARM Code 200 crt0.o(.emb_text)
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CTR_BROM_ARM11 0x00000000 Data 0 crt0.o(.emb_text)
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stupInitExceptions 0x00011000 ARM Code 64 crt0_excp.o(.emb_text)
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_start 0x00000000 Data 131072 crt0.o(.emb_text)
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i_stupExcpTerminateCode 0x00011040 ARM Code 8 crt0_excp.o(.emb_text)
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CTR_BROM_ARM9 0x00010000 Data 0 crt0.o(.emb_text)
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i_stupIAbtTerminateCode 0x00011048 ARM Code 8 crt0_excp.o(.emb_text)
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i_stupSwiVeneerCode 0x00011050 ARM Code 8 crt0_excp.o(.emb_text)
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i_stupIrqVeneer 0x00011058 ARM Code 4 crt0_excp.o(.emb_text)
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i_stupFiqVeneer 0x0001105c ARM Code 8 crt0_excp.o(.emb_text)
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i_stupSwiVeneer 0x00011064 ARM Code 8 crt0_excp.o(.emb_text)
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i_stupUndefVeneer 0x0001106c ARM Code 8 crt0_excp.o(.emb_text)
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i_stupIAbtVeneer 0x00011074 ARM Code 8 crt0_excp.o(.emb_text)
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i_stupDAbtVeneer 0x0001107c ARM Code 8 crt0_excp.o(.emb_text)
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i_stupSwiSemihosting 0x00011084 ARM Code 40 crt0_excp.o(.emb_text)
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i_stupSwiHandler 0x000110ac ARM Code 162 crt0_excp.o(.emb_text)
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SWI_Table 0x0001114c Data 0 crt0_excp.o(.emb_text)
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SWI_TableEnd 0x0001114f Thumb Code 0 crt0_excp.o(.emb_text)
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osDisableInterrupts 0x0001114f Thumb Code 8 os_interrupt.o(i.osDisableInterrupts)
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memcpy 0x00011158 ARM Code 16 memcpy.o(.text)
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__aeabi_memcpy4 0x00011168 ARM Code 0 rt_memcpy_w_mpc.o(.text)
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__aeabi_memcpy8 0x00011168 ARM Code 0 rt_memcpy_w_mpc.o(.text)
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__rt_memcpy_w 0x00011168 ARM Code 116 rt_memcpy_w_mpc.o(.text)
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_memcpy_lastbytes_aligned 0x000111c4 ARM Code 0 rt_memcpy_w_mpc.o(.text)
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__aeabi_memcpy 0x000111dc ARM Code 0 rt_memcpy.o(.text)
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__rt_memcpy 0x000111dc ARM Code 212 rt_memcpy.o(.text)
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_memcpy_lastbytes 0x00011290 ARM Code 0 rt_memcpy.o(.text)
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stupInitMMUTable 0x000112b0 ARM Code 448 crt0_secure.o(i.stupInitMMUTable)
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i_stupStartHandler 0x00018000 ARM Code 100 crt0_secure.o(.emb_text)
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i_stupInitDDR2 0x00018080 ARM Code 360 crt0_secure.o(.emb_text)
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stupDisableCP15 0x00018234 ARM Code 56 crt0_secure.o(.emb_text)
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stupEnableCP15 0x00018270 ARM Code 68 crt0_secure.o(.emb_text)
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stupInitMMU 0x000182b8 ARM Code 84 crt0_secure.o(.emb_text)
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__user_initial_stackheap 0x00018310 ARM Code 4 crt0_secure.o(.emb_text)
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stupInitSections 0x00018314 ARM Code 4 crt0_secure.o(.emb_text)
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stupInitStaticSections 0x00018318 ARM Code 60 crt0_secure.o(.emb_text)
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i_stupCpuCopy32 0x00018364 ARM Code 24 crt0_secure.o(.emb_text)
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i_stupCpuClear32 0x0001837c ARM Code 20 crt0_secure.o(.emb_text)
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i_stupNotifyToARM9 0x00018390 ARM Code 20 crt0_secure.o(.emb_text)
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i_stupWaitARM9 0x000183a8 ARM Code 24 crt0_secure.o(.emb_text)
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i_stupWaitCpuCycles 0x000183c0 ARM Code 16 crt0_secure.o(.emb_text)
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osGetProcMode 0x000183d0 ARM Code 12 os_system.o(.emb_text)
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i_osWaitCpuCycles 0x000183dc ARM Code 16 os_system.o(.emb_text)
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osHalt 0x000183ec ARM Code 8 os_system.o(.emb_text)
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osHaltUntilEvent 0x000183f4 ARM Code 8 os_system.o(.emb_text)
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osEnableIrq 0x000183fc ARM Code 20 os_interrupt.o(.emb_text)
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osDisableIrq 0x00018410 ARM Code 20 os_interrupt.o(.emb_text)
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osRestoreIrq 0x00018424 ARM Code 24 os_interrupt.o(.emb_text)
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osEnableFiq 0x0001843c ARM Code 20 os_interrupt.o(.emb_text)
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osDisableFiq 0x00018450 ARM Code 20 os_interrupt.o(.emb_text)
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osRestoreFiq 0x00018464 ARM Code 24 os_interrupt.o(.emb_text)
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osEnableIrqAndFiq 0x0001847c ARM Code 20 os_interrupt.o(.emb_text)
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osDisableIrqAndFiq 0x00018490 ARM Code 20 os_interrupt.o(.emb_text)
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osRestoreIrqAndFiq 0x000184a4 ARM Code 24 os_interrupt.o(.emb_text)
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osEnableDCache 0x000184bc ARM Code 24 os_cache.o(.emb_text)
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osDisableDCache 0x000184d4 ARM Code 24 os_cache.o(.emb_text)
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osRestoreDCache 0x000184ec ARM Code 40 os_cache.o(.emb_text)
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osInvalidateDCacheAll 0x00018514 ARM Code 12 os_cache.o(.emb_text)
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osStoreDCacheAll 0x00018520 ARM Code 44 os_cache.o(.emb_text)
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osFlushDCacheAll 0x0001854c ARM Code 52 os_cache.o(.emb_text)
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osInvalidateDCacheRange 0x00018580 ARM Code 28 os_cache.o(.emb_text)
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osStoreDCacheRange 0x0001859c ARM Code 28 os_cache.o(.emb_text)
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osFlushDCacheRange 0x000185b8 ARM Code 36 os_cache.o(.emb_text)
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osLockdownDCacheRange 0x000185dc ARM Code 0 os_cache.o(.emb_text)
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osUnlockdownDCache 0x000185dc ARM Code 0 os_cache.o(.emb_text)
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osUnlockdownDCacheAll 0x000185dc ARM Code 0 os_cache.o(.emb_text)
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osWaitWriteBufferEmpty 0x000185dc ARM Code 12 os_cache.o(.emb_text)
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osTouchDCacheRange 0x000185e8 ARM Code 28 os_cache.o(.emb_text)
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osKeepDataAccessOrder 0x00018604 ARM Code 12 os_cache.o(.emb_text)
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osEnableICache 0x00018610 ARM Code 24 os_cache.o(.emb_text)
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osDisableICache 0x00018628 ARM Code 24 os_cache.o(.emb_text)
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osRestoreICache 0x00018640 ARM Code 40 os_cache.o(.emb_text)
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osInvalidateICacheAll 0x00018668 ARM Code 12 os_cache.o(.emb_text)
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osInvalidateICacheRange 0x00018674 ARM Code 28 os_cache.o(.emb_text)
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osPrefetchICacheRange 0x00018690 ARM Code 28 os_cache.o(.emb_text)
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osInvalidateInstPrefetchBuffer 0x000186ac ARM Code 12 os_cache.o(.emb_text)
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osEnableBCache 0x000186b8 ARM Code 20 os_cache.o(.emb_text)
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osDisableBCache 0x000186cc ARM Code 20 os_cache.o(.emb_text)
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osRestoreBCache 0x000186e0 ARM Code 36 os_cache.o(.emb_text)
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osInvalidateBCacheAll 0x00018704 ARM Code 12 os_cache.o(.emb_text)
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osInvalidateBCacheRange 0x00018710 ARM Code 28 os_cache.o(.emb_text)
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osEnableMMU 0x0001872c ARM Code 16 os_mmu.o(.emb_text)
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osDisableMMU 0x0001873c ARM Code 16 os_mmu.o(.emb_text)
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osGetPhysicalAddr 0x0001874c ARM Code 44 os_mmu.o(.emb_text)
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osGetMemRegionType 0x00018780 ARM Code 36 os_mmu.o(.emb_text)
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osGetMemRegionCacheAttr 0x000187a4 ARM Code 36 os_mmu.o(.emb_text)
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osIsMemRegionShareable 0x000187c8 ARM Code 36 os_mmu.o(.emb_text)
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osIsMemRegionAbort 0x000187ec ARM Code 24 os_mmu.o(.emb_text)
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osInvalidateTLBAll 0x00018804 ARM Code 12 os_mmu.o(.emb_text)
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osInvalidateITLBAll 0x00018810 ARM Code 12 os_mmu.o(.emb_text)
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osInvalidateDTLBAll 0x0001881c ARM Code 12 os_mmu.o(.emb_text)
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osInvalidateTLBRange 0x00018828 ARM Code 32 os_mmu.o(.emb_text)
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|
||||||
osInvalidateITLBRange 0x00018848 ARM Code 32 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateDTLBRange 0x00018868 ARM Code 32 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateTLBAllWithASID 0x00018888 ARM Code 12 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateITLBAllWithASID 0x00018894 ARM Code 12 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateDTLBAllWithASID 0x000188a0 ARM Code 12 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateTLBRangeWithASID 0x000188ac ARM Code 48 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateITLBRangeWithASID 0x000188dc ARM Code 40 os_mmu.o(.emb_text)
|
|
||||||
osInvalidateDTLBRangeWithASID 0x00018904 ARM Code 40 os_mmu.o(.emb_text)
|
|
||||||
osStartTLBLockDown 0x0001892c ARM Code 20 os_mmu.o(.emb_text)
|
|
||||||
osEndTLBLockDown 0x00018940 ARM Code 12 os_mmu.o(.emb_text)
|
|
||||||
i_osFinalize 0x0001894d Thumb Code 100 os_boot.o(i.i_osFinalize)
|
|
||||||
osClearInterruptPendingMask 0x000189b5 Thumb Code 58 os_interrupt.o(i.osClearInterruptPendingMask)
|
|
||||||
osDisableInterruptMask 0x000189f5 Thumb Code 58 os_interrupt.o(i.osDisableInterruptMask)
|
|
||||||
Image$$SEC_RO$$Limit 0x00018a44 Number 0 anon$$obj.o(linker$$defined$$symbols)
|
|
||||||
Image$$RW$$Base 0x8ffe8000 Number 0 anon$$obj.o(linker$$defined$$symbols)
|
|
||||||
Image$$ZI$$ZI$$Base 0x8ffe8000 Number 0 anon$$obj.o(linker$$defined$$symbols)
|
|
||||||
Image$$ZI$$ZI$$Limit 0x8ffe8000 Number 0 anon$$obj.o(linker$$defined$$symbols)
|
|
||||||
|
|
||||||
|
|
||||||
================================================================================
|
================================================================================
|
||||||
|
|
||||||
Memory Map of the image
|
Memory Map of the image
|
||||||
|
|
||||||
Image Entry point : 0x00010000
|
Image entry point : Not specified.
|
||||||
|
|
||||||
Load Region LOAD_NORMAL (Base: 0x00010000, Size: 0x000000c8, Max: 0x00001000, ABSOLUTE)
|
Load Region LOAD_STATIC (Base: 0x00000000, Size: 0x00020000, Max: 0x00020000, ABSOLUTE)
|
||||||
|
|
||||||
Execution Region STUP_ENTRY (Base: 0x00010000, Size: 0x000000c8, Max: 0xffffffff, ABSOLUTE)
|
Execution Region STUP_ENTRY (Base: 0x00000000, Size: 0x00020000, Max: 0xffffffff, ABSOLUTE)
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
Base Addr Size Type Attr Idx E Section Name Object
|
||||||
|
|
||||||
0x00010000 0x000000c8 Code RO 3 * .emb_text crt0.o
|
0x00000000 0x00020000 Code RO 1 .emb_text crt0.o
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Load Region LOAD_UNABORT (Base: 0x00011000, Size: 0x0000049c, Max: 0x00007000, ABSOLUTE)
|
|
||||||
|
|
||||||
Execution Region NML_RO (Base: 0x00011000, Size: 0x00000158, Max: 0xffffffff, ABSOLUTE)
|
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
|
|
||||||
0x00011000 0x0000014e Code RO 256 .emb_text crt0_excp.o
|
|
||||||
0x0001114e 0x00000008 Code RO 322 i.osDisableInterrupts os_interrupt.o(Release\libos.brom.thumb.a)
|
|
||||||
|
|
||||||
|
|
||||||
Execution Region RO (Base: 0x00011158, Size: 0x00000344, Max: 0xffffffff, ABSOLUTE)
|
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
|
|
||||||
0x00011158 0x00000010 Code RO 626 .text memcpy.o(c_t__un.l)
|
|
||||||
0x00011168 0x00000074 Code RO 628 .text rt_memcpy_w_mpc.o(c_t__un.l)
|
|
||||||
0x000111dc 0x000000d4 Code RO 630 .text rt_memcpy.o(c_t__un.l)
|
|
||||||
0x000112b0 0x000001ec Code RO 229 i.stupInitMMUTable crt0_secure.o
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Load Region LOAD_SECURE (Base: 0x00018000, Size: 0x00000a44, Max: 0x00008000, ABSOLUTE)
|
|
||||||
|
|
||||||
Execution Region SEC_RO (Base: 0x00018000, Size: 0x00000a44, Max: 0xffffffff, ABSOLUTE)
|
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
|
|
||||||
0x00018000 0x000003d0 Code RO 228 .emb_text crt0_secure.o
|
|
||||||
0x000183d0 0x0000002c Code RO 269 .emb_text os_system.o(Release\libos.brom.thumb.a)
|
|
||||||
0x000183fc 0x000000c0 Code RO 319 .emb_text os_interrupt.o(Release\libos.brom.thumb.a)
|
|
||||||
0x000184bc 0x00000270 Code RO 546 .emb_text os_cache.o(Release\libos.brom.thumb.a)
|
|
||||||
0x0001872c 0x00000220 Code RO 594 .emb_text os_mmu.o(Release\libos.brom.thumb.a)
|
|
||||||
0x0001894c 0x00000068 Code RO 302 i.i_osFinalize os_boot.o(Release\libos.brom.thumb.a)
|
|
||||||
0x000189b4 0x00000040 Code RO 337 i.osClearInterruptPendingMask os_interrupt.o(Release\libos.brom.thumb.a)
|
|
||||||
0x000189f4 0x00000040 Code RO 333 i.osDisableInterruptMask os_interrupt.o(Release\libos.brom.thumb.a)
|
|
||||||
0x00018a34 0x00000010 Data RO 303 .constdata os_boot.o(Release\libos.brom.thumb.a)
|
|
||||||
|
|
||||||
|
|
||||||
Execution Region RW (Base: 0x8ffe8000, Size: 0x00000000, Max: 0x00008000, ABSOLUTE)
|
|
||||||
|
|
||||||
**** No section assigned to this execution region ****
|
|
||||||
|
|
||||||
|
|
||||||
Execution Region ZI (Base: 0x8ffe8000, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
|
|
||||||
|
|
||||||
**** No section assigned to this execution region ****
|
|
||||||
|
|
||||||
|
|
||||||
Execution Region BUF_OVER_BARRIER (Base: 0x8fff0000, Size: 0x00000000, Max: 0x00000000, ABSOLUTE, UNINIT)
|
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
|
|
||||||
0x8fff0000 0x00000000 Zero RW 1 BUF_OVER_BARRIER.bss anon$$obj.o
|
|
||||||
|
|
||||||
|
|
||||||
Execution Region TO_FIRM (Base: 0x8fffa000, Size: 0x00004000, Max: 0x00004000, ABSOLUTE, UNINIT)
|
|
||||||
|
|
||||||
Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
|
|
||||||
0x8fffa000 0x00004000 Zero RW 2 TO_FIRM.bss anon$$obj.o
|
|
||||||
|
|
||||||
|
|
||||||
================================================================================
|
================================================================================
|
||||||
@ -255,41 +44,16 @@ Image component sizes
|
|||||||
|
|
||||||
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
|
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
|
||||||
|
|
||||||
200 20 0 0 0 7356 crt0.o
|
131072 131072 0 0 0 7016 crt0.o
|
||||||
334 62 0 0 0 524 crt0_excp.o
|
|
||||||
1468 180 0 0 0 1336 crt0_secure.o
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
2002 262 0 0 16384 9216 Object Totals
|
131072 131072 0 0 0 7016 Object Totals
|
||||||
0 0 0 0 16384 0 (incl. Generated)
|
0 0 0 0 0 0 (incl. Generated)
|
||||||
0 0 0 0 0 0 (incl. Padding)
|
0 0 0 0 0 0 (incl. Padding)
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
|
0 0 0 0 0 0 Library Totals
|
||||||
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
|
0 0 0 0 0 0 (incl. Padding)
|
||||||
|
|
||||||
16 0 0 0 0 0 memcpy.o
|
|
||||||
104 4 16 0 0 576 os_boot.o
|
|
||||||
624 0 0 0 0 536 os_cache.o
|
|
||||||
328 12 0 0 0 3352 os_interrupt.o
|
|
||||||
544 8 0 0 0 368 os_mmu.o
|
|
||||||
44 0 0 0 0 356 os_system.o
|
|
||||||
212 0 0 0 0 0 rt_memcpy.o
|
|
||||||
116 0 0 0 0 0 rt_memcpy_w_mpc.o
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
|
||||||
1990 24 16 0 0 5188 Library Totals
|
|
||||||
2 0 0 0 0 0 (incl. Padding)
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
|
|
||||||
|
|
||||||
1644 24 16 0 0 5188 Release\libos.brom.thumb.a
|
|
||||||
344 0 0 0 0 0 c_t__un.l
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
|
||||||
1990 24 16 0 0 5188 Library Totals
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
|
|
||||||
@ -298,14 +62,14 @@ Image component sizes
|
|||||||
|
|
||||||
Code (inc. data) RO Data RW Data ZI Data Debug
|
Code (inc. data) RO Data RW Data ZI Data Debug
|
||||||
|
|
||||||
3992 286 16 0 16384 14404 Grand Totals
|
131072 131072 0 0 0 7016 Grand Totals
|
||||||
3992 286 16 0 16384 14404 Image Totals
|
131072 131072 0 0 0 7016 Image Totals
|
||||||
|
|
||||||
================================================================================
|
================================================================================
|
||||||
|
|
||||||
Total RO Size (Code + RO Data) 4008 ( 3.91kB)
|
Total RO Size (Code + RO Data) 131072 ( 128.00kB)
|
||||||
Total RW Size (RW Data + ZI Data) 16384 ( 16.00kB)
|
Total RW Size (RW Data + ZI Data) 0 ( 0.00kB)
|
||||||
Total ROM Size (Code + RO Data + RW Data) 4008 ( 3.91kB)
|
Total ROM Size (Code + RO Data + RW Data) 131072 ( 128.00kB)
|
||||||
|
|
||||||
================================================================================
|
================================================================================
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user