mirror of
https://github.com/rvtr/ctr_firmware.git
synced 2025-10-31 07:51:08 -04:00
割り込みライブラリ追加。
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@88 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima
parent
63c169ea3c
commit
450a4db341
@ -29,6 +29,8 @@ SRCDIR = . ../common
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SRCS = \
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os_timer.c \
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os_interrupt.c \
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os_interrupt_common.c \
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TARGET_LIB = libos$(BROM_LIBSUFFIX).a
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280
trunk/bootrom/build/libraries/os/ARM11/os_interrupt.c
Normal file
280
trunk/bootrom/build/libraries/os/ARM11/os_interrupt.c
Normal file
@ -0,0 +1,280 @@
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/*---------------------------------------------------------------------------*
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Project: CtrBrom - libraries - OS
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File: os_interrupt.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/os.h>
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/*---------------------------------------------------------------------------*
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Name: osInitInterrupt
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Description: Initialize Interrupts
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void osInitInterrupt( void )
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{
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static BOOL isInit;
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if ( isInit == FALSE )
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{
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isInit = TRUE;
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(void)osDisableIrqAndFiq();
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osInitInterruptTable();
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{
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u32 num = OS_INTR_ID_NUM;
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u32 conf = 0;
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int i;
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for ( i=0; i<MATH_ROUNDUP(num, 32)/32; i++ )
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{
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reg_OS_IDR_CLR_IE[i] = HW_IDR_WORD_MASK;
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reg_OS_IDR_CLR_PND[i] = HW_IDR_WORD_MASK;
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}
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for ( i=0; i<num; i++ )
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{
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reg_OS_IDR_TGT[i] = REG_OS_IDR_TGT0_C0_MASK;
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reg_OS_IDR_PRIO[i] = OS_IDR_INTR_PRIO_DEFAULT << 4;
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}
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for ( i=0; i<32; i+=2 )
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{
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conf |= (HW_IDR_INTR_RISE_EDGE | HW_IDR_INTR_1_N_MODEL) << i;
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}
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for ( i=0; i<MATH_ROUNDUP(num, 16)/16; i++ )
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{
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reg_OS_IDR_CFG[i] = conf;
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}
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}
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reg_OS_IDR_CNT = REG_OS_IDR_CNT_E_MASK;
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reg_OS_CPUI_PRIO = 15 << REG_OS_CPUI_PRIO_THLD_SHIFT;
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reg_OS_CPUI_BP = REG_OS_CPUI_BP_DECI_MASK;
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reg_OS_CPUI_CNT = REG_OS_CPUI_CNT_E_MASK;
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}
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}
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/*---------------------------------------------------------------------------*
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Name: osEnableInterruptID
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Description: set Interrupt Set Enable Register
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Arguments: Interrupt Distributor ID
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Returns: TRUE if last state is enabled
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*---------------------------------------------------------------------------*/
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BOOL osEnableInterruptID( OSIntrID id )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_IE[ofs] >> sft);
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reg_OS_IDR_SET_IE[ofs] = 1 << sft;
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osDisableInterruptID
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Description: set Interrupt Clear Enable Register
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Arguments: Interrupt Distributor ID
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Returns: TRUE if last state is enabled
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*---------------------------------------------------------------------------*/
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BOOL osDisableInterruptID( OSIntrID id )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_IE[ofs] >> sft);
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reg_OS_IDR_CLR_IE[ofs] = 1 << sft;
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osRestoreInterruptID
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Description: set Interrupt Clear Enable Register
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Arguments: id : Interrupt Distributor ID
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state : state whether interrupt is enabled
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Returns: TRUE if last state is enabled
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*---------------------------------------------------------------------------*/
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BOOL osRestoreInterruptID( OSIntrID id, BOOL state )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_IE[ofs] >> sft);
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if ( state == TRUE )
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{
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reg_OS_IDR_SET_IE[ofs] = 1 << sft;
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}
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else
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{
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reg_OS_IDR_CLR_IE[ofs] = 1 << sft;
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}
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osSetInterruptPending
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Description: set Interrupt Set Pending Register
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Arguments: Interrupt Distributor ID
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Returns: TRUE if last state is pending
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*---------------------------------------------------------------------------*/
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BOOL osSetInterruptPending( OSIntrID id )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_PND[ofs] >> sft);
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reg_OS_IDR_SET_PND[ofs] = 1 << sft;
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osClearInterruptPending
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Description: set Interrupt Clear Pending Register
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Arguments: Interrupt Distributor ID
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Returns: TRUE if last state is pending
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*---------------------------------------------------------------------------*/
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BOOL osClearInterruptPending( OSIntrID id )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_PND[ofs] >> sft);
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reg_OS_IDR_CLR_PND[ofs] = 1 << sft;
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osRestoreInterruptPending
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Description: restore Interrupt Pending
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Arguments: id : Interrupt Distributor ID
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state : state whether interrupt is enabled
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Returns: TRUE if last state is pending
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*---------------------------------------------------------------------------*/
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BOOL osRestoreInterruptPending( OSIntrID id, BOOL state )
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{
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_PND[ofs] >> sft);
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if ( state == TRUE )
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{
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reg_OS_IDR_SET_PND[ofs] = 1 << sft;
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}
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else
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{
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reg_OS_IDR_CLR_PND[ofs] = 1 << sft;
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}
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return retval;
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}
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/*---------------------------------------------------------------------------*
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Name: osSetEndOfInterruptRegister
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Description: set ID to End of Interrupt Register
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change state to Inactive.
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Arguments: Interrupt Distributor ID
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Returns: None
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*---------------------------------------------------------------------------*/
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void osSetEndOfInterruptRegister( OSIntrID id )
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{
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reg_OS_CPUI_EOI = id;
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}
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/*---------------------------------------------------------------------------*
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Name: i_osReadHighestPendingInterruptRegister
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Description: read ID from Highest Pending Interrupt Register
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Arguments: None
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Returns: Interrupt Distributor ID
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*---------------------------------------------------------------------------*/
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OSIntrID i_osReadHighestPendingInterruptRegister( void )
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{
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return (OSIntrID)(reg_OS_CPUI_HI_PND & REG_OS_CPUI_HI_PND_ID_MASK);
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}
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/*---------------------------------------------------------------------------*
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Name: i_osReadInterruptAcknowledgeRegister
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Description: read ID from Interrupt Acknowledge Register
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get interrupt ID and change state to NotPending and Active.
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Arguments: None
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Returns: Interrupt Distributor ID
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*---------------------------------------------------------------------------*/
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OSIntrID i_osReadInterruptAcknowledgeRegister( void )
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{
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return (OSIntrID)(reg_OS_CPUI_ACK & REG_OS_CPUI_ACK_ID_MASK);
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}
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@ -15,7 +15,6 @@
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/os.h>
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#include <brom/memorymap.h>
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void timer_handler(void);
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@ -31,8 +31,10 @@ BROM_PROC = ARM9
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SRCDIR = . ../common
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SRCS = \
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os_tick.c \
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os_interrupt.c \
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os_timer.c \
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os_tick.c \
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os_interrupt_common.c \
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TARGET_LIB = libos_sp$(BROM_LIBSUFFIX).a
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374
trunk/bootrom/build/libraries/os/ARM9/os_interrupt.c
Normal file
374
trunk/bootrom/build/libraries/os/ARM9/os_interrupt.c
Normal file
@ -0,0 +1,374 @@
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/*---------------------------------------------------------------------------*
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Project: CtrBrom - libraries - OS
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File: os_interrupt.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
|
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proprietary information of Nintendo of America Inc. and/or Nintendo
|
||||
Company Ltd., and are protected by Federal copyright law. They may
|
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not be disclosed to third parties or copied or duplicated in any form,
|
||||
in whole or in part, without the prior written consent of Nintendo.
|
||||
|
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/os.h>
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/*---------------------------------------------------------------------------*
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Name: osInitInterrupt
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Description: Initialize Interrupts
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void osInitInterrupt( void )
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{
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static BOOL isInit;
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if ( isInit == FALSE )
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{
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isInit = TRUE;
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(void)osDisableIrqAndFiq();
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i_osInitInterruptTable();
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reg_OS_IE = 0;
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reg_OS_IF = 0xffffffff;
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(void)osEnableInterrupts();
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}
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}
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//================================================================================
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// InterruptMask
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//================================================================================
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/*---------------------------------------------------------------------------*
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Name: osSetInterruptMask
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Description: set interrupt factor
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Arguments: mask interrupt factor
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Returns: previous factors
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*---------------------------------------------------------------------------*/
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OSIntrMask osSetInterruptMask( OSIntrMask mask )
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{
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OSIntrMode enabled = osDisableInterrupts();
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#ifdef SDK_ARM9
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OSIntrMask prep = reg_OS_IE;
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reg_OS_IE = mask;
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#else // MPCORE
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OSIntrMask prep = reg_OS_IDR_SET_ENABLE_ST;
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reg_OS_IDR_CLR_ENABLE_WP[0] = HW_IDR_WORD_MASK;
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reg_OS_IDR_CLR_ENABLE_WP[1] = HW_IDR_WORD_MASK;
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reg_OS_IDR_CLR_ENABLE_WP[2] = HW_IDR_WORD_MASK;
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reg_OS_IDR_SET_ENABLE_ST = mask;
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#endif // MPCORE
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(void)osRestoreInterrupts( enabled );
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return prep;
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}
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/*---------------------------------------------------------------------------*
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Name: osEnableInterruptMask
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Description: set specified interrupt factor
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Arguments: mask interrupt factor
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Returns: previous factors
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*---------------------------------------------------------------------------*/
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OSIntrMask osEnableInterruptMask( OSIntrMask mask )
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{
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OSIntrMode enabled = osDisableInterrupts();
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#ifdef SDK_ARM9
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OSIntrMask prep = reg_OS_IE;
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reg_OS_IE = prep | mask;
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#else // MPCORE
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OSIntrMask prep = reg_OS_IDR_SET_ENABLE_ST;
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reg_OS_IDR_SET_ENABLE_ST = mask;
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#endif // MPCORE
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(void)osRestoreInterrupts( enabled );
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return prep;
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}
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/*---------------------------------------------------------------------------*
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Name: osDisableInterruptMask
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Description: unset specified interrupt factor
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Arguments: mask interrupt factor
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Returns: previous factors
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*---------------------------------------------------------------------------*/
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OSIntrMask osDisableInterruptMask( OSIntrMask mask )
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{
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OSIntrMode enabled = osDisableInterrupts();
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#ifdef SDK_ARM9
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OSIntrMask prep = reg_OS_IE;
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reg_OS_IE = prep & ~mask;
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#else // MPCORE
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OSIntrMask prep = reg_OS_IDR_CLR_ENABLE_ST;
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reg_OS_IDR_CLR_ENABLE_ST = mask;
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#endif // MPCORE
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(void)osRestoreInterrupts( enabled );
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return prep;
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}
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/*---------------------------------------------------------------------------*
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Name: osEnableInterruptID
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Description: set Interrupt Set Enable Register
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Arguments: Interrupt Distributor ID
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Returns: TRUE if last state is enabled
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*---------------------------------------------------------------------------*/
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BOOL osEnableInterruptID( OSIntrID id )
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{
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OSIntrMode enabled = osDisableInterrupts();
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#ifdef SDK_ARM9
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OSIntrMask prep = reg_OS_IE;
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BOOL retval;
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retval = TRUE & (BOOL)(prep >> id);
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reg_OS_IE = prep | (1 << id);
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#else // MPCORE
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u32 ofs = id/32;
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u32 sft = id%32;
|
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BOOL retval;
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retval = TRUE & (reg_OS_IDR_SET_ENABLE_WP[ofs] >> sft);
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reg_OS_IDR_SET_ENABLE_WP[ofs] = 1 << sft;
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#endif // MPCORE
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(void)osRestoreInterrupts( enabled );
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return retval;
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}
|
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|
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/*---------------------------------------------------------------------------*
|
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Name: osDisableInterruptID
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|
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Description: set Interrupt Clear Enable Register
|
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|
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Arguments: Interrupt Distributor ID
|
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|
||||
Returns: TRUE if last state is enabled
|
||||
*---------------------------------------------------------------------------*/
|
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|
||||
BOOL osDisableInterruptID( OSIntrID id )
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{
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OSIntrMode enabled = osDisableInterrupts();
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#ifdef SDK_ARM9
|
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OSIntrMask prep = reg_OS_IE;
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BOOL retval;
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retval = TRUE & (BOOL)(prep >> id);
|
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reg_OS_IE = prep & ~(1 << id);
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#else // MPCORE
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u32 ofs = id/32;
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u32 sft = id%32;
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BOOL retval;
|
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|
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retval = TRUE & (reg_OS_IDR_SET_ENABLE_WP[ofs] >> sft);
|
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reg_OS_IDR_CLR_ENABLE_WP[ofs] = 1 << sft;
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#endif // MPCORE
|
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(void)osRestoreInterrupts( enabled );
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|
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return retval;
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}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreInterruptID
|
||||
|
||||
Description: set Interrupt Clear Enable Register
|
||||
|
||||
Arguments: id : Interrupt Distributor ID
|
||||
state : state whether interrupt is enabled
|
||||
|
||||
Returns: TRUE if last state is enabled
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
BOOL osRestoreInterruptID( OSIntrID id, BOOL state )
|
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{
|
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OSIntrMode enabled = osDisableInterrupts();
|
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#ifdef SDK_ARM9
|
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OSIntrMask prep = reg_OS_IE;
|
||||
BOOL retval;
|
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|
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retval = TRUE & (BOOL)(prep >> id);
|
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if ( state == TRUE )
|
||||
{
|
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reg_OS_IE = prep | (state << id);
|
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}
|
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else
|
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{
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reg_OS_IE = prep & ~(state << id);
|
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}
|
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#else // MPCORE
|
||||
u32 ofs = id/32;
|
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u32 sft = id%32;
|
||||
BOOL retval;
|
||||
|
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retval = TRUE & (reg_OS_IDR_SET_ENABLE_WP[ofs] >> sft);
|
||||
|
||||
if ( state == TRUE )
|
||||
{
|
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reg_OS_IDR_SET_ENABLE_WP[ofs] = 1 << sft;
|
||||
}
|
||||
else
|
||||
{
|
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reg_OS_IDR_CLR_ENABLE_WP[ofs] = 1 << sft;
|
||||
}
|
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#endif // MPCORE
|
||||
(void)osRestoreInterrupts( enabled );
|
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|
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return retval;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// INTERRUPT PENDING
|
||||
//================================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osClearInterruptPendingMask
|
||||
|
||||
Description: reset IF bit
|
||||
(setting bit causes to clear bit for interrupt)
|
||||
|
||||
Arguments: mask interrupt factor
|
||||
|
||||
Returns: previous factors
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
OSIntrMask osClearInterruptPendingMask( OSIntrMask mask )
|
||||
{
|
||||
OSIntrMode enabled = osDisableInterrupts();
|
||||
#ifdef SDK_ARM9
|
||||
OSIntrMask prep = reg_OS_IF;
|
||||
reg_OS_IF = mask;
|
||||
#else // MPCORE
|
||||
OSIntrMask prep = reg_OS_IDR_SET_PENDING_ST;
|
||||
reg_OS_IDR_CLR_PENDING_ST = mask;
|
||||
#endif // MPCORE
|
||||
(void)osRestoreInterrupts( enabled );
|
||||
|
||||
return prep;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osClearInterruptPendingID
|
||||
|
||||
Description: set Interrupt Clear Pending Register
|
||||
|
||||
Arguments: Interrupt Distributor ID
|
||||
|
||||
Returns: TRUE if last state is pending
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
BOOL osClearInterruptPendingID( OSIntrID id )
|
||||
{
|
||||
OSIntrMode enabled = osDisableInterrupts();
|
||||
#ifdef SDK_ARM9
|
||||
OSIntrMask prep = reg_OS_IF;
|
||||
BOOL retval;
|
||||
|
||||
retval = TRUE & (BOOL)(prep >> id);
|
||||
reg_OS_IF = (u32)(1 << id);
|
||||
#else // MPCORE
|
||||
u32 ofs = id/32;
|
||||
u32 sft = id%32;
|
||||
BOOL retval;
|
||||
|
||||
retval = TRUE & (reg_OS_IDR_SET_PENDING_WP[ofs] >> sft);
|
||||
reg_OS_IDR_CLR_PENDING_WP[ofs] = 1 << sft;
|
||||
#endif // MPCORE
|
||||
(void)osRestoreInterrupts( enabled );
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// IRQ CHEKE BUFFER
|
||||
//================================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osSetInterruptCheckFlag
|
||||
|
||||
Description: set irq flag to check being called
|
||||
|
||||
Arguments: irq factors to be set
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osSetInterruptCheckFlag( OSIntrMask mask )
|
||||
{
|
||||
OSIntrMode enabled = osDisableInterrupts();
|
||||
*(vu32 *)HW_INTR_CHECK_BUF |= (u32)mask;
|
||||
(void)osRestoreInterrupts( enabled );
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osClearInterruptCheckFlag
|
||||
|
||||
Description: clear irq flag stored in HW_INTR_CHECK_BUF
|
||||
|
||||
Arguments: irq factors to be cleared
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osClearInterruptCheckFlag( OSIntrMask mask )
|
||||
{
|
||||
OSIntrMode enabled = osDisableInterrupts();
|
||||
*(vu32 *)HW_INTR_CHECK_BUF &= (u32)~mask;
|
||||
(void)osRestoreInterrupts( enabled );
|
||||
}
|
||||
|
||||
//============================================================================
|
||||
// WAIT
|
||||
//============================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osWaitInterrupt
|
||||
|
||||
Description: wait specifiled interrupt.
|
||||
OS_WaitInterrupt doesn't switch thread.
|
||||
OS_WaitInterrupt wait by using OS_Halt().
|
||||
|
||||
Arguments: clear TRUE if want to clear interrupt flag before wait.
|
||||
FALSE if not.
|
||||
irqFlags bit of interrupts to wait for
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osWaitInterrupt( BOOL clear, OSIntrMask irqFlags )
|
||||
{
|
||||
OSIntrMode cpsrIrq = osDisableInterrupts();
|
||||
|
||||
if (clear)
|
||||
{
|
||||
(void)osClearInterruptCheckFlag( irqFlags );
|
||||
}
|
||||
|
||||
while (!(osGetInterruptCheckFlag() & irqFlags))
|
||||
{
|
||||
i_osHalt();
|
||||
(void)osEnableInterrupts();
|
||||
(void)osDisableInterrupts();
|
||||
}
|
||||
|
||||
(void)osClearInterruptCheckFlag( irqFlags );
|
||||
(void)osRestoreInterrupts( cpsrIrq );
|
||||
}
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
$Author$
|
||||
*---------------------------------------------------------------------------*/
|
||||
#include <brom/os.h>
|
||||
#include <brom/memorymap.h>
|
||||
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
@ -72,7 +71,6 @@ void osInitTick(void)
|
||||
|
||||
//---- set interrupt callback
|
||||
osSetInterruptHandler( OS_INTR_ID_TIMER3, i_osCountUpTick );
|
||||
osSetMultiInterruptMask( OS_INTR_ID_TIMER3, (OSIntrMask)0xffffffff ); // ？, osInitTimerの真似
|
||||
|
||||
//---- enable timer interrupt
|
||||
osEnableInterruptID(OSi_TICK_IE_TIMER_ID);
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
$Author$
|
||||
*---------------------------------------------------------------------------*/
|
||||
#include <brom/os.h>
|
||||
#include <brom/memorymap.h>
|
||||
|
||||
void timer_handler(void);
|
||||
|
||||
@ -58,7 +57,6 @@ void osInitTimer( void )
|
||||
OSIntrMask imask = 0xffffffff;
|
||||
|
||||
osSetInterruptHandler( OS_INTR_ID_TIMER1, timer_handler );
|
||||
osSetMultiInterruptMask( OS_INTR_ID_TIMER1, imask );
|
||||
}
|
||||
|
||||
osEnableInterruptID( OS_INTR_ID_TIMER1 );
|
||||
|
||||
400
trunk/bootrom/build/libraries/os/common/os_interrupt_common.c
Normal file
400
trunk/bootrom/build/libraries/os/common/os_interrupt_common.c
Normal file
@ -0,0 +1,400 @@
|
||||
/*---------------------------------------------------------------------------*
|
||||
Project: CtrBrom - libraries - OS
|
||||
File: os_interrupt_common.c
|
||||
|
||||
Copyright 2008 Nintendo. All rights reserved.
|
||||
|
||||
These coded instructions, statements, and computer programs contain
|
||||
proprietary information of Nintendo of America Inc. and/or Nintendo
|
||||
Company Ltd., and are protected by Federal copyright law. They may
|
||||
not be disclosed to third parties or copied or duplicated in any form,
|
||||
in whole or in part, without the prior written consent of Nintendo.
|
||||
|
||||
$Date:: $
|
||||
$Rev$
|
||||
$Author$
|
||||
*---------------------------------------------------------------------------*/
|
||||
#include <brom/os.h>
|
||||
|
||||
|
||||
#ifdef SDK_ARM11
|
||||
OSIntrFunction osIntrTable[OS_INTR_ID_NUM];
|
||||
#else // SDK_ARM9
|
||||
OSIntrFunction osIntrTable[OS_INTR_ID_NUM] ATTRIBUTE_SECTION(.dtcm);
|
||||
#endif // SDK_ARM9
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: i_osInitInterruptTable
|
||||
|
||||
Description: Initialize InterruptTable
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void i_osInitInterruptTable( void )
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<OS_INTR_ID_NUM; i++)
|
||||
{
|
||||
osIntrTable[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osSetInterruptHandler
|
||||
|
||||
Description: Set interrupt handler
|
||||
|
||||
Arguments: interrupt ID
|
||||
interrupt handler
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void osSetInterruptHandler( OSIntrID id, OSIntrFunction handler )
|
||||
{
|
||||
osIntrTable[id] = handler;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osGetInterruptHandler
|
||||
|
||||
Description: Get interrupt handler
|
||||
|
||||
Arguments: interrupt ID
|
||||
interrupt handler
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
OSIntrFunction osGetInterruptHandler( OSIntrID id )
|
||||
{
|
||||
return osIntrTable[id];
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableInterrupts
|
||||
|
||||
Description: Set CPSR to enable irq and fiq interrupts
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
OSIntrMode osEnableInterrupts( void )
|
||||
{
|
||||
return osEnableIrq();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableInterrupts
|
||||
|
||||
Description: Set CPSR to disable irq and fiq interrupts
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
OSIntrMode osDisableInterrupts( void )
|
||||
{
|
||||
return osDisableIrq();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreInterrupts
|
||||
|
||||
Description: Restore CPSR irq and fiq interrupts
|
||||
|
||||
Arguments: state of irq interrupt bit
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
OSIntrMode osRestoreInterrupts( OSIntrMode state )
|
||||
{
|
||||
return osRestoreIrq( state );
|
||||
}
|
||||
|
||||
#include <brom/code32.h>
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osHaltUntilInterrupt
|
||||
|
||||
Description: Halt CPU Core until Interrupt
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osHaltUntilInterrupt( void )
|
||||
{
|
||||
PRESERVE8
|
||||
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c0, 4
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
#ifdef SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osHaltUntilEvent
|
||||
|
||||
Description: Halt CPU Core until Event
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osHaltUntilEvent( void )
|
||||
{
|
||||
wfe
|
||||
bx lr
|
||||
}
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
|
||||
//============================================================================
|
||||
// Control the master of all interrupts
|
||||
//============================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableIrq
|
||||
|
||||
Description: Set CPSR to enable irq interrupt
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osEnableIrq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsie i
|
||||
#else
|
||||
bic r1, r0, #HW_PSR_IRQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_IRQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableIrq
|
||||
|
||||
Description: Set CPSR to disable irq interrupt
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osDisableIrq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsid i
|
||||
#else
|
||||
orr r1, r0, #HW_PSR_IRQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_IRQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreIrq
|
||||
|
||||
Description: Restore CPSR irq interrupt
|
||||
|
||||
Arguments: state of irq and fiq interrupt bit
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osRestoreIrq( OSIntrMode state )
|
||||
{
|
||||
mrs r1, cpsr
|
||||
bic r2, r1, #HW_PSR_IRQ_DISABLE
|
||||
orr r2, r2, r0
|
||||
msr cpsr_c, r2
|
||||
and r0, r1, #HW_PSR_IRQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableFiq
|
||||
|
||||
Description: Set CPSR to enable fiq interrupt
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osEnableFiq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsie f
|
||||
#else
|
||||
bic r1, r0, #HW_PSR_FIQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableFiq
|
||||
|
||||
Description: Set CPSR to disable fiq interrupt
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osDisableFiq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsid f
|
||||
#else
|
||||
orr r1, r0, #HW_PSR_FIQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreFiq
|
||||
|
||||
Description: Restore CPSR fiq interrupt
|
||||
|
||||
Arguments: state of fiq interrupt bit
|
||||
|
||||
Returns: last state of HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osRestoreFiq( OSIntrMode state )
|
||||
{
|
||||
mrs r1, cpsr
|
||||
bic r2, r1, #HW_PSR_FIQ_DISABLE
|
||||
orr r2, r2, r0
|
||||
msr cpsr_c, r2
|
||||
and r0, r1, #HW_PSR_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableIrqAndFiq
|
||||
|
||||
Description: Set CPSR to enable irq and fiq interrupts
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osEnableIrqAndFiq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsie if
|
||||
#else
|
||||
bic r1, r0, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableIrqAndFiq
|
||||
|
||||
Description: Set CPSR to disable irq and fiq interrupts
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osDisableIrqAndFiq( void )
|
||||
{
|
||||
mrs r0, cpsr
|
||||
|
||||
#ifdef SDK_USE_MPCORE_EXTEND_OP
|
||||
cpsid if
|
||||
#else
|
||||
orr r1, r0, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
msr cpsr_c, r1
|
||||
#endif
|
||||
|
||||
and r0, r0, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreIrqAndFiq
|
||||
|
||||
Description: Restore CPSR irq and fiq interrupts
|
||||
|
||||
Arguments: state of irq and fiq interrupt bit
|
||||
|
||||
Returns: last state of HW_PSR_IRQ_DISABLE & HW_PSR_FIQ_DISABLE
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM OSIntrMode osRestoreIrqAndFiq( OSIntrMode state )
|
||||
{
|
||||
mrs r1, cpsr
|
||||
bic r2, r1, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
orr r2, r2, r0
|
||||
msr cpsr_c, r2
|
||||
and r0, r1, #HW_PSR_IRQ_FIQ_DISABLE
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
#include <brom/codereset.h>
|
||||
|
||||
@ -27,11 +27,11 @@ extern "C" {
|
||||
#define OS_IDR_INTR_PRIO_DEFAULT 8 // Interrupt priority default (0-15)
|
||||
|
||||
|
||||
extern OSIntrFunction osIntrDistrTable[OS_INTR_DISTR_ID_LIMIT];
|
||||
extern OSIntrFunction osIntrTable[OS_INTR_ID_NUM];
|
||||
|
||||
|
||||
OSIntrID osi_ReadHighestPendingInterruptRegister( void );
|
||||
OSIntrID osi_ReadInterruptAcknowledgeRegister( void );
|
||||
OSIntrID i_osReadHighestPendingInterruptRegister( void );
|
||||
OSIntrID i_osReadInterruptAcknowledgeRegister( void );
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
|
||||
@ -24,10 +24,28 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define reg_OS_IDR_SET_IE (( REGType32v *) REG_IDR_SET_IE0_ADDR)
|
||||
#define reg_OS_IDR_CLR_IE (( REGType32v *) REG_IDR_CLR_IE0_ADDR)
|
||||
#define reg_OS_IDR_SET_PND (( REGType32v *) REG_IDR_SET_PND0_ADDR)
|
||||
#define reg_OS_IDR_CLR_PND (( REGType32v *) REG_IDR_CLR_PND0_ADDR)
|
||||
#define reg_OS_IDR_ACT (( REGType32v *) REG_IDR_ACT0_ADDR)
|
||||
#define reg_OS_IDR_TGT (( REGType8v *) REG_IDR_TGT0_ADDR)
|
||||
#define reg_OS_IDR_PRIO (( REGType8v *) REG_IDR_PRIO0_ADDR)
|
||||
#define reg_OS_IDR_CFG (( REGType32v *) REG_IDR_CFG0_ADDR)
|
||||
|
||||
#define HW_IDR_WORD_MASK (~0)
|
||||
|
||||
// Interrupt configuration registers
|
||||
|
||||
#define HW_IDR_INTR_RISE_EDGE 0x2 // The interrupt line is rising edge sensitive
|
||||
#define HW_IDR_INTR_LEVEL_HIGH 0x0 // level high active
|
||||
#define HW_IDR_INTR_1_N_MODEL 0x1 // The interrupt line uses the 1-N software model
|
||||
#define HW_IDR_INTR_N_N_MODEL 0x0 // the N-N software model
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 w[3];
|
||||
u32 w[6];
|
||||
}
|
||||
OSIntrMask;
|
||||
|
||||
@ -56,9 +74,9 @@ typedef enum
|
||||
OS_INTR_ID_TIMER = REG_OS_IDR_SET_IE0_TM_SHIFT, // 29
|
||||
OS_INTR_ID_WATCHDOG = REG_OS_IDR_SET_IE0_WDOG_SHIFT, // 30
|
||||
|
||||
OS_INTR_DISTR_ID_MIN = OS_INTR_ID_IPI_MIN,
|
||||
OS_INTR_DISTR_ID_MAX = (32*5) + REG_OS_IDR_SET_IE5_PMUIRQ7_SHIFT,
|
||||
OS_INTR_DISTR_ID_LIMIT
|
||||
OS_INTR_ID_MIN = OS_INTR_ID_IPI_MIN,
|
||||
OS_INTR_ID_MAX = (32*5) + REG_OS_IDR_SET_IE5_PMUIRQ7_SHIFT,
|
||||
OS_INTR_ID_NUM
|
||||
}
|
||||
OSIntrID;
|
||||
|
||||
|
||||
@ -193,21 +193,6 @@ static inline BOOL osIsInterruptPending( OSIntrID id )
|
||||
return retval;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// MULTI INTERRUPT
|
||||
//================================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osSetMultiInterruptMask
|
||||
|
||||
Description: Set interrupt mask for multi interrupt
|
||||
|
||||
Arguments: interrupt ID
|
||||
interrupt mask
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osSetMultiInterruptMask( OSIntrID id, OSIntrMask mask );
|
||||
|
||||
//================================================================================
|
||||
// INTERRUPT HANDLER
|
||||
//================================================================================
|
||||
|
||||
@ -404,7 +404,7 @@
|
||||
0x7e01310,,IDR_ACT4,32,r,OS,volatile,DS_WL,31,1,KEY,30,1,PDN,29,1,MIC,28,1,SPI2,27,1,SPI1,26,1,I2C2,25,1,I2C1,24,1,PXI_RX,19,1,PXI_TX,18,1,CPU1,17,1,CPU0,16,1,SCR2,13,1,SCR1,12,1,YUV2RGB,11,1,DSP,10,1,CAM2,9,1,CAM1,8,1,LGC_DET,6,1,LGC_IREQ,5,1,LMC,4,1,SD3_A,3,1,SD3,2,1,SD2_A,1,1,SD2,0,1,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01314,,IDR_ACT5,32,r,OS,volatile,PMUIRQ7,29,1,PMUIRQ6,28,1,PMUIRQ5,27,1,PMUIRQ4,26,1,PMUIRQ1,25,1,PMUIRQ0,24,1,DEPOP,6,1,MCU,5,1,HP,4,1,RTC,1,1,COVER,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01400,,IDR_PRIO0,8,rw,OS,volatile,PRIO,4,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01800,,IDR_TGT0,8,rw,OS,volatile,C3,1,3,C2,1,2,C1,1,1,C0,1,0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01800,,IDR_TGT0,8,rw,OS,volatile,C3,3,1,C2,2,1,C1,1,1,C0,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01c00,,IDR_CFG0,32,rw,OS,volatile,IPI15_1N,31,1,IPI15_TRG,30,1,IPI14_1N,29,1,IPI14_TRG,28,1,IPI13_1N,27,1,IPI13_TRG,26,1,IPI12_1N,25,1,IPI12_TRG,24,1,IPI11_1N,23,1,IPI11_TRG,22,1,IPI10_1N,21,1,IPI10_TRG,20,1,IPI9_1N,19,1,IPI9_TRG,18,1,IPI8_1N,17,1,IPI8_TRG,16,1,IPI7_1N,15,1,IPI7_TRG,14,1,IPI6_1N,13,1,IPI6_TRG,12,1,IPI5_1N,11,1,IPI5_TRG,10,1,IPI4_1N,9,1,IPI4_TRG,8,1,IPI3_1N,7,1,IPI3_TRG,6,1,IPI2_1N,5,1,IPI2_TRG,4,1,IPI1_1N,3,1,IPI1_TRG,2,1,IPI0_1N,1,1,IPI0_TRG,0,1
|
||||
0x7e01c04,,IDR_CFG1,32,rw,OS,volatile,WDOG_1N,29,1,WDOG_TRG,28,1,TM_1N,29,1,TM_TRG,29,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x7e01c08,,IDR_CFG2,32,rw,OS,volatile,DBG_SPI_1N,9,1,DBG_SPI_TRG,8,1,J1_TX_1N,7,1,J1_TX_TRG,6,1,J1_RX_1N,5,1,J1_RX_TRG,4,1,J0_TX_1N,3,1,J0_TX_TRG,2,1,J0_RX_1N,1,1,J0_RX_TRG,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
|
||||
|
Can't render this file because it has a wrong number of fields in line 17.
|
@ -277,21 +277,21 @@
|
||||
0x149000,,KEYINPUT,16,rw,PAD,volatile,X,11,1,Y,10,1,L,9,1,R,8,1,DOWN,7,1,UP,6,1,LEFT,5,1,RIGHT,4,1,START,3,1,SEL,2,1,B,1,1,A,0,1,,,,,,
|
||||
0x149002,,KEYCNT,16,rw,PAD,volatile,LOGIC,15,1,INTR,14,1,X,11,1,Y,10,1,L,9,1,R,8,1,DOWN,7,1,UP,6,1,LEFT,5,1,RIGHT,4,1,START,3,1,SEL,2,1,B,1,1,A,0,1
|
||||
#SPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x142000,,SPI1CNT,16,rw,SPI,volatile,E,15,1,I,14,1,SEL,12,2,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,
|
||||
0x142002,,SPI1D,8,rw,SPI,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x143000,,SPI2CNT,16,rw,SPI,volatile,E,15,1,I,14,1,SEL,12,2,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,
|
||||
0x143002,,SPI2D,8,rw,SPI,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14b000,,SPI3CNT,16,rw,SPI,volatile,E,15,1,I,14,1,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14b002,,SPI3D,8,rw,SPI,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x142000,,SPI1CNT,16,rw,SIO,volatile,E,15,1,I,14,1,SEL,12,2,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,
|
||||
0x142002,,SPI1D,8,rw,SIO,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x143000,,SPI2CNT,16,rw,SIO,volatile,E,15,1,I,14,1,SEL,12,2,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,
|
||||
0x143002,,SPI2D,8,rw,SIO,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14b000,,SPI3CNT,16,rw,SIO,volatile,E,15,1,I,14,1,MODE,11,1,CLKMODE,10,1,BUSY,7,1,BAUDRATE,0,3,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14b002,,SPI3D,8,rw,SIO,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
#I2C,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144000,,I2C1_DAT,8,rw,OS,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144001,,I2C1_CNT,8,rw,OS,volatile,E,7,1,I,6,1,RW,5,1,ACK,4,1,CNT,3,3,NT,2,1,START,1,1,STOP,0,1,,,,,,,,,,,,,,,,,,
|
||||
0x144002,,I2C1_CNT_EX,16,rw,OS,volatile,LGCY,15,1,WT,1,1,SCL,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144004,,I2C1_SCL,16,rw,OS,volatile,HI_PRD,8,5,LO_PRD,0,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145000,,I2C2_DAT,8,rw,OS,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145001,,I2C2_CNT,8,rw,OS,volatile,E,7,1,I,6,1,RW,5,1,ACK,4,1,CNT,3,3,NT,2,1,START,1,1,STOP,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145002,,I2C2_CNT_EX,16,rw,OS,volatile,LGCY,15,1,WT,1,1,SCL,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145004,,I2C2_SCL,16,rw,OS,volatile,HI_PRD,8,5,LO_PRD,0,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144000,,I2C1_DAT,8,rw,SIO,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144001,,I2C1_CNT,8,rw,SIO,volatile,E,7,1,I,6,1,RW,5,1,ACK,4,1,CNT,3,3,NT,2,1,START,1,1,STOP,0,1,,,,,,,,,,,,,,,,,,
|
||||
0x144002,,I2C1_CNT_EX,16,rw,SIO,volatile,LGCY,15,1,WT,1,1,SCL,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x144004,,I2C1_SCL,16,rw,SIO,volatile,HI_PRD,8,5,LO_PRD,0,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145000,,I2C2_DAT,8,rw,SIO,volatile,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145001,,I2C2_CNT,8,rw,SIO,volatile,E,7,1,I,6,1,RW,5,1,ACK,4,1,CNT,3,3,NT,2,1,START,1,1,STOP,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145002,,I2C2_CNT_EX,16,rw,SIO,volatile,LGCY,15,1,WT,1,1,SCL,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x145004,,I2C2_SCL,16,rw,SIO,volatile,HI_PRD,8,5,LO_PRD,0,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
#GPIO,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14a000,,RCNT0_L,16,rw,EXI,volatile,RE1,15,1,RE0,14,1,I,8,1,DIR_SO,7,1,DIR_SI,6,1,DIR_SD,5,1,DIR_SC,4,1,DATA_SO,3,1,DATA_SI,2,1,DATA_SD,1,1,DATA_SC,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
0x14a002,,RCNT0_H,16,rw,EXI,volatile,DATA_R7,7,1,DATA_R6,6,1,DATA_R5,5,1,DATA_R4,4,1,DATA_R3,3,1,DATA_R2,2,1,DATA_R1,1,1,DATA_R0,0,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
|
||||
|
Can't render this file because it has a wrong number of fields in line 33.
|
Loading…
Reference in New Issue
Block a user