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コア1のブート待ち対応。
NULLジャンプ時のデータアボート対応。 SWIハンドラアドレス格納。 git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@78 b871894f-2f95-9b40-918c-086798483c85
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@ -50,8 +50,16 @@ reserve b reserve
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irq b STUPi_IrqVeneer
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fiq b STUPi_FiqVeneer
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INASM_EXTERN( STUPi_SwiHandler )
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DCD STUPi_SwiHandler
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stupStartHandlerVeneer
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// NULLジャンプ時のデータアボート有効時はここで発生
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mov r12, #0
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ldr r12, [r12]
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//---- check CPU ID
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mrc p15,0, r0, c0, c0, 5
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tst r0, #HW_C0_AP_CPU_ID_MASK
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@ -68,15 +76,25 @@ stupStartHandlerVeneer
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ldr r3, =REG_IDR_CNT_ADDR
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mov r0, #REG_OS_IDR_CNT_E_MASK
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str r0, [r3]
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ldr r3, =REG_IDR_CLR_PND0_ADDR
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ldr r1, =REG_OS_IDR_CLR_PND0_IPI_ALL_MASK
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mov r0, #~0
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str r0, [r3]
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LSYM(10)
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wfi
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ldr r0, [r3]
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tst r0, r1
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wfieq
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nop
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b BSYM(10)
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beq BSYM(10)
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ldr lr, =HW_START_VECTOR1_PTR
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bx lr
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core0_start
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INASM_EXTERN( STUPi_StartHandler )
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b STUPi_StartHandler
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LTORG
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}
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@ -50,16 +50,19 @@ reserve b reserve
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irq b STUPi_IrqVeneer
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fiq b STUPi_FiqVeneer
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stupStartHandlerVeneer
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INASM_EXTERN( STUPi_SwiHandler )
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INASM_EXTERN( STUPi_StartHandler )
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b STUPi_StartHandler
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DCD 0
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DCD STUPi_SwiHandler
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INASM_EXTERN( |Image$$SVC_RW$$Base| )
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INASM_EXTERN( |Load$$SVC_RW$$Base| )
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DCD |Image$$SVC_RW$$Base|
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DCD |Load$$SVC_RW$$Base|
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stupStartHandlerVeneer
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INASM_EXTERN( STUPi_StartHandler )
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b STUPi_StartHandler
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}
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@ -36,6 +36,7 @@ extern "C" {
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#define HW_AXI_WRAM_SYSRV_OFS_UDEF_VENEER 0x18
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#define HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER 0x20
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#define HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER 0x28
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#define HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1 0x54
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0 0x58
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1 0x5c
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@ -46,6 +47,7 @@ extern "C" {
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#define HW_IABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER)
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#define HW_DABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER)
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#define HW_UDEF_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_UDEF_VENEER)
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#define HW_START_VECTOR1_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
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#define HW_INTR_CHECK0_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0)
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#define HW_INTR_CHECK1_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)
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