rvtr/ctr_firmware
1
Fork 0
mirror of https://github.com/rvtr/ctr_firmware.git synced 2025-10-31 07:51:08 -04:00
Code Issues Actions Packages Projects Releases Wiki Activity

コア１のブート待ち対応。

Browse Source 
NULLジャンプ時のデータアボート対応。
SWIハンドラアドレス格納。


git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@78 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-04 10:42:53 +00:00
parent 71553dd061
commit 32a52af0e8
3 changed files with 32 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
trunk/bootrom/build/libraries/init/ARM11/crt0.c
View File

@ -50,8 +50,16 @@ reserve b reserve
irq b STUPi_IrqVeneer
fiq b STUPi_FiqVeneer
INASM_EXTERN( STUPi_SwiHandler )
DCD STUPi_SwiHandler
stupStartHandlerVeneer
// NULLジャンプ時のデータアボート有効時はここで発生
mov r12, #0
ldr r12, [r12]
//---- check CPU ID
mrc p15,0, r0, c0, c0, 5
tst r0, #HW_C0_AP_CPU_ID_MASK
@ -68,15 +76,25 @@ stupStartHandlerVeneer
ldr r3, =REG_IDR_CNT_ADDR
mov r0, #REG_OS_IDR_CNT_E_MASK
str r0, [r3]
ldr r3, =REG_IDR_CLR_PND0_ADDR
ldr r1, =REG_OS_IDR_CLR_PND0_IPI_ALL_MASK
mov r0, #~0
str r0, [r3]
LSYM(10)
wfi
ldr r0, [r3]
tst r0, r1
wfieq
nop
b BSYM(10)
beq BSYM(10)
ldr lr, =HW_START_VECTOR1_PTR
bx lr
core0_start
INASM_EXTERN( STUPi_StartHandler )
b STUPi_StartHandler
LTORG
}

17
trunk/bootrom/build/libraries/init/ARM9/crt0.c
View File

@ -50,16 +50,19 @@ reserve b reserve
irq b STUPi_IrqVeneer
fiq b STUPi_FiqVeneer
INASM_EXTERN( STUPi_SwiHandler )
DCD STUPi_SwiHandler
INASM_EXTERN( |Image$$SVC_RW$$Base| )
INASM_EXTERN( |Load$$SVC_RW$$Base| )
DCD |Image$$SVC_RW$$Base|
DCD |Load$$SVC_RW$$Base|
stupStartHandlerVeneer
INASM_EXTERN( STUPi_StartHandler )
b STUPi_StartHandler
DCD 0
INASM_EXTERN( |Image$$SVC_RW$$Base| )
INASM_EXTERN( |Load$$SVC_RW$$Base| )
DCD |Image$$SVC_RW$$Base|
DCD |Load$$SVC_RW$$Base|
}

2
trunk/include/ctr/hw/ARM11/mmap_axi_wram.h
View File

@ -36,6 +36,7 @@ extern "C" {
#define HW_AXI_WRAM_SYSRV_OFS_UDEF_VENEER 0x18
#define HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER 0x20
#define HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER 0x28
#define HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1 0x54
#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0 0x58
#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1 0x5c
@ -46,6 +47,7 @@ extern "C" {
#define HW_IABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER)
#define HW_DABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER)
#define HW_UDEF_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_UDEF_VENEER)
#define HW_START_VECTOR1_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
#define HW_INTR_CHECK0_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0)
#define HW_INTR_CHECK1_PTR (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)