diff --git a/trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c b/trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c index ab2166a..836bf8d 100644 --- a/trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c +++ b/trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c @@ -87,316 +87,9 @@ terminate b terminate } -/*---------------------------------------------------------------------------* - Name: stupInitMMU - - Description: Initialize MMU - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void stupInitMMU( void ) -{ - stmfd sp!, {r4, lr} // stack requires 8byte alignment - - // Invalidate ITLB DTLB - mov r0, #0 - mcr p15, 0, r0, c8, c5, 0 - mcr p15, 0, r0, c8, c6, 0 - - ldr r0, =HW_BROM_MMU_T1 - - mov r2, #HW_C2_V5_T1_BOUNBARY_16KB - - // MMU L1 Table Base - - ldr r1, =HW_C2_0_T1_BASE_MASK_MIN - mov r1, r1, ASR r2 - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 0 - - ldr r1, =HW_C2_1_T1_BASE_MASK - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 1 - - // MMU L1 Table Boundary - - mcr p15, 0, r2, c2, c0, 2 - - // Domain Access Permission -#if 1 // miya - ldr r1, =0x00000001 -#else - ldr r1, = HW_C3_DOMAIN_PACK( \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER \ - ) -#endif - - - mcr p15, 0, r1, c3, c0, 0 - - // VFP Access Permission - - ldr r1, =HW_C1_VFP_AP_PACK( \ - HW_C1_AP_PRIV, HW_C1_AP_PRIV ) - mcr p15, 0, r1, c1, c0, 2 - - // Initialize MMU Table - - bl __cpp(stupInitMMUTable) - - ldmfd sp!, {r4, pc} // stack requires 8byte alignment -} - - -/*---------------------------------------------------------------------------* - Name: stupInitMMUTable - - Description: Initialize MMU Table - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -void stupInitMMUTable( void ) -{ - u32* t1Base = (u32* )HW_BROM_MMU_T1; - u32* t2Base = (u32* )HW_BROM_MMU_T2; - - u32* table; - u32 paddr = (u32 )NULL; - - // Initialize as Access Prohibition - table = t1Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_APX_NA, - HW_MMU6_T1_RGT_STRONG_ORDER, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - } - - table = t2Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_NA, - HW_MMU6_T2_LP_RGT_STRONG_ORDER, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - } - - - // Main Memory Region (128MB cached) - paddr = HW_MAIN_MEM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#ifndef SDK_MG20EMU - // MG20には拡張メインメモリは無い - while ( paddr < HW_MAIN_MEM_EX_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_ALL, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#else // SDK_MG20EMU - // for AXI-WRAM & DSP-WRAM Emulation - paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#endif // SDK_MG20EMU - - // IO Registers Region (16MB) - paddr = HW_IOREG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE ) - { - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_SHARED_DEV, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // MPCore Registers Region (1MB) - paddr = HW_MPCORE_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); - - // VRAM Region (4MB cached) - paddr = HW_VRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_VRAM_END ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } #ifdef SDK_NE1EMU - // NE1-TB DDR2 Registers Region (1MB) - paddr = HW_NE1DDR2_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); +#include <./../../../../libraries/init/ARM11/crt0_ne1.c> #endif // SDK_NE1EMU - - // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) - paddr = HW_DSP_WRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_LP_XN); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - while ( paddr < HW_BROM_MMU_TBL ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_BROM_MMU_TBL - while ( paddr < HW_BROM_MMU_TBL_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_AXI_WRAM_SHARED - while ( paddr < HW_AXI_WRAM_SHARED_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); // for exception veneer - paddr += HW_MMU6_T2_SP_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); - - // BROM Region (64KBx2 cached) - paddr = HW_BROM_IMG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr != HW_BROM_END ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); -} - - +#include <./../../../../libraries/init/ARM11/crt0_mmu.c> #include <./../../../../libraries/init/ARM11/crt0_misc.c> - diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c index b2835c3..68b36d8 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_app.c @@ -18,8 +18,10 @@ #include //#include +#undef BROM_TARGET_BROM +#define BROM_TARGET_APP + void _start(void); -void stupInitMMUTable( void ); /*---------------------------------------------------------------------------* Name: _start @@ -77,316 +79,5 @@ terminate b terminate } -/*---------------------------------------------------------------------------* - Name: stupInitMMU - - Description: Initialize MMU - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void stupInitMMU( void ) -{ - stmfd sp!, {r4, lr} // stack requires 8byte alignment - - // Invalidate ITLB DTLB - mov r0, #0 - mcr p15, 0, r0, c8, c5, 0 - mcr p15, 0, r0, c8, c6, 0 - - ldr r0, =HW_BROM_MMU_T1 - - mov r2, #HW_C2_V5_T1_BOUNBARY_16KB - - // MMU L1 Table Base - - ldr r1, =HW_C2_0_T1_BASE_MASK_MIN - mov r1, r1, ASR r2 - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 0 - - ldr r1, =HW_C2_1_T1_BASE_MASK - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 1 - - // MMU L1 Table Boundary - - mcr p15, 0, r2, c2, c0, 2 - - // Domain Access Permission -#if 1 // miya - ldr r1, =0x00000001 -#else - ldr r1, = HW_C3_DOMAIN_PACK( \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER \ - ) -#endif - - - mcr p15, 0, r1, c3, c0, 0 - - // VFP Access Permission - - ldr r1, =HW_C1_VFP_AP_PACK( \ - HW_C1_AP_PRIV, HW_C1_AP_PRIV ) - mcr p15, 0, r1, c1, c0, 2 - - // Initialize MMU Table - - bl __cpp(stupInitMMUTable) - - ldmfd sp!, {r4, pc} // stack requires 8byte alignment -} - - -/*---------------------------------------------------------------------------* - Name: stupInitMMUTable - - Description: Initialize MMU Table - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -void stupInitMMUTable( void ) -{ - u32* t1Base = (u32* )HW_BROM_MMU_T1; - u32* t2Base = (u32* )HW_BROM_MMU_T2; - - u32* table; - u32 paddr = (u32 )NULL; - - // Initialize as Access Prohibition - table = t1Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_APX_NA, - HW_MMU6_T1_RGT_STRONG_ORDER, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - } - - table = t2Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_NA, - HW_MMU6_T2_LP_RGT_STRONG_ORDER, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - } - - - // Main Memory Region (128MB cached) - paddr = HW_MAIN_MEM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - FALSE - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#ifndef SDK_MG20EMU - // MG20には拡張メインメモリは無い - while ( paddr < HW_MAIN_MEM_EX_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_ALL, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - FALSE - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#else // SDK_MG20EMU - // for AXI-WRAM & DSP-WRAM Emulation - paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#endif // SDK_MG20EMU - - // IO Registers Region (16MB) - paddr = HW_IOREG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE ) - { - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_SHARED_DEV, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // MPCore Registers Region (1MB) - paddr = HW_MPCORE_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); - - // VRAM Region (4MB cached) - paddr = HW_VRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_VRAM_END ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } - -#ifdef SDK_NE1EMU - // NE1-TB DDR2 Registers Region (1MB) - paddr = HW_NE1DDR2_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); -#endif // SDK_NE1EMU - - // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) - paddr = HW_DSP_WRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_LP_XN); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - while ( paddr < HW_BROM_MMU_TBL ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_BROM_MMU_TBL - while ( paddr < HW_BROM_MMU_TBL_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_AXI_WRAM_SHARED - while ( paddr < HW_AXI_WRAM_SHARED_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); // for exception veneer - paddr += HW_MMU6_T2_SP_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); - - // BROM Region (64KBx2 cached) - paddr = HW_BROM_IMG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr != HW_BROM_END ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); -} - -#undef BROM_TARGET_BROM +#include <./crt0_mmu.c> #include <./crt0_misc.c> - diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c index 5be3097..845a964 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c @@ -17,281 +17,6 @@ #include #include -#ifdef SDK_NE1EMU - -/*---------------------------------------------------------------------------* - Name: i_stupInitDDR2 - - Description: Initialize DDR2 for NE1-TBoard - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void i_stupInitDDR2( void ) -{ - INASM_EXTERN( i_osWaitCpuCycles ) - - mov r3, lr - - ldr r0, =HW_NE1EXBUS_REG - - ldr r1, =0x0000004A - str r1, [r0, #REG_EXBUS_PCS0_OFFSET] - - ldr r1, =0x08000049 - str r1, [r0, #REG_EXBUS_PCS1_OFFSET] - - ldr r1, =0x0600004E - str r1, [r0, #REG_EXBUS_PCS2_OFFSET] - - ldr r1, =0x0400004B - str r1, [r0, #REG_EXBUS_PCS3_OFFSET] - - ldr r1, =0x1000004A - str r1, [r0, #REG_EXBUS_PCS4_OFFSET] - - ldr r1, =0x1400000A - str r1, [r0, #REG_EXBUS_PCS5_OFFSET] - - ldr r1, =0x10388E7F - str r1, [r0, #REG_EXBUS_PCS0TIM_OFFSET] - - ldr r1, =0x10388E7E - str r1, [r0, #REG_EXBUS_PCS1TIM_OFFSET] - - ldr r1, =0x10388E7E - str r1, [r0, #REG_EXBUS_PCS2TIM_OFFSET] - - ldr r1, =0x10388E7F - str r1, [r0, #REG_EXBUS_PCS3TIM_OFFSET] - - ldr r1, =0x10388E7E - str r1, [r0, #REG_EXBUS_PCS4TIM_OFFSET] - - ldr r1, =0x10388E7E - str r1, [r0, #REG_EXBUS_PCS5TIM_OFFSET] - - // Check device version - // ES1.0 : go to ContinueBoot - ldr r0, =HW_NE1SYS_REG - ldr r1, [r0, #REG_SYS_VERSION_OFFSET] - ldr r2, =0x00000001 - cmp r1, r2 - bne ContinueBoot - - // Check reset cause - // Software reset : ContinueBoot - ldr r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] - and r1, r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK - mov r2, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK - cmp r1, r2 - beq ContinueBoot - - // Check BTM - // DSW1_7 OFF : ContinueBoot - ldr r1, [r0, #REG_SYS_BOOT_ID_OFFSET] - and r1, r1, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK - mov r2, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK - cmp r1, r2 - bne ContinueBoot - - // Change WTOP normal mode setting - ldr r1, [r0, #REG_SYS_WTOP_MODE_OFFSET] - and r1, r1, #0xFFFFFFFE - str r1, [r0, #REG_SYS_WTOP_MODE_OFFSET] - - // Do Software reset - mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_MASK - str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] - -wait_reset - b wait_reset - -ContinueBoot - // Clear Software reset - mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK - str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] - - // Setup DDR2 - ldr r0, =HW_NE1DDR2_REG - - ldr r1, =0x30022123 - str r1, [r0, #REG_MIF_SDC_CFG2_OFFSET] - - mov r1, #0x1 - str r1, [r0, #REG_MIF_DLL_CFG_OFFSET] - - mov r1, #0x20 - str r1, [r0, #REG_MIF_INIT_OFFSET] - -// wait 480ns - ldr r0, =__cpp(OS_USEC_TO_TICK32(10)) - bl i_osWaitCpuCycles - - ldr r0, =HW_NE1DDR2_REG - - ldr r1, =0x10000004 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x00010002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x00018002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x00008002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x1D480002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x10000004 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - mov r1, #0x1 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - mov r1, #0x1 - str r1, [r0, #REG_MIF_INIT_OFFSET] - -// wait 1080ns - ldr r0, =__cpp(OS_USEC_TO_TICK32(10)) - bl i_osWaitCpuCycles - - ldr r0, =HW_NE1DDR2_REG - - ldr r1, =0x19480002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x01308002 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - mov r1, #0x100 - str r1, [r0, #REG_MIF_INIT_OFFSET] - - ldr r1, =0x1485A912 - str r1, [r0, #REG_MIF_SDC_CFG1_OFFSET] - - ldr r1, =0x00000121 - str r1, [r0, #REG_MIF_REF_CFG_OFFSET] - - mov lr, r3 - bx lr -} - -#endif // SDK_NE1EMU - -/*---------------------------------------------------------------------------* - Name: stupDisableCP15 - - Description: Disable Coprocessor 15 - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void stupDisableCP15( void ) -{ - // MMU/Caches/BranchPrediction disable - - mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ - | HW_C1_FORCE_AP_BIT \ - | HW_C1_TEX_CB_REMAP \ - | HW_C1_EXCEPT_BIG_ENDIAN \ - | HW_C1_BR_PREDICT_ENABLE \ - | HW_C1_LD_INTERWORK_DISABLE \ - | HW_C1_UNALIGN_ACCESS_ENABLE \ - | HW_C1_ALIGN_FAULT_ENABLE \ - | HW_C1_ROM_PROTECT_ENABLE \ - | HW_C1_MMU_PROTECT_ENABLE \ - | HW_C1_MMU_ENABLE -#ifndef SDK_MG20EMU - orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER -#endif // SDK_MG20EMU - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - mrc p15, 0, r0, c1, c0, 1 - ldr r1, =HW_C1_SMP_MODE \ - | HW_C1_EXCLUSIVE_L1C_L2C \ - | HW_C1_BR_FOLDING_ENABLE \ - | HW_C1_SBR_PREDICT_ENABLE \ - | HW_C1_DBR_PREDICT_ENABLE \ - | HW_C1_RETURN_STACK_ENABLE - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 1 - - // Invalidate Caches - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 // Inst Cache - mcr p15, 0, r0, c7, c6, 0 // Data cache - - // Wait for write buffer empty - mcr p15, 0, r0, c7, c10, 4 - - bx lr -} - - -/*---------------------------------------------------------------------------* - Name: stupEnableCP15 - - Description: Enable Coprocessor 15 - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void stupEnableCP15( void ) -{ - // - // Auxiliary Control - // - mrc p15, 0, r0, c1, c0, 1 - ldr r1, =HW_C1_AMP_MODE \ - | HW_C1_BR_FOLDING_ENABLE \ - | HW_C1_SBR_PREDICT_ENABLE \ - | HW_C1_DBR_PREDICT_ENABLE \ - | HW_C1_RETURN_STACK_ENABLE - orr r0, r0, r1 - - mcr p15, 0, r0, c1, c0, 1 - - // - // Master Control - // - mrc p15, 0, r0, c1, c0, 0 - - ldr r1, = 0 \ - | HW_C1_EXCEPT_LITTLE_ENDIAN \ - | HW_C1_UNALIGN_ACCESS_ENABLE \ - | HW_C1_BR_PREDICT_ENABLE \ - | HW_C1_MMU_V6 \ - | HW_C1_IC_ENABLE \ - | HW_C1_DC_ENABLE \ - | HW_C1_MMU_ENABLE -#ifdef SDK_MG20EMU - orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER -#endif // SDK_MG20EMU - - orr r0, r0, r1 - - mcr p15, 0, r0, c1, c0, 0 - - // Invalidate Caches - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 // Inst Cache - mcr p15, 0, r0, c7, c6, 0 // Data cache - - // Wait for write buffer empty - mcr p15, 0, r0, c7, c10, 4 - - - bx lr - -} /*---------------------------------------------------------------------------* Name: __user_initial_stackheap diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_mmu.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_mmu.c new file mode 100644 index 0000000..898861f --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_mmu.c @@ -0,0 +1,449 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_mmu.c + + Copyright 2009 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: $ + $Rev$ + $Author$ + *---------------------------------------------------------------------------*/ +#include +#include + +void stupInitMMUTable( void ); + +/*---------------------------------------------------------------------------* + Name: stupDisableCP15 + + Description: Disable Coprocessor 15 + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void stupDisableCP15( void ) +{ + // MMU/Caches/BranchPrediction disable + + mrc p15, 0, r0, c1, c0, 0 + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ + | HW_C1_FORCE_AP_BIT \ + | HW_C1_TEX_CB_REMAP \ + | HW_C1_EXCEPT_BIG_ENDIAN \ + | HW_C1_BR_PREDICT_ENABLE \ + | HW_C1_LD_INTERWORK_DISABLE \ + | HW_C1_UNALIGN_ACCESS_ENABLE \ + | HW_C1_ALIGN_FAULT_ENABLE \ + | HW_C1_ROM_PROTECT_ENABLE \ + | HW_C1_MMU_PROTECT_ENABLE \ + | HW_C1_MMU_ENABLE +#ifndef SDK_MG20EMU + orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER +#endif // SDK_MG20EMU + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c1, c0, 1 + ldr r1, =HW_C1_SMP_MODE \ + | HW_C1_EXCLUSIVE_L1C_L2C \ + | HW_C1_BR_FOLDING_ENABLE \ + | HW_C1_SBR_PREDICT_ENABLE \ + | HW_C1_DBR_PREDICT_ENABLE \ + | HW_C1_RETURN_STACK_ENABLE + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 1 + + // Invalidate Caches + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // Inst Cache + mcr p15, 0, r0, c7, c6, 0 // Data cache + + // Wait for write buffer empty + mcr p15, 0, r0, c7, c10, 4 + + bx lr +} + + +/*---------------------------------------------------------------------------* + Name: stupEnableCP15 + + Description: Enable Coprocessor 15 + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void stupEnableCP15( void ) +{ + // + // Auxiliary Control + // + mrc p15, 0, r0, c1, c0, 1 + ldr r1, =HW_C1_AMP_MODE \ + | HW_C1_BR_FOLDING_ENABLE \ + | HW_C1_SBR_PREDICT_ENABLE \ + | HW_C1_DBR_PREDICT_ENABLE \ + | HW_C1_RETURN_STACK_ENABLE + orr r0, r0, r1 + + mcr p15, 0, r0, c1, c0, 1 + + // + // Master Control + // + mrc p15, 0, r0, c1, c0, 0 + + ldr r1, = 0 \ + | HW_C1_EXCEPT_LITTLE_ENDIAN \ + | HW_C1_UNALIGN_ACCESS_ENABLE \ + | HW_C1_BR_PREDICT_ENABLE \ + | HW_C1_MMU_V6 \ + | HW_C1_IC_ENABLE \ + | HW_C1_DC_ENABLE \ + | HW_C1_MMU_ENABLE +#ifdef SDK_MG20EMU + orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER +#endif // SDK_MG20EMU + + orr r0, r0, r1 + + mcr p15, 0, r0, c1, c0, 0 + + // Invalidate Caches + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // Inst Cache + mcr p15, 0, r0, c7, c6, 0 // Data cache + + // Wait for write buffer empty + mcr p15, 0, r0, c7, c10, 4 + + bx lr + +} + +/*---------------------------------------------------------------------------* + Name: stupInitMMU + + Description: Initialize MMU + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void stupInitMMU( void ) +{ + stmfd sp!, {r4, lr} // stack requires 8byte alignment + + // Invalidate ITLB DTLB + mov r0, #0 + mcr p15, 0, r0, c8, c5, 0 + mcr p15, 0, r0, c8, c6, 0 + + ldr r0, =HW_BROM_MMU_T1 + + mov r2, #HW_C2_V5_T1_BOUNBARY_16KB + + // MMU L1 Table Base + + ldr r1, =HW_C2_0_T1_BASE_MASK_MIN + mov r1, r1, ASR r2 + and r1 ,r1, r0 + orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ + | HW_C2_WALK_ON_SHARED_MEM + mcr p15, 0, r1, c2, c0, 0 + + ldr r1, =HW_C2_1_T1_BASE_MASK + and r1 ,r1, r0 + orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ + | HW_C2_WALK_ON_SHARED_MEM + mcr p15, 0, r1, c2, c0, 1 + + // MMU L1 Table Boundary + + mcr p15, 0, r2, c2, c0, 2 + + // Domain Access Permission +#if 1 // miya + ldr r1, =0x00000001 +#else + ldr r1, = HW_C3_DOMAIN_PACK( \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_CLIENT, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER, \ + HW_C3_DM_AP_MANAGER \ + ) +#endif + + + mcr p15, 0, r1, c3, c0, 0 + + // VFP Access Permission + + ldr r1, =HW_C1_VFP_AP_PACK( \ + HW_C1_AP_PRIV, HW_C1_AP_PRIV ) + mcr p15, 0, r1, c1, c0, 2 + + // Initialize MMU Table + + bl __cpp(stupInitMMUTable) + + ldmfd sp!, {r4, pc} // stack requires 8byte alignment +} + + +/*---------------------------------------------------------------------------* + Name: stupInitMMUTable + + Description: Initialize MMU Table + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +void stupInitMMUTable( void ) +{ + u32* t1Base = (u32* )HW_BROM_MMU_T1; + u32* t2Base = (u32* )HW_BROM_MMU_T2; + + u32* table; + u32 paddr = (u32 )NULL; + + // Initialize as Access Prohibition + table = t1Base; + for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_APX_NA, + HW_MMU6_T1_RGT_STRONG_ORDER, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN, + 0); + } + + table = t2Base; + for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_NA, + HW_MMU6_T2_LP_RGT_STRONG_ORDER, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_SP_XN); + } + + + // Main Memory Region (128MB cached) + paddr = HW_MAIN_MEM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_MAIN_MEM_END ) + { + + *table++ = HW_MMU6_T1_SUSEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, +#ifdef BROM_TARGET_BROM + HW_MMU6_T1_XN +#else // BROM_TARGET_FIRM || BROM_TARGET_APP + FALSE +#endif // BROM_TARGET_FIRM || BROM_TARGET_APP + ); + paddr += HW_MMU6_T1_SEC_SIZE; + } +#ifndef SDK_MG20EMU + // MG20には拡張メインメモリは無い + while ( paddr < HW_MAIN_MEM_EX_END ) + { + + *table++ = HW_MMU6_T1_SUSEC_PACK( + paddr, + HW_MMU6_T1_APX_ALL, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, +#ifdef BROM_TARGET_BROM + HW_MMU6_T1_XN +#else // BROM_TARGET_FIRM || BROM_TARGET_APP + FALSE +#endif // BROM_TARGET_FIRM || BROM_TARGET_APP + ); + paddr += HW_MMU6_T1_SEC_SIZE; + } +#else // SDK_MG20EMU + // for AXI-WRAM & DSP-WRAM Emulation + paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_MAIN_MEM_END ) + { + + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } +#endif // SDK_MG20EMU + + // IO Registers Region (16MB) + paddr = HW_IOREG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE ) + { + *table++ = HW_MMU6_T1_SUSEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_SHARED_DEV, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN + ); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // MPCore Registers Region (1MB) + paddr = HW_MPCORE_REG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); + + // VRAM Region (4MB cached) + paddr = HW_VRAM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_VRAM_END ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + +#ifdef SDK_NE1EMU + // NE1-TB DDR2 Registers Region (1MB) + paddr = HW_NE1DDR2_REG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); +#endif // SDK_NE1EMU + + // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) + paddr = HW_DSP_WRAM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); + // T2 for Page + table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; + while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_LP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_LP_XN); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + while ( paddr < HW_BROM_MMU_TBL ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_SP_XN); + paddr += HW_MMU6_T2_SP_SIZE; + } + // HW_BROM_MMU_TBL + while ( paddr < HW_BROM_MMU_TBL_END ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_SHARED_DEV, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_SP_XN); + paddr += HW_MMU6_T2_SP_SIZE; + } + // HW_AXI_WRAM_SHARED + while ( paddr < HW_AXI_WRAM_SHARED_END ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_SHARED_DEV, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + FALSE); // for exception veneer + paddr += HW_MMU6_T2_SP_SIZE; + } + // Coarse page is 1KB boundary + t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); + + // BROM Region (64KBx2 cached) + paddr = HW_BROM_IMG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); + // T2 for Page + table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; + while ( paddr != HW_BROM_END ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_LP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + FALSE); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + // Coarse page is 1KB boundary + t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); +} + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_ne1.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_ne1.c new file mode 100644 index 0000000..f81e125 --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_ne1.c @@ -0,0 +1,181 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_ne1.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: $ + $Rev$ + $Author$ + *---------------------------------------------------------------------------*/ +#include +#include + + +/*---------------------------------------------------------------------------* + Name: i_stupInitDDR2 + + Description: Initialize DDR2 for NE1-TBoard + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void i_stupInitDDR2( void ) +{ + INASM_EXTERN( i_osWaitCpuCycles ) + + mov r3, lr + + ldr r0, =HW_NE1EXBUS_REG + + ldr r1, =0x0000004A + str r1, [r0, #REG_EXBUS_PCS0_OFFSET] + + ldr r1, =0x08000049 + str r1, [r0, #REG_EXBUS_PCS1_OFFSET] + + ldr r1, =0x0600004E + str r1, [r0, #REG_EXBUS_PCS2_OFFSET] + + ldr r1, =0x0400004B + str r1, [r0, #REG_EXBUS_PCS3_OFFSET] + + ldr r1, =0x1000004A + str r1, [r0, #REG_EXBUS_PCS4_OFFSET] + + ldr r1, =0x1400000A + str r1, [r0, #REG_EXBUS_PCS5_OFFSET] + + ldr r1, =0x10388E7F + str r1, [r0, #REG_EXBUS_PCS0TIM_OFFSET] + + ldr r1, =0x10388E7E + str r1, [r0, #REG_EXBUS_PCS1TIM_OFFSET] + + ldr r1, =0x10388E7E + str r1, [r0, #REG_EXBUS_PCS2TIM_OFFSET] + + ldr r1, =0x10388E7F + str r1, [r0, #REG_EXBUS_PCS3TIM_OFFSET] + + ldr r1, =0x10388E7E + str r1, [r0, #REG_EXBUS_PCS4TIM_OFFSET] + + ldr r1, =0x10388E7E + str r1, [r0, #REG_EXBUS_PCS5TIM_OFFSET] + + // Check device version + // ES1.0 : go to ContinueBoot + ldr r0, =HW_NE1SYS_REG + ldr r1, [r0, #REG_SYS_VERSION_OFFSET] + ldr r2, =0x00000001 + cmp r1, r2 + bne ContinueBoot + + // Check reset cause + // Software reset : ContinueBoot + ldr r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] + and r1, r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK + mov r2, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK + cmp r1, r2 + beq ContinueBoot + + // Check BTM + // DSW1_7 OFF : ContinueBoot + ldr r1, [r0, #REG_SYS_BOOT_ID_OFFSET] + and r1, r1, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK + mov r2, #REG_NE1SYS_SYS_BOOT_ID_MODE_MASK + cmp r1, r2 + bne ContinueBoot + + // Change WTOP normal mode setting + ldr r1, [r0, #REG_SYS_WTOP_MODE_OFFSET] + and r1, r1, #0xFFFFFFFE + str r1, [r0, #REG_SYS_WTOP_MODE_OFFSET] + + // Do Software reset + mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_MASK + str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] + +wait_reset + b wait_reset + +ContinueBoot + // Clear Software reset + mov r1, #REG_NE1SYS_SYS_RESET_STATUS_RST_STAT_MASK + str r1, [r0, #REG_SYS_RESET_STATUS_OFFSET] + + // Setup DDR2 + ldr r0, =HW_NE1DDR2_REG + + ldr r1, =0x30022123 + str r1, [r0, #REG_MIF_SDC_CFG2_OFFSET] + + mov r1, #0x1 + str r1, [r0, #REG_MIF_DLL_CFG_OFFSET] + + mov r1, #0x20 + str r1, [r0, #REG_MIF_INIT_OFFSET] + +// wait 480ns + ldr r0, =__cpp(OS_USEC_TO_TICK32(10)) + bl i_osWaitCpuCycles + + ldr r0, =HW_NE1DDR2_REG + + ldr r1, =0x10000004 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x00010002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x00018002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x00008002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x1D480002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x10000004 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + mov r1, #0x1 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + mov r1, #0x1 + str r1, [r0, #REG_MIF_INIT_OFFSET] + +// wait 1080ns + ldr r0, =__cpp(OS_USEC_TO_TICK32(10)) + bl i_osWaitCpuCycles + + ldr r0, =HW_NE1DDR2_REG + + ldr r1, =0x19480002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x01308002 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + mov r1, #0x100 + str r1, [r0, #REG_MIF_INIT_OFFSET] + + ldr r1, =0x1485A912 + str r1, [r0, #REG_MIF_SDC_CFG1_OFFSET] + + ldr r1, =0x00000121 + str r1, [r0, #REG_MIF_REF_CFG_OFFSET] + + mov lr, r3 + bx lr +} + diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c index 2b1c8b9..eaecd31 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c @@ -18,9 +18,6 @@ #include -void stupInitMMUTable( void ); - - /*---------------------------------------------------------------------------* Name: i_stupStartHandler @@ -98,316 +95,8 @@ terminate b terminate } -/*---------------------------------------------------------------------------* - Name: stupInitMMU - - Description: Initialize MMU - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void stupInitMMU( void ) -{ - stmfd sp!, {r4, lr} // stack requires 8byte alignment - - // Invalidate ITLB DTLB - mov r0, #0 - mcr p15, 0, r0, c8, c5, 0 - mcr p15, 0, r0, c8, c6, 0 - - ldr r0, =HW_BROM_MMU_T1 - - mov r2, #HW_C2_V5_T1_BOUNBARY_16KB - - // MMU L1 Table Base - - ldr r1, =HW_C2_0_T1_BASE_MASK_MIN - mov r1, r1, ASR r2 - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 0 - - ldr r1, =HW_C2_1_T1_BASE_MASK - and r1 ,r1, r0 - orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ - | HW_C2_WALK_ON_SHARED_MEM - mcr p15, 0, r1, c2, c0, 1 - - // MMU L1 Table Boundary - - mcr p15, 0, r2, c2, c0, 2 - - // Domain Access Permission -#if 1 // miya - ldr r1, =0x00000001 -#else - ldr r1, = HW_C3_DOMAIN_PACK( \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_CLIENT, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER, \ - HW_C3_DM_AP_MANAGER \ - ) -#endif - - - mcr p15, 0, r1, c3, c0, 0 - - // VFP Access Permission - - ldr r1, =HW_C1_VFP_AP_PACK( \ - HW_C1_AP_PRIV, HW_C1_AP_PRIV ) - mcr p15, 0, r1, c1, c0, 2 - - // Initialize MMU Table - - bl __cpp(stupInitMMUTable) - - ldmfd sp!, {r4, pc} // stack requires 8byte alignment -} - - -/*---------------------------------------------------------------------------* - Name: stupInitMMUTable - - Description: Initialize MMU Table - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -void stupInitMMUTable( void ) -{ - u32* t1Base = (u32* )HW_BROM_MMU_T1; - u32* t2Base = (u32* )HW_BROM_MMU_T2; - - u32* table; - u32 paddr = (u32 )NULL; - - // Initialize as Access Prohibition - table = t1Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_APX_NA, - HW_MMU6_T1_RGT_STRONG_ORDER, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - } - - table = t2Base; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_NA, - HW_MMU6_T2_LP_RGT_STRONG_ORDER, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - } - - - // Main Memory Region (128MB cached) - paddr = HW_MAIN_MEM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#ifndef SDK_MG20EMU - // MG20には拡張メインメモリは無い - while ( paddr < HW_MAIN_MEM_EX_END ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_ALL, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#else // SDK_MG20EMU - // for AXI-WRAM & DSP-WRAM Emulation - paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_MAIN_MEM_END ) - { - - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } -#endif // SDK_MG20EMU - - // IO Registers Region (16MB) - paddr = HW_IOREG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE ) - { - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_SHARED_DEV, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // MPCore Registers Region (1MB) - paddr = HW_MPCORE_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); - - // VRAM Region (4MB cached) - paddr = HW_VRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - while ( paddr < HW_VRAM_END ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } - #ifdef SDK_NE1EMU - // NE1-TB DDR2 Registers Region (1MB) - paddr = HW_NE1DDR2_REG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); +#include <./crt0_ne1.c> #endif // SDK_NE1EMU - - // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) - paddr = HW_DSP_WRAM; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_LP_XN); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - while ( paddr < HW_BROM_MMU_TBL ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_BROM_MMU_TBL - while ( paddr < HW_BROM_MMU_TBL_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_SP_XN); - paddr += HW_MMU6_T2_SP_SIZE; - } - // HW_AXI_WRAM_SHARED - while ( paddr < HW_AXI_WRAM_SHARED_END ) - { - *table++ = HW_MMU6_T2_SP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_SP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); // for exception veneer - paddr += HW_MMU6_T2_SP_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); - - // BROM Region (64KBx2 cached) - paddr = HW_BROM_IMG; - table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; - *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); - // T2 for Page - table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE]; - while ( paddr != HW_BROM_END ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); -} - - +#include <./crt0_mmu.c> #include <./crt0_misc.c> - diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_app.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_app.c index 4bbc86e..ddb5dd1 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_app.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_app.c @@ -17,6 +17,9 @@ #include #include +#undef BROM_TARGET_BROM +#define BROM_TARGET_APP + #define STUPi_HW_DTCM |Image$$DTCM$$Base| void _start(void); @@ -90,192 +93,5 @@ terminate b terminate } -//----------------------------------------------------------------------- -// システム制御コプロセッサ 初期化 -//----------------------------------------------------------------------- -asm void i_stupInitCP15(void) -{ - // プロテクションユニット/キャッシュ/TCM ディセーブル - - mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ - | HW_C1_LD_INTERWORK_DISABLE \ - | HW_C1_PROTECT_UNIT_ENABLE -#ifdef SDK_MG20EMU - bic r1, r1, #HW_C1_ITCM_ENABLE -#endif // SDK_MG20EMU - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - // キャッシュ無効化 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ - mcr p15, 0, r0, c7, c6, 0 // データキャッシュ - - // ライトバッファ エンプティ待ち - mcr p15, 0, r0, c7, c10, 4 - -/* -; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA -; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW -; Region 3: PRV_WRAM_SYSRV:Base = 0x08000000, Size = 4KB, I:Cach Buf / D:Cach Buf, I:RO / D:RW -; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW -; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO -; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW -*/ -#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE) -#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0 -#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7)) -#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28)) -#define NA 0 -#define RW 1 -#define RO 5 - - - // - // メモリリージョン初期化 - // - //---- メインメモリ - SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB ) - SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB ) - - //---- I/Oレジスタ & VRAM & AXI-WRAM - SET_PROTECTION_A( c1, HW_IOREG, 256MB ) - SET_PROTECTION_B( c1, HW_IOREG, 256MB ) - - //---- PRV_WRAM - SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB ) - SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB ) - - //---- PRV_WRAM_SYSRV -#ifndef SDK_MG20EMU - SET_PROTECTION_A( c3, HW_PRV_WRAM_SYSRV, 4KB ) - SET_PROTECTION_B( c3, HW_PRV_WRAM_SYSRV, 4KB ) -#else // SDK_MG20EMU - SET_PROTECTION_A( c3, HW_MG20IOP_REG, 1MB ) - SET_PROTECTION_B( c3, HW_MG20IOP_REG, 1MB ) -#endif // SDK_MG20EMU - - //---- データ TCM - ldr r0, =STUPi_HW_DTCM - orr r0, r0, #HW_C6_PR_16KB - orr r0, r0, #HW_C6_PR_ENABLE - SET_PROTECTION_B( c4, HW_DTCM, 16KB ) - - //---- 命令 TCM - // データ TCM より優先が高い - SET_PROTECTION_A( c5, HW_ITCM, 32KB ) - SET_PROTECTION_B( c5, HW_ITCM, 32KB ) - - //---- BIOS - SET_PROTECTION_A( c6, HW_BIOS, 64KB ) - SET_PROTECTION_B( c6, HW_BIOS, 64KB ) - - //---- SHARED CPU 間通信ワーク領域 - SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB ) - SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB ) - - // - // 命令ＴＣＭ 設定 - // - mov r0, #HW_C9_TCMR_128MB - mcr p15, 0, r0, c9, c1, 1 - - // - // データＴＣＭ 設定 - // - ldr r0, =STUPi_HW_DTCM - orr r0, r0, #HW_C9_TCMR_16KB - mcr p15, 0, r0, c9, c1, 0 - - // - // 命令キャッシュ イネーブル (リージョン設定) - // 6: BIOS - // - mov r0, #REGION_BIT(0,0,0,0,0,0,1,0) - mcr p15, 0, r0, c2, c0, 1 - - // - // データキャッシュ イネーブル (リージョン設定) - // 0: HW_MAIN_MEM - // 2: PRV_WRAM - // 6: BIOS - // - mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) - mcr p15, 0, r0, c2, c0, 0 - - // - // ライトバッファ イネーブル(リージョン設定) - // 0: HW_MAIN_MEM - // 2: PRV_WRAM - // 6: BIOS - // - mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) - mcr p15, 0, r0, c3, c0, 0 - - // - // 命令アクセス許可 (リージョン設定) - // MAIN_MEM : NA - // IO_AXIRAM : NA - // PRV_WRAM : NA - // PRV_WRAM_SYSRV: RO - // DTCM : NA - // ITCM : RO - // BIOS : RO - // SHARED : NA - // -#ifndef SDK_MG20EMU - ldr r0, =REGION_ACC(NA,NA,NA,RO,NA,RO,RO,NA) -#else // SDK_MG20EMU - ldr r0, =REGION_ACC(NA,NA,RO,NA,NA,RO,RO,NA) -#endif // SDK_MG20EMU - mcr p15, 0, r0, c5, c0, 3 - - // - // データアクセス許可（リージョン設定） - // MAIN_MEM : RW - // IO_AXIRAM : RW - // PRV_WRAM : RW - // PRV_WRAM_SYSRV: RW - // DTCM : RW - // ITCM : RW - // BIOS : RO - // SHARED : RW - // -#ifdef BROM_ENABLE_BOOTROM_WRITE - ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RW,RW) -#else // BROM_ENABLE_BOOTROM_WRITE - ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RO,RW) -#endif // BROM_ENABLE_BOOTROM_WRITE - mcr p15, 0, r0, c5, c0, 2 - - // - // システム制御コプロセッサ マスター設定 - // - mrc p15, 0, r0, c1, c0, 0 - ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \ - | HW_C1_PROTECT_UNIT_ENABLE - orr r0, r0, r1 -#ifdef SDK_MG20EMU - bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER -#endif // SDK_MG20EMU - mcr p15, 0, r0, c1, c0, 0 - - bx lr - - LTORG - - EXPORT i_stupInitCP15_End -i_stupInitCP15_End -} - -#undef BROM_TARGET_BROM +#include <./crt0_pu.c> #include <./crt0_misc_sp.c> - diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c index d38ba92..3f65376 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c @@ -102,62 +102,6 @@ LSYM(30) bx lr } -/*---------------------------------------------------------------------------* - Name: i_stupEnableTCM - - Description: enable ITCM and DTCM - - Arguments: None - - Returns: None - *---------------------------------------------------------------------------*/ -asm void i_stupEnableTCM( void ) -{ - // プロテクションユニット/キャッシュ/TCM ディセーブル - - mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ - | HW_C1_LD_INTERWORK_DISABLE \ - | HW_C1_PROTECT_UNIT_ENABLE - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - // キャッシュ無効化 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ - mcr p15, 0, r0, c7, c6, 0 // データキャッシュ - - // ライトバッファ エンプティ待ち - mcr p15, 0, r0, c7, c10, 4 - - // - // 命令ＴＣＭ 設定 - // - mov r0, #HW_C9_TCMR_32MB - mcr p15, 0, r0, c9, c1, 1 - - // - // データＴＣＭ 設定 - // - ldr r0, =STUPi_HW_DTCM - orr r0, r0, #HW_C9_TCMR_16KB - mcr p15, 0, r0, c9, c1, 0 - - // - // システム制御コプロセッサ マスター設定 - // - mrc p15, 0, r0, c1, c0, 0 - ldr r1,=0 \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_SB1_BITSET - orr r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - bx lr -} - /*---------------------------------------------------------------------------* Name: i_stupCpuCopy32 diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_pu.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_pu.c new file mode 100644 index 0000000..5bb9c78 --- /dev/null +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_pu.c @@ -0,0 +1,262 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - library - init + File: crt0_pu.c + + Copyright 2009 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: $ + $Rev$ + $Author$ + *---------------------------------------------------------------------------*/ +#include +#include + + +/*---------------------------------------------------------------------------* + Name: i_stupEnableTCM + + Description: enable ITCM and DTCM + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +asm void i_stupEnableTCM( void ) +{ + // プロテクションユニット/キャッシュ/TCM ディセーブル + + mrc p15, 0, r0, c1, c0, 0 + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ + | HW_C1_LD_INTERWORK_DISABLE \ + | HW_C1_PROTECT_UNIT_ENABLE + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + // キャッシュ無効化 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ + mcr p15, 0, r0, c7, c6, 0 // データキャッシュ + + // ライトバッファ エンプティ待ち + mcr p15, 0, r0, c7, c10, 4 + + // + // 命令ＴＣＭ 設定 + // + mov r0, #HW_C9_TCMR_32MB + mcr p15, 0, r0, c9, c1, 1 + + // + // データＴＣＭ 設定 + // + ldr r0, =STUPi_HW_DTCM + orr r0, r0, #HW_C9_TCMR_16KB + mcr p15, 0, r0, c9, c1, 0 + + // + // システム制御コプロセッサ マスター設定 + // + mrc p15, 0, r0, c1, c0, 0 + ldr r1,=0 \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_SB1_BITSET + orr r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + bx lr +} + +//----------------------------------------------------------------------- +// システム制御コプロセッサ 初期化 +//----------------------------------------------------------------------- +asm void i_stupInitCP15(void) +{ + // プロテクションユニット/キャッシュ/TCM ディセーブル + + mrc p15, 0, r0, c1, c0, 0 + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ + | HW_C1_LD_INTERWORK_DISABLE \ + | HW_C1_PROTECT_UNIT_ENABLE +#ifdef SDK_MG20EMU + bic r1, r1, #HW_C1_ITCM_ENABLE +#endif // SDK_MG20EMU + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + // キャッシュ無効化 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ + mcr p15, 0, r0, c7, c6, 0 // データキャッシュ + + // ライトバッファ エンプティ待ち + mcr p15, 0, r0, c7, c10, 4 + +/* +; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA +; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW +; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW +; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW +; Region 3: PRV_WRAM_SYSRV:Base = 0x08000000, Size = 4KB, I:Cach Buf / D:Cach Buf, I:RO / D:RW +; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW +; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW +; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO +; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW +*/ +#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE) +#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0 +#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7)) +#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28)) +#define NA 0 +#define RW 1 +#define RO 5 + + + // + // メモリリージョン初期化 + // + //---- メインメモリ + SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB ) + SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB ) + + //---- I/Oレジスタ & VRAM & AXI-WRAM + SET_PROTECTION_A( c1, HW_IOREG, 256MB ) + SET_PROTECTION_B( c1, HW_IOREG, 256MB ) + + //---- PRV_WRAM + SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB ) + SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB ) + + //---- PRV_WRAM_SYSRV +#ifndef SDK_MG20EMU + SET_PROTECTION_A( c3, HW_PRV_WRAM_SYSRV, 4KB ) + SET_PROTECTION_B( c3, HW_PRV_WRAM_SYSRV, 4KB ) +#else // SDK_MG20EMU + SET_PROTECTION_A( c3, HW_MG20IOP_REG, 1MB ) + SET_PROTECTION_B( c3, HW_MG20IOP_REG, 1MB ) +#endif // SDK_MG20EMU + + //---- データ TCM + ldr r0, =STUPi_HW_DTCM + orr r0, r0, #HW_C6_PR_16KB + orr r0, r0, #HW_C6_PR_ENABLE + SET_PROTECTION_B( c4, HW_DTCM, 16KB ) + + //---- 命令 TCM + // データ TCM より優先が高い + SET_PROTECTION_A( c5, HW_ITCM, 32KB ) + SET_PROTECTION_B( c5, HW_ITCM, 32KB ) + + //---- BIOS + SET_PROTECTION_A( c6, HW_BIOS, 64KB ) + SET_PROTECTION_B( c6, HW_BIOS, 64KB ) + + //---- SHARED CPU 間通信ワーク領域 + SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB ) + SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB ) + + // + // 命令ＴＣＭ 設定 + // + mov r0, #HW_C9_TCMR_128MB + mcr p15, 0, r0, c9, c1, 1 + + // + // データＴＣＭ 設定 + // + ldr r0, =STUPi_HW_DTCM + orr r0, r0, #HW_C9_TCMR_16KB + mcr p15, 0, r0, c9, c1, 0 + + // + // 命令キャッシュ イネーブル (リージョン設定) + // 6: BIOS + // + mov r0, #REGION_BIT(0,0,0,0,0,0,1,0) + mcr p15, 0, r0, c2, c0, 1 + + // + // データキャッシュ イネーブル (リージョン設定) + // 0: HW_MAIN_MEM + // 2: PRV_WRAM + // 6: BIOS + // + mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) + mcr p15, 0, r0, c2, c0, 0 + + // + // ライトバッファ イネーブル(リージョン設定) + // 0: HW_MAIN_MEM + // 2: PRV_WRAM + // 6: BIOS + // + mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) + mcr p15, 0, r0, c3, c0, 0 + + // + // 命令アクセス許可 (リージョン設定) + // MAIN_MEM : NA + // IO_AXIRAM : NA + // PRV_WRAM : NA + // PRV_WRAM_SYSRV: RO + // DTCM : NA + // ITCM : RO + // BIOS : RO + // SHARED : NA + // +#ifndef SDK_MG20EMU + ldr r0, =REGION_ACC(NA,NA,NA,RO,NA,RO,RO,NA) +#else // SDK_MG20EMU + ldr r0, =REGION_ACC(NA,NA,RO,NA,NA,RO,RO,NA) +#endif // SDK_MG20EMU + mcr p15, 0, r0, c5, c0, 3 + + // + // データアクセス許可（リージョン設定） + // MAIN_MEM : RW + // IO_AXIRAM : RW + // PRV_WRAM : RW + // PRV_WRAM_SYSRV: RW + // DTCM : RW + // ITCM : RW + // BIOS : RO + // SHARED : RW + // +#ifdef BROM_ENABLE_BOOTROM_WRITE + ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RW,RW) +#else // BROM_ENABLE_BOOTROM_WRITE + ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RO,RW) +#endif // BROM_ENABLE_BOOTROM_WRITE + mcr p15, 0, r0, c5, c0, 2 + + // + // システム制御コプロセッサ マスター設定 + // + mrc p15, 0, r0, c1, c0, 0 + ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \ + | HW_C1_PROTECT_UNIT_ENABLE + orr r0, r0, r1 +#ifdef SDK_MG20EMU + bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER +#endif // SDK_MG20EMU + mcr p15, 0, r0, c1, c0, 0 + + bx lr + + LTORG + + EXPORT i_stupInitCP15_End +i_stupInitCP15_End +} + diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c index 55dfa95..b900de7 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c @@ -104,191 +104,5 @@ terminate b terminate } -//----------------------------------------------------------------------- -// システム制御コプロセッサ 初期化 -//----------------------------------------------------------------------- -asm void i_stupInitCP15(void) -{ - // プロテクションユニット/キャッシュ/TCM ディセーブル - - mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ - | HW_C1_LD_INTERWORK_DISABLE \ - | HW_C1_PROTECT_UNIT_ENABLE -#ifdef SDK_MG20EMU - bic r1, r1, #HW_C1_ITCM_ENABLE -#endif // SDK_MG20EMU - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - // キャッシュ無効化 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ - mcr p15, 0, r0, c7, c6, 0 // データキャッシュ - - // ライトバッファ エンプティ待ち - mcr p15, 0, r0, c7, c10, 4 - -/* -; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA -; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW -; Region 3: PRV_WRAM_SYSRV:Base = 0x08000000, Size = 4KB, I:Cach Buf / D:Cach Buf, I:RO / D:RW -; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW -; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW -; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO -; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW -*/ -#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE) -#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0 -#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7)) -#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28)) -#define NA 0 -#define RW 1 -#define RO 5 - - - // - // メモリリージョン初期化 - // - //---- メインメモリ - SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB ) - SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB ) - - //---- I/Oレジスタ & VRAM & AXI-WRAM - SET_PROTECTION_A( c1, HW_IOREG, 256MB ) - SET_PROTECTION_B( c1, HW_IOREG, 256MB ) - - //---- PRV_WRAM - SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB ) - SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB ) - - //---- PRV_WRAM_SYSRV -#ifndef SDK_MG20EMU - SET_PROTECTION_A( c3, HW_PRV_WRAM_SYSRV, 4KB ) - SET_PROTECTION_B( c3, HW_PRV_WRAM_SYSRV, 4KB ) -#else // SDK_MG20EMU - SET_PROTECTION_A( c3, HW_MG20IOP_REG, 1MB ) - SET_PROTECTION_B( c3, HW_MG20IOP_REG, 1MB ) -#endif // SDK_MG20EMU - - //---- データ TCM - ldr r0, =STUPi_HW_DTCM - orr r0, r0, #HW_C6_PR_16KB - orr r0, r0, #HW_C6_PR_ENABLE - SET_PROTECTION_B( c4, HW_DTCM, 16KB ) - - //---- 命令 TCM - // データ TCM より優先が高い - SET_PROTECTION_A( c5, HW_ITCM, 32KB ) - SET_PROTECTION_B( c5, HW_ITCM, 32KB ) - - //---- BIOS - SET_PROTECTION_A( c6, HW_BIOS, 64KB ) - SET_PROTECTION_B( c6, HW_BIOS, 64KB ) - - //---- SHARED CPU 間通信ワーク領域 - SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB ) - SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB ) - - // - // 命令ＴＣＭ 設定 - // - mov r0, #HW_C9_TCMR_128MB - mcr p15, 0, r0, c9, c1, 1 - - // - // データＴＣＭ 設定 - // - ldr r0, =STUPi_HW_DTCM - orr r0, r0, #HW_C9_TCMR_16KB - mcr p15, 0, r0, c9, c1, 0 - - // - // 命令キャッシュ イネーブル (リージョン設定) - // 6: BIOS - // - mov r0, #REGION_BIT(0,0,0,0,0,0,1,0) - mcr p15, 0, r0, c2, c0, 1 - - // - // データキャッシュ イネーブル (リージョン設定) - // 0: HW_MAIN_MEM - // 2: PRV_WRAM - // 6: BIOS - // - mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) - mcr p15, 0, r0, c2, c0, 0 - - // - // ライトバッファ イネーブル(リージョン設定) - // 0: HW_MAIN_MEM - // 2: PRV_WRAM - // 6: BIOS - // - mov r0, #REGION_BIT(1,0,1,0,0,0,1,0) - mcr p15, 0, r0, c3, c0, 0 - - // - // 命令アクセス許可 (リージョン設定) - // MAIN_MEM : NA - // IO_AXIRAM : NA - // PRV_WRAM : NA - // PRV_WRAM_SYSRV: RO - // DTCM : NA - // ITCM : RO - // BIOS : RO - // SHARED : NA - // -#ifndef SDK_MG20EMU - ldr r0, =REGION_ACC(NA,NA,NA,RO,NA,RO,RO,NA) -#else // SDK_MG20EMU - ldr r0, =REGION_ACC(NA,NA,RO,NA,NA,RO,RO,NA) -#endif // SDK_MG20EMU - mcr p15, 0, r0, c5, c0, 3 - - // - // データアクセス許可（リージョン設定） - // MAIN_MEM : RW - // IO_AXIRAM : RW - // PRV_WRAM : RW - // PRV_WRAM_SYSRV: RW - // DTCM : RW - // ITCM : RW - // BIOS : RO - // SHARED : RW - // -#ifdef BROM_ENABLE_BOOTROM_WRITE - ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RW,RW) -#else // BROM_ENABLE_BOOTROM_WRITE - ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RO,RW) -#endif // BROM_ENABLE_BOOTROM_WRITE - mcr p15, 0, r0, c5, c0, 2 - - // - // システム制御コプロセッサ マスター設定 - // - mrc p15, 0, r0, c1, c0, 0 - ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \ - | HW_C1_PROTECT_UNIT_ENABLE - orr r0, r0, r1 -#ifdef SDK_MG20EMU - bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER -#endif // SDK_MG20EMU - mcr p15, 0, r0, c1, c0, 0 - - bx lr - - LTORG - - EXPORT i_stupInitCP15_End -i_stupInitCP15_End -} - +#include <./crt0_pu.c> #include <./crt0_misc_sp.c> -