diff --git a/trunk/bootrom/build/bootrom/Makefile b/trunk/bootrom/build/bootrom/Makefile index 7288662..ad80999 100644 --- a/trunk/bootrom/build/bootrom/Makefile +++ b/trunk/bootrom/build/bootrom/Makefile @@ -22,8 +22,9 @@ include $(CTRBROM_ROOT)/build/buildtools/commondefs SUBDIRS = \ ts-dev \ - jtag-only \ - ctr_bootrom \ + +# jtag-only \ +# ctr_bootrom \ #---------------------------------------------------------------------------- diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0.c b/trunk/bootrom/build/libraries/init/ARM11/crt0.c index 873e0d2..8b886b0 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0.c @@ -50,15 +50,26 @@ reserve b reserve irq b STUPi_IrqVeneer fiq b STUPi_FiqVeneer +#ifdef SDK_MG20EMU + // MG20_CONFIG + DCD 0x3105 +#endif // SDK_MG20EMU + INASM_EXTERN( STUPi_SwiHandler ) DCD STUPi_SwiHandler +#ifdef SDK_MG20EMU + SPACE 0x20 - 8 +#endif // SDK_MG20EMU + stupStartHandlerVeneer +#ifndef SDK_MG20EMU // NULLジャンプ時のデータアボート有効時はここで発生 mov r12, #0 ldr r12, [r12] +#endif // SDK_MG20EMU //---- check CPU ID mrc p15,0, r0, c0, c0, 5 diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c index d1a7aac..6e29766 100644 --- a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c +++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c @@ -40,15 +40,6 @@ asm void STUPi_StartHandler( void ) INASM_EXTERN( BromMain ) INASM_EXTERN( main ) - //---- disable cp15 - bl stupDisableCP15 - - //---- initialize MMU - bl stupInitMMU - - //---- enable cp15 - bl stupEnableCP15 - //---- initialize stack pointer // SVC mode mov r0, #HW_PSR_SVC_MODE @@ -67,6 +58,15 @@ asm void STUPi_StartHandler( void ) ldr r0, =HW_BROM_SYS_STACK_END mov sp, r0 + //---- disable cp15 + bl stupDisableCP15 + + //---- initialize MMU + bl stupInitMMU + + //---- enable cp15 + bl stupEnableCP15 + //---- clear wram // 1KB mov r0, #0 @@ -130,12 +130,12 @@ ASM void stupDisableCP15( void ) | HW_C1_RETURN_STACK_ENABLE bic r0, r0, r1 mcr p15, 0, r0, c1, c0, 1 -#if 0 + // Invalidate Caches mov r0, #0 mcr p15, 0, r0, c7, c5, 0 // Inst Cache mcr p15, 0, r0, c7, c6, 0 // Data cache -#endif + // Wait for write buffer empty mcr p15, 0, r0, c7, c10, 4 @@ -173,7 +173,9 @@ ASM void stupEnableCP15( void ) // mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_0_SB1 \ +// | HW_C1_0_SB1 \ + + ldr r1, = 0 \ | HW_C1_EXCEPT_LITTLE_ENDIAN \ | HW_C1_UNALIGN_ACCESS_ENABLE \ | HW_C1_BR_PREDICT_ENABLE \ @@ -230,12 +232,14 @@ ASM void stupInitMMU( void ) ldr r1, =HW_C2_0_T1_BASE_MASK_MIN mov r1, r1, ASR r2 and r1 ,r1, r0 - orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT + orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ + | HW_C2_WALK_ON_SHARED_MEM mcr p15, 0, r1, c2, c0, 0 ldr r1, =HW_C2_1_T1_BASE_MASK and r1 ,r1, r0 - orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT + orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \ + | HW_C2_WALK_ON_SHARED_MEM mcr p15, 0, r1, c2, c0, 1 // MMU L1 Table Boundary @@ -295,8 +299,6 @@ ASM void stupInitMMU( void ) void stupInitMMUTable( void ) { - - u32* t1Base = (u32* )HW_BROM_MMU_T1; u32* t2Base = (u32* )HW_BROM_MMU_T2; @@ -304,7 +306,7 @@ void stupInitMMUTable( void ) u32 paddr = (u32 )NULL; // Initialize as Access Prohibition - table = &t1Base[0]; + table = t1Base; for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) { *table++ = HW_MMU6_T1_SEC_PACK( @@ -315,11 +317,11 @@ void stupInitMMUTable( void ) HW_MMU6_T1_SHARED, HW_MMU6_T1_XN, 0); - paddr += HW_MMU6_T1_SEC_SIZE; +// paddr += HW_MMU6_T1_SEC_SIZE; } - table = &t2Base[0]; - for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; ) + table = t2Base; + for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; ) { *table++ = HW_MMU6_T2_SP_PACK( paddr, @@ -331,116 +333,10 @@ void stupInitMMUTable( void ) } - // BROM Region (64KBx2 cached) - table = &t1Base[HW_BROM_IMG/HW_MMU6_T1_SEC_SIZE]; - paddr = HW_BROM_IMG; - *table = HW_MMU6_T1_COURSE_PACK( paddr, 0 ); - // T2 for Page - table = &t2Base[0]; - for ( paddr = HW_BROM_IMG; paddr != HW_BROM_END; ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); - - // IO Registers Region (16MB) - table = &t1Base[HW_IOREG/HW_MMU6_T1_SEC_SIZE]; - for ( paddr = HW_IOREG; paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE; ) - { - - *table++ = HW_MMU6_T1_SUSEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_SHARED_DEV, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN - ); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // MPCore Registers Region (1MB) - table = &t1Base[HW_MPCORE_REG/HW_MMU6_T1_SEC_SIZE]; - paddr = HW_MPCORE_REG; - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_NSHARED_DEV, - HW_MMU6_T1_GLOBAL, - FALSE, - HW_MMU6_T1_XN, - 0); - - // VRAM Region (4MB cached) - table = &t1Base[HW_VRAM/HW_MMU6_T1_SEC_SIZE]; - for ( paddr = HW_VRAM; paddr < HW_VRAM_END; ) - { - *table++ = HW_MMU6_T1_SEC_PACK( - paddr, - HW_MMU6_T1_APX_S_RW_U_NA, - HW_MMU6_T1_RGT_L1C_WB_WA, - HW_MMU6_T1_GLOBAL, - HW_MMU6_T1_SHARED, - HW_MMU6_T1_XN, - 0); - paddr += HW_MMU6_T1_SEC_SIZE; - } - - // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) - table = &t1Base[HW_DSP_WRAM/HW_MMU6_T1_SEC_SIZE]; - paddr = HW_DSP_WRAM; - *table = HW_MMU6_T1_COURSE_PACK( paddr, 0 ); - // T2 for Page - table = &t2Base[0]; - for ( paddr = HW_DSP_WRAM; paddr < HW_BROM_MMU_TBL; ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_L1C_WB_WA, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_LP_XN); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // HW_BROM_MMU_TBL - while ( paddr < HW_BROM_MMU_TBL_END ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - HW_MMU6_T2_LP_XN); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // HW_AXI_WRAM_SHARED - while ( paddr < HW_AXI_WRAM_SHARED_END ) - { - *table++ = HW_MMU6_T2_LP_PACK( - paddr, - HW_MMU6_T2_APX_S_RW_U_NA, - HW_MMU6_T2_LP_RGT_SHARED_DEV, - HW_MMU6_T2_GLOBAL, - HW_MMU6_T2_SHARED, - FALSE); - paddr += HW_MMU6_T2_LP_ALIAS_SIZE; - } - // Coarse page is 1KB boundary - t2Base += MATH_ROUNDUP(HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); - // Main Memory Region (128MB cached) - table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE]; - for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_END; ) + paddr = HW_MAIN_MEM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_MAIN_MEM_END ) { *table++ = HW_MMU6_T1_SUSEC_PACK( @@ -453,6 +349,7 @@ void stupInitMMUTable( void ) ); paddr += HW_MMU6_T1_SEC_SIZE; } +#ifndef SDK_MG20EMU while ( paddr < HW_MAIN_MEM_EX_END ) { @@ -466,6 +363,155 @@ void stupInitMMUTable( void ) ); paddr += HW_MMU6_T1_SEC_SIZE; } +#else // SDK_MG20EMU + // for AXI-WRAM & DSP-WRAM Emulation + paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_MAIN_MEM_END ) + { + + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } +#endif // SDK_MG20EMU + + // IO Registers Region (16MB) + paddr = HW_IOREG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE ) + { + *table++ = HW_MMU6_T1_SUSEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_SHARED_DEV, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN + ); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // MPCore Registers Region (1MB) + paddr = HW_MPCORE_REG; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); + + // VRAM Region (4MB cached) + paddr = HW_VRAM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + while ( paddr < HW_VRAM_END ) + { + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_L1C_WB_WA, + HW_MMU6_T1_GLOBAL, + HW_MMU6_T1_SHARED, + HW_MMU6_T1_XN, + 0); + paddr += HW_MMU6_T1_SEC_SIZE; + } + + // AXI-WRAM & DSP-WRAM Region (1MB cached & uncached) + paddr = HW_DSP_WRAM; + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); + // T2 for Page + table = t2Base; + while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_LP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_LP_XN); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + while ( paddr < HW_BROM_MMU_TBL ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_SP_XN); + paddr += HW_MMU6_T2_SP_SIZE; + } + // HW_BROM_MMU_TBL + while ( paddr < HW_BROM_MMU_TBL_END ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_SHARED_DEV, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + HW_MMU6_T2_SP_XN); + paddr += HW_MMU6_T2_SP_SIZE; + } + // HW_AXI_WRAM_SHARED + while ( paddr < HW_AXI_WRAM_SHARED_END ) + { + *table++ = HW_MMU6_T2_SP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_SP_RGT_SHARED_DEV, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + FALSE); // for exception veneer + paddr += HW_MMU6_T2_SP_SIZE; + } + // Coarse page is 1KB boundary + t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); + + // BROM Region (64KBx2 cached) + paddr = HW_BROM_IMG; +#if 1 + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table++ = HW_MMU6_T1_SEC_PACK( + paddr, + HW_MMU6_T1_APX_S_RW_U_NA, + HW_MMU6_T1_RGT_NSHARED_DEV, + HW_MMU6_T1_GLOBAL, + FALSE, + HW_MMU6_T1_XN, + 0); +#else + table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE]; + *table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 ); + // T2 for Page + table = t2Base; + while ( paddr != HW_BROM_END ) + { + *table++ = HW_MMU6_T2_LP_PACK( + paddr, + HW_MMU6_T2_APX_S_RW_U_NA, + HW_MMU6_T2_LP_RGT_L1C_WB_WA, + HW_MMU6_T2_GLOBAL, + HW_MMU6_T2_SHARED, + FALSE); + paddr += HW_MMU6_T2_LP_ALIAS_SIZE; + } + // Coarse page is 1KB boundary + t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]); +#endif } diff --git a/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h index 759227b..7d2100c 100644 --- a/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h +++ b/trunk/bootrom/include/brom/hw/ARM11/mmap_axi_wram.h @@ -25,7 +25,7 @@ extern "C" { //------------------------------------- HW_BROM_STACK #define HW_BROM_STACK (HW_BROM_STACK_END - HW_BROM_STACK_SIZE) -#define HW_BROM_STACK_END HW_FIRM_FROM_BROM_BUF +#define HW_BROM_STACK_END HW_BROM_MMU_TBL #define HW_BROM_STACK_SIZE 0x4000 // 16KB #define HW_BROM_SVC_STACK (HW_BROM_SVC_STACK_END - HW_BROM_SVC_STACK_SIZE) @@ -42,7 +42,7 @@ extern "C" { //------------------------------------- HW_BROM_MMU_TBL #define HW_BROM_MMU_TBL (HW_BROM_MMU_TBL_END - HW_BROM_MMU_TBL_SIZE) -#define HW_BROM_MMU_TBL_END HW_AXI_WRAM_SHARED +#define HW_BROM_MMU_TBL_END HW_FIRM_FROM_BROM_BUF // (16+8)KB #define HW_BROM_MMU_TBL_SIZE (HW_BROM_MMU_T1_SIZE + HW_BROM_MMU_T2_SIZE) // 24KB #define HW_BROM_MMU_T1 HW_BROM_MMU_TBL @@ -54,13 +54,13 @@ extern "C" { //------------------------------------- BROM_SYSRV -#define HW_BROM_SYSRV HW_AXI_WRAM_SHARED_USR +#define HW_BROM_SYSRV HW_AXI_WRAM_SHARED_SYS #define HW_BROM_SYSRV_END (HW_BROM_SYSRV + HW_BROM_SYSRV_SIZE) -#define HW_BROM_SYSRV_SIZE HW_AXI_WRAM_SHARED_USR_SIZE +#define HW_BROM_SYSRV_SIZE HW_AXI_WRAM_SHARED_SYS_SIZE -#define HW_BROM_SYSRV_IOFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) -#define HW_BROM_SYSRV_IOFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) -#define HW_BROM_SYSRV_IOFS_INTR_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) +#define HW_BROM_SYSRV_OFS_EXCP_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) +#define HW_BROM_SYSRV_OFS_INTR_CHECK (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) +#define HW_BROM_SYSRV_OFS_INTR_VECTOR (HW_PRV_WRAM_SYSRV_SIZE - HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) //------------------------------------- HW_BROM_TO_FIRM_BUF #define HW_BROM_TO_FIRM_BUF HW_FIRM_FROM_BROM_BUF // defined in mmap_firm.h diff --git a/trunk/bootrom/include/brom/math/math.h b/trunk/bootrom/include/brom/math/math.h index 94a7484..46f3c41 100644 --- a/trunk/bootrom/include/brom/math/math.h +++ b/trunk/bootrom/include/brom/math/math.h @@ -11,8 +11,8 @@ in whole or in part, without the prior written consent of Nintendo. $Date:: $ - $Rev:$ - $Author:$ + $Rev$ + $Author$ *---------------------------------------------------------------------------*/ #ifndef BROM_MATH_MATH_H_ #define BROM_MATH_MATH_H_ diff --git a/trunk/bootrom/include/brom/specfiles/ARM11.ldscript.template b/trunk/bootrom/include/brom/specfiles/ARM11.ldscript.template index ce0aa47..b2f87fb 100644 --- a/trunk/bootrom/include/brom/specfiles/ARM11.ldscript.template +++ b/trunk/bootrom/include/brom/specfiles/ARM11.ldscript.template @@ -22,15 +22,19 @@ #include -LOAD_NORMAL HW_BROM_NML HW_BROM_NML_SIZE +LOAD_NORMAL HW_BROM_NML HW_BROM_NML_ABT_SIZE { STUP_ENTRY +0 { *crt0.*o (.emb_text, +FIRST) } - NML_RO HW_BROM_NML_ABT_END +} + +LOAD_UNABORT HW_BROM_NML_ABT_END (HW_BROM_NML_SIZE - HW_BROM_NML_ABT_SIZE) +{ + NML_RO +0 { - *crt0_excp.o (.emb_text) + *crt0_excp.o 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+ +2006/12/1 +IOP: LCD-DACパラメータ最適化 + +2006/11/30 +IOP: LCD-DAC初期化&バックライトON + サウンドイネーブル + バス調停方式をラウンドロビンへ初期化 + +2006/11/29 +MG20-NV: DDR設定の最適化 + +2006/11/23 +MG20-NV: NVIDIA製PROMでDDRが使用可能になるもの + +2006/11/17 +IOP: MG20 からの初期化完了コマンド受信を待っていた箇所を一時的に削除 + +2006/11/16 +MG20: JTAG は NV-ROM でイネーブルにしているので無限ループのみ + +2006/11/14 +IOP: LinkIF & PMIC初期化 + JTAGイネーブル直前にキャッシュ&プロテクションユニットディセーブル + +2006/11/13 +IOP: JTAGイネーブルのみ + diff --git a/trunk/build/buildtools/commondefs b/trunk/build/buildtools/commondefs index 117d019..030d3e1 100644 --- a/trunk/build/buildtools/commondefs +++ b/trunk/build/buildtools/commondefs @@ -40,7 +40,7 @@ CTRSDK_VERSION_MAJOR ?= 4 # CTR_PROC = [ARM11/ARM9/ARM7] # -CTR_PLATFORM ?= TS +CTR_PLATFORM ?= TEG CTR_MEMSIZE ?= 64M CTR_CODEGEN ?= ARM CTR_PROC ?= ARM11 diff --git a/trunk/include/ctr/hw/ARM11/mmap_global.h b/trunk/include/ctr/hw/ARM11/mmap_global.h index aeb74fb..8d9ac42 100644 --- a/trunk/include/ctr/hw/ARM11/mmap_global.h +++ b/trunk/include/ctr/hw/ARM11/mmap_global.h @@ -51,14 +51,14 @@ extern "C" { #else // SDK_MG20EMU //----------------------------- AXI-WRAM -#define HW_AXI_WRAM 0x00100000 -#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE) -#define HW_AXI_WRAM_SIZE 0x1000 // 4KB +#define HW_AXI_WRAM (HW_AXI_WRAM_END - HW_AXI_WRAM_SIZE) +#define HW_AXI_WRAM_END HW_MAIN_MEM_END +#define HW_AXI_WRAM_SIZE 0x80000 // 512KB //----------------------------- DSP-WRAM -#define HW_DSP_WRAM HW_AXI_WRAM -#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE) -#define HW_DSP_WRAM_SIZE 0 // 0B +#define HW_DSP_WRAM (HW_DSP_WRAM_END - HW_DSP_WRAM_SIZE) +#define HW_DSP_WRAM_END HW_AXI_WRAM +#define HW_DSP_WRAM_SIZE 0x80000 // 512KB //----------------------------- VRAM #define HW_VRAM 0x1e000000 @@ -97,7 +97,7 @@ extern "C" { #define HW_BIOS_IMG 0x00000000 #define HW_BIOS 0x00010000 #else // SDK_MG20EMU -#define HW_BIOS_IMG 0xffff0000 +#define HW_BIOS_IMG 0xfffe0000 #define HW_BIOS 0xffff0000 #endif // SDK_MG20EMU #define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE) diff --git a/trunk/include/firm/hw/ARM11/mmap_firm.h b/trunk/include/firm/hw/ARM11/mmap_firm.h index 26cc0a6..2c7fa09 100644 --- a/trunk/include/firm/hw/ARM11/mmap_firm.h +++ b/trunk/include/firm/hw/ARM11/mmap_firm.h @@ -27,8 +27,8 @@ extern "C" { #define HW_FIRM_SIZE 0x80000 // 512KB //------------------------------------- HW_FIRM_FROM_BROM_BUF -#define HW_FIRM_FROM_BROM_BUF (HW_FIRM_FROM_BROM_BUF_END - HW_FIRM_FROM_BROM_BUF_SIZE) -#define HW_FIRM_FROM_BROM_BUF_END (HW_AXI_WRAM_SHARED_END - 0x8000) // END - 32KB +#define HW_FIRM_FROM_BROM_BUF (HW_FIRM_FROM_BROM_BUF_END - HW_FIRM_FROM_BROM_BUF_SIZE) // 24KB +#define HW_FIRM_FROM_BROM_BUF_END HW_AXI_WRAM_SHARED // 8KB #define HW_FIRM_FROM_BROM_BUF_SIZE 0x4000 // 16KB #ifdef __cplusplus