システム領域をアドレス変換でリマップしてデュアルコア動作可能に。

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@261 b871894f-2f95-9b40-918c-086798483c85

trunk/bootrom/build/bootrom/teg-dev/ARM11/crt0_secure.c

@@ -79,6 +79,12 @@ image_to_physical
         rsb             r2, r1, #HW_AXI_WRAM_END
         bl              i_stupCpuClear32
 
+        //---- copy system area
+        ldr             r0, =HW_AXI_WRAM_SHARED_SYS_A11
+        ldr             r1, =HW_AXI_WRAM_SHARED_SYS_A11 - HW_AXI_WRAM_SHARED_SYS_SIZE
+        mov             r2, #HW_AXI_WRAM_SHARED_SYS_A11_SIZE
+        bl              i_stupCpuCopy32
+
         // os finalize
         bl              i_osFinalize
 

trunk/bootrom/build/libraries/init/ARM11/crt0_mmu.c

@@ -437,6 +437,21 @@ void stupInitMMUTable( u32* t1Base, u32* t1End, u32* t2Base, u32* t2End )
                   FALSE);  // for exception veneer
         paddr += HW_MMU6_T2_SP_SIZE;
     }
+    // HW_AXI_WRAM_SHARED_GBL to HW_AXI_WRAM_SHARED_SYS for core 1
+#ifndef BROM_TARGET_BROM
+    if ( i_osGetCpuID() == 1 )
+    {
+        paddr = HW_AXI_WRAM_SHARED_GBL;
+        *--table = HW_MMU6_T2_SP_PACK(
+                  paddr,
+                  HW_MMU6_T2_APX_S_RW_U_NA,
+                  HW_MMU6_T2_SP_RGT_SHARED_DEV,
+                  HW_MMU6_T2_GLOBAL,
+                  HW_MMU6_T2_SHARED,
+                  FALSE);  // for exception veneer
+        *table++;
+    }
+#endif // BROM_TARGET_BROM
     // Coarse page is 1KB boundary
     t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
 

trunk/bootrom/build/libraries/os/common/os_system.c

@@ -19,7 +19,6 @@
 #define osTPrintf(...) ((void)0)
 
 #ifdef SDK_ARM11
-#ifdef BROM_ENABLE_SMP_CODE
 
 //============================================================================
 //          MULTI CORE
@@ -34,7 +33,7 @@
   Returns:      CPU-ID (field 0-3)
  *---------------------------------------------------------------------------*/
 #include <brom/code32.h>
-asm u8 osGetCpuID( void )
+asm u8 i_osGetCpuID( void )
 {
     mrc     p15,0, r0, c0, c0, 5
     and     r0, r0, #HW_C0_AP_CPU_ID_MASK
@@ -43,7 +42,6 @@ asm u8 osGetCpuID( void )
 }
 #include <brom/codereset.h>
 
-#endif // BROM_ENABLE_SMP_CODE
 #endif // SDK_ARM11
 
 //============================================================================

trunk/bootrom/include/brom/os/common/system.h

@@ -144,14 +144,16 @@ static inline u32 i_osCpuCycleToNSec( OSCpuCycle cyc )
 
   Returns:      CPU-ID (field 0-3)
  *---------------------------------------------------------------------------*/
-#ifdef BROM_ENABLE_SMP_CODE
+u8 i_osGetCpuID( void );
-u8 osGetCpuID( void );
+
-#else // BROM_ENABLE_SMP_CODE
 static inline u8 osGetCpuID( void )
 {
+#ifdef BROM_ENABLE_SMP_CODE
+    return i_osGetCpuID( void );
+#else // BROM_ENABLE_SMP_CODE
     return 0;
-}
 #endif // BROM_ENABLE_SMP_CODE
+}
 
 //============================================================================
 //          PROCESSER MODE

trunk/public/include/ctr/hw/ARM11/mmap_axi_wram.h

@@ -38,8 +38,8 @@ extern "C" {
 #define HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER   0x20
 #define HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER   0x28
 #endif // SDK_ARM11
-#define HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF     0x30  // for firmware
+#define HW_AXI_WRAM_SYSRV_OFS_INIT_LOCK_BUF ((u32)(0x38 - HW_AXI_WRAM_SHARED_SYS_SIZE))  // for firmware
-#define HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF     0x34  // for firmware
+#define HW_AXI_WRAM_SYSRV_OFS_CARD_LOCK_BUF ((u32)(0x3a - HW_AXI_WRAM_SHARED_SYS_SIZE))  // for firmware
 #ifdef SDK_ARM11
 #define HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1 0x3c
 #define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1   0x40
@@ -64,8 +64,8 @@ extern "C" {
 #define HW_DABT_VENEER_BUF                  (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER)
 #define HW_DABT_VECTOR_BUF                  (HW_DABT_VENEER_BUF + 4)
 #endif // SDK_ARM11
-#define HW_INIT_LOCK_BUF                    (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF)
+#define HW_INIT_LOCK_BUF                    (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INIT_LOCK_BUF)
-#define HW_CARD_LOCK_BUF                    (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF)
+#define HW_CARD_LOCK_BUF                    (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_CARD_LOCK_BUF)
 #ifdef SDK_ARM11
 #define HW_START_VECTOR1_BUF                (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
 #define HW_INTR_CHECK1_BUF                  (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)

trunk/public/include/ctr/hw/common/mmap_shared.h

@@ -27,9 +27,10 @@ extern "C" {
 
 #define HW_AXI_WRAM_SHARED              (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE)
 #define HW_AXI_WRAM_SHARED_END          (HW_AXI_WRAM_END)
-#define HW_AXI_WRAM_SHARED_SIZE         (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_USR_SIZE) // 8KB
+#define HW_AXI_WRAM_SHARED_SIZE         (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_GBL_SIZE) // 8KB
 
-#define HW_AXI_WRAM_SHARED_SYS          (HW_AXI_WRAM_SHARED_SYS_END - HW_AXI_WRAM_SHARED_SIZE)
+// コア毎に独立したシステム領域（コア１は HW_AXI_WRAM_SHARED_GBL からリマップ）
+#define HW_AXI_WRAM_SHARED_SYS          (HW_AXI_WRAM_SHARED_SYS_END - HW_AXI_WRAM_SHARED_SYS_SIZE)
 #define HW_AXI_WRAM_SHARED_SYS_END      HW_AXI_WRAM_SHARED_END
 #define HW_AXI_WRAM_SHARED_SYS_SIZE     0x1000 // 4KB
 
@@ -37,9 +38,10 @@ extern "C" {
 #define HW_AXI_WRAM_SHARED_SYS_A11_END  HW_AXI_WRAM_SHARED_SYS_END
 #define HW_AXI_WRAM_SHARED_SYS_A11_SIZE 0x60 // 96B
 
-#define HW_AXI_WRAM_SHARED_USR          (HW_AXI_WRAM_SHARED_USR_END - HW_AXI_WRAM_SHARED_USR_SIZE)
+// 両コアで共通したシステム領域
-#define HW_AXI_WRAM_SHARED_USR_END      HW_AXI_WRAM_SHARED_SYS
+#define HW_AXI_WRAM_SHARED_GBL          (HW_AXI_WRAM_SHARED_GBL_END - HW_AXI_WRAM_SHARED_GBL_SIZE)
-#define HW_AXI_WRAM_SHARED_USR_SIZE     0x1000 // 4KB
+#define HW_AXI_WRAM_SHARED_GBL_END      HW_AXI_WRAM_SHARED_SYS
+#define HW_AXI_WRAM_SHARED_GBL_SIZE     0x1000 // 4KB
 
 
 #ifdef __cplusplus