mirror of
https://github.com/rvtr/ctr_firmware.git
synced 2025-06-18 16:55:31 -04:00
システム領域をアドレス変換でリマップしてデュアルコア動作可能に。
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@261 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima
parent
197e91a909
commit
0f38a1f949
@ -79,6 +79,12 @@ image_to_physical
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rsb r2, r1, #HW_AXI_WRAM_END
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bl i_stupCpuClear32
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//---- copy system area
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ldr r0, =HW_AXI_WRAM_SHARED_SYS_A11
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ldr r1, =HW_AXI_WRAM_SHARED_SYS_A11 - HW_AXI_WRAM_SHARED_SYS_SIZE
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mov r2, #HW_AXI_WRAM_SHARED_SYS_A11_SIZE
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bl i_stupCpuCopy32
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// os finalize
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bl i_osFinalize
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@ -437,6 +437,21 @@ void stupInitMMUTable( u32* t1Base, u32* t1End, u32* t2Base, u32* t2End )
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FALSE); // for exception veneer
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paddr += HW_MMU6_T2_SP_SIZE;
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}
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// HW_AXI_WRAM_SHARED_GBL to HW_AXI_WRAM_SHARED_SYS for core 1
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#ifndef BROM_TARGET_BROM
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if ( i_osGetCpuID() == 1 )
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{
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paddr = HW_AXI_WRAM_SHARED_GBL;
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*--table = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_SP_RGT_SHARED_DEV,
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HW_MMU6_T2_GLOBAL,
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HW_MMU6_T2_SHARED,
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FALSE); // for exception veneer
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*table++;
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}
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#endif // BROM_TARGET_BROM
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// Coarse page is 1KB boundary
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t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
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@ -19,7 +19,6 @@
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#define osTPrintf(...) ((void)0)
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#ifdef SDK_ARM11
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#ifdef BROM_ENABLE_SMP_CODE
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//============================================================================
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// MULTI CORE
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@ -34,7 +33,7 @@
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Returns: CPU-ID (field 0-3)
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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asm u8 osGetCpuID( void )
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asm u8 i_osGetCpuID( void )
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{
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mrc p15,0, r0, c0, c0, 5
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and r0, r0, #HW_C0_AP_CPU_ID_MASK
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@ -43,7 +42,6 @@ asm u8 osGetCpuID( void )
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}
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#include <brom/codereset.h>
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#endif // BROM_ENABLE_SMP_CODE
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#endif // SDK_ARM11
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//============================================================================
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@ -144,14 +144,16 @@ static inline u32 i_osCpuCycleToNSec( OSCpuCycle cyc )
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Returns: CPU-ID (field 0-3)
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*---------------------------------------------------------------------------*/
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#ifdef BROM_ENABLE_SMP_CODE
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u8 osGetCpuID( void );
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#else // BROM_ENABLE_SMP_CODE
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u8 i_osGetCpuID( void );
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static inline u8 osGetCpuID( void )
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{
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#ifdef BROM_ENABLE_SMP_CODE
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return i_osGetCpuID( void );
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#else // BROM_ENABLE_SMP_CODE
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return 0;
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}
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#endif // BROM_ENABLE_SMP_CODE
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}
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//============================================================================
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// PROCESSER MODE
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@ -38,8 +38,8 @@ extern "C" {
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#define HW_AXI_WRAM_SYSRV_OFS_IABT_VENEER 0x20
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#define HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER 0x28
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#endif // SDK_ARM11
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#define HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF 0x30 // for firmware
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#define HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF 0x34 // for firmware
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#define HW_AXI_WRAM_SYSRV_OFS_INIT_LOCK_BUF ((u32)(0x38 - HW_AXI_WRAM_SHARED_SYS_SIZE)) // for firmware
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#define HW_AXI_WRAM_SYSRV_OFS_CARD_LOCK_BUF ((u32)(0x3a - HW_AXI_WRAM_SHARED_SYS_SIZE)) // for firmware
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#ifdef SDK_ARM11
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#define HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1 0x3c
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#define HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1 0x40
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@ -64,8 +64,8 @@ extern "C" {
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#define HW_DABT_VENEER_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_DABT_VENEER)
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#define HW_DABT_VECTOR_BUF (HW_DABT_VENEER_BUF + 4)
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#endif // SDK_ARM11
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#define HW_INIT_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_INIT_LOCK_BUF)
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#define HW_CARD_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF)
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#define HW_INIT_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INIT_LOCK_BUF)
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#define HW_CARD_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_CARD_LOCK_BUF)
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#ifdef SDK_ARM11
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#define HW_START_VECTOR1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
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#define HW_INTR_CHECK1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)
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@ -27,9 +27,10 @@ extern "C" {
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#define HW_AXI_WRAM_SHARED (HW_AXI_WRAM_SHARED_END - HW_AXI_WRAM_SHARED_SIZE)
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#define HW_AXI_WRAM_SHARED_END (HW_AXI_WRAM_END)
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#define HW_AXI_WRAM_SHARED_SIZE (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_USR_SIZE) // 8KB
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#define HW_AXI_WRAM_SHARED_SIZE (HW_AXI_WRAM_SHARED_SYS_SIZE + HW_AXI_WRAM_SHARED_GBL_SIZE) // 8KB
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#define HW_AXI_WRAM_SHARED_SYS (HW_AXI_WRAM_SHARED_SYS_END - HW_AXI_WRAM_SHARED_SIZE)
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// コア毎に独立したシステム領域（コア１は HW_AXI_WRAM_SHARED_GBL からリマップ）
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#define HW_AXI_WRAM_SHARED_SYS (HW_AXI_WRAM_SHARED_SYS_END - HW_AXI_WRAM_SHARED_SYS_SIZE)
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#define HW_AXI_WRAM_SHARED_SYS_END HW_AXI_WRAM_SHARED_END
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#define HW_AXI_WRAM_SHARED_SYS_SIZE 0x1000 // 4KB
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@ -37,9 +38,10 @@ extern "C" {
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#define HW_AXI_WRAM_SHARED_SYS_A11_END HW_AXI_WRAM_SHARED_SYS_END
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#define HW_AXI_WRAM_SHARED_SYS_A11_SIZE 0x60 // 96B
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#define HW_AXI_WRAM_SHARED_USR (HW_AXI_WRAM_SHARED_USR_END - HW_AXI_WRAM_SHARED_USR_SIZE)
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#define HW_AXI_WRAM_SHARED_USR_END HW_AXI_WRAM_SHARED_SYS
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#define HW_AXI_WRAM_SHARED_USR_SIZE 0x1000 // 4KB
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// 両コアで共通したシステム領域
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#define HW_AXI_WRAM_SHARED_GBL (HW_AXI_WRAM_SHARED_GBL_END - HW_AXI_WRAM_SHARED_GBL_SIZE)
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#define HW_AXI_WRAM_SHARED_GBL_END HW_AXI_WRAM_SHARED_SYS
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#define HW_AXI_WRAM_SHARED_GBL_SIZE 0x1000 // 4KB
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#ifdef __cplusplus
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